From 3fb7603cb503251a5e6c7aefdaff28b1b2054624 Mon Sep 17 00:00:00 2001 From: Flex Software Development Robot Date: Thu, 29 Aug 2024 15:58:52 +0000 Subject: [PATCH] Release v5.5.0 --- CONTRIBUTING.md | 65 + README.md | 9 +- SUPPORTED_SOFTWARE.md | 25 +- ra/board/ra2l1_voice/board.h | 47 + ra/board/ra2l1_voice/board_init.c | 48 + ra/board/ra2l1_voice/board_init.h | 44 + ra/board/ra2l1_voice/board_leds.c | 57 + ra/board/ra2l1_voice/board_leds.h | 61 + ra/board/ra4e1_voice/board.h | 47 + ra/board/ra4e1_voice/board_init.c | 48 + ra/board/ra4e1_voice/board_init.h | 44 + ra/board/ra4e1_voice/board_leds.c | 57 + ra/board/ra4e1_voice/board_leds.h | 60 + ra/board/ra6e1_voice/board.h | 47 + ra/board/ra6e1_voice/board_init.c | 48 + ra/board/ra6e1_voice/board_init.h | 44 + ra/board/ra6e1_voice/board_leds.c | 57 + ra/board/ra6e1_voice/board_leds.h | 60 + ra/board/ra8m1_vk/board.h | 47 + ra/board/ra8m1_vk/board_init.c | 48 + ra/board/ra8m1_vk/board_init.h | 44 + ra/board/ra8m1_vk/board_leds.c | 57 + ra/board/ra8m1_vk/board_leds.h | 60 + ra/fsp/inc/api/r_lpm_api.h | 15 + ra/fsp/inc/api/r_rtc_api.h | 14 +- ra/fsp/inc/api/rm_comms_api.h | 1 + ra/fsp/inc/api/rm_zmod4xxx_api.h | 21 + ra/fsp/inc/fsp_version.h | 6 +- ra/fsp/inc/instances/r_adc.h | 1 + ra/fsp/inc/instances/r_ospi_b.h | 8 + ra/fsp/inc/instances/r_sau_uart.h | 14 +- ra/fsp/inc/instances/r_sci_uart.h | 33 + ra/fsp/inc/instances/r_uarta.h | 31 +- ra/fsp/inc/instances/rm_comms_smbus.h | 17 + ra/fsp/inc/instances/rm_littlefs_flash.h | 4 +- ra/fsp/inc/instances/rm_littlefs_spi_flash.h | 120 + ra/fsp/inc/instances/rm_motor_120_driver.h | 3 +- ra/fsp/inc/instances/rm_motor_driver.h | 3 +- ra/fsp/inc/instances/rm_zmod4xxx.h | 4 + .../cmsis/Device/RENESAS/Include/R7FA0E107.h | 282 +- .../cmsis/Device/RENESAS/Include/R7FA2A1AB.h | 254 +- .../cmsis/Device/RENESAS/Include/R7FA2A2AD.h | 151 +- .../cmsis/Device/RENESAS/Include/R7FA2E1A9.h | 151 +- .../cmsis/Device/RENESAS/Include/R7FA2E2A7.h | 965 +- .../cmsis/Device/RENESAS/Include/R7FA2E307.h | 151 +- .../cmsis/Device/RENESAS/Include/R7FA2L1AB.h | 151 +- .../cmsis/Device/RENESAS/Include/R7FA4E10D.h | 194 +- .../cmsis/Device/RENESAS/Include/R7FA4E2B9.h | 1138 +- .../cmsis/Device/RENESAS/Include/R7FA4M1AB.h | 194 +- .../cmsis/Device/RENESAS/Include/R7FA4M2AD.h | 194 +- .../cmsis/Device/RENESAS/Include/R7FA4M3AF.h | 194 +- .../cmsis/Device/RENESAS/Include/R7FA4T1BB.h | 1187 +- .../cmsis/Device/RENESAS/Include/R7FA4W1AD.h | 194 +- .../cmsis/Device/RENESAS/Include/R7FA6E10F.h | 194 +- .../cmsis/Device/RENESAS/Include/R7FA6E2BB.h | 1138 +- .../cmsis/Device/RENESAS/Include/R7FA6M1AD.h | 270 +- .../cmsis/Device/RENESAS/Include/R7FA6M2AF.h | 1084 +- .../cmsis/Device/RENESAS/Include/R7FA6M3AH.h | 270 +- .../cmsis/Device/RENESAS/Include/R7FA6M4AF.h | 194 +- .../cmsis/Device/RENESAS/Include/R7FA6M5BH.h | 1132 +- .../cmsis/Device/RENESAS/Include/R7FA6T1AD.h | 243 +- .../cmsis/Device/RENESAS/Include/R7FA6T2BD.h | 1193 +- .../cmsis/Device/RENESAS/Include/R7FA6T3BB.h | 1214 +- .../cmsis/Device/RENESAS/Include/R7FA8D1BH.h | 1220 +- .../cmsis/Device/RENESAS/Include/R7FA8M1AH.h | 1220 +- .../cmsis/Device/RENESAS/Include/R7FA8T1AH.h | 1218 +- .../bsp/cmsis/Device/RENESAS/Source/system.c | 2 +- ra/fsp/src/bsp/mcu/all/bsp_clocks.c | 77 +- ra/fsp/src/bsp/mcu/all/bsp_clocks.h | 1 - ra/fsp/src/bsp/mcu/all/bsp_irq.c | 2 +- ra/fsp/src/bsp/mcu/all/bsp_module_stop.h | 47 +- ra/fsp/src/bsp/mcu/ra0e1/bsp_feature.h | 143 +- ra/fsp/src/bsp/mcu/ra0e1/bsp_feature_gen.h | 2 + ra/fsp/src/bsp/mcu/ra0e1/bsp_override.h | 1 - ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h | 168 +- ra/fsp/src/bsp/mcu/ra2a1/bsp_feature_gen.h | 2 + ra/fsp/src/bsp/mcu/ra2a2/bsp_feature.h | 187 +- ra/fsp/src/bsp/mcu/ra2a2/bsp_feature_gen.h | 2 + ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h | 181 +- ra/fsp/src/bsp/mcu/ra2e1/bsp_feature_gen.h | 2 + ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h | 176 +- ra/fsp/src/bsp/mcu/ra2e2/bsp_feature_gen.h | 2 + ra/fsp/src/bsp/mcu/ra2e3/bsp_feature.h | 170 +- ra/fsp/src/bsp/mcu/ra2e3/bsp_feature_gen.h | 2 + ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h | 188 +- ra/fsp/src/bsp/mcu/ra2l1/bsp_feature_gen.h | 2 + ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h | 154 +- ra/fsp/src/bsp/mcu/ra4e1/bsp_feature_gen.h | 2 + ra/fsp/src/bsp/mcu/ra4e2/bsp_feature.h | 145 +- ra/fsp/src/bsp/mcu/ra4e2/bsp_feature_gen.h | 2 + ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h | 156 +- ra/fsp/src/bsp/mcu/ra4m1/bsp_feature_gen.h | 2 + ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h | 138 +- ra/fsp/src/bsp/mcu/ra4m2/bsp_feature_gen.h | 2 + ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h | 137 +- ra/fsp/src/bsp/mcu/ra4m3/bsp_feature_gen.h | 2 + ra/fsp/src/bsp/mcu/ra4t1/bsp_feature.h | 146 +- ra/fsp/src/bsp/mcu/ra4t1/bsp_feature_gen.h | 2 + ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h | 160 +- ra/fsp/src/bsp/mcu/ra4w1/bsp_feature_gen.h | 2 + ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h | 134 +- ra/fsp/src/bsp/mcu/ra6e1/bsp_feature_gen.h | 2 + ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h | 145 +- ra/fsp/src/bsp/mcu/ra6e2/bsp_feature_gen.h | 2 + ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h | 132 +- ra/fsp/src/bsp/mcu/ra6m1/bsp_feature_gen.h | 4 +- ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h | 124 +- ra/fsp/src/bsp/mcu/ra6m2/bsp_feature_gen.h | 4 +- ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h | 124 +- ra/fsp/src/bsp/mcu/ra6m3/bsp_feature_gen.h | 4 +- ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h | 128 +- ra/fsp/src/bsp/mcu/ra6m4/bsp_feature_gen.h | 2 + ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h | 128 +- ra/fsp/src/bsp/mcu/ra6m5/bsp_feature_gen.h | 2 + ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h | 146 +- ra/fsp/src/bsp/mcu/ra6t1/bsp_feature_gen.h | 4 +- ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h | 152 +- ra/fsp/src/bsp/mcu/ra6t2/bsp_feature_gen.h | 2 + ra/fsp/src/bsp/mcu/ra6t3/bsp_feature.h | 147 +- ra/fsp/src/bsp/mcu/ra6t3/bsp_feature_gen.h | 2 + ra/fsp/src/bsp/mcu/ra8d1/bsp_elc.h | 2 +- ra/fsp/src/bsp/mcu/ra8d1/bsp_feature.h | 128 +- ra/fsp/src/bsp/mcu/ra8d1/bsp_feature_gen.h | 2 + ra/fsp/src/bsp/mcu/ra8m1/bsp_elc.h | 2 +- ra/fsp/src/bsp/mcu/ra8m1/bsp_feature.h | 128 +- ra/fsp/src/bsp/mcu/ra8m1/bsp_feature_gen.h | 2 + ra/fsp/src/bsp/mcu/ra8t1/bsp_elc.h | 2 +- ra/fsp/src/bsp/mcu/ra8t1/bsp_feature.h | 140 +- ra/fsp/src/bsp/mcu/ra8t1/bsp_feature_gen.h | 2 + ra/fsp/src/r_agt/r_agt.c | 11 - ra/fsp/src/r_can/r_can.c | 12 +- ra/fsp/src/r_ceu/r_ceu.c | 8 +- ra/fsp/src/r_i3c/r_i3c.c | 15 +- ra/fsp/src/r_iica_master/r_iica_master.c | 22 +- ra/fsp/src/r_lpm/r_lpm.c | 6 +- ra/fsp/src/r_mipi_dsi/r_mipi_dsi.c | 36 +- ra/fsp/src/r_ospi_b/r_ospi_b.c | 135 +- .../src/rsip/common/primitive/r_rsip_util.h | 2 +- .../src/rsip/common/private/r_rsip_private.c | 4 +- .../ra/primitive/ra_rsip_e51a/r_rsip_p2c.c | 15 +- ra/fsp/src/r_rtc/r_rtc.c | 6 +- ra/fsp/src/r_sau_uart/r_sau_uart.c | 173 +- .../r_sce/aes2/adaptors/hw_sce_ra_private.h | 47 + .../src/r_sce/aes2/adaptors/r_sce_AES_adapt.c | 106 + .../src/rsip7/plainkey/adaptors/r_sce_adapt.c | 78 + .../plainkey/private/inc/hw_sce_ra_private.h | 14 + .../src/rsip7/plainkey/public/inc/r_sce_if.h | 6 +- .../rsip_e11a/plainkey/adaptors/r_sce_adapt.c | 840 + .../plainkey/primitive/DomainParams.c | 563 + .../plainkey/primitive/hw_sce_p_func008.c | 86 + .../plainkey/primitive/hw_sce_p_func043.c | 93 + .../plainkey/primitive/hw_sce_p_func044.c | 50 + .../plainkey/primitive/hw_sce_p_func048.c | 16 + .../plainkey/primitive/hw_sce_p_func049.c | 16 + .../plainkey/primitive/hw_sce_p_func056.c | 19 + .../plainkey/primitive/hw_sce_p_func057.c | 113 + .../plainkey/primitive/hw_sce_p_func058.c | 63 + .../plainkey/primitive/hw_sce_p_func070.c | 82 + .../plainkey/primitive/hw_sce_p_func071.c | 45 + .../plainkey/primitive/hw_sce_p_func073.c | 572 + .../plainkey/primitive/hw_sce_p_func088.c | 161 + .../plainkey/primitive/hw_sce_p_func093.c | 108 + .../plainkey/primitive/hw_sce_p_func100.c | 16 + .../plainkey/primitive/hw_sce_p_func101.c | 16 + .../plainkey/primitive/hw_sce_p_func102.c | 15 + .../plainkey/primitive/hw_sce_p_func103.c | 38 + .../plainkey/primitive/hw_sce_p_func205.c | 17 + .../plainkey/primitive/hw_sce_p_func206.c | 18 + .../plainkey/primitive/hw_sce_p_p00.c | 15 + .../plainkey/primitive/hw_sce_p_p07.c | 110 + .../plainkey/primitive/hw_sce_p_p08.c | 126 + .../plainkey/primitive/hw_sce_p_p20.c | 37 + .../plainkey/primitive/hw_sce_p_p21.c | 63 + .../plainkey/primitive/hw_sce_p_p29a.c | 27 + .../plainkey/primitive/hw_sce_p_p29f.c | 150 + .../plainkey/primitive/hw_sce_p_p29i.c | 161 + .../plainkey/primitive/hw_sce_p_p29t.c | 24 + .../plainkey/primitive/hw_sce_p_p29u.c | 37 + .../plainkey/primitive/hw_sce_p_p32a.c | 27 + .../plainkey/primitive/hw_sce_p_p32f.c | 194 + .../plainkey/primitive/hw_sce_p_p32i.c | 160 + .../plainkey/primitive/hw_sce_p_p32t.c | 24 + .../plainkey/primitive/hw_sce_p_p32u.c | 37 + .../plainkey/primitive/hw_sce_p_p34a.c | 27 + .../plainkey/primitive/hw_sce_p_p34f.c | 150 + .../plainkey/primitive/hw_sce_p_p34i.c | 159 + .../plainkey/primitive/hw_sce_p_p34t.c | 24 + .../plainkey/primitive/hw_sce_p_p34u.c | 37 + .../plainkey/primitive/hw_sce_p_p36a.c | 27 + .../plainkey/primitive/hw_sce_p_p36f.c | 194 + .../plainkey/primitive/hw_sce_p_p36i.c | 159 + .../plainkey/primitive/hw_sce_p_p36t.c | 24 + .../plainkey/primitive/hw_sce_p_p36u.c | 37 + .../plainkey/primitive/hw_sce_p_p40.c | 247 + .../plainkey/primitive/hw_sce_p_p47f.c | 37 + .../plainkey/primitive/hw_sce_p_p47i.c | 193 + .../plainkey/primitive/hw_sce_p_p47u.c | 103 + .../plainkey/primitive/hw_sce_p_p50f.c | 37 + .../plainkey/primitive/hw_sce_p_p50i.c | 188 + .../plainkey/primitive/hw_sce_p_p50u.c | 108 + .../plainkey/primitive/hw_sce_p_p6e.c | 208 + .../plainkey/primitive/hw_sce_p_p70.c | 118 + .../plainkey/primitive/hw_sce_p_p72.c | 64 + .../plainkey/primitive/hw_sce_p_p81.c | 80 + .../plainkey/primitive/hw_sce_p_p82.c | 415 + .../plainkey/primitive/hw_sce_p_p9a.c | 222 + .../plainkey/primitive/hw_sce_p_pf0.c | 421 + .../plainkey/primitive/hw_sce_p_pf1.c | 97 + .../plainkey/primitive/hw_sce_p_pf4.c | 441 + .../rsip_e11a/plainkey/primitive/s_flash.c | 81 + .../plainkey/private/inc/SCE_ProcCommon.h | 93089 ++++++++++++++++ .../plainkey/private/inc/SCE_module.h | 30 + .../plainkey/private/inc/hw_sce_ra_private.h | 356 + .../rsip_e11a/plainkey/public/inc/r_sce_if.h | 1703 + .../src/sce5/plainkey/adaptors/r_sce_adapt.c | 80 +- .../plainkey/private/inc/hw_sce_ra_private.h | 15 +- .../src/sce5b/plainkey/adaptors/r_sce_adapt.c | 80 +- .../plainkey/private/inc/hw_sce_ra_private.h | 14 + .../src/sce7/plainkey/adaptors/r_sce_adapt.c | 80 +- .../plainkey/private/inc/hw_sce_ra_private.h | 14 + .../src/sce9/plainkey/adaptors/r_sce_adapt.c | 79 +- .../plainkey/private/inc/hw_sce_ra_private.h | 15 +- ra/fsp/src/r_sce/hw_sce_aes_private.h | 5 - ra/fsp/src/r_sce/hw_sce_ecc_private.h | 18 +- ra/fsp/src/r_sce/hw_sce_hash_private.h | 9 + .../r_sce/ra2/adaptors/hw_sce_ra_private.h | 12 + .../src/r_sce/ra2/adaptors/r_sce_AES_adapt.c | 22 + ra/fsp/src/r_sci_b_spi/r_sci_b_spi.c | 3 + ra/fsp/src/r_sci_uart/r_sci_uart.c | 90 +- ra/fsp/src/r_tml/r_tml.c | 427 +- ra/fsp/src/r_uarta/r_uarta.c | 243 +- .../r_usb_basic/src/hw/r_usb_hreg_access.c | 2 +- .../r_usb_basic/src/hw/r_usb_preg_access.c | 2 +- ra/fsp/src/rm_ble_abs_gtl/r_ble_gtl_api.c | 78 +- .../rm_block_media_ram/rm_block_media_ram.c | 19 +- .../cellular_gm.c} | 12 +- .../cellular_gm.h} | 34 +- .../cellular_gm_api.c} | 138 +- .../cellular_gm_urc_handler.c} | 48 +- .../cellular_gm_wrapper.c} | 2 +- ra/fsp/src/rm_comms_smbus/rm_comms_smbus.c | 33 +- .../rm_freertos_plus_tcp/NetworkInterface.c | 2 +- .../src/rm_littlefs_flash/rm_littlefs_flash.c | 8 +- .../rm_littlefs_spi_flash.c | 382 + ra/fsp/src/rm_lwip_ether/rm_lwip_ether.c | 434 + ra/fsp/src/rm_lwip_ether/rm_lwip_ether.h | 82 + ra/fsp/src/rm_lwip_sys_port/arch/cc.h | 16 + .../baremetal/arch/sys_arch.h | 10 + .../baremetal/rm_lwip_sys_baremetal.c | 440 + .../baremetal/rm_lwip_sys_baremetal.h | 43 + ra/fsp/src/rm_mbedtls/x509_crt.c | 39 +- ra/fsp/src/rm_mcuboot_port/rm_mcuboot_port.c | 23 +- .../rm_motor_120_driver/rm_motor_120_driver.c | 8 +- ra/fsp/src/rm_motor_driver/rm_motor_driver.c | 4 +- ra/fsp/src/rm_psa_crypto/aes_alt.c | 185 +- ra/fsp/src/rm_psa_crypto/aes_alt_process.c | 106 +- ra/fsp/src/rm_psa_crypto/asymmetric_vendor.c | 4 +- ra/fsp/src/rm_psa_crypto/ccm_alt.c | 98 +- ra/fsp/src/rm_psa_crypto/ccm_alt_process.c | 15 +- ra/fsp/src/rm_psa_crypto/cipher_alt.c | 54 +- ra/fsp/src/rm_psa_crypto/cmac_alt.c | 62 +- ra/fsp/src/rm_psa_crypto/ctr_drbg_alt.c | 221 +- ra/fsp/src/rm_psa_crypto/ecdh_alt.c | 29 +- ra/fsp/src/rm_psa_crypto/ecdsa_alt.c | 13 +- ra/fsp/src/rm_psa_crypto/ecdsa_alt_process.c | 19 +- ra/fsp/src/rm_psa_crypto/ecp_alt.c | 123 +- ra/fsp/src/rm_psa_crypto/ecp_alt_process.c | 274 +- ra/fsp/src/rm_psa_crypto/ecp_curves_alt.c | 678 +- ra/fsp/src/rm_psa_crypto/gcm_alt.c | 406 +- ra/fsp/src/rm_psa_crypto/gcm_alt_process.c | 107 +- ra/fsp/src/rm_psa_crypto/inc/ecp_alt.h | 2 +- ra/fsp/src/rm_psa_crypto/inc/gcm_alt.h | 32 +- ra/fsp/src/rm_psa_crypto/rsa_alt.c | 556 +- ra/fsp/src/rm_psa_crypto/rsa_alt_process.c | 11 - ra/fsp/src/rm_psa_crypto/sha256_alt.c | 166 +- ra/fsp/src/rm_psa_crypto/sha256_alt_process.c | 18 +- ra/fsp/src/rm_psa_crypto/sha512_alt.c | 53 +- ra/fsp/src/rm_psa_crypto/sha512_alt_process.c | 6 - ra/fsp/src/rm_psa_crypto/vendor.c | 42 +- ra/fsp/src/rm_tfm_port/config_impl.h | 35 +- ra/fsp/src/rm_tfm_port/ra/boot_hal_bl2.c | 13 + ra/fsp/src/rm_tfm_port/ra/tfm_hal_isolation.c | 2 + ra/fsp/src/rm_tfm_port/ra/tz_shim_layer.c | 11 +- ra/fsp/src/rm_touch/rm_touch.c | 12 +- .../iaq_1st_gen/rm_zmod4410_iaq_1st_gen.c | 20 + .../iaq_2nd_gen/rm_zmod4410_iaq_2nd_gen.c | 20 + .../rm_zmod4410_iaq_2nd_gen_ulp.c | 20 + ra/fsp/src/rm_zmod4xxx/no2_o3/no2_o3.h | 104 + .../rm_zmod4xxx/no2_o3/rm_zmod4510_no2_o3.c | 420 + .../no2_o3/zmod4510_config_no2_o3.h | 101 + .../oaq_1st_gen/rm_zmod4510_oaq_1st_gen.c | 20 + .../src/rm_zmod4xxx/oaq_2nd_gen/oaq_2nd_gen.h | 128 +- .../oaq_2nd_gen/rm_zmod4510_oaq_2nd_gen.c | 23 + ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/ulp_o3.h | 102 + .../oaq_2nd_gen/zmod4510_config_oaq2.h | 96 +- .../oaq_2nd_gen/zmod4510_config_ulp_o3.h | 95 + .../src/rm_zmod4xxx/odor/rm_zmod4410_odor.c | 20 + .../src/rm_zmod4xxx/pbaq/rm_zmod4410_pbaq.c | 20 + ra/fsp/src/rm_zmod4xxx/raq/rm_zmod4450_raq.c | 20 + .../rm_zmod4xxx/rel_iaq/rm_zmod4410_rel_iaq.c | 20 + .../rel_iaq_ulp/rm_zmod4410_rel_iaq_ulp.c | 20 + ra/fsp/src/rm_zmod4xxx/rm_zmod4xxx.c | 38 + .../sulfur_odor/rm_zmod4410_sulfur_odor.c | 20 + 303 files changed, 127262 insertions(+), 5986 deletions(-) create mode 100644 CONTRIBUTING.md create mode 100644 ra/board/ra2l1_voice/board.h create mode 100644 ra/board/ra2l1_voice/board_init.c create mode 100644 ra/board/ra2l1_voice/board_init.h create mode 100644 ra/board/ra2l1_voice/board_leds.c create mode 100644 ra/board/ra2l1_voice/board_leds.h create mode 100644 ra/board/ra4e1_voice/board.h create mode 100644 ra/board/ra4e1_voice/board_init.c create mode 100644 ra/board/ra4e1_voice/board_init.h create mode 100644 ra/board/ra4e1_voice/board_leds.c create mode 100644 ra/board/ra4e1_voice/board_leds.h create mode 100644 ra/board/ra6e1_voice/board.h create mode 100644 ra/board/ra6e1_voice/board_init.c create mode 100644 ra/board/ra6e1_voice/board_init.h create mode 100644 ra/board/ra6e1_voice/board_leds.c create mode 100644 ra/board/ra6e1_voice/board_leds.h create mode 100644 ra/board/ra8m1_vk/board.h create mode 100644 ra/board/ra8m1_vk/board_init.c create mode 100644 ra/board/ra8m1_vk/board_init.h create mode 100644 ra/board/ra8m1_vk/board_leds.c create mode 100644 ra/board/ra8m1_vk/board_leds.h create mode 100644 ra/fsp/inc/instances/rm_littlefs_spi_flash.h create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/adaptors/r_sce_adapt.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/DomainParams.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func008.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func043.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func044.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func048.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func049.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func056.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func057.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func058.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func070.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func071.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func073.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func088.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func093.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func100.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func101.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func102.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func103.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func205.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func206.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p00.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p07.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p08.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p20.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p21.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p29a.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p29f.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p29i.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p29t.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p29u.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p32a.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p32f.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p32i.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p32t.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p32u.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p34a.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p34f.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p34i.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p34t.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p34u.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p36a.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p36f.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p36i.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p36t.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p36u.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p40.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p47f.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p47i.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p47u.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p50f.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p50i.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p50u.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p6e.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p70.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p72.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p81.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p82.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p9a.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_pf0.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_pf1.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_pf4.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/s_flash.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/private/inc/SCE_ProcCommon.h create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/private/inc/SCE_module.h create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/private/inc/hw_sce_ra_private.h create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/public/inc/r_sce_if.h rename ra/fsp/src/{rm_cellular_ryz_aws/cellular_ryz.c => rm_cellular_gm_aws/cellular_gm.c} (95%) rename ra/fsp/src/{rm_cellular_ryz_aws/cellular_ryz.h => rm_cellular_gm_aws/cellular_gm.h} (64%) rename ra/fsp/src/{rm_cellular_ryz_aws/cellular_ryz_api.c => rm_cellular_gm_aws/cellular_gm_api.c} (95%) rename ra/fsp/src/{rm_cellular_ryz_aws/cellular_ryz_urc_handler.c => rm_cellular_gm_aws/cellular_gm_urc_handler.c} (73%) rename ra/fsp/src/{rm_cellular_ryz_aws/cellular_ryz_wrapper.c => rm_cellular_gm_aws/cellular_gm_wrapper.c} (99%) create mode 100644 ra/fsp/src/rm_littlefs_spi_flash/rm_littlefs_spi_flash.c create mode 100644 ra/fsp/src/rm_lwip_ether/rm_lwip_ether.c create mode 100644 ra/fsp/src/rm_lwip_ether/rm_lwip_ether.h create mode 100644 ra/fsp/src/rm_lwip_sys_port/arch/cc.h create mode 100644 ra/fsp/src/rm_lwip_sys_port/baremetal/arch/sys_arch.h create mode 100644 ra/fsp/src/rm_lwip_sys_port/baremetal/rm_lwip_sys_baremetal.c create mode 100644 ra/fsp/src/rm_lwip_sys_port/baremetal/rm_lwip_sys_baremetal.h create mode 100644 ra/fsp/src/rm_zmod4xxx/no2_o3/no2_o3.h create mode 100644 ra/fsp/src/rm_zmod4xxx/no2_o3/rm_zmod4510_no2_o3.c create mode 100644 ra/fsp/src/rm_zmod4xxx/no2_o3/zmod4510_config_no2_o3.h create mode 100644 ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/ulp_o3.h create mode 100644 ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/zmod4510_config_ulp_o3.h diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md new file mode 100644 index 000000000..27ff6eb1d --- /dev/null +++ b/CONTRIBUTING.md @@ -0,0 +1,65 @@ +# Contributing to FSP for Renesas RA MCU Family + +Thank you for your interest in contributing to FSP for RA. This document will help you navigate the contribution process. + +## Table of Contents + +- [Bug Reports](#bug-reports) +- [Feature/Enhancement Requests](#featureenhancement-requests) +- [Contributing Code](#contributing-code) + - [Signing Contributor License Agreement](#signing-contributor-license-agreement) + - [Contributing through a Pull Request](#contributing-through-a-pull-request) +- [Technical support](#technical-support) + +## Bug Reports + +If the bug is a security vulnerability, follow the instructions for reporting a vulnerability [here](https://github.com/renesas/fsp/security). + +For all other bugs, [create a Github issue](https://docs.github.com/en/issues/tracking-your-work-with-issues/creating-an-issue). To help us reproduce and address the bug, please include the following information: + +- Expected behavior +- Actual behavior +- Steps to reproduce +- Logs/screenshots/measurements (if relevant to the issue) + +An FSP maintainer will review the issue and follow up in a comment. + +## Feature/Enhancement Requests + +We consider all feature requests made through [Github issues](https://docs.github.com/en/issues/tracking-your-work-with-issues/creating-an-issue). + +- The FSP team will review your request and may respond with follow-up questions. +- If we determine the feature is a good fit for FSP, we will prioritize and assign it internally. +- When work begins on a feature, we will add a comment to the issue. +- When the feature is included in an FSP release, we will close the issue and add a comment containing the release version that contains the feature. +- Unfortunately, not all feature requests can be implemented. Issues that will not be implemented (ex. not feasible, not a good fit for FSP, insufficient details) will be closed. + +If you would like to implement a feature request made by someone else, and work has not already started on that issue, please comment on the issue that you would like to work on it, and your plan for implementation. Then follow the [Contributing Code](#contributing-code) process to make the updates. + +## Contributing Code + +### Signing Contributor License Agreement + +We require community contributors to sign a Contributor License Agreement (CLA). If you or your organization haven't previously signed, a bot comment will prompt you to sign the CLA when you create a pull request. + +Ensure a CLA has been signed for your GitHub account by checking the [CLA page](https://cla-assistant.io/renesas/fsp). + +### Contributing through a Pull Request + +We welcome contributions via Github Pull Requests. If you're interested in contributing, please follow these steps: + +1. Make sure the code change is relevant to FSP for the Renesas RA MCU Family +1. Search the Github issues (including closed issues) to confirm the change is not a duplicate of another issue +1. [Create a GitHub issue](https://docs.github.com/en/issues/tracking-your-work-with-issues/creating-an-issue) with details of the proposed features or improvements or comment the planned changes on the existing issue (if applicable) + - The FSP team will review the plan and either approve it or suggest changes as needed. + - We highly recommend waiting for FSP team approval for all substantial changes, however if your change is very straightforward (ex. 1-line bug fix), you can make a PR without waiting for approval. +1. [Fork the repository](https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/fork-a-repo) to your GitHub account for the feature development. + - Once development is complete, create a [pull request](https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/proposing-changes-to-your-work-with-pull-requests/creating-a-pull-request-from-a-fork). + 1. The FSP team will review your PR, ask questions if we have any, and perform internal integration and testing. + - When the change is accepted, we will let you know in a Github comment and close the pull request. + +**Important:** If you are contributing multiple independent features/bug fixes, please submit a separate pull request for each item. + +## Technical Support + +Need help with something other than RA FSP? For general support requests or questions related to Renesas products, tools, or environments, feel free to submit a ticket in our support [system](https://www.renesas.com/us/en/support). We're here to help! diff --git a/README.md b/README.md index c56c089ae..037b91c06 100644 --- a/README.md +++ b/README.md @@ -10,7 +10,7 @@ FSP uses an open software ecosystem and provides flexibility in using your prefe ### Current Release -[FSP v5.4.0](https://github.com/renesas/fsp/releases/tag/v5.4.0) +[FSP v5.5.0](https://github.com/renesas/fsp/releases/tag/v5.5.0) ### Supported RA MCU Kits @@ -54,6 +54,10 @@ FSP uses an open software ecosystem and provides flexibility in using your prefe - MCK-RA8T1 - RSSK-RA2L1 - RSSK-RA6T1 +- VK-RA8M1 +- VOICE-RA2L1 +- VOICE-RA4E1 +- VOICE-RA6E1 ### Supported Software Packaged with FSP @@ -96,6 +100,7 @@ It is important to note that updates for Azure RTOS on these hardware will no lo - FSP versions of 5.0.0 and later require a minimum e² studio version of 2023-10. - FSP versions of 5.2.0 and later require a minimum e² studio version of 2024-01.1. - FSP versions of 5.3.0 and later require a minimum e² studio version of 2024-04. +- FSP versions of 5.5.0 and later require a minimum e² studio version of 2024-07. If you have already installed a previous FSP release that included e² studio then you can download the packs separately. These are available for download under the Assets section for each release. There is a zipped version, FSP_Packs_\.zip, that will work on any supported OS. There is also a self-extracting installer version, FSP_Packs_\.exe, that will work on Windows. @@ -103,7 +108,7 @@ When using the zipped version of the packs the zip file should be extracted into #### For new users that are using FSP with e² studio -1. Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v5.4.0). +1. Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v5.5.0). 2. Run the installer. This will install the e² studio tool, FSP packs, GCC toolchain and other tools required to use this software. No additional installations are required. #### If using RA Smart Configurator (RASC) with IAR Embedded Workbench or Keil MDK #### diff --git a/SUPPORTED_SOFTWARE.md b/SUPPORTED_SOFTWARE.md index ecf75356c..17ecae0d7 100644 --- a/SUPPORTED_SOFTWARE.md +++ b/SUPPORTED_SOFTWARE.md @@ -175,13 +175,15 @@ * [BLE Mesh Network (rm_ble_mesh_network)](https://renesas.github.io/fsp/group___r_m___b_l_e___m_e_s_h___n_e_t_w_o_r_k.html) * [BLE Mesh Provision (rm_ble_mesh_provision)](https://renesas.github.io/fsp/group___r_m___b_l_e___m_e_s_h___p_r_o_v_i_s_i_o_n.html) * [BLE Mesh Upper Trans (rm_ble_mesh_upper_trans)](https://renesas.github.io/fsp/group___r_m___b_l_e___m_e_s_h___u_p_p_e_r___t_r_a_n_s.html) + * [AWS Cellular Interface on GM (rm_cellular_gm_aws)](https://renesas.github.io/fsp/group___r_m___c_e_l_l_u_l_a_r___r_y_z___a_w_s.html) * [AWS Cellular Interface on RYZ (rm_cellular_ryz_aws) [Deprecated]](https://renesas.github.io/fsp/group___r_m___c_e_l_l_u_l_a_r___r_y_z___a_w_s.html) * [AWS Core HTTP](https://docs.aws.amazon.com/freertos/latest/userguide/core-http.html) * [AWS Core MQTT](https://docs.aws.amazon.com/freertos/latest/userguide/coremqtt.html) * [AWS IoT Over-the-air Update Library](https://github.com/aws/ota-for-aws-iot-embedded-sdk) * [AWS Transport Interface on MbedTLS/PKCS11 (rm_aws_transport_interface_port)](https://docs.aws.amazon.com/embedded-csdk/latest/lib-ref/libraries/standard/coreMQTT/docs/doxygen/output/html/mqtt_transport_interface.html) - * [Azure EWF Adapter on RYZ014A [Deprecated]](https://renesas.github.io/fsp/group___r_m___a_z_u_r_e___e_w_f___r_y_z.html) - * [Azure EWF Adapter on RYZ024A [Deprecated]](https://renesas.github.io/fsp/group___r_m___a_z_u_r_e___e_w_f___r_y_z.html) + * [Azure EWF Adapter on GM02S](https://renesas.github.io/fsp/group___r_m___a_z_u_r_e___e_w_f___g_m.html) + * [Azure EWF Adapter on RYZ014A [Deprecated]](https://renesas.github.io/fsp/group___r_m___a_z_u_r_e___e_w_f___g_m.html) + * [Azure EWF Adapter on RYZ024A [Deprecated]](https://renesas.github.io/fsp/group___r_m___a_z_u_r_e___e_w_f___g_m.html) * [Azure RTOS NetX Duo Auto IP](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-auto-ip/chapter1.md) * [Azure RTOS NetX Duo BSD Support](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/netx-duo-bsd/chapter1.md) * [Azure RTOS NetX Duo Common](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/netx-duo/index.md) @@ -217,14 +219,16 @@ * [FreeRTOS+TCP](https://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/TCP_IP_Configuration.html) * [GTL BLE Abstraction (rm_ble_abs_gtl)](https://renesas.github.io/fsp/group___b_l_e___a_b_s.html) * [HTTP Client on DA16XXX (rm_http_onchip_da16xxx)](https://renesas.github.io/fsp/group___h_t_t_p___o_n_c_h_i_p___d_a16_x_x_x.html) + * [LwIP system FreeRTOS port](https://www.nongnu.org/lwip/2_1_x/index.html) * [MQTT Client on DA16XXX (rm_mqtt_onchip_da16xxx)](https://renesas.github.io/fsp/group___m_q_t_t___o_n_c_h_i_p___d_a16_x_x_x.html) * [PTP (r_ptp)](https://renesas.github.io/fsp/group___p_t_p.html) * [SPP BLE Abstraction (rm_ble_abs_spp)](https://renesas.github.io/fsp/group___b_l_e___a_b_s.html) + * [lwIP tcpip (lwip_tcpip)](https://www.nongnu.org/lwip/2_1_x/index.html) * Power * [Low Power Modes (r_lpm)](https://renesas.github.io/fsp/group___l_p_m.html) * RTOS * [Azure RTOS ThreadX Port (rm_threadx_port)](https://renesas.github.io/fsp/group___r_m___t_h_r_e_a_d_x___p_o_r_t.html) - * [FreeRTOS Buffer Allocation 2](https://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/Embedded_Ethernet_Buffer_Management.html) + * [FreeRTOS Buffer Allocation 2](https://www.freertos.org/Documentation/03-Libraries/02-FreeRTOS-plus/02-FreeRTOS-plus-TCP/05-Buffer-management) * [FreeRTOS Heap 1](https://www.freertos.org/a00111.html#heap_1) * [FreeRTOS Heap 2](https://www.freertos.org/a00111.html#heap_2) * [FreeRTOS Heap 3](https://www.freertos.org/a00111.html#heap_3) @@ -245,11 +249,11 @@ * [Trusted Firmware-M Non-Secure](https://tf-m-user-guide.trustedfirmware.org/) * Sensor * [FS1015 Flow Sensor (rm_fs1015)](https://renesas.github.io/fsp/group___r_m___f_s1015.html) - * [FS2012 Flow Sensor (rm_fs2012)](https://renesas.github.io/fsp/group___r_m___f_s2012.html) + * [FS2012 Flow Sensor (rm_fs2012) [Deprecated]](https://renesas.github.io/fsp/group___r_m___f_s2012.html) * [FS3000 Flow Sensor (rm_fs3000)](https://renesas.github.io/fsp/group___r_m___f_s3000.html) * [HS300X Temperature/Humidity Sensor (rm_hs300x)](https://renesas.github.io/fsp/group___r_m___h_s300_x.html) * [HS400X Temperature/Humidity Sensor (rm_hs400x)](https://renesas.github.io/fsp/group___r_m___h_s400_x.html) - * [OB1203 Light/Proximity/PPG Sensor (rm_ob1203)](https://renesas.github.io/fsp/group___r_m___o_b1203.html) + * [OB1203 Light/Proximity/PPG Sensor (rm_ob1203) [Deprecated]](https://renesas.github.io/fsp/group___r_m___o_b1203.html) * [RRH46410 Gas Sensor Module (rm_rrh46410)](https://renesas.github.io/fsp/group___r_m___r_r_h46410.html) * [ZMOD4XXX Gas Sensor (rm_zmod4xxx)](https://renesas.github.io/fsp/group___r_m___z_m_o_d4_x_x_x.html) * Storage @@ -347,6 +351,7 @@ * [AWS PKCS11 to MbedTLS](https://docs.aws.amazon.com/freertos/latest/userguide/security-pkcs.html) * [AWS Silex WiFi Sockets Wrapper (rm_aws_sockets_wrapper_silex)](https://docs.aws.amazon.com/embedded-csdk/latest/lib-ref/libraries/standard/coreMQTT/docs/doxygen/output/html/mqtt_transport_interface.html) * [AWS TCP Sockets Wrapper](https://docs.aws.amazon.com/embedded-csdk/latest/lib-ref/libraries/standard/coreMQTT/docs/doxygen/output/html/mqtt_transport_interface.html) + * [Azure EWF Adapter on GM01Q](https://renesas.github.io/fsp/group___r_m___a_z_u_r_e___e_w_f___g_m.html) * [Azure EWF Heap Allocator](https://azure.github.io/embedded-wireless-framework/html/index.html) * [Azure EWF Interface on r_uart](https://azure.github.io/embedded-wireless-framework/html/index.html) * [Azure EWF Memory Pool Allocator](https://azure.github.io/embedded-wireless-framework/html/index.html) @@ -380,11 +385,15 @@ * [WiFi Common](https://docs.aws.amazon.com/freertos/latest/userguide/freertos-wifi.html) * [WiFi DA16XXX Framework Driver (rm_wifi_da16xxx)](https://renesas.github.io/fsp/group___w_i_f_i___d_a16_x_x_x.html) * [WiFi Onchip Silex Driver using UART (rm_wifi_onchip_silex)](https://renesas.github.io/fsp/group___w_i_f_i___o_n_c_h_i_p___s_i_l_e_x.html) + * [lwIP Wrapper to r_ether (rm_lwip_ether)](https://renesas.github.io/fsp/group___r_m___l_w_i_p___e_t_h_e_r.html) + * [lwIP system baremetal (rm_lwip_sys_baremetal)](https://renesas.github.io/fsp/group___r_m___l_w_i_p___s_y_s___b_a_r_e_m_e_t_a_l.html) + * [lwIP system freertos Ethernet (rm_lwip_sys_freertos)](https://renesas.github.io/fsp/group___r_m___l_w_i_p___s_y_s___f_r_e_e_r_t_o_s.html) * Security * [Azure RTOS NetX Crypto HW Acceleration (rm_netx_secure_crypto)](https://renesas.github.io/fsp/group___r_m___n_e_t_x___s_e_c_u_r_e___c_r_y_p_t_o.html) * [Azure RTOS NetX Crypto Software Only](https://renesas.github.io/fsp/group___r_m___n_e_t_x___s_e_c_u_r_e___c_r_y_p_t_o.html) * [Crypto AES2](https://renesas.github.io/fsp/) * [Crypto RA2](https://renesas.github.io/fsp/) + * [Crypto RSIP E11A](https://renesas.github.io/fsp/) * [FreeRTOS MbedTLS Port](https://renesas.github.io/fsp/) * [Key Injection for PSA Crypto](https://renesas.github.io/fsp/group___s_c_e___k_e_y___i_n_j_e_c_t_i_o_n.html) * [MCUBoot TinyCrypt H/W Acceleration (rm_mcuboot_tinycrypt_port)](https://renesas.github.io/fsp/group___r_m___t_i_n_y_c_r_y_p_t___p_o_r_t.html) @@ -413,13 +422,14 @@ * [ZMOD4410 IAQ 1st Generation (rm_zmod4xxx)](https://renesas.github.io/fsp/group___r_m___z_m_o_d4_x_x_x.html) * [ZMOD4410 IAQ 2nd Generation (rm_zmod4xxx)](https://renesas.github.io/fsp/group___r_m___z_m_o_d4_x_x_x.html) * [ZMOD4410 IAQ 2nd Generation Ultra Low Power (rm_zmod4xxx)](https://renesas.github.io/fsp/group___r_m___z_m_o_d4_x_x_x.html) - * [ZMOD4410 Odor (rm_zmod4xxx)](https://renesas.github.io/fsp/group___r_m___z_m_o_d4_x_x_x.html) + * [ZMOD4410 Odor (rm_zmod4xxx) [Deprecated]](https://renesas.github.io/fsp/group___r_m___z_m_o_d4_x_x_x.html) * [ZMOD4410 PBAQ (rm_zmod4xxx)](https://renesas.github.io/fsp/group___r_m___z_m_o_d4_x_x_x.html) * [ZMOD4410 Relative IAQ (rm_zmod4xxx)](https://renesas.github.io/fsp/group___r_m___z_m_o_d4_x_x_x.html) * [ZMOD4410 Relative IAQ Ultra Low Power (rm_zmod4xxx)](https://renesas.github.io/fsp/group___r_m___z_m_o_d4_x_x_x.html) * [ZMOD4410 Sulfur-based Odor (rm_zmod4xxx)](https://renesas.github.io/fsp/group___r_m___z_m_o_d4_x_x_x.html) * [ZMOD4450 RAQ (rm_zmod4xxx)](https://renesas.github.io/fsp/group___r_m___z_m_o_d4_x_x_x.html) - * [ZMOD4510 OAQ 1st Generation (rm_zmod4xxx)](https://renesas.github.io/fsp/group___r_m___z_m_o_d4_x_x_x.html) + * [ZMOD4510 NO2 O3 (rm_zmod4xxx)](https://renesas.github.io/fsp/group___r_m___z_m_o_d4_x_x_x.html) + * [ZMOD4510 OAQ 1st Generation (rm_zmod4xxx) [Deprecated]](https://renesas.github.io/fsp/group___r_m___z_m_o_d4_x_x_x.html) * [ZMOD4510 OAQ 2nd Generation (rm_zmod4xxx)](https://renesas.github.io/fsp/group___r_m___z_m_o_d4_x_x_x.html) * Storage * [AWS OTA PAL (rm_aws_ota_pal_mcuboot)](https://renesas.github.io/fsp/group___r_m___a_w_s___o_t_a___p_a_l___m_c_u_b_o_o_t.html) @@ -430,6 +440,7 @@ * [FreeRTOS+FAT Port for RA (rm_freertos_plus_fat)](https://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_FAT/index.html) * [LevelX NOR Port (rm_levelx_nor_spi)](https://renesas.github.io/fsp/group___r_m___l_e_v_e_l_x___n_o_r___s_p_i.html) * [LittleFS on Flash (rm_littlefs_flash)](https://renesas.github.io/fsp/group___r_m___l_i_t_t_l_e_f_s___f_l_a_s_h.html) + * [LittleFS on SPI Flash (rm_littlefs_spi_flash)](https://renesas.github.io/fsp/group___r_m___l_i_t_t_l_e_f_s___f_l_a_s_h.html) * System * [Arm CMSIS6 Core (M)](https://arm-software.github.io/CMSIS_6/latest/Core/index.html) * Timers diff --git a/ra/board/ra2l1_voice/board.h b/ra/board/ra2l1_voice/board.h new file mode 100644 index 000000000..d70741dc2 --- /dev/null +++ b/ra/board/ra2l1_voice/board.h @@ -0,0 +1,47 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup BOARDS + * @defgroup BOARD_RA2L1_VOICE for the RA2L1-VOICE board + * @brief BSP for the RA2L1-VOICE Board + * + * The RA2L1-VOICE is a development kit for the Renesas R7FA2L1AB3CFL microcontroller in a LQFP48 package. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_H +#define BOARD_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP Board Specific Includes. */ +#include "board_init.h" +#include "board_leds.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BOARD_RA2L1_VOICE + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end defgroup BOARD_RA2L1_VOICE) */ + +#endif diff --git a/ra/board/ra2l1_voice/board_init.c b/ra/board/ra2l1_voice/board_init.c new file mode 100644 index 000000000..3371c0e8b --- /dev/null +++ b/ra/board/ra2l1_voice/board_init.c @@ -0,0 +1,48 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA2L1_VOICE + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if defined(BOARD_RA2L1_VOICE) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Performs any initialization specific to this BSP. + * + * @param[in] p_args Pointer to arguments of the user's choice. + **********************************************************************************************************************/ +void bsp_init (void * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); +} + +#endif + +/** @} (end addtogroup BOARD_RA2L1_VOICE) */ diff --git a/ra/board/ra2l1_voice/board_init.h b/ra/board/ra2l1_voice/board_init.h new file mode 100644 index 000000000..d4204620c --- /dev/null +++ b/ra/board/ra2l1_voice/board_init.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA2L1_VOICE + * @brief Board specific code for the RA2L1-VOICE Board + * + * This include file is specific to the RA2L1-VOICE board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_INIT_H +#define BOARD_INIT_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void bsp_init(void * p_args); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end addtogroup BOARD_RA2L1_VOICE) */ diff --git a/ra/board/ra2l1_voice/board_leds.c b/ra/board/ra2l1_voice/board_leds.c new file mode 100644 index 000000000..b1df3dcf4 --- /dev/null +++ b/ra/board/ra2l1_voice/board_leds.c @@ -0,0 +1,57 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA2L1_VOICE_LEDS + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#if defined(BOARD_RA2L1_VOICE) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** Array of LED IOPORT pins. */ +static const uint16_t g_bsp_prv_leds[] = +{ + (uint16_t) BSP_IO_PORT_05_PIN_00, ///< LED1 + (uint16_t) BSP_IO_PORT_02_PIN_13, ///< LED2 + (uint16_t) BSP_IO_PORT_02_PIN_12, ///< LED3 +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/** Structure with LED information for this board. */ + +const bsp_leds_t g_bsp_leds = +{ + .led_count = (uint16_t) ((sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0]))), + .p_leds = &g_bsp_prv_leds[0] +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +#endif + +/** @} (end addtogroup BOARD_RA2L1_VOICE_LEDS) */ diff --git a/ra/board/ra2l1_voice/board_leds.h b/ra/board/ra2l1_voice/board_leds.h new file mode 100644 index 000000000..361501f65 --- /dev/null +++ b/ra/board/ra2l1_voice/board_leds.h @@ -0,0 +1,61 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RA2L1_VOICE + * @defgroup BOARD_RA2L1_VOICE_LEDS Board LEDs + * @brief LED information for this board. + * + * This is code specific to the VOICE board. It includes info on the number of LEDs and which pins are they + * are on. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_LEDS_H +#define BOARD_LEDS_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Information on how many LEDs and what pins they are on. */ +typedef struct st_bsp_leds +{ + uint16_t led_count; ///< The number of LEDs on this board + uint16_t const * p_leds; ///< Pointer to an array of IOPORT pins for controlling LEDs +} bsp_leds_t; + +/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins + * found in the bsp_leds_t structure. */ +typedef enum e_bsp_led +{ + BSP_LED_LED1, ///< LED1 + BSP_LED_LED2, ///< LED2 + BSP_LED_LED3, ///< LED3 +} bsp_led_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RA2L1_VOICE_LEDS) */ diff --git a/ra/board/ra4e1_voice/board.h b/ra/board/ra4e1_voice/board.h new file mode 100644 index 000000000..32f41068c --- /dev/null +++ b/ra/board/ra4e1_voice/board.h @@ -0,0 +1,47 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup BOARDS + * @defgroup BOARD_RA4E1_VOICE for the RA4E1-VK board + * @brief BSP for the RA4E1-VOICE Board + * + * The RA4E1-VOICE is a development kit for the Renesas R7FA4E10D2CNE microcontroller in a QFN48 package. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_H +#define BOARD_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP Board Specific Includes. */ +#include "board_init.h" +#include "board_leds.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BOARD_RA4E1_VOICE + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end defgroup BOARD_RA4E1_VOICE) */ + +#endif diff --git a/ra/board/ra4e1_voice/board_init.c b/ra/board/ra4e1_voice/board_init.c new file mode 100644 index 000000000..3371c0e8b --- /dev/null +++ b/ra/board/ra4e1_voice/board_init.c @@ -0,0 +1,48 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA2L1_VOICE + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if defined(BOARD_RA2L1_VOICE) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Performs any initialization specific to this BSP. + * + * @param[in] p_args Pointer to arguments of the user's choice. + **********************************************************************************************************************/ +void bsp_init (void * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); +} + +#endif + +/** @} (end addtogroup BOARD_RA2L1_VOICE) */ diff --git a/ra/board/ra4e1_voice/board_init.h b/ra/board/ra4e1_voice/board_init.h new file mode 100644 index 000000000..96ad0ba75 --- /dev/null +++ b/ra/board/ra4e1_voice/board_init.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA4E1_VOICE + * @brief Board specific code for the RA4E1-VOICE Board + * + * This include file is specific to the RA4E1-VOICE board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_INIT_H +#define BOARD_INIT_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void bsp_init(void * p_args); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end addtogroup BOARD_RA4E1_VOICE) */ diff --git a/ra/board/ra4e1_voice/board_leds.c b/ra/board/ra4e1_voice/board_leds.c new file mode 100644 index 000000000..ac78b848e --- /dev/null +++ b/ra/board/ra4e1_voice/board_leds.c @@ -0,0 +1,57 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA4E1_VOICE_LEDS + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#if defined(BOARD_RA4E1_VOICE) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** Array of LED IOPORT pins. */ +static const uint16_t g_bsp_prv_leds[] = +{ + (uint16_t) BSP_IO_PORT_05_PIN_00, ///< LED1 + (uint16_t) BSP_IO_PORT_02_PIN_13, ///< LED2 + (uint16_t) BSP_IO_PORT_02_PIN_12, ///< LED3 +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/** Structure with LED information for this board. */ + +const bsp_leds_t g_bsp_leds = +{ + .led_count = (uint16_t) ((sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0]))), + .p_leds = &g_bsp_prv_leds[0] +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +#endif + +/** @} (end addtogroup BOARD_RA4E1_VOICE_LEDS) */ diff --git a/ra/board/ra4e1_voice/board_leds.h b/ra/board/ra4e1_voice/board_leds.h new file mode 100644 index 000000000..930065486 --- /dev/null +++ b/ra/board/ra4e1_voice/board_leds.h @@ -0,0 +1,60 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RA4E1_VOICE + * @defgroup BOARD_RA4E1_VOICE_LEDS Board LEDs + * @brief LED information for this board. + * + * This is code specific to the VOICE board. It includes info on the number of LEDs and which pins they are on. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_LEDS_H +#define BOARD_LEDS_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Information on how many LEDs and what pins they are on. */ +typedef struct st_bsp_leds +{ + uint16_t led_count; ///< The number of LEDs on this board + uint16_t const * p_leds; ///< Pointer to an array of IOPORT pins for controlling LEDs +} bsp_leds_t; + +/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins + * found in the bsp_leds_t structure. */ +typedef enum e_bsp_led +{ + BSP_LED_LED1, ///< LED1 + BSP_LED_LED2, ///< LED2 + BSP_LED_LED3, ///< LED3 +} bsp_led_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RA4E1_VOICE_LEDS) */ diff --git a/ra/board/ra6e1_voice/board.h b/ra/board/ra6e1_voice/board.h new file mode 100644 index 000000000..e3944f9ac --- /dev/null +++ b/ra/board/ra6e1_voice/board.h @@ -0,0 +1,47 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup BOARDS + * @defgroup BOARD_RA6E1_VOICE for the RA6E1-VK board + * @brief BSP for the RA6E1-VOICE Board + * + * The RA6E1-VOICE is a development kit for the Renesas R7FA6E10F2CFM microcontroller in a LQFP64 package. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_H +#define BOARD_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP Board Specific Includes. */ +#include "board_init.h" +#include "board_leds.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BOARD_RA6E1_VOICE + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end defgroup BOARD_RA6E1_VOICE) */ + +#endif diff --git a/ra/board/ra6e1_voice/board_init.c b/ra/board/ra6e1_voice/board_init.c new file mode 100644 index 000000000..3371c0e8b --- /dev/null +++ b/ra/board/ra6e1_voice/board_init.c @@ -0,0 +1,48 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA2L1_VOICE + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if defined(BOARD_RA2L1_VOICE) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Performs any initialization specific to this BSP. + * + * @param[in] p_args Pointer to arguments of the user's choice. + **********************************************************************************************************************/ +void bsp_init (void * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); +} + +#endif + +/** @} (end addtogroup BOARD_RA2L1_VOICE) */ diff --git a/ra/board/ra6e1_voice/board_init.h b/ra/board/ra6e1_voice/board_init.h new file mode 100644 index 000000000..e6e108b14 --- /dev/null +++ b/ra/board/ra6e1_voice/board_init.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA6E1_VOICE + * @brief Board specific code for the RA6E1-VOICE Board + * + * This include file is specific to the RA6E1-VOICE board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_INIT_H +#define BOARD_INIT_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void bsp_init(void * p_args); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end addtogroup BOARD_RA6E1_VOICE) */ diff --git a/ra/board/ra6e1_voice/board_leds.c b/ra/board/ra6e1_voice/board_leds.c new file mode 100644 index 000000000..b9e08cc32 --- /dev/null +++ b/ra/board/ra6e1_voice/board_leds.c @@ -0,0 +1,57 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA6E1_VOICE_LEDS + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#if defined(BOARD_RA6E1_VOICE) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** Array of LED IOPORT pins. */ +static const uint16_t g_bsp_prv_leds[] = +{ + (uint16_t) BSP_IO_PORT_05_PIN_00, ///< LED1 + (uint16_t) BSP_IO_PORT_04_PIN_00, ///< LED2 + (uint16_t) BSP_IO_PORT_01_PIN_13, ///< LED3 +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/** Structure with LED information for this board. */ + +const bsp_leds_t g_bsp_leds = +{ + .led_count = (uint16_t) ((sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0]))), + .p_leds = &g_bsp_prv_leds[0] +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +#endif + +/** @} (end addtogroup BOARD_RA6E1_VOICE_LEDS) */ diff --git a/ra/board/ra6e1_voice/board_leds.h b/ra/board/ra6e1_voice/board_leds.h new file mode 100644 index 000000000..c265edd17 --- /dev/null +++ b/ra/board/ra6e1_voice/board_leds.h @@ -0,0 +1,60 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RA6E1_VOICE + * @defgroup BOARD_RA6E1_VOICE_LEDS Board LEDs + * @brief LED information for this board. + * + * This is code specific to the VOICE board. It includes info on the number of LEDs and which pins they are on. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_LEDS_H +#define BOARD_LEDS_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Information on how many LEDs and what pins they are on. */ +typedef struct st_bsp_leds +{ + uint16_t led_count; ///< The number of LEDs on this board + uint16_t const * p_leds; ///< Pointer to an array of IOPORT pins for controlling LEDs +} bsp_leds_t; + +/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins + * found in the bsp_leds_t structure. */ +typedef enum e_bsp_led +{ + BSP_LED_LED1, ///< LED1 + BSP_LED_LED2, ///< LED2 + BSP_LED_LED3, ///< LED3 +} bsp_led_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RA6E1_VOICE_LEDS) */ diff --git a/ra/board/ra8m1_vk/board.h b/ra/board/ra8m1_vk/board.h new file mode 100644 index 000000000..7fb0eedfe --- /dev/null +++ b/ra/board/ra8m1_vk/board.h @@ -0,0 +1,47 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup BOARDS + * @defgroup BOARD_RA8M1_VK for the RA8M1-VK board + * @brief BSP for the RA8M1-VK Board + * + * The RA8M1-VK is a development kit for the Renesas R7FA8M1AHECFP microcontroller in a LQFP100 package. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_H +#define BOARD_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP Board Specific Includes. */ +#include "board_init.h" +#include "board_leds.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BOARD_RA8M1_VK + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end defgroup BOARD_RA8M1_VK) */ + +#endif diff --git a/ra/board/ra8m1_vk/board_init.c b/ra/board/ra8m1_vk/board_init.c new file mode 100644 index 000000000..56a67cd67 --- /dev/null +++ b/ra/board/ra8m1_vk/board_init.c @@ -0,0 +1,48 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA8M1_VK + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if defined(BOARD_RA8M1_VK) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Performs any initialization specific to this BSP. + * + * @param[in] p_args Pointer to arguments of the user's choice. + **********************************************************************************************************************/ +void bsp_init (void * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); +} + +#endif + +/** @} (end addtogroup BOARD_RA8M1_VK) */ diff --git a/ra/board/ra8m1_vk/board_init.h b/ra/board/ra8m1_vk/board_init.h new file mode 100644 index 000000000..019ced0e1 --- /dev/null +++ b/ra/board/ra8m1_vk/board_init.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA8M1_VK + * @brief Board specific code for the RA8M1-VK Board + * + * This include file is specific to the RA8M1-VK board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_INIT_H +#define BOARD_INIT_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void bsp_init(void * p_args); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end addtogroup BOARD_RA8M1_VK) */ diff --git a/ra/board/ra8m1_vk/board_leds.c b/ra/board/ra8m1_vk/board_leds.c new file mode 100644 index 000000000..848f4822a --- /dev/null +++ b/ra/board/ra8m1_vk/board_leds.c @@ -0,0 +1,57 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA8M1_VK_LEDS + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#if defined(BOARD_RA8M1_VK) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** Array of LED IOPORT pins. */ +static const uint16_t g_bsp_prv_leds[] = +{ + (uint16_t) BSP_IO_PORT_04_PIN_04, ///< LED1 + (uint16_t) BSP_IO_PORT_04_PIN_05, ///< LED2 + (uint16_t) BSP_IO_PORT_04_PIN_06, ///< LED3 +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/** Structure with LED information for this board. */ + +const bsp_leds_t g_bsp_leds = +{ + .led_count = (uint16_t) ((sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0]))), + .p_leds = &g_bsp_prv_leds[0] +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +#endif + +/** @} (end addtogroup BOARD_RA8M1_VK_LEDS) */ diff --git a/ra/board/ra8m1_vk/board_leds.h b/ra/board/ra8m1_vk/board_leds.h new file mode 100644 index 000000000..fac08f722 --- /dev/null +++ b/ra/board/ra8m1_vk/board_leds.h @@ -0,0 +1,60 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RA8M1_VK + * @defgroup BOARD_RA8M1_VK_LEDS Board LEDs + * @brief LED information for this board. + * + * This is code specific to the VK board. It includes info on the number of LEDs and which pins they are on. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_LEDS_H +#define BOARD_LEDS_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Information on how many LEDs and what pins they are on. */ +typedef struct st_bsp_leds +{ + uint16_t led_count; ///< The number of LEDs on this board + uint16_t const * p_leds; ///< Pointer to an array of IOPORT pins for controlling LEDs +} bsp_leds_t; + +/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins + * found in the bsp_leds_t structure. */ +typedef enum e_bsp_led +{ + BSP_LED_LED1, ///< LED1 + BSP_LED_LED2, ///< LED2 + BSP_LED_LED3, ///< LED3 +} bsp_led_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RA8M1_VK_LEDS) */ diff --git a/ra/fsp/inc/api/r_lpm_api.h b/ra/fsp/inc/api/r_lpm_api.h index 5a6995dc8..bd3b5e15a 100644 --- a/ra/fsp/inc/api/r_lpm_api.h +++ b/ra/fsp/inc/api/r_lpm_api.h @@ -212,6 +212,17 @@ typedef enum e_lpm_standby_wake_source LPM_STANDBY_WAKE_SOURCE_ULP1B = 0x400000000000ULL, ///< ULPT1 Compare Match B Interrupt } lpm_standby_wake_source_t; +#if BSP_FEATURE_ICU_HAS_WUPEN2 +typedef enum e_lpm_standby_wake_source_2 +{ + LPM_STANDBY_WAKE_SOURCE_INTUR0 = 0x00000001ULL, ///< UARTA0 INTUR Interrupt + LPM_STANDBY_WAKE_SOURCE_INTURE0 = 0x00000002ULL, ///< UARTA0 INTURE Interrupt + LPM_STANDBY_WAKE_SOURCE_INTUR1 = 0x00000004ULL, ///< UARTA1 INTUR Interrupt + LPM_STANDBY_WAKE_SOURCE_INTURE1 = 0x00000008ULL, ///< UARTA1 INTURE Interrupt + LPM_STANDBY_WAKE_SOURCE_USBCCS = 0x00000010ULL, ///< USBCC Status Change Interrupt +} lpm_standby_wake_source_2_t; +#endif + typedef uint64_t lpm_standby_wake_source_bits_t; #endif @@ -453,6 +464,10 @@ typedef struct st_lpm_cfg /** Bitwise list of sources to wake from deep sleep and standby mode */ lpm_standby_wake_source_bits_t standby_wake_sources; +#if BSP_FEATURE_ICU_HAS_WUPEN2 + lpm_standby_wake_source_bits_t standby_wake_sources_2; +#endif + #if BSP_FEATURE_LPM_HAS_SNOOZE /** Snooze request source */ diff --git a/ra/fsp/inc/api/r_rtc_api.h b/ra/fsp/inc/api/r_rtc_api.h index 3857e0cf2..bb6211f8a 100644 --- a/ra/fsp/inc/api/r_rtc_api.h +++ b/ra/fsp/inc/api/r_rtc_api.h @@ -153,8 +153,8 @@ typedef enum e_rtc_time_capture_source /** Time capture trigger mode */ typedef enum e_rtc_time_capture_mode { - RTC_TIME_CAPTURE_MODE_CONTINUOUS = 0, ///< Continuous capturing to all capturing channels - RTC_TIME_CAPTURE_MODE_ONE_SHOT = 1, ///< Single capture to a particular channel + RTC_TIME_CAPTURE_MODE_CONTINUOUS = 0, ///< Continuous capturing to all capturing channels + RTC_TIME_CAPTURE_MODE_ONE_SHOT = 1, ///< Single capture to a particular channel } rtc_time_capture_mode_t; /** Time capture noise filter control */ @@ -197,11 +197,11 @@ typedef struct st_rtc_alarm_time /** Time capture configuration structure */ typedef struct st_rtc_time_capture { - rtc_time_t time; ///< Time structure - uint8_t channel; ///< Capture channel - rtc_time_capture_source_t source; ///< Trigger source - rtc_time_capture_noise_filter_t noise_filter; ///< Noise filter - rtc_time_capture_mode_t mode; ///< Capture mode + rtc_time_t time; ///< Time structure + uint8_t channel; ///< Capture channel + rtc_time_capture_source_t source; ///< Trigger source + rtc_time_capture_noise_filter_t noise_filter; ///< Noise filter + rtc_time_capture_mode_t mode; ///< Capture mode } rtc_time_capture_t; /** RTC Information Structure for information returned by infoGet() */ diff --git a/ra/fsp/inc/api/rm_comms_api.h b/ra/fsp/inc/api/rm_comms_api.h index f1f8e7a87..cb06a6b89 100644 --- a/ra/fsp/inc/api/rm_comms_api.h +++ b/ra/fsp/inc/api/rm_comms_api.h @@ -71,6 +71,7 @@ typedef struct st_rm_comms_write_read_params typedef struct st_rm_comms_callback_args { void const * p_context; + void * p_instance_args; rm_comms_event_t event; } rm_comms_callback_args_t; diff --git a/ra/fsp/inc/api/rm_zmod4xxx_api.h b/ra/fsp/inc/api/rm_zmod4xxx_api.h index 356b8c4f9..3f55f0757 100644 --- a/ra/fsp/inc/api/rm_zmod4xxx_api.h +++ b/ra/fsp/inc/api/rm_zmod4xxx_api.h @@ -135,6 +135,7 @@ typedef struct st_rm_zmod4xxx_oaq_1st_data typedef struct st_rm_zmod4xxx_oaq_2nd_data { float rmox[8]; ///< MOx resistance. + float temperature; ///< Temperature (degC) used for ambient compensation float ozone_concentration; ///< The ozone concentration in part-per-billion uint16_t fast_aqi; ///< 1-minute average of the Air Quality Index according to the EPA standard based on ozone uint16_t epa_aqi; ///< The Air Quality Index according to the EPA standard based on ozone @@ -167,6 +168,17 @@ typedef struct st_rm_zmod4xxx_pbaq_data uint8_t sample_id; ///< Sample ID. RRH46410 only. } rm_zmod4xxx_pbaq_data_t; +/** ZMOD4XXX NO2 O3 data structure */ +typedef struct st_rm_zmod4xxx_no2_o3_data +{ + float rmox[4]; ///< MOx resistance. + float temperature; ///< Temperature (degC) used for ambient compensation + float ozone_concentration; ///< O3_conc_ppb stands for the ozone concentration in part-per-billion + float no2_concentration; ///< NO2_conc_ppb stands for the NO2 concentration in part-per-billion + uint16_t fast_aqi; ///< FAST_AQI stands for a 1-minute average of the Air Quality Index according to the EPA standard based on ozone + uint16_t epa_aqi; ///< EPA_AQI stands for the Air Quality Index according to the EPA standard based on ozone. +} rm_zmod4xxx_no2_o3_data_t; + /** ZMOD4XXX configuration block */ typedef struct st_rm_zmod4xxx_cfg { @@ -298,6 +310,15 @@ typedef struct st_rm_zmod4xxx_api fsp_err_t (* pbaqDataCalculate)(rm_zmod4xxx_ctrl_t * const p_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, rm_zmod4xxx_pbaq_data_t * const p_zmod4xxx_data); + /** Calculate NO2 O3 values from ADC data. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_raw_data Pointer to raw data. + * @param[in] p_zmod4xxx_data Pointer to ZMOD4XXXX data structure. + */ + fsp_err_t (* no2O3DataCalculate)(rm_zmod4xxx_ctrl_t * const p_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data); + /** Set temperature and humidity. * * @param[in] p_ctrl Pointer to control structure. diff --git a/ra/fsp/inc/fsp_version.h b/ra/fsp/inc/fsp_version.h index c9206d27b..19dc9d42f 100644 --- a/ra/fsp/inc/fsp_version.h +++ b/ra/fsp/inc/fsp_version.h @@ -31,7 +31,7 @@ extern "C" { #define FSP_VERSION_MAJOR (5U) /** FSP pack minor version. */ - #define FSP_VERSION_MINOR (4U) + #define FSP_VERSION_MINOR (5U) /** FSP pack patch version. */ #define FSP_VERSION_PATCH (0U) @@ -40,10 +40,10 @@ extern "C" { #define FSP_VERSION_BUILD (0U) /** Public FSP version name. */ - #define FSP_VERSION_STRING ("5.4.0") + #define FSP_VERSION_STRING ("5.5.0") /** Unique FSP version ID. */ - #define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 5.4.0") + #define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 5.5.0") /********************************************************************************************************************** * Typedef definitions diff --git a/ra/fsp/inc/instances/r_adc.h b/ra/fsp/inc/instances/r_adc.h index c68451bc2..4c86648be 100644 --- a/ra/fsp/inc/instances/r_adc.h +++ b/ra/fsp/inc/instances/r_adc.h @@ -207,6 +207,7 @@ typedef enum e_adc_window_b_channel ADC_WINDOW_B_CHANNEL_28, ADC_WINDOW_B_CHANNEL_TEMPERATURE = 32, ADC_WINDOW_B_CHANNEL_VOLT = 33, + ADC_WINDOW_B_CHANNEL_NONE = 63, } adc_window_b_channel_t; /** ADC Window B comparison mode */ diff --git a/ra/fsp/inc/instances/r_ospi_b.h b/ra/fsp/inc/instances/r_ospi_b.h index c0fe74f58..adee0868a 100644 --- a/ra/fsp/inc/instances/r_ospi_b.h +++ b/ra/fsp/inc/instances/r_ospi_b.h @@ -153,10 +153,18 @@ typedef enum e_ospi_b_dotf_aes_key_type OSPI_B_DOTF_AES_KEY_TYPE_256 = 2U } ospi_b_dotf_aes_key_type_t; +/* OSPI DOTF key Type. */ +typedef enum e_ospi_b_dotf_key_format +{ + OSPI_B_DOTF_KEY_FORMAT_PLAINTEXT = 0U, + OSPI_B_DOTF_KEY_FORMAT_WRAPPED = 1U, +} ospi_b_dotf_key_format_t; + /* This structure is used to hold all the DOTF related configuration. */ typedef struct st_ospi_b_dotf_cfg { ospi_b_dotf_aes_key_type_t key_type; + ospi_b_dotf_key_format_t format; uint32_t * p_start_addr; uint32_t * p_end_addr; uint32_t * p_key; diff --git a/ra/fsp/inc/instances/r_sau_uart.h b/ra/fsp/inc/instances/r_sau_uart.h index 536ff2fcf..1f567e6be 100644 --- a/ra/fsp/inc/instances/r_sau_uart.h +++ b/ra/fsp/inc/instances/r_sau_uart.h @@ -43,13 +43,6 @@ typedef enum e_sau_operation_clock SAU_UART_OPERATION_CLOCK_CK1 = 1U, ///< Operating clock use CK1 } sau_operation_clock_t; -/** UART transfer mode selection definition */ -typedef enum e_sau_uart_transfer_mode -{ - SAU_UART_TRANSFER_MODE_SINGLE = 0U, ///< Single transfer mode - SAU_UART_TRANSFER_MODE_CONTINUOUS = 1U, ///< Continuous transfer mode -} sau_uart_transfer_mode_t; - /** UART data signal level definition */ typedef enum e_sau_uart_signal_level { @@ -68,10 +61,9 @@ typedef struct typedef struct st_sau_uart_extended_cfg { /* UART generic configuration */ - sau_uart_transfer_mode_t transfer_mode; ///< Select single transfer mode or continuous transfer mode - sau_uart_data_sequence_t sequence; ///< Transfer sequence (LSB or MSB) - sau_uart_signal_level_t signal_level; ///< Transfer data signal level (standard or inverted) - sau_uart_baudrate_setting_t * p_baudrate; ///< Baud rate setting (SPS and SDR value) + sau_uart_data_sequence_t sequence; ///< Transfer sequence (LSB or MSB) + sau_uart_signal_level_t signal_level; ///< Transfer data signal level (standard or inverted) + sau_uart_baudrate_setting_t * p_baudrate; ///< Baud rate setting (SPS and SDR value) } sau_uart_extended_cfg_t; /** UART instance control block. DO NOT INITIALIZE. */ diff --git a/ra/fsp/inc/instances/r_sci_uart.h b/ra/fsp/inc/instances/r_sci_uart.h index 4997acc3d..0bcb38223 100644 --- a/ra/fsp/inc/instances/r_sci_uart.h +++ b/ra/fsp/inc/instances/r_sci_uart.h @@ -164,6 +164,38 @@ typedef struct st_sci_uart_rs485_setting bsp_io_port_pin_t de_control_pin; ///< UART Driver Enable pin. } sci_uart_rs485_setting_t; +/** IrDA Enable/Disable. */ +typedef enum e_sci_uart_irda_enable +{ + SCI_UART_IRDA_DISABLED = 0, ///< IrDA disabled. + SCI_UART_IRDA_ENABLED = 1, ///< IrDA enabled. +} sci_uart_irda_enable_t; + +/** IrDA Polarity Switching. */ +typedef enum e_sci_uart_irda_polarity +{ + SCI_UART_IRDA_POLARITY_NORMAL = 0, ///< IrDA Tx/Rx polarity not inverted. + SCI_UART_IRDA_POLARITY_INVERTED = 1, ///< IrDA Tx/Rx polarity inverted. +} sci_uart_irda_polarity_t; + +/** Configuration settings for IrDA interface. */ +typedef struct st_sci_uart_irda_setting +{ + union + { + uint8_t ircr_bits; + + struct + { + uint8_t : 2; + uint8_t irrxinv : 1; ///< IRRXD Polarity Switching + uint8_t irtxinv : 1; ///< IRTXD Polarity Switching + uint8_t : 3; + uint8_t ire : 1; ///< Enable IrDA pulse encoding and decoding. + } ircr_bits_b; + }; +} sci_uart_irda_setting_t; + /** UART on SCI device Configuration */ typedef struct st_sci_uart_extended_cfg { @@ -175,6 +207,7 @@ typedef struct st_sci_uart_extended_cfg bsp_io_port_pin_t flow_control_pin; ///< UART Driver Enable pin sci_uart_flow_control_t flow_control; ///< CTS/RTS function of the SSn pin sci_uart_rs485_setting_t rs485_setting; ///< RS-485 settings. + sci_uart_irda_setting_t irda_setting; ///< IrDA settings } sci_uart_extended_cfg_t; /********************************************************************************************************************** diff --git a/ra/fsp/inc/instances/r_uarta.h b/ra/fsp/inc/instances/r_uarta.h index 93222488b..b4342735c 100644 --- a/ra/fsp/inc/instances/r_uarta.h +++ b/ra/fsp/inc/instances/r_uarta.h @@ -25,8 +25,8 @@ FSP_HEADER /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ - -#define UARTA_UTA0CK_SOSC_LOCO_SETTING (0x08U) +#define UARTA_UTAnCK_LOCO_SETTING (0x08U) // for LOCO or FSXP +#define UARTA_UTAnCK_SOSC_SETTING (0x09U) /********************************************************************************************************************** * Typedef definitions @@ -35,10 +35,12 @@ FSP_HEADER /** Enumeration for UARTA clock source */ typedef enum e_uarta_clock_source { - UARTA_CLOCK_SOURCE_SOSC_LOCO = 0U, ///< SOSC/LOCO - UARTA_CLOCK_SOURCE_MOSC = 1U, ///< MOSC - UARTA_CLOCK_SOURCE_HOCO = 2U, ///< HOCO - UARTA_CLOCK_SOURCE_MOCO = 3U, ///< MOCO + UARTA_CLOCK_SOURCE_SOSC_LOCO = 0U, ///< SOSC/LOCO + UARTA_CLOCK_SOURCE_LOCO = UARTA_CLOCK_SOURCE_SOSC_LOCO, ///< LOCO + UARTA_CLOCK_SOURCE_MOSC = 1U, ///< MOSC + UARTA_CLOCK_SOURCE_HOCO = 2U, ///< HOCO + UARTA_CLOCK_SOURCE_MOCO = 3U, ///< MOCO + UARTA_CLOCK_SOURCE_SOSC = 4U, ///< SOSC } uarta_clock_source_t; /** Enumeration for UARTA clock divider */ @@ -54,6 +56,13 @@ typedef enum e_uarta_clock_div UARTA_CLOCK_DIV_COUNT, ///< Total number of clock divider options. } uarta_clock_div_t; +/** Enabled/Disabled Clock output */ +typedef enum e_uarta_clock_out +{ + UARTA_CLOCK_OUTPUT_DISABLED = 0U, ///< Disables CLKAn output + UARTA_CLOCK_OUTPUT_ENABLED = 1U, ///< Enables CLKAn output +} uarta_clock_out_t; + /** Transmission/reception order configuration. */ typedef enum e_uarta_dir_bit { @@ -73,14 +82,14 @@ typedef struct st_uarta_baud_setting { union { - uint8_t uta0ck_clock; + uint8_t utanck_clock; struct { - uint8_t uta0ck : 4; ///< UARTA operation clock select (f_UTA0n) + uint8_t utanck : 4; ///< UARTA operation clock select (f_UTA0n) uint8_t utasel : 2; ///< fSEL clock select uint8_t : 2; - } uta0ck_clock_b; + } utanck_clock_b; }; uint8_t brgca; ///< Baud rate generator control setting uint16_t delay_time; ///< Delay time (us) required to enable TX at open @@ -91,6 +100,7 @@ typedef struct st_uarta_extended_cfg { uarta_dir_bit_t transfer_dir; ///< Transmission/reception order configuration uarta_alv_bit_t transfer_level; ///< Transmission/reception level configuration + uarta_clock_out_t clock_output; ///< Disable/Enable clock output uarta_baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate. } uarta_extended_cfg_t; @@ -113,6 +123,9 @@ typedef struct st_uarta_instance_ctrl /* Size of destination buffer pointer used for receiving data. */ uint32_t rx_dest_bytes; + /* Base register for this channel. */ + R_UARTA0_Type * p_reg; + /* Pointer to the configuration block. */ uart_cfg_t const * p_cfg; diff --git a/ra/fsp/inc/instances/rm_comms_smbus.h b/ra/fsp/inc/instances/rm_comms_smbus.h index 6f79095cb..9fedcab1d 100644 --- a/ra/fsp/inc/instances/rm_comms_smbus.h +++ b/ra/fsp/inc/instances/rm_comms_smbus.h @@ -38,6 +38,22 @@ FSP_HEADER * Typedef definitions **********************************************************************************************************************/ +/** SMBus specific event */ +typedef enum e_rm_comms_smbus_event +{ + RM_COMMS_SMBUS_NO_ERROR = 0, ///< SMBus transmission complete without any error. + RM_COMMS_SMBUS_MISC_ERROR, ///< Dependency modules failed. + RM_COMMS_SMBUS_DATA_CORRUPT, ///< PEC byte is incorrect. + RM_COMMS_SMBUS_SEXT_TIMEOUT, ///< Total transmission time exceeded 25 ms. + RM_COMMS_SMBUS_MEXT_TIMEOUT, ///< Transmission time between each event exceeded 10 ms. +} rm_comms_smbus_event_t; + +/** SMBus error structure */ +typedef struct rm_comms_smbus_error_t +{ + rm_comms_smbus_event_t smbus_event; +} rm_comms_smbus_error_t; + /********************************************************************************************************************** * Exported global variables **********************************************************************************************************************/ @@ -69,6 +85,7 @@ typedef struct st_rm_comms_smbus_instance_ctrl uint32_t open; ///< Open flag. rm_comms_i2c_instance_ctrl_t * p_comms_i2c_ctrl; ///< Control block of rm_comms_i2c + rm_comms_smbus_error_t * p_smbus_error; ///< SMBus specific error code const void * p_context; } rm_comms_smbus_instance_ctrl_t; diff --git a/ra/fsp/inc/instances/rm_littlefs_flash.h b/ra/fsp/inc/instances/rm_littlefs_flash.h index 55eff8140..91d4dc9b5 100644 --- a/ra/fsp/inc/instances/rm_littlefs_flash.h +++ b/ra/fsp/inc/instances/rm_littlefs_flash.h @@ -13,7 +13,7 @@ #include "rm_littlefs_api.h" #include "r_flash_api.h" #include "lfs.h" -#if LFS_THREAD_SAFE +#ifdef LFS_THREADSAFE #include "FreeRTOS.h" #include "semphr.h" @@ -45,7 +45,7 @@ typedef struct st_rm_littlefs_flash_instance_ctrl { uint32_t open; rm_littlefs_cfg_t const * p_cfg; -#if LFS_THREAD_SAFE +#ifdef LFS_THREADSAFE SemaphoreHandle_t xSemaphore; StaticSemaphore_t xMutexBuffer; #endif diff --git a/ra/fsp/inc/instances/rm_littlefs_spi_flash.h b/ra/fsp/inc/instances/rm_littlefs_spi_flash.h new file mode 100644 index 000000000..a30487f10 --- /dev/null +++ b/ra/fsp/inc/instances/rm_littlefs_spi_flash.h @@ -0,0 +1,120 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef RM_LITTLEFS_SPI_FLASH_H +#define RM_LITTLEFS_SPI_FLASH_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "rm_littlefs_api.h" +#include "r_spi_flash_api.h" +#include "lfs.h" +#include "rm_littlefs_spi_flash_cfg.h" +#ifdef LFS_THREADSAFE + #include "FreeRTOS.h" + #include "semphr.h" + +#endif + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup RM_LITTLEFS_SPI_FLASH + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Options for the callback events. */ +typedef enum e_rm_littlefs_spi_flash_event +{ + RM_LITTLEFS_SPI_FLASH_EVENT_BUSY, ///< Pending operation, user can define their own wait functionality. +} rm_littlefs_spi_flash_event_t; + +/** RM_LITTLEFS callback arguments definitions */ +typedef struct st_rm_littlefs_spi_flash_callback_args +{ + rm_littlefs_spi_flash_event_t event; ///< LevelX NOR driver callback event + void const * p_context; ///< Placeholder for user data +} rm_littlefs_spi_flash_callback_args_t; + +/** User configuration structure, used in open function */ +typedef struct st_rm_littlefs_spi_flash_cfg +{ + spi_flash_instance_t const * p_lower_lvl; ///< Pointer to a spi flash instance + uint32_t base_address; ///< Base address of memory mapped region. + uint32_t address_offset; ///< Offset to use subset of available flash size if desired. + uint32_t size; ///< Size of the partitioned region. + uint32_t poll_status_count; ///< Number of times to poll for operation complete status before returning an error. + void const * p_context; ///< Placeholder for user data. Passed to the user callback. + void (* p_callback)(rm_littlefs_spi_flash_callback_args_t * p_args); ///< Callback function +} rm_littlefs_spi_flash_cfg_t; + +/** Instance control block. This is private to the FSP and should not be used or modified by the application. */ +typedef struct st_rm_littlefs_spi_flash_instance_ctrl +{ + uint32_t open; + rm_littlefs_cfg_t const * p_cfg; + uint32_t start_address; ///< Start address of partition to use within memory mapped region. + uint32_t size; ///< Size of partition to use within memory mapped region. +#ifdef LFS_THREADSAFE + SemaphoreHandle_t xSemaphore; + StaticSemaphore_t xMutexBuffer; +#endif +} rm_littlefs_spi_flash_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const rm_littlefs_api_t g_rm_littlefs_on_flash; + +/** @endcond */ + +/********************************************************************************************************************** + * Function Prototypes + **********************************************************************************************************************/ +fsp_err_t RM_LITTLEFS_SPI_FLASH_Open(rm_littlefs_ctrl_t * const p_ctrl, rm_littlefs_cfg_t const * const p_cfg); + +fsp_err_t RM_LITTLEFS_SPI_FLASH_Close(rm_littlefs_ctrl_t * const p_ctrl); + +int rm_littlefs_spi_flash_read(const struct lfs_config * c, + lfs_block_t block, + lfs_off_t off, + void * buffer, + lfs_size_t size); + +int rm_littlefs_spi_flash_write(const struct lfs_config * c, + lfs_block_t block, + lfs_off_t off, + const void * buffer, + lfs_size_t size); + +int rm_littlefs_spi_flash_erase(const struct lfs_config * c, lfs_block_t block); + +int rm_littlefs_spi_flash_lock(const struct lfs_config * c); + +int rm_littlefs_spi_flash_unlock(const struct lfs_config * c); + +int rm_littlefs_spi_flash_sync(const struct lfs_config * c); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // RM_LITTLEFS_SPI_FLASH_H + +/*******************************************************************************************************************//** + * @} (end addtogroup RM_LITTLEFS) + **********************************************************************************************************************/ diff --git a/ra/fsp/inc/instances/rm_motor_120_driver.h b/ra/fsp/inc/instances/rm_motor_120_driver.h index f01550180..1e1278295 100644 --- a/ra/fsp/inc/instances/rm_motor_120_driver.h +++ b/ra/fsp/inc/instances/rm_motor_120_driver.h @@ -108,7 +108,8 @@ typedef struct st_motor_120_driver_extended_cfg bsp_io_port_pin_t port_wn; ///< PWM output port WN uint32_t u4_pwm_timer_freq; ///< PWM timer frequency (MHz) - uint32_t u4_pwm_carrier_freq; ///< PWM carrier frequency (kHz) + float u4_pwm_carrier_freq; ///< PWM carrier frequency (kHz) [DEPRECATED] + float pwm_carrier_freq; ///< PWM carrier frequency (kHz) uint32_t u4_deadtime; ///< PWM deadtime (usec) float f_current_range; ///< A/D current measure range (max current) (A) diff --git a/ra/fsp/inc/instances/rm_motor_driver.h b/ra/fsp/inc/instances/rm_motor_driver.h index 6998ce954..16d7c5870 100644 --- a/ra/fsp/inc/instances/rm_motor_driver.h +++ b/ra/fsp/inc/instances/rm_motor_driver.h @@ -84,7 +84,8 @@ typedef struct st_motor_driver_extended_shared_cfg typedef struct st_motor_driver_extended_cfg { uint16_t u2_pwm_timer_freq; ///< PWM timer frequency [MHz] - uint16_t u2_pwm_carrier_freq; ///< PWM carrier frequency [kHz] + float u2_pwm_carrier_freq; ///< PWM carrier frequency [kHz] [DEPRECATED] + float pwm_carrier_freq; ///< PWM carrier frequency [kHz] uint16_t u2_deadtime; ///< PWM deadtime [usec] float f_current_range; ///< A/D current measure range (max current) [A] diff --git a/ra/fsp/inc/instances/rm_zmod4xxx.h b/ra/fsp/inc/instances/rm_zmod4xxx.h index 08c15e58a..6eb446445 100644 --- a/ra/fsp/inc/instances/rm_zmod4xxx.h +++ b/ra/fsp/inc/instances/rm_zmod4xxx.h @@ -55,6 +55,7 @@ typedef enum e_rm_zmod4xxx_lib_type RM_ZMOD4410_LIB_TYPE_PBAQ, RM_ZMOD4510_LIB_TYPE_OAQ_1ST_GEN, RM_ZMOD4510_LIB_TYPE_OAQ_2ND_GEN, + RM_ZMOD4510_LIB_TYPE_NO2_O3, RM_ZMOD4450_LIB_TYPE_RAQ, } rm_zmod4xxx_lib_type_t; @@ -158,6 +159,9 @@ fsp_err_t RM_ZMOD4XXX_RelIaqDataCalculate(rm_zmod4xxx_ctrl_t * const p_a fsp_err_t RM_ZMOD4XXX_PbaqDataCalculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, rm_zmod4xxx_pbaq_data_t * const p_zmod4xxx_data); +fsp_err_t RM_ZMOD4XXX_No2O3DataCalculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data); fsp_err_t RM_ZMOD4XXX_Close(rm_zmod4xxx_ctrl_t * const p_api_ctrl); #if defined(__CCRX__) || defined(__ICCRX__) || defined(__RX__) diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA0E107.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA0E107.h index 8793c43b2..72b4b57d6 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA0E107.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA0E107.h @@ -4462,21 +4462,21 @@ typedef struct /*!< (@ 0x400D1000) R_TRNG Structure } R_TRNG_Type; /*!< Size = 4 (0x4) */ /* =========================================================================================================================== */ -/* ================ R_UARTA ================ */ +/* ================ R_UARTA0 ================ */ /* =========================================================================================================================== */ /** - * @brief Serial Interface UARTA (R_UARTA) + * @brief Serial Interface UARTA (R_UARTA0) */ -typedef struct /*!< (@ 0x400A3400) R_UARTA Structure */ +typedef struct /*!< (@ 0x400A3400) R_UARTA0 Structure */ { - __IOM uint8_t TXBA0; /*!< (@ 0x00000000) Transmit Buffer Register 0 */ - __IM uint8_t RXBA0; /*!< (@ 0x00000001) Receive Buffer Register 0 */ + __IOM uint8_t TXBAn; /*!< (@ 0x00000000) Transmit Buffer Register 0 */ + __IM uint8_t RXBAn; /*!< (@ 0x00000001) Receive Buffer Register 0 */ union { - __IOM uint8_t ASIMA00; /*!< (@ 0x00000002) Operation Mode Setting Register 00 */ + __IOM uint8_t ASIMAn0; /*!< (@ 0x00000002) Operation Mode Setting Register 00 */ struct { @@ -4486,12 +4486,12 @@ typedef struct /*!< (@ 0x400A3400) R_UARTA Structure __IOM uint8_t RXEA : 1; /*!< [5..5] Reception Enable */ __IOM uint8_t TXEA : 1; /*!< [6..6] Transmission Enable */ __IOM uint8_t EN : 1; /*!< [7..7] UART Operation Enable */ - } ASIMA00_b; + } ASIMAn0_b; }; union { - __IOM uint8_t ASIMA01; /*!< (@ 0x00000003) Operation Mode Setting Register 01 */ + __IOM uint8_t ASIMAn1; /*!< (@ 0x00000003) Operation Mode Setting Register 01 */ struct { @@ -4501,13 +4501,13 @@ typedef struct /*!< (@ 0x400A3400) R_UARTA Structure __IOM uint8_t CL : 2; /*!< [4..3] Transmission and Reception Character Length Setting */ __IOM uint8_t PS : 2; /*!< [6..5] Transmission and Reception Parity Bit Setting */ uint8_t : 1; - } ASIMA01_b; + } ASIMAn1_b; }; - __IOM uint8_t BRGCA0; /*!< (@ 0x00000004) Baud Rate Generator Control Register 0 */ + __IOM uint8_t BRGCAn; /*!< (@ 0x00000004) Baud Rate Generator Control Register 0 */ union { - __IM uint8_t ASISA0; /*!< (@ 0x00000005) Status Register 0 */ + __IM uint8_t ASISAn; /*!< (@ 0x00000005) Status Register 0 */ struct { @@ -4518,12 +4518,12 @@ typedef struct /*!< (@ 0x400A3400) R_UARTA Structure __IM uint8_t TXSFA : 1; /*!< [4..4] Transmit Shift Register Data Flag */ __IM uint8_t TXBFA : 1; /*!< [5..5] Transmit Buffer Data Flag */ uint8_t : 2; - } ASISA0_b; + } ASISAn_b; }; union { - __IOM uint8_t ASCTA0; /*!< (@ 0x00000006) Status Clear Trigger Register 0 */ + __IOM uint8_t ASCTAn; /*!< (@ 0x00000006) Status Clear Trigger Register 0 */ struct { @@ -4531,22 +4531,33 @@ typedef struct /*!< (@ 0x400A3400) R_UARTA Structure __IOM uint8_t FECTA : 1; /*!< [1..1] Framing Error Flag Clear Trigger */ __IOM uint8_t PECTA : 1; /*!< [2..2] Parity Error Flag Clear Trigger */ uint8_t : 5; - } ASCTA0_b; + } ASCTAn_b; }; - __IM uint8_t RESERVED[249]; +} R_UARTA0_Type; /*!< Size = 7 (0x7) */ +/* =========================================================================================================================== */ +/* ================ R_UARTA_CK ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Interface UARTA Clock (R_UARTA_CK) + */ + +typedef struct /*!< (@ 0x400A3500) R_UARTA_CK Structure */ +{ union { - __IOM uint8_t UTA0CK; /*!< (@ 0x00000100) UARTA Clock Select Register 0 */ + __IOM uint8_t UTAnCK[2]; /*!< (@ 0x00000000) UARTA Clock Select Register */ struct { - __IOM uint8_t CK : 4; /*!< [3..0] UARTA0 Operation Clock Select (fUTA0) */ + __IOM uint8_t CK : 4; /*!< [3..0] UARTAn Operation Clock Select (fUTAn) */ __IOM uint8_t SEL : 2; /*!< [5..4] fSEL Clock Select */ - uint8_t : 2; - } UTA0CK_b; + uint8_t : 1; + __IOM uint8_t EN : 1; /*!< [7..7] UARTAn clock output function enable */ + } UTAnCK_b[2]; }; -} R_UARTA_Type; /*!< Size = 257 (0x101) */ +} R_UARTA_CK_Type; /*!< Size = 2 (0x2) */ /* =========================================================================================================================== */ /* ================ R_PCLBUZ ================ */ @@ -4763,36 +4774,37 @@ typedef struct /*!< (@ 0x400A2C00) R_RTC_C Structure * @{ */ - #define R_ADC_D_BASE 0x400A1800UL - #define R_BUS_BASE 0x40003000UL - #define R_CRC_BASE 0x40074000UL - #define R_DEBUG_BASE 0x4001B000UL - #define R_DTC_BASE 0x40005400UL - #define R_ELC_BASE 0x40041000UL - #define R_FACI_LP_BASE 0x407EC000UL - #define R_ICU_BASE 0x40006000UL - #define R_IICA_BASE 0x400A3000UL - #define R_IWDT_BASE 0x40044400UL - #define R_MSTP_BASE (0x40047000UL - 4UL) /* MSTPCRA is not located in R_MSTP so the base address must be moved so that MSTPCRB is located at 0x40047000. */ - #define R_PORT0_BASE 0x400A0000UL - #define R_PORT1_BASE 0x400A0020UL - #define R_PORT2_BASE 0x400A0040UL - #define R_PORT3_BASE 0x400A0060UL - #define R_PORT4_BASE 0x400A0080UL - #define R_PORT9_BASE 0x400A0120UL - #define R_PORGA_BASE 0x400A1000UL - #define R_PFS_BASE 0x400A0200UL - #define R_PMISC_BASE 0x400A0340UL - #define R_SAU0_BASE 0x400A2000UL - #define R_SAU1_BASE 0x400A2200UL - #define R_SRAM_BASE 0x40002000UL - #define R_SYSTEM_BASE 0x4001E000UL - #define R_TAU_BASE 0x400A2600UL - #define R_TML_BASE 0x400A3800UL - #define R_TRNG_BASE 0x400D1000UL - #define R_UARTA_BASE 0x400A3400UL - #define R_PCLBUZ_BASE 0x400A3B00UL - #define R_RTC_C_BASE 0x400A2C00UL + #define R_ADC_D_BASE 0x400A1800UL + #define R_BUS_BASE 0x40003000UL + #define R_CRC_BASE 0x40074000UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40041000UL + #define R_FACI_LP_BASE 0x407EC000UL + #define R_ICU_BASE 0x40006000UL + #define R_IICA_BASE 0x400A3000UL + #define R_IWDT_BASE 0x40044400UL + #define R_MSTP_BASE (0x40047000UL - 4UL) /* MSTPCRA is not located in R_MSTP so the base address must be moved so that MSTPCRB is located at 0x40047000. */ + #define R_PORT0_BASE 0x400A0000UL + #define R_PORT1_BASE 0x400A0020UL + #define R_PORT2_BASE 0x400A0040UL + #define R_PORT3_BASE 0x400A0060UL + #define R_PORT4_BASE 0x400A0080UL + #define R_PORT9_BASE 0x400A0120UL + #define R_PORGA_BASE 0x400A1000UL + #define R_PFS_BASE 0x400A0200UL + #define R_PMISC_BASE 0x400A0340UL + #define R_SAU0_BASE 0x400A2000UL + #define R_SAU1_BASE 0x400A2200UL + #define R_SRAM_BASE 0x40002000UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_TAU_BASE 0x400A2600UL + #define R_TML_BASE 0x400A3800UL + #define R_TRNG_BASE 0x400D1000UL + #define R_UARTA0_BASE 0x400A3400UL + #define R_UARTA_CK_BASE 0x400A3500UL + #define R_PCLBUZ_BASE 0x400A3B00UL + #define R_RTC_C_BASE 0x400A2C00UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -4804,36 +4816,37 @@ typedef struct /*!< (@ 0x400A2C00) R_RTC_C Structure * @{ */ - #define R_ADC_D ((R_ADC_D_Type *) R_ADC_D_BASE) - #define R_BUS ((R_BUS_Type *) R_BUS_BASE) - #define R_CRC ((R_CRC_Type *) R_CRC_BASE) - #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) - #define R_DTC ((R_DTC_Type *) R_DTC_BASE) - #define R_ELC ((R_ELC_Type *) R_ELC_BASE) - #define R_FACI_LP ((R_FACI_LP_Type *) R_FACI_LP_BASE) - #define R_ICU ((R_ICU_Type *) R_ICU_BASE) - #define R_IICA ((R_IICA_Type *) R_IICA_BASE) - #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) - #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) - #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) - #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) - #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) - #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) - #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) - #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) - #define R_PORGA ((R_PORGA_Type *) R_PORGA_BASE) - #define R_PFS ((R_PFS_Type *) R_PFS_BASE) - #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) - #define R_SAU0 ((R_SAU0_Type *) R_SAU0_BASE) - #define R_SAU1 ((R_SAU0_Type *) R_SAU1_BASE) - #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) - #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) - #define R_TAU ((R_TAU_Type *) R_TAU_BASE) - #define R_TML ((R_TML_Type *) R_TML_BASE) - #define R_TRNG ((R_TRNG_Type *) R_TRNG_BASE) - #define R_UARTA ((R_UARTA_Type *) R_UARTA_BASE) - #define R_PCLBUZ ((R_PCLBUZ_Type *) R_PCLBUZ_BASE) - #define R_RTC_C ((R_RTC_C_Type *) R_RTC_C_BASE) + #define R_ADC_D ((R_ADC_D_Type *) R_ADC_D_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_FACI_LP ((R_FACI_LP_Type *) R_FACI_LP_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IICA ((R_IICA_Type *) R_IICA_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORGA ((R_PORGA_Type *) R_PORGA_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_SAU0 ((R_SAU0_Type *) R_SAU0_BASE) + #define R_SAU1 ((R_SAU0_Type *) R_SAU1_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TAU ((R_TAU_Type *) R_TAU_BASE) + #define R_TML ((R_TML_Type *) R_TML_BASE) + #define R_TRNG ((R_TRNG_Type *) R_TRNG_BASE) + #define R_UARTA0 ((R_UARTA0_Type *) R_UARTA0_BASE) + #define R_UARTA_CK ((R_UARTA_CK_Type *) R_UARTA_CK_BASE) + #define R_PCLBUZ ((R_PCLBUZ_Type *) R_PCLBUZ_BASE) + #define R_RTC_C ((R_RTC_C_Type *) R_RTC_C_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -6445,57 +6458,64 @@ typedef struct /*!< (@ 0x400A2C00) R_RTC_C Structure #define R_TRNG_TRNGSCR1_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ -/* ================ R_UARTA ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= TXBA0 ========================================================= */ -/* ========================================================= RXBA0 ========================================================= */ -/* ======================================================== ASIMA00 ======================================================== */ - #define R_UARTA_ASIMA00_ISRMA_Pos (0UL) /*!< ISRMA (Bit 0) */ - #define R_UARTA_ASIMA00_ISRMA_Msk (0x1UL) /*!< ISRMA (Bitfield-Mask: 0x01) */ - #define R_UARTA_ASIMA00_ISSMA_Pos (1UL) /*!< ISSMA (Bit 1) */ - #define R_UARTA_ASIMA00_ISSMA_Msk (0x2UL) /*!< ISSMA (Bitfield-Mask: 0x01) */ - #define R_UARTA_ASIMA00_RXEA_Pos (5UL) /*!< RXEA (Bit 5) */ - #define R_UARTA_ASIMA00_RXEA_Msk (0x20UL) /*!< RXEA (Bitfield-Mask: 0x01) */ - #define R_UARTA_ASIMA00_TXEA_Pos (6UL) /*!< TXEA (Bit 6) */ - #define R_UARTA_ASIMA00_TXEA_Msk (0x40UL) /*!< TXEA (Bitfield-Mask: 0x01) */ - #define R_UARTA_ASIMA00_EN_Pos (7UL) /*!< EN (Bit 7) */ - #define R_UARTA_ASIMA00_EN_Msk (0x80UL) /*!< EN (Bitfield-Mask: 0x01) */ -/* ======================================================== ASIMA01 ======================================================== */ - #define R_UARTA_ASIMA01_ALV_Pos (0UL) /*!< ALV (Bit 0) */ - #define R_UARTA_ASIMA01_ALV_Msk (0x1UL) /*!< ALV (Bitfield-Mask: 0x01) */ - #define R_UARTA_ASIMA01_DIR_Pos (1UL) /*!< DIR (Bit 1) */ - #define R_UARTA_ASIMA01_DIR_Msk (0x2UL) /*!< DIR (Bitfield-Mask: 0x01) */ - #define R_UARTA_ASIMA01_SL_Pos (2UL) /*!< SL (Bit 2) */ - #define R_UARTA_ASIMA01_SL_Msk (0x4UL) /*!< SL (Bitfield-Mask: 0x01) */ - #define R_UARTA_ASIMA01_CL_Pos (3UL) /*!< CL (Bit 3) */ - #define R_UARTA_ASIMA01_CL_Msk (0x18UL) /*!< CL (Bitfield-Mask: 0x03) */ - #define R_UARTA_ASIMA01_PS_Pos (5UL) /*!< PS (Bit 5) */ - #define R_UARTA_ASIMA01_PS_Msk (0x60UL) /*!< PS (Bitfield-Mask: 0x03) */ -/* ======================================================== BRGCA0 ========================================================= */ -/* ======================================================== ASISA0 ========================================================= */ - #define R_UARTA_ASISA0_OVEA_Pos (0UL) /*!< OVEA (Bit 0) */ - #define R_UARTA_ASISA0_OVEA_Msk (0x1UL) /*!< OVEA (Bitfield-Mask: 0x01) */ - #define R_UARTA_ASISA0_FEA_Pos (1UL) /*!< FEA (Bit 1) */ - #define R_UARTA_ASISA0_FEA_Msk (0x2UL) /*!< FEA (Bitfield-Mask: 0x01) */ - #define R_UARTA_ASISA0_PEA_Pos (2UL) /*!< PEA (Bit 2) */ - #define R_UARTA_ASISA0_PEA_Msk (0x4UL) /*!< PEA (Bitfield-Mask: 0x01) */ - #define R_UARTA_ASISA0_TXSFA_Pos (4UL) /*!< TXSFA (Bit 4) */ - #define R_UARTA_ASISA0_TXSFA_Msk (0x10UL) /*!< TXSFA (Bitfield-Mask: 0x01) */ - #define R_UARTA_ASISA0_TXBFA_Pos (5UL) /*!< TXBFA (Bit 5) */ - #define R_UARTA_ASISA0_TXBFA_Msk (0x20UL) /*!< TXBFA (Bitfield-Mask: 0x01) */ -/* ======================================================== ASCTA0 ========================================================= */ - #define R_UARTA_ASCTA0_OVECTA_Pos (0UL) /*!< OVECTA (Bit 0) */ - #define R_UARTA_ASCTA0_OVECTA_Msk (0x1UL) /*!< OVECTA (Bitfield-Mask: 0x01) */ - #define R_UARTA_ASCTA0_FECTA_Pos (1UL) /*!< FECTA (Bit 1) */ - #define R_UARTA_ASCTA0_FECTA_Msk (0x2UL) /*!< FECTA (Bitfield-Mask: 0x01) */ - #define R_UARTA_ASCTA0_PECTA_Pos (2UL) /*!< PECTA (Bit 2) */ - #define R_UARTA_ASCTA0_PECTA_Msk (0x4UL) /*!< PECTA (Bitfield-Mask: 0x01) */ -/* ======================================================== UTA0CK ========================================================= */ - #define R_UARTA_UTA0CK_CK_Pos (0UL) /*!< CK (Bit 0) */ - #define R_UARTA_UTA0CK_CK_Msk (0xfUL) /*!< CK (Bitfield-Mask: 0x0f) */ - #define R_UARTA_UTA0CK_SEL_Pos (4UL) /*!< SEL (Bit 4) */ - #define R_UARTA_UTA0CK_SEL_Msk (0x30UL) /*!< SEL (Bitfield-Mask: 0x03) */ +/* ================ R_UARTA0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TXBAn ========================================================= */ +/* ========================================================= RXBAn ========================================================= */ +/* ======================================================== ASIMAn0 ======================================================== */ + #define R_UARTA0_ASIMAn0_ISRMA_Pos (0UL) /*!< ISRMA (Bit 0) */ + #define R_UARTA0_ASIMAn0_ISRMA_Msk (0x1UL) /*!< ISRMA (Bitfield-Mask: 0x01) */ + #define R_UARTA0_ASIMAn0_ISSMA_Pos (1UL) /*!< ISSMA (Bit 1) */ + #define R_UARTA0_ASIMAn0_ISSMA_Msk (0x2UL) /*!< ISSMA (Bitfield-Mask: 0x01) */ + #define R_UARTA0_ASIMAn0_RXEA_Pos (5UL) /*!< RXEA (Bit 5) */ + #define R_UARTA0_ASIMAn0_RXEA_Msk (0x20UL) /*!< RXEA (Bitfield-Mask: 0x01) */ + #define R_UARTA0_ASIMAn0_TXEA_Pos (6UL) /*!< TXEA (Bit 6) */ + #define R_UARTA0_ASIMAn0_TXEA_Msk (0x40UL) /*!< TXEA (Bitfield-Mask: 0x01) */ + #define R_UARTA0_ASIMAn0_EN_Pos (7UL) /*!< EN (Bit 7) */ + #define R_UARTA0_ASIMAn0_EN_Msk (0x80UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ======================================================== ASIMAn1 ======================================================== */ + #define R_UARTA0_ASIMAn1_ALV_Pos (0UL) /*!< ALV (Bit 0) */ + #define R_UARTA0_ASIMAn1_ALV_Msk (0x1UL) /*!< ALV (Bitfield-Mask: 0x01) */ + #define R_UARTA0_ASIMAn1_DIR_Pos (1UL) /*!< DIR (Bit 1) */ + #define R_UARTA0_ASIMAn1_DIR_Msk (0x2UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_UARTA0_ASIMAn1_SL_Pos (2UL) /*!< SL (Bit 2) */ + #define R_UARTA0_ASIMAn1_SL_Msk (0x4UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_UARTA0_ASIMAn1_CL_Pos (3UL) /*!< CL (Bit 3) */ + #define R_UARTA0_ASIMAn1_CL_Msk (0x18UL) /*!< CL (Bitfield-Mask: 0x03) */ + #define R_UARTA0_ASIMAn1_PS_Pos (5UL) /*!< PS (Bit 5) */ + #define R_UARTA0_ASIMAn1_PS_Msk (0x60UL) /*!< PS (Bitfield-Mask: 0x03) */ +/* ======================================================== BRGCAn ========================================================= */ +/* ======================================================== ASISAn ========================================================= */ + #define R_UARTA0_ASISAn_OVEA_Pos (0UL) /*!< OVEA (Bit 0) */ + #define R_UARTA0_ASISAn_OVEA_Msk (0x1UL) /*!< OVEA (Bitfield-Mask: 0x01) */ + #define R_UARTA0_ASISAn_FEA_Pos (1UL) /*!< FEA (Bit 1) */ + #define R_UARTA0_ASISAn_FEA_Msk (0x2UL) /*!< FEA (Bitfield-Mask: 0x01) */ + #define R_UARTA0_ASISAn_PEA_Pos (2UL) /*!< PEA (Bit 2) */ + #define R_UARTA0_ASISAn_PEA_Msk (0x4UL) /*!< PEA (Bitfield-Mask: 0x01) */ + #define R_UARTA0_ASISAn_TXSFA_Pos (4UL) /*!< TXSFA (Bit 4) */ + #define R_UARTA0_ASISAn_TXSFA_Msk (0x10UL) /*!< TXSFA (Bitfield-Mask: 0x01) */ + #define R_UARTA0_ASISAn_TXBFA_Pos (5UL) /*!< TXBFA (Bit 5) */ + #define R_UARTA0_ASISAn_TXBFA_Msk (0x20UL) /*!< TXBFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ASCTAn ========================================================= */ + #define R_UARTA0_ASCTAn_OVECTA_Pos (0UL) /*!< OVECTA (Bit 0) */ + #define R_UARTA0_ASCTAn_OVECTA_Msk (0x1UL) /*!< OVECTA (Bitfield-Mask: 0x01) */ + #define R_UARTA0_ASCTAn_FECTA_Pos (1UL) /*!< FECTA (Bit 1) */ + #define R_UARTA0_ASCTAn_FECTA_Msk (0x2UL) /*!< FECTA (Bitfield-Mask: 0x01) */ + #define R_UARTA0_ASCTAn_PECTA_Pos (2UL) /*!< PECTA (Bit 2) */ + #define R_UARTA0_ASCTAn_PECTA_Msk (0x4UL) /*!< PECTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_UARTA_CK ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== UTAnCK ========================================================= */ + #define R_UARTA_CK_UTAnCK_CK_Pos (0UL) /*!< CK (Bit 0) */ + #define R_UARTA_CK_UTAnCK_CK_Msk (0xfUL) /*!< CK (Bitfield-Mask: 0x0f) */ + #define R_UARTA_CK_UTAnCK_SEL_Pos (4UL) /*!< SEL (Bit 4) */ + #define R_UARTA_CK_UTAnCK_SEL_Msk (0x30UL) /*!< SEL (Bitfield-Mask: 0x03) */ + #define R_UARTA_CK_UTAnCK_EN_Pos (7UL) /*!< EN (Bit 7) */ + #define R_UARTA_CK_UTAnCK_EN_Msk (0x80UL) /*!< EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_PCLBUZ ================ */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h index 579766b69..090f68741 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h @@ -1962,7 +1962,31 @@ typedef struct /*!< (@ 0x40085000) R_ACMPHS0 Structure __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ } CPIOC_b; }; -} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ + __IM uint8_t RESERVED4[47]; + + union + { + __IOM uint8_t CPINTCTL; /*!< (@ 0x00000040) Comparator Interrupt Control Register */ + + struct + { + __IOM uint8_t MSKE : 1; /*!< [0..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 7; + } CPINTCTL_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t CPMSKCTL; /*!< (@ 0x00000044) Comparator Interrupt Mask Control Register */ + + struct + { + __IOM uint8_t MSKSEL : 3; /*!< [2..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 5; + } CPMSKCTL_b; + }; +} R_ACMPHS0_Type; /*!< Size = 69 (0x45) */ /* =========================================================================================================================== */ /* ================ R_ACMPLP ================ */ @@ -2311,7 +2335,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -2324,7 +2348,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -6115,7 +6139,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -6162,7 +6187,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -6173,7 +6199,10 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -6190,24 +6219,26 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -6251,12 +6282,24 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -6733,7 +6776,57 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -12675,7 +12768,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * data. */ uint16_t : 1; __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ } CFIFOCTR_b; }; @@ -12695,7 +12788,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D0FIFOSEL_b; }; @@ -12729,7 +12822,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D1FIFOSEL_b; }; @@ -13004,14 +13097,13 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure union { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ struct { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; + uint16_t : 15; __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; + } DVCHGR_b; }; union @@ -13024,8 +13116,8 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * the USB address assigned by the host when the USBHS processed * the SET_ADDRESS request successfully. */ uint16_t : 1; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; } USBADDR_b; }; __IM uint16_t RESERVED9; @@ -13796,6 +13888,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_AGTX7_BASE 0x40084700UL #define R_AGTX8_BASE 0x40084800UL #define R_AGTX9_BASE 0x40084900UL + #define R_WDT1_BASE 0x40044300UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -13909,6 +14002,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -14697,32 +14791,38 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== CMPCTL ========================================================= */ - #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ - #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ - #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ - #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ - #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ - #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ - #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ - #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ - #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ /* ======================================================== CMPSEL0 ======================================================== */ - #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ - #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ /* ======================================================== CMPSEL1 ======================================================== */ - #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ - #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ /* ======================================================== CMPMON ========================================================= */ - #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ - #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ /* ========================================================= CPIOC ========================================================= */ - #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ - #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ - #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPINTCTL ======================================================== */ + #define R_ACMPHS0_CPINTCTL_MSKE_Pos (0UL) /*!< MSKE (Bit 0) */ + #define R_ACMPHS0_CPINTCTL_MSKE_Msk (0x1UL) /*!< MSKE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPMSKCTL ======================================================== */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Pos (0UL) /*!< MSKSEL (Bit 0) */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Msk (0x7UL) /*!< MSKSEL (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_ACMPLP ================ */ @@ -16468,6 +16568,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -16491,6 +16593,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -16530,9 +16634,15 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -16607,7 +16717,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -16644,8 +16760,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -16831,6 +16945,24 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ @@ -19638,14 +19770,12 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== UFRMNUM ======================================================== */ - #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ /* ======================================================== USBADDR ======================================================== */ #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ /* ======================================================== USBREQ ========================================================= */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A2AD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A2AD.h index 9d3099773..edc0c3273 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A2AD.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A2AD.h @@ -2224,7 +2224,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -2237,7 +2237,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -5037,7 +5037,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -5084,7 +5085,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -5095,7 +5097,10 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -5112,24 +5117,26 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -5173,12 +5180,24 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -5655,7 +5674,57 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -12918,6 +12987,7 @@ typedef struct /*!< (@ 0x4009C000) R_SDADC_B Structure #define R_IRTC_BASE 0x40044000UL #define R_MACL_BASE 0x400A0000UL #define R_SDADC_B_BASE 0x4009C000UL + #define R_WDT1_BASE 0x40044300UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -13019,6 +13089,7 @@ typedef struct /*!< (@ 0x4009C000) R_SDADC_B Structure #define R_IRTC ((R_IRTC_Type *) R_IRTC_BASE) #define R_MACL ((R_MACL_Type *) R_MACL_BASE) #define R_SDADC_B ((R_SDADC_B_Type *) R_SDADC_B_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -14931,6 +15002,8 @@ typedef struct /*!< (@ 0x4009C000) R_SDADC_B Structure #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -14954,6 +15027,8 @@ typedef struct /*!< (@ 0x4009C000) R_SDADC_B Structure #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -14993,9 +15068,15 @@ typedef struct /*!< (@ 0x4009C000) R_SDADC_B Structure #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -15070,7 +15151,13 @@ typedef struct /*!< (@ 0x4009C000) R_SDADC_B Structure #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -15107,8 +15194,6 @@ typedef struct /*!< (@ 0x4009C000) R_SDADC_B Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -15294,6 +15379,24 @@ typedef struct /*!< (@ 0x4009C000) R_SDADC_B Structure #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h index 5e385cfaf..296479589 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h @@ -2110,7 +2110,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -2123,7 +2123,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -5790,7 +5790,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -5837,7 +5838,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -5848,7 +5850,10 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -5865,24 +5870,26 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -5926,12 +5933,24 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -6408,7 +6427,57 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -12061,6 +12130,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_AGTX7_BASE 0x40084700UL #define R_AGTX8_BASE 0x40084800UL #define R_AGTX9_BASE 0x40084900UL + #define R_WDT1_BASE 0x40044300UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -12160,6 +12230,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -14534,6 +14605,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -14557,6 +14630,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -14596,9 +14671,15 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -14673,7 +14754,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -14710,8 +14797,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -14897,6 +14982,24 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h index 0bd5793d2..5d59d84e8 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h @@ -1865,7 +1865,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -1878,7 +1878,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -4684,7 +4684,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -4731,7 +4732,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -4742,7 +4744,10 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -4759,24 +4764,26 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -4820,12 +4827,24 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -5302,7 +5321,57 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -6337,20 +6406,25 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure union { - __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ struct { - __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ - __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ - __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ - __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ - __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ - __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ - __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ - uint32_t : 9; - __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ - uint32_t : 15; + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 2; + __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset */ + __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese */ + __IOM uint32_t HTDBRST : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset */ + __IOM uint32_t HRDBRST : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset */ + uint32_t : 3; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; } RSTCTL_b; }; @@ -6480,8 +6554,8 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ uint32_t : 8; __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ - __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */ - uint32_t : 15; + __IOM uint32_t SVAEn : 3; /*!< [18..16] Slave Address Enable */ + uint32_t : 13; } SVCTL_b; }; __IM uint32_t RESERVED6[2]; @@ -6523,7 +6597,7 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ uint32_t : 2; - __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */ + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull */ uint32_t : 2; } EXTBR_b; }; @@ -6677,7 +6751,57 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ } SVTDLG0_b; }; - __IM uint32_t RESERVED11[31]; + __IM uint32_t RESERVED11[23]; + + union + { + __IOM uint32_t STCTL; /*!< (@ 0x00000120) Synchronous Timing Control Register */ + + struct + { + __IOM uint32_t STOE : 1; /*!< [0..0] Synchronous Timing output Enable */ + uint32_t : 31; + } STCTL_b; + }; + + union + { + __IOM uint32_t ATCTL; /*!< (@ 0x00000124) Asynchronous Timing Control Register */ + + struct + { + __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select */ + __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow) */ + __IOM uint32_t AMEOE : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable */ + uint32_t : 5; + __IOM uint32_t CDIV : 8; /*!< [15..8] TCLK Counter Divide Setting */ + uint32_t : 16; + } ATCTL_b; + }; + + union + { + __IOM uint32_t ATTRG; /*!< (@ 0x00000128) Asynchronous Timing Trigger Register */ + + struct + { + __OM uint32_t ATSTRG : 1; /*!< [0..0] Asynchronous Timing Software Trigger */ + uint32_t : 31; + } ATTRG_b; + }; + + union + { + __IOM uint32_t ATCCNTE; /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register */ + + struct + { + __IOM uint32_t ATCE : 1; /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1, + * SC2. */ + uint32_t : 31; + } ATCCNTE_b; + }; + __IM uint32_t RESERVED12[4]; union { @@ -6691,14 +6815,43 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure uint32_t : 29; } CNDCTL_b; }; - __IM uint32_t RESERVED12[3]; + __IM uint32_t RESERVED13[3]; __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ - __IM uint32_t RESERVED13[8]; + __IM uint32_t RESERVED14[8]; __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ - __IM uint32_t RESERVED14[3]; + + union + { + __OM uint32_t HCMDQP; /*!< (@ 0x00000184) High Priority Command Queue Port Register */ + + struct + { + __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port */ + } HCMDQP_b; + }; + + union + { + __IM uint32_t HRSPQP; /*!< (@ 0x00000188) High Priority Response Queue Port Register */ + + struct + { + __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port */ + } HRSPQP_b; + }; + + union + { + __IOM uint32_t HTDTBP; /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register */ + + struct + { + __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port */ + } HTDTBP_b; + }; union { @@ -6743,7 +6896,37 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure uint32_t : 24; } NRQTHCTL_b; }; - __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t HQTHCTL; /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold */ + uint32_t : 16; + } HQTHCTL_b; + }; + + union + { + __IOM uint32_t HTBTHCTL; /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold + * Control Register */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold */ + uint32_t : 5; + } HTBTHCTL_b; + }; + __IM uint32_t RESERVED16; union { @@ -6916,7 +7099,79 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure uint32_t : 11; } NTSTFC_b; }; - __IM uint32_t RESERVED17[8]; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint32_t HTST; /*!< (@ 0x00000200) High Priority Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag */ + __IOM uint32_t RDBFF : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag */ + uint32_t : 1; + __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] High Priority Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] High Priority Transfer Error Flag */ + uint32_t : 22; + } HTST_b; + }; + + union + { + __IOM uint32_t HTSTE; /*!< (@ 0x00000204) High Priority Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable */ + __IOM uint32_t RDBFE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] High Priority Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] High Priority Transfer Error Enable */ + uint32_t : 22; + } HTSTE_b; + }; + + union + { + __IOM uint32_t HTIE; /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable */ + __IOM uint32_t RDBFIE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable */ + uint32_t : 22; + } HTIE_b; + }; + + union + { + __IOM uint32_t HTSTFC; /*!< (@ 0x0000020C) High Priority Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force */ + __OM uint32_t RDBFFC : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force */ + uint32_t : 1; + __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] High Priority Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] High Priority Transfer Error Force */ + uint32_t : 22; + } HTSTFC_b; + }; union { @@ -6943,22 +7198,32 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ uint32_t : 8; __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ - __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */ - uint32_t : 15; + __IOM uint32_t SVAFn : 3; /*!< [18..16] Slave Address Detection Flag */ + uint32_t : 13; } SVST_b; }; union { - __IOM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Control Register */ + __IM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Operating Status Register */ struct { - __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ - uint32_t : 31; + __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; } WUST_b; }; - __IM uint32_t RESERVED18[2]; + + union + { + __IM uint32_t MRCCPT; /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register */ + + struct + { + __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture */ + } MRCCPT_b; + }; + __IM uint32_t RESERVED18; union { @@ -7038,7 +7303,87 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ } DATBAS3_b; }; - __IM uint32_t RESERVED22[24]; + __IM uint32_t RESERVED22; + + union + { + __IOM uint32_t DATBAS4; /*!< (@ 0x00000244) Device Address Table Basic Register 4 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS4_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IOM uint32_t DATBAS5; /*!< (@ 0x0000024C) Device Address Table Basic Register 5 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS5_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t DATBAS6; /*!< (@ 0x00000254) Device Address Table Basic Register 6 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS6_b; + }; + __IM uint32_t RESERVED25; + + union + { + __IOM uint32_t DATBAS7; /*!< (@ 0x0000025C) Device Address Table Basic Register 7 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS7_b; + }; + __IM uint32_t RESERVED26[16]; union { @@ -7054,7 +7399,7 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ } EXDATBAS_b; }; - __IM uint32_t RESERVED23[3]; + __IM uint32_t RESERVED27[3]; union { @@ -7103,7 +7448,7 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure uint32_t : 9; } SDATBAS2_b; }; - __IM uint32_t RESERVED24[5]; + __IM uint32_t RESERVED28[5]; union { @@ -7176,7 +7521,79 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure uint32_t : 16; } MSDCT3_b; }; - __IM uint32_t RESERVED25[16]; + + union + { + __IOM uint32_t MSDCT4; /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT4_b; + }; + + union + { + __IOM uint32_t MSDCT5; /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT5_b; + }; + + union + { + __IOM uint32_t MSDCT6; /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT6_b; + }; + + union + { + __IOM uint32_t MSDCT7; /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT7_b; + }; + __IM uint32_t RESERVED29[12]; union { @@ -7199,7 +7616,7 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure * ID Low Register */ __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional * ID High Register */ - __IM uint32_t RESERVED26; + __IM uint32_t RESERVED30; union { @@ -7216,7 +7633,39 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ } SVDVAD0_b; }; - __IM uint32_t RESERVED27[7]; + + union + { + __IM uint32_t SVDVAD1; /*!< (@ 0x00000334) Slave Device Address Register 1 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD1_b; + }; + + union + { + __IM uint32_t SVDVAD2; /*!< (@ 0x00000338) Slave Device Address Register 2 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD2_b; + }; + __IM uint32_t RESERVED31[5]; union { @@ -7329,18 +7778,35 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure union { - __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) - * Register */ + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ struct { - uint32_t : 8; - __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ - __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ - uint32_t : 8; + __IOM uint32_t SPTSYN : 1; /*!< [0..0] Supports Sync Mode */ + __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0 */ + __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1 */ + uint32_t : 5; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; } CETSM_b; }; - __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t CETSS; /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State) + * Register */ + + struct + { + __IOM uint32_t SYNE : 1; /*!< [0..0] Sync Mode Enabled */ + __IOM uint32_t ASYNE : 2; /*!< [2..1] Async Mode Enabled */ + uint32_t : 4; + __IOM uint32_t ICOVF : 1; /*!< [7..7] Internal Counter Overflow */ + uint32_t : 24; + } CETSS_b; + }; union { @@ -7367,7 +7833,7 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure uint32_t : 24; } BITCNT_b; }; - __IM uint32_t RESERVED29[4]; + __IM uint32_t RESERVED32[4]; union { @@ -7385,7 +7851,7 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure union { - __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */ + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0 */ struct { @@ -7394,7 +7860,7 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure uint32_t : 16; } NDBSTLV0_b; }; - __IM uint32_t RESERVED30[9]; + __IM uint32_t RESERVED33[9]; union { @@ -7406,7 +7872,30 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure uint32_t : 24; } NRSQSTLV_b; }; - __IM uint32_t RESERVED31[2]; + + union + { + __IM uint32_t HQSTLV; /*!< (@ 0x000003C4) High Priority Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQLV : 8; /*!< [7..0] High Priority Command Queue Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] High Priority Response Queue Level */ + uint32_t : 16; + } HQSTLV_b; + }; + + union + { + __IM uint32_t HDBSTLV; /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] High Priority Tx Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] High Priority Rx Data Buffer Level */ + uint32_t : 16; + } HDBSTLV_b; + }; union { @@ -7432,7 +7921,30 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure uint32_t : 24; } MSERRCNT_b; }; -} R_I3C0_Type; /*!< Size = 980 (0x3d4) */ + __IM uint32_t RESERVED34[3]; + + union + { + __IM uint32_t SC1CPT; /*!< (@ 0x000003E0) SC1 Capture monitor Register */ + + struct + { + __IM uint32_t SC1C : 16; /*!< [15..0] SC1 Capture */ + uint32_t : 16; + } SC1CPT_b; + }; + + union + { + __IM uint32_t SC2CPT; /*!< (@ 0x000003E4) SC2 Capture monitor Register */ + + struct + { + __IM uint32_t SC2C : 16; /*!< [15..0] SC2 Capture */ + uint32_t : 16; + } SC2CPT_b; + }; +} R_I3C0_Type; /*!< Size = 1000 (0x3e8) */ /* =========================================================================================================================== */ /* ================ R_MPU_MMPU ================ */ @@ -11614,6 +12126,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_AGTX7_BASE 0x40084700UL #define R_AGTX8_BASE 0x40084800UL #define R_AGTX9_BASE 0x40084900UL + #define R_WDT1_BASE 0x40044300UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -11711,6 +12224,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_AGTW7 ((R_AGTX0_Type *) R_AGTX7_BASE) #define R_AGTW8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGTW9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -13471,6 +13985,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -13494,6 +14010,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -13533,9 +14051,15 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -13610,7 +14134,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -13647,8 +14177,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -13834,6 +14362,24 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ @@ -14523,6 +15069,14 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HCMDQRST_Pos (9UL) /*!< HCMDQRST (Bit 9) */ + #define R_I3C0_RSTCTL_HCMDQRST_Msk (0x200UL) /*!< HCMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRSPQRST_Pos (10UL) /*!< HRSPQRST (Bit 10) */ + #define R_I3C0_RSTCTL_HRSPQRST_Msk (0x400UL) /*!< HRSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HTDBRST_Pos (11UL) /*!< HTDBRST (Bit 11) */ + #define R_I3C0_RSTCTL_HTDBRST_Msk (0x800UL) /*!< HTDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRDBRST_Pos (12UL) /*!< HRDBRST (Bit 12) */ + #define R_I3C0_RSTCTL_HRDBRST_Msk (0x1000UL) /*!< HRDBRST (Bitfield-Mask: 0x01) */ #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ /* ========================================================= PRSST ========================================================= */ @@ -14579,7 +15133,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ - #define R_I3C0_SVCTL_SVAEn_Msk (0x10000UL) /*!< SVAEn (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_SVAEn_Msk (0x70000UL) /*!< SVAEn (Bitfield-Mask: 0x07) */ /* ======================================================= REFCKCTL ======================================================== */ #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ @@ -14674,6 +15228,24 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================== SVTDLG0 ======================================================== */ #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= STCTL ========================================================= */ + #define R_I3C0_STCTL_STOE_Pos (0UL) /*!< STOE (Bit 0) */ + #define R_I3C0_STCTL_STOE_Msk (0x1UL) /*!< STOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ATCTL ========================================================= */ + #define R_I3C0_ATCTL_ATTRGS_Pos (0UL) /*!< ATTRGS (Bit 0) */ + #define R_I3C0_ATCTL_ATTRGS_Msk (0x1UL) /*!< ATTRGS (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_MREFOE_Pos (1UL) /*!< MREFOE (Bit 1) */ + #define R_I3C0_ATCTL_MREFOE_Msk (0x2UL) /*!< MREFOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_AMEOE_Pos (2UL) /*!< AMEOE (Bit 2) */ + #define R_I3C0_ATCTL_AMEOE_Msk (0x4UL) /*!< AMEOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_CDIV_Pos (8UL) /*!< CDIV (Bit 8) */ + #define R_I3C0_ATCTL_CDIV_Msk (0xff00UL) /*!< CDIV (Bitfield-Mask: 0xff) */ +/* ========================================================= ATTRG ========================================================= */ + #define R_I3C0_ATTRG_ATSTRG_Pos (0UL) /*!< ATSTRG (Bit 0) */ + #define R_I3C0_ATTRG_ATSTRG_Msk (0x1UL) /*!< ATSTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== ATCCNTE ======================================================== */ + #define R_I3C0_ATCCNTE_ATCE_Pos (0UL) /*!< ATCE (Bit 0) */ + #define R_I3C0_ATCCNTE_ATCE_Msk (0x1UL) /*!< ATCE (Bitfield-Mask: 0x01) */ /* ======================================================== CNDCTL ========================================================= */ #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ @@ -14686,6 +15258,15 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================== NTDTBP0 ======================================================== */ /* ======================================================== NIBIQP ========================================================= */ /* ========================================================= NRSQP ========================================================= */ +/* ======================================================== HCMDQP ========================================================= */ + #define R_I3C0_HCMDQP_HCMDQP_Pos (0UL) /*!< HCMDQP (Bit 0) */ + #define R_I3C0_HCMDQP_HCMDQP_Msk (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HRSPQP ========================================================= */ + #define R_I3C0_HRSPQP_HRSPQP_Pos (0UL) /*!< HRSPQP (Bit 0) */ + #define R_I3C0_HRSPQP_HRSPQP_Msk (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HTDTBP ========================================================= */ + #define R_I3C0_HTDTBP_HTDTBP_Pos (0UL) /*!< HTDTBP (Bit 0) */ + #define R_I3C0_HTDTBP_HTDTBP_Msk (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff) */ /* ======================================================== NQTHCTL ======================================================== */ #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ @@ -14707,6 +15288,20 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================= NRQTHCTL ======================================================== */ #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ +/* ======================================================== HQTHCTL ======================================================== */ + #define R_I3C0_HQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_HQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_HQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= HTBTHCTL ======================================================== */ + #define R_I3C0_HTBTHCTL_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_HTBTHCTL_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ /* ========================================================== BST ========================================================== */ #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ @@ -14843,6 +15438,58 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ +/* ========================================================= HTST ========================================================== */ + #define R_I3C0_HTST_TDBEF_Pos (0UL) /*!< TDBEF (Bit 0) */ + #define R_I3C0_HTST_TDBEF_Msk (0x1UL) /*!< TDBEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RDBFF_Pos (1UL) /*!< RDBFF (Bit 1) */ + #define R_I3C0_HTST_RDBFF_Msk (0x2UL) /*!< RDBFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_HTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_HTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_HTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_HTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ +/* ========================================================= HTSTE ========================================================= */ + #define R_I3C0_HTSTE_TDBEE_Pos (0UL) /*!< TDBEE (Bit 0) */ + #define R_I3C0_HTSTE_TDBEE_Msk (0x1UL) /*!< TDBEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RDBFE_Pos (1UL) /*!< RDBFE (Bit 1) */ + #define R_I3C0_HTSTE_RDBFE_Msk (0x2UL) /*!< RDBFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_HTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_HTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_HTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_HTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ +/* ========================================================= HTIE ========================================================== */ + #define R_I3C0_HTIE_TDBEIE_Pos (0UL) /*!< TDBEIE (Bit 0) */ + #define R_I3C0_HTIE_TDBEIE_Msk (0x1UL) /*!< TDBEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RDBFIE_Pos (1UL) /*!< RDBFIE (Bit 1) */ + #define R_I3C0_HTIE_RDBFIE_Msk (0x2UL) /*!< RDBFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_HTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_HTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_HTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_HTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== HTSTFC ========================================================= */ + #define R_I3C0_HTSTFC_TDBEFC_Pos (0UL) /*!< TDBEFC (Bit 0) */ + #define R_I3C0_HTSTFC_TDBEFC_Msk (0x1UL) /*!< TDBEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RDBFFC_Pos (1UL) /*!< RDBFFC (Bit 1) */ + #define R_I3C0_HTSTFC_RDBFFC_Msk (0x2UL) /*!< RDBFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_HTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_HTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_HTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_HTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ /* ========================================================= BCST ========================================================== */ #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ @@ -14860,10 +15507,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ - #define R_I3C0_SVST_SVAFn_Msk (0x10000UL) /*!< SVAFn (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_SVAFn_Msk (0x70000UL) /*!< SVAFn (Bitfield-Mask: 0x07) */ /* ========================================================= WUST ========================================================== */ #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCCPT ========================================================= */ + #define R_I3C0_MRCCPT_MRCCPT_Pos (0UL) /*!< MRCCPT (Bit 0) */ + #define R_I3C0_MRCCPT_MRCCPT_Msk (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff) */ /* ======================================================== DATBAS0 ======================================================== */ #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ @@ -14932,6 +15582,74 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS4 ======================================================== */ + #define R_I3C0_DATBAS4_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS4_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS4_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS4_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS4_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS4_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS4_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS4_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS4_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS4_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS4_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS5 ======================================================== */ + #define R_I3C0_DATBAS5_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS5_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS5_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS5_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS5_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS5_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS5_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS5_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS5_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS5_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS5_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS6 ======================================================== */ + #define R_I3C0_DATBAS6_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS6_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS6_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS6_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS6_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS6_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS6_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS6_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS6_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS6_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS6_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS7 ======================================================== */ + #define R_I3C0_DATBAS7_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS7_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS7_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS7_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS7_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS7_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS7_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS7_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS7_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS7_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS7_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ /* ======================================================= EXDATBAS ======================================================== */ #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ @@ -15028,6 +15746,66 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT4 ========================================================= */ + #define R_I3C0_MSDCT4_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT4_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT4_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT4_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT4_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT4_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT4_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT4_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT5 ========================================================= */ + #define R_I3C0_MSDCT5_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT5_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT5_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT5_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT5_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT5_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT5_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT5_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT6 ========================================================= */ + #define R_I3C0_MSDCT6_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT6_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT6_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT6_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT6_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT6_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT6_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT6_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT7 ========================================================= */ + #define R_I3C0_MSDCT7_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT7_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT7_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT7_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT7_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT7_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT7_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT7_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ========================================================= SVDCT ========================================================= */ #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ @@ -15056,6 +15834,24 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD1 ======================================================== */ + #define R_I3C0_SVDVAD1_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD1_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD1_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD1_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD1_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD1_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD2 ======================================================== */ + #define R_I3C0_SVDVAD2_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD2_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD2_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD2_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD2_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD2_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ /* ======================================================== CSECMD ========================================================= */ #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ @@ -15100,10 +15896,23 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ /* ========================================================= CETSM ========================================================= */ + #define R_I3C0_CETSM_SPTSYN_Pos (0UL) /*!< SPTSYN (Bit 0) */ + #define R_I3C0_CETSM_SPTSYN_Msk (0x1UL) /*!< SPTSYN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN0_Pos (1UL) /*!< SPTASYN0 (Bit 1) */ + #define R_I3C0_CETSM_SPTASYN0_Msk (0x2UL) /*!< SPTASYN0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN1_Pos (2UL) /*!< SPTASYN1 (Bit 2) */ + #define R_I3C0_CETSM_SPTASYN1_Msk (0x4UL) /*!< SPTASYN1 (Bitfield-Mask: 0x01) */ #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ========================================================= CETSS ========================================================= */ + #define R_I3C0_CETSS_SYNE_Pos (0UL) /*!< SYNE (Bit 0) */ + #define R_I3C0_CETSS_SYNE_Msk (0x1UL) /*!< SYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSS_ASYNE_Pos (1UL) /*!< ASYNE (Bit 1) */ + #define R_I3C0_CETSS_ASYNE_Msk (0x6UL) /*!< ASYNE (Bitfield-Mask: 0x03) */ + #define R_I3C0_CETSS_ICOVF_Pos (7UL) /*!< ICOVF (Bit 7) */ + #define R_I3C0_CETSS_ICOVF_Msk (0x80UL) /*!< ICOVF (Bitfield-Mask: 0x01) */ /* ======================================================= CGHDRCAP ======================================================== */ #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ @@ -15133,6 +15942,16 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================= NRSQSTLV ======================================================== */ #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HQSTLV ========================================================= */ + #define R_I3C0_HQSTLV_CMDQLV_Pos (0UL) /*!< CMDQLV (Bit 0) */ + #define R_I3C0_HQSTLV_CMDQLV_Msk (0xffUL) /*!< CMDQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_HQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HDBSTLV ======================================================== */ + #define R_I3C0_HDBSTLV_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_HDBSTLV_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HDBSTLV_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_HDBSTLV_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ /* ======================================================== PRSTDBG ======================================================== */ #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ @@ -15145,6 +15964,12 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================= MSERRCNT ======================================================== */ #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ +/* ======================================================== SC1CPT ========================================================= */ + #define R_I3C0_SC1CPT_SC1C_Pos (0UL) /*!< SC1C (Bit 0) */ + #define R_I3C0_SC1CPT_SC1C_Msk (0xffffUL) /*!< SC1C (Bitfield-Mask: 0xffff) */ +/* ======================================================== SC2CPT ========================================================= */ + #define R_I3C0_SC2CPT_SC2C_Pos (0UL) /*!< SC2C (Bit 0) */ + #define R_I3C0_SC2CPT_SC2C_Msk (0xffffUL) /*!< SC2C (Bitfield-Mask: 0xffff) */ /* =========================================================================================================================== */ /* ================ R_MPU_MMPU ================ */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E307.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E307.h index 9f3f77d80..b07513aff 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E307.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E307.h @@ -2024,7 +2024,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -2037,7 +2037,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -4843,7 +4843,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -4890,7 +4891,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -4901,7 +4903,10 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -4918,24 +4923,26 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -4979,12 +4986,24 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -5461,7 +5480,57 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -10994,6 +11063,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_AGTX7_BASE 0x40084700UL #define R_AGTX8_BASE 0x40084800UL #define R_AGTX9_BASE 0x40084900UL + #define R_WDT1_BASE 0x40044300UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -11088,6 +11158,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -12906,6 +12977,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -12929,6 +13002,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -12968,9 +13043,15 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -13045,7 +13126,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -13082,8 +13169,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -13269,6 +13354,24 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h index fd96fcf47..38f6edc63 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h @@ -2169,7 +2169,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -2182,7 +2182,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -6464,7 +6464,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -6511,7 +6512,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -6522,7 +6524,10 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -6539,24 +6544,26 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -6600,12 +6607,24 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -7082,7 +7101,57 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -12738,6 +12807,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_AGTX7_BASE 0x40084700UL #define R_AGTX8_BASE 0x40084800UL #define R_AGTX9_BASE 0x40084900UL + #define R_WDT1_BASE 0x40044300UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -12840,6 +12910,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -15679,6 +15750,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -15702,6 +15775,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -15741,9 +15816,15 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -15818,7 +15899,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -15855,8 +15942,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -16042,6 +16127,24 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h index e3fff4b58..d324432ba 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h @@ -2113,7 +2113,7 @@ typedef struct /*!< (@ 0x40170000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -2126,7 +2126,7 @@ typedef struct /*!< (@ 0x40170000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -4485,8 +4485,8 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure struct { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ uint32_t : 7; __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ @@ -5961,7 +5961,8 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -6008,7 +6009,8 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -6019,7 +6021,10 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -6036,24 +6041,26 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -6097,12 +6104,24 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -6579,7 +6598,57 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -12238,7 +12307,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * data. */ uint16_t : 1; __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ } CFIFOCTR_b; }; @@ -12258,7 +12327,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D0FIFOSEL_b; }; @@ -12292,7 +12361,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D1FIFOSEL_b; }; @@ -12567,14 +12636,13 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure union { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ struct { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; + uint16_t : 15; __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; + } DVCHGR_b; }; union @@ -12587,8 +12655,8 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * the USB address assigned by the host when the USBHS processed * the SET_ADDRESS request successfully. */ uint16_t : 1; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; } USBADDR_b; }; __IM uint16_t RESERVED9; @@ -13728,6 +13796,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGTX8_BASE 0x400E8800UL #define R_AGTX9_BASE 0x400E8900UL #define R_FLAD_BASE 0x407FC000UL + #define R_WDT1_BASE 0x40044300UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -13839,6 +13908,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -15848,9 +15918,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================= DMAST ========================================================= */ #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* ======================================================== DMECHR ========================================================= */ #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ @@ -15860,11 +15935,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -16387,6 +16457,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -16410,6 +16482,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -16449,9 +16523,15 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -16526,7 +16606,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -16563,8 +16649,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -16750,6 +16834,24 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ @@ -19406,14 +19508,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== UFRMNUM ======================================================== */ - #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ /* ======================================================== USBADDR ======================================================== */ #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ /* ======================================================== USBREQ ========================================================= */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E2B9.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E2B9.h index c597f5f58..56af160d0 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E2B9.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E2B9.h @@ -2568,7 +2568,7 @@ typedef struct /*!< (@ 0x40170000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -2581,7 +2581,7 @@ typedef struct /*!< (@ 0x40170000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -4405,8 +4405,8 @@ typedef struct /*!< (@ 0x400B0000) R_CANFD0 Structure struct { - __IM uint32_t RFXIF : 1; /*!< [0..0] RX FIFO[x] Interrupt Flag Status */ - uint32_t : 31; + __IM uint32_t RFXIF : 2; /*!< [1..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 30; } CFDRFISTS_b; }; @@ -5098,8 +5098,8 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure struct { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ uint32_t : 7; __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ @@ -6574,7 +6574,8 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -6621,7 +6622,8 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -6632,7 +6634,10 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -6649,24 +6654,26 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -6710,12 +6717,24 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -7192,7 +7211,57 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -8168,20 +8237,25 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure union { - __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ struct { - __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ - __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ - __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ - __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ - __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ - __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ - __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ - uint32_t : 9; - __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ - uint32_t : 15; + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 2; + __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset */ + __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese */ + __IOM uint32_t HTDBRST : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset */ + __IOM uint32_t HRDBRST : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset */ + uint32_t : 3; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; } RSTCTL_b; }; @@ -8311,8 +8385,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ uint32_t : 8; __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ - __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */ - uint32_t : 15; + __IOM uint32_t SVAEn : 3; /*!< [18..16] Slave Address Enable */ + uint32_t : 13; } SVCTL_b; }; __IM uint32_t RESERVED6[2]; @@ -8354,7 +8428,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ uint32_t : 2; - __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */ + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull */ uint32_t : 2; } EXTBR_b; }; @@ -8508,7 +8582,57 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ } SVTDLG0_b; }; - __IM uint32_t RESERVED11[31]; + __IM uint32_t RESERVED11[23]; + + union + { + __IOM uint32_t STCTL; /*!< (@ 0x00000120) Synchronous Timing Control Register */ + + struct + { + __IOM uint32_t STOE : 1; /*!< [0..0] Synchronous Timing output Enable */ + uint32_t : 31; + } STCTL_b; + }; + + union + { + __IOM uint32_t ATCTL; /*!< (@ 0x00000124) Asynchronous Timing Control Register */ + + struct + { + __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select */ + __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow) */ + __IOM uint32_t AMEOE : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable */ + uint32_t : 5; + __IOM uint32_t CDIV : 8; /*!< [15..8] TCLK Counter Divide Setting */ + uint32_t : 16; + } ATCTL_b; + }; + + union + { + __IOM uint32_t ATTRG; /*!< (@ 0x00000128) Asynchronous Timing Trigger Register */ + + struct + { + __OM uint32_t ATSTRG : 1; /*!< [0..0] Asynchronous Timing Software Trigger */ + uint32_t : 31; + } ATTRG_b; + }; + + union + { + __IOM uint32_t ATCCNTE; /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register */ + + struct + { + __IOM uint32_t ATCE : 1; /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1, + * SC2. */ + uint32_t : 31; + } ATCCNTE_b; + }; + __IM uint32_t RESERVED12[4]; union { @@ -8522,14 +8646,43 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 29; } CNDCTL_b; }; - __IM uint32_t RESERVED12[3]; + __IM uint32_t RESERVED13[3]; __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ - __IM uint32_t RESERVED13[8]; + __IM uint32_t RESERVED14[8]; __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ - __IM uint32_t RESERVED14[3]; + + union + { + __OM uint32_t HCMDQP; /*!< (@ 0x00000184) High Priority Command Queue Port Register */ + + struct + { + __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port */ + } HCMDQP_b; + }; + + union + { + __IM uint32_t HRSPQP; /*!< (@ 0x00000188) High Priority Response Queue Port Register */ + + struct + { + __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port */ + } HRSPQP_b; + }; + + union + { + __IOM uint32_t HTDTBP; /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register */ + + struct + { + __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port */ + } HTDTBP_b; + }; union { @@ -8574,7 +8727,37 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } NRQTHCTL_b; }; - __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t HQTHCTL; /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold */ + uint32_t : 16; + } HQTHCTL_b; + }; + + union + { + __IOM uint32_t HTBTHCTL; /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold + * Control Register */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold */ + uint32_t : 5; + } HTBTHCTL_b; + }; + __IM uint32_t RESERVED16; union { @@ -8747,7 +8930,79 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 11; } NTSTFC_b; }; - __IM uint32_t RESERVED17[8]; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint32_t HTST; /*!< (@ 0x00000200) High Priority Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag */ + __IOM uint32_t RDBFF : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag */ + uint32_t : 1; + __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] High Priority Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] High Priority Transfer Error Flag */ + uint32_t : 22; + } HTST_b; + }; + + union + { + __IOM uint32_t HTSTE; /*!< (@ 0x00000204) High Priority Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable */ + __IOM uint32_t RDBFE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] High Priority Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] High Priority Transfer Error Enable */ + uint32_t : 22; + } HTSTE_b; + }; + + union + { + __IOM uint32_t HTIE; /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable */ + __IOM uint32_t RDBFIE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable */ + uint32_t : 22; + } HTIE_b; + }; + + union + { + __IOM uint32_t HTSTFC; /*!< (@ 0x0000020C) High Priority Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force */ + __OM uint32_t RDBFFC : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force */ + uint32_t : 1; + __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] High Priority Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] High Priority Transfer Error Force */ + uint32_t : 22; + } HTSTFC_b; + }; union { @@ -8774,22 +9029,32 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ uint32_t : 8; __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ - __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */ - uint32_t : 15; + __IOM uint32_t SVAFn : 3; /*!< [18..16] Slave Address Detection Flag */ + uint32_t : 13; } SVST_b; }; union { - __IOM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Control Register */ + __IM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Operating Status Register */ struct { - __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ - uint32_t : 31; + __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; } WUST_b; }; - __IM uint32_t RESERVED18[2]; + + union + { + __IM uint32_t MRCCPT; /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register */ + + struct + { + __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture */ + } MRCCPT_b; + }; + __IM uint32_t RESERVED18; union { @@ -8869,7 +9134,87 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ } DATBAS3_b; }; - __IM uint32_t RESERVED22[24]; + __IM uint32_t RESERVED22; + + union + { + __IOM uint32_t DATBAS4; /*!< (@ 0x00000244) Device Address Table Basic Register 4 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS4_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IOM uint32_t DATBAS5; /*!< (@ 0x0000024C) Device Address Table Basic Register 5 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS5_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t DATBAS6; /*!< (@ 0x00000254) Device Address Table Basic Register 6 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS6_b; + }; + __IM uint32_t RESERVED25; + + union + { + __IOM uint32_t DATBAS7; /*!< (@ 0x0000025C) Device Address Table Basic Register 7 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS7_b; + }; + __IM uint32_t RESERVED26[16]; union { @@ -8885,7 +9230,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ } EXDATBAS_b; }; - __IM uint32_t RESERVED23[3]; + __IM uint32_t RESERVED27[3]; union { @@ -8934,7 +9279,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 9; } SDATBAS2_b; }; - __IM uint32_t RESERVED24[5]; + __IM uint32_t RESERVED28[5]; union { @@ -9007,7 +9352,79 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 16; } MSDCT3_b; }; - __IM uint32_t RESERVED25[16]; + + union + { + __IOM uint32_t MSDCT4; /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT4_b; + }; + + union + { + __IOM uint32_t MSDCT5; /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT5_b; + }; + + union + { + __IOM uint32_t MSDCT6; /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT6_b; + }; + + union + { + __IOM uint32_t MSDCT7; /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT7_b; + }; + __IM uint32_t RESERVED29[12]; union { @@ -9030,7 +9447,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure * ID Low Register */ __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional * ID High Register */ - __IM uint32_t RESERVED26; + __IM uint32_t RESERVED30; union { @@ -9047,7 +9464,39 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ } SVDVAD0_b; }; - __IM uint32_t RESERVED27[7]; + + union + { + __IM uint32_t SVDVAD1; /*!< (@ 0x00000334) Slave Device Address Register 1 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD1_b; + }; + + union + { + __IM uint32_t SVDVAD2; /*!< (@ 0x00000338) Slave Device Address Register 2 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD2_b; + }; + __IM uint32_t RESERVED31[5]; union { @@ -9160,18 +9609,35 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure union { - __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) - * Register */ + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ struct { - uint32_t : 8; - __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ - __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ - uint32_t : 8; + __IOM uint32_t SPTSYN : 1; /*!< [0..0] Supports Sync Mode */ + __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0 */ + __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1 */ + uint32_t : 5; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; } CETSM_b; }; - __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t CETSS; /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State) + * Register */ + + struct + { + __IOM uint32_t SYNE : 1; /*!< [0..0] Sync Mode Enabled */ + __IOM uint32_t ASYNE : 2; /*!< [2..1] Async Mode Enabled */ + uint32_t : 4; + __IOM uint32_t ICOVF : 1; /*!< [7..7] Internal Counter Overflow */ + uint32_t : 24; + } CETSS_b; + }; union { @@ -9198,7 +9664,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } BITCNT_b; }; - __IM uint32_t RESERVED29[4]; + __IM uint32_t RESERVED32[4]; union { @@ -9216,7 +9682,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure union { - __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */ + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0 */ struct { @@ -9225,7 +9691,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 16; } NDBSTLV0_b; }; - __IM uint32_t RESERVED30[9]; + __IM uint32_t RESERVED33[9]; union { @@ -9237,7 +9703,30 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } NRSQSTLV_b; }; - __IM uint32_t RESERVED31[2]; + + union + { + __IM uint32_t HQSTLV; /*!< (@ 0x000003C4) High Priority Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQLV : 8; /*!< [7..0] High Priority Command Queue Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] High Priority Response Queue Level */ + uint32_t : 16; + } HQSTLV_b; + }; + + union + { + __IM uint32_t HDBSTLV; /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] High Priority Tx Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] High Priority Rx Data Buffer Level */ + uint32_t : 16; + } HDBSTLV_b; + }; union { @@ -9263,7 +9752,30 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } MSERRCNT_b; }; -} R_I3C0_Type; /*!< Size = 980 (0x3d4) */ + __IM uint32_t RESERVED34[3]; + + union + { + __IM uint32_t SC1CPT; /*!< (@ 0x000003E0) SC1 Capture monitor Register */ + + struct + { + __IM uint32_t SC1C : 16; /*!< [15..0] SC1 Capture */ + uint32_t : 16; + } SC1CPT_b; + }; + + union + { + __IM uint32_t SC2CPT; /*!< (@ 0x000003E4) SC2 Capture monitor Register */ + + struct + { + __IM uint32_t SC2C : 16; /*!< [15..0] SC2 Capture */ + uint32_t : 16; + } SC2CPT_b; + }; +} R_I3C0_Type; /*!< Size = 1000 (0x3e8) */ /* =========================================================================================================================== */ /* ================ R_MPU_MMPU ================ */ @@ -14122,7 +14634,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * data. */ uint16_t : 1; __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ } CFIFOCTR_b; }; @@ -14142,7 +14654,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D0FIFOSEL_b; }; @@ -14176,7 +14688,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D1FIFOSEL_b; }; @@ -14451,14 +14963,13 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure union { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ struct { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; + uint16_t : 15; __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; + } DVCHGR_b; }; union @@ -14471,8 +14982,8 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * the USB address assigned by the host when the USBHS processed * the SET_ADDRESS request successfully. */ uint16_t : 1; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; } USBADDR_b; }; __IM uint16_t RESERVED9; @@ -15936,6 +16447,81 @@ typedef struct /*!< (@ 0x400E8000) R_AGTX0 Structure }; } R_AGTX0_Type; /*!< Size = 20 (0x14) */ +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CANFD ECC (R_ECCMB0) + */ + +typedef struct /*!< (@ 0x4036F200) R_ECCMB0 Structure */ +{ + union + { + __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ + + struct + { + __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Message Flag */ + __IM uint32_t ECER1F : 1; /*!< [1..1] ECC Error Detection and Correction Flag */ + __IM uint32_t ECER2F : 1; /*!< [2..2] 2-bit ECC Error Detection Flag */ + __IOM uint32_t EC1EDIC : 1; /*!< [3..3] ECC 1-bit Error Detection Interrupt Control */ + __IOM uint32_t EC2EDIC : 1; /*!< [4..4] ECC 2-bit Error Detection Interrupt Control */ + __IOM uint32_t EC1ECP : 1; /*!< [5..5] ECC 1-bit Error Correction Permission */ + __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Judgment Enable Flag */ + uint32_t : 2; + __IOM uint32_t ECER1C : 1; /*!< [9..9] Accumulating ECC Error Detection and Correction Flag + * Clear */ + __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-bit ECC Error Detection Flag Clear */ + __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Overflow Detection Flag */ + uint32_t : 2; + __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Select bit */ + __IM uint32_t ECSEDF0 : 1; /*!< [16..16] ECC Single bit Error Address Detection Flag */ + __IM uint32_t ECDEDF0 : 1; /*!< [17..17] ECC Dual Bit Error Address Detection Flag */ + uint32_t : 14; + } EC710CTL_b; + }; + + union + { + __IOM uint16_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ + uint16_t : 5; + __IOM uint16_t ECTMCE : 1; /*!< [7..7] ECC Test Mode Control Enable */ + uint16_t : 6; + __IOM uint16_t ETMA : 2; /*!< [15..14] ECC Test Mode Bit Access Control */ + } EC710TMC_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Test Substitute Data Register */ + + struct + { + __IOM uint32_t ECEDB : 32; /*!< [31..0] ECC Test Substitute Data */ + } EC710TED_b; + }; + + union + { + __IM uint32_t EC710EAD0; /*!< (@ 0x00000010) ECC Error Address Register */ + + struct + { + __IM uint32_t ECEAD : 10; /*!< [9..0] ECC Error Address */ + uint32_t : 22; + } EC710EAD0_b; + }; +} R_ECCMB0_Type; /*!< Size = 20 (0x14) */ + /* =========================================================================================================================== */ /* ================ R_FLAD ================ */ /* =========================================================================================================================== */ @@ -16076,7 +16662,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGTX7_BASE 0x400E8700UL #define R_AGTX8_BASE 0x400E8800UL #define R_AGTX9_BASE 0x400E8900UL + #define R_ECCMB0_BASE 0x4036F200UL + #define R_ECCMB1_BASE 0x4036F300UL #define R_FLAD_BASE 0x407FC000UL + #define R_WDT1_BASE 0x40044300UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -16196,7 +16785,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGTW7 ((R_AGTX0_Type *) R_AGTX7_BASE) #define R_AGTW8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGTW9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_ECCMB0 ((R_ECCMB0_Type *) R_ECCMB0_BASE) + #define R_ECCMB1 ((R_ECCMB0_Type *) R_ECCMB1_BASE) #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -18185,7 +18777,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x100UL) /*!< CFXMLT (Bitfield-Mask: 0x01) */ /* ======================================================= CFDRFISTS ======================================================= */ #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ - #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x1UL) /*!< RFXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x3UL) /*!< RFXIF (Bitfield-Mask: 0x03) */ /* ======================================================== CFDTMC ========================================================= */ #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ @@ -18431,9 +19023,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================= DMAST ========================================================= */ #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* ======================================================== DMECHR ========================================================= */ #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ @@ -18443,11 +19040,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -18970,6 +19562,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -18993,6 +19587,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -19032,9 +19628,15 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -19109,7 +19711,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -19146,8 +19754,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -19333,6 +19939,24 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ @@ -19978,6 +20602,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HCMDQRST_Pos (9UL) /*!< HCMDQRST (Bit 9) */ + #define R_I3C0_RSTCTL_HCMDQRST_Msk (0x200UL) /*!< HCMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRSPQRST_Pos (10UL) /*!< HRSPQRST (Bit 10) */ + #define R_I3C0_RSTCTL_HRSPQRST_Msk (0x400UL) /*!< HRSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HTDBRST_Pos (11UL) /*!< HTDBRST (Bit 11) */ + #define R_I3C0_RSTCTL_HTDBRST_Msk (0x800UL) /*!< HTDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRDBRST_Pos (12UL) /*!< HRDBRST (Bit 12) */ + #define R_I3C0_RSTCTL_HRDBRST_Msk (0x1000UL) /*!< HRDBRST (Bitfield-Mask: 0x01) */ #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ /* ========================================================= PRSST ========================================================= */ @@ -20034,7 +20666,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ - #define R_I3C0_SVCTL_SVAEn_Msk (0x10000UL) /*!< SVAEn (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_SVAEn_Msk (0x70000UL) /*!< SVAEn (Bitfield-Mask: 0x07) */ /* ======================================================= REFCKCTL ======================================================== */ #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ @@ -20129,6 +20761,24 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================== SVTDLG0 ======================================================== */ #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= STCTL ========================================================= */ + #define R_I3C0_STCTL_STOE_Pos (0UL) /*!< STOE (Bit 0) */ + #define R_I3C0_STCTL_STOE_Msk (0x1UL) /*!< STOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ATCTL ========================================================= */ + #define R_I3C0_ATCTL_ATTRGS_Pos (0UL) /*!< ATTRGS (Bit 0) */ + #define R_I3C0_ATCTL_ATTRGS_Msk (0x1UL) /*!< ATTRGS (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_MREFOE_Pos (1UL) /*!< MREFOE (Bit 1) */ + #define R_I3C0_ATCTL_MREFOE_Msk (0x2UL) /*!< MREFOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_AMEOE_Pos (2UL) /*!< AMEOE (Bit 2) */ + #define R_I3C0_ATCTL_AMEOE_Msk (0x4UL) /*!< AMEOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_CDIV_Pos (8UL) /*!< CDIV (Bit 8) */ + #define R_I3C0_ATCTL_CDIV_Msk (0xff00UL) /*!< CDIV (Bitfield-Mask: 0xff) */ +/* ========================================================= ATTRG ========================================================= */ + #define R_I3C0_ATTRG_ATSTRG_Pos (0UL) /*!< ATSTRG (Bit 0) */ + #define R_I3C0_ATTRG_ATSTRG_Msk (0x1UL) /*!< ATSTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== ATCCNTE ======================================================== */ + #define R_I3C0_ATCCNTE_ATCE_Pos (0UL) /*!< ATCE (Bit 0) */ + #define R_I3C0_ATCCNTE_ATCE_Msk (0x1UL) /*!< ATCE (Bitfield-Mask: 0x01) */ /* ======================================================== CNDCTL ========================================================= */ #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ @@ -20141,6 +20791,15 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================== NTDTBP0 ======================================================== */ /* ======================================================== NIBIQP ========================================================= */ /* ========================================================= NRSQP ========================================================= */ +/* ======================================================== HCMDQP ========================================================= */ + #define R_I3C0_HCMDQP_HCMDQP_Pos (0UL) /*!< HCMDQP (Bit 0) */ + #define R_I3C0_HCMDQP_HCMDQP_Msk (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HRSPQP ========================================================= */ + #define R_I3C0_HRSPQP_HRSPQP_Pos (0UL) /*!< HRSPQP (Bit 0) */ + #define R_I3C0_HRSPQP_HRSPQP_Msk (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HTDTBP ========================================================= */ + #define R_I3C0_HTDTBP_HTDTBP_Pos (0UL) /*!< HTDTBP (Bit 0) */ + #define R_I3C0_HTDTBP_HTDTBP_Msk (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff) */ /* ======================================================== NQTHCTL ======================================================== */ #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ @@ -20162,6 +20821,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= NRQTHCTL ======================================================== */ #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ +/* ======================================================== HQTHCTL ======================================================== */ + #define R_I3C0_HQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_HQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_HQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= HTBTHCTL ======================================================== */ + #define R_I3C0_HTBTHCTL_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_HTBTHCTL_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ /* ========================================================== BST ========================================================== */ #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ @@ -20298,6 +20971,58 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ +/* ========================================================= HTST ========================================================== */ + #define R_I3C0_HTST_TDBEF_Pos (0UL) /*!< TDBEF (Bit 0) */ + #define R_I3C0_HTST_TDBEF_Msk (0x1UL) /*!< TDBEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RDBFF_Pos (1UL) /*!< RDBFF (Bit 1) */ + #define R_I3C0_HTST_RDBFF_Msk (0x2UL) /*!< RDBFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_HTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_HTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_HTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_HTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ +/* ========================================================= HTSTE ========================================================= */ + #define R_I3C0_HTSTE_TDBEE_Pos (0UL) /*!< TDBEE (Bit 0) */ + #define R_I3C0_HTSTE_TDBEE_Msk (0x1UL) /*!< TDBEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RDBFE_Pos (1UL) /*!< RDBFE (Bit 1) */ + #define R_I3C0_HTSTE_RDBFE_Msk (0x2UL) /*!< RDBFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_HTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_HTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_HTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_HTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ +/* ========================================================= HTIE ========================================================== */ + #define R_I3C0_HTIE_TDBEIE_Pos (0UL) /*!< TDBEIE (Bit 0) */ + #define R_I3C0_HTIE_TDBEIE_Msk (0x1UL) /*!< TDBEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RDBFIE_Pos (1UL) /*!< RDBFIE (Bit 1) */ + #define R_I3C0_HTIE_RDBFIE_Msk (0x2UL) /*!< RDBFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_HTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_HTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_HTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_HTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== HTSTFC ========================================================= */ + #define R_I3C0_HTSTFC_TDBEFC_Pos (0UL) /*!< TDBEFC (Bit 0) */ + #define R_I3C0_HTSTFC_TDBEFC_Msk (0x1UL) /*!< TDBEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RDBFFC_Pos (1UL) /*!< RDBFFC (Bit 1) */ + #define R_I3C0_HTSTFC_RDBFFC_Msk (0x2UL) /*!< RDBFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_HTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_HTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_HTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_HTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ /* ========================================================= BCST ========================================================== */ #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ @@ -20315,10 +21040,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ - #define R_I3C0_SVST_SVAFn_Msk (0x10000UL) /*!< SVAFn (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_SVAFn_Msk (0x70000UL) /*!< SVAFn (Bitfield-Mask: 0x07) */ /* ========================================================= WUST ========================================================== */ #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCCPT ========================================================= */ + #define R_I3C0_MRCCPT_MRCCPT_Pos (0UL) /*!< MRCCPT (Bit 0) */ + #define R_I3C0_MRCCPT_MRCCPT_Msk (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff) */ /* ======================================================== DATBAS0 ======================================================== */ #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ @@ -20387,6 +21115,74 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS4 ======================================================== */ + #define R_I3C0_DATBAS4_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS4_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS4_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS4_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS4_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS4_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS4_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS4_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS4_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS4_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS4_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS5 ======================================================== */ + #define R_I3C0_DATBAS5_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS5_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS5_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS5_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS5_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS5_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS5_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS5_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS5_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS5_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS5_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS6 ======================================================== */ + #define R_I3C0_DATBAS6_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS6_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS6_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS6_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS6_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS6_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS6_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS6_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS6_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS6_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS6_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS7 ======================================================== */ + #define R_I3C0_DATBAS7_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS7_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS7_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS7_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS7_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS7_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS7_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS7_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS7_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS7_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS7_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ /* ======================================================= EXDATBAS ======================================================== */ #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ @@ -20483,6 +21279,66 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT4 ========================================================= */ + #define R_I3C0_MSDCT4_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT4_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT4_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT4_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT4_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT4_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT4_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT4_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT5 ========================================================= */ + #define R_I3C0_MSDCT5_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT5_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT5_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT5_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT5_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT5_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT5_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT5_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT6 ========================================================= */ + #define R_I3C0_MSDCT6_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT6_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT6_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT6_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT6_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT6_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT6_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT6_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT7 ========================================================= */ + #define R_I3C0_MSDCT7_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT7_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT7_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT7_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT7_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT7_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT7_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT7_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ========================================================= SVDCT ========================================================= */ #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ @@ -20511,6 +21367,24 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD1 ======================================================== */ + #define R_I3C0_SVDVAD1_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD1_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD1_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD1_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD1_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD1_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD2 ======================================================== */ + #define R_I3C0_SVDVAD2_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD2_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD2_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD2_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD2_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD2_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ /* ======================================================== CSECMD ========================================================= */ #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ @@ -20555,10 +21429,23 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ /* ========================================================= CETSM ========================================================= */ + #define R_I3C0_CETSM_SPTSYN_Pos (0UL) /*!< SPTSYN (Bit 0) */ + #define R_I3C0_CETSM_SPTSYN_Msk (0x1UL) /*!< SPTSYN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN0_Pos (1UL) /*!< SPTASYN0 (Bit 1) */ + #define R_I3C0_CETSM_SPTASYN0_Msk (0x2UL) /*!< SPTASYN0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN1_Pos (2UL) /*!< SPTASYN1 (Bit 2) */ + #define R_I3C0_CETSM_SPTASYN1_Msk (0x4UL) /*!< SPTASYN1 (Bitfield-Mask: 0x01) */ #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ========================================================= CETSS ========================================================= */ + #define R_I3C0_CETSS_SYNE_Pos (0UL) /*!< SYNE (Bit 0) */ + #define R_I3C0_CETSS_SYNE_Msk (0x1UL) /*!< SYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSS_ASYNE_Pos (1UL) /*!< ASYNE (Bit 1) */ + #define R_I3C0_CETSS_ASYNE_Msk (0x6UL) /*!< ASYNE (Bitfield-Mask: 0x03) */ + #define R_I3C0_CETSS_ICOVF_Pos (7UL) /*!< ICOVF (Bit 7) */ + #define R_I3C0_CETSS_ICOVF_Msk (0x80UL) /*!< ICOVF (Bitfield-Mask: 0x01) */ /* ======================================================= CGHDRCAP ======================================================== */ #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ @@ -20588,6 +21475,16 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= NRSQSTLV ======================================================== */ #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HQSTLV ========================================================= */ + #define R_I3C0_HQSTLV_CMDQLV_Pos (0UL) /*!< CMDQLV (Bit 0) */ + #define R_I3C0_HQSTLV_CMDQLV_Msk (0xffUL) /*!< CMDQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_HQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HDBSTLV ======================================================== */ + #define R_I3C0_HDBSTLV_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_HDBSTLV_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HDBSTLV_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_HDBSTLV_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ /* ======================================================== PRSTDBG ======================================================== */ #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ @@ -20600,6 +21497,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= MSERRCNT ======================================================== */ #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ +/* ======================================================== SC1CPT ========================================================= */ + #define R_I3C0_SC1CPT_SC1C_Pos (0UL) /*!< SC1C (Bit 0) */ + #define R_I3C0_SC1CPT_SC1C_Msk (0xffffUL) /*!< SC1C (Bitfield-Mask: 0xffff) */ +/* ======================================================== SC2CPT ========================================================= */ + #define R_I3C0_SC2CPT_SC2C_Pos (0UL) /*!< SC2C (Bit 0) */ + #define R_I3C0_SC2CPT_SC2C_Msk (0xffffUL) /*!< SC2C (Bitfield-Mask: 0xffff) */ /* =========================================================================================================================== */ /* ================ R_MPU_MMPU ================ */ @@ -22754,14 +23657,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== UFRMNUM ======================================================== */ - #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ /* ======================================================== USBADDR ======================================================== */ #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ /* ======================================================== USBREQ ========================================================= */ @@ -23432,6 +24333,51 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ R_AGTX0 ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= EC710CTL ======================================================== */ + #define R_ECCMB0_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ + #define R_ECCMB0_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ + #define R_ECCMB0_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ + #define R_ECCMB0_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ + #define R_ECCMB0_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ + #define R_ECCMB0_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ + #define R_ECCMB0_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ + #define R_ECCMB0_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Pos (16UL) /*!< ECSEDF0 (Bit 16) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Msk (0x10000UL) /*!< ECSEDF0 (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Pos (17UL) /*!< ECDEDF0 (Bit 17) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Msk (0x20000UL) /*!< ECDEDF0 (Bitfield-Mask: 0x01) */ +/* ======================================================= EC710TMC ======================================================== */ + #define R_ECCMB0_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ + #define R_ECCMB0_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ + #define R_ECCMB0_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ +/* ======================================================= EC710TED ======================================================== */ + #define R_ECCMB0_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ + #define R_ECCMB0_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EC710EAD0 ======================================================= */ + #define R_ECCMB0_EC710EAD0_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ + #define R_ECCMB0_EC710EAD0_ECEAD_Msk (0x3ffUL) /*!< ECEAD (Bitfield-Mask: 0x3ff) */ + /* =========================================================================================================================== */ /* ================ R_FLAD ================ */ /* =========================================================================================================================== */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h index 5ced06ec5..a894750bb 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h @@ -2235,7 +2235,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -2248,7 +2248,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -4686,8 +4686,8 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure struct { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ uint32_t : 7; __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ @@ -6310,7 +6310,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -6357,7 +6358,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -6368,7 +6370,10 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -6385,24 +6390,26 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -6446,12 +6453,24 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -6928,7 +6947,57 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -12889,7 +12958,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * data. */ uint16_t : 1; __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ } CFIFOCTR_b; }; @@ -12909,7 +12978,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D0FIFOSEL_b; }; @@ -12943,7 +13012,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D1FIFOSEL_b; }; @@ -13218,14 +13287,13 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure union { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ struct { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; + uint16_t : 15; __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; + } DVCHGR_b; }; union @@ -13238,8 +13306,8 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * the USB address assigned by the host when the USBHS processed * the SET_ADDRESS request successfully. */ uint16_t : 1; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; } USBADDR_b; }; __IM uint16_t RESERVED9; @@ -13949,6 +14017,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_AGTX7_BASE 0x40084700UL #define R_AGTX8_BASE 0x40084800UL #define R_AGTX9_BASE 0x40084900UL + #define R_WDT1_BASE 0x40044300UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -14064,6 +14133,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -16117,9 +16187,14 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================= DMAST ========================================================= */ #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* ======================================================== DMECHR ========================================================= */ #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ @@ -16129,11 +16204,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -16705,6 +16775,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -16728,6 +16800,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -16767,9 +16841,15 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -16844,7 +16924,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -16881,8 +16967,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -17068,6 +17152,24 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ @@ -19914,14 +20016,12 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== UFRMNUM ======================================================== */ - #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ /* ======================================================== USBADDR ======================================================== */ #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ /* ======================================================== USBREQ ========================================================= */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h index f1ae62e6c..7471c517e 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h @@ -2113,7 +2113,7 @@ typedef struct /*!< (@ 0x40170000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -2126,7 +2126,7 @@ typedef struct /*!< (@ 0x40170000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -4728,8 +4728,8 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure struct { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ uint32_t : 7; __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ @@ -6204,7 +6204,8 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -6251,7 +6252,8 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -6262,7 +6264,10 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -6279,24 +6284,26 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -6340,12 +6347,24 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -6822,7 +6841,57 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -13229,7 +13298,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * data. */ uint16_t : 1; __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ } CFIFOCTR_b; }; @@ -13249,7 +13318,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D0FIFOSEL_b; }; @@ -13283,7 +13352,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D1FIFOSEL_b; }; @@ -13558,14 +13627,13 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure union { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ struct { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; + uint16_t : 15; __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; + } DVCHGR_b; }; union @@ -13578,8 +13646,8 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * the USB address assigned by the host when the USBHS processed * the SET_ADDRESS request successfully. */ uint16_t : 1; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; } USBADDR_b; }; __IM uint16_t RESERVED9; @@ -14726,6 +14794,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGTX8_BASE 0x400E8800UL #define R_AGTX9_BASE 0x400E8900UL #define R_FLAD_BASE 0x407FC000UL + #define R_WDT1_BASE 0x40044300UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -14844,6 +14913,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -16957,9 +17027,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================= DMAST ========================================================= */ #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* ======================================================== DMECHR ========================================================= */ #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ @@ -16969,11 +17044,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -17496,6 +17566,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -17519,6 +17591,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -17558,9 +17632,15 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -17635,7 +17715,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -17672,8 +17758,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -17859,6 +17943,24 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ @@ -20915,14 +21017,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== UFRMNUM ======================================================== */ - #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ /* ======================================================== USBADDR ======================================================== */ #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ /* ======================================================== USBREQ ========================================================= */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h index 778be37a1..6d1d954c9 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h @@ -2113,7 +2113,7 @@ typedef struct /*!< (@ 0x40170000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -2126,7 +2126,7 @@ typedef struct /*!< (@ 0x40170000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -4728,8 +4728,8 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure struct { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ uint32_t : 7; __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ @@ -6204,7 +6204,8 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -6251,7 +6252,8 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -6262,7 +6264,10 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -6279,24 +6284,26 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -6340,12 +6347,24 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -6822,7 +6841,57 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -13229,7 +13298,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * data. */ uint16_t : 1; __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ } CFIFOCTR_b; }; @@ -13249,7 +13318,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D0FIFOSEL_b; }; @@ -13283,7 +13352,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D1FIFOSEL_b; }; @@ -13558,14 +13627,13 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure union { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ struct { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; + uint16_t : 15; __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; + } DVCHGR_b; }; union @@ -13578,8 +13646,8 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * the USB address assigned by the host when the USBHS processed * the SET_ADDRESS request successfully. */ uint16_t : 1; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; } USBADDR_b; }; __IM uint16_t RESERVED9; @@ -14830,6 +14898,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGTX8_BASE 0x400E8800UL #define R_AGTX9_BASE 0x400E8900UL #define R_FLAD_BASE 0x407FC000UL + #define R_WDT1_BASE 0x40044300UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -14949,6 +15018,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -17062,9 +17132,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================= DMAST ========================================================= */ #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* ======================================================== DMECHR ========================================================= */ #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ @@ -17074,11 +17149,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -17601,6 +17671,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -17624,6 +17696,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -17663,9 +17737,15 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -17740,7 +17820,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -17777,8 +17863,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -17964,6 +18048,24 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ @@ -21020,14 +21122,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== UFRMNUM ======================================================== */ - #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ /* ======================================================== USBADDR ======================================================== */ #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ /* ======================================================== USBREQ ========================================================= */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4T1BB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4T1BB.h index e08d0cf60..9a6fd8d15 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4T1BB.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4T1BB.h @@ -2210,7 +2210,31 @@ typedef struct /*!< (@ 0x400F4000) R_ACMPHS0 Structure __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ } CPIOC_b; }; -} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ + __IM uint8_t RESERVED4[47]; + + union + { + __IOM uint8_t CPINTCTL; /*!< (@ 0x00000040) Comparator Interrupt Control Register */ + + struct + { + __IOM uint8_t MSKE : 1; /*!< [0..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 7; + } CPINTCTL_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t CPMSKCTL; /*!< (@ 0x00000044) Comparator Interrupt Mask Control Register */ + + struct + { + __IOM uint8_t MSKSEL : 3; /*!< [2..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 5; + } CPMSKCTL_b; + }; +} R_ACMPHS0_Type; /*!< Size = 69 (0x45) */ /* =========================================================================================================================== */ /* ================ R_ADC0 ================ */ @@ -2473,7 +2497,7 @@ typedef struct /*!< (@ 0x40170000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -2486,7 +2510,7 @@ typedef struct /*!< (@ 0x40170000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -4310,8 +4334,8 @@ typedef struct /*!< (@ 0x400B0000) R_CANFD0 Structure struct { - __IM uint32_t RFXIF : 1; /*!< [0..0] RX FIFO[x] Interrupt Flag Status */ - uint32_t : 31; + __IM uint32_t RFXIF : 2; /*!< [1..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 30; } CFDRFISTS_b; }; @@ -5003,8 +5027,8 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure struct { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ uint32_t : 7; __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ @@ -6479,7 +6503,8 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -6526,7 +6551,8 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -6537,7 +6563,10 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -6554,24 +6583,26 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -6615,12 +6646,24 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -7097,7 +7140,57 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -8073,20 +8166,25 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure union { - __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ struct { - __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ - __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ - __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ - __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ - __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ - __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ - __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ - uint32_t : 9; - __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ - uint32_t : 15; + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 2; + __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset */ + __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese */ + __IOM uint32_t HTDBRST : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset */ + __IOM uint32_t HRDBRST : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset */ + uint32_t : 3; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; } RSTCTL_b; }; @@ -8216,8 +8314,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ uint32_t : 8; __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ - __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */ - uint32_t : 15; + __IOM uint32_t SVAEn : 3; /*!< [18..16] Slave Address Enable */ + uint32_t : 13; } SVCTL_b; }; __IM uint32_t RESERVED6[2]; @@ -8259,7 +8357,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ uint32_t : 2; - __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */ + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull */ uint32_t : 2; } EXTBR_b; }; @@ -8413,7 +8511,57 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ } SVTDLG0_b; }; - __IM uint32_t RESERVED11[31]; + __IM uint32_t RESERVED11[23]; + + union + { + __IOM uint32_t STCTL; /*!< (@ 0x00000120) Synchronous Timing Control Register */ + + struct + { + __IOM uint32_t STOE : 1; /*!< [0..0] Synchronous Timing output Enable */ + uint32_t : 31; + } STCTL_b; + }; + + union + { + __IOM uint32_t ATCTL; /*!< (@ 0x00000124) Asynchronous Timing Control Register */ + + struct + { + __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select */ + __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow) */ + __IOM uint32_t AMEOE : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable */ + uint32_t : 5; + __IOM uint32_t CDIV : 8; /*!< [15..8] TCLK Counter Divide Setting */ + uint32_t : 16; + } ATCTL_b; + }; + + union + { + __IOM uint32_t ATTRG; /*!< (@ 0x00000128) Asynchronous Timing Trigger Register */ + + struct + { + __OM uint32_t ATSTRG : 1; /*!< [0..0] Asynchronous Timing Software Trigger */ + uint32_t : 31; + } ATTRG_b; + }; + + union + { + __IOM uint32_t ATCCNTE; /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register */ + + struct + { + __IOM uint32_t ATCE : 1; /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1, + * SC2. */ + uint32_t : 31; + } ATCCNTE_b; + }; + __IM uint32_t RESERVED12[4]; union { @@ -8427,14 +8575,43 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 29; } CNDCTL_b; }; - __IM uint32_t RESERVED12[3]; + __IM uint32_t RESERVED13[3]; __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ - __IM uint32_t RESERVED13[8]; + __IM uint32_t RESERVED14[8]; __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ - __IM uint32_t RESERVED14[3]; + + union + { + __OM uint32_t HCMDQP; /*!< (@ 0x00000184) High Priority Command Queue Port Register */ + + struct + { + __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port */ + } HCMDQP_b; + }; + + union + { + __IM uint32_t HRSPQP; /*!< (@ 0x00000188) High Priority Response Queue Port Register */ + + struct + { + __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port */ + } HRSPQP_b; + }; + + union + { + __IOM uint32_t HTDTBP; /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register */ + + struct + { + __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port */ + } HTDTBP_b; + }; union { @@ -8479,7 +8656,37 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } NRQTHCTL_b; }; - __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t HQTHCTL; /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold */ + uint32_t : 16; + } HQTHCTL_b; + }; + + union + { + __IOM uint32_t HTBTHCTL; /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold + * Control Register */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold */ + uint32_t : 5; + } HTBTHCTL_b; + }; + __IM uint32_t RESERVED16; union { @@ -8652,7 +8859,79 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 11; } NTSTFC_b; }; - __IM uint32_t RESERVED17[8]; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint32_t HTST; /*!< (@ 0x00000200) High Priority Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag */ + __IOM uint32_t RDBFF : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag */ + uint32_t : 1; + __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] High Priority Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] High Priority Transfer Error Flag */ + uint32_t : 22; + } HTST_b; + }; + + union + { + __IOM uint32_t HTSTE; /*!< (@ 0x00000204) High Priority Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable */ + __IOM uint32_t RDBFE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] High Priority Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] High Priority Transfer Error Enable */ + uint32_t : 22; + } HTSTE_b; + }; + + union + { + __IOM uint32_t HTIE; /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable */ + __IOM uint32_t RDBFIE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable */ + uint32_t : 22; + } HTIE_b; + }; + + union + { + __IOM uint32_t HTSTFC; /*!< (@ 0x0000020C) High Priority Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force */ + __OM uint32_t RDBFFC : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force */ + uint32_t : 1; + __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] High Priority Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] High Priority Transfer Error Force */ + uint32_t : 22; + } HTSTFC_b; + }; union { @@ -8679,22 +8958,32 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ uint32_t : 8; __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ - __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */ - uint32_t : 15; + __IOM uint32_t SVAFn : 3; /*!< [18..16] Slave Address Detection Flag */ + uint32_t : 13; } SVST_b; }; union { - __IOM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Control Register */ + __IM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Operating Status Register */ struct { - __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ - uint32_t : 31; + __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; } WUST_b; }; - __IM uint32_t RESERVED18[2]; + + union + { + __IM uint32_t MRCCPT; /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register */ + + struct + { + __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture */ + } MRCCPT_b; + }; + __IM uint32_t RESERVED18; union { @@ -8774,7 +9063,87 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ } DATBAS3_b; }; - __IM uint32_t RESERVED22[24]; + __IM uint32_t RESERVED22; + + union + { + __IOM uint32_t DATBAS4; /*!< (@ 0x00000244) Device Address Table Basic Register 4 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS4_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IOM uint32_t DATBAS5; /*!< (@ 0x0000024C) Device Address Table Basic Register 5 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS5_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t DATBAS6; /*!< (@ 0x00000254) Device Address Table Basic Register 6 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS6_b; + }; + __IM uint32_t RESERVED25; + + union + { + __IOM uint32_t DATBAS7; /*!< (@ 0x0000025C) Device Address Table Basic Register 7 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS7_b; + }; + __IM uint32_t RESERVED26[16]; union { @@ -8790,7 +9159,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ } EXDATBAS_b; }; - __IM uint32_t RESERVED23[3]; + __IM uint32_t RESERVED27[3]; union { @@ -8839,7 +9208,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 9; } SDATBAS2_b; }; - __IM uint32_t RESERVED24[5]; + __IM uint32_t RESERVED28[5]; union { @@ -8912,7 +9281,79 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 16; } MSDCT3_b; }; - __IM uint32_t RESERVED25[16]; + + union + { + __IOM uint32_t MSDCT4; /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT4_b; + }; + + union + { + __IOM uint32_t MSDCT5; /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT5_b; + }; + + union + { + __IOM uint32_t MSDCT6; /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT6_b; + }; + + union + { + __IOM uint32_t MSDCT7; /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT7_b; + }; + __IM uint32_t RESERVED29[12]; union { @@ -8935,7 +9376,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure * ID Low Register */ __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional * ID High Register */ - __IM uint32_t RESERVED26; + __IM uint32_t RESERVED30; union { @@ -8952,7 +9393,39 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ } SVDVAD0_b; }; - __IM uint32_t RESERVED27[7]; + + union + { + __IM uint32_t SVDVAD1; /*!< (@ 0x00000334) Slave Device Address Register 1 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD1_b; + }; + + union + { + __IM uint32_t SVDVAD2; /*!< (@ 0x00000338) Slave Device Address Register 2 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD2_b; + }; + __IM uint32_t RESERVED31[5]; union { @@ -9065,18 +9538,35 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure union { - __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) - * Register */ + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ struct { - uint32_t : 8; - __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ - __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ - uint32_t : 8; + __IOM uint32_t SPTSYN : 1; /*!< [0..0] Supports Sync Mode */ + __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0 */ + __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1 */ + uint32_t : 5; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; } CETSM_b; }; - __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t CETSS; /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State) + * Register */ + + struct + { + __IOM uint32_t SYNE : 1; /*!< [0..0] Sync Mode Enabled */ + __IOM uint32_t ASYNE : 2; /*!< [2..1] Async Mode Enabled */ + uint32_t : 4; + __IOM uint32_t ICOVF : 1; /*!< [7..7] Internal Counter Overflow */ + uint32_t : 24; + } CETSS_b; + }; union { @@ -9103,7 +9593,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } BITCNT_b; }; - __IM uint32_t RESERVED29[4]; + __IM uint32_t RESERVED32[4]; union { @@ -9121,7 +9611,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure union { - __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */ + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0 */ struct { @@ -9130,7 +9620,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 16; } NDBSTLV0_b; }; - __IM uint32_t RESERVED30[9]; + __IM uint32_t RESERVED33[9]; union { @@ -9142,7 +9632,30 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } NRSQSTLV_b; }; - __IM uint32_t RESERVED31[2]; + + union + { + __IM uint32_t HQSTLV; /*!< (@ 0x000003C4) High Priority Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQLV : 8; /*!< [7..0] High Priority Command Queue Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] High Priority Response Queue Level */ + uint32_t : 16; + } HQSTLV_b; + }; + + union + { + __IM uint32_t HDBSTLV; /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] High Priority Tx Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] High Priority Rx Data Buffer Level */ + uint32_t : 16; + } HDBSTLV_b; + }; union { @@ -9168,7 +9681,30 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } MSERRCNT_b; }; -} R_I3C0_Type; /*!< Size = 980 (0x3d4) */ + __IM uint32_t RESERVED34[3]; + + union + { + __IM uint32_t SC1CPT; /*!< (@ 0x000003E0) SC1 Capture monitor Register */ + + struct + { + __IM uint32_t SC1C : 16; /*!< [15..0] SC1 Capture */ + uint32_t : 16; + } SC1CPT_b; + }; + + union + { + __IM uint32_t SC2CPT; /*!< (@ 0x000003E4) SC2 Capture monitor Register */ + + struct + { + __IM uint32_t SC2C : 16; /*!< [15..0] SC2 Capture */ + uint32_t : 16; + } SC2CPT_b; + }; +} R_I3C0_Type; /*!< Size = 1000 (0x3e8) */ /* =========================================================================================================================== */ /* ================ R_MPU_MMPU ================ */ @@ -13823,6 +14359,81 @@ typedef struct /*!< (@ 0x400E8000) R_AGTX0 Structure }; } R_AGTX0_Type; /*!< Size = 20 (0x14) */ +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CANFD ECC (R_ECCMB0) + */ + +typedef struct /*!< (@ 0x4036F200) R_ECCMB0 Structure */ +{ + union + { + __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ + + struct + { + __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Message Flag */ + __IM uint32_t ECER1F : 1; /*!< [1..1] ECC Error Detection and Correction Flag */ + __IM uint32_t ECER2F : 1; /*!< [2..2] 2-bit ECC Error Detection Flag */ + __IOM uint32_t EC1EDIC : 1; /*!< [3..3] ECC 1-bit Error Detection Interrupt Control */ + __IOM uint32_t EC2EDIC : 1; /*!< [4..4] ECC 2-bit Error Detection Interrupt Control */ + __IOM uint32_t EC1ECP : 1; /*!< [5..5] ECC 1-bit Error Correction Permission */ + __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Judgment Enable Flag */ + uint32_t : 2; + __IOM uint32_t ECER1C : 1; /*!< [9..9] Accumulating ECC Error Detection and Correction Flag + * Clear */ + __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-bit ECC Error Detection Flag Clear */ + __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Overflow Detection Flag */ + uint32_t : 2; + __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Select bit */ + __IM uint32_t ECSEDF0 : 1; /*!< [16..16] ECC Single bit Error Address Detection Flag */ + __IM uint32_t ECDEDF0 : 1; /*!< [17..17] ECC Dual Bit Error Address Detection Flag */ + uint32_t : 14; + } EC710CTL_b; + }; + + union + { + __IOM uint16_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ + uint16_t : 5; + __IOM uint16_t ECTMCE : 1; /*!< [7..7] ECC Test Mode Control Enable */ + uint16_t : 6; + __IOM uint16_t ETMA : 2; /*!< [15..14] ECC Test Mode Bit Access Control */ + } EC710TMC_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Test Substitute Data Register */ + + struct + { + __IOM uint32_t ECEDB : 32; /*!< [31..0] ECC Test Substitute Data */ + } EC710TED_b; + }; + + union + { + __IM uint32_t EC710EAD0; /*!< (@ 0x00000010) ECC Error Address Register */ + + struct + { + __IM uint32_t ECEAD : 10; /*!< [9..0] ECC Error Address */ + uint32_t : 22; + } EC710EAD0_b; + }; +} R_ECCMB0_Type; /*!< Size = 20 (0x14) */ + /* =========================================================================================================================== */ /* ================ R_FLAD ================ */ /* =========================================================================================================================== */ @@ -13966,7 +14577,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGTX7_BASE 0x400E8700UL #define R_AGTX8_BASE 0x400E8800UL #define R_AGTX9_BASE 0x400E8900UL + #define R_ECCMB0_BASE 0x4036F200UL + #define R_ECCMB1_BASE 0x4036F300UL #define R_FLAD_BASE 0x407FC000UL + #define R_WDT1_BASE 0x40044300UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -14089,7 +14703,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGTW7 ((R_AGTX0_Type *) R_AGTX7_BASE) #define R_AGTW8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGTW9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_ECCMB0 ((R_ECCMB0_Type *) R_ECCMB0_BASE) + #define R_ECCMB1 ((R_ECCMB0_Type *) R_ECCMB1_BASE) #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -15108,32 +15725,38 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== CMPCTL ========================================================= */ - #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ - #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ - #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ - #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ - #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ - #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ - #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ - #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ - #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ /* ======================================================== CMPSEL0 ======================================================== */ - #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ - #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ /* ======================================================== CMPSEL1 ======================================================== */ - #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ - #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ /* ======================================================== CMPMON ========================================================= */ - #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ - #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ /* ========================================================= CPIOC ========================================================= */ - #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ - #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ - #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPINTCTL ======================================================== */ + #define R_ACMPHS0_CPINTCTL_MSKE_Pos (0UL) /*!< MSKE (Bit 0) */ + #define R_ACMPHS0_CPINTCTL_MSKE_Msk (0x1UL) /*!< MSKE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPMSKCTL ======================================================== */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Pos (0UL) /*!< MSKSEL (Bit 0) */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Msk (0x7UL) /*!< MSKSEL (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_ADC0 ================ */ @@ -16047,7 +16670,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x100UL) /*!< CFXMLT (Bitfield-Mask: 0x01) */ /* ======================================================= CFDRFISTS ======================================================= */ #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ - #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x1UL) /*!< RFXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x3UL) /*!< RFXIF (Bitfield-Mask: 0x03) */ /* ======================================================== CFDTMC ========================================================= */ #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ @@ -16293,9 +16916,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================= DMAST ========================================================= */ #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* ======================================================== DMECHR ========================================================= */ #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ @@ -16305,11 +16933,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -16832,6 +17455,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -16855,6 +17480,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -16894,9 +17521,15 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -16971,7 +17604,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -17008,8 +17647,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -17195,6 +17832,24 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ @@ -17840,6 +18495,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HCMDQRST_Pos (9UL) /*!< HCMDQRST (Bit 9) */ + #define R_I3C0_RSTCTL_HCMDQRST_Msk (0x200UL) /*!< HCMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRSPQRST_Pos (10UL) /*!< HRSPQRST (Bit 10) */ + #define R_I3C0_RSTCTL_HRSPQRST_Msk (0x400UL) /*!< HRSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HTDBRST_Pos (11UL) /*!< HTDBRST (Bit 11) */ + #define R_I3C0_RSTCTL_HTDBRST_Msk (0x800UL) /*!< HTDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRDBRST_Pos (12UL) /*!< HRDBRST (Bit 12) */ + #define R_I3C0_RSTCTL_HRDBRST_Msk (0x1000UL) /*!< HRDBRST (Bitfield-Mask: 0x01) */ #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ /* ========================================================= PRSST ========================================================= */ @@ -17896,7 +18559,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ - #define R_I3C0_SVCTL_SVAEn_Msk (0x10000UL) /*!< SVAEn (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_SVAEn_Msk (0x70000UL) /*!< SVAEn (Bitfield-Mask: 0x07) */ /* ======================================================= REFCKCTL ======================================================== */ #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ @@ -17991,6 +18654,24 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================== SVTDLG0 ======================================================== */ #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= STCTL ========================================================= */ + #define R_I3C0_STCTL_STOE_Pos (0UL) /*!< STOE (Bit 0) */ + #define R_I3C0_STCTL_STOE_Msk (0x1UL) /*!< STOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ATCTL ========================================================= */ + #define R_I3C0_ATCTL_ATTRGS_Pos (0UL) /*!< ATTRGS (Bit 0) */ + #define R_I3C0_ATCTL_ATTRGS_Msk (0x1UL) /*!< ATTRGS (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_MREFOE_Pos (1UL) /*!< MREFOE (Bit 1) */ + #define R_I3C0_ATCTL_MREFOE_Msk (0x2UL) /*!< MREFOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_AMEOE_Pos (2UL) /*!< AMEOE (Bit 2) */ + #define R_I3C0_ATCTL_AMEOE_Msk (0x4UL) /*!< AMEOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_CDIV_Pos (8UL) /*!< CDIV (Bit 8) */ + #define R_I3C0_ATCTL_CDIV_Msk (0xff00UL) /*!< CDIV (Bitfield-Mask: 0xff) */ +/* ========================================================= ATTRG ========================================================= */ + #define R_I3C0_ATTRG_ATSTRG_Pos (0UL) /*!< ATSTRG (Bit 0) */ + #define R_I3C0_ATTRG_ATSTRG_Msk (0x1UL) /*!< ATSTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== ATCCNTE ======================================================== */ + #define R_I3C0_ATCCNTE_ATCE_Pos (0UL) /*!< ATCE (Bit 0) */ + #define R_I3C0_ATCCNTE_ATCE_Msk (0x1UL) /*!< ATCE (Bitfield-Mask: 0x01) */ /* ======================================================== CNDCTL ========================================================= */ #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ @@ -18003,6 +18684,15 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================== NTDTBP0 ======================================================== */ /* ======================================================== NIBIQP ========================================================= */ /* ========================================================= NRSQP ========================================================= */ +/* ======================================================== HCMDQP ========================================================= */ + #define R_I3C0_HCMDQP_HCMDQP_Pos (0UL) /*!< HCMDQP (Bit 0) */ + #define R_I3C0_HCMDQP_HCMDQP_Msk (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HRSPQP ========================================================= */ + #define R_I3C0_HRSPQP_HRSPQP_Pos (0UL) /*!< HRSPQP (Bit 0) */ + #define R_I3C0_HRSPQP_HRSPQP_Msk (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HTDTBP ========================================================= */ + #define R_I3C0_HTDTBP_HTDTBP_Pos (0UL) /*!< HTDTBP (Bit 0) */ + #define R_I3C0_HTDTBP_HTDTBP_Msk (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff) */ /* ======================================================== NQTHCTL ======================================================== */ #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ @@ -18024,6 +18714,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= NRQTHCTL ======================================================== */ #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ +/* ======================================================== HQTHCTL ======================================================== */ + #define R_I3C0_HQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_HQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_HQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= HTBTHCTL ======================================================== */ + #define R_I3C0_HTBTHCTL_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_HTBTHCTL_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ /* ========================================================== BST ========================================================== */ #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ @@ -18160,6 +18864,58 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ +/* ========================================================= HTST ========================================================== */ + #define R_I3C0_HTST_TDBEF_Pos (0UL) /*!< TDBEF (Bit 0) */ + #define R_I3C0_HTST_TDBEF_Msk (0x1UL) /*!< TDBEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RDBFF_Pos (1UL) /*!< RDBFF (Bit 1) */ + #define R_I3C0_HTST_RDBFF_Msk (0x2UL) /*!< RDBFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_HTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_HTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_HTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_HTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ +/* ========================================================= HTSTE ========================================================= */ + #define R_I3C0_HTSTE_TDBEE_Pos (0UL) /*!< TDBEE (Bit 0) */ + #define R_I3C0_HTSTE_TDBEE_Msk (0x1UL) /*!< TDBEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RDBFE_Pos (1UL) /*!< RDBFE (Bit 1) */ + #define R_I3C0_HTSTE_RDBFE_Msk (0x2UL) /*!< RDBFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_HTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_HTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_HTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_HTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ +/* ========================================================= HTIE ========================================================== */ + #define R_I3C0_HTIE_TDBEIE_Pos (0UL) /*!< TDBEIE (Bit 0) */ + #define R_I3C0_HTIE_TDBEIE_Msk (0x1UL) /*!< TDBEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RDBFIE_Pos (1UL) /*!< RDBFIE (Bit 1) */ + #define R_I3C0_HTIE_RDBFIE_Msk (0x2UL) /*!< RDBFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_HTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_HTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_HTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_HTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== HTSTFC ========================================================= */ + #define R_I3C0_HTSTFC_TDBEFC_Pos (0UL) /*!< TDBEFC (Bit 0) */ + #define R_I3C0_HTSTFC_TDBEFC_Msk (0x1UL) /*!< TDBEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RDBFFC_Pos (1UL) /*!< RDBFFC (Bit 1) */ + #define R_I3C0_HTSTFC_RDBFFC_Msk (0x2UL) /*!< RDBFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_HTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_HTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_HTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_HTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ /* ========================================================= BCST ========================================================== */ #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ @@ -18177,10 +18933,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ - #define R_I3C0_SVST_SVAFn_Msk (0x10000UL) /*!< SVAFn (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_SVAFn_Msk (0x70000UL) /*!< SVAFn (Bitfield-Mask: 0x07) */ /* ========================================================= WUST ========================================================== */ #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCCPT ========================================================= */ + #define R_I3C0_MRCCPT_MRCCPT_Pos (0UL) /*!< MRCCPT (Bit 0) */ + #define R_I3C0_MRCCPT_MRCCPT_Msk (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff) */ /* ======================================================== DATBAS0 ======================================================== */ #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ @@ -18249,6 +19008,74 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS4 ======================================================== */ + #define R_I3C0_DATBAS4_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS4_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS4_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS4_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS4_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS4_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS4_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS4_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS4_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS4_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS4_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS5 ======================================================== */ + #define R_I3C0_DATBAS5_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS5_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS5_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS5_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS5_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS5_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS5_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS5_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS5_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS5_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS5_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS6 ======================================================== */ + #define R_I3C0_DATBAS6_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS6_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS6_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS6_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS6_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS6_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS6_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS6_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS6_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS6_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS6_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS7 ======================================================== */ + #define R_I3C0_DATBAS7_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS7_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS7_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS7_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS7_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS7_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS7_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS7_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS7_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS7_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS7_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ /* ======================================================= EXDATBAS ======================================================== */ #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ @@ -18345,6 +19172,66 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT4 ========================================================= */ + #define R_I3C0_MSDCT4_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT4_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT4_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT4_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT4_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT4_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT4_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT4_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT5 ========================================================= */ + #define R_I3C0_MSDCT5_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT5_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT5_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT5_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT5_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT5_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT5_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT5_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT6 ========================================================= */ + #define R_I3C0_MSDCT6_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT6_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT6_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT6_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT6_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT6_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT6_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT6_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT7 ========================================================= */ + #define R_I3C0_MSDCT7_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT7_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT7_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT7_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT7_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT7_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT7_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT7_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ========================================================= SVDCT ========================================================= */ #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ @@ -18373,6 +19260,24 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD1 ======================================================== */ + #define R_I3C0_SVDVAD1_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD1_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD1_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD1_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD1_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD1_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD2 ======================================================== */ + #define R_I3C0_SVDVAD2_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD2_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD2_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD2_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD2_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD2_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ /* ======================================================== CSECMD ========================================================= */ #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ @@ -18417,10 +19322,23 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ /* ========================================================= CETSM ========================================================= */ + #define R_I3C0_CETSM_SPTSYN_Pos (0UL) /*!< SPTSYN (Bit 0) */ + #define R_I3C0_CETSM_SPTSYN_Msk (0x1UL) /*!< SPTSYN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN0_Pos (1UL) /*!< SPTASYN0 (Bit 1) */ + #define R_I3C0_CETSM_SPTASYN0_Msk (0x2UL) /*!< SPTASYN0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN1_Pos (2UL) /*!< SPTASYN1 (Bit 2) */ + #define R_I3C0_CETSM_SPTASYN1_Msk (0x4UL) /*!< SPTASYN1 (Bitfield-Mask: 0x01) */ #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ========================================================= CETSS ========================================================= */ + #define R_I3C0_CETSS_SYNE_Pos (0UL) /*!< SYNE (Bit 0) */ + #define R_I3C0_CETSS_SYNE_Msk (0x1UL) /*!< SYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSS_ASYNE_Pos (1UL) /*!< ASYNE (Bit 1) */ + #define R_I3C0_CETSS_ASYNE_Msk (0x6UL) /*!< ASYNE (Bitfield-Mask: 0x03) */ + #define R_I3C0_CETSS_ICOVF_Pos (7UL) /*!< ICOVF (Bit 7) */ + #define R_I3C0_CETSS_ICOVF_Msk (0x80UL) /*!< ICOVF (Bitfield-Mask: 0x01) */ /* ======================================================= CGHDRCAP ======================================================== */ #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ @@ -18450,6 +19368,16 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= NRSQSTLV ======================================================== */ #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HQSTLV ========================================================= */ + #define R_I3C0_HQSTLV_CMDQLV_Pos (0UL) /*!< CMDQLV (Bit 0) */ + #define R_I3C0_HQSTLV_CMDQLV_Msk (0xffUL) /*!< CMDQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_HQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HDBSTLV ======================================================== */ + #define R_I3C0_HDBSTLV_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_HDBSTLV_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HDBSTLV_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_HDBSTLV_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ /* ======================================================== PRSTDBG ======================================================== */ #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ @@ -18462,6 +19390,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= MSERRCNT ======================================================== */ #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ +/* ======================================================== SC1CPT ========================================================= */ + #define R_I3C0_SC1CPT_SC1C_Pos (0UL) /*!< SC1C (Bit 0) */ + #define R_I3C0_SC1CPT_SC1C_Msk (0xffffUL) /*!< SC1C (Bitfield-Mask: 0xffff) */ +/* ======================================================== SC2CPT ========================================================= */ + #define R_I3C0_SC2CPT_SC2C_Pos (0UL) /*!< SC2C (Bit 0) */ + #define R_I3C0_SC2CPT_SC2C_Msk (0xffffUL) /*!< SC2C (Bitfield-Mask: 0xffff) */ /* =========================================================================================================================== */ /* ================ R_MPU_MMPU ================ */ @@ -20313,6 +21247,51 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ R_AGTX0 ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= EC710CTL ======================================================== */ + #define R_ECCMB0_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ + #define R_ECCMB0_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ + #define R_ECCMB0_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ + #define R_ECCMB0_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ + #define R_ECCMB0_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ + #define R_ECCMB0_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ + #define R_ECCMB0_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ + #define R_ECCMB0_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Pos (16UL) /*!< ECSEDF0 (Bit 16) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Msk (0x10000UL) /*!< ECSEDF0 (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Pos (17UL) /*!< ECDEDF0 (Bit 17) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Msk (0x20000UL) /*!< ECDEDF0 (Bitfield-Mask: 0x01) */ +/* ======================================================= EC710TMC ======================================================== */ + #define R_ECCMB0_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ + #define R_ECCMB0_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ + #define R_ECCMB0_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ +/* ======================================================= EC710TED ======================================================== */ + #define R_ECCMB0_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ + #define R_ECCMB0_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EC710EAD0 ======================================================= */ + #define R_ECCMB0_EC710EAD0_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ + #define R_ECCMB0_EC710EAD0_ECEAD_Msk (0x3ffUL) /*!< ECEAD (Bitfield-Mask: 0x3ff) */ + /* =========================================================================================================================== */ /* ================ R_FLAD ================ */ /* =========================================================================================================================== */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h index 6c48ef516..77275fd4c 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h @@ -2235,7 +2235,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -2248,7 +2248,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -4686,8 +4686,8 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure struct { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ uint32_t : 7; __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ @@ -6310,7 +6310,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -6357,7 +6358,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -6368,7 +6370,10 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -6385,24 +6390,26 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -6446,12 +6453,24 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -6928,7 +6947,57 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -12725,7 +12794,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * data. */ uint16_t : 1; __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ } CFIFOCTR_b; }; @@ -12745,7 +12814,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D0FIFOSEL_b; }; @@ -12779,7 +12848,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D1FIFOSEL_b; }; @@ -13054,14 +13123,13 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure union { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ struct { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; + uint16_t : 15; __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; + } DVCHGR_b; }; union @@ -13074,8 +13142,8 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * the USB address assigned by the host when the USBHS processed * the SET_ADDRESS request successfully. */ uint16_t : 1; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; } USBADDR_b; }; __IM uint16_t RESERVED9; @@ -13784,6 +13852,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_AGTX7_BASE 0x40084700UL #define R_AGTX8_BASE 0x40084800UL #define R_AGTX9_BASE 0x40084900UL + #define R_WDT1_BASE 0x40044300UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -13898,6 +13967,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -15951,9 +16021,14 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================= DMAST ========================================================= */ #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* ======================================================== DMECHR ========================================================= */ #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ @@ -15963,11 +16038,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -16539,6 +16609,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -16562,6 +16634,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -16601,9 +16675,15 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -16678,7 +16758,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -16715,8 +16801,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -16902,6 +16986,24 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ @@ -19646,14 +19748,12 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== UFRMNUM ======================================================== */ - #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ /* ======================================================== USBADDR ======================================================== */ #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ /* ======================================================== USBREQ ========================================================= */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h index 92c09d331..01dfd6381 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h @@ -2113,7 +2113,7 @@ typedef struct /*!< (@ 0x40170000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -2126,7 +2126,7 @@ typedef struct /*!< (@ 0x40170000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -4485,8 +4485,8 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure struct { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ uint32_t : 7; __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ @@ -6689,7 +6689,8 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -6736,7 +6737,8 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -6747,7 +6749,10 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -6764,24 +6769,26 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -6825,12 +6832,24 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -7307,7 +7326,57 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -13612,7 +13681,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * data. */ uint16_t : 1; __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ } CFIFOCTR_b; }; @@ -13632,7 +13701,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D0FIFOSEL_b; }; @@ -13666,7 +13735,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D1FIFOSEL_b; }; @@ -13941,14 +14010,13 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure union { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ struct { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; + uint16_t : 15; __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; + } DVCHGR_b; }; union @@ -13961,8 +14029,8 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * the USB address assigned by the host when the USBHS processed * the SET_ADDRESS request successfully. */ uint16_t : 1; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; } USBADDR_b; }; __IM uint16_t RESERVED9; @@ -15211,6 +15279,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGTX8_BASE 0x400E8800UL #define R_AGTX9_BASE 0x400E8900UL #define R_FLAD_BASE 0x407FC000UL + #define R_WDT1_BASE 0x40044300UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -15328,6 +15397,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -17337,9 +17407,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================= DMAST ========================================================= */ #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* ======================================================== DMECHR ========================================================= */ #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ @@ -17349,11 +17424,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -18170,6 +18240,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -18193,6 +18265,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -18232,9 +18306,15 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -18309,7 +18389,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -18346,8 +18432,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -18533,6 +18617,24 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ @@ -21531,14 +21633,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== UFRMNUM ======================================================== */ - #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ /* ======================================================== USBADDR ======================================================== */ #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ /* ======================================================== USBREQ ========================================================= */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E2BB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E2BB.h index 08053ff9e..fe59ca6ad 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E2BB.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E2BB.h @@ -2568,7 +2568,7 @@ typedef struct /*!< (@ 0x40170000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -2581,7 +2581,7 @@ typedef struct /*!< (@ 0x40170000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -4405,8 +4405,8 @@ typedef struct /*!< (@ 0x400B0000) R_CANFD0 Structure struct { - __IM uint32_t RFXIF : 1; /*!< [0..0] RX FIFO[x] Interrupt Flag Status */ - uint32_t : 31; + __IM uint32_t RFXIF : 2; /*!< [1..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 30; } CFDRFISTS_b; }; @@ -5098,8 +5098,8 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure struct { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ uint32_t : 7; __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ @@ -6574,7 +6574,8 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -6621,7 +6622,8 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -6632,7 +6634,10 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -6649,24 +6654,26 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -6710,12 +6717,24 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -7192,7 +7211,57 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -8168,20 +8237,25 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure union { - __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ struct { - __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ - __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ - __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ - __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ - __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ - __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ - __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ - uint32_t : 9; - __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ - uint32_t : 15; + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 2; + __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset */ + __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese */ + __IOM uint32_t HTDBRST : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset */ + __IOM uint32_t HRDBRST : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset */ + uint32_t : 3; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; } RSTCTL_b; }; @@ -8311,8 +8385,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ uint32_t : 8; __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ - __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */ - uint32_t : 15; + __IOM uint32_t SVAEn : 3; /*!< [18..16] Slave Address Enable */ + uint32_t : 13; } SVCTL_b; }; __IM uint32_t RESERVED6[2]; @@ -8354,7 +8428,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ uint32_t : 2; - __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */ + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull */ uint32_t : 2; } EXTBR_b; }; @@ -8508,7 +8582,57 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ } SVTDLG0_b; }; - __IM uint32_t RESERVED11[31]; + __IM uint32_t RESERVED11[23]; + + union + { + __IOM uint32_t STCTL; /*!< (@ 0x00000120) Synchronous Timing Control Register */ + + struct + { + __IOM uint32_t STOE : 1; /*!< [0..0] Synchronous Timing output Enable */ + uint32_t : 31; + } STCTL_b; + }; + + union + { + __IOM uint32_t ATCTL; /*!< (@ 0x00000124) Asynchronous Timing Control Register */ + + struct + { + __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select */ + __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow) */ + __IOM uint32_t AMEOE : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable */ + uint32_t : 5; + __IOM uint32_t CDIV : 8; /*!< [15..8] TCLK Counter Divide Setting */ + uint32_t : 16; + } ATCTL_b; + }; + + union + { + __IOM uint32_t ATTRG; /*!< (@ 0x00000128) Asynchronous Timing Trigger Register */ + + struct + { + __OM uint32_t ATSTRG : 1; /*!< [0..0] Asynchronous Timing Software Trigger */ + uint32_t : 31; + } ATTRG_b; + }; + + union + { + __IOM uint32_t ATCCNTE; /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register */ + + struct + { + __IOM uint32_t ATCE : 1; /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1, + * SC2. */ + uint32_t : 31; + } ATCCNTE_b; + }; + __IM uint32_t RESERVED12[4]; union { @@ -8522,14 +8646,43 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 29; } CNDCTL_b; }; - __IM uint32_t RESERVED12[3]; + __IM uint32_t RESERVED13[3]; __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ - __IM uint32_t RESERVED13[8]; + __IM uint32_t RESERVED14[8]; __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ - __IM uint32_t RESERVED14[3]; + + union + { + __OM uint32_t HCMDQP; /*!< (@ 0x00000184) High Priority Command Queue Port Register */ + + struct + { + __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port */ + } HCMDQP_b; + }; + + union + { + __IM uint32_t HRSPQP; /*!< (@ 0x00000188) High Priority Response Queue Port Register */ + + struct + { + __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port */ + } HRSPQP_b; + }; + + union + { + __IOM uint32_t HTDTBP; /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register */ + + struct + { + __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port */ + } HTDTBP_b; + }; union { @@ -8574,7 +8727,37 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } NRQTHCTL_b; }; - __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t HQTHCTL; /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold */ + uint32_t : 16; + } HQTHCTL_b; + }; + + union + { + __IOM uint32_t HTBTHCTL; /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold + * Control Register */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold */ + uint32_t : 5; + } HTBTHCTL_b; + }; + __IM uint32_t RESERVED16; union { @@ -8747,7 +8930,79 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 11; } NTSTFC_b; }; - __IM uint32_t RESERVED17[8]; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint32_t HTST; /*!< (@ 0x00000200) High Priority Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag */ + __IOM uint32_t RDBFF : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag */ + uint32_t : 1; + __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] High Priority Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] High Priority Transfer Error Flag */ + uint32_t : 22; + } HTST_b; + }; + + union + { + __IOM uint32_t HTSTE; /*!< (@ 0x00000204) High Priority Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable */ + __IOM uint32_t RDBFE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] High Priority Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] High Priority Transfer Error Enable */ + uint32_t : 22; + } HTSTE_b; + }; + + union + { + __IOM uint32_t HTIE; /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable */ + __IOM uint32_t RDBFIE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable */ + uint32_t : 22; + } HTIE_b; + }; + + union + { + __IOM uint32_t HTSTFC; /*!< (@ 0x0000020C) High Priority Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force */ + __OM uint32_t RDBFFC : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force */ + uint32_t : 1; + __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] High Priority Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] High Priority Transfer Error Force */ + uint32_t : 22; + } HTSTFC_b; + }; union { @@ -8774,22 +9029,32 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ uint32_t : 8; __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ - __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */ - uint32_t : 15; + __IOM uint32_t SVAFn : 3; /*!< [18..16] Slave Address Detection Flag */ + uint32_t : 13; } SVST_b; }; union { - __IOM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Control Register */ + __IM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Operating Status Register */ struct { - __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ - uint32_t : 31; + __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; } WUST_b; }; - __IM uint32_t RESERVED18[2]; + + union + { + __IM uint32_t MRCCPT; /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register */ + + struct + { + __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture */ + } MRCCPT_b; + }; + __IM uint32_t RESERVED18; union { @@ -8869,7 +9134,87 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ } DATBAS3_b; }; - __IM uint32_t RESERVED22[24]; + __IM uint32_t RESERVED22; + + union + { + __IOM uint32_t DATBAS4; /*!< (@ 0x00000244) Device Address Table Basic Register 4 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS4_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IOM uint32_t DATBAS5; /*!< (@ 0x0000024C) Device Address Table Basic Register 5 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS5_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t DATBAS6; /*!< (@ 0x00000254) Device Address Table Basic Register 6 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS6_b; + }; + __IM uint32_t RESERVED25; + + union + { + __IOM uint32_t DATBAS7; /*!< (@ 0x0000025C) Device Address Table Basic Register 7 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS7_b; + }; + __IM uint32_t RESERVED26[16]; union { @@ -8885,7 +9230,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ } EXDATBAS_b; }; - __IM uint32_t RESERVED23[3]; + __IM uint32_t RESERVED27[3]; union { @@ -8934,7 +9279,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 9; } SDATBAS2_b; }; - __IM uint32_t RESERVED24[5]; + __IM uint32_t RESERVED28[5]; union { @@ -9007,7 +9352,79 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 16; } MSDCT3_b; }; - __IM uint32_t RESERVED25[16]; + + union + { + __IOM uint32_t MSDCT4; /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT4_b; + }; + + union + { + __IOM uint32_t MSDCT5; /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT5_b; + }; + + union + { + __IOM uint32_t MSDCT6; /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT6_b; + }; + + union + { + __IOM uint32_t MSDCT7; /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT7_b; + }; + __IM uint32_t RESERVED29[12]; union { @@ -9030,7 +9447,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure * ID Low Register */ __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional * ID High Register */ - __IM uint32_t RESERVED26; + __IM uint32_t RESERVED30; union { @@ -9047,7 +9464,39 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ } SVDVAD0_b; }; - __IM uint32_t RESERVED27[7]; + + union + { + __IM uint32_t SVDVAD1; /*!< (@ 0x00000334) Slave Device Address Register 1 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD1_b; + }; + + union + { + __IM uint32_t SVDVAD2; /*!< (@ 0x00000338) Slave Device Address Register 2 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD2_b; + }; + __IM uint32_t RESERVED31[5]; union { @@ -9160,18 +9609,35 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure union { - __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) - * Register */ + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ struct { - uint32_t : 8; - __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ - __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ - uint32_t : 8; + __IOM uint32_t SPTSYN : 1; /*!< [0..0] Supports Sync Mode */ + __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0 */ + __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1 */ + uint32_t : 5; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; } CETSM_b; }; - __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t CETSS; /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State) + * Register */ + + struct + { + __IOM uint32_t SYNE : 1; /*!< [0..0] Sync Mode Enabled */ + __IOM uint32_t ASYNE : 2; /*!< [2..1] Async Mode Enabled */ + uint32_t : 4; + __IOM uint32_t ICOVF : 1; /*!< [7..7] Internal Counter Overflow */ + uint32_t : 24; + } CETSS_b; + }; union { @@ -9198,7 +9664,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } BITCNT_b; }; - __IM uint32_t RESERVED29[4]; + __IM uint32_t RESERVED32[4]; union { @@ -9216,7 +9682,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure union { - __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */ + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0 */ struct { @@ -9225,7 +9691,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 16; } NDBSTLV0_b; }; - __IM uint32_t RESERVED30[9]; + __IM uint32_t RESERVED33[9]; union { @@ -9237,7 +9703,30 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } NRSQSTLV_b; }; - __IM uint32_t RESERVED31[2]; + + union + { + __IM uint32_t HQSTLV; /*!< (@ 0x000003C4) High Priority Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQLV : 8; /*!< [7..0] High Priority Command Queue Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] High Priority Response Queue Level */ + uint32_t : 16; + } HQSTLV_b; + }; + + union + { + __IM uint32_t HDBSTLV; /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] High Priority Tx Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] High Priority Rx Data Buffer Level */ + uint32_t : 16; + } HDBSTLV_b; + }; union { @@ -9263,7 +9752,30 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } MSERRCNT_b; }; -} R_I3C0_Type; /*!< Size = 980 (0x3d4) */ + __IM uint32_t RESERVED34[3]; + + union + { + __IM uint32_t SC1CPT; /*!< (@ 0x000003E0) SC1 Capture monitor Register */ + + struct + { + __IM uint32_t SC1C : 16; /*!< [15..0] SC1 Capture */ + uint32_t : 16; + } SC1CPT_b; + }; + + union + { + __IM uint32_t SC2CPT; /*!< (@ 0x000003E4) SC2 Capture monitor Register */ + + struct + { + __IM uint32_t SC2C : 16; /*!< [15..0] SC2 Capture */ + uint32_t : 16; + } SC2CPT_b; + }; +} R_I3C0_Type; /*!< Size = 1000 (0x3e8) */ /* =========================================================================================================================== */ /* ================ R_MPU_MMPU ================ */ @@ -14326,7 +14838,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * data. */ uint16_t : 1; __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ } CFIFOCTR_b; }; @@ -14346,7 +14858,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D0FIFOSEL_b; }; @@ -14380,7 +14892,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D1FIFOSEL_b; }; @@ -14655,14 +15167,13 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure union { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ struct { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; + uint16_t : 15; __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; + } DVCHGR_b; }; union @@ -14675,8 +15186,8 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * the USB address assigned by the host when the USBHS processed * the SET_ADDRESS request successfully. */ uint16_t : 1; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; } USBADDR_b; }; __IM uint16_t RESERVED9; @@ -16140,6 +16651,81 @@ typedef struct /*!< (@ 0x400E8000) R_AGTX0 Structure }; } R_AGTX0_Type; /*!< Size = 20 (0x14) */ +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CANFD ECC (R_ECCMB0) + */ + +typedef struct /*!< (@ 0x4036F200) R_ECCMB0 Structure */ +{ + union + { + __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ + + struct + { + __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Message Flag */ + __IM uint32_t ECER1F : 1; /*!< [1..1] ECC Error Detection and Correction Flag */ + __IM uint32_t ECER2F : 1; /*!< [2..2] 2-bit ECC Error Detection Flag */ + __IOM uint32_t EC1EDIC : 1; /*!< [3..3] ECC 1-bit Error Detection Interrupt Control */ + __IOM uint32_t EC2EDIC : 1; /*!< [4..4] ECC 2-bit Error Detection Interrupt Control */ + __IOM uint32_t EC1ECP : 1; /*!< [5..5] ECC 1-bit Error Correction Permission */ + __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Judgment Enable Flag */ + uint32_t : 2; + __IOM uint32_t ECER1C : 1; /*!< [9..9] Accumulating ECC Error Detection and Correction Flag + * Clear */ + __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-bit ECC Error Detection Flag Clear */ + __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Overflow Detection Flag */ + uint32_t : 2; + __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Select bit */ + __IM uint32_t ECSEDF0 : 1; /*!< [16..16] ECC Single bit Error Address Detection Flag */ + __IM uint32_t ECDEDF0 : 1; /*!< [17..17] ECC Dual Bit Error Address Detection Flag */ + uint32_t : 14; + } EC710CTL_b; + }; + + union + { + __IOM uint16_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ + uint16_t : 5; + __IOM uint16_t ECTMCE : 1; /*!< [7..7] ECC Test Mode Control Enable */ + uint16_t : 6; + __IOM uint16_t ETMA : 2; /*!< [15..14] ECC Test Mode Bit Access Control */ + } EC710TMC_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Test Substitute Data Register */ + + struct + { + __IOM uint32_t ECEDB : 32; /*!< [31..0] ECC Test Substitute Data */ + } EC710TED_b; + }; + + union + { + __IM uint32_t EC710EAD0; /*!< (@ 0x00000010) ECC Error Address Register */ + + struct + { + __IM uint32_t ECEAD : 10; /*!< [9..0] ECC Error Address */ + uint32_t : 22; + } EC710EAD0_b; + }; +} R_ECCMB0_Type; /*!< Size = 20 (0x14) */ + /* =========================================================================================================================== */ /* ================ R_FLAD ================ */ /* =========================================================================================================================== */ @@ -16281,7 +16867,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGTX7_BASE 0x400E8700UL #define R_AGTX8_BASE 0x400E8800UL #define R_AGTX9_BASE 0x400E8900UL + #define R_ECCMB0_BASE 0x4036F200UL + #define R_ECCMB1_BASE 0x4036F300UL #define R_FLAD_BASE 0x407FC000UL + #define R_WDT1_BASE 0x40044300UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -16402,7 +16991,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGTW7 ((R_AGTX0_Type *) R_AGTX7_BASE) #define R_AGTW8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGTW9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_ECCMB0 ((R_ECCMB0_Type *) R_ECCMB0_BASE) + #define R_ECCMB1 ((R_ECCMB0_Type *) R_ECCMB1_BASE) #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -18391,7 +18983,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x100UL) /*!< CFXMLT (Bitfield-Mask: 0x01) */ /* ======================================================= CFDRFISTS ======================================================= */ #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ - #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x1UL) /*!< RFXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x3UL) /*!< RFXIF (Bitfield-Mask: 0x03) */ /* ======================================================== CFDTMC ========================================================= */ #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ @@ -18637,9 +19229,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================= DMAST ========================================================= */ #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* ======================================================== DMECHR ========================================================= */ #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ @@ -18649,11 +19246,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -19176,6 +19768,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -19199,6 +19793,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -19238,9 +19834,15 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -19315,7 +19917,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -19352,8 +19960,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -19539,6 +20145,24 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ @@ -20184,6 +20808,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HCMDQRST_Pos (9UL) /*!< HCMDQRST (Bit 9) */ + #define R_I3C0_RSTCTL_HCMDQRST_Msk (0x200UL) /*!< HCMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRSPQRST_Pos (10UL) /*!< HRSPQRST (Bit 10) */ + #define R_I3C0_RSTCTL_HRSPQRST_Msk (0x400UL) /*!< HRSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HTDBRST_Pos (11UL) /*!< HTDBRST (Bit 11) */ + #define R_I3C0_RSTCTL_HTDBRST_Msk (0x800UL) /*!< HTDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRDBRST_Pos (12UL) /*!< HRDBRST (Bit 12) */ + #define R_I3C0_RSTCTL_HRDBRST_Msk (0x1000UL) /*!< HRDBRST (Bitfield-Mask: 0x01) */ #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ /* ========================================================= PRSST ========================================================= */ @@ -20240,7 +20872,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ - #define R_I3C0_SVCTL_SVAEn_Msk (0x10000UL) /*!< SVAEn (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_SVAEn_Msk (0x70000UL) /*!< SVAEn (Bitfield-Mask: 0x07) */ /* ======================================================= REFCKCTL ======================================================== */ #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ @@ -20335,6 +20967,24 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================== SVTDLG0 ======================================================== */ #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= STCTL ========================================================= */ + #define R_I3C0_STCTL_STOE_Pos (0UL) /*!< STOE (Bit 0) */ + #define R_I3C0_STCTL_STOE_Msk (0x1UL) /*!< STOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ATCTL ========================================================= */ + #define R_I3C0_ATCTL_ATTRGS_Pos (0UL) /*!< ATTRGS (Bit 0) */ + #define R_I3C0_ATCTL_ATTRGS_Msk (0x1UL) /*!< ATTRGS (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_MREFOE_Pos (1UL) /*!< MREFOE (Bit 1) */ + #define R_I3C0_ATCTL_MREFOE_Msk (0x2UL) /*!< MREFOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_AMEOE_Pos (2UL) /*!< AMEOE (Bit 2) */ + #define R_I3C0_ATCTL_AMEOE_Msk (0x4UL) /*!< AMEOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_CDIV_Pos (8UL) /*!< CDIV (Bit 8) */ + #define R_I3C0_ATCTL_CDIV_Msk (0xff00UL) /*!< CDIV (Bitfield-Mask: 0xff) */ +/* ========================================================= ATTRG ========================================================= */ + #define R_I3C0_ATTRG_ATSTRG_Pos (0UL) /*!< ATSTRG (Bit 0) */ + #define R_I3C0_ATTRG_ATSTRG_Msk (0x1UL) /*!< ATSTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== ATCCNTE ======================================================== */ + #define R_I3C0_ATCCNTE_ATCE_Pos (0UL) /*!< ATCE (Bit 0) */ + #define R_I3C0_ATCCNTE_ATCE_Msk (0x1UL) /*!< ATCE (Bitfield-Mask: 0x01) */ /* ======================================================== CNDCTL ========================================================= */ #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ @@ -20347,6 +20997,15 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================== NTDTBP0 ======================================================== */ /* ======================================================== NIBIQP ========================================================= */ /* ========================================================= NRSQP ========================================================= */ +/* ======================================================== HCMDQP ========================================================= */ + #define R_I3C0_HCMDQP_HCMDQP_Pos (0UL) /*!< HCMDQP (Bit 0) */ + #define R_I3C0_HCMDQP_HCMDQP_Msk (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HRSPQP ========================================================= */ + #define R_I3C0_HRSPQP_HRSPQP_Pos (0UL) /*!< HRSPQP (Bit 0) */ + #define R_I3C0_HRSPQP_HRSPQP_Msk (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HTDTBP ========================================================= */ + #define R_I3C0_HTDTBP_HTDTBP_Pos (0UL) /*!< HTDTBP (Bit 0) */ + #define R_I3C0_HTDTBP_HTDTBP_Msk (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff) */ /* ======================================================== NQTHCTL ======================================================== */ #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ @@ -20368,6 +21027,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= NRQTHCTL ======================================================== */ #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ +/* ======================================================== HQTHCTL ======================================================== */ + #define R_I3C0_HQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_HQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_HQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= HTBTHCTL ======================================================== */ + #define R_I3C0_HTBTHCTL_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_HTBTHCTL_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ /* ========================================================== BST ========================================================== */ #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ @@ -20504,6 +21177,58 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ +/* ========================================================= HTST ========================================================== */ + #define R_I3C0_HTST_TDBEF_Pos (0UL) /*!< TDBEF (Bit 0) */ + #define R_I3C0_HTST_TDBEF_Msk (0x1UL) /*!< TDBEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RDBFF_Pos (1UL) /*!< RDBFF (Bit 1) */ + #define R_I3C0_HTST_RDBFF_Msk (0x2UL) /*!< RDBFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_HTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_HTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_HTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_HTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ +/* ========================================================= HTSTE ========================================================= */ + #define R_I3C0_HTSTE_TDBEE_Pos (0UL) /*!< TDBEE (Bit 0) */ + #define R_I3C0_HTSTE_TDBEE_Msk (0x1UL) /*!< TDBEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RDBFE_Pos (1UL) /*!< RDBFE (Bit 1) */ + #define R_I3C0_HTSTE_RDBFE_Msk (0x2UL) /*!< RDBFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_HTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_HTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_HTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_HTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ +/* ========================================================= HTIE ========================================================== */ + #define R_I3C0_HTIE_TDBEIE_Pos (0UL) /*!< TDBEIE (Bit 0) */ + #define R_I3C0_HTIE_TDBEIE_Msk (0x1UL) /*!< TDBEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RDBFIE_Pos (1UL) /*!< RDBFIE (Bit 1) */ + #define R_I3C0_HTIE_RDBFIE_Msk (0x2UL) /*!< RDBFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_HTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_HTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_HTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_HTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== HTSTFC ========================================================= */ + #define R_I3C0_HTSTFC_TDBEFC_Pos (0UL) /*!< TDBEFC (Bit 0) */ + #define R_I3C0_HTSTFC_TDBEFC_Msk (0x1UL) /*!< TDBEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RDBFFC_Pos (1UL) /*!< RDBFFC (Bit 1) */ + #define R_I3C0_HTSTFC_RDBFFC_Msk (0x2UL) /*!< RDBFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_HTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_HTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_HTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_HTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ /* ========================================================= BCST ========================================================== */ #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ @@ -20521,10 +21246,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ - #define R_I3C0_SVST_SVAFn_Msk (0x10000UL) /*!< SVAFn (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_SVAFn_Msk (0x70000UL) /*!< SVAFn (Bitfield-Mask: 0x07) */ /* ========================================================= WUST ========================================================== */ #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCCPT ========================================================= */ + #define R_I3C0_MRCCPT_MRCCPT_Pos (0UL) /*!< MRCCPT (Bit 0) */ + #define R_I3C0_MRCCPT_MRCCPT_Msk (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff) */ /* ======================================================== DATBAS0 ======================================================== */ #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ @@ -20593,6 +21321,74 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS4 ======================================================== */ + #define R_I3C0_DATBAS4_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS4_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS4_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS4_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS4_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS4_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS4_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS4_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS4_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS4_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS4_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS5 ======================================================== */ + #define R_I3C0_DATBAS5_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS5_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS5_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS5_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS5_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS5_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS5_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS5_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS5_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS5_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS5_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS6 ======================================================== */ + #define R_I3C0_DATBAS6_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS6_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS6_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS6_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS6_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS6_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS6_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS6_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS6_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS6_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS6_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS7 ======================================================== */ + #define R_I3C0_DATBAS7_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS7_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS7_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS7_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS7_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS7_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS7_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS7_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS7_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS7_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS7_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ /* ======================================================= EXDATBAS ======================================================== */ #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ @@ -20689,6 +21485,66 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT4 ========================================================= */ + #define R_I3C0_MSDCT4_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT4_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT4_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT4_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT4_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT4_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT4_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT4_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT5 ========================================================= */ + #define R_I3C0_MSDCT5_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT5_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT5_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT5_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT5_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT5_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT5_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT5_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT6 ========================================================= */ + #define R_I3C0_MSDCT6_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT6_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT6_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT6_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT6_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT6_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT6_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT6_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT7 ========================================================= */ + #define R_I3C0_MSDCT7_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT7_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT7_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT7_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT7_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT7_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT7_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT7_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ========================================================= SVDCT ========================================================= */ #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ @@ -20717,6 +21573,24 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD1 ======================================================== */ + #define R_I3C0_SVDVAD1_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD1_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD1_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD1_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD1_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD1_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD2 ======================================================== */ + #define R_I3C0_SVDVAD2_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD2_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD2_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD2_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD2_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD2_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ /* ======================================================== CSECMD ========================================================= */ #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ @@ -20761,10 +21635,23 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ /* ========================================================= CETSM ========================================================= */ + #define R_I3C0_CETSM_SPTSYN_Pos (0UL) /*!< SPTSYN (Bit 0) */ + #define R_I3C0_CETSM_SPTSYN_Msk (0x1UL) /*!< SPTSYN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN0_Pos (1UL) /*!< SPTASYN0 (Bit 1) */ + #define R_I3C0_CETSM_SPTASYN0_Msk (0x2UL) /*!< SPTASYN0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN1_Pos (2UL) /*!< SPTASYN1 (Bit 2) */ + #define R_I3C0_CETSM_SPTASYN1_Msk (0x4UL) /*!< SPTASYN1 (Bitfield-Mask: 0x01) */ #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ========================================================= CETSS ========================================================= */ + #define R_I3C0_CETSS_SYNE_Pos (0UL) /*!< SYNE (Bit 0) */ + #define R_I3C0_CETSS_SYNE_Msk (0x1UL) /*!< SYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSS_ASYNE_Pos (1UL) /*!< ASYNE (Bit 1) */ + #define R_I3C0_CETSS_ASYNE_Msk (0x6UL) /*!< ASYNE (Bitfield-Mask: 0x03) */ + #define R_I3C0_CETSS_ICOVF_Pos (7UL) /*!< ICOVF (Bit 7) */ + #define R_I3C0_CETSS_ICOVF_Msk (0x80UL) /*!< ICOVF (Bitfield-Mask: 0x01) */ /* ======================================================= CGHDRCAP ======================================================== */ #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ @@ -20794,6 +21681,16 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= NRSQSTLV ======================================================== */ #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HQSTLV ========================================================= */ + #define R_I3C0_HQSTLV_CMDQLV_Pos (0UL) /*!< CMDQLV (Bit 0) */ + #define R_I3C0_HQSTLV_CMDQLV_Msk (0xffUL) /*!< CMDQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_HQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HDBSTLV ======================================================== */ + #define R_I3C0_HDBSTLV_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_HDBSTLV_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HDBSTLV_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_HDBSTLV_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ /* ======================================================== PRSTDBG ======================================================== */ #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ @@ -20806,6 +21703,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= MSERRCNT ======================================================== */ #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ +/* ======================================================== SC1CPT ========================================================= */ + #define R_I3C0_SC1CPT_SC1C_Pos (0UL) /*!< SC1C (Bit 0) */ + #define R_I3C0_SC1CPT_SC1C_Msk (0xffffUL) /*!< SC1C (Bitfield-Mask: 0xffff) */ +/* ======================================================== SC2CPT ========================================================= */ + #define R_I3C0_SC2CPT_SC2C_Pos (0UL) /*!< SC2C (Bit 0) */ + #define R_I3C0_SC2CPT_SC2C_Msk (0xffffUL) /*!< SC2C (Bitfield-Mask: 0xffff) */ /* =========================================================================================================================== */ /* ================ R_MPU_MMPU ================ */ @@ -23042,14 +23945,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== UFRMNUM ======================================================== */ - #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ /* ======================================================== USBADDR ======================================================== */ #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ /* ======================================================== USBREQ ========================================================= */ @@ -23720,6 +24621,51 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ R_AGTX0 ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= EC710CTL ======================================================== */ + #define R_ECCMB0_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ + #define R_ECCMB0_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ + #define R_ECCMB0_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ + #define R_ECCMB0_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ + #define R_ECCMB0_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ + #define R_ECCMB0_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ + #define R_ECCMB0_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ + #define R_ECCMB0_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Pos (16UL) /*!< ECSEDF0 (Bit 16) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Msk (0x10000UL) /*!< ECSEDF0 (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Pos (17UL) /*!< ECDEDF0 (Bit 17) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Msk (0x20000UL) /*!< ECDEDF0 (Bitfield-Mask: 0x01) */ +/* ======================================================= EC710TMC ======================================================== */ + #define R_ECCMB0_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ + #define R_ECCMB0_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ + #define R_ECCMB0_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ +/* ======================================================= EC710TED ======================================================== */ + #define R_ECCMB0_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ + #define R_ECCMB0_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EC710EAD0 ======================================================= */ + #define R_ECCMB0_EC710EAD0_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ + #define R_ECCMB0_EC710EAD0_ECEAD_Msk (0x3ffUL) /*!< ECEAD (Bitfield-Mask: 0x3ff) */ + /* =========================================================================================================================== */ /* ================ R_FLAD ================ */ /* =========================================================================================================================== */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h index a863332a3..cc5bdb30d 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h @@ -1986,7 +1986,31 @@ typedef struct /*!< (@ 0x40085000) R_ACMPHS0 Structure __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ } CPIOC_b; }; -} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ + __IM uint8_t RESERVED4[47]; + + union + { + __IOM uint8_t CPINTCTL; /*!< (@ 0x00000040) Comparator Interrupt Control Register */ + + struct + { + __IOM uint8_t MSKE : 1; /*!< [0..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 7; + } CPINTCTL_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t CPMSKCTL; /*!< (@ 0x00000044) Comparator Interrupt Mask Control Register */ + + struct + { + __IOM uint8_t MSKSEL : 3; /*!< [2..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 5; + } CPMSKCTL_b; + }; +} R_ACMPHS0_Type; /*!< Size = 69 (0x45) */ /* =========================================================================================================================== */ /* ================ R_ADC0 ================ */ @@ -2249,7 +2273,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -2262,7 +2286,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -4640,8 +4664,8 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure struct { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ uint32_t : 7; __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ @@ -6116,7 +6140,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -6163,7 +6188,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -6174,7 +6200,10 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -6191,24 +6220,26 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -6252,12 +6283,24 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -6734,7 +6777,57 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -13423,7 +13516,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * data. */ uint16_t : 1; __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ } CFIFOCTR_b; }; @@ -13443,7 +13536,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D0FIFOSEL_b; }; @@ -13477,7 +13570,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D1FIFOSEL_b; }; @@ -13752,14 +13845,13 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure union { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ struct { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; + uint16_t : 15; __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; + } DVCHGR_b; }; union @@ -13772,8 +13864,8 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * the USB address assigned by the host when the USBHS processed * the SET_ADDRESS request successfully. */ uint16_t : 1; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; } USBADDR_b; }; __IM uint16_t RESERVED9; @@ -15482,6 +15574,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_AGTX7_BASE 0x40084700UL #define R_AGTX8_BASE 0x40084800UL #define R_AGTX9_BASE 0x40084900UL + #define R_WDT1_BASE 0x40044300UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -15609,6 +15702,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -16402,32 +16496,38 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== CMPCTL ========================================================= */ - #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ - #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ - #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ - #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ - #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ - #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ - #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ - #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ - #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ /* ======================================================== CMPSEL0 ======================================================== */ - #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ - #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ /* ======================================================== CMPSEL1 ======================================================== */ - #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ - #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ /* ======================================================== CMPMON ========================================================= */ - #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ - #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ /* ========================================================= CPIOC ========================================================= */ - #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ - #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ - #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPINTCTL ======================================================== */ + #define R_ACMPHS0_CPINTCTL_MSKE_Pos (0UL) /*!< MSKE (Bit 0) */ + #define R_ACMPHS0_CPINTCTL_MSKE_Msk (0x1UL) /*!< MSKE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPMSKCTL ======================================================== */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Pos (0UL) /*!< MSKSEL (Bit 0) */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Msk (0x7UL) /*!< MSKSEL (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_ADC0 ================ */ @@ -17618,9 +17718,14 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================= DMAST ========================================================= */ #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* ======================================================== DMECHR ========================================================= */ #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ @@ -17630,11 +17735,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -18157,6 +18257,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -18180,6 +18282,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -18219,9 +18323,15 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -18296,7 +18406,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -18333,8 +18449,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -18520,6 +18634,24 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ @@ -21733,14 +21865,12 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== UFRMNUM ======================================================== */ - #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ /* ======================================================== USBADDR ======================================================== */ #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ /* ======================================================== USBREQ ========================================================= */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h index ba558caba..4a2538f23 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h @@ -1986,7 +1986,31 @@ typedef struct /*!< (@ 0x40085000) R_ACMPHS0 Structure __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ } CPIOC_b; }; -} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ + __IM uint8_t RESERVED4[47]; + + union + { + __IOM uint8_t CPINTCTL; /*!< (@ 0x00000040) Comparator Interrupt Control Register */ + + struct + { + __IOM uint8_t MSKE : 1; /*!< [0..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 7; + } CPINTCTL_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t CPMSKCTL; /*!< (@ 0x00000044) Comparator Interrupt Mask Control Register */ + + struct + { + __IOM uint8_t MSKSEL : 3; /*!< [2..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 5; + } CPMSKCTL_b; + }; +} R_ACMPHS0_Type; /*!< Size = 69 (0x45) */ /* =========================================================================================================================== */ /* ================ R_ADC0 ================ */ @@ -2249,7 +2273,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -2262,7 +2286,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -4640,8 +4664,8 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure struct { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ uint32_t : 7; __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ @@ -6844,7 +6868,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -6891,7 +6916,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -6902,7 +6928,10 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -6919,24 +6948,26 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -6980,12 +7011,24 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -7462,7 +7505,57 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -8570,20 +8663,25 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure union { - __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ struct { - __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ - __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ - __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ - __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ - __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ - __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ - __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ - uint32_t : 9; - __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ - uint32_t : 15; + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 2; + __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset */ + __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese */ + __IOM uint32_t HTDBRST : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset */ + __IOM uint32_t HRDBRST : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset */ + uint32_t : 3; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; } RSTCTL_b; }; @@ -8713,8 +8811,8 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ uint32_t : 8; __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ - __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */ - uint32_t : 15; + __IOM uint32_t SVAEn : 3; /*!< [18..16] Slave Address Enable */ + uint32_t : 13; } SVCTL_b; }; __IM uint32_t RESERVED6[2]; @@ -8756,7 +8854,7 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ uint32_t : 2; - __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */ + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull */ uint32_t : 2; } EXTBR_b; }; @@ -8910,7 +9008,57 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ } SVTDLG0_b; }; - __IM uint32_t RESERVED11[31]; + __IM uint32_t RESERVED11[23]; + + union + { + __IOM uint32_t STCTL; /*!< (@ 0x00000120) Synchronous Timing Control Register */ + + struct + { + __IOM uint32_t STOE : 1; /*!< [0..0] Synchronous Timing output Enable */ + uint32_t : 31; + } STCTL_b; + }; + + union + { + __IOM uint32_t ATCTL; /*!< (@ 0x00000124) Asynchronous Timing Control Register */ + + struct + { + __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select */ + __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow) */ + __IOM uint32_t AMEOE : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable */ + uint32_t : 5; + __IOM uint32_t CDIV : 8; /*!< [15..8] TCLK Counter Divide Setting */ + uint32_t : 16; + } ATCTL_b; + }; + + union + { + __IOM uint32_t ATTRG; /*!< (@ 0x00000128) Asynchronous Timing Trigger Register */ + + struct + { + __OM uint32_t ATSTRG : 1; /*!< [0..0] Asynchronous Timing Software Trigger */ + uint32_t : 31; + } ATTRG_b; + }; + + union + { + __IOM uint32_t ATCCNTE; /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register */ + + struct + { + __IOM uint32_t ATCE : 1; /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1, + * SC2. */ + uint32_t : 31; + } ATCCNTE_b; + }; + __IM uint32_t RESERVED12[4]; union { @@ -8924,14 +9072,43 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure uint32_t : 29; } CNDCTL_b; }; - __IM uint32_t RESERVED12[3]; + __IM uint32_t RESERVED13[3]; __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ - __IM uint32_t RESERVED13[8]; + __IM uint32_t RESERVED14[8]; __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ - __IM uint32_t RESERVED14[3]; + + union + { + __OM uint32_t HCMDQP; /*!< (@ 0x00000184) High Priority Command Queue Port Register */ + + struct + { + __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port */ + } HCMDQP_b; + }; + + union + { + __IM uint32_t HRSPQP; /*!< (@ 0x00000188) High Priority Response Queue Port Register */ + + struct + { + __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port */ + } HRSPQP_b; + }; + + union + { + __IOM uint32_t HTDTBP; /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register */ + + struct + { + __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port */ + } HTDTBP_b; + }; union { @@ -8976,7 +9153,37 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure uint32_t : 24; } NRQTHCTL_b; }; - __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t HQTHCTL; /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold */ + uint32_t : 16; + } HQTHCTL_b; + }; + + union + { + __IOM uint32_t HTBTHCTL; /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold + * Control Register */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold */ + uint32_t : 5; + } HTBTHCTL_b; + }; + __IM uint32_t RESERVED16; union { @@ -9149,7 +9356,79 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure uint32_t : 11; } NTSTFC_b; }; - __IM uint32_t RESERVED17[8]; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint32_t HTST; /*!< (@ 0x00000200) High Priority Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag */ + __IOM uint32_t RDBFF : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag */ + uint32_t : 1; + __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] High Priority Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] High Priority Transfer Error Flag */ + uint32_t : 22; + } HTST_b; + }; + + union + { + __IOM uint32_t HTSTE; /*!< (@ 0x00000204) High Priority Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable */ + __IOM uint32_t RDBFE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] High Priority Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] High Priority Transfer Error Enable */ + uint32_t : 22; + } HTSTE_b; + }; + + union + { + __IOM uint32_t HTIE; /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable */ + __IOM uint32_t RDBFIE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable */ + uint32_t : 22; + } HTIE_b; + }; + + union + { + __IOM uint32_t HTSTFC; /*!< (@ 0x0000020C) High Priority Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force */ + __OM uint32_t RDBFFC : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force */ + uint32_t : 1; + __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] High Priority Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] High Priority Transfer Error Force */ + uint32_t : 22; + } HTSTFC_b; + }; union { @@ -9176,22 +9455,32 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ uint32_t : 8; __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ - __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */ - uint32_t : 15; + __IOM uint32_t SVAFn : 3; /*!< [18..16] Slave Address Detection Flag */ + uint32_t : 13; } SVST_b; }; union { - __IOM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Control Register */ + __IM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Operating Status Register */ struct { - __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ - uint32_t : 31; + __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; } WUST_b; }; - __IM uint32_t RESERVED18[2]; + + union + { + __IM uint32_t MRCCPT; /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register */ + + struct + { + __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture */ + } MRCCPT_b; + }; + __IM uint32_t RESERVED18; union { @@ -9271,7 +9560,87 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ } DATBAS3_b; }; - __IM uint32_t RESERVED22[24]; + __IM uint32_t RESERVED22; + + union + { + __IOM uint32_t DATBAS4; /*!< (@ 0x00000244) Device Address Table Basic Register 4 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS4_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IOM uint32_t DATBAS5; /*!< (@ 0x0000024C) Device Address Table Basic Register 5 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS5_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t DATBAS6; /*!< (@ 0x00000254) Device Address Table Basic Register 6 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS6_b; + }; + __IM uint32_t RESERVED25; + + union + { + __IOM uint32_t DATBAS7; /*!< (@ 0x0000025C) Device Address Table Basic Register 7 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS7_b; + }; + __IM uint32_t RESERVED26[16]; union { @@ -9287,7 +9656,7 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ } EXDATBAS_b; }; - __IM uint32_t RESERVED23[3]; + __IM uint32_t RESERVED27[3]; union { @@ -9336,7 +9705,7 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure uint32_t : 9; } SDATBAS2_b; }; - __IM uint32_t RESERVED24[5]; + __IM uint32_t RESERVED28[5]; union { @@ -9409,7 +9778,79 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure uint32_t : 16; } MSDCT3_b; }; - __IM uint32_t RESERVED25[16]; + + union + { + __IOM uint32_t MSDCT4; /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT4_b; + }; + + union + { + __IOM uint32_t MSDCT5; /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT5_b; + }; + + union + { + __IOM uint32_t MSDCT6; /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT6_b; + }; + + union + { + __IOM uint32_t MSDCT7; /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT7_b; + }; + __IM uint32_t RESERVED29[12]; union { @@ -9432,7 +9873,7 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure * ID Low Register */ __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional * ID High Register */ - __IM uint32_t RESERVED26; + __IM uint32_t RESERVED30; union { @@ -9449,7 +9890,39 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ } SVDVAD0_b; }; - __IM uint32_t RESERVED27[7]; + + union + { + __IM uint32_t SVDVAD1; /*!< (@ 0x00000334) Slave Device Address Register 1 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD1_b; + }; + + union + { + __IM uint32_t SVDVAD2; /*!< (@ 0x00000338) Slave Device Address Register 2 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD2_b; + }; + __IM uint32_t RESERVED31[5]; union { @@ -9562,18 +10035,35 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure union { - __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) - * Register */ + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ struct { - uint32_t : 8; - __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ - __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ - uint32_t : 8; + __IOM uint32_t SPTSYN : 1; /*!< [0..0] Supports Sync Mode */ + __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0 */ + __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1 */ + uint32_t : 5; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; } CETSM_b; }; - __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t CETSS; /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State) + * Register */ + + struct + { + __IOM uint32_t SYNE : 1; /*!< [0..0] Sync Mode Enabled */ + __IOM uint32_t ASYNE : 2; /*!< [2..1] Async Mode Enabled */ + uint32_t : 4; + __IOM uint32_t ICOVF : 1; /*!< [7..7] Internal Counter Overflow */ + uint32_t : 24; + } CETSS_b; + }; union { @@ -9600,7 +10090,7 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure uint32_t : 24; } BITCNT_b; }; - __IM uint32_t RESERVED29[4]; + __IM uint32_t RESERVED32[4]; union { @@ -9618,7 +10108,7 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure union { - __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */ + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0 */ struct { @@ -9627,7 +10117,7 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure uint32_t : 16; } NDBSTLV0_b; }; - __IM uint32_t RESERVED30[9]; + __IM uint32_t RESERVED33[9]; union { @@ -9639,7 +10129,30 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure uint32_t : 24; } NRSQSTLV_b; }; - __IM uint32_t RESERVED31[2]; + + union + { + __IM uint32_t HQSTLV; /*!< (@ 0x000003C4) High Priority Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQLV : 8; /*!< [7..0] High Priority Command Queue Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] High Priority Response Queue Level */ + uint32_t : 16; + } HQSTLV_b; + }; + + union + { + __IM uint32_t HDBSTLV; /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] High Priority Tx Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] High Priority Rx Data Buffer Level */ + uint32_t : 16; + } HDBSTLV_b; + }; union { @@ -9665,7 +10178,30 @@ typedef struct /*!< (@ 0x40083000) R_I3C0 Structure uint32_t : 24; } MSERRCNT_b; }; -} R_I3C0_Type; /*!< Size = 980 (0x3d4) */ + __IM uint32_t RESERVED34[3]; + + union + { + __IM uint32_t SC1CPT; /*!< (@ 0x000003E0) SC1 Capture monitor Register */ + + struct + { + __IM uint32_t SC1C : 16; /*!< [15..0] SC1 Capture */ + uint32_t : 16; + } SC1CPT_b; + }; + + union + { + __IM uint32_t SC2CPT; /*!< (@ 0x000003E4) SC2 Capture monitor Register */ + + struct + { + __IM uint32_t SC2C : 16; /*!< [15..0] SC2 Capture */ + uint32_t : 16; + } SC2CPT_b; + }; +} R_I3C0_Type; /*!< Size = 1000 (0x3e8) */ /* =========================================================================================================================== */ /* ================ R_MMF ================ */ @@ -15430,7 +15966,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * data. */ uint16_t : 1; __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ } CFIFOCTR_b; }; @@ -15450,7 +15986,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D0FIFOSEL_b; }; @@ -15484,7 +16020,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D1FIFOSEL_b; }; @@ -15759,14 +16295,13 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure union { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ struct { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; + uint16_t : 15; __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; + } DVCHGR_b; }; union @@ -15779,8 +16314,8 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * the USB address assigned by the host when the USBHS processed * the SET_ADDRESS request successfully. */ uint16_t : 1; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; } USBADDR_b; }; __IM uint16_t RESERVED9; @@ -17494,6 +18029,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_AGTX7_BASE 0x40084700UL #define R_AGTX8_BASE 0x40084800UL #define R_AGTX9_BASE 0x40084900UL + #define R_WDT1_BASE 0x40044300UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -17626,6 +18162,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -18419,32 +18956,38 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== CMPCTL ========================================================= */ - #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ - #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ - #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ - #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ - #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ - #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ - #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ - #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ - #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ /* ======================================================== CMPSEL0 ======================================================== */ - #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ - #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ /* ======================================================== CMPSEL1 ======================================================== */ - #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ - #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ /* ======================================================== CMPMON ========================================================= */ - #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ - #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ /* ========================================================= CPIOC ========================================================= */ - #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ - #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ - #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPINTCTL ======================================================== */ + #define R_ACMPHS0_CPINTCTL_MSKE_Pos (0UL) /*!< MSKE (Bit 0) */ + #define R_ACMPHS0_CPINTCTL_MSKE_Msk (0x1UL) /*!< MSKE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPMSKCTL ======================================================== */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Pos (0UL) /*!< MSKSEL (Bit 0) */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Msk (0x7UL) /*!< MSKSEL (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_ADC0 ================ */ @@ -19635,9 +20178,14 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================= DMAST ========================================================= */ #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* ======================================================== DMECHR ========================================================= */ #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ @@ -19647,11 +20195,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -20468,6 +21011,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -20491,6 +21036,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -20530,9 +21077,15 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -20607,7 +21160,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -20644,8 +21203,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -20831,6 +21388,24 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ @@ -21551,6 +22126,14 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HCMDQRST_Pos (9UL) /*!< HCMDQRST (Bit 9) */ + #define R_I3C0_RSTCTL_HCMDQRST_Msk (0x200UL) /*!< HCMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRSPQRST_Pos (10UL) /*!< HRSPQRST (Bit 10) */ + #define R_I3C0_RSTCTL_HRSPQRST_Msk (0x400UL) /*!< HRSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HTDBRST_Pos (11UL) /*!< HTDBRST (Bit 11) */ + #define R_I3C0_RSTCTL_HTDBRST_Msk (0x800UL) /*!< HTDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRDBRST_Pos (12UL) /*!< HRDBRST (Bit 12) */ + #define R_I3C0_RSTCTL_HRDBRST_Msk (0x1000UL) /*!< HRDBRST (Bitfield-Mask: 0x01) */ #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ /* ========================================================= PRSST ========================================================= */ @@ -21607,7 +22190,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ - #define R_I3C0_SVCTL_SVAEn_Msk (0x10000UL) /*!< SVAEn (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_SVAEn_Msk (0x70000UL) /*!< SVAEn (Bitfield-Mask: 0x07) */ /* ======================================================= REFCKCTL ======================================================== */ #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ @@ -21702,6 +22285,24 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================== SVTDLG0 ======================================================== */ #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= STCTL ========================================================= */ + #define R_I3C0_STCTL_STOE_Pos (0UL) /*!< STOE (Bit 0) */ + #define R_I3C0_STCTL_STOE_Msk (0x1UL) /*!< STOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ATCTL ========================================================= */ + #define R_I3C0_ATCTL_ATTRGS_Pos (0UL) /*!< ATTRGS (Bit 0) */ + #define R_I3C0_ATCTL_ATTRGS_Msk (0x1UL) /*!< ATTRGS (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_MREFOE_Pos (1UL) /*!< MREFOE (Bit 1) */ + #define R_I3C0_ATCTL_MREFOE_Msk (0x2UL) /*!< MREFOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_AMEOE_Pos (2UL) /*!< AMEOE (Bit 2) */ + #define R_I3C0_ATCTL_AMEOE_Msk (0x4UL) /*!< AMEOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_CDIV_Pos (8UL) /*!< CDIV (Bit 8) */ + #define R_I3C0_ATCTL_CDIV_Msk (0xff00UL) /*!< CDIV (Bitfield-Mask: 0xff) */ +/* ========================================================= ATTRG ========================================================= */ + #define R_I3C0_ATTRG_ATSTRG_Pos (0UL) /*!< ATSTRG (Bit 0) */ + #define R_I3C0_ATTRG_ATSTRG_Msk (0x1UL) /*!< ATSTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== ATCCNTE ======================================================== */ + #define R_I3C0_ATCCNTE_ATCE_Pos (0UL) /*!< ATCE (Bit 0) */ + #define R_I3C0_ATCCNTE_ATCE_Msk (0x1UL) /*!< ATCE (Bitfield-Mask: 0x01) */ /* ======================================================== CNDCTL ========================================================= */ #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ @@ -21714,6 +22315,15 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================== NTDTBP0 ======================================================== */ /* ======================================================== NIBIQP ========================================================= */ /* ========================================================= NRSQP ========================================================= */ +/* ======================================================== HCMDQP ========================================================= */ + #define R_I3C0_HCMDQP_HCMDQP_Pos (0UL) /*!< HCMDQP (Bit 0) */ + #define R_I3C0_HCMDQP_HCMDQP_Msk (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HRSPQP ========================================================= */ + #define R_I3C0_HRSPQP_HRSPQP_Pos (0UL) /*!< HRSPQP (Bit 0) */ + #define R_I3C0_HRSPQP_HRSPQP_Msk (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HTDTBP ========================================================= */ + #define R_I3C0_HTDTBP_HTDTBP_Pos (0UL) /*!< HTDTBP (Bit 0) */ + #define R_I3C0_HTDTBP_HTDTBP_Msk (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff) */ /* ======================================================== NQTHCTL ======================================================== */ #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ @@ -21735,6 +22345,20 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================= NRQTHCTL ======================================================== */ #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ +/* ======================================================== HQTHCTL ======================================================== */ + #define R_I3C0_HQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_HQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_HQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= HTBTHCTL ======================================================== */ + #define R_I3C0_HTBTHCTL_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_HTBTHCTL_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ /* ========================================================== BST ========================================================== */ #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ @@ -21871,6 +22495,58 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ +/* ========================================================= HTST ========================================================== */ + #define R_I3C0_HTST_TDBEF_Pos (0UL) /*!< TDBEF (Bit 0) */ + #define R_I3C0_HTST_TDBEF_Msk (0x1UL) /*!< TDBEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RDBFF_Pos (1UL) /*!< RDBFF (Bit 1) */ + #define R_I3C0_HTST_RDBFF_Msk (0x2UL) /*!< RDBFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_HTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_HTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_HTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_HTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ +/* ========================================================= HTSTE ========================================================= */ + #define R_I3C0_HTSTE_TDBEE_Pos (0UL) /*!< TDBEE (Bit 0) */ + #define R_I3C0_HTSTE_TDBEE_Msk (0x1UL) /*!< TDBEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RDBFE_Pos (1UL) /*!< RDBFE (Bit 1) */ + #define R_I3C0_HTSTE_RDBFE_Msk (0x2UL) /*!< RDBFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_HTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_HTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_HTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_HTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ +/* ========================================================= HTIE ========================================================== */ + #define R_I3C0_HTIE_TDBEIE_Pos (0UL) /*!< TDBEIE (Bit 0) */ + #define R_I3C0_HTIE_TDBEIE_Msk (0x1UL) /*!< TDBEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RDBFIE_Pos (1UL) /*!< RDBFIE (Bit 1) */ + #define R_I3C0_HTIE_RDBFIE_Msk (0x2UL) /*!< RDBFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_HTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_HTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_HTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_HTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== HTSTFC ========================================================= */ + #define R_I3C0_HTSTFC_TDBEFC_Pos (0UL) /*!< TDBEFC (Bit 0) */ + #define R_I3C0_HTSTFC_TDBEFC_Msk (0x1UL) /*!< TDBEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RDBFFC_Pos (1UL) /*!< RDBFFC (Bit 1) */ + #define R_I3C0_HTSTFC_RDBFFC_Msk (0x2UL) /*!< RDBFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_HTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_HTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_HTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_HTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ /* ========================================================= BCST ========================================================== */ #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ @@ -21888,10 +22564,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ - #define R_I3C0_SVST_SVAFn_Msk (0x10000UL) /*!< SVAFn (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_SVAFn_Msk (0x70000UL) /*!< SVAFn (Bitfield-Mask: 0x07) */ /* ========================================================= WUST ========================================================== */ #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCCPT ========================================================= */ + #define R_I3C0_MRCCPT_MRCCPT_Pos (0UL) /*!< MRCCPT (Bit 0) */ + #define R_I3C0_MRCCPT_MRCCPT_Msk (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff) */ /* ======================================================== DATBAS0 ======================================================== */ #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ @@ -21960,6 +22639,74 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS4 ======================================================== */ + #define R_I3C0_DATBAS4_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS4_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS4_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS4_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS4_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS4_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS4_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS4_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS4_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS4_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS4_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS5 ======================================================== */ + #define R_I3C0_DATBAS5_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS5_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS5_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS5_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS5_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS5_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS5_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS5_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS5_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS5_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS5_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS6 ======================================================== */ + #define R_I3C0_DATBAS6_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS6_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS6_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS6_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS6_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS6_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS6_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS6_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS6_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS6_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS6_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS7 ======================================================== */ + #define R_I3C0_DATBAS7_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS7_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS7_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS7_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS7_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS7_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS7_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS7_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS7_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS7_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS7_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ /* ======================================================= EXDATBAS ======================================================== */ #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ @@ -22056,6 +22803,66 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT4 ========================================================= */ + #define R_I3C0_MSDCT4_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT4_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT4_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT4_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT4_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT4_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT4_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT4_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT5 ========================================================= */ + #define R_I3C0_MSDCT5_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT5_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT5_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT5_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT5_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT5_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT5_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT5_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT6 ========================================================= */ + #define R_I3C0_MSDCT6_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT6_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT6_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT6_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT6_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT6_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT6_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT6_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT7 ========================================================= */ + #define R_I3C0_MSDCT7_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT7_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT7_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT7_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT7_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT7_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT7_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT7_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ========================================================= SVDCT ========================================================= */ #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ @@ -22084,6 +22891,24 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD1 ======================================================== */ + #define R_I3C0_SVDVAD1_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD1_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD1_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD1_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD1_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD1_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD2 ======================================================== */ + #define R_I3C0_SVDVAD2_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD2_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD2_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD2_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD2_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD2_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ /* ======================================================== CSECMD ========================================================= */ #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ @@ -22128,10 +22953,23 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ /* ========================================================= CETSM ========================================================= */ + #define R_I3C0_CETSM_SPTSYN_Pos (0UL) /*!< SPTSYN (Bit 0) */ + #define R_I3C0_CETSM_SPTSYN_Msk (0x1UL) /*!< SPTSYN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN0_Pos (1UL) /*!< SPTASYN0 (Bit 1) */ + #define R_I3C0_CETSM_SPTASYN0_Msk (0x2UL) /*!< SPTASYN0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN1_Pos (2UL) /*!< SPTASYN1 (Bit 2) */ + #define R_I3C0_CETSM_SPTASYN1_Msk (0x4UL) /*!< SPTASYN1 (Bitfield-Mask: 0x01) */ #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ========================================================= CETSS ========================================================= */ + #define R_I3C0_CETSS_SYNE_Pos (0UL) /*!< SYNE (Bit 0) */ + #define R_I3C0_CETSS_SYNE_Msk (0x1UL) /*!< SYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSS_ASYNE_Pos (1UL) /*!< ASYNE (Bit 1) */ + #define R_I3C0_CETSS_ASYNE_Msk (0x6UL) /*!< ASYNE (Bitfield-Mask: 0x03) */ + #define R_I3C0_CETSS_ICOVF_Pos (7UL) /*!< ICOVF (Bit 7) */ + #define R_I3C0_CETSS_ICOVF_Msk (0x80UL) /*!< ICOVF (Bitfield-Mask: 0x01) */ /* ======================================================= CGHDRCAP ======================================================== */ #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ @@ -22161,6 +22999,16 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================= NRSQSTLV ======================================================== */ #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HQSTLV ========================================================= */ + #define R_I3C0_HQSTLV_CMDQLV_Pos (0UL) /*!< CMDQLV (Bit 0) */ + #define R_I3C0_HQSTLV_CMDQLV_Msk (0xffUL) /*!< CMDQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_HQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HDBSTLV ======================================================== */ + #define R_I3C0_HDBSTLV_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_HDBSTLV_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HDBSTLV_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_HDBSTLV_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ /* ======================================================== PRSTDBG ======================================================== */ #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ @@ -22173,6 +23021,12 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ======================================================= MSERRCNT ======================================================== */ #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ +/* ======================================================== SC1CPT ========================================================= */ + #define R_I3C0_SC1CPT_SC1C_Pos (0UL) /*!< SC1C (Bit 0) */ + #define R_I3C0_SC1CPT_SC1C_Msk (0xffffUL) /*!< SC1C (Bitfield-Mask: 0xffff) */ +/* ======================================================== SC2CPT ========================================================= */ + #define R_I3C0_SC2CPT_SC2C_Pos (0UL) /*!< SC2C (Bit 0) */ + #define R_I3C0_SC2CPT_SC2C_Msk (0xffffUL) /*!< SC2C (Bitfield-Mask: 0xffff) */ /* =========================================================================================================================== */ /* ================ R_MMF ================ */ @@ -24778,14 +25632,12 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== UFRMNUM ======================================================== */ - #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ /* ======================================================== USBADDR ======================================================== */ #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ /* ======================================================== USBREQ ========================================================= */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h index 11ed480ce..ad0d56459 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h @@ -2896,7 +2896,31 @@ typedef struct /*!< (@ 0x40085000) R_ACMPHS0 Structure __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ } CPIOC_b; }; -} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ + __IM uint8_t RESERVED4[47]; + + union + { + __IOM uint8_t CPINTCTL; /*!< (@ 0x00000040) Comparator Interrupt Control Register */ + + struct + { + __IOM uint8_t MSKE : 1; /*!< [0..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 7; + } CPINTCTL_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t CPMSKCTL; /*!< (@ 0x00000044) Comparator Interrupt Mask Control Register */ + + struct + { + __IOM uint8_t MSKSEL : 3; /*!< [2..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 5; + } CPMSKCTL_b; + }; +} R_ACMPHS0_Type; /*!< Size = 69 (0x45) */ /* =========================================================================================================================== */ /* ================ R_ADC0 ================ */ @@ -3159,7 +3183,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -3172,7 +3196,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -5550,8 +5574,8 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure struct { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ uint32_t : 7; __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ @@ -10130,7 +10154,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -10177,7 +10202,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -10188,7 +10214,10 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -10205,24 +10234,26 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -10266,12 +10297,24 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -10748,7 +10791,57 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -18075,7 +18168,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * data. */ uint16_t : 1; __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ } CFIFOCTR_b; }; @@ -18095,7 +18188,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D0FIFOSEL_b; }; @@ -18129,7 +18222,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D1FIFOSEL_b; }; @@ -18404,14 +18497,13 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure union { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ struct { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; + uint16_t : 15; __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; + } DVCHGR_b; }; union @@ -18424,8 +18516,8 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * the USB address assigned by the host when the USBHS processed * the SET_ADDRESS request successfully. */ uint16_t : 1; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; } USBADDR_b; }; __IM uint16_t RESERVED9; @@ -20145,6 +20237,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_AGTX7_BASE 0x40084700UL #define R_AGTX8_BASE 0x40084800UL #define R_AGTX9_BASE 0x40084900UL + #define R_WDT1_BASE 0x40044300UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -20283,6 +20376,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -21430,32 +21524,38 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== CMPCTL ========================================================= */ - #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ - #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ - #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ - #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ - #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ - #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ - #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ - #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ - #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ /* ======================================================== CMPSEL0 ======================================================== */ - #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ - #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ /* ======================================================== CMPSEL1 ======================================================== */ - #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ - #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ /* ======================================================== CMPMON ========================================================= */ - #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ - #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ /* ========================================================= CPIOC ========================================================= */ - #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ - #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ - #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPINTCTL ======================================================== */ + #define R_ACMPHS0_CPINTCTL_MSKE_Pos (0UL) /*!< MSKE (Bit 0) */ + #define R_ACMPHS0_CPINTCTL_MSKE_Msk (0x1UL) /*!< MSKE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPMSKCTL ======================================================== */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Pos (0UL) /*!< MSKSEL (Bit 0) */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Msk (0x7UL) /*!< MSKSEL (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_ADC0 ================ */ @@ -22646,9 +22746,14 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================= DMAST ========================================================= */ #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* ======================================================== DMECHR ========================================================= */ #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ @@ -22658,11 +22763,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -24542,6 +24642,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -24565,6 +24667,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -24604,9 +24708,15 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -24681,7 +24791,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -24718,8 +24834,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -24905,6 +25019,24 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ @@ -28368,14 +28500,12 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== UFRMNUM ======================================================== */ - #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ /* ======================================================== USBADDR ======================================================== */ #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ /* ======================================================== USBREQ ========================================================= */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h index c2962cb37..7d5d5650c 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h @@ -2148,7 +2148,7 @@ typedef struct /*!< (@ 0x40170000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -2161,7 +2161,7 @@ typedef struct /*!< (@ 0x40170000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -4763,8 +4763,8 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure struct { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ uint32_t : 7; __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ @@ -6967,7 +6967,8 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -7014,7 +7015,8 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -7025,7 +7027,10 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -7042,24 +7047,26 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -7103,12 +7110,24 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -7585,7 +7604,57 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -13992,7 +14061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * data. */ uint16_t : 1; __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ } CFIFOCTR_b; }; @@ -14012,7 +14081,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D0FIFOSEL_b; }; @@ -14046,7 +14115,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D1FIFOSEL_b; }; @@ -14321,14 +14390,13 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure union { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ struct { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; + uint16_t : 15; __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; + } DVCHGR_b; }; union @@ -14341,8 +14409,8 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * the USB address assigned by the host when the USBHS processed * the SET_ADDRESS request successfully. */ uint16_t : 1; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; } USBADDR_b; }; __IM uint16_t RESERVED9; @@ -16909,6 +16977,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGTX8_BASE 0x400E8800UL #define R_AGTX9_BASE 0x400E8900UL #define R_FLAD_BASE 0x407FC000UL + #define R_WDT1_BASE 0x40044300UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -17032,6 +17101,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -19158,9 +19228,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================= DMAST ========================================================= */ #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* ======================================================== DMECHR ========================================================= */ #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ @@ -19170,11 +19245,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -19991,6 +20061,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -20014,6 +20086,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -20053,9 +20127,15 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -20130,7 +20210,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -20167,8 +20253,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -20354,6 +20438,24 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ @@ -23410,14 +23512,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== UFRMNUM ======================================================== */ - #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ /* ======================================================== USBADDR ======================================================== */ #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ /* ======================================================== USBREQ ========================================================= */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h index b9a6bdccc..4e352a343 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h @@ -2633,7 +2633,7 @@ typedef struct /*!< (@ 0x40170000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -2646,7 +2646,7 @@ typedef struct /*!< (@ 0x40170000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -5888,8 +5888,8 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure struct { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ uint32_t : 7; __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ @@ -8092,7 +8092,8 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -8139,7 +8140,8 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -8150,7 +8152,10 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -8167,24 +8172,26 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -8228,12 +8235,24 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -8710,7 +8729,57 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -9686,20 +9755,25 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure union { - __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ struct { - __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ - __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ - __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ - __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ - __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ - __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ - __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ - uint32_t : 9; - __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ - uint32_t : 15; + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 2; + __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset */ + __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese */ + __IOM uint32_t HTDBRST : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset */ + __IOM uint32_t HRDBRST : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset */ + uint32_t : 3; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; } RSTCTL_b; }; @@ -9829,8 +9903,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ uint32_t : 8; __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ - __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */ - uint32_t : 15; + __IOM uint32_t SVAEn : 3; /*!< [18..16] Slave Address Enable */ + uint32_t : 13; } SVCTL_b; }; __IM uint32_t RESERVED6[2]; @@ -9872,7 +9946,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ uint32_t : 2; - __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */ + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull */ uint32_t : 2; } EXTBR_b; }; @@ -10026,7 +10100,57 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ } SVTDLG0_b; }; - __IM uint32_t RESERVED11[31]; + __IM uint32_t RESERVED11[23]; + + union + { + __IOM uint32_t STCTL; /*!< (@ 0x00000120) Synchronous Timing Control Register */ + + struct + { + __IOM uint32_t STOE : 1; /*!< [0..0] Synchronous Timing output Enable */ + uint32_t : 31; + } STCTL_b; + }; + + union + { + __IOM uint32_t ATCTL; /*!< (@ 0x00000124) Asynchronous Timing Control Register */ + + struct + { + __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select */ + __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow) */ + __IOM uint32_t AMEOE : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable */ + uint32_t : 5; + __IOM uint32_t CDIV : 8; /*!< [15..8] TCLK Counter Divide Setting */ + uint32_t : 16; + } ATCTL_b; + }; + + union + { + __IOM uint32_t ATTRG; /*!< (@ 0x00000128) Asynchronous Timing Trigger Register */ + + struct + { + __OM uint32_t ATSTRG : 1; /*!< [0..0] Asynchronous Timing Software Trigger */ + uint32_t : 31; + } ATTRG_b; + }; + + union + { + __IOM uint32_t ATCCNTE; /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register */ + + struct + { + __IOM uint32_t ATCE : 1; /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1, + * SC2. */ + uint32_t : 31; + } ATCCNTE_b; + }; + __IM uint32_t RESERVED12[4]; union { @@ -10040,14 +10164,43 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 29; } CNDCTL_b; }; - __IM uint32_t RESERVED12[3]; + __IM uint32_t RESERVED13[3]; __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ - __IM uint32_t RESERVED13[8]; + __IM uint32_t RESERVED14[8]; __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ - __IM uint32_t RESERVED14[3]; + + union + { + __OM uint32_t HCMDQP; /*!< (@ 0x00000184) High Priority Command Queue Port Register */ + + struct + { + __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port */ + } HCMDQP_b; + }; + + union + { + __IM uint32_t HRSPQP; /*!< (@ 0x00000188) High Priority Response Queue Port Register */ + + struct + { + __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port */ + } HRSPQP_b; + }; + + union + { + __IOM uint32_t HTDTBP; /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register */ + + struct + { + __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port */ + } HTDTBP_b; + }; union { @@ -10092,7 +10245,37 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } NRQTHCTL_b; }; - __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t HQTHCTL; /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold */ + uint32_t : 16; + } HQTHCTL_b; + }; + + union + { + __IOM uint32_t HTBTHCTL; /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold + * Control Register */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold */ + uint32_t : 5; + } HTBTHCTL_b; + }; + __IM uint32_t RESERVED16; union { @@ -10265,7 +10448,79 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 11; } NTSTFC_b; }; - __IM uint32_t RESERVED17[8]; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint32_t HTST; /*!< (@ 0x00000200) High Priority Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag */ + __IOM uint32_t RDBFF : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag */ + uint32_t : 1; + __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] High Priority Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] High Priority Transfer Error Flag */ + uint32_t : 22; + } HTST_b; + }; + + union + { + __IOM uint32_t HTSTE; /*!< (@ 0x00000204) High Priority Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable */ + __IOM uint32_t RDBFE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] High Priority Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] High Priority Transfer Error Enable */ + uint32_t : 22; + } HTSTE_b; + }; + + union + { + __IOM uint32_t HTIE; /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable */ + __IOM uint32_t RDBFIE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable */ + uint32_t : 22; + } HTIE_b; + }; + + union + { + __IOM uint32_t HTSTFC; /*!< (@ 0x0000020C) High Priority Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force */ + __OM uint32_t RDBFFC : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force */ + uint32_t : 1; + __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] High Priority Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] High Priority Transfer Error Force */ + uint32_t : 22; + } HTSTFC_b; + }; union { @@ -10292,22 +10547,32 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ uint32_t : 8; __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ - __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */ - uint32_t : 15; + __IOM uint32_t SVAFn : 3; /*!< [18..16] Slave Address Detection Flag */ + uint32_t : 13; } SVST_b; }; union { - __IOM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Control Register */ + __IM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Operating Status Register */ struct { - __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ - uint32_t : 31; + __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; } WUST_b; }; - __IM uint32_t RESERVED18[2]; + + union + { + __IM uint32_t MRCCPT; /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register */ + + struct + { + __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture */ + } MRCCPT_b; + }; + __IM uint32_t RESERVED18; union { @@ -10387,7 +10652,87 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ } DATBAS3_b; }; - __IM uint32_t RESERVED22[24]; + __IM uint32_t RESERVED22; + + union + { + __IOM uint32_t DATBAS4; /*!< (@ 0x00000244) Device Address Table Basic Register 4 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS4_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IOM uint32_t DATBAS5; /*!< (@ 0x0000024C) Device Address Table Basic Register 5 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS5_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t DATBAS6; /*!< (@ 0x00000254) Device Address Table Basic Register 6 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS6_b; + }; + __IM uint32_t RESERVED25; + + union + { + __IOM uint32_t DATBAS7; /*!< (@ 0x0000025C) Device Address Table Basic Register 7 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS7_b; + }; + __IM uint32_t RESERVED26[16]; union { @@ -10403,7 +10748,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ } EXDATBAS_b; }; - __IM uint32_t RESERVED23[3]; + __IM uint32_t RESERVED27[3]; union { @@ -10452,7 +10797,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 9; } SDATBAS2_b; }; - __IM uint32_t RESERVED24[5]; + __IM uint32_t RESERVED28[5]; union { @@ -10525,7 +10870,79 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 16; } MSDCT3_b; }; - __IM uint32_t RESERVED25[16]; + + union + { + __IOM uint32_t MSDCT4; /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT4_b; + }; + + union + { + __IOM uint32_t MSDCT5; /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT5_b; + }; + + union + { + __IOM uint32_t MSDCT6; /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT6_b; + }; + + union + { + __IOM uint32_t MSDCT7; /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT7_b; + }; + __IM uint32_t RESERVED29[12]; union { @@ -10548,7 +10965,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure * ID Low Register */ __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional * ID High Register */ - __IM uint32_t RESERVED26; + __IM uint32_t RESERVED30; union { @@ -10565,7 +10982,39 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ } SVDVAD0_b; }; - __IM uint32_t RESERVED27[7]; + + union + { + __IM uint32_t SVDVAD1; /*!< (@ 0x00000334) Slave Device Address Register 1 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD1_b; + }; + + union + { + __IM uint32_t SVDVAD2; /*!< (@ 0x00000338) Slave Device Address Register 2 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD2_b; + }; + __IM uint32_t RESERVED31[5]; union { @@ -10678,18 +11127,35 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure union { - __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) - * Register */ + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ struct { - uint32_t : 8; - __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ - __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ - uint32_t : 8; + __IOM uint32_t SPTSYN : 1; /*!< [0..0] Supports Sync Mode */ + __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0 */ + __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1 */ + uint32_t : 5; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; } CETSM_b; }; - __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t CETSS; /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State) + * Register */ + + struct + { + __IOM uint32_t SYNE : 1; /*!< [0..0] Sync Mode Enabled */ + __IOM uint32_t ASYNE : 2; /*!< [2..1] Async Mode Enabled */ + uint32_t : 4; + __IOM uint32_t ICOVF : 1; /*!< [7..7] Internal Counter Overflow */ + uint32_t : 24; + } CETSS_b; + }; union { @@ -10716,7 +11182,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } BITCNT_b; }; - __IM uint32_t RESERVED29[4]; + __IM uint32_t RESERVED32[4]; union { @@ -10734,7 +11200,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure union { - __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */ + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0 */ struct { @@ -10743,7 +11209,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 16; } NDBSTLV0_b; }; - __IM uint32_t RESERVED30[9]; + __IM uint32_t RESERVED33[9]; union { @@ -10755,7 +11221,30 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } NRSQSTLV_b; }; - __IM uint32_t RESERVED31[2]; + + union + { + __IM uint32_t HQSTLV; /*!< (@ 0x000003C4) High Priority Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQLV : 8; /*!< [7..0] High Priority Command Queue Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] High Priority Response Queue Level */ + uint32_t : 16; + } HQSTLV_b; + }; + + union + { + __IM uint32_t HDBSTLV; /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] High Priority Tx Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] High Priority Rx Data Buffer Level */ + uint32_t : 16; + } HDBSTLV_b; + }; union { @@ -10781,7 +11270,30 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } MSERRCNT_b; }; -} R_I3C0_Type; /*!< Size = 980 (0x3d4) */ + __IM uint32_t RESERVED34[3]; + + union + { + __IM uint32_t SC1CPT; /*!< (@ 0x000003E0) SC1 Capture monitor Register */ + + struct + { + __IM uint32_t SC1C : 16; /*!< [15..0] SC1 Capture */ + uint32_t : 16; + } SC1CPT_b; + }; + + union + { + __IM uint32_t SC2CPT; /*!< (@ 0x000003E4) SC2 Capture monitor Register */ + + struct + { + __IM uint32_t SC2C : 16; /*!< [15..0] SC2 Capture */ + uint32_t : 16; + } SC2CPT_b; + }; +} R_I3C0_Type; /*!< Size = 1000 (0x3e8) */ /* =========================================================================================================================== */ /* ================ R_MPU_MMPU ================ */ @@ -16280,7 +16792,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * data. */ uint16_t : 1; __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ } CFIFOCTR_b; }; @@ -16300,7 +16812,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D0FIFOSEL_b; }; @@ -16334,7 +16846,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D1FIFOSEL_b; }; @@ -16609,14 +17121,13 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure union { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ struct { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; + uint16_t : 15; __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; + } DVCHGR_b; }; union @@ -16629,8 +17140,8 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * the USB address assigned by the host when the USBHS processed * the SET_ADDRESS request successfully. */ uint16_t : 1; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; } USBADDR_b; }; __IM uint16_t RESERVED9; @@ -19406,6 +19917,81 @@ typedef struct /*!< (@ 0x400E8000) R_AGTX0 Structure }; } R_AGTX0_Type; /*!< Size = 20 (0x14) */ +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CANFD ECC (R_ECCMB0) + */ + +typedef struct /*!< (@ 0x4036F200) R_ECCMB0 Structure */ +{ + union + { + __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ + + struct + { + __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Message Flag */ + __IM uint32_t ECER1F : 1; /*!< [1..1] ECC Error Detection and Correction Flag */ + __IM uint32_t ECER2F : 1; /*!< [2..2] 2-bit ECC Error Detection Flag */ + __IOM uint32_t EC1EDIC : 1; /*!< [3..3] ECC 1-bit Error Detection Interrupt Control */ + __IOM uint32_t EC2EDIC : 1; /*!< [4..4] ECC 2-bit Error Detection Interrupt Control */ + __IOM uint32_t EC1ECP : 1; /*!< [5..5] ECC 1-bit Error Correction Permission */ + __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Judgment Enable Flag */ + uint32_t : 2; + __IOM uint32_t ECER1C : 1; /*!< [9..9] Accumulating ECC Error Detection and Correction Flag + * Clear */ + __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-bit ECC Error Detection Flag Clear */ + __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Overflow Detection Flag */ + uint32_t : 2; + __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Select bit */ + __IM uint32_t ECSEDF0 : 1; /*!< [16..16] ECC Single bit Error Address Detection Flag */ + __IM uint32_t ECDEDF0 : 1; /*!< [17..17] ECC Dual Bit Error Address Detection Flag */ + uint32_t : 14; + } EC710CTL_b; + }; + + union + { + __IOM uint16_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ + uint16_t : 5; + __IOM uint16_t ECTMCE : 1; /*!< [7..7] ECC Test Mode Control Enable */ + uint16_t : 6; + __IOM uint16_t ETMA : 2; /*!< [15..14] ECC Test Mode Bit Access Control */ + } EC710TMC_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Test Substitute Data Register */ + + struct + { + __IOM uint32_t ECEDB : 32; /*!< [31..0] ECC Test Substitute Data */ + } EC710TED_b; + }; + + union + { + __IM uint32_t EC710EAD0; /*!< (@ 0x00000010) ECC Error Address Register */ + + struct + { + __IM uint32_t ECEAD : 10; /*!< [9..0] ECC Error Address */ + uint32_t : 22; + } EC710EAD0_b; + }; +} R_ECCMB0_Type; /*!< Size = 20 (0x14) */ + /* =========================================================================================================================== */ /* ================ R_FLAD ================ */ /* =========================================================================================================================== */ @@ -19552,7 +20138,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGTX7_BASE 0x400E8700UL #define R_AGTX8_BASE 0x400E8800UL #define R_AGTX9_BASE 0x400E8900UL + #define R_ECCMB0_BASE 0x4036F200UL + #define R_ECCMB1_BASE 0x4036F300UL #define R_FLAD_BASE 0x407FC000UL + #define R_WDT1_BASE 0x40044300UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -19677,7 +20266,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_ECCMB0 ((R_ECCMB0_Type *) R_ECCMB0_BASE) + #define R_ECCMB1 ((R_ECCMB0_Type *) R_ECCMB1_BASE) #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -22363,9 +22955,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================= DMAST ========================================================= */ #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* ======================================================== DMECHR ========================================================= */ #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ @@ -22375,11 +22972,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -23196,6 +23788,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -23219,6 +23813,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -23258,9 +23854,15 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -23335,7 +23937,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -23372,8 +23980,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -23559,6 +24165,24 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ @@ -24204,6 +24828,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HCMDQRST_Pos (9UL) /*!< HCMDQRST (Bit 9) */ + #define R_I3C0_RSTCTL_HCMDQRST_Msk (0x200UL) /*!< HCMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRSPQRST_Pos (10UL) /*!< HRSPQRST (Bit 10) */ + #define R_I3C0_RSTCTL_HRSPQRST_Msk (0x400UL) /*!< HRSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HTDBRST_Pos (11UL) /*!< HTDBRST (Bit 11) */ + #define R_I3C0_RSTCTL_HTDBRST_Msk (0x800UL) /*!< HTDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRDBRST_Pos (12UL) /*!< HRDBRST (Bit 12) */ + #define R_I3C0_RSTCTL_HRDBRST_Msk (0x1000UL) /*!< HRDBRST (Bitfield-Mask: 0x01) */ #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ /* ========================================================= PRSST ========================================================= */ @@ -24260,7 +24892,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ - #define R_I3C0_SVCTL_SVAEn_Msk (0x10000UL) /*!< SVAEn (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_SVAEn_Msk (0x70000UL) /*!< SVAEn (Bitfield-Mask: 0x07) */ /* ======================================================= REFCKCTL ======================================================== */ #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ @@ -24355,6 +24987,24 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================== SVTDLG0 ======================================================== */ #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= STCTL ========================================================= */ + #define R_I3C0_STCTL_STOE_Pos (0UL) /*!< STOE (Bit 0) */ + #define R_I3C0_STCTL_STOE_Msk (0x1UL) /*!< STOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ATCTL ========================================================= */ + #define R_I3C0_ATCTL_ATTRGS_Pos (0UL) /*!< ATTRGS (Bit 0) */ + #define R_I3C0_ATCTL_ATTRGS_Msk (0x1UL) /*!< ATTRGS (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_MREFOE_Pos (1UL) /*!< MREFOE (Bit 1) */ + #define R_I3C0_ATCTL_MREFOE_Msk (0x2UL) /*!< MREFOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_AMEOE_Pos (2UL) /*!< AMEOE (Bit 2) */ + #define R_I3C0_ATCTL_AMEOE_Msk (0x4UL) /*!< AMEOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_CDIV_Pos (8UL) /*!< CDIV (Bit 8) */ + #define R_I3C0_ATCTL_CDIV_Msk (0xff00UL) /*!< CDIV (Bitfield-Mask: 0xff) */ +/* ========================================================= ATTRG ========================================================= */ + #define R_I3C0_ATTRG_ATSTRG_Pos (0UL) /*!< ATSTRG (Bit 0) */ + #define R_I3C0_ATTRG_ATSTRG_Msk (0x1UL) /*!< ATSTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== ATCCNTE ======================================================== */ + #define R_I3C0_ATCCNTE_ATCE_Pos (0UL) /*!< ATCE (Bit 0) */ + #define R_I3C0_ATCCNTE_ATCE_Msk (0x1UL) /*!< ATCE (Bitfield-Mask: 0x01) */ /* ======================================================== CNDCTL ========================================================= */ #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ @@ -24367,6 +25017,15 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================== NTDTBP0 ======================================================== */ /* ======================================================== NIBIQP ========================================================= */ /* ========================================================= NRSQP ========================================================= */ +/* ======================================================== HCMDQP ========================================================= */ + #define R_I3C0_HCMDQP_HCMDQP_Pos (0UL) /*!< HCMDQP (Bit 0) */ + #define R_I3C0_HCMDQP_HCMDQP_Msk (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HRSPQP ========================================================= */ + #define R_I3C0_HRSPQP_HRSPQP_Pos (0UL) /*!< HRSPQP (Bit 0) */ + #define R_I3C0_HRSPQP_HRSPQP_Msk (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HTDTBP ========================================================= */ + #define R_I3C0_HTDTBP_HTDTBP_Pos (0UL) /*!< HTDTBP (Bit 0) */ + #define R_I3C0_HTDTBP_HTDTBP_Msk (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff) */ /* ======================================================== NQTHCTL ======================================================== */ #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ @@ -24388,6 +25047,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= NRQTHCTL ======================================================== */ #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ +/* ======================================================== HQTHCTL ======================================================== */ + #define R_I3C0_HQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_HQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_HQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= HTBTHCTL ======================================================== */ + #define R_I3C0_HTBTHCTL_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_HTBTHCTL_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ /* ========================================================== BST ========================================================== */ #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ @@ -24524,6 +25197,58 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ +/* ========================================================= HTST ========================================================== */ + #define R_I3C0_HTST_TDBEF_Pos (0UL) /*!< TDBEF (Bit 0) */ + #define R_I3C0_HTST_TDBEF_Msk (0x1UL) /*!< TDBEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RDBFF_Pos (1UL) /*!< RDBFF (Bit 1) */ + #define R_I3C0_HTST_RDBFF_Msk (0x2UL) /*!< RDBFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_HTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_HTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_HTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_HTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ +/* ========================================================= HTSTE ========================================================= */ + #define R_I3C0_HTSTE_TDBEE_Pos (0UL) /*!< TDBEE (Bit 0) */ + #define R_I3C0_HTSTE_TDBEE_Msk (0x1UL) /*!< TDBEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RDBFE_Pos (1UL) /*!< RDBFE (Bit 1) */ + #define R_I3C0_HTSTE_RDBFE_Msk (0x2UL) /*!< RDBFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_HTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_HTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_HTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_HTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ +/* ========================================================= HTIE ========================================================== */ + #define R_I3C0_HTIE_TDBEIE_Pos (0UL) /*!< TDBEIE (Bit 0) */ + #define R_I3C0_HTIE_TDBEIE_Msk (0x1UL) /*!< TDBEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RDBFIE_Pos (1UL) /*!< RDBFIE (Bit 1) */ + #define R_I3C0_HTIE_RDBFIE_Msk (0x2UL) /*!< RDBFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_HTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_HTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_HTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_HTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== HTSTFC ========================================================= */ + #define R_I3C0_HTSTFC_TDBEFC_Pos (0UL) /*!< TDBEFC (Bit 0) */ + #define R_I3C0_HTSTFC_TDBEFC_Msk (0x1UL) /*!< TDBEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RDBFFC_Pos (1UL) /*!< RDBFFC (Bit 1) */ + #define R_I3C0_HTSTFC_RDBFFC_Msk (0x2UL) /*!< RDBFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_HTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_HTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_HTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_HTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ /* ========================================================= BCST ========================================================== */ #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ @@ -24541,10 +25266,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ - #define R_I3C0_SVST_SVAFn_Msk (0x10000UL) /*!< SVAFn (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_SVAFn_Msk (0x70000UL) /*!< SVAFn (Bitfield-Mask: 0x07) */ /* ========================================================= WUST ========================================================== */ #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCCPT ========================================================= */ + #define R_I3C0_MRCCPT_MRCCPT_Pos (0UL) /*!< MRCCPT (Bit 0) */ + #define R_I3C0_MRCCPT_MRCCPT_Msk (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff) */ /* ======================================================== DATBAS0 ======================================================== */ #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ @@ -24613,6 +25341,74 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS4 ======================================================== */ + #define R_I3C0_DATBAS4_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS4_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS4_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS4_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS4_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS4_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS4_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS4_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS4_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS4_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS4_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS5 ======================================================== */ + #define R_I3C0_DATBAS5_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS5_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS5_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS5_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS5_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS5_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS5_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS5_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS5_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS5_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS5_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS6 ======================================================== */ + #define R_I3C0_DATBAS6_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS6_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS6_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS6_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS6_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS6_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS6_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS6_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS6_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS6_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS6_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS7 ======================================================== */ + #define R_I3C0_DATBAS7_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS7_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS7_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS7_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS7_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS7_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS7_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS7_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS7_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS7_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS7_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ /* ======================================================= EXDATBAS ======================================================== */ #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ @@ -24709,6 +25505,66 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT4 ========================================================= */ + #define R_I3C0_MSDCT4_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT4_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT4_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT4_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT4_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT4_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT4_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT4_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT5 ========================================================= */ + #define R_I3C0_MSDCT5_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT5_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT5_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT5_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT5_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT5_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT5_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT5_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT6 ========================================================= */ + #define R_I3C0_MSDCT6_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT6_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT6_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT6_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT6_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT6_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT6_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT6_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT7 ========================================================= */ + #define R_I3C0_MSDCT7_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT7_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT7_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT7_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT7_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT7_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT7_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT7_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ========================================================= SVDCT ========================================================= */ #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ @@ -24737,6 +25593,24 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD1 ======================================================== */ + #define R_I3C0_SVDVAD1_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD1_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD1_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD1_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD1_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD1_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD2 ======================================================== */ + #define R_I3C0_SVDVAD2_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD2_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD2_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD2_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD2_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD2_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ /* ======================================================== CSECMD ========================================================= */ #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ @@ -24781,10 +25655,23 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ /* ========================================================= CETSM ========================================================= */ + #define R_I3C0_CETSM_SPTSYN_Pos (0UL) /*!< SPTSYN (Bit 0) */ + #define R_I3C0_CETSM_SPTSYN_Msk (0x1UL) /*!< SPTSYN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN0_Pos (1UL) /*!< SPTASYN0 (Bit 1) */ + #define R_I3C0_CETSM_SPTASYN0_Msk (0x2UL) /*!< SPTASYN0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN1_Pos (2UL) /*!< SPTASYN1 (Bit 2) */ + #define R_I3C0_CETSM_SPTASYN1_Msk (0x4UL) /*!< SPTASYN1 (Bitfield-Mask: 0x01) */ #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ========================================================= CETSS ========================================================= */ + #define R_I3C0_CETSS_SYNE_Pos (0UL) /*!< SYNE (Bit 0) */ + #define R_I3C0_CETSS_SYNE_Msk (0x1UL) /*!< SYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSS_ASYNE_Pos (1UL) /*!< ASYNE (Bit 1) */ + #define R_I3C0_CETSS_ASYNE_Msk (0x6UL) /*!< ASYNE (Bitfield-Mask: 0x03) */ + #define R_I3C0_CETSS_ICOVF_Pos (7UL) /*!< ICOVF (Bit 7) */ + #define R_I3C0_CETSS_ICOVF_Msk (0x80UL) /*!< ICOVF (Bitfield-Mask: 0x01) */ /* ======================================================= CGHDRCAP ======================================================== */ #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ @@ -24814,6 +25701,16 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= NRSQSTLV ======================================================== */ #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HQSTLV ========================================================= */ + #define R_I3C0_HQSTLV_CMDQLV_Pos (0UL) /*!< CMDQLV (Bit 0) */ + #define R_I3C0_HQSTLV_CMDQLV_Msk (0xffUL) /*!< CMDQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_HQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HDBSTLV ======================================================== */ + #define R_I3C0_HDBSTLV_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_HDBSTLV_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HDBSTLV_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_HDBSTLV_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ /* ======================================================== PRSTDBG ======================================================== */ #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ @@ -24826,6 +25723,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= MSERRCNT ======================================================== */ #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ +/* ======================================================== SC1CPT ========================================================= */ + #define R_I3C0_SC1CPT_SC1C_Pos (0UL) /*!< SC1C (Bit 0) */ + #define R_I3C0_SC1CPT_SC1C_Msk (0xffffUL) /*!< SC1C (Bitfield-Mask: 0xffff) */ +/* ======================================================== SC2CPT ========================================================= */ + #define R_I3C0_SC2CPT_SC2C_Pos (0UL) /*!< SC2C (Bit 0) */ + #define R_I3C0_SC2CPT_SC2C_Msk (0xffffUL) /*!< SC2C (Bitfield-Mask: 0xffff) */ /* =========================================================================================================================== */ /* ================ R_MPU_MMPU ================ */ @@ -27281,14 +28184,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== UFRMNUM ======================================================== */ - #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ /* ======================================================== USBADDR ======================================================== */ #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ /* ======================================================== USBREQ ========================================================= */ @@ -28687,6 +29588,51 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ R_AGTX0 ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= EC710CTL ======================================================== */ + #define R_ECCMB0_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ + #define R_ECCMB0_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ + #define R_ECCMB0_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ + #define R_ECCMB0_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ + #define R_ECCMB0_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ + #define R_ECCMB0_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ + #define R_ECCMB0_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ + #define R_ECCMB0_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Pos (16UL) /*!< ECSEDF0 (Bit 16) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Msk (0x10000UL) /*!< ECSEDF0 (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Pos (17UL) /*!< ECDEDF0 (Bit 17) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Msk (0x20000UL) /*!< ECDEDF0 (Bitfield-Mask: 0x01) */ +/* ======================================================= EC710TMC ======================================================== */ + #define R_ECCMB0_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ + #define R_ECCMB0_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ + #define R_ECCMB0_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ +/* ======================================================= EC710TED ======================================================== */ + #define R_ECCMB0_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ + #define R_ECCMB0_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EC710EAD0 ======================================================= */ + #define R_ECCMB0_EC710EAD0_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ + #define R_ECCMB0_EC710EAD0_ECEAD_Msk (0x3ffUL) /*!< ECEAD (Bitfield-Mask: 0x3ff) */ + /* =========================================================================================================================== */ /* ================ R_FLAD ================ */ /* =========================================================================================================================== */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h index 3c210a047..9e9a351f0 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h @@ -1763,7 +1763,31 @@ typedef struct /*!< (@ 0x40085000) R_ACMPHS0 Structure __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ } CPIOC_b; }; -} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ + __IM uint8_t RESERVED4[47]; + + union + { + __IOM uint8_t CPINTCTL; /*!< (@ 0x00000040) Comparator Interrupt Control Register */ + + struct + { + __IOM uint8_t MSKE : 1; /*!< [0..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 7; + } CPINTCTL_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t CPMSKCTL; /*!< (@ 0x00000044) Comparator Interrupt Mask Control Register */ + + struct + { + __IOM uint8_t MSKSEL : 3; /*!< [2..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 5; + } CPMSKCTL_b; + }; +} R_ACMPHS0_Type; /*!< Size = 69 (0x45) */ /* =========================================================================================================================== */ /* ================ R_ADC0 ================ */ @@ -2026,7 +2050,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -2039,7 +2063,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -4174,8 +4198,8 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure struct { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ uint32_t : 7; __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ @@ -5650,7 +5674,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -5697,7 +5722,8 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -5708,7 +5734,10 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -5725,24 +5754,26 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -5786,12 +5817,24 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -6268,7 +6311,57 @@ typedef struct /*!< (@ 0x40078000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -11595,6 +11688,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_AGTX7_BASE 0x40084700UL #define R_AGTX8_BASE 0x40084800UL #define R_AGTX9_BASE 0x40084900UL + #define R_WDT1_BASE 0x40044300UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -11714,6 +11808,7 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -12423,32 +12518,38 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== CMPCTL ========================================================= */ - #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ - #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ - #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ - #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ - #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ - #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ - #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ - #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ - #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ /* ======================================================== CMPSEL0 ======================================================== */ - #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ - #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ /* ======================================================== CMPSEL1 ======================================================== */ - #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ - #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ /* ======================================================== CMPMON ========================================================= */ - #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ - #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ /* ========================================================= CPIOC ========================================================= */ - #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ - #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ - #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPINTCTL ======================================================== */ + #define R_ACMPHS0_CPINTCTL_MSKE_Pos (0UL) /*!< MSKE (Bit 0) */ + #define R_ACMPHS0_CPINTCTL_MSKE_Msk (0x1UL) /*!< MSKE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPMSKCTL ======================================================== */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Pos (0UL) /*!< MSKSEL (Bit 0) */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Msk (0x7UL) /*!< MSKSEL (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_ADC0 ================ */ @@ -13535,9 +13636,14 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================= DMAST ========================================================= */ #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* ======================================================== DMECHR ========================================================= */ #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ @@ -13547,11 +13653,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -14074,6 +14175,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -14097,6 +14200,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -14136,9 +14241,15 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -14213,7 +14324,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -14250,8 +14367,6 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -14437,6 +14552,24 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h index ac9db4c0f..6ec5be061 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h @@ -2262,7 +2262,31 @@ typedef struct /*!< (@ 0x400F4000) R_ACMPHS0 Structure __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ } CPIOC_b; }; -} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ + __IM uint8_t RESERVED4[47]; + + union + { + __IOM uint8_t CPINTCTL; /*!< (@ 0x00000040) Comparator Interrupt Control Register */ + + struct + { + __IOM uint8_t MSKE : 1; /*!< [0..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 7; + } CPINTCTL_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t CPMSKCTL; /*!< (@ 0x00000044) Comparator Interrupt Mask Control Register */ + + struct + { + __IOM uint8_t MSKSEL : 3; /*!< [2..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 5; + } CPMSKCTL_b; + }; +} R_ACMPHS0_Type; /*!< Size = 69 (0x45) */ /* =========================================================================================================================== */ /* ================ R_ADC0 ================ */ @@ -2525,7 +2549,7 @@ typedef struct /*!< (@ 0x40170000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -2538,7 +2562,7 @@ typedef struct /*!< (@ 0x40170000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -4362,8 +4386,8 @@ typedef struct /*!< (@ 0x400B0000) R_CANFD0 Structure struct { - __IM uint32_t RFXIF : 1; /*!< [0..0] RX FIFO[x] Interrupt Flag Status */ - uint32_t : 31; + __IM uint32_t RFXIF : 2; /*!< [1..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 30; } CFDRFISTS_b; }; @@ -5055,8 +5079,8 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure struct { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ uint32_t : 7; __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ @@ -6478,7 +6502,8 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -6525,7 +6550,8 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -6536,7 +6562,10 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -6553,24 +6582,26 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -6614,12 +6645,24 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -7096,7 +7139,57 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -8344,20 +8437,25 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure union { - __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ struct { - __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ - __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ - __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ - __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ - __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ - __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ - __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ - uint32_t : 9; - __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ - uint32_t : 15; + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 2; + __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset */ + __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese */ + __IOM uint32_t HTDBRST : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset */ + __IOM uint32_t HRDBRST : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset */ + uint32_t : 3; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; } RSTCTL_b; }; @@ -8487,8 +8585,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ uint32_t : 8; __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ - __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */ - uint32_t : 15; + __IOM uint32_t SVAEn : 3; /*!< [18..16] Slave Address Enable */ + uint32_t : 13; } SVCTL_b; }; __IM uint32_t RESERVED6[2]; @@ -8530,7 +8628,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ uint32_t : 2; - __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */ + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull */ uint32_t : 2; } EXTBR_b; }; @@ -8684,7 +8782,57 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ } SVTDLG0_b; }; - __IM uint32_t RESERVED11[31]; + __IM uint32_t RESERVED11[23]; + + union + { + __IOM uint32_t STCTL; /*!< (@ 0x00000120) Synchronous Timing Control Register */ + + struct + { + __IOM uint32_t STOE : 1; /*!< [0..0] Synchronous Timing output Enable */ + uint32_t : 31; + } STCTL_b; + }; + + union + { + __IOM uint32_t ATCTL; /*!< (@ 0x00000124) Asynchronous Timing Control Register */ + + struct + { + __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select */ + __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow) */ + __IOM uint32_t AMEOE : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable */ + uint32_t : 5; + __IOM uint32_t CDIV : 8; /*!< [15..8] TCLK Counter Divide Setting */ + uint32_t : 16; + } ATCTL_b; + }; + + union + { + __IOM uint32_t ATTRG; /*!< (@ 0x00000128) Asynchronous Timing Trigger Register */ + + struct + { + __OM uint32_t ATSTRG : 1; /*!< [0..0] Asynchronous Timing Software Trigger */ + uint32_t : 31; + } ATTRG_b; + }; + + union + { + __IOM uint32_t ATCCNTE; /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register */ + + struct + { + __IOM uint32_t ATCE : 1; /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1, + * SC2. */ + uint32_t : 31; + } ATCCNTE_b; + }; + __IM uint32_t RESERVED12[4]; union { @@ -8698,14 +8846,43 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 29; } CNDCTL_b; }; - __IM uint32_t RESERVED12[3]; + __IM uint32_t RESERVED13[3]; __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ - __IM uint32_t RESERVED13[8]; + __IM uint32_t RESERVED14[8]; __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ - __IM uint32_t RESERVED14[3]; + + union + { + __OM uint32_t HCMDQP; /*!< (@ 0x00000184) High Priority Command Queue Port Register */ + + struct + { + __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port */ + } HCMDQP_b; + }; + + union + { + __IM uint32_t HRSPQP; /*!< (@ 0x00000188) High Priority Response Queue Port Register */ + + struct + { + __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port */ + } HRSPQP_b; + }; + + union + { + __IOM uint32_t HTDTBP; /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register */ + + struct + { + __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port */ + } HTDTBP_b; + }; union { @@ -8750,7 +8927,37 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } NRQTHCTL_b; }; - __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t HQTHCTL; /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold */ + uint32_t : 16; + } HQTHCTL_b; + }; + + union + { + __IOM uint32_t HTBTHCTL; /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold + * Control Register */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold */ + uint32_t : 5; + } HTBTHCTL_b; + }; + __IM uint32_t RESERVED16; union { @@ -8923,7 +9130,79 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 11; } NTSTFC_b; }; - __IM uint32_t RESERVED17[8]; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint32_t HTST; /*!< (@ 0x00000200) High Priority Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag */ + __IOM uint32_t RDBFF : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag */ + uint32_t : 1; + __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] High Priority Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] High Priority Transfer Error Flag */ + uint32_t : 22; + } HTST_b; + }; + + union + { + __IOM uint32_t HTSTE; /*!< (@ 0x00000204) High Priority Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable */ + __IOM uint32_t RDBFE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] High Priority Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] High Priority Transfer Error Enable */ + uint32_t : 22; + } HTSTE_b; + }; + + union + { + __IOM uint32_t HTIE; /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable */ + __IOM uint32_t RDBFIE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable */ + uint32_t : 22; + } HTIE_b; + }; + + union + { + __IOM uint32_t HTSTFC; /*!< (@ 0x0000020C) High Priority Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force */ + __OM uint32_t RDBFFC : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force */ + uint32_t : 1; + __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] High Priority Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] High Priority Transfer Error Force */ + uint32_t : 22; + } HTSTFC_b; + }; union { @@ -8950,22 +9229,32 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ uint32_t : 8; __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ - __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */ - uint32_t : 15; + __IOM uint32_t SVAFn : 3; /*!< [18..16] Slave Address Detection Flag */ + uint32_t : 13; } SVST_b; }; union { - __IOM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Control Register */ + __IM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Operating Status Register */ struct { - __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ - uint32_t : 31; + __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; } WUST_b; }; - __IM uint32_t RESERVED18[2]; + + union + { + __IM uint32_t MRCCPT; /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register */ + + struct + { + __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture */ + } MRCCPT_b; + }; + __IM uint32_t RESERVED18; union { @@ -9045,7 +9334,87 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ } DATBAS3_b; }; - __IM uint32_t RESERVED22[24]; + __IM uint32_t RESERVED22; + + union + { + __IOM uint32_t DATBAS4; /*!< (@ 0x00000244) Device Address Table Basic Register 4 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS4_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IOM uint32_t DATBAS5; /*!< (@ 0x0000024C) Device Address Table Basic Register 5 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS5_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t DATBAS6; /*!< (@ 0x00000254) Device Address Table Basic Register 6 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS6_b; + }; + __IM uint32_t RESERVED25; + + union + { + __IOM uint32_t DATBAS7; /*!< (@ 0x0000025C) Device Address Table Basic Register 7 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS7_b; + }; + __IM uint32_t RESERVED26[16]; union { @@ -9061,7 +9430,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ } EXDATBAS_b; }; - __IM uint32_t RESERVED23[3]; + __IM uint32_t RESERVED27[3]; union { @@ -9110,7 +9479,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 9; } SDATBAS2_b; }; - __IM uint32_t RESERVED24[5]; + __IM uint32_t RESERVED28[5]; union { @@ -9183,7 +9552,79 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 16; } MSDCT3_b; }; - __IM uint32_t RESERVED25[16]; + + union + { + __IOM uint32_t MSDCT4; /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT4_b; + }; + + union + { + __IOM uint32_t MSDCT5; /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT5_b; + }; + + union + { + __IOM uint32_t MSDCT6; /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT6_b; + }; + + union + { + __IOM uint32_t MSDCT7; /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT7_b; + }; + __IM uint32_t RESERVED29[12]; union { @@ -9206,7 +9647,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure * ID Low Register */ __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional * ID High Register */ - __IM uint32_t RESERVED26; + __IM uint32_t RESERVED30; union { @@ -9223,7 +9664,39 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ } SVDVAD0_b; }; - __IM uint32_t RESERVED27[7]; + + union + { + __IM uint32_t SVDVAD1; /*!< (@ 0x00000334) Slave Device Address Register 1 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD1_b; + }; + + union + { + __IM uint32_t SVDVAD2; /*!< (@ 0x00000338) Slave Device Address Register 2 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD2_b; + }; + __IM uint32_t RESERVED31[5]; union { @@ -9336,18 +9809,35 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure union { - __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) - * Register */ + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ struct { - uint32_t : 8; - __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ - __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ - uint32_t : 8; + __IOM uint32_t SPTSYN : 1; /*!< [0..0] Supports Sync Mode */ + __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0 */ + __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1 */ + uint32_t : 5; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; } CETSM_b; }; - __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t CETSS; /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State) + * Register */ + + struct + { + __IOM uint32_t SYNE : 1; /*!< [0..0] Sync Mode Enabled */ + __IOM uint32_t ASYNE : 2; /*!< [2..1] Async Mode Enabled */ + uint32_t : 4; + __IOM uint32_t ICOVF : 1; /*!< [7..7] Internal Counter Overflow */ + uint32_t : 24; + } CETSS_b; + }; union { @@ -9374,7 +9864,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } BITCNT_b; }; - __IM uint32_t RESERVED29[4]; + __IM uint32_t RESERVED32[4]; union { @@ -9392,7 +9882,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure union { - __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */ + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0 */ struct { @@ -9401,7 +9891,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 16; } NDBSTLV0_b; }; - __IM uint32_t RESERVED30[9]; + __IM uint32_t RESERVED33[9]; union { @@ -9413,7 +9903,30 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } NRSQSTLV_b; }; - __IM uint32_t RESERVED31[2]; + + union + { + __IM uint32_t HQSTLV; /*!< (@ 0x000003C4) High Priority Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQLV : 8; /*!< [7..0] High Priority Command Queue Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] High Priority Response Queue Level */ + uint32_t : 16; + } HQSTLV_b; + }; + + union + { + __IM uint32_t HDBSTLV; /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] High Priority Tx Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] High Priority Rx Data Buffer Level */ + uint32_t : 16; + } HDBSTLV_b; + }; union { @@ -9439,7 +9952,30 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } MSERRCNT_b; }; -} R_I3C0_Type; /*!< Size = 980 (0x3d4) */ + __IM uint32_t RESERVED34[3]; + + union + { + __IM uint32_t SC1CPT; /*!< (@ 0x000003E0) SC1 Capture monitor Register */ + + struct + { + __IM uint32_t SC1C : 16; /*!< [15..0] SC1 Capture */ + uint32_t : 16; + } SC1CPT_b; + }; + + union + { + __IM uint32_t SC2CPT; /*!< (@ 0x000003E4) SC2 Capture monitor Register */ + + struct + { + __IM uint32_t SC2C : 16; /*!< [15..0] SC2 Capture */ + uint32_t : 16; + } SC2CPT_b; + }; +} R_I3C0_Type; /*!< Size = 1000 (0x3e8) */ /* =========================================================================================================================== */ /* ================ R_MPU_MMPU ================ */ @@ -14096,8 +14632,8 @@ typedef struct /*!< (@ 0x40170000) R_ADC_B0 Structure struct { - __IOM uint32_t ADIEn : 10; /*!< [9..0] Scan Group n Scan End Interrupt Enable */ - uint32_t : 22; + __IOM uint32_t ADIEn : 9; /*!< [8..0] Scan Group n Scan End Interrupt Enable */ + uint32_t : 23; } ADINTCR_b; }; __IM uint32_t RESERVED3[24]; @@ -19660,6 +20196,81 @@ typedef struct /*!< (@ 0x400E8000) R_AGTX0 Structure }; } R_AGTX0_Type; /*!< Size = 20 (0x14) */ +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CANFD ECC (R_ECCMB0) + */ + +typedef struct /*!< (@ 0x4036F200) R_ECCMB0 Structure */ +{ + union + { + __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ + + struct + { + __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Message Flag */ + __IM uint32_t ECER1F : 1; /*!< [1..1] ECC Error Detection and Correction Flag */ + __IM uint32_t ECER2F : 1; /*!< [2..2] 2-bit ECC Error Detection Flag */ + __IOM uint32_t EC1EDIC : 1; /*!< [3..3] ECC 1-bit Error Detection Interrupt Control */ + __IOM uint32_t EC2EDIC : 1; /*!< [4..4] ECC 2-bit Error Detection Interrupt Control */ + __IOM uint32_t EC1ECP : 1; /*!< [5..5] ECC 1-bit Error Correction Permission */ + __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Judgment Enable Flag */ + uint32_t : 2; + __IOM uint32_t ECER1C : 1; /*!< [9..9] Accumulating ECC Error Detection and Correction Flag + * Clear */ + __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-bit ECC Error Detection Flag Clear */ + __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Overflow Detection Flag */ + uint32_t : 2; + __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Select bit */ + __IM uint32_t ECSEDF0 : 1; /*!< [16..16] ECC Single bit Error Address Detection Flag */ + __IM uint32_t ECDEDF0 : 1; /*!< [17..17] ECC Dual Bit Error Address Detection Flag */ + uint32_t : 14; + } EC710CTL_b; + }; + + union + { + __IOM uint16_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ + uint16_t : 5; + __IOM uint16_t ECTMCE : 1; /*!< [7..7] ECC Test Mode Control Enable */ + uint16_t : 6; + __IOM uint16_t ETMA : 2; /*!< [15..14] ECC Test Mode Bit Access Control */ + } EC710TMC_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Test Substitute Data Register */ + + struct + { + __IOM uint32_t ECEDB : 32; /*!< [31..0] ECC Test Substitute Data */ + } EC710TED_b; + }; + + union + { + __IM uint32_t EC710EAD0; /*!< (@ 0x00000010) ECC Error Address Register */ + + struct + { + __IM uint32_t ECEAD : 10; /*!< [9..0] ECC Error Address */ + uint32_t : 22; + } EC710EAD0_b; + }; +} R_ECCMB0_Type; /*!< Size = 20 (0x14) */ + /* =========================================================================================================================== */ /* ================ R_FLAD ================ */ /* =========================================================================================================================== */ @@ -19815,11 +20426,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGTX7_BASE 0x400E8700UL #define R_AGTX8_BASE 0x400E8800UL #define R_AGTX9_BASE 0x400E8900UL + #define R_ECCMB0_BASE 0x4036F200UL + #define R_ECCMB1_BASE 0x4036F300UL #define R_FLAD_BASE 0x407FC000UL #define R_SCI_B5_BASE 0x40118500UL #define R_SCI_B6_BASE 0x40118600UL #define R_SCI_B7_BASE 0x40118700UL #define R_SCI_B8_BASE 0x40118800UL + #define R_WDT1_BASE 0x40044300UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -19954,11 +20568,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGTW7 ((R_AGTX0_Type *) R_AGTX7_BASE) #define R_AGTW8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGTW9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_ECCMB0 ((R_ECCMB0_Type *) R_ECCMB0_BASE) + #define R_ECCMB1 ((R_ECCMB0_Type *) R_ECCMB1_BASE) #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) #define R_SCI_B5 ((R_SCI_B0_Type *) R_SCI_B5_BASE) #define R_SCI_B6 ((R_SCI_B0_Type *) R_SCI_B6_BASE) #define R_SCI_B7 ((R_SCI_B0_Type *) R_SCI_B7_BASE) #define R_SCI_B8 ((R_SCI_B0_Type *) R_SCI_B8_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -21009,32 +21626,38 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== CMPCTL ========================================================= */ - #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ - #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ - #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ - #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ - #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ - #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ - #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ - #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ - #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ /* ======================================================== CMPSEL0 ======================================================== */ - #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ - #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ /* ======================================================== CMPSEL1 ======================================================== */ - #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ - #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ /* ======================================================== CMPMON ========================================================= */ - #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ - #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ /* ========================================================= CPIOC ========================================================= */ - #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ - #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ - #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPINTCTL ======================================================== */ + #define R_ACMPHS0_CPINTCTL_MSKE_Pos (0UL) /*!< MSKE (Bit 0) */ + #define R_ACMPHS0_CPINTCTL_MSKE_Msk (0x1UL) /*!< MSKE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPMSKCTL ======================================================== */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Pos (0UL) /*!< MSKSEL (Bit 0) */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Msk (0x7UL) /*!< MSKSEL (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_ADC0 ================ */ @@ -21948,7 +22571,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x100UL) /*!< CFXMLT (Bitfield-Mask: 0x01) */ /* ======================================================= CFDRFISTS ======================================================= */ #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ - #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x1UL) /*!< RFXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x3UL) /*!< RFXIF (Bitfield-Mask: 0x03) */ /* ======================================================== CFDTMC ========================================================= */ #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ @@ -22194,9 +22817,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================= DMAST ========================================================= */ #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* ======================================================== DMECHR ========================================================= */ #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ @@ -22206,11 +22834,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -22726,6 +23349,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -22749,6 +23374,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -22788,9 +23415,15 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -22865,7 +23498,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -22902,8 +23541,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -23089,6 +23726,24 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ @@ -23851,6 +24506,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HCMDQRST_Pos (9UL) /*!< HCMDQRST (Bit 9) */ + #define R_I3C0_RSTCTL_HCMDQRST_Msk (0x200UL) /*!< HCMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRSPQRST_Pos (10UL) /*!< HRSPQRST (Bit 10) */ + #define R_I3C0_RSTCTL_HRSPQRST_Msk (0x400UL) /*!< HRSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HTDBRST_Pos (11UL) /*!< HTDBRST (Bit 11) */ + #define R_I3C0_RSTCTL_HTDBRST_Msk (0x800UL) /*!< HTDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRDBRST_Pos (12UL) /*!< HRDBRST (Bit 12) */ + #define R_I3C0_RSTCTL_HRDBRST_Msk (0x1000UL) /*!< HRDBRST (Bitfield-Mask: 0x01) */ #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ /* ========================================================= PRSST ========================================================= */ @@ -23907,7 +24570,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ - #define R_I3C0_SVCTL_SVAEn_Msk (0x10000UL) /*!< SVAEn (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_SVAEn_Msk (0x70000UL) /*!< SVAEn (Bitfield-Mask: 0x07) */ /* ======================================================= REFCKCTL ======================================================== */ #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ @@ -24002,6 +24665,24 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================== SVTDLG0 ======================================================== */ #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= STCTL ========================================================= */ + #define R_I3C0_STCTL_STOE_Pos (0UL) /*!< STOE (Bit 0) */ + #define R_I3C0_STCTL_STOE_Msk (0x1UL) /*!< STOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ATCTL ========================================================= */ + #define R_I3C0_ATCTL_ATTRGS_Pos (0UL) /*!< ATTRGS (Bit 0) */ + #define R_I3C0_ATCTL_ATTRGS_Msk (0x1UL) /*!< ATTRGS (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_MREFOE_Pos (1UL) /*!< MREFOE (Bit 1) */ + #define R_I3C0_ATCTL_MREFOE_Msk (0x2UL) /*!< MREFOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_AMEOE_Pos (2UL) /*!< AMEOE (Bit 2) */ + #define R_I3C0_ATCTL_AMEOE_Msk (0x4UL) /*!< AMEOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_CDIV_Pos (8UL) /*!< CDIV (Bit 8) */ + #define R_I3C0_ATCTL_CDIV_Msk (0xff00UL) /*!< CDIV (Bitfield-Mask: 0xff) */ +/* ========================================================= ATTRG ========================================================= */ + #define R_I3C0_ATTRG_ATSTRG_Pos (0UL) /*!< ATSTRG (Bit 0) */ + #define R_I3C0_ATTRG_ATSTRG_Msk (0x1UL) /*!< ATSTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== ATCCNTE ======================================================== */ + #define R_I3C0_ATCCNTE_ATCE_Pos (0UL) /*!< ATCE (Bit 0) */ + #define R_I3C0_ATCCNTE_ATCE_Msk (0x1UL) /*!< ATCE (Bitfield-Mask: 0x01) */ /* ======================================================== CNDCTL ========================================================= */ #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ @@ -24014,6 +24695,15 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================== NTDTBP0 ======================================================== */ /* ======================================================== NIBIQP ========================================================= */ /* ========================================================= NRSQP ========================================================= */ +/* ======================================================== HCMDQP ========================================================= */ + #define R_I3C0_HCMDQP_HCMDQP_Pos (0UL) /*!< HCMDQP (Bit 0) */ + #define R_I3C0_HCMDQP_HCMDQP_Msk (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HRSPQP ========================================================= */ + #define R_I3C0_HRSPQP_HRSPQP_Pos (0UL) /*!< HRSPQP (Bit 0) */ + #define R_I3C0_HRSPQP_HRSPQP_Msk (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HTDTBP ========================================================= */ + #define R_I3C0_HTDTBP_HTDTBP_Pos (0UL) /*!< HTDTBP (Bit 0) */ + #define R_I3C0_HTDTBP_HTDTBP_Msk (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff) */ /* ======================================================== NQTHCTL ======================================================== */ #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ @@ -24035,6 +24725,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= NRQTHCTL ======================================================== */ #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ +/* ======================================================== HQTHCTL ======================================================== */ + #define R_I3C0_HQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_HQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_HQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= HTBTHCTL ======================================================== */ + #define R_I3C0_HTBTHCTL_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_HTBTHCTL_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ /* ========================================================== BST ========================================================== */ #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ @@ -24171,6 +24875,58 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ +/* ========================================================= HTST ========================================================== */ + #define R_I3C0_HTST_TDBEF_Pos (0UL) /*!< TDBEF (Bit 0) */ + #define R_I3C0_HTST_TDBEF_Msk (0x1UL) /*!< TDBEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RDBFF_Pos (1UL) /*!< RDBFF (Bit 1) */ + #define R_I3C0_HTST_RDBFF_Msk (0x2UL) /*!< RDBFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_HTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_HTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_HTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_HTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ +/* ========================================================= HTSTE ========================================================= */ + #define R_I3C0_HTSTE_TDBEE_Pos (0UL) /*!< TDBEE (Bit 0) */ + #define R_I3C0_HTSTE_TDBEE_Msk (0x1UL) /*!< TDBEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RDBFE_Pos (1UL) /*!< RDBFE (Bit 1) */ + #define R_I3C0_HTSTE_RDBFE_Msk (0x2UL) /*!< RDBFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_HTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_HTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_HTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_HTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ +/* ========================================================= HTIE ========================================================== */ + #define R_I3C0_HTIE_TDBEIE_Pos (0UL) /*!< TDBEIE (Bit 0) */ + #define R_I3C0_HTIE_TDBEIE_Msk (0x1UL) /*!< TDBEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RDBFIE_Pos (1UL) /*!< RDBFIE (Bit 1) */ + #define R_I3C0_HTIE_RDBFIE_Msk (0x2UL) /*!< RDBFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_HTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_HTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_HTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_HTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== HTSTFC ========================================================= */ + #define R_I3C0_HTSTFC_TDBEFC_Pos (0UL) /*!< TDBEFC (Bit 0) */ + #define R_I3C0_HTSTFC_TDBEFC_Msk (0x1UL) /*!< TDBEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RDBFFC_Pos (1UL) /*!< RDBFFC (Bit 1) */ + #define R_I3C0_HTSTFC_RDBFFC_Msk (0x2UL) /*!< RDBFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_HTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_HTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_HTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_HTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ /* ========================================================= BCST ========================================================== */ #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ @@ -24188,10 +24944,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ - #define R_I3C0_SVST_SVAFn_Msk (0x10000UL) /*!< SVAFn (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_SVAFn_Msk (0x70000UL) /*!< SVAFn (Bitfield-Mask: 0x07) */ /* ========================================================= WUST ========================================================== */ #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCCPT ========================================================= */ + #define R_I3C0_MRCCPT_MRCCPT_Pos (0UL) /*!< MRCCPT (Bit 0) */ + #define R_I3C0_MRCCPT_MRCCPT_Msk (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff) */ /* ======================================================== DATBAS0 ======================================================== */ #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ @@ -24260,6 +25019,74 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS4 ======================================================== */ + #define R_I3C0_DATBAS4_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS4_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS4_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS4_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS4_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS4_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS4_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS4_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS4_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS4_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS4_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS5 ======================================================== */ + #define R_I3C0_DATBAS5_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS5_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS5_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS5_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS5_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS5_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS5_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS5_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS5_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS5_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS5_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS6 ======================================================== */ + #define R_I3C0_DATBAS6_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS6_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS6_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS6_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS6_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS6_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS6_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS6_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS6_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS6_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS6_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS7 ======================================================== */ + #define R_I3C0_DATBAS7_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS7_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS7_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS7_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS7_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS7_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS7_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS7_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS7_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS7_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS7_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ /* ======================================================= EXDATBAS ======================================================== */ #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ @@ -24356,6 +25183,66 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT4 ========================================================= */ + #define R_I3C0_MSDCT4_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT4_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT4_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT4_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT4_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT4_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT4_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT4_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT5 ========================================================= */ + #define R_I3C0_MSDCT5_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT5_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT5_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT5_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT5_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT5_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT5_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT5_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT6 ========================================================= */ + #define R_I3C0_MSDCT6_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT6_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT6_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT6_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT6_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT6_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT6_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT6_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT7 ========================================================= */ + #define R_I3C0_MSDCT7_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT7_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT7_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT7_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT7_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT7_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT7_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT7_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ========================================================= SVDCT ========================================================= */ #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ @@ -24384,6 +25271,24 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD1 ======================================================== */ + #define R_I3C0_SVDVAD1_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD1_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD1_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD1_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD1_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD1_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD2 ======================================================== */ + #define R_I3C0_SVDVAD2_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD2_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD2_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD2_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD2_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD2_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ /* ======================================================== CSECMD ========================================================= */ #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ @@ -24428,10 +25333,23 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ /* ========================================================= CETSM ========================================================= */ + #define R_I3C0_CETSM_SPTSYN_Pos (0UL) /*!< SPTSYN (Bit 0) */ + #define R_I3C0_CETSM_SPTSYN_Msk (0x1UL) /*!< SPTSYN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN0_Pos (1UL) /*!< SPTASYN0 (Bit 1) */ + #define R_I3C0_CETSM_SPTASYN0_Msk (0x2UL) /*!< SPTASYN0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN1_Pos (2UL) /*!< SPTASYN1 (Bit 2) */ + #define R_I3C0_CETSM_SPTASYN1_Msk (0x4UL) /*!< SPTASYN1 (Bitfield-Mask: 0x01) */ #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ========================================================= CETSS ========================================================= */ + #define R_I3C0_CETSS_SYNE_Pos (0UL) /*!< SYNE (Bit 0) */ + #define R_I3C0_CETSS_SYNE_Msk (0x1UL) /*!< SYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSS_ASYNE_Pos (1UL) /*!< ASYNE (Bit 1) */ + #define R_I3C0_CETSS_ASYNE_Msk (0x6UL) /*!< ASYNE (Bitfield-Mask: 0x03) */ + #define R_I3C0_CETSS_ICOVF_Pos (7UL) /*!< ICOVF (Bit 7) */ + #define R_I3C0_CETSS_ICOVF_Msk (0x80UL) /*!< ICOVF (Bitfield-Mask: 0x01) */ /* ======================================================= CGHDRCAP ======================================================== */ #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ @@ -24461,6 +25379,16 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= NRSQSTLV ======================================================== */ #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HQSTLV ========================================================= */ + #define R_I3C0_HQSTLV_CMDQLV_Pos (0UL) /*!< CMDQLV (Bit 0) */ + #define R_I3C0_HQSTLV_CMDQLV_Msk (0xffUL) /*!< CMDQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_HQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HDBSTLV ======================================================== */ + #define R_I3C0_HDBSTLV_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_HDBSTLV_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HDBSTLV_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_HDBSTLV_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ /* ======================================================== PRSTDBG ======================================================== */ #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ @@ -24473,6 +25401,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= MSERRCNT ======================================================== */ #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ +/* ======================================================== SC1CPT ========================================================= */ + #define R_I3C0_SC1CPT_SC1C_Pos (0UL) /*!< SC1C (Bit 0) */ + #define R_I3C0_SC1CPT_SC1C_Msk (0xffffUL) /*!< SC1C (Bitfield-Mask: 0xffff) */ +/* ======================================================== SC2CPT ========================================================= */ + #define R_I3C0_SC2CPT_SC2C_Pos (0UL) /*!< SC2C (Bit 0) */ + #define R_I3C0_SC2CPT_SC2C_Msk (0xffffUL) /*!< SC2C (Bitfield-Mask: 0xffff) */ /* =========================================================================================================================== */ /* ================ R_MPU_MMPU ================ */ @@ -26350,7 +27284,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_ADC_B0_ADSGCR2_SGADS8_Msk (0x3UL) /*!< SGADS8 (Bitfield-Mask: 0x03) */ /* ======================================================== ADINTCR ======================================================== */ #define R_ADC_B0_ADINTCR_ADIEn_Pos (0UL) /*!< ADIEn (Bit 0) */ - #define R_ADC_B0_ADINTCR_ADIEn_Msk (0x3ffUL) /*!< ADIEn (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADINTCR_ADIEn_Msk (0x1ffUL) /*!< ADIEn (Bitfield-Mask: 0x1ff) */ /* ======================================================= ADTRGEXT0 ======================================================= */ #define R_ADC_B0_ADTRGEXT0_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ #define R_ADC_B0_ADTRGEXT0_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ @@ -29108,6 +30042,51 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ R_AGTX0 ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= EC710CTL ======================================================== */ + #define R_ECCMB0_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ + #define R_ECCMB0_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ + #define R_ECCMB0_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ + #define R_ECCMB0_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ + #define R_ECCMB0_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ + #define R_ECCMB0_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ + #define R_ECCMB0_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ + #define R_ECCMB0_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Pos (16UL) /*!< ECSEDF0 (Bit 16) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Msk (0x10000UL) /*!< ECSEDF0 (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Pos (17UL) /*!< ECDEDF0 (Bit 17) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Msk (0x20000UL) /*!< ECDEDF0 (Bitfield-Mask: 0x01) */ +/* ======================================================= EC710TMC ======================================================== */ + #define R_ECCMB0_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ + #define R_ECCMB0_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ + #define R_ECCMB0_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ +/* ======================================================= EC710TED ======================================================== */ + #define R_ECCMB0_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ + #define R_ECCMB0_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EC710EAD0 ======================================================= */ + #define R_ECCMB0_EC710EAD0_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ + #define R_ECCMB0_EC710EAD0_ECEAD_Msk (0x3ffUL) /*!< ECEAD (Bitfield-Mask: 0x3ff) */ + /* =========================================================================================================================== */ /* ================ R_FLAD ================ */ /* =========================================================================================================================== */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T3BB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T3BB.h index a67ed1ffd..f7285b514 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T3BB.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T3BB.h @@ -2239,7 +2239,31 @@ typedef struct /*!< (@ 0x400F4000) R_ACMPHS0 Structure __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ } CPIOC_b; }; -} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ + __IM uint8_t RESERVED4[47]; + + union + { + __IOM uint8_t CPINTCTL; /*!< (@ 0x00000040) Comparator Interrupt Control Register */ + + struct + { + __IOM uint8_t MSKE : 1; /*!< [0..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 7; + } CPINTCTL_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t CPMSKCTL; /*!< (@ 0x00000044) Comparator Interrupt Mask Control Register */ + + struct + { + __IOM uint8_t MSKSEL : 3; /*!< [2..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 5; + } CPMSKCTL_b; + }; +} R_ACMPHS0_Type; /*!< Size = 69 (0x45) */ /* =========================================================================================================================== */ /* ================ R_ADC0 ================ */ @@ -2502,7 +2526,7 @@ typedef struct /*!< (@ 0x40170000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -2515,7 +2539,7 @@ typedef struct /*!< (@ 0x40170000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -4339,8 +4363,8 @@ typedef struct /*!< (@ 0x400B0000) R_CANFD0 Structure struct { - __IM uint32_t RFXIF : 1; /*!< [0..0] RX FIFO[x] Interrupt Flag Status */ - uint32_t : 31; + __IM uint32_t RFXIF : 2; /*!< [1..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 30; } CFDRFISTS_b; }; @@ -5032,8 +5056,8 @@ typedef struct /*!< (@ 0x40005200) R_DMA Structure struct { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ uint32_t : 7; __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ @@ -6508,7 +6532,8 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -6555,7 +6580,8 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -6566,7 +6592,10 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -6583,24 +6612,26 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -6644,12 +6675,24 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -7126,7 +7169,57 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -8102,20 +8195,25 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure union { - __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ struct { - __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ - __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ - __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ - __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ - __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ - __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ - __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ - uint32_t : 9; - __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ - uint32_t : 15; + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 2; + __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset */ + __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese */ + __IOM uint32_t HTDBRST : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset */ + __IOM uint32_t HRDBRST : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset */ + uint32_t : 3; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; } RSTCTL_b; }; @@ -8245,8 +8343,8 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ uint32_t : 8; __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ - __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */ - uint32_t : 15; + __IOM uint32_t SVAEn : 3; /*!< [18..16] Slave Address Enable */ + uint32_t : 13; } SVCTL_b; }; __IM uint32_t RESERVED6[2]; @@ -8288,7 +8386,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ uint32_t : 2; - __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */ + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull */ uint32_t : 2; } EXTBR_b; }; @@ -8442,7 +8540,57 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ } SVTDLG0_b; }; - __IM uint32_t RESERVED11[31]; + __IM uint32_t RESERVED11[23]; + + union + { + __IOM uint32_t STCTL; /*!< (@ 0x00000120) Synchronous Timing Control Register */ + + struct + { + __IOM uint32_t STOE : 1; /*!< [0..0] Synchronous Timing output Enable */ + uint32_t : 31; + } STCTL_b; + }; + + union + { + __IOM uint32_t ATCTL; /*!< (@ 0x00000124) Asynchronous Timing Control Register */ + + struct + { + __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select */ + __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow) */ + __IOM uint32_t AMEOE : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable */ + uint32_t : 5; + __IOM uint32_t CDIV : 8; /*!< [15..8] TCLK Counter Divide Setting */ + uint32_t : 16; + } ATCTL_b; + }; + + union + { + __IOM uint32_t ATTRG; /*!< (@ 0x00000128) Asynchronous Timing Trigger Register */ + + struct + { + __OM uint32_t ATSTRG : 1; /*!< [0..0] Asynchronous Timing Software Trigger */ + uint32_t : 31; + } ATTRG_b; + }; + + union + { + __IOM uint32_t ATCCNTE; /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register */ + + struct + { + __IOM uint32_t ATCE : 1; /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1, + * SC2. */ + uint32_t : 31; + } ATCCNTE_b; + }; + __IM uint32_t RESERVED12[4]; union { @@ -8456,14 +8604,43 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 29; } CNDCTL_b; }; - __IM uint32_t RESERVED12[3]; + __IM uint32_t RESERVED13[3]; __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ - __IM uint32_t RESERVED13[8]; + __IM uint32_t RESERVED14[8]; __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ - __IM uint32_t RESERVED14[3]; + + union + { + __OM uint32_t HCMDQP; /*!< (@ 0x00000184) High Priority Command Queue Port Register */ + + struct + { + __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port */ + } HCMDQP_b; + }; + + union + { + __IM uint32_t HRSPQP; /*!< (@ 0x00000188) High Priority Response Queue Port Register */ + + struct + { + __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port */ + } HRSPQP_b; + }; + + union + { + __IOM uint32_t HTDTBP; /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register */ + + struct + { + __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port */ + } HTDTBP_b; + }; union { @@ -8508,7 +8685,37 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } NRQTHCTL_b; }; - __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t HQTHCTL; /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold */ + uint32_t : 16; + } HQTHCTL_b; + }; + + union + { + __IOM uint32_t HTBTHCTL; /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold + * Control Register */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold */ + uint32_t : 5; + } HTBTHCTL_b; + }; + __IM uint32_t RESERVED16; union { @@ -8681,7 +8888,79 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 11; } NTSTFC_b; }; - __IM uint32_t RESERVED17[8]; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint32_t HTST; /*!< (@ 0x00000200) High Priority Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag */ + __IOM uint32_t RDBFF : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag */ + uint32_t : 1; + __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] High Priority Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] High Priority Transfer Error Flag */ + uint32_t : 22; + } HTST_b; + }; + + union + { + __IOM uint32_t HTSTE; /*!< (@ 0x00000204) High Priority Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable */ + __IOM uint32_t RDBFE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] High Priority Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] High Priority Transfer Error Enable */ + uint32_t : 22; + } HTSTE_b; + }; + + union + { + __IOM uint32_t HTIE; /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable */ + __IOM uint32_t RDBFIE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable */ + uint32_t : 22; + } HTIE_b; + }; + + union + { + __IOM uint32_t HTSTFC; /*!< (@ 0x0000020C) High Priority Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force */ + __OM uint32_t RDBFFC : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force */ + uint32_t : 1; + __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] High Priority Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] High Priority Transfer Error Force */ + uint32_t : 22; + } HTSTFC_b; + }; union { @@ -8708,22 +8987,32 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ uint32_t : 8; __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ - __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */ - uint32_t : 15; + __IOM uint32_t SVAFn : 3; /*!< [18..16] Slave Address Detection Flag */ + uint32_t : 13; } SVST_b; }; union { - __IOM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Control Register */ + __IM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Operating Status Register */ struct { - __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ - uint32_t : 31; + __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; } WUST_b; }; - __IM uint32_t RESERVED18[2]; + + union + { + __IM uint32_t MRCCPT; /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register */ + + struct + { + __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture */ + } MRCCPT_b; + }; + __IM uint32_t RESERVED18; union { @@ -8803,7 +9092,87 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ } DATBAS3_b; }; - __IM uint32_t RESERVED22[24]; + __IM uint32_t RESERVED22; + + union + { + __IOM uint32_t DATBAS4; /*!< (@ 0x00000244) Device Address Table Basic Register 4 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS4_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IOM uint32_t DATBAS5; /*!< (@ 0x0000024C) Device Address Table Basic Register 5 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS5_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t DATBAS6; /*!< (@ 0x00000254) Device Address Table Basic Register 6 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS6_b; + }; + __IM uint32_t RESERVED25; + + union + { + __IOM uint32_t DATBAS7; /*!< (@ 0x0000025C) Device Address Table Basic Register 7 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS7_b; + }; + __IM uint32_t RESERVED26[16]; union { @@ -8819,7 +9188,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ } EXDATBAS_b; }; - __IM uint32_t RESERVED23[3]; + __IM uint32_t RESERVED27[3]; union { @@ -8868,7 +9237,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 9; } SDATBAS2_b; }; - __IM uint32_t RESERVED24[5]; + __IM uint32_t RESERVED28[5]; union { @@ -8941,7 +9310,79 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 16; } MSDCT3_b; }; - __IM uint32_t RESERVED25[16]; + + union + { + __IOM uint32_t MSDCT4; /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT4_b; + }; + + union + { + __IOM uint32_t MSDCT5; /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT5_b; + }; + + union + { + __IOM uint32_t MSDCT6; /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT6_b; + }; + + union + { + __IOM uint32_t MSDCT7; /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT7_b; + }; + __IM uint32_t RESERVED29[12]; union { @@ -8964,7 +9405,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure * ID Low Register */ __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional * ID High Register */ - __IM uint32_t RESERVED26; + __IM uint32_t RESERVED30; union { @@ -8981,7 +9422,39 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ } SVDVAD0_b; }; - __IM uint32_t RESERVED27[7]; + + union + { + __IM uint32_t SVDVAD1; /*!< (@ 0x00000334) Slave Device Address Register 1 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD1_b; + }; + + union + { + __IM uint32_t SVDVAD2; /*!< (@ 0x00000338) Slave Device Address Register 2 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD2_b; + }; + __IM uint32_t RESERVED31[5]; union { @@ -9094,18 +9567,35 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure union { - __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) - * Register */ + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ struct { - uint32_t : 8; - __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ - __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ - uint32_t : 8; + __IOM uint32_t SPTSYN : 1; /*!< [0..0] Supports Sync Mode */ + __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0 */ + __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1 */ + uint32_t : 5; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; } CETSM_b; }; - __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t CETSS; /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State) + * Register */ + + struct + { + __IOM uint32_t SYNE : 1; /*!< [0..0] Sync Mode Enabled */ + __IOM uint32_t ASYNE : 2; /*!< [2..1] Async Mode Enabled */ + uint32_t : 4; + __IOM uint32_t ICOVF : 1; /*!< [7..7] Internal Counter Overflow */ + uint32_t : 24; + } CETSS_b; + }; union { @@ -9132,7 +9622,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } BITCNT_b; }; - __IM uint32_t RESERVED29[4]; + __IM uint32_t RESERVED32[4]; union { @@ -9150,7 +9640,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure union { - __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */ + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0 */ struct { @@ -9159,7 +9649,7 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 16; } NDBSTLV0_b; }; - __IM uint32_t RESERVED30[9]; + __IM uint32_t RESERVED33[9]; union { @@ -9171,7 +9661,30 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } NRSQSTLV_b; }; - __IM uint32_t RESERVED31[2]; + + union + { + __IM uint32_t HQSTLV; /*!< (@ 0x000003C4) High Priority Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQLV : 8; /*!< [7..0] High Priority Command Queue Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] High Priority Response Queue Level */ + uint32_t : 16; + } HQSTLV_b; + }; + + union + { + __IM uint32_t HDBSTLV; /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] High Priority Tx Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] High Priority Rx Data Buffer Level */ + uint32_t : 16; + } HDBSTLV_b; + }; union { @@ -9197,7 +9710,30 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure uint32_t : 24; } MSERRCNT_b; }; -} R_I3C0_Type; /*!< Size = 980 (0x3d4) */ + __IM uint32_t RESERVED34[3]; + + union + { + __IM uint32_t SC1CPT; /*!< (@ 0x000003E0) SC1 Capture monitor Register */ + + struct + { + __IM uint32_t SC1C : 16; /*!< [15..0] SC1 Capture */ + uint32_t : 16; + } SC1CPT_b; + }; + + union + { + __IM uint32_t SC2CPT; /*!< (@ 0x000003E4) SC2 Capture monitor Register */ + + struct + { + __IM uint32_t SC2C : 16; /*!< [15..0] SC2 Capture */ + uint32_t : 16; + } SC2CPT_b; + }; +} R_I3C0_Type; /*!< Size = 1000 (0x3e8) */ /* =========================================================================================================================== */ /* ================ R_MPU_MMPU ================ */ @@ -13393,7 +13929,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * data. */ uint16_t : 1; __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ } CFIFOCTR_b; }; @@ -13413,7 +13949,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D0FIFOSEL_b; }; @@ -13447,7 +13983,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D1FIFOSEL_b; }; @@ -13722,14 +14258,13 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure union { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ struct { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; + uint16_t : 15; __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; + } DVCHGR_b; }; union @@ -13742,8 +14277,8 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure * the USB address assigned by the host when the USBHS processed * the SET_ADDRESS request successfully. */ uint16_t : 1; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; } USBADDR_b; }; __IM uint16_t RESERVED9; @@ -14921,6 +15456,81 @@ typedef struct /*!< (@ 0x400E8000) R_AGTX0 Structure }; } R_AGTX0_Type; /*!< Size = 20 (0x14) */ +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CANFD ECC (R_ECCMB0) + */ + +typedef struct /*!< (@ 0x4036F200) R_ECCMB0 Structure */ +{ + union + { + __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ + + struct + { + __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Message Flag */ + __IM uint32_t ECER1F : 1; /*!< [1..1] ECC Error Detection and Correction Flag */ + __IM uint32_t ECER2F : 1; /*!< [2..2] 2-bit ECC Error Detection Flag */ + __IOM uint32_t EC1EDIC : 1; /*!< [3..3] ECC 1-bit Error Detection Interrupt Control */ + __IOM uint32_t EC2EDIC : 1; /*!< [4..4] ECC 2-bit Error Detection Interrupt Control */ + __IOM uint32_t EC1ECP : 1; /*!< [5..5] ECC 1-bit Error Correction Permission */ + __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Judgment Enable Flag */ + uint32_t : 2; + __IOM uint32_t ECER1C : 1; /*!< [9..9] Accumulating ECC Error Detection and Correction Flag + * Clear */ + __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-bit ECC Error Detection Flag Clear */ + __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Overflow Detection Flag */ + uint32_t : 2; + __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Select bit */ + __IM uint32_t ECSEDF0 : 1; /*!< [16..16] ECC Single bit Error Address Detection Flag */ + __IM uint32_t ECDEDF0 : 1; /*!< [17..17] ECC Dual Bit Error Address Detection Flag */ + uint32_t : 14; + } EC710CTL_b; + }; + + union + { + __IOM uint16_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ + uint16_t : 5; + __IOM uint16_t ECTMCE : 1; /*!< [7..7] ECC Test Mode Control Enable */ + uint16_t : 6; + __IOM uint16_t ETMA : 2; /*!< [15..14] ECC Test Mode Bit Access Control */ + } EC710TMC_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Test Substitute Data Register */ + + struct + { + __IOM uint32_t ECEDB : 32; /*!< [31..0] ECC Test Substitute Data */ + } EC710TED_b; + }; + + union + { + __IM uint32_t EC710EAD0; /*!< (@ 0x00000010) ECC Error Address Register */ + + struct + { + __IM uint32_t ECEAD : 10; /*!< [9..0] ECC Error Address */ + uint32_t : 22; + } EC710EAD0_b; + }; +} R_ECCMB0_Type; /*!< Size = 20 (0x14) */ + /* =========================================================================================================================== */ /* ================ R_FLAD ================ */ /* =========================================================================================================================== */ @@ -15065,7 +15675,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGTX7_BASE 0x400E8700UL #define R_AGTX8_BASE 0x400E8800UL #define R_AGTX9_BASE 0x400E8900UL + #define R_ECCMB0_BASE 0x4036F200UL + #define R_ECCMB1_BASE 0x4036F300UL #define R_FLAD_BASE 0x407FC000UL + #define R_WDT1_BASE 0x40044300UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -15189,7 +15802,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGTW7 ((R_AGTX0_Type *) R_AGTX7_BASE) #define R_AGTW8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGTW9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_ECCMB0 ((R_ECCMB0_Type *) R_ECCMB0_BASE) + #define R_ECCMB1 ((R_ECCMB0_Type *) R_ECCMB1_BASE) #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -16221,32 +16837,38 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== CMPCTL ========================================================= */ - #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ - #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ - #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ - #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ - #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ - #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ - #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ - #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ - #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ /* ======================================================== CMPSEL0 ======================================================== */ - #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ - #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ /* ======================================================== CMPSEL1 ======================================================== */ - #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ - #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ /* ======================================================== CMPMON ========================================================= */ - #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ - #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ /* ========================================================= CPIOC ========================================================= */ - #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ - #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ - #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPINTCTL ======================================================== */ + #define R_ACMPHS0_CPINTCTL_MSKE_Pos (0UL) /*!< MSKE (Bit 0) */ + #define R_ACMPHS0_CPINTCTL_MSKE_Msk (0x1UL) /*!< MSKE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPMSKCTL ======================================================== */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Pos (0UL) /*!< MSKSEL (Bit 0) */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Msk (0x7UL) /*!< MSKSEL (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_ADC0 ================ */ @@ -17160,7 +17782,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x100UL) /*!< CFXMLT (Bitfield-Mask: 0x01) */ /* ======================================================= CFDRFISTS ======================================================= */ #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ - #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x1UL) /*!< RFXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x3UL) /*!< RFXIF (Bitfield-Mask: 0x03) */ /* ======================================================== CFDTMC ========================================================= */ #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ @@ -17406,9 +18028,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================= DMAST ========================================================= */ #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* ======================================================== DMECHR ========================================================= */ #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ @@ -17418,11 +18045,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -17945,6 +18567,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -17968,6 +18592,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -18007,9 +18633,15 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -18084,7 +18716,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -18121,8 +18759,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -18308,6 +18944,24 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ @@ -18953,6 +19607,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HCMDQRST_Pos (9UL) /*!< HCMDQRST (Bit 9) */ + #define R_I3C0_RSTCTL_HCMDQRST_Msk (0x200UL) /*!< HCMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRSPQRST_Pos (10UL) /*!< HRSPQRST (Bit 10) */ + #define R_I3C0_RSTCTL_HRSPQRST_Msk (0x400UL) /*!< HRSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HTDBRST_Pos (11UL) /*!< HTDBRST (Bit 11) */ + #define R_I3C0_RSTCTL_HTDBRST_Msk (0x800UL) /*!< HTDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRDBRST_Pos (12UL) /*!< HRDBRST (Bit 12) */ + #define R_I3C0_RSTCTL_HRDBRST_Msk (0x1000UL) /*!< HRDBRST (Bitfield-Mask: 0x01) */ #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ /* ========================================================= PRSST ========================================================= */ @@ -19009,7 +19671,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ - #define R_I3C0_SVCTL_SVAEn_Msk (0x10000UL) /*!< SVAEn (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_SVAEn_Msk (0x70000UL) /*!< SVAEn (Bitfield-Mask: 0x07) */ /* ======================================================= REFCKCTL ======================================================== */ #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ @@ -19104,6 +19766,24 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================== SVTDLG0 ======================================================== */ #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= STCTL ========================================================= */ + #define R_I3C0_STCTL_STOE_Pos (0UL) /*!< STOE (Bit 0) */ + #define R_I3C0_STCTL_STOE_Msk (0x1UL) /*!< STOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ATCTL ========================================================= */ + #define R_I3C0_ATCTL_ATTRGS_Pos (0UL) /*!< ATTRGS (Bit 0) */ + #define R_I3C0_ATCTL_ATTRGS_Msk (0x1UL) /*!< ATTRGS (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_MREFOE_Pos (1UL) /*!< MREFOE (Bit 1) */ + #define R_I3C0_ATCTL_MREFOE_Msk (0x2UL) /*!< MREFOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_AMEOE_Pos (2UL) /*!< AMEOE (Bit 2) */ + #define R_I3C0_ATCTL_AMEOE_Msk (0x4UL) /*!< AMEOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_CDIV_Pos (8UL) /*!< CDIV (Bit 8) */ + #define R_I3C0_ATCTL_CDIV_Msk (0xff00UL) /*!< CDIV (Bitfield-Mask: 0xff) */ +/* ========================================================= ATTRG ========================================================= */ + #define R_I3C0_ATTRG_ATSTRG_Pos (0UL) /*!< ATSTRG (Bit 0) */ + #define R_I3C0_ATTRG_ATSTRG_Msk (0x1UL) /*!< ATSTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== ATCCNTE ======================================================== */ + #define R_I3C0_ATCCNTE_ATCE_Pos (0UL) /*!< ATCE (Bit 0) */ + #define R_I3C0_ATCCNTE_ATCE_Msk (0x1UL) /*!< ATCE (Bitfield-Mask: 0x01) */ /* ======================================================== CNDCTL ========================================================= */ #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ @@ -19116,6 +19796,15 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================== NTDTBP0 ======================================================== */ /* ======================================================== NIBIQP ========================================================= */ /* ========================================================= NRSQP ========================================================= */ +/* ======================================================== HCMDQP ========================================================= */ + #define R_I3C0_HCMDQP_HCMDQP_Pos (0UL) /*!< HCMDQP (Bit 0) */ + #define R_I3C0_HCMDQP_HCMDQP_Msk (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HRSPQP ========================================================= */ + #define R_I3C0_HRSPQP_HRSPQP_Pos (0UL) /*!< HRSPQP (Bit 0) */ + #define R_I3C0_HRSPQP_HRSPQP_Msk (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HTDTBP ========================================================= */ + #define R_I3C0_HTDTBP_HTDTBP_Pos (0UL) /*!< HTDTBP (Bit 0) */ + #define R_I3C0_HTDTBP_HTDTBP_Msk (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff) */ /* ======================================================== NQTHCTL ======================================================== */ #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ @@ -19137,6 +19826,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= NRQTHCTL ======================================================== */ #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ +/* ======================================================== HQTHCTL ======================================================== */ + #define R_I3C0_HQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_HQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_HQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= HTBTHCTL ======================================================== */ + #define R_I3C0_HTBTHCTL_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_HTBTHCTL_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ /* ========================================================== BST ========================================================== */ #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ @@ -19273,6 +19976,58 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ +/* ========================================================= HTST ========================================================== */ + #define R_I3C0_HTST_TDBEF_Pos (0UL) /*!< TDBEF (Bit 0) */ + #define R_I3C0_HTST_TDBEF_Msk (0x1UL) /*!< TDBEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RDBFF_Pos (1UL) /*!< RDBFF (Bit 1) */ + #define R_I3C0_HTST_RDBFF_Msk (0x2UL) /*!< RDBFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_HTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_HTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_HTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_HTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ +/* ========================================================= HTSTE ========================================================= */ + #define R_I3C0_HTSTE_TDBEE_Pos (0UL) /*!< TDBEE (Bit 0) */ + #define R_I3C0_HTSTE_TDBEE_Msk (0x1UL) /*!< TDBEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RDBFE_Pos (1UL) /*!< RDBFE (Bit 1) */ + #define R_I3C0_HTSTE_RDBFE_Msk (0x2UL) /*!< RDBFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_HTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_HTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_HTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_HTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ +/* ========================================================= HTIE ========================================================== */ + #define R_I3C0_HTIE_TDBEIE_Pos (0UL) /*!< TDBEIE (Bit 0) */ + #define R_I3C0_HTIE_TDBEIE_Msk (0x1UL) /*!< TDBEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RDBFIE_Pos (1UL) /*!< RDBFIE (Bit 1) */ + #define R_I3C0_HTIE_RDBFIE_Msk (0x2UL) /*!< RDBFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_HTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_HTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_HTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_HTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== HTSTFC ========================================================= */ + #define R_I3C0_HTSTFC_TDBEFC_Pos (0UL) /*!< TDBEFC (Bit 0) */ + #define R_I3C0_HTSTFC_TDBEFC_Msk (0x1UL) /*!< TDBEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RDBFFC_Pos (1UL) /*!< RDBFFC (Bit 1) */ + #define R_I3C0_HTSTFC_RDBFFC_Msk (0x2UL) /*!< RDBFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_HTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_HTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_HTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_HTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ /* ========================================================= BCST ========================================================== */ #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ @@ -19290,10 +20045,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ - #define R_I3C0_SVST_SVAFn_Msk (0x10000UL) /*!< SVAFn (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_SVAFn_Msk (0x70000UL) /*!< SVAFn (Bitfield-Mask: 0x07) */ /* ========================================================= WUST ========================================================== */ #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCCPT ========================================================= */ + #define R_I3C0_MRCCPT_MRCCPT_Pos (0UL) /*!< MRCCPT (Bit 0) */ + #define R_I3C0_MRCCPT_MRCCPT_Msk (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff) */ /* ======================================================== DATBAS0 ======================================================== */ #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ @@ -19362,6 +20120,74 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS4 ======================================================== */ + #define R_I3C0_DATBAS4_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS4_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS4_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS4_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS4_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS4_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS4_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS4_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS4_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS4_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS4_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS5 ======================================================== */ + #define R_I3C0_DATBAS5_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS5_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS5_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS5_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS5_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS5_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS5_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS5_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS5_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS5_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS5_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS6 ======================================================== */ + #define R_I3C0_DATBAS6_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS6_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS6_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS6_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS6_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS6_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS6_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS6_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS6_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS6_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS6_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS7 ======================================================== */ + #define R_I3C0_DATBAS7_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS7_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS7_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS7_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS7_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS7_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS7_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS7_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS7_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS7_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS7_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ /* ======================================================= EXDATBAS ======================================================== */ #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ @@ -19458,6 +20284,66 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT4 ========================================================= */ + #define R_I3C0_MSDCT4_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT4_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT4_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT4_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT4_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT4_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT4_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT4_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT5 ========================================================= */ + #define R_I3C0_MSDCT5_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT5_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT5_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT5_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT5_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT5_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT5_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT5_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT6 ========================================================= */ + #define R_I3C0_MSDCT6_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT6_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT6_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT6_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT6_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT6_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT6_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT6_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT7 ========================================================= */ + #define R_I3C0_MSDCT7_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT7_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT7_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT7_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT7_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT7_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT7_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT7_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ========================================================= SVDCT ========================================================= */ #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ @@ -19486,6 +20372,24 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD1 ======================================================== */ + #define R_I3C0_SVDVAD1_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD1_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD1_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD1_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD1_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD1_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD2 ======================================================== */ + #define R_I3C0_SVDVAD2_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD2_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD2_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD2_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD2_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD2_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ /* ======================================================== CSECMD ========================================================= */ #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ @@ -19530,10 +20434,23 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ /* ========================================================= CETSM ========================================================= */ + #define R_I3C0_CETSM_SPTSYN_Pos (0UL) /*!< SPTSYN (Bit 0) */ + #define R_I3C0_CETSM_SPTSYN_Msk (0x1UL) /*!< SPTSYN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN0_Pos (1UL) /*!< SPTASYN0 (Bit 1) */ + #define R_I3C0_CETSM_SPTASYN0_Msk (0x2UL) /*!< SPTASYN0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN1_Pos (2UL) /*!< SPTASYN1 (Bit 2) */ + #define R_I3C0_CETSM_SPTASYN1_Msk (0x4UL) /*!< SPTASYN1 (Bitfield-Mask: 0x01) */ #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ========================================================= CETSS ========================================================= */ + #define R_I3C0_CETSS_SYNE_Pos (0UL) /*!< SYNE (Bit 0) */ + #define R_I3C0_CETSS_SYNE_Msk (0x1UL) /*!< SYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSS_ASYNE_Pos (1UL) /*!< ASYNE (Bit 1) */ + #define R_I3C0_CETSS_ASYNE_Msk (0x6UL) /*!< ASYNE (Bitfield-Mask: 0x03) */ + #define R_I3C0_CETSS_ICOVF_Pos (7UL) /*!< ICOVF (Bit 7) */ + #define R_I3C0_CETSS_ICOVF_Msk (0x80UL) /*!< ICOVF (Bitfield-Mask: 0x01) */ /* ======================================================= CGHDRCAP ======================================================== */ #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ @@ -19563,6 +20480,16 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= NRSQSTLV ======================================================== */ #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HQSTLV ========================================================= */ + #define R_I3C0_HQSTLV_CMDQLV_Pos (0UL) /*!< CMDQLV (Bit 0) */ + #define R_I3C0_HQSTLV_CMDQLV_Msk (0xffUL) /*!< CMDQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_HQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HDBSTLV ======================================================== */ + #define R_I3C0_HDBSTLV_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_HDBSTLV_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HDBSTLV_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_HDBSTLV_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ /* ======================================================== PRSTDBG ======================================================== */ #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ @@ -19575,6 +20502,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= MSERRCNT ======================================================== */ #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ +/* ======================================================== SC1CPT ========================================================= */ + #define R_I3C0_SC1CPT_SC1C_Pos (0UL) /*!< SC1C (Bit 0) */ + #define R_I3C0_SC1CPT_SC1C_Msk (0xffffUL) /*!< SC1C (Bitfield-Mask: 0xffff) */ +/* ======================================================== SC2CPT ========================================================= */ + #define R_I3C0_SC2CPT_SC2C_Pos (0UL) /*!< SC2C (Bit 0) */ + #define R_I3C0_SC2CPT_SC2C_Msk (0xffffUL) /*!< SC2C (Bitfield-Mask: 0xffff) */ /* =========================================================================================================================== */ /* ================ R_MPU_MMPU ================ */ @@ -21449,14 +22382,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== UFRMNUM ======================================================== */ - #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ /* ======================================================== USBADDR ======================================================== */ #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ /* ======================================================== USBREQ ========================================================= */ @@ -21979,6 +22910,51 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ R_AGTX0 ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= EC710CTL ======================================================== */ + #define R_ECCMB0_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ + #define R_ECCMB0_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ + #define R_ECCMB0_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ + #define R_ECCMB0_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ + #define R_ECCMB0_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ + #define R_ECCMB0_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ + #define R_ECCMB0_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ + #define R_ECCMB0_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Pos (16UL) /*!< ECSEDF0 (Bit 16) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Msk (0x10000UL) /*!< ECSEDF0 (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Pos (17UL) /*!< ECDEDF0 (Bit 17) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Msk (0x20000UL) /*!< ECDEDF0 (Bitfield-Mask: 0x01) */ +/* ======================================================= EC710TMC ======================================================== */ + #define R_ECCMB0_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ + #define R_ECCMB0_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ + #define R_ECCMB0_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ +/* ======================================================= EC710TED ======================================================== */ + #define R_ECCMB0_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ + #define R_ECCMB0_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EC710EAD0 ======================================================= */ + #define R_ECCMB0_EC710EAD0_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ + #define R_ECCMB0_EC710EAD0_ECEAD_Msk (0x3ffUL) /*!< ECEAD (Bitfield-Mask: 0x3ff) */ + /* =========================================================================================================================== */ /* ================ R_FLAD ================ */ /* =========================================================================================================================== */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8D1BH.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8D1BH.h index 63341bb67..492b64d54 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8D1BH.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8D1BH.h @@ -3534,7 +3534,31 @@ typedef struct /*!< (@ 0x40236000) R_ACMPHS0 Structure __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ } CPIOC_b; }; -} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ + __IM uint8_t RESERVED4[47]; + + union + { + __IOM uint8_t CPINTCTL; /*!< (@ 0x00000040) Comparator Interrupt Control Register */ + + struct + { + __IOM uint8_t MSKE : 1; /*!< [0..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 7; + } CPINTCTL_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t CPMSKCTL; /*!< (@ 0x00000044) Comparator Interrupt Mask Control Register */ + + struct + { + __IOM uint8_t MSKSEL : 3; /*!< [2..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 5; + } CPMSKCTL_b; + }; +} R_ACMPHS0_Type; /*!< Size = 69 (0x45) */ /* =========================================================================================================================== */ /* ================ R_ADC0 ================ */ @@ -3797,7 +3821,7 @@ typedef struct /*!< (@ 0x40332000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -3810,7 +3834,7 @@ typedef struct /*!< (@ 0x40332000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -5869,8 +5893,8 @@ typedef struct /*!< (@ 0x40380000) R_CANFD0 Structure struct { - __IM uint32_t RFXIF : 1; /*!< [0..0] RX FIFO[x] Interrupt Flag Status */ - uint32_t : 31; + __IM uint32_t RFXIF : 2; /*!< [1..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 30; } CFDRFISTS_b; }; @@ -6562,8 +6586,8 @@ typedef struct /*!< (@ 0x4000A800) R_DMA Structure struct { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ uint32_t : 7; __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ @@ -9578,7 +9602,8 @@ typedef struct /*!< (@ 0x40322000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -9625,7 +9650,8 @@ typedef struct /*!< (@ 0x40322000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -9636,7 +9662,10 @@ typedef struct /*!< (@ 0x40322000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -9653,24 +9682,26 @@ typedef struct /*!< (@ 0x40322000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -9714,12 +9745,24 @@ typedef struct /*!< (@ 0x40322000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -10196,7 +10239,57 @@ typedef struct /*!< (@ 0x40322000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -11176,20 +11269,25 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure union { - __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ struct { - __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ - __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ - __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ - __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ - __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ - __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ - __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ - uint32_t : 9; - __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ - uint32_t : 15; + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 2; + __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset */ + __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese */ + __IOM uint32_t HTDBRST : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset */ + __IOM uint32_t HRDBRST : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset */ + uint32_t : 3; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; } RSTCTL_b; }; @@ -11319,8 +11417,8 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ uint32_t : 8; __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ - __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */ - uint32_t : 15; + __IOM uint32_t SVAEn : 3; /*!< [18..16] Slave Address Enable */ + uint32_t : 13; } SVCTL_b; }; __IM uint32_t RESERVED6[2]; @@ -11362,7 +11460,7 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ uint32_t : 2; - __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */ + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull */ uint32_t : 2; } EXTBR_b; }; @@ -11516,7 +11614,57 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ } SVTDLG0_b; }; - __IM uint32_t RESERVED11[31]; + __IM uint32_t RESERVED11[23]; + + union + { + __IOM uint32_t STCTL; /*!< (@ 0x00000120) Synchronous Timing Control Register */ + + struct + { + __IOM uint32_t STOE : 1; /*!< [0..0] Synchronous Timing output Enable */ + uint32_t : 31; + } STCTL_b; + }; + + union + { + __IOM uint32_t ATCTL; /*!< (@ 0x00000124) Asynchronous Timing Control Register */ + + struct + { + __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select */ + __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow) */ + __IOM uint32_t AMEOE : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable */ + uint32_t : 5; + __IOM uint32_t CDIV : 8; /*!< [15..8] TCLK Counter Divide Setting */ + uint32_t : 16; + } ATCTL_b; + }; + + union + { + __IOM uint32_t ATTRG; /*!< (@ 0x00000128) Asynchronous Timing Trigger Register */ + + struct + { + __OM uint32_t ATSTRG : 1; /*!< [0..0] Asynchronous Timing Software Trigger */ + uint32_t : 31; + } ATTRG_b; + }; + + union + { + __IOM uint32_t ATCCNTE; /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register */ + + struct + { + __IOM uint32_t ATCE : 1; /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1, + * SC2. */ + uint32_t : 31; + } ATCCNTE_b; + }; + __IM uint32_t RESERVED12[4]; union { @@ -11530,14 +11678,43 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 29; } CNDCTL_b; }; - __IM uint32_t RESERVED12[3]; + __IM uint32_t RESERVED13[3]; __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ - __IM uint32_t RESERVED13[8]; + __IM uint32_t RESERVED14[8]; __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ - __IM uint32_t RESERVED14[3]; + + union + { + __OM uint32_t HCMDQP; /*!< (@ 0x00000184) High Priority Command Queue Port Register */ + + struct + { + __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port */ + } HCMDQP_b; + }; + + union + { + __IM uint32_t HRSPQP; /*!< (@ 0x00000188) High Priority Response Queue Port Register */ + + struct + { + __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port */ + } HRSPQP_b; + }; + + union + { + __IOM uint32_t HTDTBP; /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register */ + + struct + { + __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port */ + } HTDTBP_b; + }; union { @@ -11582,7 +11759,37 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 24; } NRQTHCTL_b; }; - __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t HQTHCTL; /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold */ + uint32_t : 16; + } HQTHCTL_b; + }; + + union + { + __IOM uint32_t HTBTHCTL; /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold + * Control Register */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold */ + uint32_t : 5; + } HTBTHCTL_b; + }; + __IM uint32_t RESERVED16; union { @@ -11755,7 +11962,79 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 11; } NTSTFC_b; }; - __IM uint32_t RESERVED17[8]; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint32_t HTST; /*!< (@ 0x00000200) High Priority Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag */ + __IOM uint32_t RDBFF : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag */ + uint32_t : 1; + __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] High Priority Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] High Priority Transfer Error Flag */ + uint32_t : 22; + } HTST_b; + }; + + union + { + __IOM uint32_t HTSTE; /*!< (@ 0x00000204) High Priority Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable */ + __IOM uint32_t RDBFE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] High Priority Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] High Priority Transfer Error Enable */ + uint32_t : 22; + } HTSTE_b; + }; + + union + { + __IOM uint32_t HTIE; /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable */ + __IOM uint32_t RDBFIE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable */ + uint32_t : 22; + } HTIE_b; + }; + + union + { + __IOM uint32_t HTSTFC; /*!< (@ 0x0000020C) High Priority Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force */ + __OM uint32_t RDBFFC : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force */ + uint32_t : 1; + __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] High Priority Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] High Priority Transfer Error Force */ + uint32_t : 22; + } HTSTFC_b; + }; union { @@ -11782,22 +12061,32 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ uint32_t : 8; __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ - __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */ - uint32_t : 15; + __IOM uint32_t SVAFn : 3; /*!< [18..16] Slave Address Detection Flag */ + uint32_t : 13; } SVST_b; }; union { - __IOM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Control Register */ + __IM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Operating Status Register */ struct { - __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ - uint32_t : 31; + __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; } WUST_b; }; - __IM uint32_t RESERVED18[2]; + + union + { + __IM uint32_t MRCCPT; /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register */ + + struct + { + __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture */ + } MRCCPT_b; + }; + __IM uint32_t RESERVED18; union { @@ -11877,7 +12166,87 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ } DATBAS3_b; }; - __IM uint32_t RESERVED22[24]; + __IM uint32_t RESERVED22; + + union + { + __IOM uint32_t DATBAS4; /*!< (@ 0x00000244) Device Address Table Basic Register 4 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS4_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IOM uint32_t DATBAS5; /*!< (@ 0x0000024C) Device Address Table Basic Register 5 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS5_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t DATBAS6; /*!< (@ 0x00000254) Device Address Table Basic Register 6 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS6_b; + }; + __IM uint32_t RESERVED25; + + union + { + __IOM uint32_t DATBAS7; /*!< (@ 0x0000025C) Device Address Table Basic Register 7 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS7_b; + }; + __IM uint32_t RESERVED26[16]; union { @@ -11893,7 +12262,7 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ } EXDATBAS_b; }; - __IM uint32_t RESERVED23[3]; + __IM uint32_t RESERVED27[3]; union { @@ -11942,7 +12311,7 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 9; } SDATBAS2_b; }; - __IM uint32_t RESERVED24[5]; + __IM uint32_t RESERVED28[5]; union { @@ -12015,7 +12384,79 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 16; } MSDCT3_b; }; - __IM uint32_t RESERVED25[16]; + + union + { + __IOM uint32_t MSDCT4; /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT4_b; + }; + + union + { + __IOM uint32_t MSDCT5; /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT5_b; + }; + + union + { + __IOM uint32_t MSDCT6; /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT6_b; + }; + + union + { + __IOM uint32_t MSDCT7; /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT7_b; + }; + __IM uint32_t RESERVED29[12]; union { @@ -12038,7 +12479,7 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure * ID Low Register */ __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional * ID High Register */ - __IM uint32_t RESERVED26; + __IM uint32_t RESERVED30; union { @@ -12055,7 +12496,39 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ } SVDVAD0_b; }; - __IM uint32_t RESERVED27[7]; + + union + { + __IM uint32_t SVDVAD1; /*!< (@ 0x00000334) Slave Device Address Register 1 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD1_b; + }; + + union + { + __IM uint32_t SVDVAD2; /*!< (@ 0x00000338) Slave Device Address Register 2 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD2_b; + }; + __IM uint32_t RESERVED31[5]; union { @@ -12168,18 +12641,35 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure union { - __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) - * Register */ + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ struct { - uint32_t : 8; - __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ - __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ - uint32_t : 8; + __IOM uint32_t SPTSYN : 1; /*!< [0..0] Supports Sync Mode */ + __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0 */ + __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1 */ + uint32_t : 5; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; } CETSM_b; }; - __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t CETSS; /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State) + * Register */ + + struct + { + __IOM uint32_t SYNE : 1; /*!< [0..0] Sync Mode Enabled */ + __IOM uint32_t ASYNE : 2; /*!< [2..1] Async Mode Enabled */ + uint32_t : 4; + __IOM uint32_t ICOVF : 1; /*!< [7..7] Internal Counter Overflow */ + uint32_t : 24; + } CETSS_b; + }; union { @@ -12206,7 +12696,7 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 24; } BITCNT_b; }; - __IM uint32_t RESERVED29[4]; + __IM uint32_t RESERVED32[4]; union { @@ -12224,7 +12714,7 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure union { - __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */ + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0 */ struct { @@ -12233,7 +12723,7 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 16; } NDBSTLV0_b; }; - __IM uint32_t RESERVED30[9]; + __IM uint32_t RESERVED33[9]; union { @@ -12245,7 +12735,30 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 24; } NRSQSTLV_b; }; - __IM uint32_t RESERVED31[2]; + + union + { + __IM uint32_t HQSTLV; /*!< (@ 0x000003C4) High Priority Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQLV : 8; /*!< [7..0] High Priority Command Queue Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] High Priority Response Queue Level */ + uint32_t : 16; + } HQSTLV_b; + }; + + union + { + __IM uint32_t HDBSTLV; /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] High Priority Tx Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] High Priority Rx Data Buffer Level */ + uint32_t : 16; + } HDBSTLV_b; + }; union { @@ -12271,7 +12784,30 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 24; } MSERRCNT_b; }; -} R_I3C0_Type; /*!< Size = 980 (0x3d4) */ + __IM uint32_t RESERVED34[3]; + + union + { + __IM uint32_t SC1CPT; /*!< (@ 0x000003E0) SC1 Capture monitor Register */ + + struct + { + __IM uint32_t SC1C : 16; /*!< [15..0] SC1 Capture */ + uint32_t : 16; + } SC1CPT_b; + }; + + union + { + __IM uint32_t SC2CPT; /*!< (@ 0x000003E4) SC2 Capture monitor Register */ + + struct + { + __IM uint32_t SC2C : 16; /*!< [15..0] SC2 Capture */ + uint32_t : 16; + } SC2CPT_b; + }; +} R_I3C0_Type; /*!< Size = 1000 (0x3e8) */ /* =========================================================================================================================== */ /* ================ R_MPU_MMPU ================ */ @@ -18943,7 +19479,7 @@ typedef struct /*!< (@ 0x40250000) R_USB_FS0 Structure * data. */ uint16_t : 1; __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ } CFIFOCTR_b; }; @@ -18963,7 +19499,7 @@ typedef struct /*!< (@ 0x40250000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D0FIFOSEL_b; }; @@ -18997,7 +19533,7 @@ typedef struct /*!< (@ 0x40250000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D1FIFOSEL_b; }; @@ -19272,14 +19808,13 @@ typedef struct /*!< (@ 0x40250000) R_USB_FS0 Structure union { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ struct { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; + uint16_t : 15; __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; + } DVCHGR_b; }; union @@ -19292,8 +19827,8 @@ typedef struct /*!< (@ 0x40250000) R_USB_FS0 Structure * the USB address assigned by the host when the USBHS processed * the SET_ADDRESS request successfully. */ uint16_t : 1; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; } USBADDR_b; }; __IM uint16_t RESERVED9; @@ -30054,6 +30589,81 @@ typedef struct /*!< (@ 0x40346000) R_DSILINK Structure }; } R_DSILINK_Type; /*!< Size = 2176 (0x880) */ +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CANFD ECC (R_ECCMB0) + */ + +typedef struct /*!< (@ 0x4036F200) R_ECCMB0 Structure */ +{ + union + { + __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ + + struct + { + __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Message Flag */ + __IM uint32_t ECER1F : 1; /*!< [1..1] ECC Error Detection and Correction Flag */ + __IM uint32_t ECER2F : 1; /*!< [2..2] 2-bit ECC Error Detection Flag */ + __IOM uint32_t EC1EDIC : 1; /*!< [3..3] ECC 1-bit Error Detection Interrupt Control */ + __IOM uint32_t EC2EDIC : 1; /*!< [4..4] ECC 2-bit Error Detection Interrupt Control */ + __IOM uint32_t EC1ECP : 1; /*!< [5..5] ECC 1-bit Error Correction Permission */ + __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Judgment Enable Flag */ + uint32_t : 2; + __IOM uint32_t ECER1C : 1; /*!< [9..9] Accumulating ECC Error Detection and Correction Flag + * Clear */ + __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-bit ECC Error Detection Flag Clear */ + __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Overflow Detection Flag */ + uint32_t : 2; + __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Select bit */ + __IM uint32_t ECSEDF0 : 1; /*!< [16..16] ECC Single bit Error Address Detection Flag */ + __IM uint32_t ECDEDF0 : 1; /*!< [17..17] ECC Dual Bit Error Address Detection Flag */ + uint32_t : 14; + } EC710CTL_b; + }; + + union + { + __IOM uint16_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ + uint16_t : 5; + __IOM uint16_t ECTMCE : 1; /*!< [7..7] ECC Test Mode Control Enable */ + uint16_t : 6; + __IOM uint16_t ETMA : 2; /*!< [15..14] ECC Test Mode Bit Access Control */ + } EC710TMC_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Test Substitute Data Register */ + + struct + { + __IOM uint32_t ECEDB : 32; /*!< [31..0] ECC Test Substitute Data */ + } EC710TED_b; + }; + + union + { + __IM uint32_t EC710EAD0; /*!< (@ 0x00000010) ECC Error Address Register */ + + struct + { + __IM uint32_t ECEAD : 10; /*!< [9..0] ECC Error Address */ + uint32_t : 22; + } EC710EAD0_b; + }; +} R_ECCMB0_Type; /*!< Size = 20 (0x14) */ + /* =========================================================================================================================== */ /* ================ R_FLAD ================ */ /* =========================================================================================================================== */ @@ -30222,7 +30832,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_CANFD1_BASE (0x40382000UL + BASE_NS_OFFSET) #define R_CRC_BASE (0x40310000UL + BASE_NS_OFFSET) #define R_DAC_BASE (0x40333000UL + BASE_NS_OFFSET) - #define R_DAC1_BASE (0x40333100UL + BASE_NS_OFFSET) #define R_DEBUG_BASE (0x4001B000UL + BASE_NS_OFFSET) #define R_DMA_BASE (0x4000A800UL + BASE_NS_OFFSET) #define R_DMAC0_BASE (0x4000A000UL + BASE_NS_OFFSET) @@ -30340,14 +30949,19 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_AGTX7_BASE (0x40221700UL + BASE_NS_OFFSET) #define R_AGTX8_BASE (0x40221800UL + BASE_NS_OFFSET) #define R_AGTX9_BASE (0x40221900UL + BASE_NS_OFFSET) + #define R_DOTF1_BASE (0x40268900UL + BASE_NS_OFFSET) #define R_DPHYCNT_BASE (0x40346C00UL + BASE_NS_OFFSET) #define R_DSILINK_BASE (0x40346000UL + BASE_NS_OFFSET) + #define R_ECCMB0_BASE (0x4036F200UL + BASE_NS_OFFSET) + #define R_ECCMB1_BASE (0x4036F300UL + BASE_NS_OFFSET) #define R_FLAD_BASE (0x4011C000UL + BASE_NS_OFFSET) #define R_OFS_DATAFLASH_BASE (0x27030000UL + BASE_NS_OFFSET) #define R_SCI_B5_BASE (0x40358500UL + BASE_NS_OFFSET) #define R_SCI_B6_BASE (0x40358600UL + BASE_NS_OFFSET) #define R_SCI_B7_BASE (0x40358700UL + BASE_NS_OFFSET) #define R_SCI_B8_BASE (0x40358800UL + BASE_NS_OFFSET) + #define R_WDT1_BASE (0x40044300UL + BASE_NS_OFFSET) + #define R_XSPI1_BASE (0x40268400UL + BASE_NS_OFFSET) /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -30375,7 +30989,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_CANFD1 ((R_CANFD_Type *) R_CANFD1_BASE) #define R_CRC ((R_CRC_Type *) R_CRC_BASE) #define R_DAC ((R_DAC_Type *) R_DAC_BASE) - #define R_DAC1 ((R_DAC_Type *) R_DAC1_BASE) #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) #define R_DMA ((R_DMA_Type *) R_DMA_BASE) #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) @@ -30493,14 +31106,19 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_DOTF1 ((R_DOTF_Type *) R_DOTF1_BASE) #define R_DPHYCNT ((R_DPHYCNT_Type *) R_DPHYCNT_BASE) #define R_DSILINK ((R_DSILINK_Type *) R_DSILINK_BASE) + #define R_ECCMB0 ((R_ECCMB0_Type *) R_ECCMB0_BASE) + #define R_ECCMB1 ((R_ECCMB0_Type *) R_ECCMB1_BASE) #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) #define R_OFS_DATAFLASH ((R_OFS_DATAFLASH_Type *) R_OFS_DATAFLASH_BASE) #define R_SCI_B5 ((R_SCI_B0_Type *) R_SCI_B5_BASE) #define R_SCI_B6 ((R_SCI_B0_Type *) R_SCI_B6_BASE) #define R_SCI_B7 ((R_SCI_B0_Type *) R_SCI_B7_BASE) #define R_SCI_B8 ((R_SCI_B0_Type *) R_SCI_B8_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) + #define R_XSPI1 ((R_XSPI_Type *) R_XSPI1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -32028,32 +32646,38 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* =========================================================================================================================== */ /* ======================================================== CMPCTL ========================================================= */ - #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ - #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ - #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ - #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ - #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ - #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ - #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ - #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ - #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ /* ======================================================== CMPSEL0 ======================================================== */ - #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ - #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ /* ======================================================== CMPSEL1 ======================================================== */ - #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ - #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ /* ======================================================== CMPMON ========================================================= */ - #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ - #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ /* ========================================================= CPIOC ========================================================= */ - #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ - #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ - #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPINTCTL ======================================================== */ + #define R_ACMPHS0_CPINTCTL_MSKE_Pos (0UL) /*!< MSKE (Bit 0) */ + #define R_ACMPHS0_CPINTCTL_MSKE_Msk (0x1UL) /*!< MSKE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPMSKCTL ======================================================== */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Pos (0UL) /*!< MSKSEL (Bit 0) */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Msk (0x7UL) /*!< MSKSEL (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_ADC0 ================ */ @@ -32835,7 +33459,7 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x100UL) /*!< CFXMLT (Bitfield-Mask: 0x01) */ /* ======================================================= CFDRFISTS ======================================================= */ #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ - #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x1UL) /*!< RFXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x3UL) /*!< RFXIF (Bitfield-Mask: 0x03) */ /* ======================================================== CFDTMC ========================================================= */ #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ @@ -33081,9 +33705,14 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ========================================================= DMAST ========================================================= */ #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* ======================================================== DMECHR ========================================================= */ #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ @@ -33093,11 +33722,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -34269,6 +34893,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -34292,6 +34918,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -34331,9 +34959,15 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -34408,7 +35042,13 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -34445,8 +35085,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -34632,6 +35270,24 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ @@ -35268,6 +35924,14 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HCMDQRST_Pos (9UL) /*!< HCMDQRST (Bit 9) */ + #define R_I3C0_RSTCTL_HCMDQRST_Msk (0x200UL) /*!< HCMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRSPQRST_Pos (10UL) /*!< HRSPQRST (Bit 10) */ + #define R_I3C0_RSTCTL_HRSPQRST_Msk (0x400UL) /*!< HRSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HTDBRST_Pos (11UL) /*!< HTDBRST (Bit 11) */ + #define R_I3C0_RSTCTL_HTDBRST_Msk (0x800UL) /*!< HTDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRDBRST_Pos (12UL) /*!< HRDBRST (Bit 12) */ + #define R_I3C0_RSTCTL_HRDBRST_Msk (0x1000UL) /*!< HRDBRST (Bitfield-Mask: 0x01) */ #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ /* ========================================================= PRSST ========================================================= */ @@ -35324,7 +35988,7 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ - #define R_I3C0_SVCTL_SVAEn_Msk (0x10000UL) /*!< SVAEn (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_SVAEn_Msk (0x70000UL) /*!< SVAEn (Bitfield-Mask: 0x07) */ /* ======================================================= REFCKCTL ======================================================== */ #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ @@ -35419,6 +36083,24 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================== SVTDLG0 ======================================================== */ #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= STCTL ========================================================= */ + #define R_I3C0_STCTL_STOE_Pos (0UL) /*!< STOE (Bit 0) */ + #define R_I3C0_STCTL_STOE_Msk (0x1UL) /*!< STOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ATCTL ========================================================= */ + #define R_I3C0_ATCTL_ATTRGS_Pos (0UL) /*!< ATTRGS (Bit 0) */ + #define R_I3C0_ATCTL_ATTRGS_Msk (0x1UL) /*!< ATTRGS (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_MREFOE_Pos (1UL) /*!< MREFOE (Bit 1) */ + #define R_I3C0_ATCTL_MREFOE_Msk (0x2UL) /*!< MREFOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_AMEOE_Pos (2UL) /*!< AMEOE (Bit 2) */ + #define R_I3C0_ATCTL_AMEOE_Msk (0x4UL) /*!< AMEOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_CDIV_Pos (8UL) /*!< CDIV (Bit 8) */ + #define R_I3C0_ATCTL_CDIV_Msk (0xff00UL) /*!< CDIV (Bitfield-Mask: 0xff) */ +/* ========================================================= ATTRG ========================================================= */ + #define R_I3C0_ATTRG_ATSTRG_Pos (0UL) /*!< ATSTRG (Bit 0) */ + #define R_I3C0_ATTRG_ATSTRG_Msk (0x1UL) /*!< ATSTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== ATCCNTE ======================================================== */ + #define R_I3C0_ATCCNTE_ATCE_Pos (0UL) /*!< ATCE (Bit 0) */ + #define R_I3C0_ATCCNTE_ATCE_Msk (0x1UL) /*!< ATCE (Bitfield-Mask: 0x01) */ /* ======================================================== CNDCTL ========================================================= */ #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ @@ -35431,6 +36113,15 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================== NTDTBP0 ======================================================== */ /* ======================================================== NIBIQP ========================================================= */ /* ========================================================= NRSQP ========================================================= */ +/* ======================================================== HCMDQP ========================================================= */ + #define R_I3C0_HCMDQP_HCMDQP_Pos (0UL) /*!< HCMDQP (Bit 0) */ + #define R_I3C0_HCMDQP_HCMDQP_Msk (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HRSPQP ========================================================= */ + #define R_I3C0_HRSPQP_HRSPQP_Pos (0UL) /*!< HRSPQP (Bit 0) */ + #define R_I3C0_HRSPQP_HRSPQP_Msk (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HTDTBP ========================================================= */ + #define R_I3C0_HTDTBP_HTDTBP_Pos (0UL) /*!< HTDTBP (Bit 0) */ + #define R_I3C0_HTDTBP_HTDTBP_Msk (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff) */ /* ======================================================== NQTHCTL ======================================================== */ #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ @@ -35452,6 +36143,20 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================= NRQTHCTL ======================================================== */ #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ +/* ======================================================== HQTHCTL ======================================================== */ + #define R_I3C0_HQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_HQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_HQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= HTBTHCTL ======================================================== */ + #define R_I3C0_HTBTHCTL_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_HTBTHCTL_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ /* ========================================================== BST ========================================================== */ #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ @@ -35588,6 +36293,58 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ +/* ========================================================= HTST ========================================================== */ + #define R_I3C0_HTST_TDBEF_Pos (0UL) /*!< TDBEF (Bit 0) */ + #define R_I3C0_HTST_TDBEF_Msk (0x1UL) /*!< TDBEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RDBFF_Pos (1UL) /*!< RDBFF (Bit 1) */ + #define R_I3C0_HTST_RDBFF_Msk (0x2UL) /*!< RDBFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_HTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_HTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_HTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_HTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ +/* ========================================================= HTSTE ========================================================= */ + #define R_I3C0_HTSTE_TDBEE_Pos (0UL) /*!< TDBEE (Bit 0) */ + #define R_I3C0_HTSTE_TDBEE_Msk (0x1UL) /*!< TDBEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RDBFE_Pos (1UL) /*!< RDBFE (Bit 1) */ + #define R_I3C0_HTSTE_RDBFE_Msk (0x2UL) /*!< RDBFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_HTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_HTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_HTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_HTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ +/* ========================================================= HTIE ========================================================== */ + #define R_I3C0_HTIE_TDBEIE_Pos (0UL) /*!< TDBEIE (Bit 0) */ + #define R_I3C0_HTIE_TDBEIE_Msk (0x1UL) /*!< TDBEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RDBFIE_Pos (1UL) /*!< RDBFIE (Bit 1) */ + #define R_I3C0_HTIE_RDBFIE_Msk (0x2UL) /*!< RDBFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_HTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_HTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_HTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_HTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== HTSTFC ========================================================= */ + #define R_I3C0_HTSTFC_TDBEFC_Pos (0UL) /*!< TDBEFC (Bit 0) */ + #define R_I3C0_HTSTFC_TDBEFC_Msk (0x1UL) /*!< TDBEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RDBFFC_Pos (1UL) /*!< RDBFFC (Bit 1) */ + #define R_I3C0_HTSTFC_RDBFFC_Msk (0x2UL) /*!< RDBFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_HTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_HTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_HTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_HTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ /* ========================================================= BCST ========================================================== */ #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ @@ -35605,10 +36362,13 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ - #define R_I3C0_SVST_SVAFn_Msk (0x10000UL) /*!< SVAFn (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_SVAFn_Msk (0x70000UL) /*!< SVAFn (Bitfield-Mask: 0x07) */ /* ========================================================= WUST ========================================================== */ #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCCPT ========================================================= */ + #define R_I3C0_MRCCPT_MRCCPT_Pos (0UL) /*!< MRCCPT (Bit 0) */ + #define R_I3C0_MRCCPT_MRCCPT_Msk (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff) */ /* ======================================================== DATBAS0 ======================================================== */ #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ @@ -35677,6 +36437,74 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS4 ======================================================== */ + #define R_I3C0_DATBAS4_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS4_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS4_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS4_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS4_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS4_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS4_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS4_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS4_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS4_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS4_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS5 ======================================================== */ + #define R_I3C0_DATBAS5_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS5_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS5_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS5_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS5_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS5_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS5_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS5_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS5_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS5_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS5_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS6 ======================================================== */ + #define R_I3C0_DATBAS6_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS6_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS6_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS6_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS6_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS6_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS6_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS6_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS6_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS6_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS6_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS7 ======================================================== */ + #define R_I3C0_DATBAS7_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS7_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS7_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS7_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS7_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS7_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS7_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS7_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS7_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS7_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS7_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ /* ======================================================= EXDATBAS ======================================================== */ #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ @@ -35773,6 +36601,66 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT4 ========================================================= */ + #define R_I3C0_MSDCT4_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT4_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT4_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT4_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT4_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT4_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT4_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT4_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT5 ========================================================= */ + #define R_I3C0_MSDCT5_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT5_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT5_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT5_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT5_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT5_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT5_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT5_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT6 ========================================================= */ + #define R_I3C0_MSDCT6_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT6_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT6_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT6_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT6_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT6_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT6_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT6_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT7 ========================================================= */ + #define R_I3C0_MSDCT7_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT7_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT7_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT7_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT7_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT7_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT7_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT7_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ========================================================= SVDCT ========================================================= */ #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ @@ -35801,6 +36689,24 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD1 ======================================================== */ + #define R_I3C0_SVDVAD1_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD1_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD1_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD1_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD1_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD1_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD2 ======================================================== */ + #define R_I3C0_SVDVAD2_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD2_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD2_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD2_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD2_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD2_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ /* ======================================================== CSECMD ========================================================= */ #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ @@ -35845,10 +36751,23 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ /* ========================================================= CETSM ========================================================= */ + #define R_I3C0_CETSM_SPTSYN_Pos (0UL) /*!< SPTSYN (Bit 0) */ + #define R_I3C0_CETSM_SPTSYN_Msk (0x1UL) /*!< SPTSYN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN0_Pos (1UL) /*!< SPTASYN0 (Bit 1) */ + #define R_I3C0_CETSM_SPTASYN0_Msk (0x2UL) /*!< SPTASYN0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN1_Pos (2UL) /*!< SPTASYN1 (Bit 2) */ + #define R_I3C0_CETSM_SPTASYN1_Msk (0x4UL) /*!< SPTASYN1 (Bitfield-Mask: 0x01) */ #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ========================================================= CETSS ========================================================= */ + #define R_I3C0_CETSS_SYNE_Pos (0UL) /*!< SYNE (Bit 0) */ + #define R_I3C0_CETSS_SYNE_Msk (0x1UL) /*!< SYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSS_ASYNE_Pos (1UL) /*!< ASYNE (Bit 1) */ + #define R_I3C0_CETSS_ASYNE_Msk (0x6UL) /*!< ASYNE (Bitfield-Mask: 0x03) */ + #define R_I3C0_CETSS_ICOVF_Pos (7UL) /*!< ICOVF (Bit 7) */ + #define R_I3C0_CETSS_ICOVF_Msk (0x80UL) /*!< ICOVF (Bitfield-Mask: 0x01) */ /* ======================================================= CGHDRCAP ======================================================== */ #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ @@ -35878,6 +36797,16 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================= NRSQSTLV ======================================================== */ #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HQSTLV ========================================================= */ + #define R_I3C0_HQSTLV_CMDQLV_Pos (0UL) /*!< CMDQLV (Bit 0) */ + #define R_I3C0_HQSTLV_CMDQLV_Msk (0xffUL) /*!< CMDQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_HQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HDBSTLV ======================================================== */ + #define R_I3C0_HDBSTLV_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_HDBSTLV_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HDBSTLV_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_HDBSTLV_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ /* ======================================================== PRSTDBG ======================================================== */ #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ @@ -35890,6 +36819,12 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================= MSERRCNT ======================================================== */ #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ +/* ======================================================== SC1CPT ========================================================= */ + #define R_I3C0_SC1CPT_SC1C_Pos (0UL) /*!< SC1C (Bit 0) */ + #define R_I3C0_SC1CPT_SC1C_Msk (0xffffUL) /*!< SC1C (Bitfield-Mask: 0xffff) */ +/* ======================================================== SC2CPT ========================================================= */ + #define R_I3C0_SC2CPT_SC2C_Pos (0UL) /*!< SC2C (Bit 0) */ + #define R_I3C0_SC2CPT_SC2C_Msk (0xffffUL) /*!< SC2C (Bitfield-Mask: 0xffff) */ /* =========================================================================================================================== */ /* ================ R_MPU_MMPU ================ */ @@ -38786,14 +39721,12 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== UFRMNUM ======================================================== */ - #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ /* ======================================================== USBADDR ======================================================== */ #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ /* ======================================================== USBREQ ========================================================= */ @@ -43911,6 +44844,51 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_DSILINK_SQCH1DSC7DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ #define R_DSILINK_SQCH1DSC7DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= EC710CTL ======================================================== */ + #define R_ECCMB0_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ + #define R_ECCMB0_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ + #define R_ECCMB0_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ + #define R_ECCMB0_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ + #define R_ECCMB0_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ + #define R_ECCMB0_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ + #define R_ECCMB0_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ + #define R_ECCMB0_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Pos (16UL) /*!< ECSEDF0 (Bit 16) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Msk (0x10000UL) /*!< ECSEDF0 (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Pos (17UL) /*!< ECDEDF0 (Bit 17) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Msk (0x20000UL) /*!< ECDEDF0 (Bitfield-Mask: 0x01) */ +/* ======================================================= EC710TMC ======================================================== */ + #define R_ECCMB0_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ + #define R_ECCMB0_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ + #define R_ECCMB0_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ +/* ======================================================= EC710TED ======================================================== */ + #define R_ECCMB0_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ + #define R_ECCMB0_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EC710EAD0 ======================================================= */ + #define R_ECCMB0_EC710EAD0_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ + #define R_ECCMB0_EC710EAD0_ECEAD_Msk (0x3ffUL) /*!< ECEAD (Bitfield-Mask: 0x3ff) */ + /* =========================================================================================================================== */ /* ================ R_FLAD ================ */ /* =========================================================================================================================== */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8M1AH.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8M1AH.h index b03b96cd8..4553a5589 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8M1AH.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8M1AH.h @@ -2708,7 +2708,31 @@ typedef struct /*!< (@ 0x40236000) R_ACMPHS0 Structure __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ } CPIOC_b; }; -} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ + __IM uint8_t RESERVED4[47]; + + union + { + __IOM uint8_t CPINTCTL; /*!< (@ 0x00000040) Comparator Interrupt Control Register */ + + struct + { + __IOM uint8_t MSKE : 1; /*!< [0..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 7; + } CPINTCTL_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t CPMSKCTL; /*!< (@ 0x00000044) Comparator Interrupt Mask Control Register */ + + struct + { + __IOM uint8_t MSKSEL : 3; /*!< [2..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 5; + } CPMSKCTL_b; + }; +} R_ACMPHS0_Type; /*!< Size = 69 (0x45) */ /* =========================================================================================================================== */ /* ================ R_ADC0 ================ */ @@ -2971,7 +2995,7 @@ typedef struct /*!< (@ 0x40332000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -2984,7 +3008,7 @@ typedef struct /*!< (@ 0x40332000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -5043,8 +5067,8 @@ typedef struct /*!< (@ 0x40380000) R_CANFD0 Structure struct { - __IM uint32_t RFXIF : 1; /*!< [0..0] RX FIFO[x] Interrupt Flag Status */ - uint32_t : 31; + __IM uint32_t RFXIF : 2; /*!< [1..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 30; } CFDRFISTS_b; }; @@ -5736,8 +5760,8 @@ typedef struct /*!< (@ 0x4000A800) R_DMA Structure struct { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ uint32_t : 7; __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ @@ -7976,7 +8000,8 @@ typedef struct /*!< (@ 0x40322000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -8023,7 +8048,8 @@ typedef struct /*!< (@ 0x40322000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -8034,7 +8060,10 @@ typedef struct /*!< (@ 0x40322000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -8051,24 +8080,26 @@ typedef struct /*!< (@ 0x40322000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -8112,12 +8143,24 @@ typedef struct /*!< (@ 0x40322000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -8594,7 +8637,57 @@ typedef struct /*!< (@ 0x40322000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -9574,20 +9667,25 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure union { - __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ struct { - __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ - __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ - __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ - __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ - __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ - __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ - __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ - uint32_t : 9; - __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ - uint32_t : 15; + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 2; + __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset */ + __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese */ + __IOM uint32_t HTDBRST : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset */ + __IOM uint32_t HRDBRST : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset */ + uint32_t : 3; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; } RSTCTL_b; }; @@ -9717,8 +9815,8 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ uint32_t : 8; __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ - __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */ - uint32_t : 15; + __IOM uint32_t SVAEn : 3; /*!< [18..16] Slave Address Enable */ + uint32_t : 13; } SVCTL_b; }; __IM uint32_t RESERVED6[2]; @@ -9760,7 +9858,7 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ uint32_t : 2; - __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */ + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull */ uint32_t : 2; } EXTBR_b; }; @@ -9914,7 +10012,57 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ } SVTDLG0_b; }; - __IM uint32_t RESERVED11[31]; + __IM uint32_t RESERVED11[23]; + + union + { + __IOM uint32_t STCTL; /*!< (@ 0x00000120) Synchronous Timing Control Register */ + + struct + { + __IOM uint32_t STOE : 1; /*!< [0..0] Synchronous Timing output Enable */ + uint32_t : 31; + } STCTL_b; + }; + + union + { + __IOM uint32_t ATCTL; /*!< (@ 0x00000124) Asynchronous Timing Control Register */ + + struct + { + __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select */ + __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow) */ + __IOM uint32_t AMEOE : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable */ + uint32_t : 5; + __IOM uint32_t CDIV : 8; /*!< [15..8] TCLK Counter Divide Setting */ + uint32_t : 16; + } ATCTL_b; + }; + + union + { + __IOM uint32_t ATTRG; /*!< (@ 0x00000128) Asynchronous Timing Trigger Register */ + + struct + { + __OM uint32_t ATSTRG : 1; /*!< [0..0] Asynchronous Timing Software Trigger */ + uint32_t : 31; + } ATTRG_b; + }; + + union + { + __IOM uint32_t ATCCNTE; /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register */ + + struct + { + __IOM uint32_t ATCE : 1; /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1, + * SC2. */ + uint32_t : 31; + } ATCCNTE_b; + }; + __IM uint32_t RESERVED12[4]; union { @@ -9928,14 +10076,43 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 29; } CNDCTL_b; }; - __IM uint32_t RESERVED12[3]; + __IM uint32_t RESERVED13[3]; __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ - __IM uint32_t RESERVED13[8]; + __IM uint32_t RESERVED14[8]; __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ - __IM uint32_t RESERVED14[3]; + + union + { + __OM uint32_t HCMDQP; /*!< (@ 0x00000184) High Priority Command Queue Port Register */ + + struct + { + __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port */ + } HCMDQP_b; + }; + + union + { + __IM uint32_t HRSPQP; /*!< (@ 0x00000188) High Priority Response Queue Port Register */ + + struct + { + __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port */ + } HRSPQP_b; + }; + + union + { + __IOM uint32_t HTDTBP; /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register */ + + struct + { + __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port */ + } HTDTBP_b; + }; union { @@ -9980,7 +10157,37 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 24; } NRQTHCTL_b; }; - __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t HQTHCTL; /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold */ + uint32_t : 16; + } HQTHCTL_b; + }; + + union + { + __IOM uint32_t HTBTHCTL; /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold + * Control Register */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold */ + uint32_t : 5; + } HTBTHCTL_b; + }; + __IM uint32_t RESERVED16; union { @@ -10153,7 +10360,79 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 11; } NTSTFC_b; }; - __IM uint32_t RESERVED17[8]; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint32_t HTST; /*!< (@ 0x00000200) High Priority Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag */ + __IOM uint32_t RDBFF : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag */ + uint32_t : 1; + __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] High Priority Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] High Priority Transfer Error Flag */ + uint32_t : 22; + } HTST_b; + }; + + union + { + __IOM uint32_t HTSTE; /*!< (@ 0x00000204) High Priority Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable */ + __IOM uint32_t RDBFE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] High Priority Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] High Priority Transfer Error Enable */ + uint32_t : 22; + } HTSTE_b; + }; + + union + { + __IOM uint32_t HTIE; /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable */ + __IOM uint32_t RDBFIE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable */ + uint32_t : 22; + } HTIE_b; + }; + + union + { + __IOM uint32_t HTSTFC; /*!< (@ 0x0000020C) High Priority Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force */ + __OM uint32_t RDBFFC : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force */ + uint32_t : 1; + __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] High Priority Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] High Priority Transfer Error Force */ + uint32_t : 22; + } HTSTFC_b; + }; union { @@ -10180,22 +10459,32 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ uint32_t : 8; __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ - __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */ - uint32_t : 15; + __IOM uint32_t SVAFn : 3; /*!< [18..16] Slave Address Detection Flag */ + uint32_t : 13; } SVST_b; }; union { - __IOM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Control Register */ + __IM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Operating Status Register */ struct { - __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ - uint32_t : 31; + __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; } WUST_b; }; - __IM uint32_t RESERVED18[2]; + + union + { + __IM uint32_t MRCCPT; /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register */ + + struct + { + __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture */ + } MRCCPT_b; + }; + __IM uint32_t RESERVED18; union { @@ -10275,7 +10564,87 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ } DATBAS3_b; }; - __IM uint32_t RESERVED22[24]; + __IM uint32_t RESERVED22; + + union + { + __IOM uint32_t DATBAS4; /*!< (@ 0x00000244) Device Address Table Basic Register 4 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS4_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IOM uint32_t DATBAS5; /*!< (@ 0x0000024C) Device Address Table Basic Register 5 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS5_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t DATBAS6; /*!< (@ 0x00000254) Device Address Table Basic Register 6 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS6_b; + }; + __IM uint32_t RESERVED25; + + union + { + __IOM uint32_t DATBAS7; /*!< (@ 0x0000025C) Device Address Table Basic Register 7 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS7_b; + }; + __IM uint32_t RESERVED26[16]; union { @@ -10291,7 +10660,7 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ } EXDATBAS_b; }; - __IM uint32_t RESERVED23[3]; + __IM uint32_t RESERVED27[3]; union { @@ -10340,7 +10709,7 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 9; } SDATBAS2_b; }; - __IM uint32_t RESERVED24[5]; + __IM uint32_t RESERVED28[5]; union { @@ -10413,7 +10782,79 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 16; } MSDCT3_b; }; - __IM uint32_t RESERVED25[16]; + + union + { + __IOM uint32_t MSDCT4; /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT4_b; + }; + + union + { + __IOM uint32_t MSDCT5; /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT5_b; + }; + + union + { + __IOM uint32_t MSDCT6; /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT6_b; + }; + + union + { + __IOM uint32_t MSDCT7; /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT7_b; + }; + __IM uint32_t RESERVED29[12]; union { @@ -10436,7 +10877,7 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure * ID Low Register */ __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional * ID High Register */ - __IM uint32_t RESERVED26; + __IM uint32_t RESERVED30; union { @@ -10453,7 +10894,39 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ } SVDVAD0_b; }; - __IM uint32_t RESERVED27[7]; + + union + { + __IM uint32_t SVDVAD1; /*!< (@ 0x00000334) Slave Device Address Register 1 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD1_b; + }; + + union + { + __IM uint32_t SVDVAD2; /*!< (@ 0x00000338) Slave Device Address Register 2 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD2_b; + }; + __IM uint32_t RESERVED31[5]; union { @@ -10566,18 +11039,35 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure union { - __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) - * Register */ + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ struct { - uint32_t : 8; - __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ - __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ - uint32_t : 8; + __IOM uint32_t SPTSYN : 1; /*!< [0..0] Supports Sync Mode */ + __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0 */ + __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1 */ + uint32_t : 5; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; } CETSM_b; }; - __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t CETSS; /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State) + * Register */ + + struct + { + __IOM uint32_t SYNE : 1; /*!< [0..0] Sync Mode Enabled */ + __IOM uint32_t ASYNE : 2; /*!< [2..1] Async Mode Enabled */ + uint32_t : 4; + __IOM uint32_t ICOVF : 1; /*!< [7..7] Internal Counter Overflow */ + uint32_t : 24; + } CETSS_b; + }; union { @@ -10604,7 +11094,7 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 24; } BITCNT_b; }; - __IM uint32_t RESERVED29[4]; + __IM uint32_t RESERVED32[4]; union { @@ -10622,7 +11112,7 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure union { - __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */ + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0 */ struct { @@ -10631,7 +11121,7 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 16; } NDBSTLV0_b; }; - __IM uint32_t RESERVED30[9]; + __IM uint32_t RESERVED33[9]; union { @@ -10643,7 +11133,30 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 24; } NRSQSTLV_b; }; - __IM uint32_t RESERVED31[2]; + + union + { + __IM uint32_t HQSTLV; /*!< (@ 0x000003C4) High Priority Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQLV : 8; /*!< [7..0] High Priority Command Queue Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] High Priority Response Queue Level */ + uint32_t : 16; + } HQSTLV_b; + }; + + union + { + __IM uint32_t HDBSTLV; /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] High Priority Tx Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] High Priority Rx Data Buffer Level */ + uint32_t : 16; + } HDBSTLV_b; + }; union { @@ -10669,7 +11182,30 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 24; } MSERRCNT_b; }; -} R_I3C0_Type; /*!< Size = 980 (0x3d4) */ + __IM uint32_t RESERVED34[3]; + + union + { + __IM uint32_t SC1CPT; /*!< (@ 0x000003E0) SC1 Capture monitor Register */ + + struct + { + __IM uint32_t SC1C : 16; /*!< [15..0] SC1 Capture */ + uint32_t : 16; + } SC1CPT_b; + }; + + union + { + __IM uint32_t SC2CPT; /*!< (@ 0x000003E4) SC2 Capture monitor Register */ + + struct + { + __IM uint32_t SC2C : 16; /*!< [15..0] SC2 Capture */ + uint32_t : 16; + } SC2CPT_b; + }; +} R_I3C0_Type; /*!< Size = 1000 (0x3e8) */ /* =========================================================================================================================== */ /* ================ R_MPU_MMPU ================ */ @@ -17341,7 +17877,7 @@ typedef struct /*!< (@ 0x40250000) R_USB_FS0 Structure * data. */ uint16_t : 1; __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ } CFIFOCTR_b; }; @@ -17361,7 +17897,7 @@ typedef struct /*!< (@ 0x40250000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D0FIFOSEL_b; }; @@ -17395,7 +17931,7 @@ typedef struct /*!< (@ 0x40250000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D1FIFOSEL_b; }; @@ -17670,14 +18206,13 @@ typedef struct /*!< (@ 0x40250000) R_USB_FS0 Structure union { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ struct { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; + uint16_t : 15; __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; + } DVCHGR_b; }; union @@ -17690,8 +18225,8 @@ typedef struct /*!< (@ 0x40250000) R_USB_FS0 Structure * the USB address assigned by the host when the USBHS processed * the SET_ADDRESS request successfully. */ uint16_t : 1; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; } USBADDR_b; }; __IM uint16_t RESERVED9; @@ -22196,6 +22731,81 @@ typedef struct /*!< (@ 0x40221000) R_AGTX0 Structure }; } R_AGTX0_Type; /*!< Size = 20 (0x14) */ +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CANFD ECC (R_ECCMB0) + */ + +typedef struct /*!< (@ 0x4036F200) R_ECCMB0 Structure */ +{ + union + { + __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ + + struct + { + __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Message Flag */ + __IM uint32_t ECER1F : 1; /*!< [1..1] ECC Error Detection and Correction Flag */ + __IM uint32_t ECER2F : 1; /*!< [2..2] 2-bit ECC Error Detection Flag */ + __IOM uint32_t EC1EDIC : 1; /*!< [3..3] ECC 1-bit Error Detection Interrupt Control */ + __IOM uint32_t EC2EDIC : 1; /*!< [4..4] ECC 2-bit Error Detection Interrupt Control */ + __IOM uint32_t EC1ECP : 1; /*!< [5..5] ECC 1-bit Error Correction Permission */ + __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Judgment Enable Flag */ + uint32_t : 2; + __IOM uint32_t ECER1C : 1; /*!< [9..9] Accumulating ECC Error Detection and Correction Flag + * Clear */ + __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-bit ECC Error Detection Flag Clear */ + __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Overflow Detection Flag */ + uint32_t : 2; + __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Select bit */ + __IM uint32_t ECSEDF0 : 1; /*!< [16..16] ECC Single bit Error Address Detection Flag */ + __IM uint32_t ECDEDF0 : 1; /*!< [17..17] ECC Dual Bit Error Address Detection Flag */ + uint32_t : 14; + } EC710CTL_b; + }; + + union + { + __IOM uint16_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ + uint16_t : 5; + __IOM uint16_t ECTMCE : 1; /*!< [7..7] ECC Test Mode Control Enable */ + uint16_t : 6; + __IOM uint16_t ETMA : 2; /*!< [15..14] ECC Test Mode Bit Access Control */ + } EC710TMC_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Test Substitute Data Register */ + + struct + { + __IOM uint32_t ECEDB : 32; /*!< [31..0] ECC Test Substitute Data */ + } EC710TED_b; + }; + + union + { + __IM uint32_t EC710EAD0; /*!< (@ 0x00000010) ECC Error Address Register */ + + struct + { + __IM uint32_t ECEAD : 10; /*!< [9..0] ECC Error Address */ + uint32_t : 22; + } EC710EAD0_b; + }; +} R_ECCMB0_Type; /*!< Size = 20 (0x14) */ + /* =========================================================================================================================== */ /* ================ R_FLAD ================ */ /* =========================================================================================================================== */ @@ -22364,7 +22974,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_CANFD1_BASE (0x40382000UL + BASE_NS_OFFSET) #define R_CRC_BASE (0x40310000UL + BASE_NS_OFFSET) #define R_DAC_BASE (0x40333000UL + BASE_NS_OFFSET) - #define R_DAC1_BASE (0x40333100UL + BASE_NS_OFFSET) #define R_DEBUG_BASE (0x4001B000UL + BASE_NS_OFFSET) #define R_DMA_BASE (0x4000A800UL + BASE_NS_OFFSET) #define R_DMAC0_BASE (0x4000A000UL + BASE_NS_OFFSET) @@ -22480,12 +23089,17 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_AGTX7_BASE (0x40221700UL + BASE_NS_OFFSET) #define R_AGTX8_BASE (0x40221800UL + BASE_NS_OFFSET) #define R_AGTX9_BASE (0x40221900UL + BASE_NS_OFFSET) + #define R_DOTF1_BASE (0x40268900UL + BASE_NS_OFFSET) + #define R_ECCMB0_BASE (0x4036F200UL + BASE_NS_OFFSET) + #define R_ECCMB1_BASE (0x4036F300UL + BASE_NS_OFFSET) #define R_FLAD_BASE (0x4011C000UL + BASE_NS_OFFSET) #define R_OFS_DATAFLASH_BASE (0x27030000UL + BASE_NS_OFFSET) #define R_SCI_B5_BASE (0x40358500UL + BASE_NS_OFFSET) #define R_SCI_B6_BASE (0x40358600UL + BASE_NS_OFFSET) #define R_SCI_B7_BASE (0x40358700UL + BASE_NS_OFFSET) #define R_SCI_B8_BASE (0x40358800UL + BASE_NS_OFFSET) + #define R_WDT1_BASE (0x40044300UL + BASE_NS_OFFSET) + #define R_XSPI1_BASE (0x40268400UL + BASE_NS_OFFSET) /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -22513,7 +23127,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_CANFD1 ((R_CANFD_Type *) R_CANFD1_BASE) #define R_CRC ((R_CRC_Type *) R_CRC_BASE) #define R_DAC ((R_DAC_Type *) R_DAC_BASE) - #define R_DAC1 ((R_DAC_Type *) R_DAC1_BASE) #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) #define R_DMA ((R_DMA_Type *) R_DMA_BASE) #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) @@ -22629,12 +23242,17 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_DOTF1 ((R_DOTF_Type *) R_DOTF1_BASE) + #define R_ECCMB0 ((R_ECCMB0_Type *) R_ECCMB0_BASE) + #define R_ECCMB1 ((R_ECCMB0_Type *) R_ECCMB1_BASE) #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) #define R_OFS_DATAFLASH ((R_OFS_DATAFLASH_Type *) R_OFS_DATAFLASH_BASE) #define R_SCI_B5 ((R_SCI_B0_Type *) R_SCI_B5_BASE) #define R_SCI_B6 ((R_SCI_B0_Type *) R_SCI_B6_BASE) #define R_SCI_B7 ((R_SCI_B0_Type *) R_SCI_B7_BASE) #define R_SCI_B8 ((R_SCI_B0_Type *) R_SCI_B8_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) + #define R_XSPI1 ((R_XSPI_Type *) R_XSPI1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -23836,32 +24454,38 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* =========================================================================================================================== */ /* ======================================================== CMPCTL ========================================================= */ - #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ - #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ - #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ - #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ - #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ - #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ - #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ - #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ - #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ /* ======================================================== CMPSEL0 ======================================================== */ - #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ - #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ /* ======================================================== CMPSEL1 ======================================================== */ - #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ - #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ /* ======================================================== CMPMON ========================================================= */ - #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ - #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ /* ========================================================= CPIOC ========================================================= */ - #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ - #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ - #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPINTCTL ======================================================== */ + #define R_ACMPHS0_CPINTCTL_MSKE_Pos (0UL) /*!< MSKE (Bit 0) */ + #define R_ACMPHS0_CPINTCTL_MSKE_Msk (0x1UL) /*!< MSKE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPMSKCTL ======================================================== */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Pos (0UL) /*!< MSKSEL (Bit 0) */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Msk (0x7UL) /*!< MSKSEL (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_ADC0 ================ */ @@ -24643,7 +25267,7 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x100UL) /*!< CFXMLT (Bitfield-Mask: 0x01) */ /* ======================================================= CFDRFISTS ======================================================= */ #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ - #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x1UL) /*!< RFXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x3UL) /*!< RFXIF (Bitfield-Mask: 0x03) */ /* ======================================================== CFDTMC ========================================================= */ #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ @@ -24889,9 +25513,14 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ========================================================= DMAST ========================================================= */ #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* ======================================================== DMECHR ========================================================= */ #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ @@ -24901,11 +25530,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -25699,6 +26323,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -25722,6 +26348,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -25761,9 +26389,15 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -25838,7 +26472,13 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -25875,8 +26515,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -26062,6 +26700,24 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ @@ -26698,6 +27354,14 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HCMDQRST_Pos (9UL) /*!< HCMDQRST (Bit 9) */ + #define R_I3C0_RSTCTL_HCMDQRST_Msk (0x200UL) /*!< HCMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRSPQRST_Pos (10UL) /*!< HRSPQRST (Bit 10) */ + #define R_I3C0_RSTCTL_HRSPQRST_Msk (0x400UL) /*!< HRSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HTDBRST_Pos (11UL) /*!< HTDBRST (Bit 11) */ + #define R_I3C0_RSTCTL_HTDBRST_Msk (0x800UL) /*!< HTDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRDBRST_Pos (12UL) /*!< HRDBRST (Bit 12) */ + #define R_I3C0_RSTCTL_HRDBRST_Msk (0x1000UL) /*!< HRDBRST (Bitfield-Mask: 0x01) */ #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ /* ========================================================= PRSST ========================================================= */ @@ -26754,7 +27418,7 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ - #define R_I3C0_SVCTL_SVAEn_Msk (0x10000UL) /*!< SVAEn (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_SVAEn_Msk (0x70000UL) /*!< SVAEn (Bitfield-Mask: 0x07) */ /* ======================================================= REFCKCTL ======================================================== */ #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ @@ -26849,6 +27513,24 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================== SVTDLG0 ======================================================== */ #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= STCTL ========================================================= */ + #define R_I3C0_STCTL_STOE_Pos (0UL) /*!< STOE (Bit 0) */ + #define R_I3C0_STCTL_STOE_Msk (0x1UL) /*!< STOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ATCTL ========================================================= */ + #define R_I3C0_ATCTL_ATTRGS_Pos (0UL) /*!< ATTRGS (Bit 0) */ + #define R_I3C0_ATCTL_ATTRGS_Msk (0x1UL) /*!< ATTRGS (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_MREFOE_Pos (1UL) /*!< MREFOE (Bit 1) */ + #define R_I3C0_ATCTL_MREFOE_Msk (0x2UL) /*!< MREFOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_AMEOE_Pos (2UL) /*!< AMEOE (Bit 2) */ + #define R_I3C0_ATCTL_AMEOE_Msk (0x4UL) /*!< AMEOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_CDIV_Pos (8UL) /*!< CDIV (Bit 8) */ + #define R_I3C0_ATCTL_CDIV_Msk (0xff00UL) /*!< CDIV (Bitfield-Mask: 0xff) */ +/* ========================================================= ATTRG ========================================================= */ + #define R_I3C0_ATTRG_ATSTRG_Pos (0UL) /*!< ATSTRG (Bit 0) */ + #define R_I3C0_ATTRG_ATSTRG_Msk (0x1UL) /*!< ATSTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== ATCCNTE ======================================================== */ + #define R_I3C0_ATCCNTE_ATCE_Pos (0UL) /*!< ATCE (Bit 0) */ + #define R_I3C0_ATCCNTE_ATCE_Msk (0x1UL) /*!< ATCE (Bitfield-Mask: 0x01) */ /* ======================================================== CNDCTL ========================================================= */ #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ @@ -26861,6 +27543,15 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================== NTDTBP0 ======================================================== */ /* ======================================================== NIBIQP ========================================================= */ /* ========================================================= NRSQP ========================================================= */ +/* ======================================================== HCMDQP ========================================================= */ + #define R_I3C0_HCMDQP_HCMDQP_Pos (0UL) /*!< HCMDQP (Bit 0) */ + #define R_I3C0_HCMDQP_HCMDQP_Msk (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HRSPQP ========================================================= */ + #define R_I3C0_HRSPQP_HRSPQP_Pos (0UL) /*!< HRSPQP (Bit 0) */ + #define R_I3C0_HRSPQP_HRSPQP_Msk (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HTDTBP ========================================================= */ + #define R_I3C0_HTDTBP_HTDTBP_Pos (0UL) /*!< HTDTBP (Bit 0) */ + #define R_I3C0_HTDTBP_HTDTBP_Msk (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff) */ /* ======================================================== NQTHCTL ======================================================== */ #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ @@ -26882,6 +27573,20 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================= NRQTHCTL ======================================================== */ #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ +/* ======================================================== HQTHCTL ======================================================== */ + #define R_I3C0_HQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_HQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_HQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= HTBTHCTL ======================================================== */ + #define R_I3C0_HTBTHCTL_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_HTBTHCTL_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ /* ========================================================== BST ========================================================== */ #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ @@ -27018,6 +27723,58 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ +/* ========================================================= HTST ========================================================== */ + #define R_I3C0_HTST_TDBEF_Pos (0UL) /*!< TDBEF (Bit 0) */ + #define R_I3C0_HTST_TDBEF_Msk (0x1UL) /*!< TDBEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RDBFF_Pos (1UL) /*!< RDBFF (Bit 1) */ + #define R_I3C0_HTST_RDBFF_Msk (0x2UL) /*!< RDBFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_HTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_HTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_HTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_HTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ +/* ========================================================= HTSTE ========================================================= */ + #define R_I3C0_HTSTE_TDBEE_Pos (0UL) /*!< TDBEE (Bit 0) */ + #define R_I3C0_HTSTE_TDBEE_Msk (0x1UL) /*!< TDBEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RDBFE_Pos (1UL) /*!< RDBFE (Bit 1) */ + #define R_I3C0_HTSTE_RDBFE_Msk (0x2UL) /*!< RDBFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_HTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_HTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_HTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_HTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ +/* ========================================================= HTIE ========================================================== */ + #define R_I3C0_HTIE_TDBEIE_Pos (0UL) /*!< TDBEIE (Bit 0) */ + #define R_I3C0_HTIE_TDBEIE_Msk (0x1UL) /*!< TDBEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RDBFIE_Pos (1UL) /*!< RDBFIE (Bit 1) */ + #define R_I3C0_HTIE_RDBFIE_Msk (0x2UL) /*!< RDBFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_HTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_HTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_HTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_HTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== HTSTFC ========================================================= */ + #define R_I3C0_HTSTFC_TDBEFC_Pos (0UL) /*!< TDBEFC (Bit 0) */ + #define R_I3C0_HTSTFC_TDBEFC_Msk (0x1UL) /*!< TDBEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RDBFFC_Pos (1UL) /*!< RDBFFC (Bit 1) */ + #define R_I3C0_HTSTFC_RDBFFC_Msk (0x2UL) /*!< RDBFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_HTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_HTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_HTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_HTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ /* ========================================================= BCST ========================================================== */ #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ @@ -27035,10 +27792,13 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ - #define R_I3C0_SVST_SVAFn_Msk (0x10000UL) /*!< SVAFn (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_SVAFn_Msk (0x70000UL) /*!< SVAFn (Bitfield-Mask: 0x07) */ /* ========================================================= WUST ========================================================== */ #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCCPT ========================================================= */ + #define R_I3C0_MRCCPT_MRCCPT_Pos (0UL) /*!< MRCCPT (Bit 0) */ + #define R_I3C0_MRCCPT_MRCCPT_Msk (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff) */ /* ======================================================== DATBAS0 ======================================================== */ #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ @@ -27107,6 +27867,74 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS4 ======================================================== */ + #define R_I3C0_DATBAS4_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS4_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS4_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS4_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS4_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS4_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS4_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS4_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS4_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS4_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS4_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS5 ======================================================== */ + #define R_I3C0_DATBAS5_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS5_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS5_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS5_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS5_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS5_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS5_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS5_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS5_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS5_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS5_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS6 ======================================================== */ + #define R_I3C0_DATBAS6_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS6_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS6_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS6_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS6_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS6_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS6_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS6_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS6_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS6_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS6_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS7 ======================================================== */ + #define R_I3C0_DATBAS7_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS7_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS7_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS7_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS7_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS7_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS7_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS7_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS7_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS7_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS7_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ /* ======================================================= EXDATBAS ======================================================== */ #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ @@ -27203,6 +28031,66 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT4 ========================================================= */ + #define R_I3C0_MSDCT4_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT4_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT4_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT4_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT4_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT4_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT4_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT4_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT5 ========================================================= */ + #define R_I3C0_MSDCT5_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT5_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT5_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT5_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT5_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT5_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT5_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT5_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT6 ========================================================= */ + #define R_I3C0_MSDCT6_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT6_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT6_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT6_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT6_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT6_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT6_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT6_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT7 ========================================================= */ + #define R_I3C0_MSDCT7_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT7_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT7_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT7_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT7_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT7_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT7_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT7_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ========================================================= SVDCT ========================================================= */ #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ @@ -27231,6 +28119,24 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD1 ======================================================== */ + #define R_I3C0_SVDVAD1_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD1_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD1_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD1_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD1_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD1_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD2 ======================================================== */ + #define R_I3C0_SVDVAD2_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD2_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD2_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD2_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD2_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD2_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ /* ======================================================== CSECMD ========================================================= */ #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ @@ -27275,10 +28181,23 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ /* ========================================================= CETSM ========================================================= */ + #define R_I3C0_CETSM_SPTSYN_Pos (0UL) /*!< SPTSYN (Bit 0) */ + #define R_I3C0_CETSM_SPTSYN_Msk (0x1UL) /*!< SPTSYN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN0_Pos (1UL) /*!< SPTASYN0 (Bit 1) */ + #define R_I3C0_CETSM_SPTASYN0_Msk (0x2UL) /*!< SPTASYN0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN1_Pos (2UL) /*!< SPTASYN1 (Bit 2) */ + #define R_I3C0_CETSM_SPTASYN1_Msk (0x4UL) /*!< SPTASYN1 (Bitfield-Mask: 0x01) */ #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ========================================================= CETSS ========================================================= */ + #define R_I3C0_CETSS_SYNE_Pos (0UL) /*!< SYNE (Bit 0) */ + #define R_I3C0_CETSS_SYNE_Msk (0x1UL) /*!< SYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSS_ASYNE_Pos (1UL) /*!< ASYNE (Bit 1) */ + #define R_I3C0_CETSS_ASYNE_Msk (0x6UL) /*!< ASYNE (Bitfield-Mask: 0x03) */ + #define R_I3C0_CETSS_ICOVF_Pos (7UL) /*!< ICOVF (Bit 7) */ + #define R_I3C0_CETSS_ICOVF_Msk (0x80UL) /*!< ICOVF (Bitfield-Mask: 0x01) */ /* ======================================================= CGHDRCAP ======================================================== */ #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ @@ -27308,6 +28227,16 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================= NRSQSTLV ======================================================== */ #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HQSTLV ========================================================= */ + #define R_I3C0_HQSTLV_CMDQLV_Pos (0UL) /*!< CMDQLV (Bit 0) */ + #define R_I3C0_HQSTLV_CMDQLV_Msk (0xffUL) /*!< CMDQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_HQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HDBSTLV ======================================================== */ + #define R_I3C0_HDBSTLV_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_HDBSTLV_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HDBSTLV_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_HDBSTLV_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ /* ======================================================== PRSTDBG ======================================================== */ #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ @@ -27320,6 +28249,12 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================= MSERRCNT ======================================================== */ #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ +/* ======================================================== SC1CPT ========================================================= */ + #define R_I3C0_SC1CPT_SC1C_Pos (0UL) /*!< SC1C (Bit 0) */ + #define R_I3C0_SC1CPT_SC1C_Msk (0xffffUL) /*!< SC1C (Bitfield-Mask: 0xffff) */ +/* ======================================================== SC2CPT ========================================================= */ + #define R_I3C0_SC2CPT_SC2C_Pos (0UL) /*!< SC2C (Bit 0) */ + #define R_I3C0_SC2CPT_SC2C_Msk (0xffffUL) /*!< SC2C (Bitfield-Mask: 0xffff) */ /* =========================================================================================================================== */ /* ================ R_MPU_MMPU ================ */ @@ -30216,14 +31151,12 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== UFRMNUM ======================================================== */ - #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ /* ======================================================== USBADDR ======================================================== */ #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ /* ======================================================== USBREQ ========================================================= */ @@ -32623,6 +33556,51 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ================ R_AGTX0 ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= EC710CTL ======================================================== */ + #define R_ECCMB0_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ + #define R_ECCMB0_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ + #define R_ECCMB0_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ + #define R_ECCMB0_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ + #define R_ECCMB0_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ + #define R_ECCMB0_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ + #define R_ECCMB0_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ + #define R_ECCMB0_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Pos (16UL) /*!< ECSEDF0 (Bit 16) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Msk (0x10000UL) /*!< ECSEDF0 (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Pos (17UL) /*!< ECDEDF0 (Bit 17) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Msk (0x20000UL) /*!< ECDEDF0 (Bitfield-Mask: 0x01) */ +/* ======================================================= EC710TMC ======================================================== */ + #define R_ECCMB0_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ + #define R_ECCMB0_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ + #define R_ECCMB0_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ +/* ======================================================= EC710TED ======================================================== */ + #define R_ECCMB0_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ + #define R_ECCMB0_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EC710EAD0 ======================================================= */ + #define R_ECCMB0_EC710EAD0_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ + #define R_ECCMB0_EC710EAD0_ECEAD_Msk (0x3ffUL) /*!< ECEAD (Bitfield-Mask: 0x3ff) */ + /* =========================================================================================================================== */ /* ================ R_FLAD ================ */ /* =========================================================================================================================== */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8T1AH.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8T1AH.h index e97b28d16..8463e54b6 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8T1AH.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8T1AH.h @@ -2673,7 +2673,31 @@ typedef struct /*!< (@ 0x40236000) R_ACMPHS0 Structure __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ } CPIOC_b; }; -} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ + __IM uint8_t RESERVED4[47]; + + union + { + __IOM uint8_t CPINTCTL; /*!< (@ 0x00000040) Comparator Interrupt Control Register */ + + struct + { + __IOM uint8_t MSKE : 1; /*!< [0..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 7; + } CPINTCTL_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t CPMSKCTL; /*!< (@ 0x00000044) Comparator Interrupt Mask Control Register */ + + struct + { + __IOM uint8_t MSKSEL : 3; /*!< [2..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 5; + } CPMSKCTL_b; + }; +} R_ACMPHS0_Type; /*!< Size = 69 (0x45) */ /* =========================================================================================================================== */ /* ================ R_ADC0 ================ */ @@ -2936,7 +2960,7 @@ typedef struct /*!< (@ 0x40332000) R_ADC0 Structure struct { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ } ADRD_RIGHT_b; @@ -2949,7 +2973,7 @@ typedef struct /*!< (@ 0x40332000) R_ADC0 Structure struct { __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for * data determine ADCER.ADRFMT and ADCER.ADPRC. */ } ADRD_LEFT_b; }; @@ -5008,8 +5032,8 @@ typedef struct /*!< (@ 0x40380000) R_CANFD0 Structure struct { - __IM uint32_t RFXIF : 1; /*!< [0..0] RX FIFO[x] Interrupt Flag Status */ - uint32_t : 31; + __IM uint32_t RFXIF : 2; /*!< [1..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 30; } CFDRFISTS_b; }; @@ -5701,8 +5725,8 @@ typedef struct /*!< (@ 0x4000A800) R_DMA Structure struct { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ uint32_t : 7; __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ @@ -7941,7 +7965,8 @@ typedef struct /*!< (@ 0x40322000) R_GPT0 Structure __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; } GTICASR_b; }; @@ -7988,7 +8013,8 @@ typedef struct /*!< (@ 0x40322000) R_GPT0 Structure __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; } GTICBSR_b; }; @@ -7999,7 +8025,10 @@ typedef struct /*!< (@ 0x40322000) R_GPT0 Structure struct { __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ @@ -8016,24 +8045,26 @@ typedef struct /*!< (@ 0x40322000) R_GPT0 Structure union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; } GTUDDTYC_b; }; @@ -8077,12 +8108,24 @@ typedef struct /*!< (@ 0x40322000) R_GPT0 Structure union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous * Clear Enable */ @@ -8559,7 +8602,57 @@ typedef struct /*!< (@ 0x40322000) R_GPT0 Structure uint32_t : 4; } GTPC_b; }; - __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; union { @@ -9539,20 +9632,25 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure union { - __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ struct { - __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ - __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ - __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ - __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ - __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ - __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ - __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ - uint32_t : 9; - __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ - uint32_t : 15; + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 2; + __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset */ + __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese */ + __IOM uint32_t HTDBRST : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset */ + __IOM uint32_t HRDBRST : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset */ + uint32_t : 3; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; } RSTCTL_b; }; @@ -9682,8 +9780,8 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ uint32_t : 8; __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ - __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */ - uint32_t : 15; + __IOM uint32_t SVAEn : 3; /*!< [18..16] Slave Address Enable */ + uint32_t : 13; } SVCTL_b; }; __IM uint32_t RESERVED6[2]; @@ -9725,7 +9823,7 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ uint32_t : 2; - __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */ + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull */ uint32_t : 2; } EXTBR_b; }; @@ -9879,7 +9977,57 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ } SVTDLG0_b; }; - __IM uint32_t RESERVED11[31]; + __IM uint32_t RESERVED11[23]; + + union + { + __IOM uint32_t STCTL; /*!< (@ 0x00000120) Synchronous Timing Control Register */ + + struct + { + __IOM uint32_t STOE : 1; /*!< [0..0] Synchronous Timing output Enable */ + uint32_t : 31; + } STCTL_b; + }; + + union + { + __IOM uint32_t ATCTL; /*!< (@ 0x00000124) Asynchronous Timing Control Register */ + + struct + { + __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select */ + __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow) */ + __IOM uint32_t AMEOE : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable */ + uint32_t : 5; + __IOM uint32_t CDIV : 8; /*!< [15..8] TCLK Counter Divide Setting */ + uint32_t : 16; + } ATCTL_b; + }; + + union + { + __IOM uint32_t ATTRG; /*!< (@ 0x00000128) Asynchronous Timing Trigger Register */ + + struct + { + __OM uint32_t ATSTRG : 1; /*!< [0..0] Asynchronous Timing Software Trigger */ + uint32_t : 31; + } ATTRG_b; + }; + + union + { + __IOM uint32_t ATCCNTE; /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register */ + + struct + { + __IOM uint32_t ATCE : 1; /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1, + * SC2. */ + uint32_t : 31; + } ATCCNTE_b; + }; + __IM uint32_t RESERVED12[4]; union { @@ -9893,14 +10041,43 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 29; } CNDCTL_b; }; - __IM uint32_t RESERVED12[3]; + __IM uint32_t RESERVED13[3]; __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ - __IM uint32_t RESERVED13[8]; + __IM uint32_t RESERVED14[8]; __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ - __IM uint32_t RESERVED14[3]; + + union + { + __OM uint32_t HCMDQP; /*!< (@ 0x00000184) High Priority Command Queue Port Register */ + + struct + { + __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port */ + } HCMDQP_b; + }; + + union + { + __IM uint32_t HRSPQP; /*!< (@ 0x00000188) High Priority Response Queue Port Register */ + + struct + { + __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port */ + } HRSPQP_b; + }; + + union + { + __IOM uint32_t HTDTBP; /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register */ + + struct + { + __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port */ + } HTDTBP_b; + }; union { @@ -9945,7 +10122,37 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 24; } NRQTHCTL_b; }; - __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t HQTHCTL; /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold */ + uint32_t : 16; + } HQTHCTL_b; + }; + + union + { + __IOM uint32_t HTBTHCTL; /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold + * Control Register */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold */ + uint32_t : 5; + } HTBTHCTL_b; + }; + __IM uint32_t RESERVED16; union { @@ -10118,7 +10325,79 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 11; } NTSTFC_b; }; - __IM uint32_t RESERVED17[8]; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint32_t HTST; /*!< (@ 0x00000200) High Priority Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag */ + __IOM uint32_t RDBFF : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag */ + uint32_t : 1; + __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] High Priority Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] High Priority Transfer Error Flag */ + uint32_t : 22; + } HTST_b; + }; + + union + { + __IOM uint32_t HTSTE; /*!< (@ 0x00000204) High Priority Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable */ + __IOM uint32_t RDBFE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] High Priority Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] High Priority Transfer Error Enable */ + uint32_t : 22; + } HTSTE_b; + }; + + union + { + __IOM uint32_t HTIE; /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable */ + __IOM uint32_t RDBFIE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable */ + uint32_t : 22; + } HTIE_b; + }; + + union + { + __IOM uint32_t HTSTFC; /*!< (@ 0x0000020C) High Priority Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force */ + __OM uint32_t RDBFFC : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force */ + uint32_t : 1; + __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] High Priority Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] High Priority Transfer Error Force */ + uint32_t : 22; + } HTSTFC_b; + }; union { @@ -10145,22 +10424,32 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ uint32_t : 8; __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ - __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */ - uint32_t : 15; + __IOM uint32_t SVAFn : 3; /*!< [18..16] Slave Address Detection Flag */ + uint32_t : 13; } SVST_b; }; union { - __IOM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Control Register */ + __IM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Operating Status Register */ struct { - __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ - uint32_t : 31; + __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; } WUST_b; }; - __IM uint32_t RESERVED18[2]; + + union + { + __IM uint32_t MRCCPT; /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register */ + + struct + { + __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture */ + } MRCCPT_b; + }; + __IM uint32_t RESERVED18; union { @@ -10240,7 +10529,87 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ } DATBAS3_b; }; - __IM uint32_t RESERVED22[24]; + __IM uint32_t RESERVED22; + + union + { + __IOM uint32_t DATBAS4; /*!< (@ 0x00000244) Device Address Table Basic Register 4 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS4_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IOM uint32_t DATBAS5; /*!< (@ 0x0000024C) Device Address Table Basic Register 5 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS5_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t DATBAS6; /*!< (@ 0x00000254) Device Address Table Basic Register 6 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS6_b; + }; + __IM uint32_t RESERVED25; + + union + { + __IOM uint32_t DATBAS7; /*!< (@ 0x0000025C) Device Address Table Basic Register 7 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS7_b; + }; + __IM uint32_t RESERVED26[16]; union { @@ -10256,7 +10625,7 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ } EXDATBAS_b; }; - __IM uint32_t RESERVED23[3]; + __IM uint32_t RESERVED27[3]; union { @@ -10305,7 +10674,7 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 9; } SDATBAS2_b; }; - __IM uint32_t RESERVED24[5]; + __IM uint32_t RESERVED28[5]; union { @@ -10378,7 +10747,79 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 16; } MSDCT3_b; }; - __IM uint32_t RESERVED25[16]; + + union + { + __IOM uint32_t MSDCT4; /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT4_b; + }; + + union + { + __IOM uint32_t MSDCT5; /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT5_b; + }; + + union + { + __IOM uint32_t MSDCT6; /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT6_b; + }; + + union + { + __IOM uint32_t MSDCT7; /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT7_b; + }; + __IM uint32_t RESERVED29[12]; union { @@ -10401,7 +10842,7 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure * ID Low Register */ __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional * ID High Register */ - __IM uint32_t RESERVED26; + __IM uint32_t RESERVED30; union { @@ -10418,7 +10859,39 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ } SVDVAD0_b; }; - __IM uint32_t RESERVED27[7]; + + union + { + __IM uint32_t SVDVAD1; /*!< (@ 0x00000334) Slave Device Address Register 1 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD1_b; + }; + + union + { + __IM uint32_t SVDVAD2; /*!< (@ 0x00000338) Slave Device Address Register 2 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD2_b; + }; + __IM uint32_t RESERVED31[5]; union { @@ -10531,18 +11004,35 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure union { - __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) - * Register */ + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ struct { - uint32_t : 8; - __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ - __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ - uint32_t : 8; + __IOM uint32_t SPTSYN : 1; /*!< [0..0] Supports Sync Mode */ + __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0 */ + __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1 */ + uint32_t : 5; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; } CETSM_b; }; - __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t CETSS; /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State) + * Register */ + + struct + { + __IOM uint32_t SYNE : 1; /*!< [0..0] Sync Mode Enabled */ + __IOM uint32_t ASYNE : 2; /*!< [2..1] Async Mode Enabled */ + uint32_t : 4; + __IOM uint32_t ICOVF : 1; /*!< [7..7] Internal Counter Overflow */ + uint32_t : 24; + } CETSS_b; + }; union { @@ -10569,7 +11059,7 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 24; } BITCNT_b; }; - __IM uint32_t RESERVED29[4]; + __IM uint32_t RESERVED32[4]; union { @@ -10587,7 +11077,7 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure union { - __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */ + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0 */ struct { @@ -10596,7 +11086,7 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 16; } NDBSTLV0_b; }; - __IM uint32_t RESERVED30[9]; + __IM uint32_t RESERVED33[9]; union { @@ -10608,7 +11098,30 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 24; } NRSQSTLV_b; }; - __IM uint32_t RESERVED31[2]; + + union + { + __IM uint32_t HQSTLV; /*!< (@ 0x000003C4) High Priority Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQLV : 8; /*!< [7..0] High Priority Command Queue Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] High Priority Response Queue Level */ + uint32_t : 16; + } HQSTLV_b; + }; + + union + { + __IM uint32_t HDBSTLV; /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] High Priority Tx Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] High Priority Rx Data Buffer Level */ + uint32_t : 16; + } HDBSTLV_b; + }; union { @@ -10634,7 +11147,30 @@ typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure uint32_t : 24; } MSERRCNT_b; }; -} R_I3C0_Type; /*!< Size = 980 (0x3d4) */ + __IM uint32_t RESERVED34[3]; + + union + { + __IM uint32_t SC1CPT; /*!< (@ 0x000003E0) SC1 Capture monitor Register */ + + struct + { + __IM uint32_t SC1C : 16; /*!< [15..0] SC1 Capture */ + uint32_t : 16; + } SC1CPT_b; + }; + + union + { + __IM uint32_t SC2CPT; /*!< (@ 0x000003E4) SC2 Capture monitor Register */ + + struct + { + __IM uint32_t SC2C : 16; /*!< [15..0] SC2 Capture */ + uint32_t : 16; + } SC2CPT_b; + }; +} R_I3C0_Type; /*!< Size = 1000 (0x3e8) */ /* =========================================================================================================================== */ /* ================ R_MPU_MMPU ================ */ @@ -17306,7 +17842,7 @@ typedef struct /*!< (@ 0x40250000) R_USB_FS0 Structure * data. */ uint16_t : 1; __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ } CFIFOCTR_b; }; @@ -17326,7 +17862,7 @@ typedef struct /*!< (@ 0x40250000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D0FIFOSEL_b; }; @@ -17360,7 +17896,7 @@ typedef struct /*!< (@ 0x40250000) R_USB_FS0 Structure __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ } D1FIFOSEL_b; }; @@ -17635,14 +18171,13 @@ typedef struct /*!< (@ 0x40250000) R_USB_FS0 Structure union { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ struct { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; + uint16_t : 15; __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; + } DVCHGR_b; }; union @@ -17655,8 +18190,8 @@ typedef struct /*!< (@ 0x40250000) R_USB_FS0 Structure * the USB address assigned by the host when the USBHS processed * the SET_ADDRESS request successfully. */ uint16_t : 1; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; } USBADDR_b; }; __IM uint16_t RESERVED9; @@ -20227,6 +20762,81 @@ typedef struct /*!< (@ 0x40221000) R_AGTX0 Structure }; } R_AGTX0_Type; /*!< Size = 20 (0x14) */ +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CANFD ECC (R_ECCMB0) + */ + +typedef struct /*!< (@ 0x4036F200) R_ECCMB0 Structure */ +{ + union + { + __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ + + struct + { + __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Message Flag */ + __IM uint32_t ECER1F : 1; /*!< [1..1] ECC Error Detection and Correction Flag */ + __IM uint32_t ECER2F : 1; /*!< [2..2] 2-bit ECC Error Detection Flag */ + __IOM uint32_t EC1EDIC : 1; /*!< [3..3] ECC 1-bit Error Detection Interrupt Control */ + __IOM uint32_t EC2EDIC : 1; /*!< [4..4] ECC 2-bit Error Detection Interrupt Control */ + __IOM uint32_t EC1ECP : 1; /*!< [5..5] ECC 1-bit Error Correction Permission */ + __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Judgment Enable Flag */ + uint32_t : 2; + __IOM uint32_t ECER1C : 1; /*!< [9..9] Accumulating ECC Error Detection and Correction Flag + * Clear */ + __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-bit ECC Error Detection Flag Clear */ + __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Overflow Detection Flag */ + uint32_t : 2; + __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Select bit */ + __IM uint32_t ECSEDF0 : 1; /*!< [16..16] ECC Single bit Error Address Detection Flag */ + __IM uint32_t ECDEDF0 : 1; /*!< [17..17] ECC Dual Bit Error Address Detection Flag */ + uint32_t : 14; + } EC710CTL_b; + }; + + union + { + __IOM uint16_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ + uint16_t : 5; + __IOM uint16_t ECTMCE : 1; /*!< [7..7] ECC Test Mode Control Enable */ + uint16_t : 6; + __IOM uint16_t ETMA : 2; /*!< [15..14] ECC Test Mode Bit Access Control */ + } EC710TMC_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Test Substitute Data Register */ + + struct + { + __IOM uint32_t ECEDB : 32; /*!< [31..0] ECC Test Substitute Data */ + } EC710TED_b; + }; + + union + { + __IM uint32_t EC710EAD0; /*!< (@ 0x00000010) ECC Error Address Register */ + + struct + { + __IM uint32_t ECEAD : 10; /*!< [9..0] ECC Error Address */ + uint32_t : 22; + } EC710EAD0_b; + }; +} R_ECCMB0_Type; /*!< Size = 20 (0x14) */ + /* =========================================================================================================================== */ /* ================ R_FLAD ================ */ /* =========================================================================================================================== */ @@ -20395,7 +21005,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_CANFD1_BASE (0x40382000UL + BASE_NS_OFFSET) #define R_CRC_BASE (0x40310000UL + BASE_NS_OFFSET) #define R_DAC_BASE (0x40333000UL + BASE_NS_OFFSET) - #define R_DAC1_BASE (0x40333100UL + BASE_NS_OFFSET) #define R_DEBUG_BASE (0x4001B000UL + BASE_NS_OFFSET) #define R_DMA_BASE (0x4000A800UL + BASE_NS_OFFSET) #define R_DMAC0_BASE (0x4000A000UL + BASE_NS_OFFSET) @@ -20508,12 +21117,16 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_AGTX7_BASE (0x40221700UL + BASE_NS_OFFSET) #define R_AGTX8_BASE (0x40221800UL + BASE_NS_OFFSET) #define R_AGTX9_BASE (0x40221900UL + BASE_NS_OFFSET) + #define R_ECCMB0_BASE (0x4036F200UL + BASE_NS_OFFSET) + #define R_ECCMB1_BASE (0x4036F300UL + BASE_NS_OFFSET) #define R_FLAD_BASE (0x4011C000UL + BASE_NS_OFFSET) #define R_OFS_DATAFLASH_BASE (0x27030000UL + BASE_NS_OFFSET) #define R_SCI_B5_BASE (0x40358500UL + BASE_NS_OFFSET) #define R_SCI_B6_BASE (0x40358600UL + BASE_NS_OFFSET) #define R_SCI_B7_BASE (0x40358700UL + BASE_NS_OFFSET) #define R_SCI_B8_BASE (0x40358800UL + BASE_NS_OFFSET) + #define R_WDT1_BASE (0x40044300UL + BASE_NS_OFFSET) + #define R_XSPI1_BASE (0x40268400UL + BASE_NS_OFFSET) /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -20541,7 +21154,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_CANFD1 ((R_CANFD_Type *) R_CANFD1_BASE) #define R_CRC ((R_CRC_Type *) R_CRC_BASE) #define R_DAC ((R_DAC_Type *) R_DAC_BASE) - #define R_DAC1 ((R_DAC_Type *) R_DAC1_BASE) #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) #define R_DMA ((R_DMA_Type *) R_DMA_BASE) #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) @@ -20654,12 +21266,16 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_ECCMB0 ((R_ECCMB0_Type *) R_ECCMB0_BASE) + #define R_ECCMB1 ((R_ECCMB0_Type *) R_ECCMB1_BASE) #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) #define R_OFS_DATAFLASH ((R_OFS_DATAFLASH_Type *) R_OFS_DATAFLASH_BASE) #define R_SCI_B5 ((R_SCI_B0_Type *) R_SCI_B5_BASE) #define R_SCI_B6 ((R_SCI_B0_Type *) R_SCI_B6_BASE) #define R_SCI_B7 ((R_SCI_B0_Type *) R_SCI_B7_BASE) #define R_SCI_B8 ((R_SCI_B0_Type *) R_SCI_B8_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) + #define R_XSPI1 ((R_XSPI_Type *) R_XSPI1_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -21848,32 +22464,38 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* =========================================================================================================================== */ /* ======================================================== CMPCTL ========================================================= */ - #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ - #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ - #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ - #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ - #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ - #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ - #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ - #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ - #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ /* ======================================================== CMPSEL0 ======================================================== */ - #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ - #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ /* ======================================================== CMPSEL1 ======================================================== */ - #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ - #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ /* ======================================================== CMPMON ========================================================= */ - #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ - #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ /* ========================================================= CPIOC ========================================================= */ - #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ - #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ - #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ - #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPINTCTL ======================================================== */ + #define R_ACMPHS0_CPINTCTL_MSKE_Pos (0UL) /*!< MSKE (Bit 0) */ + #define R_ACMPHS0_CPINTCTL_MSKE_Msk (0x1UL) /*!< MSKE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPMSKCTL ======================================================== */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Pos (0UL) /*!< MSKSEL (Bit 0) */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Msk (0x7UL) /*!< MSKSEL (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_ADC0 ================ */ @@ -22655,7 +23277,7 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x100UL) /*!< CFXMLT (Bitfield-Mask: 0x01) */ /* ======================================================= CFDRFISTS ======================================================= */ #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ - #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x1UL) /*!< RFXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x3UL) /*!< RFXIF (Bitfield-Mask: 0x03) */ /* ======================================================== CFDTMC ========================================================= */ #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ @@ -22901,9 +23523,14 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ========================================================= DMAST ========================================================= */ #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* ======================================================== DMECHR ========================================================= */ #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ @@ -22913,11 +23540,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -23711,6 +24333,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ @@ -23734,6 +24358,8 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ /* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ @@ -23773,9 +24399,15 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ /* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ @@ -23850,7 +24482,13 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ @@ -23887,8 +24525,6 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -24074,6 +24710,24 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ /* ======================================================== GTSECSR ======================================================== */ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ @@ -24710,6 +25364,14 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HCMDQRST_Pos (9UL) /*!< HCMDQRST (Bit 9) */ + #define R_I3C0_RSTCTL_HCMDQRST_Msk (0x200UL) /*!< HCMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRSPQRST_Pos (10UL) /*!< HRSPQRST (Bit 10) */ + #define R_I3C0_RSTCTL_HRSPQRST_Msk (0x400UL) /*!< HRSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HTDBRST_Pos (11UL) /*!< HTDBRST (Bit 11) */ + #define R_I3C0_RSTCTL_HTDBRST_Msk (0x800UL) /*!< HTDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRDBRST_Pos (12UL) /*!< HRDBRST (Bit 12) */ + #define R_I3C0_RSTCTL_HRDBRST_Msk (0x1000UL) /*!< HRDBRST (Bitfield-Mask: 0x01) */ #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ /* ========================================================= PRSST ========================================================= */ @@ -24766,7 +25428,7 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ - #define R_I3C0_SVCTL_SVAEn_Msk (0x10000UL) /*!< SVAEn (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_SVAEn_Msk (0x70000UL) /*!< SVAEn (Bitfield-Mask: 0x07) */ /* ======================================================= REFCKCTL ======================================================== */ #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ @@ -24861,6 +25523,24 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================== SVTDLG0 ======================================================== */ #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= STCTL ========================================================= */ + #define R_I3C0_STCTL_STOE_Pos (0UL) /*!< STOE (Bit 0) */ + #define R_I3C0_STCTL_STOE_Msk (0x1UL) /*!< STOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ATCTL ========================================================= */ + #define R_I3C0_ATCTL_ATTRGS_Pos (0UL) /*!< ATTRGS (Bit 0) */ + #define R_I3C0_ATCTL_ATTRGS_Msk (0x1UL) /*!< ATTRGS (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_MREFOE_Pos (1UL) /*!< MREFOE (Bit 1) */ + #define R_I3C0_ATCTL_MREFOE_Msk (0x2UL) /*!< MREFOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_AMEOE_Pos (2UL) /*!< AMEOE (Bit 2) */ + #define R_I3C0_ATCTL_AMEOE_Msk (0x4UL) /*!< AMEOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_CDIV_Pos (8UL) /*!< CDIV (Bit 8) */ + #define R_I3C0_ATCTL_CDIV_Msk (0xff00UL) /*!< CDIV (Bitfield-Mask: 0xff) */ +/* ========================================================= ATTRG ========================================================= */ + #define R_I3C0_ATTRG_ATSTRG_Pos (0UL) /*!< ATSTRG (Bit 0) */ + #define R_I3C0_ATTRG_ATSTRG_Msk (0x1UL) /*!< ATSTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== ATCCNTE ======================================================== */ + #define R_I3C0_ATCCNTE_ATCE_Pos (0UL) /*!< ATCE (Bit 0) */ + #define R_I3C0_ATCCNTE_ATCE_Msk (0x1UL) /*!< ATCE (Bitfield-Mask: 0x01) */ /* ======================================================== CNDCTL ========================================================= */ #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ @@ -24873,6 +25553,15 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================== NTDTBP0 ======================================================== */ /* ======================================================== NIBIQP ========================================================= */ /* ========================================================= NRSQP ========================================================= */ +/* ======================================================== HCMDQP ========================================================= */ + #define R_I3C0_HCMDQP_HCMDQP_Pos (0UL) /*!< HCMDQP (Bit 0) */ + #define R_I3C0_HCMDQP_HCMDQP_Msk (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HRSPQP ========================================================= */ + #define R_I3C0_HRSPQP_HRSPQP_Pos (0UL) /*!< HRSPQP (Bit 0) */ + #define R_I3C0_HRSPQP_HRSPQP_Msk (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HTDTBP ========================================================= */ + #define R_I3C0_HTDTBP_HTDTBP_Pos (0UL) /*!< HTDTBP (Bit 0) */ + #define R_I3C0_HTDTBP_HTDTBP_Msk (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff) */ /* ======================================================== NQTHCTL ======================================================== */ #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ @@ -24894,6 +25583,20 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================= NRQTHCTL ======================================================== */ #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ +/* ======================================================== HQTHCTL ======================================================== */ + #define R_I3C0_HQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_HQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_HQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= HTBTHCTL ======================================================== */ + #define R_I3C0_HTBTHCTL_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_HTBTHCTL_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ /* ========================================================== BST ========================================================== */ #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ @@ -25030,6 +25733,58 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ +/* ========================================================= HTST ========================================================== */ + #define R_I3C0_HTST_TDBEF_Pos (0UL) /*!< TDBEF (Bit 0) */ + #define R_I3C0_HTST_TDBEF_Msk (0x1UL) /*!< TDBEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RDBFF_Pos (1UL) /*!< RDBFF (Bit 1) */ + #define R_I3C0_HTST_RDBFF_Msk (0x2UL) /*!< RDBFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_HTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_HTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_HTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_HTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ +/* ========================================================= HTSTE ========================================================= */ + #define R_I3C0_HTSTE_TDBEE_Pos (0UL) /*!< TDBEE (Bit 0) */ + #define R_I3C0_HTSTE_TDBEE_Msk (0x1UL) /*!< TDBEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RDBFE_Pos (1UL) /*!< RDBFE (Bit 1) */ + #define R_I3C0_HTSTE_RDBFE_Msk (0x2UL) /*!< RDBFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_HTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_HTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_HTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_HTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ +/* ========================================================= HTIE ========================================================== */ + #define R_I3C0_HTIE_TDBEIE_Pos (0UL) /*!< TDBEIE (Bit 0) */ + #define R_I3C0_HTIE_TDBEIE_Msk (0x1UL) /*!< TDBEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RDBFIE_Pos (1UL) /*!< RDBFIE (Bit 1) */ + #define R_I3C0_HTIE_RDBFIE_Msk (0x2UL) /*!< RDBFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_HTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_HTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_HTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_HTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== HTSTFC ========================================================= */ + #define R_I3C0_HTSTFC_TDBEFC_Pos (0UL) /*!< TDBEFC (Bit 0) */ + #define R_I3C0_HTSTFC_TDBEFC_Msk (0x1UL) /*!< TDBEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RDBFFC_Pos (1UL) /*!< RDBFFC (Bit 1) */ + #define R_I3C0_HTSTFC_RDBFFC_Msk (0x2UL) /*!< RDBFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_HTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_HTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_HTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_HTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ /* ========================================================= BCST ========================================================== */ #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ @@ -25047,10 +25802,13 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ - #define R_I3C0_SVST_SVAFn_Msk (0x10000UL) /*!< SVAFn (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_SVAFn_Msk (0x70000UL) /*!< SVAFn (Bitfield-Mask: 0x07) */ /* ========================================================= WUST ========================================================== */ #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCCPT ========================================================= */ + #define R_I3C0_MRCCPT_MRCCPT_Pos (0UL) /*!< MRCCPT (Bit 0) */ + #define R_I3C0_MRCCPT_MRCCPT_Msk (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff) */ /* ======================================================== DATBAS0 ======================================================== */ #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ @@ -25119,6 +25877,74 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS4 ======================================================== */ + #define R_I3C0_DATBAS4_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS4_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS4_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS4_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS4_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS4_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS4_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS4_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS4_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS4_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS4_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS5 ======================================================== */ + #define R_I3C0_DATBAS5_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS5_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS5_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS5_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS5_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS5_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS5_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS5_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS5_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS5_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS5_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS6 ======================================================== */ + #define R_I3C0_DATBAS6_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS6_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS6_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS6_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS6_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS6_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS6_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS6_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS6_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS6_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS6_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS7 ======================================================== */ + #define R_I3C0_DATBAS7_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS7_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS7_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS7_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS7_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS7_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS7_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS7_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS7_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS7_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS7_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ /* ======================================================= EXDATBAS ======================================================== */ #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ @@ -25215,6 +26041,66 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT4 ========================================================= */ + #define R_I3C0_MSDCT4_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT4_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT4_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT4_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT4_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT4_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT4_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT4_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT5 ========================================================= */ + #define R_I3C0_MSDCT5_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT5_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT5_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT5_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT5_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT5_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT5_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT5_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT6 ========================================================= */ + #define R_I3C0_MSDCT6_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT6_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT6_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT6_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT6_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT6_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT6_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT6_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT7 ========================================================= */ + #define R_I3C0_MSDCT7_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT7_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT7_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT7_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT7_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT7_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT7_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT7_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ /* ========================================================= SVDCT ========================================================= */ #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ @@ -25243,6 +26129,24 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD1 ======================================================== */ + #define R_I3C0_SVDVAD1_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD1_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD1_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD1_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD1_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD1_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD2 ======================================================== */ + #define R_I3C0_SVDVAD2_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD2_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD2_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD2_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD2_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD2_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ /* ======================================================== CSECMD ========================================================= */ #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ @@ -25287,10 +26191,23 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ /* ========================================================= CETSM ========================================================= */ + #define R_I3C0_CETSM_SPTSYN_Pos (0UL) /*!< SPTSYN (Bit 0) */ + #define R_I3C0_CETSM_SPTSYN_Msk (0x1UL) /*!< SPTSYN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN0_Pos (1UL) /*!< SPTASYN0 (Bit 1) */ + #define R_I3C0_CETSM_SPTASYN0_Msk (0x2UL) /*!< SPTASYN0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN1_Pos (2UL) /*!< SPTASYN1 (Bit 2) */ + #define R_I3C0_CETSM_SPTASYN1_Msk (0x4UL) /*!< SPTASYN1 (Bitfield-Mask: 0x01) */ #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ========================================================= CETSS ========================================================= */ + #define R_I3C0_CETSS_SYNE_Pos (0UL) /*!< SYNE (Bit 0) */ + #define R_I3C0_CETSS_SYNE_Msk (0x1UL) /*!< SYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSS_ASYNE_Pos (1UL) /*!< ASYNE (Bit 1) */ + #define R_I3C0_CETSS_ASYNE_Msk (0x6UL) /*!< ASYNE (Bitfield-Mask: 0x03) */ + #define R_I3C0_CETSS_ICOVF_Pos (7UL) /*!< ICOVF (Bit 7) */ + #define R_I3C0_CETSS_ICOVF_Msk (0x80UL) /*!< ICOVF (Bitfield-Mask: 0x01) */ /* ======================================================= CGHDRCAP ======================================================== */ #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ @@ -25320,6 +26237,16 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================= NRSQSTLV ======================================================== */ #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HQSTLV ========================================================= */ + #define R_I3C0_HQSTLV_CMDQLV_Pos (0UL) /*!< CMDQLV (Bit 0) */ + #define R_I3C0_HQSTLV_CMDQLV_Msk (0xffUL) /*!< CMDQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_HQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HDBSTLV ======================================================== */ + #define R_I3C0_HDBSTLV_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_HDBSTLV_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HDBSTLV_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_HDBSTLV_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ /* ======================================================== PRSTDBG ======================================================== */ #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ @@ -25332,6 +26259,12 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ======================================================= MSERRCNT ======================================================== */ #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ +/* ======================================================== SC1CPT ========================================================= */ + #define R_I3C0_SC1CPT_SC1C_Pos (0UL) /*!< SC1C (Bit 0) */ + #define R_I3C0_SC1CPT_SC1C_Msk (0xffffUL) /*!< SC1C (Bitfield-Mask: 0xffff) */ +/* ======================================================== SC2CPT ========================================================= */ + #define R_I3C0_SC2CPT_SC2C_Pos (0UL) /*!< SC2C (Bit 0) */ + #define R_I3C0_SC2CPT_SC2C_Msk (0xffffUL) /*!< SC2C (Bitfield-Mask: 0xffff) */ /* =========================================================================================================================== */ /* ================ R_MPU_MMPU ================ */ @@ -28228,14 +29161,12 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== UFRMNUM ======================================================== */ - #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ - #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ /* ======================================================== USBADDR ======================================================== */ #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ /* ======================================================== USBREQ ========================================================= */ @@ -29746,6 +30677,51 @@ typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Struc /* ================ R_AGTX0 ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= EC710CTL ======================================================== */ + #define R_ECCMB0_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ + #define R_ECCMB0_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ + #define R_ECCMB0_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ + #define R_ECCMB0_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ + #define R_ECCMB0_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ + #define R_ECCMB0_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ + #define R_ECCMB0_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ + #define R_ECCMB0_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Pos (16UL) /*!< ECSEDF0 (Bit 16) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Msk (0x10000UL) /*!< ECSEDF0 (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Pos (17UL) /*!< ECDEDF0 (Bit 17) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Msk (0x20000UL) /*!< ECDEDF0 (Bitfield-Mask: 0x01) */ +/* ======================================================= EC710TMC ======================================================== */ + #define R_ECCMB0_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ + #define R_ECCMB0_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ + #define R_ECCMB0_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ +/* ======================================================= EC710TED ======================================================== */ + #define R_ECCMB0_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ + #define R_ECCMB0_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EC710EAD0 ======================================================= */ + #define R_ECCMB0_EC710EAD0_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ + #define R_ECCMB0_EC710EAD0_ECEAD_Msk (0x3ffUL) /*!< ECEAD (Bitfield-Mask: 0x3ff) */ + /* =========================================================================================================================== */ /* ================ R_FLAD ================ */ /* =========================================================================================================================== */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c index 283173aaa..807117bf3 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c @@ -524,7 +524,7 @@ void SystemInit (void) } #endif -#if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS && !BSP_CFG_SKIP_INIT +#if BSP_FEATURE_CGC_HAS_EXTRACLK2 && !BSP_CFG_SKIP_INIT bsp_internal_prv_enable_extra_power_domain(); #endif diff --git a/ra/fsp/src/bsp/mcu/all/bsp_clocks.c b/ra/fsp/src/bsp/mcu/all/bsp_clocks.c index 5f42b4f5c..75481405f 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_clocks.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_clocks.c @@ -156,73 +156,78 @@ /* Choose the value to write to FLLCR2 (if applicable). */ #if BSP_PRV_HOCO_USE_FLL #if 1U == BSP_CFG_HOCO_FREQUENCY - #define BSP_PRV_FLL_FLLCR2 (0x226U) + #define BSP_PRV_FLL_FLLCR2 (0x226U) #elif 2U == BSP_CFG_HOCO_FREQUENCY - #define BSP_PRV_FLL_FLLCR2 (0x263U) + #define BSP_PRV_FLL_FLLCR2 (0x263U) #elif 4U == BSP_CFG_HOCO_FREQUENCY - #define BSP_PRV_FLL_FLLCR2 (0x263U) + #define BSP_PRV_FLL_FLLCR2 (0x263U) #else /* When BSP_CFG_HOCO_FREQUENCY is 0, 4, 7 */ - #define BSP_PRV_FLL_FLLCR2 (0x1E9U) + #define BSP_PRV_FLL_FLLCR2 (0x1E9U) #endif #endif /* Calculate the value to write to SCKDIVCR. */ -#define BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS ((BSP_CFG_ICLK_DIV & 0xFU) << 24U) +#define BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS ((BSP_CFG_ICLK_DIV & 0xFU) << 24U) #if BSP_FEATURE_CGC_HAS_PCLKE - #define BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS ((BSP_CFG_PCLKE_DIV & 0xFU) << 20U) + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS ((BSP_CFG_PCLKE_DIV & 0xFU) << 20U) #else - #define BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS (0U) + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS (0U) #endif #if BSP_FEATURE_CGC_HAS_PCLKD - #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (BSP_CFG_PCLKD_DIV & 0xFU) + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (BSP_CFG_PCLKD_DIV & 0xFU) #else - #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (0U) + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (0U) #endif #if BSP_FEATURE_CGC_HAS_PCLKC - #define BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS ((BSP_CFG_PCLKC_DIV & 0xFU) << 4U) + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS ((BSP_CFG_PCLKC_DIV & 0xFU) << 4U) #else - #define BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS (0U) + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS (0U) #endif #if BSP_FEATURE_CGC_HAS_PCLKB - #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 8U) + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 8U) #else - #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS (0U) + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS (0U) #endif #if BSP_FEATURE_CGC_HAS_PCLKA - #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS ((BSP_CFG_PCLKA_DIV & 0xFU) << 12U) + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS ((BSP_CFG_PCLKA_DIV & 0xFU) << 12U) #else - #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS (0U) + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS (0U) #endif #if BSP_FEATURE_CGC_HAS_BCLK - #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_BCLK_DIV & 0xFU) << 16U) + #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_BCLK_DIV & 0xFU) << 16U) #elif BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB /* Some MCUs have a requirement that bits 18-16 be set to the same value as the bits for configuring the PCLKB divisor. */ - #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 16U) + #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 16U) #else - #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS (0U) + #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS (0U) #endif #if BSP_FEATURE_CGC_HAS_FCLK - #define BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS ((BSP_CFG_FCLK_DIV & 0xFU) << 28U) + #define BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS ((BSP_CFG_FCLK_DIV & 0xFU) << 28U) #else - #define BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS (0U) -#endif -#define BSP_PRV_STARTUP_SCKDIVCR (BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS | \ - BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS | \ - BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS | \ - BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS | \ - BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS | \ - BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS | \ - BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS | \ - BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS) + #define BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS (0U) +#endif +#define BSP_PRV_STARTUP_SCKDIVCR (BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS) #if BSP_FEATURE_CGC_HAS_CPUCLK - #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS (BSP_CFG_CPUCLK_DIV & 0xFU) + #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS (BSP_CFG_CPUCLK_DIV & 0xFU) #else - #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS (0) + #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS (0) #endif #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + +/* Set extraclk2 to the same value as extraclk3 if the MCU does not support extraclk2. */ + #if (BSP_FEATURE_CGC_HAS_EXTRACLK2 == 0) + #define BSP_CFG_EXTRACLK2_DIV (BSP_CFG_EXTRACLK3_DIV) + #endif #define BSP_PRV_STARTUP_SCKDIVCR2_EXTRACK1_BITS ((BSP_CFG_EXTRACLK1_DIV & 0xFU) << 4U) #define BSP_PRV_STARTUP_SCKDIVCR2_EXTRACK2_BITS ((BSP_CFG_EXTRACLK2_DIV & 0xFU) << 8U) #define BSP_PRV_STARTUP_SCKDIVCR2_EXTRACK3_BITS ((BSP_CFG_EXTRACLK3_DIV & 0xFU) << 12U) @@ -437,7 +442,7 @@ #define BSP_PRV_MAIN_OSC_USED (1) #elif defined(BSP_CFG_SDADC_CLOCK_SOURCE) && (BSP_CFG_SDADC_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) #define BSP_PRV_MAIN_OSC_USED (1) -#elif defined(BSP_CFG_UARTA_CLOCK_SOURCE) && (BSP_CFG_UARTA_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) +#elif defined(BSP_CFG_UARTA0_CLOCK_SOURCE) && (BSP_CFG_UARTA0_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) #define BSP_PRV_MAIN_OSC_USED (1) #elif defined(BSP_CFG_UARTA1_CLOCK_SOURCE) && (BSP_CFG_UARTA1_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) #define BSP_PRV_MAIN_OSC_USED (1) @@ -484,7 +489,7 @@ #define BSP_PRV_HOCO_USED (1) #elif defined(BSP_CFG_SDADC_CLOCK_SOURCE) && (BSP_CFG_SDADC_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_HOCO) #define BSP_PRV_HOCO_USED (1) -#elif defined(BSP_CFG_UARTA_CLOCK_SOURCE) && (BSP_CFG_UARTA_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_HOCO) +#elif defined(BSP_CFG_UARTA0_CLOCK_SOURCE) && (BSP_CFG_UARTA0_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_HOCO) #define BSP_PRV_HOCO_USED (1) #elif defined(BSP_CFG_UARTA1_CLOCK_SOURCE) && (BSP_CFG_UARTA1_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_HOCO) #define BSP_PRV_HOCO_USED (1) @@ -525,7 +530,7 @@ #define BSP_PRV_MOCO_USED (1) #elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) #define BSP_PRV_MOCO_USED (1) -#elif defined(BSP_CFG_UARTA_CLOCK_SOURCE) && (BSP_CFG_UARTA_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) +#elif defined(BSP_CFG_UARTA0_CLOCK_SOURCE) && (BSP_CFG_UARTA0_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) #define BSP_PRV_MOCO_USED (1) #elif defined(BSP_CFG_UARTA1_CLOCK_SOURCE) && (BSP_CFG_UARTA1_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) #define BSP_PRV_MOCO_USED (1) @@ -557,10 +562,10 @@ #define BSP_PRV_LOCO_USED (1) #elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) #define BSP_PRV_LOCO_USED (1) -#elif (defined(BSP_CFG_UARTA_CLOCK_SOURCE) && (BSP_CFG_UARTA_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_FSXP)) && \ +#elif (defined(BSP_CFG_UARTA0_CLOCK_SOURCE) && (BSP_CFG_UARTA0_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_FSXP)) && \ (defined(BSP_CFG_FSXP_SOURCE) && (BSP_CFG_FSXP_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)) #define BSP_PRV_LOCO_USED (1) -#elif defined(BSP_CFG_UARTA_CLOCK_SOURCE) && (BSP_CFG_UARTA_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) +#elif defined(BSP_CFG_UARTA0_CLOCK_SOURCE) && (BSP_CFG_UARTA0_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) #define BSP_PRV_LOCO_USED (1) #elif defined(BSP_CFG_UARTA1_CLOCK_SOURCE) && (BSP_CFG_UARTA1_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) #define BSP_PRV_LOCO_USED (1) diff --git a/ra/fsp/src/bsp/mcu/all/bsp_clocks.h b/ra/fsp/src/bsp/mcu/all/bsp_clocks.h index 0c750cfd6..1a5d36a5d 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_clocks.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_clocks.h @@ -74,7 +74,6 @@ FSP_HEADER (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ (4U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ (5U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ - (6U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ !BSP_CLOCK_CFG_MAIN_OSC_POPULATED) #define BSP_PRV_PLL_SUPPORTED (1) #if BSP_FEATURE_CGC_HAS_PLL2 diff --git a/ra/fsp/src/bsp/mcu/all/bsp_irq.c b/ra/fsp/src/bsp/mcu/all/bsp_irq.c index a4ca62a48..e103d01ba 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_irq.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_irq.c @@ -109,7 +109,7 @@ BSP_SECTION_FLASH_GAP void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, /* The following statement is used in place of NVIC_SetPriority to avoid including a branch for system exceptions * every time a priority is configured in the NVIC. */ #if (4U == __CORTEX_M) - NVIC->IP[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); + NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); #elif (33 == __CORTEX_M) NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); #elif (23 == __CORTEX_M) diff --git a/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h b/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h index 9e092a4d8..947e78721 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h @@ -74,8 +74,12 @@ FSP_HEADER #if 0U == BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH >= \ + #if !BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 6U) + #else + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH >= \ channel) ? (1U << 5U) : (1U << 6U)); + #endif #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRD #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); @@ -91,15 +95,16 @@ FSP_HEADER * Ch 4-5: MSTPD[ 1: 0] (AGT2, AGT3) * Ch 6-9: MSTPD[10: 7] (AGT4, AGT5, AGT6, AGT7) */ - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << \ - ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ - ? (3U - channel) \ - : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 2U) \ - ? (19U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ - : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 4U) \ - ? (1U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + \ - 2U) \ - : (10U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + \ + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << \ + ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ + ? (3U - channel) \ + : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 2U) \ + ? (19U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ + : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 4U) \ + ? (1U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + \ + 2U) \ + : (10U - channel + \ + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + \ 4U))))); #else @@ -108,7 +113,11 @@ FSP_HEADER #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U)); + #if BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); + #else + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U)); + #endif #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t #else #if (2U == BSP_FEATURE_ELC_VERSION) @@ -124,7 +133,8 @@ FSP_HEADER #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t #elif BSP_MCU_GROUP_NEPTUNE #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - ((channel >= 4U && channel <= 9U) ? 4U : channel))) // GPT Channels 4-9 share stop bits on this MCU + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << \ + (31 - ((channel >= 4U && channel <= 9U) ? 4U : channel))) // GPT Channels 4-9 share stop bits on this MCU #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRD #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (6U)); @@ -160,9 +170,10 @@ FSP_HEADER #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t #define BSP_MSTP_REG_FSP_IP_AGT(channel) *((3U >= channel) ? &R_MSTP->MSTPCRD : &R_MSTP->MSTPCRE) - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) ((3U >= \ - channel) ? (1U << (3U - channel)) : (1U << \ - (15U - (channel - 4U)))); + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) ((3U >= \ + channel) ? (1U << (3U - channel)) : (1U << \ + (15U - \ + (channel - 4U)))); #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel)); @@ -229,11 +240,7 @@ FSP_HEADER #define BSP_MSTP_BIT_FSP_IP_ETHER(channel) (1U << (15U - channel)); #define BSP_MSTP_REG_TYPE_FSP_IP_ETHER(channel) uint32_t #define BSP_MSTP_REG_FSP_IP_UARTA(channel) R_MSTP->MSTPCRB -#if BSP_FEATURE_CGC_REGISTER_SET_B - #define BSP_MSTP_BIT_FSP_IP_UARTA(channel) (1U << (15U)); -#else - #define BSP_MSTP_BIT_FSP_IP_UARTA(channel) (1U << (0U)); -#endif +#define BSP_MSTP_BIT_FSP_IP_UARTA(channel) (1U << BSP_FEATURE_UARTA_MSTP_OFFSET); #define BSP_MSTP_REG_TYPE_FSP_IP_UARTA(channel) uint32_t #define BSP_MSTP_REG_FSP_IP_OSPI(channel) R_MSTP->MSTPCRB #define BSP_MSTP_BIT_FSP_IP_OSPI(channel) (1U << (16U - channel)); diff --git a/ra/fsp/src/bsp/mcu/ra0e1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra0e1/bsp_feature.h index 3d47f1c08..870177388 100644 --- a/ra/fsp/src/bsp/mcu/ra0e1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra0e1/bsp_feature.h @@ -75,6 +75,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x00) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_FLASH_CACHE (0) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) @@ -82,9 +83,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (1) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -111,8 +112,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x000FFFFFU) +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_NUM_PMSAR (0U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) @@ -143,12 +146,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (0U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLL (0U) #define BSP_FEATURE_CGC_HAS_FLWT (0U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (0U) #define BSP_FEATURE_CGC_HAS_PCLKB (0U) #define BSP_FEATURE_CGC_HAS_PCLKC (0U) @@ -172,49 +177,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (1U) #define BSP_FEATURE_CGC_MODRV_MASK (0x01U) #define BSP_FEATURE_CGC_MODRV_SHIFT (0x0U) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (0U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_TYPE (0U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (0U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // This MCU does not have PLL +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_REGISTER_SET_B (1) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) #define BSP_FEATURE_CGC_SODRV_MASK (0x06U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x1U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (0) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (1) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0) // Feature not available on this MCU -#define BSP_FEATURE_CRC_HAS_SNOOP (0U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U) // Don't care #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (0) +#define BSP_FEATURE_CRC_HAS_SNOOP (0U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x18U) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U) // Don't care +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) #define BSP_FEATURE_CRYPTO_HAS_AES (0) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) #define BSP_FEATURE_CRYPTO_HAS_ECC (0) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) #define BSP_FEATURE_CRYPTO_HAS_HASH (0) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (0) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) @@ -249,28 +255,28 @@ #define BSP_FEATURE_DWT_CYCCNT (0U) -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x1F800000U) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (1U) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_CODE_FLASH_START (0x0U) #define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) -#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (0) -#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0x7FFU) #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (11) #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x800U) +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (4) #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x100U) #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) @@ -289,21 +295,22 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (0U) #define BSP_FEATURE_ICU_HAS_IELSR (0U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (0) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x3FU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (8U) // Max used index in NMIER -#define BSP_FEATURE_ICU_WUPEN_MASK (0x00000000U) -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_SBYEDCR_MASK (0x3838C1404FFULL) +#define BSP_FEATURE_ICU_WUPEN_MASK (0x00000000U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU @@ -313,7 +320,6 @@ #define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_IOPORT_ELC_PORTS (0x0006U) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) #define BSP_FEATURE_IOPORT_VERSION (3U) // The RA0 family IOPORT periphral #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (16384UL) @@ -330,6 +336,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (1) +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (1) #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -338,64 +346,69 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_STCONR (0) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (1) #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (1) -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (1) +#define BSP_FEATURE_LPM_HAS_STCONR (0) // Feature not available on this MCU #define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (1) #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0U) #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (1) +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (0) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_4_08V) // 4.08V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_63V) // 1.63V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // LVD1 operation stabilization time after LVD1 is enabled (TBD for RA0E1) #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (0) // Feature not available on this MCU -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // LVD1 operation stabilization time after LVD1 is enabled (TBD for RA0E1) #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (0U) // Feature not available on this MCU #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (2U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU + +#define BSP_FEATURE_MACL_SUPPORTED (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_BASE_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (4U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (100U) // This information comes from the Electrical Characteristics chapter of the hardware manual. #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (10U) #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) -#define BSP_FEATURE_POEG_CHANNEL_MASK (0x0U) // Feature not available on this MCU +#define BSP_FEATURE_POEG_CHANNEL_MASK (0x0U) // Feature not available on this MCU #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0U) #define BSP_FEATURE_RTC_HAS_TCEN (0U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (0U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (7U) #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) #define BSP_FEATURE_SCI_CHANNELS (0x0U) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKB) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x0U) +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x0U) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (0U) #define BSP_FEATURE_SCI_VERSION (0U) -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU @@ -405,12 +418,12 @@ #define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SPI_HAS_SPCR3 (0) // Feature not available on this MCU @@ -423,35 +436,43 @@ #define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0) // Feature not available on this MCU #define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TAU_CLOCK_SOURCE (FSP_PRIV_CLOCK_ICLK) +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) + #define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0x00FF) +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU + #define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (TIMER_SOURCE_DIV_128) #define BSP_FEATURE_TML_NUM_CHANNELS (4) #define BSP_FEATURE_TML_VALID_CHANNEL_MASK ((1 << BSP_FEATURE_TML_NUM_CHANNELS) - 1) -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU - #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (1U) -#define BSP_FEATURE_TZ_NS_OFFSET (0U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0) // Feature not available on this MCU + #define BSP_FEATURE_TZ_HAS_DLM (0) // Feature not available on this MCU +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0) // Feature not available on this MCU +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_VERSION (0U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0x0FU) +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (0) // Feature not available on this MCU +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) #define BSP_FEATURE_USB_HAS_USBHS (0U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module #endif diff --git a/ra/fsp/src/bsp/mcu/ra0e1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra0e1/bsp_feature_gen.h index 57320ed0c..28ebb799e 100644 --- a/ra/fsp/src/bsp/mcu/ra0e1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra0e1/bsp_feature_gen.h @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0x1) #define BSP_PERIPHERAL_UARTA_PRESENT (1) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (1) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra0e1/bsp_override.h b/ra/fsp/src/bsp/mcu/ra0e1/bsp_override.h index d6a245113..4dee3cae6 100644 --- a/ra/fsp/src/bsp/mcu/ra0e1/bsp_override.h +++ b/ra/fsp/src/bsp/mcu/ra0e1/bsp_override.h @@ -38,7 +38,6 @@ #define BSP_OVERRIDE_TIMER_MODE_T #define BSP_OVERRIDE_TIMER_SOURCE_DIV_T #define BSP_OVERRIDE_UART_DATA_BITS_T -#define BSP_OVERRIDE_UART_DATA_BITS_T /*********************************************************************************************************************** * Typedef definitions diff --git a/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h index 8014ae1df..e27c09ff8 100644 --- a/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h @@ -75,6 +75,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) @@ -82,9 +83,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -111,8 +112,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x407FB19C) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x000FFFFFU) +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (1) #define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (0U) +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_NUM_PMSAR (0U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) @@ -145,12 +148,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLL (0U) #define BSP_FEATURE_CGC_HAS_FLWT (0U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (1U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (0U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (0U) @@ -174,50 +179,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (1U) #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV1_Msk) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV1_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (0U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (0U) // Feature not available on this MCU - #define BSP_FEATURE_CGC_PLLCCR_TYPE (0U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (0U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // This MCU does not have PLL +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x03U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (2) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x44000404) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (1U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (1U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (1) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) #define BSP_FEATURE_CRYPTO_HAS_ECC (0) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) #define BSP_FEATURE_CRYPTO_HAS_HASH (0) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (0) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (1) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) @@ -252,28 +257,28 @@ #define BSP_FEATURE_DWT_CYCCNT (0U) -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x005CD30FU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (1U) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_CODE_FLASH_START (0x0U) #define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) -#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (0) -#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0xFFFU) #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (10) #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x800U) +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (8) #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) @@ -292,31 +297,31 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0xFB8F00FFU) -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) -#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU -#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_IIC_FAST_MODE_PLUS (0U) #define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x03) -#define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_IOPORT_ELC_PORTS (0x0006U) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) #define BSP_FEATURE_IOPORT_VERSION (1U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) @@ -333,6 +338,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -341,41 +348,43 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) -#define BSP_FEATURE_LPM_HAS_STCONR (0U) -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_STCONR (0U) #define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x738200FFU) #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (300U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_MACL_SUPPORTED (0U) #define BSP_FEATURE_OPAMP_BASE_ADDRESS (2U) #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (1U) #define BSP_FEATURE_OPAMP_HAS_SWITCHES (1U) -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (4U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (220U) // This information comes from the Electrical Characteristics chapter of the hardware manual. #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (10U) #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (1U) #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0x7U) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) @@ -383,40 +392,40 @@ #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0U) #define BSP_FEATURE_RTC_HAS_TCEN (0U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (0U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) #define BSP_FEATURE_SCI_CHANNELS (0x203U) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKB) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x0U) +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x1U) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) -#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) @@ -424,41 +433,48 @@ #define BSP_FEATURE_SPI_MAX_CHANNEL (2U) #define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x0U) -#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0) // Feature not available on this MCU +#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0) // Feature not available on this MCU -#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0) // Feature not available on this MCU -#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0) // Feature not available on this MCU +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) + +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (1U) -#define BSP_FEATURE_TZ_NS_OFFSET (0U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) + #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_VERSION (0U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (1U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (1U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) #define BSP_FEATURE_USB_HAS_USBHS (0U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (1U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (1U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (1U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (1U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (1U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module -#define BSP_FEATURE_USB_HAS_NOT_HOST (1U) #endif diff --git a/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature_gen.h index 7210f1ef2..af1176d13 100644 --- a/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature_gen.h @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra2a2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2a2/bsp_feature.h index c4b695418..5e174870f 100644 --- a/ra/fsp/src/bsp/mcu/ra2a2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2a2/bsp_feature.h @@ -75,15 +75,17 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (1) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0xFF) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_FLASH_CACHE (0) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (1) #define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (1U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -102,16 +104,18 @@ #define BSP_FEATURE_BSP_HAS_SP_MON (1U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) // On the RA6M4 there is a request bit that must be set before changing USB clock settings. #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x000FFFFFU) +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (0) #define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (3U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (0U) +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_NUM_PMSAR (0U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) @@ -142,12 +146,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (0U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (1U) #define BSP_FEATURE_CGC_HAS_FLL (0U) #define BSP_FEATURE_CGC_HAS_FLWT (0U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (1U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (1) #define BSP_FEATURE_CGC_HAS_PCLKA (0U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (0U) @@ -160,9 +166,9 @@ #define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_SRAMWTSC (0U) #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (1U) -#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) -#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) #define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_16) #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (100U) #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (2000000U) // This MCU does have Low Speed Mode, up to 2 MHz @@ -171,49 +177,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (1U) #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV1_Msk) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV1_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (0U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (12795904U) -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (11993088U) -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (32768U) -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (32768U) #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_TYPE (4U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (13000000U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (12795904U) +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (11993088U) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (32768U) +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (32768U) #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) #define BSP_FEATURE_CGC_SODRV_MASK (0x03U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (1) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (1) -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x04000404) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (1U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (1U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (2) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) #define BSP_FEATURE_CRYPTO_HAS_ECC (0) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) #define BSP_FEATURE_CRYPTO_HAS_HASH (0) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (0) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (2) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) @@ -229,6 +236,7 @@ #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU #define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) #define BSP_FEATURE_DAC_HAS_DAVREFCR (1U) #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U) @@ -247,28 +255,28 @@ #define BSP_FEATURE_DWT_CYCCNT (0U) -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0000C30FU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (1U) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_CODE_FLASH_START (0x0U) #define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) -#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (0) -#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0x7FFU) #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (11) #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x800U) +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0x00040000U) #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (4) #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) @@ -287,21 +295,22 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (36U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (1U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0x1FFFBFD0FFFULL) // Note there is another WUPEN1 register -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (36U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU @@ -311,7 +320,6 @@ #define BSP_FEATURE_IIC_VERSION (1) #define BSP_FEATURE_IOPORT_ELC_PORTS (0x0006U) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) #define BSP_FEATURE_IOPORT_VERSION (1U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) @@ -328,6 +336,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -336,44 +346,43 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) -#define BSP_FEATURE_LPM_HAS_STCONR (0U) -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_STCONR (0U) #define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (1U) -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x73800FFFU) #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (500U) // Time in microseconds required for EXLVD to stabilize #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (1U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (1200U) // LVD2 operation stabilization time after LVD2 is enabled -#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (500U) // Time in microseconds required for LVD VBAT to stabilize -#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (500U) // Time in microseconds required for LVD VRTC to stabilize -#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (500U) // Time in microseconds required for EXLVD to stabilize #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (500U) // Time in microseconds required for LVD VBAT to stabilize #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (500U) // Time in microseconds required for LVD VRTC to stabilize #define BSP_FEATURE_MACL_SUPPORTED (1U) -#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0U) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0U) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0U) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0U) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) // Feature not available on this MCU - +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0U) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0U) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0U) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0U) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) // Feature not available on this MCU + +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) @@ -381,40 +390,40 @@ #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) -#define BSP_FEATURE_RTC_IS_IRTC (1U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0U) #define BSP_FEATURE_RTC_HAS_TCEN (1U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (1U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (3U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) #define BSP_FEATURE_SCI_CHANNELS (0x20FU) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKB) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x0U) +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x1U) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) -#define BSP_FEATURE_SDHI_CLOCK (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_SDRAM_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (22U) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (9U) #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (1U) #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (1U) -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (44U) #define BSP_FEATURE_SLCDC_HAS_VL1SEL (1U) -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (9U) -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (22U) +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (44U) #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) @@ -422,40 +431,48 @@ #define BSP_FEATURE_SPI_MAX_CHANNEL (2U) #define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x0U) -#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0) // Feature not available on this MCU +#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0) // Feature not available on this MCU + +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0) // Feature not available on this MCU +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0) // Feature not available on this MCU -#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (1U) -#define BSP_FEATURE_TZ_NS_OFFSET (0U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) + #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_VERSION (0U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (0) // Feature not available on this MCU +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) #define BSP_FEATURE_USB_HAS_USBHS (0U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module #endif diff --git a/ra/fsp/src/bsp/mcu/ra2a2/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra2a2/bsp_feature_gen.h index b96ac490d..9ca9db5de 100644 --- a/ra/fsp/src/bsp/mcu/ra2a2/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra2a2/bsp_feature_gen.h @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h index b187105cf..89be0cb44 100644 --- a/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h @@ -75,6 +75,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_FLASH_CACHE (0) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (1) @@ -82,9 +83,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (1U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -111,8 +112,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x000FFFFFU) +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (1) #define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_NUM_PMSAR (0U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) @@ -143,12 +146,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (0U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (1U) #define BSP_FEATURE_CGC_HAS_FLL (0U) #define BSP_FEATURE_CGC_HAS_FLWT (0U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (1U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (0U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (0U) @@ -172,49 +177,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (1U) #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV1_Msk) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV1_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (0U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_TYPE (0U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (0U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // This MCU does not have PLL +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) #define BSP_FEATURE_CGC_SODRV_MASK (0x03U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (1) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x04000404) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (1U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (1U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (1) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) // #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) #define BSP_FEATURE_CRYPTO_HAS_ECC (0) // #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) // #define BSP_FEATURE_CRYPTO_HAS_HASH (0) // -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (0) // #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) // -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (1) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) @@ -249,28 +255,28 @@ #define BSP_FEATURE_DWT_CYCCNT (0U) -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0004C30FU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (1U) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_CODE_FLASH_START (0x0U) #define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) -#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (0) -#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0x7FFU) #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (11) #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x800U) +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (4) #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) @@ -289,30 +295,31 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (1U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (0) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0xF38F00FFU) -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) -#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU -#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_IIC_FAST_MODE_PLUS (0U) #define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x01) -#define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_IOPORT_ELC_PORTS (0x0006U) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) #define BSP_FEATURE_IOPORT_VERSION (1U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) @@ -329,6 +336,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -337,41 +346,43 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_STCONR (0) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_STCONR (0) // Feature not available on this MCU #define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x738200FFU) #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (1) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (1200U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_MACL_SUPPORTED (0U) -#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (4U) -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (100U) // This information comes from the Electrical Characteristics chapter of the hardware manual. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (100U) // This information comes from the Electrical Characteristics chapter of the hardware manual. #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (10U) -#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) @@ -379,81 +390,89 @@ #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (1U) #define BSP_FEATURE_RTC_HAS_TCEN (0U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (0U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) #define BSP_FEATURE_SCI_CHANNELS (0x207U) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKB) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x0U) +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x1U) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) -#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKB) -#define BSP_FEATURE_SPI_HAS_SPCR3 (0) // Feature not available on this MCU +#define BSP_FEATURE_SPI_HAS_SPCR3 (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (0U) #define BSP_FEATURE_SPI_MAX_CHANNEL (1U) #define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x0U) -#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0) // Feature not available on this MCU +#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0) // Feature not available on this MCU -#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0) // Feature not available on this MCU -#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0) // Feature not available on this MCU +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU + +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (1U) + +#define BSP_FEATURE_TZ_HAS_DLM (0) // Feature not available on this MCU +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0) // Feature not available on this MCU #define BSP_FEATURE_TZ_NS_OFFSET (0U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0) // Feature not available on this MCU -#define BSP_FEATURE_TZ_HAS_DLM (0) // Feature not available on this MCU -#define BSP_FEATURE_TZ_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_TZ_VERSION (0) // Feature not available on this MCU + +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (0) // Feature not available on this MCU +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) #define BSP_FEATURE_USB_HAS_USBHS (0U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module #endif diff --git a/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature_gen.h index 290c41b4b..efb3073ec 100644 --- a/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature_gen.h @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h index d99dc1a6e..7d8d02369 100644 --- a/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h @@ -75,6 +75,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (1) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_FLASH_CACHE (0) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (1) @@ -82,9 +83,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (1U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -111,8 +112,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x000FFFFFU) +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (0) #define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_NUM_PMSAR (0U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) @@ -143,12 +146,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (0U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (1U) #define BSP_FEATURE_CGC_HAS_FLL (0U) #define BSP_FEATURE_CGC_HAS_FLWT (0U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (1U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (0U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (0U) @@ -172,49 +177,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (1U) #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV1_Msk) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV1_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (0U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_TYPE (0U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (0U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // This MCU does not have PLL +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) #define BSP_FEATURE_CGC_SODRV_MASK (0x03U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (1) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x04000404) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (1U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (1U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (1) #define BSP_FEATURE_CRYPTO_HAS_AES (1) // #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) // #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) #define BSP_FEATURE_CRYPTO_HAS_ECC (0) // #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) // #define BSP_FEATURE_CRYPTO_HAS_HASH (0) // -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (0) // #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) // -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (1) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) @@ -249,28 +255,28 @@ #define BSP_FEATURE_DWT_CYCCNT (0U) -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0000C30FU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (1U) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_CODE_FLASH_START (0x0U) #define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) -#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (0) -#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0x7FFU) #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (11) #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x800U) +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (4) #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) @@ -289,21 +295,22 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MAX_DEV_COUNT (4U) +#define BSP_FEATURE_I3C_MSTP_OFFSET (9U) #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (2U) #define BSP_FEATURE_I3C_NUM_CHANNELS (1U) -#define BSP_FEATURE_I3C_MSTP_OFFSET (9U) -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (1U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (0) // Feature not available on this MCU -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x0FU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0x700F00FFU) -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (3U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (1U) @@ -313,7 +320,6 @@ #define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_IOPORT_ELC_PORTS (0x0006U) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) #define BSP_FEATURE_IOPORT_VERSION (1U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) @@ -330,6 +336,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -338,41 +346,43 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_STCONR (0) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_STCONR (0) // Feature not available on this MCU #define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000001FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x700200FFU) #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (1) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (1200U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_MACL_SUPPORTED (0U) -#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (4U) -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (100U) // This information comes from the Electrical Characteristics chapter of the hardware manual. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (100U) // This information comes from the Electrical Characteristics chapter of the hardware manual. #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (10U) -#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) @@ -380,81 +390,89 @@ #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (0U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0U) #define BSP_FEATURE_RTC_HAS_TCEN (0U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (0U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (0U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) #define BSP_FEATURE_SCI_CHANNELS (0x200U) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKB) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x0U) +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x0U) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (0U) #define BSP_FEATURE_SCI_VERSION (1U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) -#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKB) -#define BSP_FEATURE_SPI_HAS_SPCR3 (0) // Feature not available on this MCU +#define BSP_FEATURE_SPI_HAS_SPCR3 (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (0U) #define BSP_FEATURE_SPI_MAX_CHANNEL (1U) #define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x0U) -#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0) // Feature not available on this MCU +#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0) // Feature not available on this MCU -#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0) // Feature not available on this MCU -#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0) // Feature not available on this MCU +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU + +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (1U) + +#define BSP_FEATURE_TZ_HAS_DLM (0) // Feature not available on this MCU +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0) // Feature not available on this MCU #define BSP_FEATURE_TZ_NS_OFFSET (0U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0) // Feature not available on this MCU -#define BSP_FEATURE_TZ_HAS_DLM (0) // Feature not available on this MCU -#define BSP_FEATURE_TZ_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_TZ_VERSION (0) // Feature not available on this MCU + +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (0) // Feature not available on this MCU +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) #define BSP_FEATURE_USB_HAS_USBHS (0U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module #endif diff --git a/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature_gen.h index ed45f36d6..aa543f3c9 100644 --- a/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature_gen.h @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra2e3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2e3/bsp_feature.h index 54545e9a0..c09d798d2 100644 --- a/ra/fsp/src/bsp/mcu/ra2e3/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2e3/bsp_feature.h @@ -75,6 +75,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_FLASH_CACHE (0) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (1) @@ -82,9 +83,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (1U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -111,8 +112,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x000FFFFFU) +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (1) #define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_NUM_PMSAR (0U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) @@ -143,12 +146,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (0U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (1U) #define BSP_FEATURE_CGC_HAS_FLL (0U) #define BSP_FEATURE_CGC_HAS_FLWT (0U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (1U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (0U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (0U) @@ -172,49 +177,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (1U) #define BSP_FEATURE_CGC_MODRV_MASK (0x08U) #define BSP_FEATURE_CGC_MODRV_SHIFT (0x3U) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (0U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_TYPE (0U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (0U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // This MCU does not have PLL +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) #define BSP_FEATURE_CGC_SODRV_MASK (0x03U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (1) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x04000404) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (1U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (1U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_AES (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_ECC (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_HASH (0) // Feature not available on this MCU -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) // Feature not available on this MCU -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) // Feature not available on this MCU @@ -249,28 +255,28 @@ #define BSP_FEATURE_DWT_CYCCNT (0U) -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0004C30FU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (1U) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_CODE_FLASH_START (0x0U) #define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) -#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0x7FFU) #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (11) #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x800U) +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (4) #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) @@ -283,27 +289,28 @@ #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x1) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (4U) #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) -#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU -#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU -#define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU -#define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) -#define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (1U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (0) // Feature not available on this MCU -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0xF38F00FFU) -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) // Feature not available on this MCU #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) // Feature not available on this MCU #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU @@ -313,7 +320,6 @@ #define BSP_FEATURE_IIC_VERSION (1U) #define BSP_FEATURE_IOPORT_ELC_PORTS (0x0006U) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) #define BSP_FEATURE_IOPORT_VERSION (1U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) @@ -330,6 +336,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -338,39 +346,43 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_STCONR (0) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_STCONR (0) // Feature not available on this MCU #define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x738200FFU) #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (1) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD1 to stabilize #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD1 to stabilize #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (1200U) // Time in microseconds required for LVD2 to stabilize #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU + +#define BSP_FEATURE_MACL_SUPPORTED (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_BASE_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (4U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (100U) // This information comes from the Electrical Characteristics chapter of the hardware manual. #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (10U) #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) @@ -378,25 +390,25 @@ #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (1U) #define BSP_FEATURE_RTC_HAS_TCEN (0U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (0U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) #define BSP_FEATURE_SCI_CHANNELS (0x207U) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKB) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x0U) +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x1U) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU @@ -406,12 +418,12 @@ #define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SPI_HAS_SPCR3 (0) // Feature not available on this MCU @@ -419,40 +431,48 @@ #define BSP_FEATURE_SPI_MAX_CHANNEL (1U) #define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x0U) -#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0) // Feature not available on this MCU +#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0) // Feature not available on this MCU + +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0) // Feature not available on this MCU +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU + +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) + +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0) // Feature not available on this MCU -#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0) // Feature not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU +#define BSP_FEATURE_TZ_HAS_DLM (0) // Feature not available on this MCU +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0) // Feature not available on this MCU +#define BSP_FEATURE_TZ_NS_OFFSET (0U) // Feature not available on this MCU +#define BSP_FEATURE_TZ_VERSION (0) // Feature not available on this MCU -#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0) // Feature not available on this MCU -#define BSP_FEATURE_TZ_NS_OFFSET (0U) // Feature not available on this MCU -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0) // Feature not available on this MCU -#define BSP_FEATURE_TZ_HAS_DLM (0) // Feature not available on this MCU -#define BSP_FEATURE_TZ_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (0) // Feature not available on this MCU +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) #define BSP_FEATURE_USB_HAS_USBHS (0U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module #endif diff --git a/ra/fsp/src/bsp/mcu/ra2e3/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra2e3/bsp_feature_gen.h index afadb8446..6b8c52a20 100644 --- a/ra/fsp/src/bsp/mcu/ra2e3/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra2e3/bsp_feature_gen.h @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h index afc9ae31f..6b64b1746 100644 --- a/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h @@ -75,6 +75,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_FLASH_CACHE (0) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (1) @@ -82,9 +83,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (1U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (1U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -111,8 +112,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x000FFFFFU) +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (1) #define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (3U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (0U) +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_NUM_PMSAR (0U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) @@ -143,12 +146,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (0U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (1U) #define BSP_FEATURE_CGC_HAS_FLL (0U) #define BSP_FEATURE_CGC_HAS_FLWT (0U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (1U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (0U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (0U) @@ -172,49 +177,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (1U) #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV1_Msk) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV1_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (0U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_TYPE (0U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (0U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // This MCU does not have PLL +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) #define BSP_FEATURE_CGC_SODRV_MASK (0x03U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (1) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x04000404) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (1U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (1U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (1) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) #define BSP_FEATURE_CRYPTO_HAS_ECC (0) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) #define BSP_FEATURE_CRYPTO_HAS_HASH (0) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (0) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (1) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) @@ -249,28 +255,28 @@ #define BSP_FEATURE_DWT_CYCCNT (0U) -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0004D30FU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (1U) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_CODE_FLASH_START (0x0U) #define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) -#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (0) -#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0x7FFU) #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (11) #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x800U) +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (4) #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) @@ -289,31 +295,31 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (1U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0xF38F00FFU) -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) -#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU -#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_IIC_FAST_MODE_PLUS (0U) #define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x03) -#define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_IOPORT_ELC_PORTS (0x0006U) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) #define BSP_FEATURE_IOPORT_VERSION (1U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) @@ -330,6 +336,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -338,41 +346,43 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) -#define BSP_FEATURE_LPM_HAS_STCONR (0U) -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_STCONR (0U) #define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x738200FFU) #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (1200U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_MACL_SUPPORTED (0U) -#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0U) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0U) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0U) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0U) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) // Feature not available on this MCU - +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0U) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0U) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0U) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0U) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) // Feature not available on this MCU + +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) @@ -380,40 +390,40 @@ #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (1U) #define BSP_FEATURE_RTC_HAS_TCEN (0U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (0U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) #define BSP_FEATURE_SCI_CHANNELS (0x20FU) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKB) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x0U) +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x1U) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) -#define BSP_FEATURE_SDHI_CLOCK (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_SDRAM_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) -#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) @@ -421,40 +431,48 @@ #define BSP_FEATURE_SPI_MAX_CHANNEL (2U) #define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x0U) -#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0) // Feature not available on this MCU +#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0) // Feature not available on this MCU + +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0) // Feature not available on this MCU +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0) // Feature not available on this MCU -#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (1U) -#define BSP_FEATURE_TZ_NS_OFFSET (0U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) + #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_VERSION (0U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (0) // Feature not available on this MCU +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) #define BSP_FEATURE_USB_HAS_USBHS (0U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module #endif diff --git a/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature_gen.h index dd53e77cc..fb3b003ae 100644 --- a/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature_gen.h @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h index 868349c1f..34ffe694b 100644 --- a/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h @@ -79,6 +79,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x2F) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) @@ -86,9 +87,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -115,8 +116,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPCRE is present than the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (0) // If MSTPCRE is present then the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U) +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_NUM_PMSAR (6U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) @@ -147,12 +150,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLL (1U) #define BSP_FEATURE_CGC_HAS_FLWT (1U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (1U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (1U) @@ -176,49 +181,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (1U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (200000000U) -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (100000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (240000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (120000000U) -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (200000000U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (200000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (100000000U) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (0U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U) // Don't care #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (0U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U) // Don't care +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) #define BSP_FEATURE_CRYPTO_HAS_AES (0) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) #define BSP_FEATURE_CRYPTO_HAS_ECC (0) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) #define BSP_FEATURE_CRYPTO_HAS_HASH (0) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (0) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) @@ -251,18 +257,17 @@ #define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) -#define BSP_FEATURE_DWT_CYCCNT (1U) // This MCU has Data Watchpoint Cycle Count Register +#define BSP_FEATURE_DWT_CYCCNT (1U) // This MCU has Data Watchpoint Cycle Count Register -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0003D1FFU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (1U) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_CODE_FLASH_START (0x0U) #define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000U) -#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U) #define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U) #define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U) @@ -275,6 +280,7 @@ #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU @@ -293,21 +299,22 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x23FFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (13U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0x7FB0D23FFULL) // Note there is another WUPEN1 register -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU @@ -317,7 +324,6 @@ #define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) #define BSP_FEATURE_IOPORT_VERSION (1U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) @@ -334,6 +340,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -342,41 +350,43 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U) +#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STCONR (0U) -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (1) -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note there is another SNZEREQCR1 register +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note there is another SNZEREQCR1 register #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_MACL_SUPPORTED (0U) #define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) @@ -384,40 +394,40 @@ #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0U) #define BSP_FEATURE_RTC_HAS_TCEN (1U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (1U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x219U) #define BSP_FEATURE_SCI_CHANNELS (0x219U) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x0006U) // Channel 1 and channel 2 have ABCSE bit restriction #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x0219U) // Channel 0, channel 3, Channel 4, channel 9 have CSTPEN feature +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x219U) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x0006U) // Channel 1 and channel 2 have ABCSE bit restriction #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0U) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0U) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0U) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0U) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) // Feature not available on this MCU +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) -#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) @@ -427,38 +437,46 @@ #define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0x01U) -#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0U) // Feature not available on this MCU -#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0U) // Feature not available on this MCU +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU + +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) -#define BSP_FEATURE_TZ_NS_OFFSET (0U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) + #define BSP_FEATURE_TZ_HAS_DLM (1U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_VERSION (1U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (0) // Feature not available on this MCU +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) #define BSP_FEATURE_USB_HAS_USBHS (0U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module #endif diff --git a/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature_gen.h index 92fef1a30..ecc25a17d 100644 --- a/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature_gen.h @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature.h index 79f7c315e..f6bb684ec 100644 --- a/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature.h @@ -79,6 +79,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3U) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) @@ -86,9 +87,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1) #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (1) #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (1) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -101,6 +102,7 @@ #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0U) #define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SP_MON (0U) @@ -114,8 +116,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (0) // If MSTPCRE is present then the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U) +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_NUM_PMSAR (9U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) @@ -146,12 +150,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLL (1U) #define BSP_FEATURE_CGC_HAS_FLWT (1U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (1U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (1U) @@ -175,49 +181,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (0U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (240000000U) -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (100000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (240000000U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (240000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (100000000U) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22002222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (0U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (0U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) #define BSP_FEATURE_CRYPTO_HAS_AES (0) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) #define BSP_FEATURE_CRYPTO_HAS_ECC (0) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) #define BSP_FEATURE_CRYPTO_HAS_HASH (0) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (0) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) @@ -233,6 +240,7 @@ #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU #define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) #define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U) @@ -249,14 +257,13 @@ #define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) -#define BSP_FEATURE_DWT_CYCCNT (1U) // RA4E2 has Data Watchpoint Cycle Count Register +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA4E2 has Data Watchpoint Cycle Count Register -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0083F3FFU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (1U) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0U) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_MAX_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0U) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_CODE_FLASH_START (0x0U) #define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000U) @@ -273,6 +280,7 @@ #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU @@ -291,21 +299,22 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MAX_DEV_COUNT (8U) +#define BSP_FEATURE_I3C_MSTP_OFFSET (4U) #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (16U) #define BSP_FEATURE_I3C_NUM_CHANNELS (1U) -#define BSP_FEATURE_I3C_MSTP_OFFSET (4U) -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x7FFFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0x8007B0D7FFFULL) // Note there is another WUPEN1 register -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (5U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0x01) @@ -315,7 +324,6 @@ #define BSP_FEATURE_IIC_VERSION (2) #define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) #define BSP_FEATURE_IOPORT_VERSION (1U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) @@ -332,6 +340,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -340,41 +350,43 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) -#define BSP_FEATURE_LPM_HAS_STCONR (0U) -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_STCONR (0U) #define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (1U) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x73007FFFU) #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_MACL_SUPPORTED (0U) #define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) @@ -382,40 +394,40 @@ #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0U) #define BSP_FEATURE_RTC_HAS_TCEN (1U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (2U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x201U) #define BSP_FEATURE_SCI_CHANNELS (0x201U) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x201U) +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x201U) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) -#define BSP_FEATURE_SDHI_CLOCK (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) // Feature not available on this MCU +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) -#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) @@ -428,36 +440,43 @@ #define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) #define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0x01U) -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_TFU_SUPPORTED (0U) +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU + #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (1U) -#define BSP_FEATURE_TZ_NS_OFFSET (0U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) + #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_VERSION (1U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (1U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (1U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) #define BSP_FEATURE_USB_HAS_USBHS (0U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (1U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module -#define BSP_FEATURE_USB_HAS_NOT_HOST (1U) #endif diff --git a/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature_gen.h index 1b92ef4c3..3d3e6203d 100644 --- a/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature_gen.h @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h index a4734f38d..dd2ee4698 100644 --- a/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h @@ -75,6 +75,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) @@ -82,9 +83,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -111,8 +112,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (1U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x407FB19C) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFU) +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (1) #define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (1U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (0U) +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_NUM_PMSAR (0U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) @@ -145,12 +148,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (0U) // This MCU does not have a BCLK #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLL (0U) #define BSP_FEATURE_CGC_HAS_FLWT (0U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (1U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (1U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (1U) @@ -174,49 +179,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (1U) #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV1_Msk) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV1_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (0U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (64000000U) -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (12500000U) -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (4000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_TYPE (2U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (0U) // This MCU does not use PLLCCR to set PLL frequency +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (1U) // 1 us wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (64000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (24000000U) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (12500000U) +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (4000000U) #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1U) // RA4M1 requires that bits 16-18 of SCKDIVCR be the same as the bits for PCKB #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1U) // RA4M1 requires that bits 16-18 of SCKDIVCR be the same as the bits for PCKB #define BSP_FEATURE_CGC_SODRV_MASK (0x03U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (2) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x44044444) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (1U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (1U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) #define BSP_FEATURE_CRYPTO_HAS_ECC (0) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) #define BSP_FEATURE_CRYPTO_HAS_HASH (0) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (0) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (1) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) @@ -249,30 +255,30 @@ #define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) -#define BSP_FEATURE_DWT_CYCCNT (1U) // RA4M1 has Data Watchpoint Cycle Count Register +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA4M1 has Data Watchpoint Cycle Count Register -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007D3FFU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (1U) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_CODE_FLASH_START (0x0U) #define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) -#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (0) -#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0xFFFU) #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (10) #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x800U) +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (8) #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) @@ -291,31 +297,31 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xDFFFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0xFB9FDFFFU) -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) -#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU -#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_IIC_FAST_MODE_PLUS (0U) #define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x03) -#define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) #define BSP_FEATURE_IOPORT_VERSION (1U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) @@ -332,6 +338,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -340,41 +348,43 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) -#define BSP_FEATURE_LPM_HAS_STCONR (0U) -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_STCONR (0U) #define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (1U) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7382DFFFU) #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (300U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_MACL_SUPPORTED (0U) #define BSP_FEATURE_OPAMP_BASE_ADDRESS (1U) #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0U) #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (1U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (13U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (650U) // This information comes from the Electrical Characteristics chapter of the hardware manual. #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0xFFFFU) // Middle speed mode not supported #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0xFU) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) @@ -382,40 +392,40 @@ #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0U) #define BSP_FEATURE_RTC_HAS_TCEN (1U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (3U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) #define BSP_FEATURE_SCI_CHANNELS (0x207U) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x0U) +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3U) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (15U) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (6U) #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (1U) #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (1U) -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (38U) #define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (6U) -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (15U) +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (38U) #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) @@ -428,35 +438,43 @@ #define BSP_FEATURE_SSI_FIFO_NUM_STAGES (8U) #define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U) -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) + +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) -#define BSP_FEATURE_TZ_NS_OFFSET (0U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) + #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_VERSION (0U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (0) // Feature not available on this MCU +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) #define BSP_FEATURE_USB_HAS_USBHS (0U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (1U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (1U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module #endif diff --git a/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature_gen.h index fb798d8ab..9182db751 100644 --- a/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature_gen.h @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h index 188e03b3d..c9b6f8c4d 100644 --- a/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h @@ -79,6 +79,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3F) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) @@ -86,9 +87,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -115,8 +116,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (0) // If MSTPCRE is present then the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U) +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_NUM_PMSAR (8U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) @@ -147,12 +150,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLL (1U) #define BSP_FEATURE_CGC_HAS_FLWT (1U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (1U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (1U) @@ -176,49 +181,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (1U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (200000000U) -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (100000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (240000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (120000000U) -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (200000000U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (200000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (100000000U) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (0U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (0U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) #define BSP_FEATURE_CRYPTO_HAS_ECC (1) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_HASH (1) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (1) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) @@ -251,18 +257,17 @@ #define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) -#define BSP_FEATURE_DWT_CYCCNT (1U) // RA4M2 has Data Watchpoint Cycle Count Register +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA4M2 has Data Watchpoint Cycle Count Register -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007F3FFU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (1U) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_CODE_FLASH_START (0x0U) #define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000U) -#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U) #define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U) #define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U) @@ -275,6 +280,7 @@ #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU @@ -293,21 +299,22 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (13U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0x7FB0DFFFFULL) // Note there is another WUPEN1 register -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU @@ -317,7 +324,6 @@ #define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) #define BSP_FEATURE_IOPORT_VERSION (1U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) @@ -334,6 +340,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -342,41 +350,43 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U) +#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STCONR (0U) -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000019FU) // note there is another SNZEDCR1 register -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note there is another SNZEREQCR1 register +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000019FU) // note there is another SNZEDCR1 register +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note there is another SNZEREQCR1 register #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_MACL_SUPPORTED (0U) #define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) @@ -384,40 +394,40 @@ #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0U) #define BSP_FEATURE_RTC_HAS_TCEN (0U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (0U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x219U) #define BSP_FEATURE_SCI_CHANNELS (0x21FU) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x0006U) // Channel 1 and channel 2 have ABCSE bit restriction #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x0219U) // Channel 0, channel 3, Channel 4, channel 9 have CSTPEN feature +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x219U) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x0006U) // Channel 1 and channel 2 have ABCSE bit restriction #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // 1 (2^0) is minimum division supported -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0U) // ra4m2 does not support 8-bit MMC +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // 1 (2^0) is minimum division supported +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0U) // ra4m2 does not support 8-bit MMC #define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x01U) #define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) @@ -430,35 +440,43 @@ #define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) #define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U) -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) + +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) -#define BSP_FEATURE_TZ_NS_OFFSET (0U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) + #define BSP_FEATURE_TZ_HAS_DLM (1U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_VERSION (1U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (0) // Feature not available on this MCU +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) #define BSP_FEATURE_USB_HAS_USBHS (0U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module #endif diff --git a/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature_gen.h index 1169bc148..8a69e79b7 100644 --- a/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature_gen.h @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h index 906cd9b88..79466d9f1 100644 --- a/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h @@ -79,6 +79,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3F) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) @@ -86,9 +87,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -115,14 +116,15 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (0) // If MSTPCRE is present then the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U) +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_NUM_PMSAR (9U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) -#define BSP_FEATURE_BSP_VTOR_LOCKED (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_BSP_RESET_TRNG (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). @@ -148,12 +150,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLL (1U) #define BSP_FEATURE_CGC_HAS_FLWT (1U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (1U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (1U) @@ -177,49 +181,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (1U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (200000000U) -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (100000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (240000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (120000000U) -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (200000000U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (200000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (100000000U) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (0U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (0U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) #define BSP_FEATURE_CRYPTO_HAS_ECC (1) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_HASH (1) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (1) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) @@ -252,18 +257,17 @@ #define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) -#define BSP_FEATURE_DWT_CYCCNT (1U) // RA4M3 has Data Watchpoint Cycle Count Register +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA4M3 has Data Watchpoint Cycle Count Register -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (1U) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_CODE_FLASH_START (0x0U) #define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000U) -#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U) #define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U) #define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U) @@ -276,6 +280,7 @@ #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU @@ -294,21 +299,22 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0x7FB0DFFFFULL) // Note there is another WUPEN1 register -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU @@ -318,7 +324,6 @@ #define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) #define BSP_FEATURE_IOPORT_VERSION (1U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) @@ -335,6 +340,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -343,41 +350,43 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U) +#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STCONR (0U) -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note there is another SNZEREQCR1 register +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note there is another SNZEREQCR1 register #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_MACL_SUPPORTED (0U) #define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) @@ -385,40 +394,40 @@ #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0U) #define BSP_FEATURE_RTC_HAS_TCEN (1U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (3U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x219U) #define BSP_FEATURE_SCI_CHANNELS (0x21FU) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x0006U) // Channel 1 and channel 2 have ABCSE bit restriction #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x0219U) // Channel 0, channel 3, Channel 4, channel 9 have CSTPEN feature +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x219U) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x0006U) // Channel 1 and channel 2 have ABCSE bit restriction #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // 0 (2^0) is minimum division supported +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // 0 (2^0) is minimum division supported #define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1U) #define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x01U) #define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) @@ -431,35 +440,43 @@ #define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) #define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U) -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) + +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) -#define BSP_FEATURE_TZ_NS_OFFSET (0U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) + #define BSP_FEATURE_TZ_HAS_DLM (1U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_VERSION (1U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (0) // Feature not available on this MCU +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) #define BSP_FEATURE_USB_HAS_USBHS (0U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module #endif diff --git a/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature_gen.h index 0fa5716a8..b336b0433 100644 --- a/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature_gen.h @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature.h index 96ef7ddde..beb82cc96 100644 --- a/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature.h @@ -79,6 +79,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3U) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) @@ -86,9 +87,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1) #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (1) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -115,8 +116,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (0) // If MSTPCRE is present then the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U) +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_NUM_PMSAR (9U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) @@ -147,12 +150,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLL (1U) #define BSP_FEATURE_CGC_HAS_FLWT (1U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (1U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (1U) @@ -176,49 +181,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (0U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (240000000U) -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (100000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (240000000U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (240000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (100000000U) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22002222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (0U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (0U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) #define BSP_FEATURE_CRYPTO_HAS_AES (0) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) #define BSP_FEATURE_CRYPTO_HAS_ECC (0) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) #define BSP_FEATURE_CRYPTO_HAS_HASH (0) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (0) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) @@ -251,14 +257,13 @@ #define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) -#define BSP_FEATURE_DWT_CYCCNT (1U) // RA4T1 has Data Watchpoint Cycle Count Register +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA4T1 has Data Watchpoint Cycle Count Register -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0083F3FFU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (1U) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0U) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_MAX_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0U) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_CODE_FLASH_START (0x0U) #define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000U) @@ -275,6 +280,7 @@ #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU @@ -293,21 +299,22 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MAX_DEV_COUNT (8U) +#define BSP_FEATURE_I3C_MSTP_OFFSET (4U) #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (16U) #define BSP_FEATURE_I3C_NUM_CHANNELS (1U) -#define BSP_FEATURE_I3C_MSTP_OFFSET (4U) -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x7FFFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0x800700D7FFFULL) // Note there is another WUPEN1 register -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (5U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0x01) @@ -317,7 +324,6 @@ #define BSP_FEATURE_IIC_VERSION (2) #define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) #define BSP_FEATURE_IOPORT_VERSION (1U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) @@ -334,6 +340,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -342,41 +350,43 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) -#define BSP_FEATURE_LPM_HAS_STCONR (0U) -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_STCONR (0U) #define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (1U) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x70407FFFU) #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_MACL_SUPPORTED (0U) #define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) @@ -384,40 +394,40 @@ #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (0U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0U) #define BSP_FEATURE_RTC_HAS_TCEN (1U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (0U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (2U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x201U) #define BSP_FEATURE_SCI_CHANNELS (0x201U) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x201U) +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x201U) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) -#define BSP_FEATURE_SDHI_CLOCK (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) // Feature not available on this MCU +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) -#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) @@ -427,38 +437,46 @@ #define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0x01U) -#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0U) // Feature not available on this MCU -#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0U) // Feature not available on this MCU +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_TFU_SUPPORTED (1U) +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU + #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (1U) -#define BSP_FEATURE_TZ_NS_OFFSET (0U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) + #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_VERSION (1U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (0) // Feature not available on this MCU +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) #define BSP_FEATURE_USB_HAS_USBHS (0U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module #endif diff --git a/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature_gen.h index 0af368c68..fd5f05dbd 100644 --- a/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature_gen.h @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h index a868aebbe..bec8be8ea 100644 --- a/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h @@ -75,6 +75,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_FLASH_CACHE (1U) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) @@ -82,9 +83,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -111,8 +112,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (1U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x407FB19C) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFU) +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (1) #define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (3U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (0U) +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_NUM_PMSAR (0U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) @@ -145,12 +148,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (0U) // This MCU does not have a BCLK #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLL (0U) #define BSP_FEATURE_CGC_HAS_FLWT (0U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (1U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (1U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (1U) @@ -174,49 +179,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (1U) #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV1_Msk) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV1_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (0U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (64000000U) -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (12500000U) -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (4000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_TYPE (2U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (0U) // This MCU does not use PLLCCR to set PLL frequency +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (1U) // 1 us wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (64000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (24000000U) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (12500000U) +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (4000000U) #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1U) // RA4W1 requires that bits 16-18 of SCKDIVCR be the same as the bits for PCKB #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1U) // RA4W1 requires that bits 16-18 of SCKDIVCR be the same as the bits for PCKB #define BSP_FEATURE_CGC_SODRV_MASK (0x03U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (2) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x44044444) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (1U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (1U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) #define BSP_FEATURE_CRYPTO_HAS_ECC (0) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) #define BSP_FEATURE_CRYPTO_HAS_HASH (0) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (0) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (1) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) @@ -249,30 +255,30 @@ #define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) -#define BSP_FEATURE_DWT_CYCCNT (1U) // RA4W1 has Data Watchpoint Cycle Count Register +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA4W1 has Data Watchpoint Cycle Count Register -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007D3FFU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (1U) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_CODE_FLASH_START (0x0U) #define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) -#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (0) -#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0xFFFU) #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (10) #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x800U) +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (8) #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) @@ -291,31 +297,31 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xCBDFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0xFB97CADFU) -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) -#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU -#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_IIC_FAST_MODE_PLUS (0U) #define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x03) -#define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) #define BSP_FEATURE_IOPORT_VERSION (1U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) @@ -332,6 +338,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -340,41 +348,43 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) -#define BSP_FEATURE_LPM_HAS_STCONR (0U) -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_STCONR (0U) #define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7382CADFU) #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (300U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_MACL_SUPPORTED (0U) #define BSP_FEATURE_OPAMP_BASE_ADDRESS (1U) #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0U) #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (1U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (13U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (650U) // This information comes from the Electrical Characteristics chapter of the hardware manual. #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0xFFFFU) // Middle speed mode not supported #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0xFU) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) @@ -382,40 +392,40 @@ #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0U) #define BSP_FEATURE_RTC_HAS_TCEN (1U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (1U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) #define BSP_FEATURE_SCI_CHANNELS (0x213U) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x0U) +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3U) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0U) #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0U) -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (54U) #define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (54U) #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) @@ -423,40 +433,48 @@ #define BSP_FEATURE_SPI_MAX_CHANNEL (2U) #define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x1U) -#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0) // Feature not available on this MCU +#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0) // Feature not available on this MCU #define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0U) -#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU + +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) -#define BSP_FEATURE_TZ_NS_OFFSET (0U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) + #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_VERSION (0U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (0) // Feature not available on this MCU +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) #define BSP_FEATURE_USB_HAS_USBHS (0U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (1U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (1U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module #endif diff --git a/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature_gen.h index a3e3c8139..eec066653 100644 --- a/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature_gen.h @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h index 76a5afb11..4b6b74956 100644 --- a/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h @@ -79,6 +79,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3F) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) @@ -86,9 +87,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -115,8 +116,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (0) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U) +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_NUM_PMSAR (8U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) @@ -147,12 +150,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLL (1U) #define BSP_FEATURE_CGC_HAS_FLWT (1U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (1U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (1U) @@ -176,49 +181,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (1U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (200000000U) -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (240000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (120000000U) -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (200000000U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (200000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000U) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (0U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (0U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) #define BSP_FEATURE_CRYPTO_HAS_AES (0) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) #define BSP_FEATURE_CRYPTO_HAS_ECC (0) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) #define BSP_FEATURE_CRYPTO_HAS_HASH (0) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (0) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) @@ -251,9 +257,8 @@ #define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) -#define BSP_FEATURE_DWT_CYCCNT (1U) // This MCU has Data Watchpoint Cycle Count Register +#define BSP_FEATURE_DWT_CYCCNT (1U) // This MCU has Data Watchpoint Cycle Count Register -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0003D3FFU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (1U) #define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU) @@ -275,6 +280,7 @@ #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU @@ -293,21 +299,22 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0x7FB0DFFFFULL) // Note there is another WUPEN1 register -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU @@ -317,7 +324,6 @@ #define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (1U) #define BSP_FEATURE_IOPORT_VERSION (1U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) @@ -334,6 +340,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -342,41 +350,43 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U) +#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STCONR (0U) -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000019FU) // note there is another SNZEDCR1 register -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000019FU) // note there is another SNZEDCR1 register +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_MACL_SUPPORTED (0U) #define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) @@ -384,40 +394,40 @@ #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0U) #define BSP_FEATURE_RTC_HAS_TCEN (1U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (3U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x219U) #define BSP_FEATURE_SCI_CHANNELS (0x21FU) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x0006U) // Channel 1 and channel 2 have ABCSE bit restriction #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x0219U) // Channel 0, channel 3, Channel 4, channel 9 have CSTPEN feature +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x219U) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x0006U) // Channel 1 and channel 2 have ABCSE bit restriction #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // 1 (2^0) is minimum division supported +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // 1 (2^0) is minimum division supported #define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0U) #define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (1U) -#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) // Feature not available on this MCU +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) -#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) @@ -430,35 +440,43 @@ #define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) #define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U) -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) + +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) -#define BSP_FEATURE_TZ_NS_OFFSET (0U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) + #define BSP_FEATURE_TZ_HAS_DLM (1U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_VERSION (1U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (0) // Feature not available on this MCU +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) #define BSP_FEATURE_USB_HAS_USBHS (0U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module #endif diff --git a/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature_gen.h index e4e9dc17d..ca827b1c5 100644 --- a/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature_gen.h @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h index 87ceab996..c63a5ac87 100644 --- a/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h @@ -79,6 +79,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3U) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) @@ -86,9 +87,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1) #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (1) #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (1) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -101,6 +102,7 @@ #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0U) #define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SP_MON (0U) @@ -114,8 +116,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (0) // If MSTPCRE is present then the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U) +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_NUM_PMSAR (9U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) @@ -146,12 +150,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLL (1U) #define BSP_FEATURE_CGC_HAS_FLWT (1U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (1U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (1U) @@ -175,49 +181,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (0U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (240000000U) -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (240000000U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (240000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000U) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22002222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (0U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (0U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) #define BSP_FEATURE_CRYPTO_HAS_AES (0) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) #define BSP_FEATURE_CRYPTO_HAS_ECC (0) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) #define BSP_FEATURE_CRYPTO_HAS_HASH (0) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (0) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) @@ -233,6 +240,7 @@ #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU #define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) #define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U) @@ -249,14 +257,13 @@ #define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) -#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6E2 has Data Watchpoint Cycle Count Register +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6E2 has Data Watchpoint Cycle Count Register -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0083F3FFU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (1U) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0U) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_MAX_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0U) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_CODE_FLASH_START (0x0U) #define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000U) @@ -273,6 +280,7 @@ #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU @@ -291,21 +299,22 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MAX_DEV_COUNT (8U) +#define BSP_FEATURE_I3C_MSTP_OFFSET (4U) #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (16U) #define BSP_FEATURE_I3C_NUM_CHANNELS (1U) -#define BSP_FEATURE_I3C_MSTP_OFFSET (4U) -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x7FFFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0x8007B0D7FFFULL) // Note there is another WUPEN1 register -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (5U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0x01) @@ -315,7 +324,6 @@ #define BSP_FEATURE_IIC_VERSION (2) #define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) #define BSP_FEATURE_IOPORT_VERSION (1U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) @@ -332,6 +340,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -340,41 +350,43 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) -#define BSP_FEATURE_LPM_HAS_STCONR (0U) -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_STCONR (0U) #define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (1U) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x73007FFFU) #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_MACL_SUPPORTED (0U) #define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) @@ -382,40 +394,40 @@ #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0U) #define BSP_FEATURE_RTC_HAS_TCEN (1U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (2U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x201U) #define BSP_FEATURE_SCI_CHANNELS (0x201U) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x201U) +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x201U) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) -#define BSP_FEATURE_SDHI_CLOCK (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) // Feature not available on this MCU +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) -#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) @@ -428,36 +440,43 @@ #define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) #define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0x01U) -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_TFU_SUPPORTED (0U) +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU + #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (1U) -#define BSP_FEATURE_TZ_NS_OFFSET (0U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) + #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_VERSION (1U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (1U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (1U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) #define BSP_FEATURE_USB_HAS_USBHS (0U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (1U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module -#define BSP_FEATURE_USB_HAS_NOT_HOST (1U) #endif diff --git a/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature_gen.h index d7c9e64a0..bc33032f2 100644 --- a/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature_gen.h @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h index 4ea8d9ee8..67191a5c5 100644 --- a/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h @@ -79,6 +79,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) @@ -86,9 +87,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -115,8 +116,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x407FB19C) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFU) +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (1) #define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (7U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (0U) +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_NUM_PMSAR (0U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) @@ -149,12 +152,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (1U) #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLL (1U) #define BSP_FEATURE_CGC_HAS_FLWT (1U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (1U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (1U) @@ -178,49 +183,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (0U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (240000000U) -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (240000000U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (240000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000U) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x1U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (1U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (1U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) #define BSP_FEATURE_CRYPTO_HAS_ECC (1) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_HASH (1) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (1) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (1) @@ -253,18 +259,17 @@ #define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) -#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M1 has Data Watchpoint Cycle Count Register +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M1 has Data Watchpoint Cycle Count Register -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (1U) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_CODE_FLASH_START (0x0U) #define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) -#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U) #define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U) #define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U) @@ -277,6 +282,7 @@ #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU @@ -295,31 +301,31 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (80000000U) #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x3FFFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0xFB4FFFFFU) -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) -#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU -#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_IIC_FAST_MODE_PLUS (1U) #define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x03) -#define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) #define BSP_FEATURE_IOPORT_VERSION (1U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) @@ -336,6 +342,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -344,41 +352,43 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) -#define BSP_FEATURE_LPM_HAS_STCONR (1U) -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_STCONR (1U) #define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000FFU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7342FFFFU) #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_MACL_SUPPORTED (0U) #define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) @@ -386,25 +396,25 @@ #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0U) #define BSP_FEATURE_RTC_HAS_TCEN (1U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (3U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) #define BSP_FEATURE_SCI_CHANNELS (0x31FU) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x0U) +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x31FU) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) @@ -414,12 +424,12 @@ #define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) @@ -432,35 +442,43 @@ #define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) #define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U) -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) + +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) -#define BSP_FEATURE_TZ_NS_OFFSET (0U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) + #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_VERSION (0U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (0) // Feature not available on this MCU +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) #define BSP_FEATURE_USB_HAS_USBHS (0U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (1U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0xEU) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (1U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0xEU) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module #endif diff --git a/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature_gen.h index 2502d074a..7a30304f6 100644 --- a/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature_gen.h @@ -231,7 +231,7 @@ #define BSP_PERIPHERAL_IICA_PRESENT (0) #define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_IIRFA_PRESENT (0) -#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0x2) #define BSP_PERIPHERAL_IRDA_PRESENT (1) #define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) #define BSP_PERIPHERAL_IRTC_PRESENT (0) @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h index 22df2bc48..55cfb1fa0 100644 --- a/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h @@ -79,6 +79,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) @@ -86,9 +87,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -115,8 +116,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x407FB19C) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFU) +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (1) #define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (7U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (0U) +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_NUM_PMSAR (0U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) @@ -149,12 +152,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (1U) #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLL (1U) #define BSP_FEATURE_CGC_HAS_FLWT (1U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (1U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (1U) @@ -178,49 +183,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (0U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (240000000U) -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (240000000U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (240000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000U) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x1U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (1U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (1U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) #define BSP_FEATURE_CRYPTO_HAS_ECC (1) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_HASH (1) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (1) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (1) @@ -253,9 +259,8 @@ #define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) -#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M2 has Data Watchpoint Cycle Count Register +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M2 has Data Watchpoint Cycle Count Register -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (1U) #define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU) @@ -277,6 +282,7 @@ #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU @@ -295,31 +301,31 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (80000000U) #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0xFB4FFFFFU) -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) -#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU -#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_IIC_FAST_MODE_PLUS (1U) #define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07) -#define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (1U) #define BSP_FEATURE_IOPORT_VERSION (1U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) @@ -336,6 +342,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -344,41 +352,43 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) -#define BSP_FEATURE_LPM_HAS_STCONR (1U) -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_STCONR (1U) #define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000FFU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7342FFFFU) #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_MACL_SUPPORTED (0U) #define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) @@ -386,25 +396,25 @@ #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0U) #define BSP_FEATURE_RTC_HAS_TCEN (1U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (3U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) #define BSP_FEATURE_SCI_CHANNELS (0x3FFU) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x0U) +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3FFU) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) @@ -414,12 +424,12 @@ #define BSP_FEATURE_SDRAM_START_ADDRESS (0x90000000U) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) @@ -432,35 +442,43 @@ #define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) #define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U) -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) + +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) -#define BSP_FEATURE_TZ_NS_OFFSET (0U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) + #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_VERSION (0U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (0) // Feature not available on this MCU +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) #define BSP_FEATURE_USB_HAS_USBHS (0U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (1U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0xEU) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (1U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0xEU) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module #endif diff --git a/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature_gen.h index c38b79d53..cbc732f91 100644 --- a/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature_gen.h @@ -231,7 +231,7 @@ #define BSP_PERIPHERAL_IICA_PRESENT (0) #define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_IIRFA_PRESENT (0) -#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0x2) #define BSP_PERIPHERAL_IRDA_PRESENT (1) #define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) #define BSP_PERIPHERAL_IRTC_PRESENT (0) @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h index f312d3a1a..1797a714f 100644 --- a/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h @@ -79,6 +79,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) @@ -86,9 +87,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -115,8 +116,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x407FB19C) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFU) +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (1) #define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (7U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (0U) +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_NUM_PMSAR (0U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) @@ -149,12 +152,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (1U) #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLL (1U) #define BSP_FEATURE_CGC_HAS_FLWT (1U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (1U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (1U) @@ -178,49 +183,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (0U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (240000000U) -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (240000000U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (240000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000U) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x1U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (1U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (1U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) #define BSP_FEATURE_CRYPTO_HAS_ECC (1) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_HASH (1) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (1) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (1) @@ -253,9 +259,8 @@ #define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) -#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M3 has Data Watchpoint Cycle Count Register +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M3 has Data Watchpoint Cycle Count Register -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (1U) #define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU) @@ -277,6 +282,7 @@ #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU @@ -295,31 +301,31 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (80000000U) #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0xFF4FFFFFU) -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) -#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU -#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_IIC_FAST_MODE_PLUS (1U) #define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07) -#define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (1U) #define BSP_FEATURE_IOPORT_VERSION (1U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) @@ -336,6 +342,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -344,41 +352,43 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) -#define BSP_FEATURE_LPM_HAS_STCONR (1U) -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_STCONR (1U) #define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000FFU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7342FFFFU) #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_MACL_SUPPORTED (0U) #define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) @@ -386,25 +396,25 @@ #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0U) #define BSP_FEATURE_RTC_HAS_TCEN (1U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (3U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) #define BSP_FEATURE_SCI_CHANNELS (0x3FFU) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x0U) +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3FFU) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) @@ -414,12 +424,12 @@ #define BSP_FEATURE_SDRAM_START_ADDRESS (0x90000000U) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) @@ -432,35 +442,43 @@ #define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) #define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (3U) -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) + +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) -#define BSP_FEATURE_TZ_NS_OFFSET (0U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) + #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_VERSION (0U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (0) // Feature not available on this MCU +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) #define BSP_FEATURE_USB_HAS_USBHS (1U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (1U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (1U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0xEU) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (1U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0xEU) -#define BSP_FEATURE_USB_HAS_USBHS_BC (1U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module #endif diff --git a/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature_gen.h index b7be761e1..6d23363e1 100644 --- a/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature_gen.h @@ -231,7 +231,7 @@ #define BSP_PERIPHERAL_IICA_PRESENT (0) #define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_IIRFA_PRESENT (0) -#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0x2) #define BSP_PERIPHERAL_IRDA_PRESENT (1) #define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) #define BSP_PERIPHERAL_IRTC_PRESENT (0) @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h index ca7f12016..25e8b6965 100644 --- a/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h @@ -79,6 +79,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3F) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) @@ -86,9 +87,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -115,8 +116,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (0) // If MSTPCRE is present then the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U) +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_NUM_PMSAR (9U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) @@ -147,12 +150,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (1U) #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLL (1U) #define BSP_FEATURE_CGC_HAS_FLWT (1U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (1U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (1U) @@ -176,49 +181,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (1U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (200000000U) -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (240000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (120000000U) -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (200000000U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (200000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000U) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (0U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (0U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) #define BSP_FEATURE_CRYPTO_HAS_ECC (1) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_HASH (1) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (1) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) @@ -251,9 +257,8 @@ #define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) -#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M4 has Data Watchpoint Cycle Count Register +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M4 has Data Watchpoint Cycle Count Register -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (1U) #define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU) @@ -275,6 +280,7 @@ #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU @@ -293,21 +299,22 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0x7FB0DFFFFULL) // Note there is another WUPEN1 register -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU @@ -317,7 +324,6 @@ #define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (1U) #define BSP_FEATURE_IOPORT_VERSION (1U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) @@ -334,6 +340,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -342,41 +350,43 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U) +#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STCONR (0U) -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_MACL_SUPPORTED (0U) #define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x68000000U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x70000000U) @@ -384,40 +394,40 @@ #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0U) #define BSP_FEATURE_RTC_HAS_TCEN (0U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (0U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x3F9U) #define BSP_FEATURE_SCI_CHANNELS (0x3FFU) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x0006U) // Channel 1 and channel 2 have ABCSE bit restriction #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x03F9U) // Channel 0, channel 3 to channel 9 have CSTPEN feature +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3F9U) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x0006U) // Channel 1 and channel 2 have ABCSE bit restriction #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // 1 (2^0) is minimum division supported +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // 1 (2^0) is minimum division supported #define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1U) #define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x01U) #define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) @@ -430,35 +440,43 @@ #define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) #define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U) -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) + +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) -#define BSP_FEATURE_TZ_NS_OFFSET (0U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) + #define BSP_FEATURE_TZ_HAS_DLM (1U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_VERSION (1U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (0) // Feature not available on this MCU +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) #define BSP_FEATURE_USB_HAS_USBHS (0U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module #endif diff --git a/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature_gen.h index e2383a632..1d2fac779 100644 --- a/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature_gen.h @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h index 3ab0ff147..23e88bf04 100644 --- a/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h @@ -79,6 +79,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3F) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) @@ -86,9 +87,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1) #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (1) #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -115,8 +116,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (0) // If MSTPCRE is present then the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U) +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_NUM_PMSAR (12U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) @@ -147,12 +150,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (1U) #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLL (1U) #define BSP_FEATURE_CGC_HAS_FLWT (1U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (1U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (1U) @@ -176,49 +181,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (1U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (200000000U) -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (240000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (120000000U) -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (200000000U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (200000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000U) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (0U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (0U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) #define BSP_FEATURE_CRYPTO_HAS_ECC (1) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_HASH (1) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (1) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) @@ -251,9 +257,8 @@ #define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) -#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M5 has Data Watchpoint Cycle Count Register +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M5 has Data Watchpoint Cycle Count Register -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (1U) #define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU) @@ -275,6 +280,7 @@ #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU @@ -293,21 +299,22 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0x7FF0DFFFFULL) // Note there is another WUPEN1 register -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU @@ -317,7 +324,6 @@ #define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (1U) #define BSP_FEATURE_IOPORT_VERSION (1U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) @@ -334,6 +340,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -342,41 +350,43 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U) +#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STCONR (0U) -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_MACL_SUPPORTED (0U) #define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x68000000U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x70000000U) @@ -384,40 +394,40 @@ #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0U) #define BSP_FEATURE_RTC_HAS_TCEN (0U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (0U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x3F9U) #define BSP_FEATURE_SCI_CHANNELS (0x3FFU) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x0006U) // Channel 1 and channel 2 have ABCSE bit restriction #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x03F9U) // Channel 0, channel 3 to channel 9 have CSTPEN feature +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3F9U) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x0006U) // Channel 1 and channel 2 have ABCSE bit restriction #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // 1 (2^0) is minimum division supported +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // 1 (2^0) is minimum division supported #define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1U) #define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x01U) #define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) @@ -430,35 +440,43 @@ #define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) #define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U) -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) + +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) -#define BSP_FEATURE_TZ_NS_OFFSET (0U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) + #define BSP_FEATURE_TZ_HAS_DLM (1U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_VERSION (1U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (0) // Feature not available on this MCU +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) #define BSP_FEATURE_USB_HAS_USBHS (1U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (1U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (1U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (1U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module #endif diff --git a/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature_gen.h index bf318e4c8..fa1e8b5cf 100644 --- a/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature_gen.h @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h index 7744d738a..2666c7f18 100644 --- a/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h @@ -79,6 +79,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) @@ -86,9 +87,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -115,8 +116,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x407FB19C) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFU) +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (1) #define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (7U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (0U) +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_NUM_PMSAR (0U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) @@ -149,12 +152,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLL (1U) #define BSP_FEATURE_CGC_HAS_FLWT (1U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (1U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (1U) @@ -178,49 +183,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (0U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (240000000U) -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (240000000U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (240000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000U) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1U) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1U) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x1U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (1U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (1U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) #define BSP_FEATURE_CRYPTO_HAS_ECC (1) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_HASH (1) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (1) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (1) @@ -253,18 +259,17 @@ #define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) -#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M1 has Data Watchpoint Cycle Count Register +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M1 has Data Watchpoint Cycle Count Register -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0003FFFFU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (1U) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_CODE_FLASH_START (0x0U) #define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) -#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U) #define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U) #define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U) @@ -277,6 +282,7 @@ #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU @@ -295,31 +301,31 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (80000000U) #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x3FFFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0xF04F3FFFU) -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) -#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU -#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_IIC_FAST_MODE_PLUS (1U) #define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x03) -#define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) #define BSP_FEATURE_IOPORT_VERSION (1U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) @@ -336,6 +342,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -344,41 +352,43 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) -#define BSP_FEATURE_LPM_HAS_STCONR (1U) -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_STCONR (1U) #define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000FFU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x70423FFFU) #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_MACL_SUPPORTED (0U) #define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) @@ -386,40 +396,40 @@ #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (0U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0U) #define BSP_FEATURE_RTC_HAS_TCEN (0U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (0U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (0U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) #define BSP_FEATURE_SCI_CHANNELS (0x31FU) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x0U) +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x31FU) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) -#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) @@ -432,35 +442,43 @@ #define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0U) #define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0U) -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) + +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) -#define BSP_FEATURE_TZ_NS_OFFSET (0U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) + #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_VERSION (0U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (0) // Feature not available on this MCU +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) #define BSP_FEATURE_USB_HAS_USBHS (0U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module #endif diff --git a/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature_gen.h index caabdaeb4..d40078b6a 100644 --- a/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature_gen.h @@ -231,7 +231,7 @@ #define BSP_PERIPHERAL_IICA_PRESENT (0) #define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_IIRFA_PRESENT (0) -#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0x1) +#define BSP_PERIPHERAL_IRDA_CHANNEL_MASK (0x2) #define BSP_PERIPHERAL_IRDA_PRESENT (1) #define BSP_PERIPHERAL_IRTC_CHANNEL_MASK (0) #define BSP_PERIPHERAL_IRTC_PRESENT (0) @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h index d69be6898..8ff3d3f95 100644 --- a/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h @@ -79,6 +79,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3U) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) @@ -86,9 +87,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1U) #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (1U) @@ -115,8 +116,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (0) // If MSTPCRE is present then the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U) +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_NUM_PMSAR (16U) // 16 due to offset address change from PMSAR2 to PMSAR3 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) @@ -147,12 +150,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLL (0U) #define BSP_FEATURE_CGC_HAS_FLWT (1U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (1U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (1U) @@ -176,50 +181,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (1U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (240000000U) -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (240000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (120000000U) -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (8000000U) - #define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (240000000U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (240000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000U) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1) #define BSP_FEATURE_CGC_SODRV_MASK (0U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (1U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x4U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (1U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x4U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) #define BSP_FEATURE_CRYPTO_HAS_ECC (0) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) #define BSP_FEATURE_CRYPTO_HAS_HASH (0) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (0) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (1) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) @@ -252,18 +257,17 @@ #define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) -#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M5 has Data Watchpoint Cycle Count Register +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M5 has Data Watchpoint Cycle Count Register -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x31FBF0FFU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (2U) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0U) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_MAX_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0U) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_CODE_FLASH_START (0x0U) #define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000U) -#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U) #define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U) #define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U) @@ -276,6 +280,7 @@ #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU @@ -295,21 +300,22 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (80000000U) #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0) // Feature not available on this MCU +#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0) // Feature not available on this MCU #define BSP_FEATURE_I3C_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (0) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0xF00FFFFFU) // Note there is another WUPEN1 register -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (5U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0x03) @@ -319,7 +325,6 @@ #define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_IOPORT_ELC_PORTS (0x7800U) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) #define BSP_FEATURE_IOPORT_VERSION (2U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) @@ -336,6 +341,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -344,41 +351,43 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) -#define BSP_FEATURE_LPM_HAS_STCONR (0U) -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_STCONR (0U) #define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (1U) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000AFU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7002FFFFU) #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_MACL_SUPPORTED (0U) #define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) @@ -386,41 +395,40 @@ #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (0U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0U) #define BSP_FEATURE_RTC_HAS_TCEN (0U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (0U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (0U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0U) #define BSP_FEATURE_SCI_CHANNELS (0x21FU) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_LIN_CHANNELS (BSP_FEATURE_SCI_CHANNELS) #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x21FU) #define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (1) #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x21FU) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (2U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (BSP_FEATURE_SCI_CHANNELS) -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) -#define BSP_FEATURE_SDHI_CLOCK (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) // Feature not available on this MCU +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) -#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) @@ -428,40 +436,48 @@ #define BSP_FEATURE_SPI_MAX_CHANNEL (2U) #define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x3U) -#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0) // Feature not available on this MCU +#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0) // Feature not available on this MCU + +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0U) // Feature not available on this MCU +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0U) // Feature not available on this MCU -#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (1U) // Trigonometric Function Unit (TFU) available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (1U) // Trigonometric Function Unit (TFU) available on this MCU +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) -#define BSP_FEATURE_TZ_NS_OFFSET (0U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) + #define BSP_FEATURE_TZ_HAS_DLM (1U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_VERSION (1U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (0) // Feature not available on this MCU +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (0U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) #define BSP_FEATURE_USB_HAS_USBHS (0U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module #endif diff --git a/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature_gen.h index 571a8cf84..05b7ec58c 100644 --- a/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature_gen.h @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature.h index 8572cdff3..c2d125cb8 100644 --- a/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature.h @@ -79,6 +79,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3U) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) @@ -86,9 +87,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1) #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (1) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -115,8 +116,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (0) // If MSTPCRE is present then the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U) +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_NUM_PMSAR (9U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) @@ -147,12 +150,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) #define BSP_FEATURE_CGC_HAS_BCLK (0U) #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLL (1U) #define BSP_FEATURE_CGC_HAS_FLWT (1U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (1U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (1U) @@ -176,49 +181,50 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (0U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (240000000U) -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (0U) // Feature not available on this MCU -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (0U) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (240000000U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (240000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000U) +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000U) +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22002222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (0U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (0U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) #define BSP_FEATURE_CRYPTO_HAS_AES (0) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) #define BSP_FEATURE_CRYPTO_HAS_ECC (0) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) #define BSP_FEATURE_CRYPTO_HAS_HASH (0) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_RSA (0) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) @@ -251,14 +257,13 @@ #define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) -#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6T3 has Data Watchpoint Cycle Count Register +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6T3 has Data Watchpoint Cycle Count Register -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0083F3FFU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (1U) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0U) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_MAX_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0U) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_CODE_FLASH_START (0x0U) #define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000U) @@ -275,6 +280,7 @@ #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU @@ -293,21 +299,22 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_I3C_MAX_DEV_COUNT (8U) +#define BSP_FEATURE_I3C_MSTP_OFFSET (4U) #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (16U) #define BSP_FEATURE_I3C_NUM_CHANNELS (1U) -#define BSP_FEATURE_I3C_MSTP_OFFSET (4U) -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x7FFFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0x800780D7FFFULL) // Note there is another WUPEN1 register -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (5U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0x01) @@ -317,7 +324,6 @@ #define BSP_FEATURE_IIC_VERSION (2) #define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) #define BSP_FEATURE_IOPORT_VERSION (1U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) @@ -334,6 +340,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) @@ -342,41 +350,43 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) -#define BSP_FEATURE_LPM_HAS_STCONR (0U) -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_STCONR (0U) #define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (1U) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x70407FFFU) #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_MACL_SUPPORTED (0U) #define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) @@ -384,40 +394,40 @@ #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (0U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0U) #define BSP_FEATURE_RTC_HAS_TCEN (1U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (0U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (2U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x201U) #define BSP_FEATURE_SCI_CHANNELS (0x201U) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x201U) +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x201U) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (1U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) -#define BSP_FEATURE_SDHI_CLOCK (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) // Feature not available on this MCU +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) -#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) @@ -427,39 +437,46 @@ #define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0x01U) -#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0U) // Feature not available on this MCU -#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0U) // Feature not available on this MCU +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_TFU_SUPPORTED (1U) +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU + #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (1U) -#define BSP_FEATURE_TZ_NS_OFFSET (0U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) + #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_VERSION (1U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (1U) +#define BSP_FEATURE_USB_HAS_PIPE04567 (1U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) #define BSP_FEATURE_USB_HAS_USBHS (0U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (1U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1U) // For USB Full-speed module -#define BSP_FEATURE_USB_HAS_NOT_HOST (1U) #endif diff --git a/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature_gen.h index fa5c46235..09497909b 100644 --- a/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature_gen.h @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (0) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0) #define BSP_PERIPHERAL_ULPT_PRESENT (0) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0) diff --git a/ra/fsp/src/bsp/mcu/ra8d1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra8d1/bsp_elc.h index 4f9eb124b..856818083 100644 --- a/ra/fsp/src/bsp/mcu/ra8d1/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra8d1/bsp_elc.h @@ -348,7 +348,7 @@ typedef enum e_elc_event_ra8d1 ELC_EVENT_ADC1_COMPARE_MATCH = (0x1B8), // Compare match ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x1B9), // Compare mismatch ELC_EVENT_DOC_INT = (0x1BA), // Data operation circuit interrupt - ELC_EVENT_RSIP_TADI = (0x1BC), // RSIP Tampler Detection + ELC_EVENT_RSIP_TADI = (0x1BC), // RSIP Tamper Detection ELC_EVENT_GLCDC_LINE_DETECT = (0x1CD), // Specified line ELC_EVENT_GLCDC_UNDERFLOW_1 = (0x1CE), // Graphic 1 underflow ELC_EVENT_GLCDC_UNDERFLOW_2 = (0x1CF), // Graphic 2 underflow diff --git a/ra/fsp/src/bsp/mcu/ra8d1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra8d1/bsp_feature.h index e2cdb5775..4fcfa4983 100644 --- a/ra/fsp/src/bsp/mcu/ra8d1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra8d1/bsp_feature.h @@ -78,6 +78,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3U) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) @@ -85,9 +86,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1U) #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (1U) +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (1) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (1) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -114,8 +115,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (0) // If MSTPCRE is present then the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U) +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_NUM_PMSAR (16U) // 16 due to offset address change from PMSAR2 to PMSAR3 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF1FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) @@ -146,12 +149,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (0) #define BSP_FEATURE_CGC_HAS_BCLK (1U) #define BSP_FEATURE_CGC_HAS_CPUCLK (1U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLL (1U) #define BSP_FEATURE_CGC_HAS_FLWT (1U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (1U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (1U) @@ -175,57 +180,54 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) #define BSP_FEATURE_CGC_MODRV_MASK (0x1EU) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (360000000U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (3U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (3U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (480000000U) -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (40000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (48000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (480000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (40000000U) -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (48000000U) -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLLCCR_TYPE (3U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (1440000000U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (640000000U) +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (360000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (480000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (40000000U) #define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (12000000U) #define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (6000000U) -#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (48000000U) +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) #define BSP_FEATURE_CGC_SODRV_MASK (3U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (8) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0xA5) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x00000000) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (1U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x4U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (1U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x4U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) #define BSP_FEATURE_CRYPTO_HAS_ECC (1) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_HASH (1) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (1) #define BSP_FEATURE_CRYPTO_HAS_RSA (1) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (1) +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE9 (0) -#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (1) #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (0U) // Feature not available on this MCU #define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (0U) // Feature not available on this MCU @@ -254,9 +256,8 @@ #define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) -#define BSP_FEATURE_DWT_CYCCNT (1U) // RA8D1 has Data Watchpoint Cycle Count Register +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA8D1 has Data Watchpoint Cycle Count Register -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x4003FFFFU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (2U) #define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU) @@ -278,6 +279,7 @@ #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU @@ -296,21 +298,22 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) -#define BSP_FEATURE_I3C_NUM_CHANNELS (1U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (1U) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (8U) -#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (16U) #define BSP_FEATURE_I3C_MSTP_OFFSET (4U) -#define BSP_FEATURE_I3C_HAS_HDR_MODE (1U) +#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (16U) +#define BSP_FEATURE_I3C_NUM_CHANNELS (1U) +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (1) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0x00007F08FF1DFFFFU) // Note there is another WUPEN1 register -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (5U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0x01) @@ -320,7 +323,6 @@ #define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) #define BSP_FEATURE_IOPORT_VERSION (2U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (16384UL) @@ -337,6 +339,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (1U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (1U) #define BSP_FEATURE_LPM_HAS_LPSCR (1U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (1U) @@ -345,35 +349,35 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (0U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) +#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STCONR (0U) -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0U) -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (1U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD ((lvd_threshold_t) 0) // 4.29V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD ((lvd_threshold_t) 15) // 1.71V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (30U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD ((lvd_threshold_t) 0) // 4.29V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD ((lvd_threshold_t) 15) // 1.71V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (30U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (30U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (1U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_MACL_SUPPORTED (0U) #define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU @@ -382,30 +386,32 @@ #define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0x80000000U) #define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0x90000000U) +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0) // Feature not available on this MCU #define BSP_FEATURE_RTC_HAS_TCEN (1U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (3U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0U) #define BSP_FEATURE_SCI_CHANNELS (0x21FU) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0x3U) #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (1U) +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x21FU) +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x21FU) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (2U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0x3U) -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) @@ -415,12 +421,12 @@ #define BSP_FEATURE_SDRAM_START_ADDRESS (0x68000000U) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) @@ -433,35 +439,43 @@ #define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) #define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (3U) -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU + +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) -#define BSP_FEATURE_TZ_NS_OFFSET (1U << 28U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) + #define BSP_FEATURE_TZ_HAS_DLM (1U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) +#define BSP_FEATURE_TZ_NS_OFFSET (1U << 28U) #define BSP_FEATURE_TZ_VERSION (2U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (2) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0x3U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (0) // Feature not available on this MCU +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) #define BSP_FEATURE_USB_HAS_USBHS (1U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module #endif diff --git a/ra/fsp/src/bsp/mcu/ra8d1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra8d1/bsp_feature_gen.h index 40061b621..e8772ad37 100644 --- a/ra/fsp/src/bsp/mcu/ra8d1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra8d1/bsp_feature_gen.h @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (1) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0x3) #define BSP_PERIPHERAL_ULPT_PRESENT (1) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0x3) diff --git a/ra/fsp/src/bsp/mcu/ra8m1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra8m1/bsp_elc.h index 5f8dfaae3..e173b3b90 100644 --- a/ra/fsp/src/bsp/mcu/ra8m1/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra8m1/bsp_elc.h @@ -348,7 +348,7 @@ typedef enum e_elc_event_ra8m1 ELC_EVENT_ADC1_COMPARE_MATCH = (0x1B8), // Compare match ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x1B9), // Compare mismatch ELC_EVENT_DOC_INT = (0x1BA), // Data operation circuit interrupt - ELC_EVENT_RSIP_TADI = (0x1BC), // RSIP Tampler Detection + ELC_EVENT_RSIP_TADI = (0x1BC), // RSIP Tamper Detection ELC_EVENT_CEU_CEUI = (0x1DA) // CEU interrupt } elc_event_t; diff --git a/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature.h index 97e2b0877..daa6c54d9 100644 --- a/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature.h @@ -78,6 +78,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3U) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) @@ -85,9 +86,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1U) #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (1U) +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (1) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -114,8 +115,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (0) // If MSTPCRE is present then the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U) +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_NUM_PMSAR (16U) // 16 due to offset address change from PMSAR2 to PMSAR3 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF1FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) @@ -146,12 +149,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (0) #define BSP_FEATURE_CGC_HAS_BCLK (1U) #define BSP_FEATURE_CGC_HAS_CPUCLK (1U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLL (1U) #define BSP_FEATURE_CGC_HAS_FLWT (1U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (1U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (1U) @@ -175,57 +180,54 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) #define BSP_FEATURE_CGC_MODRV_MASK (0x1EU) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (360000000U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (3U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (3U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (480000000U) -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (40000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (48000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (480000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (40000000U) -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (48000000U) -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLLCCR_TYPE (3U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (1440000000U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (640000000U) +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (360000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (480000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (40000000U) #define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (12000000U) #define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (6000000U) -#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (48000000U) +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) #define BSP_FEATURE_CGC_SODRV_MASK (3U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (8) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0xA5) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x00000000) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (1U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x4U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (1U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x4U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) #define BSP_FEATURE_CRYPTO_HAS_ECC (1) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_HASH (1) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (1) #define BSP_FEATURE_CRYPTO_HAS_RSA (1) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (1) +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE9 (0) -#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (1) #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (0U) // Feature not available on this MCU #define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (0U) // Feature not available on this MCU @@ -254,9 +256,8 @@ #define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) -#define BSP_FEATURE_DWT_CYCCNT (1U) // RA8M1 has Data Watchpoint Cycle Count Register +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA8M1 has Data Watchpoint Cycle Count Register -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x4003FFFFU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (2U) #define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU) @@ -278,6 +279,7 @@ #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU @@ -296,21 +298,22 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) -#define BSP_FEATURE_I3C_NUM_CHANNELS (1U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (1U) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (8U) -#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (16U) #define BSP_FEATURE_I3C_MSTP_OFFSET (4U) -#define BSP_FEATURE_I3C_HAS_HDR_MODE (1U) +#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (16U) +#define BSP_FEATURE_I3C_NUM_CHANNELS (1U) +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (1) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0x00007F08FF1DFFFFU) // Note there is another WUPEN1 register -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (5U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0x01) @@ -320,7 +323,6 @@ #define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) #define BSP_FEATURE_IOPORT_VERSION (2U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (16384UL) @@ -337,6 +339,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (1U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (1U) #define BSP_FEATURE_LPM_HAS_LPSCR (1U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (1U) @@ -345,35 +349,35 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (0U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) +#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STCONR (0U) -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0U) -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (1U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD ((lvd_threshold_t) 0) // 4.29V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD ((lvd_threshold_t) 15) // 1.71V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (20U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD ((lvd_threshold_t) 0) // 4.29V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD ((lvd_threshold_t) 15) // 1.71V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (20U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (20U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (1U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_MACL_SUPPORTED (0U) #define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU @@ -382,30 +386,32 @@ #define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0x80000000U) #define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0x90000000U) +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0) // Feature not available on this MCU #define BSP_FEATURE_RTC_HAS_TCEN (1U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (3U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0U) #define BSP_FEATURE_SCI_CHANNELS (0x21FU) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0x3U) #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (1U) +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x21FU) +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x21FU) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (2U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0x3U) -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) @@ -415,12 +421,12 @@ #define BSP_FEATURE_SDRAM_START_ADDRESS (0x68000000U) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) @@ -433,35 +439,43 @@ #define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) #define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (3U) -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU + +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) -#define BSP_FEATURE_TZ_NS_OFFSET (1U << 28U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) + #define BSP_FEATURE_TZ_HAS_DLM (1U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) +#define BSP_FEATURE_TZ_NS_OFFSET (1U << 28U) #define BSP_FEATURE_TZ_VERSION (2U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (2) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0x3U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (0) // Feature not available on this MCU +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) #define BSP_FEATURE_USB_HAS_USBHS (1U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module #endif diff --git a/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature_gen.h index fe7b16ceb..119438f08 100644 --- a/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature_gen.h @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (1) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0x3) #define BSP_PERIPHERAL_ULPT_PRESENT (1) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0x3) diff --git a/ra/fsp/src/bsp/mcu/ra8t1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra8t1/bsp_elc.h index 0ec153943..32277f634 100644 --- a/ra/fsp/src/bsp/mcu/ra8t1/bsp_elc.h +++ b/ra/fsp/src/bsp/mcu/ra8t1/bsp_elc.h @@ -334,7 +334,7 @@ typedef enum e_elc_event_ra8t1 ELC_EVENT_ADC1_COMPARE_MATCH = (0x1B8), // Compare match ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x1B9), // Compare mismatch ELC_EVENT_DOC_INT = (0x1BA), // Data operation circuit interrupt - ELC_EVENT_RSIP_TADI = (0x1BC) // RSIP Tampler Detection + ELC_EVENT_RSIP_TADI = (0x1BC) // RSIP Tamper Detection } elc_event_t; #define BSP_PRV_VECT_ENUM(event,group) (ELC_ ## event) diff --git a/ra/fsp/src/bsp/mcu/ra8t1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra8t1/bsp_feature.h index 263847554..be299bb20 100644 --- a/ra/fsp/src/bsp/mcu/ra8t1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra8t1/bsp_feature.h @@ -78,6 +78,7 @@ #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3U) +#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_FLASH_CACHE (1) #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) @@ -85,9 +86,9 @@ #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1U) #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (1U) +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0) #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (1) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -114,8 +115,10 @@ #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (0) // If MSTPCRE is present then the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U) +#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0) // If MSTPCRE is present then the setting is not valid. #define BSP_FEATURE_BSP_NUM_PMSAR (16U) // 16 due to offset address change from PMSAR2 to PMSAR3 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF1FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) @@ -146,12 +149,14 @@ #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (0) #define BSP_FEATURE_CGC_HAS_BCLK (1U) #define BSP_FEATURE_CGC_HAS_CPUCLK (1U) +#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0) #define BSP_FEATURE_CGC_HAS_FCLK (1U) #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) #define BSP_FEATURE_CGC_HAS_FLL (1U) #define BSP_FEATURE_CGC_HAS_FLWT (1U) #define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_PCLKA (1U) #define BSP_FEATURE_CGC_HAS_PCLKB (1U) #define BSP_FEATURE_CGC_HAS_PCLKC (1U) @@ -175,57 +180,54 @@ #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) #define BSP_FEATURE_CGC_MODRV_MASK (0x1EU) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (360000000U) +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (3U) #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (3U) -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (480000000U) -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (40000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (48000000U) -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (480000000U) #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (40000000U) -#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (48000000U) -#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_PLLCCR_TYPE (3U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (1440000000U) #define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (640000000U) +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (360000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (480000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (40000000U) #define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (12000000U) #define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (6000000U) -#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (48000000U) +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) #define BSP_FEATURE_CGC_REGISTER_SET_B (0) -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) #define BSP_FEATURE_CGC_SODRV_MASK (3U) #define BSP_FEATURE_CGC_SODRV_SHIFT (0U) #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (8) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0xA5) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x00000000) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) -#define BSP_FEATURE_CRC_HAS_SNOOP (1U) -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x4U) #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) +#define BSP_FEATURE_CRC_HAS_SNOOP (1U) #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x4U) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) #define BSP_FEATURE_CRYPTO_HAS_ECC (1) #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_HASH (1) -#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (1) #define BSP_FEATURE_CRYPTO_HAS_RSA (1) #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) -#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (1) +#define BSP_FEATURE_CRYPTO_HAS_RSIP_E11A (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) // Feature not available on this MCU #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE9 (0) -#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (1) #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (0U) // Feature not available on this MCU #define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (0U) // Feature not available on this MCU @@ -254,9 +256,8 @@ #define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4) -#define BSP_FEATURE_DWT_CYCCNT (1U) // RA8T1 has Data Watchpoint Cycle Count Register +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA8T1 has Data Watchpoint Cycle Count Register -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x4003FFFFU) // Deprecated (Removing in FSP v6.0) #define BSP_FEATURE_ELC_VERSION (2U) #define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU) @@ -278,10 +279,12 @@ #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0) // Feature not available on this MCU @@ -295,21 +298,22 @@ #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) -#define BSP_FEATURE_I3C_NUM_CHANNELS (1U) +#define BSP_FEATURE_I3C_HAS_HDR_MODE (1U) #define BSP_FEATURE_I3C_MAX_DEV_COUNT (8U) -#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (16U) #define BSP_FEATURE_I3C_MSTP_OFFSET (4U) -#define BSP_FEATURE_I3C_HAS_HDR_MODE (1U) +#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (16U) +#define BSP_FEATURE_I3C_NUM_CHANNELS (1U) +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_ICU_HAS_FILTER (1U) #define BSP_FEATURE_ICU_HAS_IELSR (1U) #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) #define BSP_FEATURE_ICU_HAS_WUPEN1 (1) -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15U) // Max used index in NMIER +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_ICU_WUPEN_MASK (0x00007F08FF1DFFFFU) // Note there is another WUPEN1 register -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (5U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0x01) @@ -319,7 +323,6 @@ #define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) #define BSP_FEATURE_IOPORT_VERSION (2U) #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (16384UL) @@ -336,6 +339,8 @@ #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0U) #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (1U) +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (1U) #define BSP_FEATURE_LPM_HAS_LPSCR (1U) #define BSP_FEATURE_LPM_HAS_PDRAMSCR (1U) @@ -344,66 +349,69 @@ #define BSP_FEATURE_LPM_HAS_SNOOZE (0U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) +#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STCONR (0U) -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0U) -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0U) // Feature not available on this MCU -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (1U) +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0U) // Feature not available on this MCU +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD ((lvd_threshold_t) 0) // 4.29V #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD ((lvd_threshold_t) 15) // 1.71V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (30U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD ((lvd_threshold_t) 0) // 4.29V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD ((lvd_threshold_t) 15) // 1.71V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (30U) // LVD1 operation stabilization time after LVD1 is enabled #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (30U) // LVD2 operation stabilization time after LVD2 is enabled #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (1U) +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0) // Feature not available on this MCU #define BSP_FEATURE_LVD_VERSION (1U) +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0) // Feature not available on this MCU + +#define BSP_FEATURE_MACL_SUPPORTED (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) -#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) -#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) #define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0x80000000U) #define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0x90000000U) +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0) // Feature not available on this MCU #define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) -#define BSP_FEATURE_HAS_RTC (1U) -#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) -#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_HAS_ROPSEL (0) // Feature not available on this MCU #define BSP_FEATURE_RTC_HAS_TCEN (1U) +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) #define BSP_FEATURE_RTC_RTCCR_CHANNELS (3U) -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0U) #define BSP_FEATURE_SCI_CHANNELS (0x21FU) #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_LIN_CHANNELS (0x3U) #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (1U) +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x21FU) +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0) // Feature not available on this MCU #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x21FU) #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) #define BSP_FEATURE_SCI_VERSION (2U) -#define BSP_FEATURE_SCI_LIN_CHANNELS (0x3U) -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0U) #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) @@ -413,12 +421,12 @@ #define BSP_FEATURE_SDRAM_START_ADDRESS (0x68000000U) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) @@ -431,35 +439,43 @@ #define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) #define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (3U) -#define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) + +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU -#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU -#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU +#define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) -#define BSP_FEATURE_TZ_NS_OFFSET (1U << 28U) -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) + #define BSP_FEATURE_TZ_HAS_DLM (1U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) +#define BSP_FEATURE_TZ_NS_OFFSET (1U << 28U) #define BSP_FEATURE_TZ_VERSION (2U) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0) // Feature not available on this MCU +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0U) // Feature not available on this MCU + #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (2) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0x3U) +#define BSP_FEATURE_USB_HAS_NOT_HOST (0) // Feature not available on this MCU +#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_TYPEC (0) // Feature not available on this MCU #define BSP_FEATURE_USB_HAS_USBFS (1U) +#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) #define BSP_FEATURE_USB_HAS_USBHS (0U) -#define BSP_FEATURE_USB_HAS_PIPE04567 (0U) +#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) #define BSP_FEATURE_USB_HAS_USBLS_PERI (0U) +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module +#define BSP_FEATURE_USB_REG_PHYSLEW (0U) +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0U) #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0U) #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW (0U) -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0U) -#define BSP_FEATURE_USB_HAS_USBHS_BC (0U) -#define BSP_FEATURE_USB_HAS_USBFS_BC (0U) -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0U) // For USB Full-speed module #endif diff --git a/ra/fsp/src/bsp/mcu/ra8t1/bsp_feature_gen.h b/ra/fsp/src/bsp/mcu/ra8t1/bsp_feature_gen.h index 0c8ea78f5..81f9162cc 100644 --- a/ra/fsp/src/bsp/mcu/ra8t1/bsp_feature_gen.h +++ b/ra/fsp/src/bsp/mcu/ra8t1/bsp_feature_gen.h @@ -385,6 +385,8 @@ #define BSP_PERIPHERAL_TZF_NS_PRESENT (1) #define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0) #define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) #define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0x3) #define BSP_PERIPHERAL_ULPT_PRESENT (1) #define BSP_PERIPHERAL_ULPT_NS_CHANNEL_MASK (0x3) diff --git a/ra/fsp/src/r_agt/r_agt.c b/ra/fsp/src/r_agt/r_agt.c index 810dc626d..4f936319d 100644 --- a/ra/fsp/src/r_agt/r_agt.c +++ b/ra/fsp/src/r_agt/r_agt.c @@ -728,17 +728,6 @@ static fsp_err_t r_agt_open_param_checking (agt_instance_ctrl_t * p_instance_ctr agt_extended_cfg_t const * p_extend = (agt_extended_cfg_t const *) p_cfg->p_extend; FSP_ASSERT((AGT_CLOCK_AGT_UNDERFLOW != p_extend->count_source) || (p_cfg->channel & 1U)); - /* Devices with RTCCR.TCEN support P402/P403/P404 as count sources. */ - #if !BSP_FEATURE_RTC_HAS_TCEN - if (AGT_PRV_IS_AGTW(p_instance_ctrl)) - { - /* Return error for MCUs that do not support P402, P403 and P404 as count sources*/ - FSP_ASSERT(AGT_CLOCK_P402 != p_extend->count_source); - FSP_ASSERT(AGT_CLOCK_P403 != p_extend->count_source); - FSP_ASSERT(AGT_CLOCK_P404 != p_extend->count_source); - } - #endif - /* Validate divider. */ if (AGT_CLOCK_PCLKB == p_extend->count_source) { diff --git a/ra/fsp/src/r_can/r_can.c b/ra/fsp/src/r_can/r_can.c index 1a9e4ba9b..f75c44823 100644 --- a/ra/fsp/src/r_can/r_can.c +++ b/ra/fsp/src/r_can/r_can.c @@ -360,11 +360,13 @@ fsp_err_t R_CAN_Open (can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p_c } } - /* Set the Mask as invalid for mailboxes that do not use the mask. */ - p_reg->MKIVLR = ~(mask_enabled); - #if CAN_CFG_FIFO_SUPPORT + /* Set the Mask as invalid for mailboxes that do not use the mask. + * Bits 24:31 in MKIVLR must not be set in FIFO mode (see Note 1 in Section 37.2.5 "Mask Invalid Register (MKIVLR) + * of the RA6M3 User's Manual (R01UH0886EJ0120)). */ + p_reg->MKIVLR = ~(mask_enabled) & CAN_MKIVLR_FIFO_MASK; + /* Get pointer to RX FIFO configuration */ can_rx_fifo_cfg_t * p_rx_fifo_cfg = p_extend->p_rx_fifo_cfg; @@ -385,6 +387,10 @@ fsp_err_t R_CAN_Open (can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p_c p_reg->MKR[6] = mask1; p_reg->MKR[7] = mask2; +#else + + /* Set the Mask as invalid for mailboxes that do not use the mask. */ + p_reg->MKIVLR = ~(mask_enabled); #endif /* Go to normal operation. */ diff --git a/ra/fsp/src/r_ceu/r_ceu.c b/ra/fsp/src/r_ceu/r_ceu.c index 21f5d6f08..378a0b3fd 100644 --- a/ra/fsp/src/r_ceu/r_ceu.c +++ b/ra/fsp/src/r_ceu/r_ceu.c @@ -211,7 +211,7 @@ fsp_err_t R_CEU_Close (capture_ctrl_t * const p_ctrl) ceu_disable_interrupts(p_instance_ctrl); - R_CEU->CAPSR = R_CEU_CAPSR_CPKIL_Msk; // Setting the CPKIL starts + R_CEU->CAPSR = R_CEU_CAPSR_CPKIL_Msk; // Setting the CPKIL stops capture /* Mark driver as closed * [Note] Set interface as closed after disabling interrupts to fascilitate any API calls in the application callback */ @@ -238,8 +238,9 @@ fsp_err_t R_CEU_Close (capture_ctrl_t * const p_ctrl) * @retval FSP_ERR_ASSERTION One or more parameters is NULL. * @retval FSP_ERR_NOT_OPEN Open has not been successfully called. * @retval FSP_ERR_INVALID_ADDRESS Invalid buffer address alignment. - * @retval FSP_ERR_IN_USE CEU is already in use. - * @retval FSP_ERR_NOT_INITIALIZED Callback function has not been set + * @retval FSP_ERR_IN_USE Capture is in progress. + * @retval FSP_ERR_INVALID_STATE Capture is pending. + * @retval FSP_ERR_NOT_INITIALIZED Callback function has not been set. **************************************************************************************************************************/ fsp_err_t R_CEU_CaptureStart (capture_ctrl_t * const p_ctrl, uint8_t * const p_buffer) { @@ -257,6 +258,7 @@ fsp_err_t R_CEU_CaptureStart (capture_ctrl_t * const p_ctrl, uint8_t * const p_b * Refer to figure 53.6 "Timing of software reset and restart of capturing" in the RA8M1 manual R01UH0994EJ0100. */ FSP_ERROR_RETURN(R_CEU->CSTSR_b.CPTON == 0x0, FSP_ERR_IN_USE); FSP_ERROR_RETURN(R_CEU->CAPSR_b.CPKIL == 0x0, FSP_ERR_IN_USE); + FSP_ERROR_RETURN(R_CEU->CAPSR_b.CE == 0x0, FSP_ERR_INVALID_STATE); ceu_extended_cfg_t * p_extend = (ceu_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; diff --git a/ra/fsp/src/r_i3c/r_i3c.c b/ra/fsp/src/r_i3c/r_i3c.c index 536456b39..a5d62b3f5 100644 --- a/ra/fsp/src/r_i3c/r_i3c.c +++ b/ra/fsp/src/r_i3c/r_i3c.c @@ -10,12 +10,9 @@ #include "r_i3c.h" #include "r_i3c_cfg.h" -/* The address of the MCU Version Register on RA2E2/RA2L2 MCUs. Different error recovery procedures are used depending on the - * version of the MCU (This is only used on RA2E2/RA2L2 devices). */ -#define I3C_A2E2_VERSION (*((uint8_t const *) 0x01001C20U)) - -/* Version of the MCU (This is only used on RA2L2_EK Boards). */ -#define I3C_A2L2_VERSION_1 51U +/* The address of the MCU Version Register on RA2E2 MCUs. Different error recovery procedures are used depending on the + * version of the MCU (This is only used on RA2E2 devices). */ +#define I3C_A2E2_VERSION (*((uint8_t const *) 0x01001C20U)) /*********************************************************************************************************************** * Typedef definitions @@ -1757,7 +1754,7 @@ void i3c_resp_isr (void) #if I3C_ERROR_RECOVERY_VERSION_1 == I3C_CFG_ERROR_RECOVERY_SUPPORT || \ I3C_ERROR_RECOVERY_VERSION_BOTH == I3C_CFG_ERROR_RECOVERY_SUPPORT #if I3C_ERROR_RECOVERY_VERSION_BOTH == I3C_CFG_ERROR_RECOVERY_SUPPORT - if ((1U == I3C_A2E2_VERSION) || (I3C_A2L2_VERSION_1 == I3C_A2E2_VERSION)) + if (1U == I3C_A2E2_VERSION) #endif { /* If the transfer length is less than expected, the driver must perform error recovery defined in @@ -2321,7 +2318,7 @@ void i3c_master_error_recovery (i3c_instance_ctrl_t * p_ctrl, bool error_recover /* For A2E2 version that has not been modified by ECO, the following error recovery procedure must be performed. * See Figure 25.96 in the hardware user manual R01UH0919EJ0100. */ - if ((1U == I3C_A2E2_VERSION) || (I3C_A2L2_VERSION_1 == I3C_A2E2_VERSION)) + if (1U == I3C_A2E2_VERSION) #endif { /* Flush the Command, Rx and Tx Buffers. */ @@ -2512,7 +2509,7 @@ void i3c_slave_error_recovery (i3c_instance_ctrl_t * p_ctrl, i3c_slave_error_rec /* For A2E2 version that has not been modified by ECO, the following error recovery procedure must be performed. * See Figure 25.97 in the hardware user manual R01UH0919EJ0100. */ - if ((1U == I3C_A2E2_VERSION) || (I3C_A2L2_VERSION_1 == I3C_A2E2_VERSION)) + if (1U == I3C_A2E2_VERSION) #endif { /* Wait for Bus Available Condition (See Figure 25.97 in the hardware user manual R01UH0919EJ0100). */ diff --git a/ra/fsp/src/r_iica_master/r_iica_master.c b/ra/fsp/src/r_iica_master/r_iica_master.c index a67bf84e5..7bca926c6 100644 --- a/ra/fsp/src/r_iica_master/r_iica_master.c +++ b/ra/fsp/src/r_iica_master/r_iica_master.c @@ -227,7 +227,7 @@ fsp_err_t R_IICA_MASTER_Abort (i2c_master_ctrl_t * const p_api_ctrl) #endif /* Abort any transfer happening on the channel */ - r_iica_master_abort_seq_master(p_ctrl, true); + r_iica_master_abort_seq_master(p_ctrl, false); return FSP_SUCCESS; } @@ -456,14 +456,22 @@ static void r_iica_master_abort_seq_master (iica_master_instance_ctrl_t * const R_IICA->IICCTL00_b.LREL = 1; /* Reset the peripheral */ - if (true == iica_reset) + if (false == iica_reset) { /* Disable interrupts */ R_IICA->IICCTL00_b.SPIE = 0U; - - /* This helper function would do a full IICA reset - * followed by re-initializing the required peripheral registers. */ - r_iica_master_open_hw_master(p_ctrl, p_ctrl->p_cfg); + } + else + { + /* Disable IICA */ + R_IICA->IICCTL00_b.IICE = 0U; + iica_master_extended_cfg_t * pextend = (iica_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + /* Disable Pin settings */ + R_BSP_PinAccessEnable(); + R_BSP_PinCfg(pextend->scl_pin_settings.pin, IOPORT_CFG_PORT_DIRECTION_INPUT); + R_BSP_PinCfg(pextend->sda_pin_settings.pin, IOPORT_CFG_PORT_DIRECTION_INPUT); + R_BSP_PinAccessDisable(); } /* Update the transfer descriptor to show no longer in-progress and an error */ @@ -572,7 +580,7 @@ static void r_iica_master_txrxi_master (iica_master_instance_ctrl_t * p_ctrl) { /* If the event was an error event, then handle it */ uint8_t reg_iics0 = R_IICA->IICS0; - if (((!(reg_iics0 & R_IICA_IICS0_ACKD_Msk) && (reg_iics0 & R_IICA_IICS0_TRC_Msk)) || + if (((!(reg_iics0 & R_IICA_IICS0_ACKD_Msk) && !(p_ctrl->dummy_read_completed)) || !(reg_iics0 & R_IICA_IICS0_MSTS_Msk) || ((reg_iics0 & R_IICA_IICS0_ALD_Msk))) && !(reg_iics0 & R_IICA_IICS0_SPD_Msk)) { diff --git a/ra/fsp/src/r_lpm/r_lpm.c b/ra/fsp/src/r_lpm/r_lpm.c index d85085285..561118438 100644 --- a/ra/fsp/src/r_lpm/r_lpm.c +++ b/ra/fsp/src/r_lpm/r_lpm.c @@ -17,6 +17,7 @@ #define LPM_LPSCR_SYSTEM_ACTIVE (0x0U) #define LPM_LPSCR_SOFTWARE_STANDBY_MODE (0x4U) +#define LPM_LPSCR_SOFTWARE_STANDBY_MODE2 (0x5U) #define LPM_LPSCR_DEEP_SOFTWARE_STANDBY_MODE1 (0x8U) #define LPM_LPSCR_DEEP_SOFTWARE_STANDBY_MODE2 (0x9U) #define LPM_LPSCR_DEEP_SOFTWARE_STANDBY_MODE3 (0xAU) @@ -678,9 +679,12 @@ fsp_err_t r_lpm_configure (lpm_cfg_t const * const p_cfg) #if BSP_FEATURE_ICU_WUPEN_MASK > 0 R_ICU->WUPEN = (uint32_t) p_cfg->standby_wake_sources & UINT32_MAX; #endif -#if BSP_FEATURE_ICU_HAS_WUPEN1 == 1 +#if BSP_FEATURE_ICU_HAS_WUPEN1 R_ICU->WUPEN1 = (uint32_t) (p_cfg->standby_wake_sources >> LPM_WUPEN1_OFFSET) & UINT32_MAX; #endif +#if BSP_FEATURE_ICU_HAS_WUPEN2 + R_ICU->WUPEN2 = (uint32_t) p_cfg->standby_wake_sources_2 & UINT32_MAX; +#endif #if BSP_FEATURE_ICU_SBYEDCR_MASK > 0 sbyedcr0 |= (uint32_t) p_cfg->standby_wake_sources & UINT32_MAX; sbyedcr1 |= (uint32_t) (p_cfg->standby_wake_sources >> LPM_SBYEDCR1_OFFSET) & UINT32_MAX; diff --git a/ra/fsp/src/r_mipi_dsi/r_mipi_dsi.c b/ra/fsp/src/r_mipi_dsi/r_mipi_dsi.c index b3aa26771..729908b14 100644 --- a/ra/fsp/src/r_mipi_dsi/r_mipi_dsi.c +++ b/ra/fsp/src/r_mipi_dsi/r_mipi_dsi.c @@ -411,20 +411,28 @@ fsp_err_t R_MIPI_DSI_UlpsExit (mipi_dsi_ctrl_t * const p_api_ctrl, mipi_dsi_lane * @retval FSP_ERR_IN_USE The physical interface is currently in use or video mode is in operation. * @retval FSP_ERR_INVALID_POINTER Invalid pointer provided * @retval FSP_ERR_INVALID_ARGUMENT Invalid message configuration - * @retval FSP_ERR_INVALID_CHANNEL Invalid channel for provided message configuration **********************************************************************************************************************/ fsp_err_t R_MIPI_DSI_Command (mipi_dsi_ctrl_t * const p_api_ctrl, mipi_dsi_cmd_t * p_cmd) { +#define SQCHnSET0R_BIT_23 (0x800000) +#define SEQUENCE_REGISTERS_SIZE (offsetof(R_DSILINK_Type, SQCH1DSC0AR) - offsetof(R_DSILINK_Type, SQCH0DSC0AR)) // 0x80 + #if MIPI_DSI_CFG_PARAM_CHECKING_ENABLE mipi_dsi_instance_ctrl_t * p_ctrl = (mipi_dsi_instance_ctrl_t *) p_api_ctrl; FSP_ASSERT(NULL != p_ctrl); FSP_ERROR_RETURN(p_cmd, FSP_ERR_INVALID_POINTER); +#endif + + bool lp = (0 != (p_cmd->flags & MIPI_DSI_CMD_FLAG_LOW_POWER)); + uint8_t sequence_channel = (lp ? 0 : 1); // Sequence Channel (distinct from Virtual Channel) + +#if MIPI_DSI_CFG_PARAM_CHECKING_ENABLE FSP_ERROR_RETURN(MIPI_DSI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); - FSP_ERROR_RETURN(p_cmd->p_tx_buffer || (p_cmd->tx_len == 0), FSP_ERR_INVALID_ARGUMENT); // Tx buffer must be supplied for non-zero Tx length + FSP_ERROR_RETURN(p_cmd->p_tx_buffer || (p_cmd->tx_len == 0), FSP_ERR_INVALID_ARGUMENT); // Tx buffer must be supplied for non-zero Tx length - FSP_ERROR_RETURN(!((p_cmd->channel == 0) && (p_cmd->tx_len > MIPI_MAX_CH0_CMD)), FSP_ERR_INVALID_ARGUMENT); // Max Tx size is 128 for channel 0 - FSP_ERROR_RETURN(!((p_cmd->channel == 1) && (p_cmd->tx_len > MIPI_MAX_CH1_CMD)), FSP_ERR_INVALID_ARGUMENT); // Max Tx size is 1k for channel 1 + FSP_ERROR_RETURN(!((sequence_channel == 0) && (p_cmd->tx_len > MIPI_MAX_CH0_CMD)), FSP_ERR_INVALID_ARGUMENT); // Max Tx size is 128 for channel 0 (LP Mode) + FSP_ERROR_RETURN(!((sequence_channel == 1) && (p_cmd->tx_len > MIPI_MAX_CH1_CMD)), FSP_ERR_INVALID_ARGUMENT); // Max Tx size is 1k for channel 1 (HS Mode) /* AUX Operation */ bool aux = (p_cmd->flags & MIPI_DSI_CMD_FLAG_AUX_OPERATION); @@ -435,14 +443,11 @@ fsp_err_t R_MIPI_DSI_Command (mipi_dsi_ctrl_t * const p_api_ctrl, mipi_dsi_cmd_t bool initial_skew = (p_cmd->flags & MIPI_DSI_CMD_FLAG_ACT_CODE_INITIAL_SKEW_CAL); bool periodic_skew = (p_cmd->flags & MIPI_DSI_CMD_FLAG_ACT_CODE_PERIODIC_SKEW_CAL); FSP_ERROR_RETURN(!bta && !p_cmd->tx_len, FSP_ERR_INVALID_ARGUMENT); - FSP_ERROR_RETURN(!R_DSILINK->LINKSR_b.VRUN, FSP_ERR_INVALID_ARGUMENT); // Aux operation is prohibited when video mode is running - FSP_ERROR_RETURN(!(initial_skew || periodic_skew) || (p_cmd->channel != 0), FSP_ERR_INVALID_ARGUMENT); // Periodic and Initial skew must be HS + FSP_ERROR_RETURN(!R_DSILINK->LINKSR_b.VRUN, FSP_ERR_INVALID_ARGUMENT); // Aux operation is prohibited when video mode is running + FSP_ERROR_RETURN(!(initial_skew || periodic_skew) || (sequence_channel == 1), FSP_ERR_INVALID_ARGUMENT); // Periodic and Initial skew must be HS } - uint8_t lp = (0 != (p_cmd->flags & MIPI_DSI_CMD_FLAG_LOW_POWER)); - - FSP_ERROR_RETURN(!(lp && R_DSILINK->LINKSR_b.VRUN), FSP_ERR_IN_USE); // LP not allowed during video mode operation. See RA8D1 UM 58.2.61 (R01UH0995EJ0060) - FSP_ERROR_RETURN(!(lp && (p_cmd->channel != 0)), FSP_ERR_INVALID_CHANNEL); // LP only allowed on channel 0 + FSP_ERROR_RETURN(!(lp && R_DSILINK->LINKSR_b.VRUN), FSP_ERR_IN_USE); // LP not allowed during video mode operation. See RA8D1 UM 58.2.61 (R01UH0995EJ0060) #else FSP_PARAMETER_NOT_USED(p_api_ctrl); #endif @@ -451,23 +456,26 @@ fsp_err_t R_MIPI_DSI_Command (mipi_dsi_ctrl_t * const p_api_ctrl, mipi_dsi_cmd_t FSP_ERROR_RETURN(!(R_DSILINK->LINKSR_b.SQ0RUN) && !(R_DSILINK->LINKSR_b.SQ1RUN), FSP_ERR_IN_USE); uint32_t * p_sequence_reg = (uint32_t *) (&R_DSILINK->SQCH0DSC0AR); - p_sequence_reg += (p_cmd->channel * 0x80) / 4; // NOLINT(readability-magic-numbers) + p_sequence_reg += (sequence_channel * SEQUENCE_REGISTERS_SIZE) / sizeof(uint32_t); // Offset into Sequence register 'n' *p_sequence_reg++ = dsi_cmd_sequence_register_a(p_cmd); *p_sequence_reg++ = dsi_cmd_sequence_register_b(p_cmd); *p_sequence_reg++ = dsi_cmd_sequence_register_c(p_cmd); *p_sequence_reg++ = dsi_cmd_sequence_register_d(p_cmd); /* Start sequence operation */ - R_DSILINK->SQCH0SET0R = (bool) (0 == p_cmd->channel); - R_DSILINK->SQCH1SET0R = (bool) (1 == p_cmd->channel); + R_DSILINK->SQCH0SET0R = SQCHnSET0R_BIT_23 | (0 == sequence_channel); + R_DSILINK->SQCH1SET0R = SQCHnSET0R_BIT_23 | (1 == sequence_channel); return FSP_SUCCESS; +#undef SQCHnSET0R_BIT_23 +#undef SEQUENCE_REGISTERS_SIZE } /******************************************************************************************************************//** * Provide information about current MIPI DSI status. * - * Note: Acknowledge and Error Status is only cleared when read by calling this function. + * Note: Accumulated Acknowledge and Error (AwER) Status is cleared by calling this function. Latest AwER status is + * only set upon reception from peripheral. * * @retval FSP_SUCCESS Information read successfully. * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. diff --git a/ra/fsp/src/r_ospi_b/r_ospi_b.c b/ra/fsp/src/r_ospi_b/r_ospi_b.c index 3a17847b6..e9a758ee3 100644 --- a/ra/fsp/src/r_ospi_b/r_ospi_b.c +++ b/ra/fsp/src/r_ospi_b/r_ospi_b.c @@ -9,6 +9,7 @@ **********************************************************************************************************************/ #include "bsp_api.h" #include "r_ospi_b.h" +#include #if OSPI_B_CFG_DMAC_SUPPORT_ENABLE #include "r_transfer_api.h" @@ -16,7 +17,13 @@ #endif #if OSPI_B_CFG_DOTF_SUPPORT_ENABLE - #include "hw_sce_ra_private.h" +#if defined OSPI_B_CFG_DOTF_PROTECTED_MODE_SUPPORT_ENABLE +#include "r_rsip_api.h" +#include "r_rsip_public.h" +extern rsip_instance_t const * const gp_rsip_instance; +#else +#include "hw_sce_ra_private.h" +#endif #endif /*********************************************************************************************************************** @@ -1211,6 +1218,86 @@ static ospi_b_xspi_command_set_t const * r_ospi_b_command_set_get (ospi_b_instan #if OSPI_B_CFG_DOTF_SUPPORT_ENABLE +#if defined OSPI_B_CFG_DOTF_PROTECTED_MODE_SUPPORT_ENABLE +/*******************************************************************************************************************//** + * Configures the device for DOTF operation. + * + * @param[in] p_dotf_cfg Pointer to the instance ctrl struct. + * @retval FSP_SUCCESS DOTF configuration completed successfully. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Key initialization failed. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Key wrapping failed. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid key type argument. + **********************************************************************************************************************/ +static fsp_err_t r_ospi_b_dotf_setup (ospi_b_dotf_cfg_t * p_dotf_cfg) +{ + fsp_err_t sce_ret = FSP_SUCCESS; + uint8_t seed[8] = {0}; + + if (OSPI_B_DOTF_KEY_FORMAT_WRAPPED != p_dotf_cfg->format) + { + return FSP_ERR_INVALID_ARGUMENT; + } + + static uint8_t s_wrapped_key[RSIP_BYTE_SIZE_WRAPPED_KEY_RSA_4096_PRIVATE]; + rsip_wrapped_key_t * p_wrapped_key = (rsip_wrapped_key_t *) s_wrapped_key; + p_wrapped_key->alg = (uint8_t) RSIP_ALG_AES; + + if (OSPI_B_DOTF_AES_KEY_TYPE_128 == p_dotf_cfg->key_type) + { + p_wrapped_key->subtype = RSIP_KEY_AES_128; + memcpy(p_wrapped_key->value, p_dotf_cfg->p_key, RSIP_BYTE_SIZE_WRAPPED_KEY_AES_128); + } + else if (OSPI_B_DOTF_AES_KEY_TYPE_192 == p_dotf_cfg->key_type) + { + return FSP_ERR_INVALID_ARGUMENT; + } + else if (OSPI_B_DOTF_AES_KEY_TYPE_256 == p_dotf_cfg->key_type) + { + p_wrapped_key->subtype = RSIP_KEY_AES_256; + memcpy(p_wrapped_key->value, p_dotf_cfg->p_key, RSIP_BYTE_SIZE_WRAPPED_KEY_AES_256); + } + else + { + } + + + sce_ret = gp_rsip_instance->p_api->open(gp_rsip_instance->p_ctrl, gp_rsip_instance->p_cfg); + if (FSP_SUCCESS != sce_ret) + { + return sce_ret; + } + + sce_ret = gp_rsip_instance->p_api->otfInit(gp_rsip_instance->p_ctrl, RSIP_OTF_CHANNEL_0, p_wrapped_key, &seed[0]); + if (FSP_SUCCESS != sce_ret) + { + return sce_ret; + } + + sce_ret = gp_rsip_instance->p_api->close(gp_rsip_instance->p_ctrl); + if (FSP_SUCCESS != sce_ret) + { + return sce_ret; + } + + if (sce_ret == FSP_SUCCESS) + { + /* Disable byte order conversion. */ + R_DOTF->REG00 = (OSPI_B_PRV_DOTF_REG00_RESET_VALUE | R_DOTF_REG00_B09_Msk); + + /* Load the IV. */ + R_DOTF->REG03 = bswap_32big(p_dotf_cfg->p_iv[0]); + R_DOTF->REG03 = bswap_32big(p_dotf_cfg->p_iv[1]); + R_DOTF->REG03 = bswap_32big(p_dotf_cfg->p_iv[2]); + R_DOTF->REG03 = bswap_32big(p_dotf_cfg->p_iv[3]); + } + + /* Set the start and end area for DOTF conversion. */ + R_DOTF->CONVAREAST = (uint32_t) p_dotf_cfg->p_start_addr; + R_DOTF->CONVAREAD = (uint32_t) p_dotf_cfg->p_end_addr; + + return sce_ret; +} +#else /*******************************************************************************************************************//** * Configures the device for DOTF operation. * @@ -1227,9 +1314,9 @@ static fsp_err_t r_ospi_b_dotf_setup (ospi_b_dotf_cfg_t * p_dotf_cfg) uint32_t wrapped_key[HW_SCE_AES256_KEY_INDEX_WORD_SIZE] = {0}; sce_oem_cmd_t key_cmd = SCE_OEM_CMD_AES128; - if((((uint32_t) &(p_dotf_cfg->p_key[0])) & 0x03) && (((uint32_t) &(p_dotf_cfg->p_iv[0])) & 0x03)) + if ((((uint32_t) &(p_dotf_cfg->p_key[0])) & 0x03) && (((uint32_t) &(p_dotf_cfg->p_iv[0])) & 0x03)) { - return FSP_ERR_INVALID_ARGUMENT; + return FSP_ERR_INVALID_ARGUMENT; } if (OSPI_B_DOTF_AES_KEY_TYPE_128 == p_dotf_cfg->key_type) @@ -1252,17 +1339,38 @@ static fsp_err_t r_ospi_b_dotf_setup (ospi_b_dotf_cfg_t * p_dotf_cfg) /* Initialize the crypto engine. */ HW_SCE_McuSpecificInit(); - /* Copnvert plaintext key to wrapped form. */ - sce_ret = - HW_SCE_GenerateOemKeyIndexPrivate(SCE_OEM_KEY_TYPE_PLAIN, - key_cmd, - NULL, - NULL, - (uint8_t *) p_dotf_cfg->p_key, - (uint32_t *) wrapped_key); - if (FSP_SUCCESS != sce_ret) + if (OSPI_B_DOTF_KEY_FORMAT_PLAINTEXT == p_dotf_cfg->format) { - return sce_ret; + /* Convert plaintext key to wrapped form. */ + sce_ret = + HW_SCE_GenerateOemKeyIndexPrivate(SCE_OEM_KEY_TYPE_PLAIN, + key_cmd, + NULL, + NULL, + (uint8_t *) p_dotf_cfg->p_key, + (uint32_t *) wrapped_key); + if (FSP_SUCCESS != sce_ret) + { + return sce_ret; + } + } + else + { + if (OSPI_B_DOTF_AES_KEY_TYPE_128 == p_dotf_cfg->key_type) + { + memcpy(wrapped_key, p_dotf_cfg->p_key, HW_SCE_AES128_KEY_INDEX_WORD_SIZE * 4); + } + else if (OSPI_B_DOTF_AES_KEY_TYPE_192 == p_dotf_cfg->key_type) + { + memcpy(wrapped_key, p_dotf_cfg->p_key, HW_SCE_AES192_KEY_INDEX_WORD_SIZE * 4); + } + else if (OSPI_B_DOTF_AES_KEY_TYPE_256 == p_dotf_cfg->key_type) + { + memcpy(wrapped_key, p_dotf_cfg->p_key, HW_SCE_AES256_KEY_INDEX_WORD_SIZE * 4); + } + else + { + } } /* Use wrapped key with DOTF AES Engine. */ @@ -1299,3 +1407,4 @@ static fsp_err_t r_ospi_b_dotf_setup (ospi_b_dotf_cfg_t * p_dotf_cfg) } #endif +#endif diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_util.h b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_util.h index f9d8ca8ac..b922c8d71 100644 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_util.h +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_util.h @@ -28,7 +28,7 @@ * IAR Embedded Workbench: "size" (enabled only if default optimization level is "high") * Other toolchains: no change */ -#if defined(__GNUC__) +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) && !defined(__llvm__) #define RSIP_PRV_PRIMITIVE_FUNC __attribute__((optimize("Os"))) #elif defined(__ICCARM__) #define RSIP_PRV_PRIMITIVE_FUNC _Pragma("optimize = size") diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private.c index ec6606876..1b14b0b1e 100644 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private.c +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private.c @@ -287,8 +287,8 @@ #define RSIP_PRV_FUNC_ECDSA_VERIFY_SECP521R1 RSIP_PRV_FUNC_NAME_ECDSA_VERIFY_SECP521R1 #else #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP521R1 NULL - #define RSIP_PRV_FUNC_KEY_WRAP_ECC_SECP521R1_PUBLIC NULL - #define RSIP_PRV_FUNC_KEY_WRAP_ECC_SECP521R1_PRIVATE NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP521R1_PUBLIC NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP521R1_PRIVATE NULL #define RSIP_PRV_FUNC_ECDSA_SIGN_SECP521R1 NULL #define RSIP_PRV_FUNC_ECDSA_VERIFY_SECP521R1 NULL diff --git a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2c.c b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2c.c index 6adbeb1a2..fbae98bb5 100644 --- a/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2c.c +++ b/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2c.c @@ -21,10 +21,6 @@ rsip_ret_t r_rsip_p2c (const uint32_t InData_KeyIndex[], const uint32_t InData_D { return RSIP_RET_RESOURCE_CONFLICT; } - else - { - ; - } WR1_PROG(REG_1B00H, 0x002c0001U); WR1_PROG(REG_144CH, 0x00000000U); @@ -103,9 +99,14 @@ rsip_ret_t r_rsip_p2c (const uint32_t InData_KeyIndex[], const uint32_t InData_D WAIT_STS(REG_1404H, 30, 0); WR1_PROG(REG_143CH, 0x00001800U); - r_rsip_func100(bswap_32big(0xc5b5de78U), bswap_32big(0x00c794f6U), bswap_32big(0x822ba7c8U), bswap_32big(0xe8e25b68U)); + r_rsip_func100(bswap_32big(0xd6446ed6U), bswap_32big(0x844d807dU), bswap_32big(0x4701e6a3U), bswap_32big(0xd90b30deU)); WR1_PROG(REG_1438H, 0x40000110U); + WR1_PROG(REG_1400H, 0x02000011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xea310309U), bswap_32big(0xcdea15b9U), bswap_32big(0x4b530004U), bswap_32big(0xacca6c86U)); WR1_PROG(REG_1600H, 0x00000821U); WR1_PROG(REG_1608H, 0x81840001U); WR1_PROG(REG_1400H, 0x02090011U); @@ -120,7 +121,7 @@ rsip_ret_t r_rsip_p2c (const uint32_t InData_KeyIndex[], const uint32_t InData_D WR1_PROG(REG_1420H, InData_DOTFSEED[1]); WR1_PROG(REG_1458H, 0x00000000U); - r_rsip_func100(bswap_32big(0x5a9e4e44U), bswap_32big(0x2a729015U), bswap_32big(0x227783abU), bswap_32big(0x2304d62fU)); + r_rsip_func100(bswap_32big(0x4b09bad8U), bswap_32big(0x7cf5ec6fU), bswap_32big(0xd91a3e0aU), bswap_32big(0xab56dd86U)); WR1_PROG(REG_1438H, 0x40000140U); WR1_PROG(REG_1608H, 0x81020000U); @@ -128,7 +129,7 @@ rsip_ret_t r_rsip_p2c (const uint32_t InData_KeyIndex[], const uint32_t InData_D WAIT_STS(REG_1404H, 30, 0); WR1_PROG(REG_143CH, 0x00001800U); - r_rsip_func102(bswap_32big(0xe60fa700U), bswap_32big(0x2c07b97aU), bswap_32big(0xb19b1bc4U), bswap_32big(0xbfc20bb7U)); + r_rsip_func102(bswap_32big(0xe53bf0f4U), bswap_32big(0x1d2adf54U), bswap_32big(0x1556405bU), bswap_32big(0x7ce73748U)); WR1_PROG(REG_14BCH, 0x00000040U); WAIT_STS(REG_142CH, 12, 0); diff --git a/ra/fsp/src/r_rtc/r_rtc.c b/ra/fsp/src/r_rtc/r_rtc.c index 4dda2b179..2a309e8ce 100644 --- a/ra/fsp/src/r_rtc/r_rtc.c +++ b/ra/fsp/src/r_rtc/r_rtc.c @@ -213,7 +213,7 @@ fsp_err_t R_RTC_Open (rtc_ctrl_t * const p_ctrl, rtc_cfg_t const * const p_cfg) /* Verify the frequency comparison value for RFRL when using LOCO */ if (RTC_CLOCK_SOURCE_LOCO == p_cfg->clock_source) { - FSP_ERROR_RETURN(FSP_SUCCESS != r_rtc_rfrl_validate(p_cfg->freq_compare_value), FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(FSP_SUCCESS == r_rtc_rfrl_validate(p_cfg->freq_compare_value), FSP_ERR_INVALID_ARGUMENT); } /* Validate the error adjustment parameters when using SubClock */ else @@ -1240,8 +1240,8 @@ static fsp_err_t r_rtc_rfrl_validate (uint32_t value) /* A value from 0007h through 01FFh can be specified as the frequency comparison value (see section 26.2.20 * Frequency Register (RFRH/RFRL)" of the RA6M3 manual R01UH0886EJ0100) */ - if ((RTC_RFRL_MIN_VALUE_LOCO <= value) && - (RTC_RFRL_MAX_VALUE_LOCO >= value)) + if ((RTC_RFRL_MIN_VALUE_LOCO >= value) || + (RTC_RFRL_MAX_VALUE_LOCO <= value)) { err = FSP_ERR_INVALID_ARGUMENT; } diff --git a/ra/fsp/src/r_sau_uart/r_sau_uart.c b/ra/fsp/src/r_sau_uart/r_sau_uart.c index 2214cedbf..d017fc0ca 100644 --- a/ra/fsp/src/r_sau_uart/r_sau_uart.c +++ b/ra/fsp/src/r_sau_uart/r_sau_uart.c @@ -24,22 +24,30 @@ #define SAU1_SPS_REG_INIT ((BSP_CFG_SAU_CK11_DIV << R_SAU0_SPS_PRS1_Pos) | BSP_CFG_SAU_CK10_DIV) #if SAU_UART_CFG_SINGLE_CHANNEL > 2 + #define SAU_DEFINE_LOCALS(p_ctrl) /* Not used. All compile time macros instead. */ #define SAU_REG (R_SAU1) #define SAU_UNIT (1) #define SAU_TX_INDEX ((SAU_UART_CFG_SINGLE_CHANNEL - 3) << 1) #define SAU_RX_INDEX (SAU_TX_INDEX + 1) #define SAU_SPS_REG_INIT (SAU1_SPS_REG_INIT) #elif SAU_UART_CFG_SINGLE_CHANNEL > 0 + #define SAU_DEFINE_LOCALS(p_ctrl) /* Not used. All compile time macros instead. */ #define SAU_REG (R_SAU0) #define SAU_UNIT (0) #define SAU_TX_INDEX ((SAU_UART_CFG_SINGLE_CHANNEL - 1) << 1) #define SAU_RX_INDEX (SAU_TX_INDEX + 1) #define SAU_SPS_REG_INIT (SAU0_SPS_REG_INIT) #else - #define SAU_REG (p_ctrl->p_reg) - #define SAU_UNIT (p_ctrl->sau_unit) - #define SAU_TX_INDEX (p_ctrl->sau_tx_channel) - #define SAU_RX_INDEX (p_ctrl->sau_tx_channel + 1) + #define SAU_DEFINE_LOCALS(p_ctrl) R_SAU0_Type * const _p_reg = (p_ctrl)->p_reg; \ + const uint8_t _sau_unit = (p_ctrl)->sau_unit; \ + const uint8_t _sau_tx_index = (p_ctrl)->sau_tx_channel; \ + const uint8_t _sau_rx_index = (p_ctrl)->sau_tx_channel + 1; \ + /* These locals will not always be used. Void cast to quiet unused variable warn */ \ + (void) _p_reg; (void) _sau_unit; (void) _sau_tx_index; (void) _sau_rx_index + #define SAU_REG (_p_reg) + #define SAU_UNIT (_sau_unit) + #define SAU_TX_INDEX (_sau_tx_index) + #define SAU_RX_INDEX (_sau_rx_index) #define SAU_SPS_REG_INIT (SAU_UNIT ? SAU1_SPS_REG_INIT : SAU0_SPS_REG_INIT) #endif @@ -119,6 +127,7 @@ void sau_uart_txi_isr(void); #endif #if SAU_UART_CFG_DTC_SUPPORT_ENABLE +static fsp_err_t r_sau_uart_transfer_disable(transfer_instance_t const * const p_transfer); static fsp_err_t r_sau_uart_transfer_configure(sau_uart_instance_ctrl_t * const p_ctrl); #endif @@ -202,6 +211,8 @@ fsp_err_t R_SAU_UART_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * co #if !SAU_UART_CFG_SINGLE_CHANNEL + /* Don't use the macros here since the macros use defined locals which copy from p_ctrl. */ + /* Each SAU can contain up to two UART channels */ p_ctrl->sau_unit = p_cfg->channel / 2; @@ -209,13 +220,15 @@ fsp_err_t R_SAU_UART_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * co p_ctrl->sau_tx_channel = (uint8_t) ((p_cfg->channel & 1) << 1); p_ctrl->p_reg = (R_SAU0_Type *) (R_SAU0_BASE + (SAU_REG_CHANNEL_SIZE * p_ctrl->sau_unit)); + + SAU_DEFINE_LOCALS(p_ctrl); #endif p_ctrl->p_cfg = p_cfg; p_ctrl->p_callback = p_cfg->p_callback; p_ctrl->p_context = p_cfg->p_context; - p_ctrl->extra_data_byte = UART_DATA_BITS_9 == p_cfg->data_bits; + p_ctrl->extra_data_byte = (UART_DATA_BITS_9 == p_cfg->data_bits); #if SAU_UART_CFG_DTC_SUPPORT_ENABLE @@ -274,6 +287,8 @@ fsp_err_t R_SAU_UART_Close (uart_ctrl_t * const p_api_ctrl) FSP_ERROR_RETURN(SAU_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); #endif + SAU_DEFINE_LOCALS(p_ctrl); + /* Mark the channel not open so other APIs cannot use it. */ p_ctrl->open = 0U; @@ -345,6 +360,8 @@ static void r_sau_uart_config_set (sau_uart_instance_ctrl_t * const p_ctrl, uart #endif sau_uart_extended_cfg_t * p_extend_cfg = (sau_uart_extended_cfg_t *) p_cfg->p_extend; + SAU_DEFINE_LOCALS(p_ctrl); + #if (0 == SAU_UART_CFG_FIXED_BAUDRATE_ENABLE) sau_uart_baudrate_setting_t * p_sau_baud_setting = p_extend_cfg->p_baudrate; @@ -381,45 +398,56 @@ static void r_sau_uart_config_set (sau_uart_instance_ctrl_t * const p_ctrl, uart /* Set SDR register value. */ SAU_REG->SDR[SAU_TX_INDEX] = (uint16_t) (p_extend_cfg->p_baudrate->stclk << R_SAU0_SDR_STCLK_Pos); + const uint16_t tx_mask = (uint16_t) (1U << SAU_TX_INDEX); + const uint16_t tx_clr_mask = (uint16_t) ~tx_mask; +#else + + /* Configure register SMR setting (setting for transmit channel in Reception only mode). */ + SAU_REG->SMR[SAU_TX_INDEX] = SAU_UART_SMR_DEFAULT_VALUE | + (uint16_t) (p_extend_cfg->p_baudrate->operation_clock << R_SAU0_SMR_CKS_Pos) | + SAU_UART_SMR_STS_TRIGGER_RXD | + SAU_UART_SMR_MD1_UART_MODE; +#endif + SAU_CRITICAL_SECTION_ENTER(); +#if SAU_UART_CFG_TX_ENABLE /* Output levels cannot be changed while output is enabled. Disable, make changes, then re-enable. */ - uint16_t reg_soe = (uint16_t) (SAU_REG->SOE & ~(1U << SAU_TX_INDEX)); + uint16_t reg_soe = (uint16_t) (SAU_REG->SOE & tx_clr_mask); SAU_REG->SOE = reg_soe; /* Set the idle output level and signal level for the UART TX pin. */ + uint16_t reg_sol = SAU_REG->SOL; + uint16_t reg_so = SAU_REG->SO; + if (SAU_UART_SIGNAL_LEVEL_INVERTED == p_extend_cfg->signal_level) { - SAU_REG->SOL |= (uint16_t) (1U << SAU_TX_INDEX); // Inverted signal - SAU_REG->SO &= (uint16_t) ~(1U << SAU_TX_INDEX); // Set idle to low + reg_sol |= tx_mask; // Inverted signal + reg_so &= tx_clr_mask; // Set idle to low } else { - SAU_REG->SOL &= (uint16_t) ~(1U << SAU_TX_INDEX); // Normal signal - SAU_REG->SO |= (uint16_t) (1U << SAU_TX_INDEX); // Set idle to high + reg_sol &= tx_clr_mask; // Normal signal + reg_so |= tx_mask; // Set idle to high } - /* Configure register SOE setting to enable serial output. */ - SAU_REG->SOE = (uint16_t) (reg_soe | (1U << SAU_TX_INDEX)); + SAU_REG->SOL = reg_sol; + SAU_REG->SO = reg_so; - SAU_CRITICAL_SECTION_EXIT(); -#else - - /* Configure register SMR setting (setting for transmit channel in Reception only mode). */ - SAU_REG->SMR[SAU_TX_INDEX] = SAU_UART_SMR_DEFAULT_VALUE | - (uint16_t) (p_extend_cfg->p_baudrate->operation_clock << R_SAU0_SMR_CKS_Pos) | - SAU_UART_SMR_STS_TRIGGER_RXD | - SAU_UART_SMR_MD1_UART_MODE; + /* Configure register SOE setting to enable serial output. */ + SAU_REG->SOE = (uint16_t) (reg_soe | tx_mask); #endif -#if (SAU_UART_CFG_RX_ENABLE) +#if SAU_UART_CFG_RX_ENABLE /* Configure register SNFENn setting. * Use a critical section since I2C and SPI need this to be disabled for their channels. */ - SAU_CRITICAL_SECTION_ENTER(); R_PORGA->SNFEN |= (uint8_t) (R_PORGA_SNFEN_SNFEN00_Msk << (p_cfg->channel << 1)); +#endif SAU_CRITICAL_SECTION_EXIT(); +#if (SAU_UART_CFG_RX_ENABLE) + /* Configure register SIR setting. */ SAU_REG->SIR[SAU_RX_INDEX] = (uint16_t) (SAU_UART_SIR_FRAME_ERROR_CLEAR | SAU_UART_SIR_PARITY_ERROR_CLEAR | @@ -476,6 +504,8 @@ fsp_err_t R_SAU_UART_Read (uart_ctrl_t * const p_api_ctrl, uint8_t * const p_des FSP_ERROR_RETURN(0U == p_ctrl->rx_count, FSP_ERR_IN_USE); #endif + SAU_DEFINE_LOCALS(p_ctrl); + /* Total number of words to read in this transfer. * Bytes is total length of the buffer, so for 9-bit it needs to be divided by 2. */ uint32_t words = bytes >> p_ctrl->extra_data_byte; @@ -544,6 +574,8 @@ fsp_err_t R_SAU_UART_Write (uart_ctrl_t * const p_api_ctrl, uint8_t const * cons FSP_ERROR_RETURN(p_ctrl->p_cfg, FSP_ERR_INVALID_ARGUMENT); #endif + SAU_DEFINE_LOCALS(p_ctrl); + /* Total number of words to write in this transfer. * Bytes is total length of the buffer, so for 9-bit it needs to be divided by 2. * Subtract one to take into account the manual write at the end of this function. */ @@ -580,16 +612,20 @@ fsp_err_t R_SAU_UART_Write (uart_ctrl_t * const p_api_ctrl, uint8_t const * cons /* Manually write the first data word. * Use p_src instead of p_ctrl->p_src because the latter is already adjusted for the next byte. */ + uint16_t data_word = 0; + if (p_ctrl->extra_data_byte) { /* Using 2 data bytes for 9-bit transfers. */ - SAU_REG->SDR[SAU_TX_INDEX] = *((uint16_t *) p_src); + data_word = *((uint16_t *) p_src); } else { - SAU_REG->SDR[SAU_TX_INDEX] = *p_src; + data_word = *p_src; } + SAU_REG->SDR[SAU_TX_INDEX] = data_word; + R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->txi_irq); return FSP_SUCCESS; @@ -637,6 +673,8 @@ fsp_err_t R_SAU_UART_BaudSet (uart_ctrl_t * const p_api_ctrl, void const * const FSP_ERROR_RETURN(SAU_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); #endif + SAU_DEFINE_LOCALS(p_ctrl); + uint16_t reg_ss = 0U; #if (SAU_UART_CFG_TX_ENABLE) reg_ss |= (uint16_t) (SAU_UART_ST_START_TRG_ON << SAU_TX_INDEX); @@ -773,54 +811,71 @@ fsp_err_t R_SAU_UART_InfoGet (uart_ctrl_t * const p_api_ctrl, uart_info_t * cons **********************************************************************************************************************/ fsp_err_t R_SAU_UART_Abort (uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort) { +#if !(SAU_UART_CFG_TX_ENABLE) && !(SAU_UART_CFG_RX_ENABLE) + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(communication_to_abort); + + return FSP_ERR_UNSUPPORTED; +#else sau_uart_instance_ctrl_t * p_ctrl = (sau_uart_instance_ctrl_t *) p_api_ctrl; - fsp_err_t err = FSP_ERR_UNSUPPORTED; + fsp_err_t err = FSP_SUCCESS; -#if (SAU_UART_CFG_PARAM_CHECKING_ENABLE) + #if (SAU_UART_CFG_TX_ENABLE) || (SAU_UART_CFG_DTC_SUPPORT_ENABLE) + uart_cfg_t const * const p_cfg = p_ctrl->p_cfg; + #endif + + #if (SAU_UART_CFG_PARAM_CHECKING_ENABLE) FSP_ASSERT(p_ctrl); FSP_ERROR_RETURN(SAU_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); -#endif + #endif -#if (SAU_UART_CFG_TX_ENABLE) + #if (SAU_UART_CFG_TX_ENABLE) if (UART_DIR_TX & communication_to_abort) { - err = FSP_SUCCESS; - R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); - - #if SAU_UART_CFG_DTC_SUPPORT_ENABLE - transfer_instance_t const * const p_dtc_tx = p_ctrl->p_cfg->p_transfer_tx; - if (NULL != p_dtc_tx) - { - err = p_dtc_tx->p_api->disable(p_dtc_tx->p_ctrl); - } - #endif - + R_BSP_IrqDisable(p_cfg->txi_irq); p_ctrl->tx_count = 0; + + #if SAU_UART_CFG_DTC_SUPPORT_ENABLE + err = r_sau_uart_transfer_disable(p_cfg->p_transfer_tx); FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + #endif } -#endif + #endif -#if (SAU_UART_CFG_RX_ENABLE) + #if (SAU_UART_CFG_RX_ENABLE) if (UART_DIR_RX & communication_to_abort) { - err = FSP_SUCCESS; - - #if SAU_UART_CFG_DTC_SUPPORT_ENABLE - transfer_instance_t const * const p_dtc_rx = p_ctrl->p_cfg->p_transfer_rx; - if (NULL != p_dtc_rx) - { - err = p_dtc_rx->p_api->disable(p_dtc_rx->p_ctrl); - } - #endif + #if SAU_UART_CFG_DTC_SUPPORT_ENABLE + err = r_sau_uart_transfer_disable(p_cfg->p_transfer_rx); + #endif p_ctrl->rx_count = 0; - FSP_ERROR_RETURN(FSP_SUCCESS == err, err); } -#endif + #endif return err; +#endif } +#if SAU_UART_CFG_DTC_SUPPORT_ENABLE + +/** + * Performs a NULL check and disables a transfer instance. + * @param[in] p_transfer Transfer instance to disable + * @return The error code from the disable api or FSP_SUCCESS if p_transfer is NULL. + */ +static fsp_err_t r_sau_uart_transfer_disable (transfer_instance_t const * const p_transfer) +{ + if (NULL == p_transfer) + { + return FSP_SUCCESS; + } + + return p_transfer->p_api->disable(p_transfer->p_ctrl); +} + +#endif + /*******************************************************************************************************************//** * Provides API to abort ongoing read. Reception is still enabled after abort(). Any characters received after abort() * and before the transfer is reset in the next call to read(), will arrive via the callback function with event @@ -903,6 +958,8 @@ fsp_err_t R_SAU_UART_BaudCalculate (sau_uart_instance_ctrl_t * const p_ctrl, FSP_ERROR_RETURN(SAU_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); #endif + SAU_DEFINE_LOCALS(p_ctrl); + #if SAU_UART_CFG_SINGLE_CHANNEL FSP_PARAMETER_NOT_USED(p_ctrl); #endif @@ -998,6 +1055,8 @@ static fsp_err_t r_sau_uart_transfer_configure (sau_uart_instance_ctrl_t * const fsp_err_t err = FSP_SUCCESS; transfer_info_t * p_info = NULL; + SAU_DEFINE_LOCALS(p_ctrl); + #if (SAU_UART_CFG_RX_ENABLE) transfer_instance_t const * p_transfer_rx = p_ctrl->p_cfg->p_transfer_rx; @@ -1099,6 +1158,9 @@ void sau_uart_txi_isr (void) /* Recover ISR context saved in open. */ sau_uart_instance_ctrl_t * p_ctrl = (sau_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + SAU_DEFINE_LOCALS(p_ctrl); + uint16_t reg_smr = SAU_REG->SMR[SAU_TX_INDEX]; if ((p_ctrl->tx_count) && (NULL == p_ctrl->p_cfg->p_transfer_rx)) @@ -1168,7 +1230,10 @@ void sau_uart_rxi_isr (void) /* Recover ISR context saved in open. */ sau_uart_instance_ctrl_t * p_ctrl = (sau_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); - const uint16_t data = SAU_REG->SDR[SAU_RX_INDEX]; + + SAU_DEFINE_LOCALS(p_ctrl); + + const uint16_t data = SAU_REG->SDR[SAU_RX_INDEX]; if (!p_ctrl->rx_count) { @@ -1227,6 +1292,8 @@ void sau_uart_eri_isr (void) /* Recover ISR context saved in open. */ sau_uart_instance_ctrl_t * p_ctrl = (sau_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + SAU_DEFINE_LOCALS(p_ctrl); + /* The data buffer must be read as part of clearing the error to avoid an overrun error after recovery. */ const uint16_t data = SAU_REG->SDR[SAU_RX_INDEX]; const uint16_t ssr_reg = SAU_REG->SSR[SAU_RX_INDEX]; diff --git a/ra/fsp/src/r_sce/aes2/adaptors/hw_sce_ra_private.h b/ra/fsp/src/r_sce/aes2/adaptors/hw_sce_ra_private.h index 79eb17f02..08186a4c0 100644 --- a/ra/fsp/src/r_sce/aes2/adaptors/hw_sce_ra_private.h +++ b/ra/fsp/src/r_sce/aes2/adaptors/hw_sce_ra_private.h @@ -191,6 +191,16 @@ fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub(const uint32_t * InData_KeyType, const uint32_t * InData_Cmd, const uint32_t * InData_KeyIndex, const uint32_t * InData_IV); +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSubAdaptor(const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]); +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSubAdaptor(const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]); void HW_SCE_Aes256EncryptDecryptUpdateSub(const uint32_t * InData_Text, uint32_t * OutData_Text, const uint32_t MAX_CNT); @@ -391,4 +401,41 @@ fsp_err_t HW_SCE_Aes256CcmDecryptFinalSub(const uint32_t InData_Text[], const uint32_t InData_MACLength[], uint32_t OutData_Text[]); +fsp_err_t HW_SCE_Aes128GcmEncryptInitSubGeneral(uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum); +fsp_err_t HW_SCE_Aes128GcmDecryptInitSubGeneral(uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum); +fsp_err_t HW_SCE_Aes192GcmDecryptInitSubGeneral(uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum); +fsp_err_t HW_SCE_Aes192GcmEncryptInitSubGeneral(uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum); +fsp_err_t HW_SCE_Aes256GcmDecryptInitSubGeneral(uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum); +fsp_err_t HW_SCE_Aes256GcmEncryptInitSubGeneral(uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum); + #endif /* HW_SCE_RA_PRIVATE_HEADER_FILE */ diff --git a/ra/fsp/src/r_sce/aes2/adaptors/r_sce_AES_adapt.c b/ra/fsp/src/r_sce/aes2/adaptors/r_sce_AES_adapt.c index 9f52380a6..592dc73a1 100644 --- a/ra/fsp/src/r_sce/aes2/adaptors/r_sce_AES_adapt.c +++ b/ra/fsp/src/r_sce/aes2/adaptors/r_sce_AES_adapt.c @@ -1382,3 +1382,109 @@ fsp_err_t HW_SCE_Aes256CcmDecryptFinalSub (const uint32_t InData_Text[], return err; } + +fsp_err_t HW_SCE_Aes128GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes128GcmEncryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes128GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes128GcmDecryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes192GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes192GcmEncryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes192GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes192GcmDecryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes256GcmEncryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes256GcmDecryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_Key); + + return HW_SCE_Aes128EncryptDecryptInitSub(InData_KeyMode, InData_Cmd, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_Key); + + return HW_SCE_Aes256EncryptDecryptInitSub(InData_KeyMode, InData_Cmd, InData_KeyIndex, InData_IV); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/adaptors/r_sce_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/adaptors/r_sce_adapt.c index d28ae8be5..165f3309e 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/adaptors/r_sce_adapt.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/adaptors/r_sce_adapt.c @@ -170,6 +170,26 @@ fsp_err_t HW_SCE_GenerateOemKeyIndexPrivate (const sce_oem_key_type_t key_type, key_index); } +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_Key); + return HW_SCE_Aes128EncryptDecryptInitSub(InData_KeyMode, InData_Cmd, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_Key); + return HW_SCE_Aes256EncryptDecryptInitSub(InData_KeyMode, InData_Cmd, InData_KeyIndex, InData_IV); +} + fsp_err_t HW_SCE_Aes128CmacInit(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[]) { return HW_SCE_Aes128CmacInitSub(InData_KeyType, InData_KeyIndex); @@ -248,6 +268,64 @@ fsp_err_t HW_SCE_Aes128GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, return (HW_SCE_Aes128GcmDecryptInitSub (InData_KeyType, InData_DataType, InData_Cmd, InData_KeyIndex, InData_IV, InData_SeqNum)); } +fsp_err_t HW_SCE_Aes192GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes192GcmEncryptInitSub(InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes192GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes192GcmDecryptInitSub(InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes256GcmEncryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes256GcmDecryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} + fsp_err_t HW_SCE_Aes128CcmEncryptInitSubGeneral (uint32_t InData_KeyType[], uint32_t InData_DataType[], uint32_t InData_Cmd[], diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/private/inc/hw_sce_ra_private.h b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/private/inc/hw_sce_ra_private.h index c0a2c0d27..e81a82640 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/private/inc/hw_sce_ra_private.h +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/private/inc/hw_sce_ra_private.h @@ -224,6 +224,12 @@ fsp_err_t HW_SCE_Aes256CmacInitSub(const uint32_t InData_KeyType[], const uint32 void HW_SCE_Aes256CmacUpdateSub(const uint32_t InData_Text[], const uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub(void); fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub (const uint32_t InData_KeyType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]); +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_Key[], const uint32_t InData_IV[]); fsp_err_t HW_SCE_Aes256EncryptDecryptFinalSub(void); fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub (const uint32_t InData_KeyType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); fsp_err_t HW_SCE_GenerateRandomNumberSub (uint32_t OutData_Text[]); @@ -395,5 +401,13 @@ fsp_err_t HW_SCE_Aes128GcmEncryptInitSubGeneral (uint32_t *InData_KeyType, uint3 uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); fsp_err_t HW_SCE_Aes128GcmDecryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes192GcmDecryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes192GcmEncryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes256GcmDecryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes256GcmEncryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); #endif /* HW_SCE_RA_PRIVATE_HEADER_FILE */ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/public/inc/r_sce_if.h b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/public/inc/r_sce_if.h index 06de493bc..52f450c31 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/public/inc/r_sce_if.h +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/public/inc/r_sce_if.h @@ -63,9 +63,9 @@ #define HW_SCE_MAC_SIZE (16U) /* For AES operation. */ - #define HW_SCE_AES128_KEY_INDEX_WORD_SIZE (12U) - #define HW_SCE_AES192_KEY_INDEX_WORD_SIZE (16U) - #define HW_SCE_AES256_KEY_INDEX_WORD_SIZE (16U) + #define HW_SCE_AES128_KEY_INDEX_WORD_SIZE (9U) + #define HW_SCE_AES192_KEY_INDEX_WORD_SIZE (13U) + #define HW_SCE_AES256_KEY_INDEX_WORD_SIZE (13U) #define HW_SCE_AES128_KEY_WORD_SIZE (4U) #define HW_SCE_AES192_KEY_WORD_SIZE (8U) #define HW_SCE_AES256_KEY_WORD_SIZE (8U) diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/adaptors/r_sce_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/adaptors/r_sce_adapt.c new file mode 100644 index 000000000..8df7761f2 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/adaptors/r_sce_adapt.c @@ -0,0 +1,840 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "../private/inc/SCE_ProcCommon.h" +#include "hw_sce_ra_private.h" +#include "hw_sce_private.h" +#include "hw_sce_trng_private.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +uint32_t S_RAM[HW_SCE_SRAM_WORD_SIZE]; +uint32_t S_HEAP[HW_SCE_SHEAP_WORD_SIZE]; +uint32_t S_INST[HW_SCE_SINST_WORD_SIZE]; +uint32_t S_INST2[HW_SCE_SINST2_WORD_SIZE]; + +uint32_t INST_DATA_SIZE; +uint32_t KEY_INDEX_SIZE; +/******************************************************* + * The following are valid SCE lifecycle states: + * + * CM1(Lifecycle state) + * + * CM2(Lifecycle state) + * + * SSD(Lifecycle state) + * + * NSECSD(Lifecycle state) + * + * DPL(Lifecycle state) + * + * LCK_DBG(Lifecycle state) + * + * LCK_BOOT(Lifecycle state) + * + * RMA_REQ(Lifecycle state) + * + * RMA_ACK(Lifecycle state) + ****************************************************/ + +#define R_RSIP_LITTLE_ENDIAN_MODE (0x00010001) +#define FSP_RSIP_DLMMON_MASK (0x0000000F) /* for lcs in stored in R_PSCU->DLMMON */ + +const uint32_t sce_oem_key_size[SCE_OEM_CMD_NUM] = +{ + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_AES128_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_AES192_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_AES256_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_AES128_XTS_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_AES256_XTS_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA1024_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA1024_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA2048_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA2048_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA3072_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA3072_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA4096_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA4096_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP192_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP192_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP224_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP224_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP256_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP256_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP384_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP384_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_HMAC_SHA224_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_HMAC_SHA256_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP256R1_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP256R1_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP384R1_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP384R1_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP512R1_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP512R1_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCSECP256K1_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCSECP256K1_PRIVATE_KEY_INST_DATA_WORD, +}; + +fsp_err_t HW_SCE_HUK_Load_LCS (void) +{ + uint32_t lc_state = R_PSCU->DLMMON & FSP_RSIP_DLMMON_MASK; + + return HW_SCE_LoadHukSub(&lc_state); +} + +fsp_err_t HW_SCE_McuSpecificInit (void) +{ + fsp_err_t iret = FSP_ERR_CRYPTO_SCE_FAIL; + + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + /* Power on the SCE module */ + HW_SCE_PowerOn(); + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); + HW_SCE_SoftwareResetSub(); + iret = HW_SCE_SelfCheck1Sub(); + if (FSP_SUCCESS == iret) + { + /* Change SCE to little endian mode */ + SCE->REG_18H = R_RSIP_LITTLE_ENDIAN_MODE; + SCE->REG_1CH = R_RSIP_LITTLE_ENDIAN_MODE; + + /* This check is moved from before the endian setting for the updated fastboot procedures */ + iret = HW_SCE_SelfCheck2Sub(); + } + + if (FSP_SUCCESS == iret) + { + iret = HW_SCE_HUK_Load_LCS(/* please try OEM mode when HUK load primitive executing */); + } + + return iret; +} + +fsp_err_t HW_SCE_RNG_Read (uint32_t * OutData_Text) +{ + if (FSP_SUCCESS != HW_SCE_GenerateRandomNumberSub(OutData_Text)) + { + return FSP_ERR_CRYPTO_SCE_FAIL; + } + + return FSP_SUCCESS; +} + +fsp_err_t HW_SCE_GenerateOemKeyIndexPrivate (const sce_oem_key_type_t key_type, + const sce_oem_cmd_t cmd, + const uint8_t * encrypted_provisioning_key, + const uint8_t * iv, + const uint8_t * encrypted_oem_key, + uint32_t * key_index) +{ + uint32_t indata_key_type[1] = {0}; + uint32_t indata_cmd[1] = {0}; + uint32_t install_key_ring_index[1] = {0}; + indata_key_type[0] = key_type; + indata_cmd[0] = change_endian_long(cmd); + install_key_ring_index[0] = 0U; + + INST_DATA_SIZE = sce_oem_key_size[cmd] - 4U; + KEY_INDEX_SIZE = sce_oem_key_size[cmd] + 1U; + + /* Casting uint32_t pointer is used for address. */ + return HW_SCE_GenerateOemKeyIndexSub(indata_key_type, + indata_cmd, + install_key_ring_index, + (uint32_t *) encrypted_provisioning_key, + (uint32_t *) iv, + (uint32_t *) encrypted_oem_key, + key_index); +} + +uint32_t change_endian_long (uint32_t a) +{ + return __REV(a); +} + +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + return HW_SCE_Aes128EncryptDecryptInitSub(InData_KeyMode, InData_Cmd, InData_KeyIndex, InData_Key, InData_IV); +} + +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + return HW_SCE_Aes256EncryptDecryptInitSub(InData_KeyMode, InData_Cmd, InData_KeyIndex, InData_Key, InData_IV); +} + +fsp_err_t HW_SCE_Aes128CmacInit(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[]) +{ + FSP_PARAMETER_NOT_USED (InData_KeyType); + FSP_PARAMETER_NOT_USED (InData_KeyIndex); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_Aes192CmacInit(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[]) +{ + FSP_PARAMETER_NOT_USED (InData_KeyType); + FSP_PARAMETER_NOT_USED (InData_KeyIndex); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_Aes256CmacInit(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[]) +{ + FSP_PARAMETER_NOT_USED (InData_KeyType); + FSP_PARAMETER_NOT_USED (InData_KeyIndex); + return FSP_ERR_UNSUPPORTED; +} + +void HW_SCE_Aes128CmacUpdate(const uint32_t InData_Text[], const uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED (InData_Text); + FSP_PARAMETER_NOT_USED (MAX_CNT); +} + +void HW_SCE_Aes192CmacUpdate(const uint32_t InData_Text[], const uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED (InData_Text); + FSP_PARAMETER_NOT_USED (MAX_CNT); +} + +fsp_err_t HW_SCE_Aes192EncryptDecryptInitSub (const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV) +{ + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_IV); + + return FSP_ERR_UNSUPPORTED; +} + +void HW_SCE_Aes192EncryptDecryptUpdateSub (const uint32_t * InData_Text, uint32_t * OutData_Text, + const uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(MAX_CNT); +} + +fsp_err_t HW_SCE_Aes192EncryptDecryptFinalSub (void) +{ + return FSP_ERR_UNSUPPORTED; +} + +void HW_SCE_Aes256CmacUpdate(const uint32_t InData_Text[], const uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED (InData_Text); + FSP_PARAMETER_NOT_USED (MAX_CNT); +} + +fsp_err_t HW_SCE_Aes128CmacFinal(const uint32_t InData_Cmd[], + const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_DataT[]) +{ + FSP_PARAMETER_NOT_USED (InData_Cmd); + FSP_PARAMETER_NOT_USED (InData_Text); + FSP_PARAMETER_NOT_USED (InData_DataT); + FSP_PARAMETER_NOT_USED (InData_DataTLen); + FSP_PARAMETER_NOT_USED (OutData_DataT); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_Aes192CmacFinal(const uint32_t InData_Cmd[], + const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_DataT[]) +{ + FSP_PARAMETER_NOT_USED (InData_Cmd); + FSP_PARAMETER_NOT_USED (InData_Text); + FSP_PARAMETER_NOT_USED (InData_DataT); + FSP_PARAMETER_NOT_USED (InData_DataTLen); + FSP_PARAMETER_NOT_USED (OutData_DataT); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_Aes256CmacFinal(const uint32_t InData_Cmd[], + const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_DataT[]) +{ + FSP_PARAMETER_NOT_USED (InData_Cmd); + FSP_PARAMETER_NOT_USED (InData_Text); + FSP_PARAMETER_NOT_USED (InData_DataT); + FSP_PARAMETER_NOT_USED (InData_DataTLen); + FSP_PARAMETER_NOT_USED (OutData_DataT); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_Aes128GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + return (HW_SCE_Aes128GcmEncryptInitSub (InData_KeyType, InData_KeyIndex, NULL, InData_IV)); +} + +fsp_err_t HW_SCE_Aes128GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + return (HW_SCE_Aes128GcmDecryptInitSub (InData_KeyType, InData_KeyIndex, NULL, InData_IV)); +} + +fsp_err_t HW_SCE_Aes192GcmEncryptInitSub (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_IV); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_Aes192GcmEncryptFinalSub(const uint32_t *InData_Text, const uint32_t *InData_TextLen, + const uint32_t *InData_DataALen, uint32_t *OutData_Text, uint32_t *OutData_DataT) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(InData_DataALen); + FSP_PARAMETER_NOT_USED(InData_TextLen); + FSP_PARAMETER_NOT_USED(OutData_DataT); + return FSP_ERR_UNSUPPORTED; +} + +void HW_SCE_Aes192GcmEncryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(MAX_CNT); +} + +fsp_err_t HW_SCE_Aes192GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes192GcmEncryptInitSub(InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes192GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes192GcmDecryptInitSub(InData_KeyIndex, InData_IV); +} + +void HW_SCE_Aes192GcmEncryptUpdateAADSub(const uint32_t *InData_DataA, const uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(InData_DataA); + FSP_PARAMETER_NOT_USED(MAX_CNT); +} + +void HW_SCE_Aes192GcmEncryptUpdateTransitionSub(void) +{ + +} + +fsp_err_t HW_SCE_Aes256GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes256GcmEncryptInitSub(InData_KeyType, InData_KeyIndex, NULL, InData_IV); +} + +fsp_err_t HW_SCE_Aes256GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes256GcmDecryptInitSub(InData_KeyType, InData_KeyIndex, NULL, InData_IV); +} + +fsp_err_t HW_SCE_Aes128CcmEncryptInitSubGeneral (uint32_t InData_KeyType[], + uint32_t InData_DataType[], + uint32_t InData_Cmd[], + uint32_t InData_TextLen[], + uint32_t InData_KeyIndex[], + uint32_t InData_IV[], + uint32_t InData_Header[], + uint32_t InData_SeqNum[], + uint32_t Header_Len) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_TextLen); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_IV); + FSP_PARAMETER_NOT_USED(InData_Header); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + FSP_PARAMETER_NOT_USED(Header_Len); + return FSP_ERR_UNSUPPORTED; +} +fsp_err_t HW_SCE_Aes192GcmDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_IV); + return FSP_ERR_UNSUPPORTED; +} + + fsp_err_t HW_SCE_Aes192CcmEncryptInitSubGeneral (uint32_t InData_KeyType[], + uint32_t InData_DataType[], + uint32_t InData_Cmd[], + uint32_t InData_TextLen[], + uint32_t InData_KeyIndex[], + uint32_t InData_IV[], + uint32_t InData_Header[], + uint32_t InData_SeqNum[], + uint32_t Header_Len) + { + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_TextLen); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_IV); + FSP_PARAMETER_NOT_USED(InData_Header); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + FSP_PARAMETER_NOT_USED(Header_Len); + return FSP_ERR_UNSUPPORTED; + } + +fsp_err_t HW_SCE_Aes256CcmEncryptInitSubGeneral (uint32_t InData_KeyType[], + uint32_t InData_DataType[], + uint32_t InData_Cmd[], + uint32_t InData_TextLen[], + uint32_t InData_KeyIndex[], + uint32_t InData_IV[], + uint32_t InData_Header[], + uint32_t InData_SeqNum[], + uint32_t Header_Len) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_TextLen); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_IV); + FSP_PARAMETER_NOT_USED(InData_Header); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + FSP_PARAMETER_NOT_USED(Header_Len); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_Aes128CcmDecryptInitSubGeneral (uint32_t InData_KeyType[], + uint32_t InData_DataType[], + uint32_t InData_Cmd[], + uint32_t InData_TextLen[], + uint32_t InData_MACLength[], + uint32_t InData_KeyIndex[], + uint32_t InData_IV[], + uint32_t InData_Header[], + uint32_t InData_SeqNum[], + uint32_t Header_Len) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_TextLen); + FSP_PARAMETER_NOT_USED(InData_MACLength); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_IV); + FSP_PARAMETER_NOT_USED(InData_Header); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + FSP_PARAMETER_NOT_USED(Header_Len); + return FSP_ERR_UNSUPPORTED; +} + + fsp_err_t HW_SCE_Aes192CcmDecryptInitSubGeneral (uint32_t InData_KeyType[], + uint32_t InData_DataType[], + uint32_t InData_Cmd[], + uint32_t InData_TextLen[], + uint32_t InData_MACLength[], + uint32_t InData_KeyIndex[], + uint32_t InData_IV[], + uint32_t InData_Header[], + uint32_t InData_SeqNum[], + uint32_t Header_Len) + { + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_TextLen); + FSP_PARAMETER_NOT_USED(InData_MACLength); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_IV); + FSP_PARAMETER_NOT_USED(InData_Header); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + FSP_PARAMETER_NOT_USED(Header_Len); + return FSP_ERR_UNSUPPORTED; + } + +fsp_err_t HW_SCE_Aes256CcmDecryptInitSubGeneral (uint32_t InData_KeyType[], + uint32_t InData_DataType[], + uint32_t InData_Cmd[], + uint32_t InData_TextLen[], + uint32_t InData_MACLength[], + uint32_t InData_KeyIndex[], + uint32_t InData_IV[], + uint32_t InData_Header[], + uint32_t InData_SeqNum[], + uint32_t Header_Len) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_TextLen); + FSP_PARAMETER_NOT_USED(InData_MACLength); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_IV); + FSP_PARAMETER_NOT_USED(InData_Header); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + FSP_PARAMETER_NOT_USED(Header_Len); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_Aes128CcmEncryptFinalSubGeneral (const uint32_t *InData_Text, const uint32_t *InData_TextLen, uint32_t *OutData_Text, uint32_t *OutData_MAC) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(InData_TextLen); + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(OutData_MAC); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_Aes128CcmDecryptFinalSubGeneral(const uint32_t *InData_Text, + const uint32_t *InData_TextLen, + const uint32_t *InData_MAC, + const uint32_t *InData_MACLength, + uint32_t *OutData_Text) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(InData_TextLen); + FSP_PARAMETER_NOT_USED(InData_MAC); + FSP_PARAMETER_NOT_USED(InData_MACLength); + FSP_PARAMETER_NOT_USED(OutData_Text); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_Ecc256ScalarMultiplicationSubAdaptor(const uint32_t InData_CurveType[], + const uint32_t InData_KeyMode[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_PubKey[], + const uint32_t InData_DomainParam[], + uint32_t OutData_R[]) +{ + return (HW_SCE_Ecc256ScalarMultiplicationSub(InData_CurveType, InData_KeyMode, InData_KeyIndex, NULL, InData_PubKey, InData_DomainParam, OutData_R)); +} + +fsp_err_t HW_SCE_Ecc384ScalarMultiplicationSubAdaptor(const uint32_t InData_CurveType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_PubKey[], + const uint32_t InData_DomainParam[], + uint32_t OutData_R[]) +{ + FSP_PARAMETER_NOT_USED(InData_CurveType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_PubKey); + FSP_PARAMETER_NOT_USED(InData_DomainParam); + FSP_PARAMETER_NOT_USED(OutData_R); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_Ecc521ScalarMultiplicationSubAdaptor(const uint32_t InData_CurveType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_PubKey[], + const uint32_t InData_DomainParam[], + uint32_t OutData_R[]) +{ + FSP_PARAMETER_NOT_USED(InData_CurveType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_PubKey); + FSP_PARAMETER_NOT_USED(InData_DomainParam); + FSP_PARAMETER_NOT_USED(OutData_R); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_EcdsaSignatureGenerateSubAdaptor(const uint32_t InData_CurveType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_DomainParam[], + uint32_t OutData_Signature[]) +{ + uint32_t indata_key_mode, curvetype = 0; + indata_key_mode = change_endian_long(*InData_Cmd); + curvetype = change_endian_long(*InData_CurveType); + if (SCE_OEM_KEY_TYPE_PLAIN == *InData_Cmd) + { + return (HW_SCE_EcdsaSignatureGenerateSub(&curvetype, &indata_key_mode, NULL, InData_KeyIndex ,InData_MsgDgst, InData_DomainParam, OutData_Signature)); + } + else + { + return (HW_SCE_EcdsaSignatureGenerateSub(&curvetype, &indata_key_mode, InData_KeyIndex, NULL ,InData_MsgDgst, InData_DomainParam, OutData_Signature)); + } +} + +fsp_err_t HW_SCE_EcdsaP384SignatureGenerateSubAdaptor(const uint32_t InData_CurveType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_DomainParam[], + uint32_t OutData_Signature[]) +{ + FSP_PARAMETER_NOT_USED(InData_CurveType); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_MsgDgst); + FSP_PARAMETER_NOT_USED(InData_DomainParam); + FSP_PARAMETER_NOT_USED(OutData_Signature); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_EcdsaP521SignatureGenerateSubAdaptor(const uint32_t InData_CurveType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_DomainParam[], + uint32_t OutData_Signature[]) +{ + FSP_PARAMETER_NOT_USED(InData_CurveType); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_MsgDgst); + FSP_PARAMETER_NOT_USED(InData_DomainParam); + FSP_PARAMETER_NOT_USED(OutData_Signature); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_EcdsaSignatureVerificationSubAdaptor(const uint32_t InData_CurveType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[]) +{ + FSP_PARAMETER_NOT_USED(InData_Cmd); + uint32_t curvetype = change_endian_long(*InData_CurveType); + return (HW_SCE_EcdsaSignatureVerificationSub(&curvetype, InData_KeyIndex, InData_MsgDgst, InData_Signature, InData_DomainParam)); +} + +fsp_err_t HW_SCE_EcdsaP384SignatureVerificationSubAdaptor(const uint32_t InData_CurveType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[]) +{ + FSP_PARAMETER_NOT_USED(InData_CurveType); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_MsgDgst); + FSP_PARAMETER_NOT_USED(InData_Signature); + FSP_PARAMETER_NOT_USED(InData_DomainParam); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_EcdsaP521SignatureVerificationSubAdaptor(const uint32_t InData_CurveType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[]) +{ + FSP_PARAMETER_NOT_USED(InData_CurveType); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_MsgDgst); + FSP_PARAMETER_NOT_USED(InData_Signature); + FSP_PARAMETER_NOT_USED(InData_DomainParam); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_GenerateEccRandomKeyIndexSubAdaptor(const uint32_t *InData_CurveType, + const uint32_t *InData_Cmd, + const uint32_t *InData_KeyType, + const uint32_t InData_DomainParam[], + uint32_t *OutData_PubKeyIndex, + uint32_t *OutData_PubKey, + uint32_t *OutData_PrivKeyIndex, + uint32_t *OutData_PrivKey) +{ + FSP_PARAMETER_NOT_USED (InData_Cmd); + FSP_PARAMETER_NOT_USED(OutData_PubKeyIndex); + return (HW_SCE_GenerateEccRandomKeyIndexSub(InData_KeyType, InData_CurveType, InData_DomainParam, OutData_PubKey, OutData_PrivKeyIndex, OutData_PrivKey)); +} + +fsp_err_t HW_SCE_GenerateEccP384RandomKeyIndexSubAdaptor(const uint32_t *InData_CurveType, + const uint32_t *InData_KeyType, + const uint32_t InData_DomainParam[], + uint32_t *OutData_PubKeyIndex, + uint32_t *OutData_PubKey, + uint32_t *OutData_PrivKeyIndex, + uint32_t *OutData_PrivKey) +{ + FSP_PARAMETER_NOT_USED (InData_CurveType); + FSP_PARAMETER_NOT_USED (InData_KeyType); + FSP_PARAMETER_NOT_USED (InData_DomainParam); + FSP_PARAMETER_NOT_USED (OutData_PubKeyIndex); + FSP_PARAMETER_NOT_USED (OutData_PubKey); + FSP_PARAMETER_NOT_USED (OutData_PrivKeyIndex); + FSP_PARAMETER_NOT_USED (OutData_PrivKey); + + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_Aes192GcmDecryptFinalSub (const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_DataALen[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_Text[]) +{ + FSP_PARAMETER_NOT_USED (InData_Text); + FSP_PARAMETER_NOT_USED (InData_TextLen); + FSP_PARAMETER_NOT_USED (InData_DataALen); + FSP_PARAMETER_NOT_USED (InData_DataT); + FSP_PARAMETER_NOT_USED (InData_DataTLen); + FSP_PARAMETER_NOT_USED (OutData_Text); + + return FSP_ERR_UNSUPPORTED; +} + +void HW_SCE_Aes192GcmDecryptUpdateAADSub (const uint32_t InData_DataA[], const uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(InData_DataA); + FSP_PARAMETER_NOT_USED(MAX_CNT); +} + +void HW_SCE_Aes192GcmDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED (InData_Text); + FSP_PARAMETER_NOT_USED (OutData_Text); + FSP_PARAMETER_NOT_USED (MAX_CNT); +} + +void HW_SCE_Aes192GcmDecryptUpdateTransitionSub (void) +{ +} + +fsp_err_t HW_SCE_Aes128XtsDecryptInitSub (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED (InData_KeyIndex); + FSP_PARAMETER_NOT_USED (InData_IV); + + return FSP_ERR_UNSUPPORTED; +} +fsp_err_t HW_SCE_Aes128XtsDecryptFinalSub (const uint32_t InData_TextBitLen[], + const uint32_t InData_Text[], + uint32_t OutData_Text[]) +{ + FSP_PARAMETER_NOT_USED (InData_TextBitLen); + FSP_PARAMETER_NOT_USED (InData_Text); + FSP_PARAMETER_NOT_USED (OutData_Text); + + return FSP_ERR_UNSUPPORTED; +} + +void HW_SCE_Aes128XtsDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED (InData_Text); + FSP_PARAMETER_NOT_USED (OutData_Text); + FSP_PARAMETER_NOT_USED (MAX_CNT); +} +fsp_err_t HW_SCE_Aes128XtsEncryptFinalSub (const uint32_t InData_TextBitLen[], + const uint32_t InData_Text[], + uint32_t OutData_Text[]) +{ + FSP_PARAMETER_NOT_USED (InData_TextBitLen); + FSP_PARAMETER_NOT_USED (InData_Text); + FSP_PARAMETER_NOT_USED (OutData_Text); + + return FSP_ERR_UNSUPPORTED; +} +fsp_err_t HW_SCE_Aes128XtsEncryptInitSub (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED (InData_KeyIndex); + FSP_PARAMETER_NOT_USED (InData_IV); + + return FSP_ERR_UNSUPPORTED; +} +void HW_SCE_Aes128XtsEncryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED (InData_Text); + FSP_PARAMETER_NOT_USED (OutData_Text); + FSP_PARAMETER_NOT_USED (MAX_CNT); +} + +fsp_err_t HW_SCE_EccEd25519ScalarMultiplicationSubAdaptor(const uint32_t InData_CurveType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_PubKey[], + const uint32_t InData_DomainParam[], + uint32_t OutData_R[]) +{ + FSP_PARAMETER_NOT_USED(InData_CurveType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_PubKey); + FSP_PARAMETER_NOT_USED(InData_DomainParam); + FSP_PARAMETER_NOT_USED(OutData_R); + return FSP_ERR_UNSUPPORTED; +} + + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/DomainParams.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/DomainParams.c new file mode 100644 index 000000000..e0995f0da --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/DomainParams.c @@ -0,0 +1,563 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +uint32_t const DomainParam_NIST_P192[] = +{ +#ifndef __ARMEB__ /* Little endian */ + 0x6b27a0a2, 0x06c30ad0, 0xbc4488f8, 0x85ba9523, + 0xa4bbc7ab, 0x54e55344, 0x046b2e6d, 0x3d0a9d4a, + 0x0f028c91, 0x82829d85, 0xea1bb2b3, 0xd066ab69, + 0x0626118c, 0x2b92d309, 0xf839aba7, 0xf9707a09, + 0xa958657d, 0x8d1c4bd7, 0x161330fb, 0xdae35b80, + 0xb9d1468c, 0xe256973a, 0x81151c52, 0x67ea2f7e, + 0xbe73b2ad, 0x998c32e5, 0x165ed2c3, 0xe2906b51, + 0x22c391c6, 0x6f72b24a, 0x91f2995a, 0x787f505b, + 0x4e60be80, 0x76d83d97, 0xbf096ed7, 0x84b0c455, + 0x2deea5b0, 0x717eccc3, 0x556cdc2e, 0xd16d8d63, + 0xcf37deb5, 0xb27afc09, 0xfdbdd1f3, 0xfc2d5241, + 0x7472f9fb, 0xe02a83b6, 0xae6e1d1b, 0xefb10c9d, + 0xef71e35b, 0x27028987, 0x4faddb26, 0x3dfdc2c9, + 0x844b666a, 0xbbe7e5f9, 0xa4bd432d, 0xcb03c2b7, + 0xea674d4c, 0xce4c1bef, 0xb960a15c, 0x634ac15e, + 0x141d4c99, 0x4a1d2fe8, 0xee41186e, 0xbbfec82c, + 0x268a8c09, 0x8fe242f3, 0x8e69b6bb, 0x59abb962, + 0x9d807b9c, 0x49255edd, 0x07cbf040, 0x897de163 + +#else /* Big endian */ + 0xa2a0276b, 0xd00ac306, 0xf88844bc, 0x2395ba85, + 0xabc7bba4, 0x4453e554, 0x6d2e6b04, 0x4a9d0a3d, + 0x918c020f, 0x859d8282, 0xb3b21bea, 0x69ab66d0, + 0x8c112606, 0x09d3922b, 0xa7ab39f8, 0x097a70f9, + 0x7d6558a9, 0xd74b1c8d, 0xfb301316, 0x805be3da, + 0x8c46d1b9, 0x3a9756e2, 0x521c1581, 0x7e2fea67, + 0xadb273be, 0xe5328c99, 0xc3d25e16, 0x516b90e2, + 0xc691c322, 0x4ab2726f, 0x5a99f291, 0x5b507f78, + 0x80be604e, 0x973dd876, 0xd76e09bf, 0x55c4b084, + 0xb0a5ee2d, 0xc3cc7e71, 0x2edc6c55, 0x638d6dd1, + 0xb5de37cf, 0x09fc7ab2, 0xf3d1bdfd, 0x41522dfc, + 0xfbf97274, 0xb6832ae0, 0x1b1d6eae, 0x9d0cb1ef, + 0x5be371ef, 0x87890227, 0x26dbad4f, 0xc9c2fd3d, + 0x6a664b84, 0xf9e5e7bb, 0x2d43bda4, 0xb7c203cb, + 0x4c4d67ea, 0xef1b4cce, 0x5ca160b9, 0x5ec14a63, + 0x994c1d14, 0xe82f1d4a, 0x6e1841ee, 0x2cc8febb, + 0x098c8a26, 0xf342e28f, 0xbbb6698e, 0x62b9ab59, + 0x9c7b809d, 0xdd5e2549, 0x40f0cb07, 0x63e17d89 +#endif /* defined __ARMEB__ */ +}; + +uint32_t const DomainParam_NIST_P224[] = +{ +#ifndef __ARMEB__ /* Little endian */ + 0xe9be3802, 0x90796634, 0xcffeb5da, 0x0fc3a8ad, + 0x1d343257, 0xc287c137, 0xe454ad5c, 0x22dc184a, + 0x8d004fb8, 0xbf351b1a, 0xe2b495bb, 0x7ad715ec, + 0xbcf2626b, 0x63d000fb, 0x55df8518, 0x5498af42, + 0x9576e995, 0x93dc9c6d, 0x02f0a5fb, 0xd02c362f, + 0x4080199d, 0x6e000422, 0xf6d5cdf8, 0x1823883d, + 0xa5aeb6e8, 0x4aae7d06, 0xac1a7a81, 0x057daf57, + 0x8a59c175, 0x1ec74c3a, 0xdeb98b1e, 0xd0c81758, + 0x6b9f371b, 0x051038ca, 0xdcdf6141, 0x41afd3e5, + 0x4eb7eb28, 0x2e6db21e, 0x84ba2871, 0xf23f18b1, + 0xa61aa210, 0xf5da7d15, 0x74e610fe, 0x62643380, + 0x30337d81, 0x83fa408e, 0x11ba665e, 0x570b5820, + 0x544e3bd9, 0x94c4b5ea, 0x1248124f, 0xffb700b7, + 0xf652b383, 0x94e6752a, 0x34a2b6fe, 0x56d44674, + 0x35f81c5f, 0x4b341590, 0x1e05b531, 0x733dc637, + 0xe94070ab, 0x0711157a, 0x3510f6f5, 0xd278861e, + 0x2dd16729, 0xcb1506e9, 0xf9fc19bd, 0xe254035f, + 0xa331c089, 0xebebe6ba, 0x1ef423f2, 0x84f0d6a5 + +#else /* Big endian */ + 0x0238bee9, 0x34667990, 0xdab5fecf, 0xada8c30f, + 0x5732341d, 0x37c187c2, 0x5cad54e4, 0x4a18dc22, + 0xb84f008d, 0x1a1b35bf, 0xbb95b4e2, 0xec15d77a, + 0x6b62f2bc, 0xfb00d063, 0x1885df55, 0x42af9854, + 0x95e97695, 0x6d9cdc93, 0xfba5f002, 0x2f362cd0, + 0x9d198040, 0x2204006e, 0xf8cdd5f6, 0x3d882318, + 0xe8b6aea5, 0x067dae4a, 0x817a1aac, 0x57af7d05, + 0x75c1598a, 0x3a4cc71e, 0x1e8bb9de, 0x5817c8d0, + 0x1b379f6b, 0xca381005, 0x4161dfdc, 0xe5d3af41, + 0x28ebb74e, 0x1eb26d2e, 0x7128ba84, 0xb1183ff2, + 0x10a21aa6, 0x157ddaf5, 0xfe10e674, 0x80336462, + 0x817d3330, 0x8e40fa83, 0x5e66ba11, 0x20580b57, + 0xd93b4e54, 0xeab5c494, 0x4f124812, 0xb700b7ff, + 0x83b352f6, 0x2a75e694, 0xfeb6a234, 0x7446d456, + 0x5f1cf835, 0x9015344b, 0x31b5051e, 0x37c63d73, + 0xab7040e9, 0x7a151107, 0xf5f61035, 0x1e8678d2, + 0x2967d12d, 0xe90615cb, 0xbd19fcf9, 0x5f0354e2, + 0x89c031a3, 0xbae6ebeb, 0xf223f41e, 0xa5d6f084 +#endif /* defined __ARMEB__ */ +}; + +uint32_t const DomainParam_NIST_P256[] = +{ +#ifndef __ARMEB__ /* Little endian */ + 0xbe0c4d57, 0xdf19f281, 0x218ef1f1, 0xff3a8043, + 0xea7f9603, 0x3570852d, 0xaedb42ee, 0xd74bdb28, + 0xc7b90cba, 0x4ab0d310, 0x623fd564, 0xc2c8dcf8, + 0xf22a8af7, 0x7df9a188, 0x8c9dd15e, 0xcf345fe3, + 0x85ae4e60, 0x77cbf7d5, 0x457b8ca5, 0xb5783c89, + 0xef9a1a43, 0xbafbc7e6, 0x5bdd65a2, 0xbca719f0, + 0x911f6703, 0x69c22c4b, 0x270d7fba, 0x38e2165a, + 0x363275e7, 0x8c4b8bb3, 0xf0dbcf65, 0x2b43abe6, + 0x22948c0c, 0xbda37784, 0x00a66615, 0xa9b35723, + 0x6aaa9634, 0x0bf3f7bd, 0xe2feaa5b, 0x6373fa44, + 0x133ed01a, 0x777de410, 0xcd588d01, 0x0b80d16a, + 0xf31f5c20, 0x67b31a35, 0x2c65b0cf, 0xc35b3765, + 0x39c3286d, 0xea128cf5, 0xba9abaaa, 0x63d54b95, + 0x3c74c427, 0x85820288, 0xf80689dc, 0x291a698a, + 0x1c2d7144, 0x01c2842c, 0x282b4b75, 0x216967b3, + 0x2a772863, 0x6a17943d, 0x417d294b, 0xafbd05dd, + 0x647bd78c, 0x684c3088, 0x23f61c88, 0xd9847f56, + 0x8d7d4763, 0xcd8acb65, 0x7fc20ad6, 0xbfa8897c + +#else /* Big endian */ + 0x574d0cbe, 0x81f219df, 0xf1f18e21, 0x43803aff, + 0x03967fea, 0x2d857035, 0xee42dbae, 0x28db4bd7, + 0xba0cb9c7, 0x10d3b04a, 0x64d53f62, 0xf8dcc8c2, + 0xf78a2af2, 0x88a1f97d, 0x5ed19d8c, 0xe35f34cf, + 0x604eae85, 0xd5f7cb77, 0xa58c7b45, 0x893c78b5, + 0x431a9aef, 0xe6c7fbba, 0xa265dd5b, 0xf019a7bc, + 0x03671f91, 0x4b2cc269, 0xba7f0d27, 0x5a16e238, + 0xe7753236, 0xb38b4b8c, 0x65cfdbf0, 0xe6ab432b, + 0x0c8c9422, 0x8477a3bd, 0x1566a600, 0x2357b3a9, + 0x3496aa6a, 0xbdf7f30b, 0x5baafee2, 0x44fa7363, + 0x1ad03e13, 0x10e47d77, 0x018d58cd, 0x6ad1800b, + 0x205c1ff3, 0x351ab367, 0xcfb0652c, 0x65375bc3, + 0x6d28c339, 0xf58c12ea, 0xaaba9aba, 0x954bd563, + 0x27c4743c, 0x88028285, 0xdc8906f8, 0x8a691a29, + 0x44712d1c, 0x2c84c201, 0x754b2b28, 0xb3676921, + 0x6328772a, 0x3d94176a, 0x4b297d41, 0xdd05bdaf, + 0x8cd77b64, 0x88304c68, 0x881cf623, 0x567f84d9, + 0x63477d8d, 0x65cb8acd, 0xd60ac27f, 0x7c89a8bf +#endif /* defined __ARMEB__ */ +}; + +uint32_t const DomainParam_NIST_P384[] = +{ +#ifndef __ARMEB__ /* Little endian */ + 0x11296620, 0x37d2d827, 0x832f6bb8, 0x851b9fda, + 0xac78c049, 0x4741660c, 0x2562c4c7, 0x8d6084fd, + 0x49cd08e4, 0x5216df79, 0x90ab8ac8, 0x75f11260, + 0xa4479a71, 0x30f1c0dd, 0xd4fd02ef, 0x7c6261f4, + 0x481f0394, 0x1dd3e399, 0x8d186637, 0xb80b74b5, + 0x7779c554, 0x3e528b01, 0x6833a961, 0x8a606c5f, + 0x4c69b595, 0xa4460ee7, 0xf9b90146, 0xe39f674e, + 0x33eb34fa, 0xc9671029, 0xa1cbd84b, 0x13414da3, + 0xb737ca61, 0xd6b9350a, 0xe7304d09, 0xe3e8fbae, + 0x63dc5e6d, 0x76257731, 0x5e80208f, 0x476b22e5, + 0xf8ac2367, 0xeadd85f3, 0x5d571889, 0x982f7132, + 0xebfc9ac8, 0xf214633a, 0xb023efb7, 0x952b4086, + 0xb886c81c, 0xd255f5d0, 0x41f08f64, 0x5e218efd, + 0x3116a9f2, 0x9dea7e8b, 0x26f6b324, 0x5b497baa, + 0x6370fd01, 0xe490f76d, 0x78481f39, 0xf5da7981, + 0x37268740, 0xb4403434, 0x044a6553, 0x5fdafee8, + 0xd9410ec2, 0xf719a281, 0x0ea4a312, 0x99686113, + 0xd3ec543c, 0x50ec7001, 0x10157efd, 0xee2f670a, + 0xbafc17e1, 0x3d18ddcb, 0xe245b888, 0x14e97e11, + 0xd62931eb, 0x95bc0362, 0x84c8c67b, 0xfec11642, + 0x76ba2423, 0xc6b26d69, 0xd8d5f21f, 0xe8d5c5d4, + 0x32e59438, 0xd53cd657, 0xaac468e3, 0x195cedd2, + 0xb6308766, 0xb248621e, 0x58ceb77f, 0x95091c29, + 0x783a0d93, 0xd1b7bf05, 0xfad79ca2, 0xb345de4f, + 0xccb9b316, 0x29100335, 0x579e38c3, 0x8d8d9792, + 0x49885605, 0xa925977c, 0x9233ce16, 0x8e216279 + +#else /* Big endian */ + 0x20662911, 0x27d8d237, 0xb86b2f83, 0xda9f1b85, + 0x49c078ac, 0x0c664147, 0xc7c46225, 0xfd84608d, + 0xe408cd49, 0x79df1652, 0xc88aab90, 0x6012f175, + 0x719a47a4, 0xddc0f130, 0xef02fdd4, 0xf461627c, + 0x94031f48, 0x99e3d31d, 0x3766188d, 0xb5740bb8, + 0x54c57977, 0x018b523e, 0x61a93368, 0x5f6c608a, + 0x95b5694c, 0xe70e46a4, 0x4601b9f9, 0x4e679fe3, + 0xfa34eb33, 0x291067c9, 0x4bd8cba1, 0xa34d4113, + 0x61ca37b7, 0x0a35b9d6, 0x094d30e7, 0xaefbe8e3, + 0x6d5edc63, 0x31772576, 0x8f20805e, 0xe5226b47, + 0x6723acf8, 0xf385ddea, 0x8918575d, 0x32712f98, + 0xc89afceb, 0x3a6314f2, 0xb7ef23b0, 0x86402b95, + 0x1cc886b8, 0xd0f555d2, 0x648ff041, 0xfd8e215e, + 0xf2a91631, 0x8b7eea9d, 0x24b3f626, 0xaa7b495b, + 0x01fd7063, 0x6df790e4, 0x391f4878, 0x8179daf5, + 0x40872637, 0x343440b4, 0x53654a04, 0xe8feda5f, + 0xc20e41d9, 0x81a219f7, 0x12a3a40e, 0x13616899, + 0x3c54ecd3, 0x0170ec50, 0xfd7e1510, 0x0a672fee, + 0xe117fcba, 0xcbdd183d, 0x88b845e2, 0x117ee914, + 0xeb3129d6, 0x6203bc95, 0x7bc6c884, 0x4216c1fe, + 0x2324ba76, 0x696db2c6, 0x1ff2d5d8, 0xd4c5d5e8, + 0x3894e532, 0x57d63cd5, 0xe368c4aa, 0xd2ed5c19, + 0x668730b6, 0x1e6248b2, 0x7fb7ce58, 0x291c0995, + 0x930d3a78, 0x05bfb7d1, 0xa29cd7fa, 0x4fde45b3, + 0x16b3b9cc, 0x35031029, 0xc3389e57, 0x92978d8d, + 0x05568849, 0x7c9725a9, 0x16ce3392, 0x7962218e +#endif /* defined __ARMEB__ */ +}; + +uint32_t const DomainParam_NIST_P521[] = +{ +#ifndef __ARMEB__ /* Little endian */ + 0xbb2dacbf, 0x5bebd870, 0x7cb24760, 0x549d633a, + 0x0f4c3073, 0x5b291739, 0x2898f98e, 0x9da196d6, + 0x99e2ceed, 0xe73d2862, 0xc1b888b7, 0xcc7a4be7, + 0x9533d4b0, 0x743c4b0e, 0xbd956640, 0x5f4bee9c, + 0x52c7e7f6, 0xe7939211, 0x02adf5bd, 0xeb7474cc, + 0x2595d910, 0xe5bb3450, 0xe9ef73e4, 0xfdee31f9, + 0xc9fc4af9, 0x73c6146e, 0x114a1886, 0x951ffda8, + 0x47527801, 0x4c6d7318, 0x04084f88, 0x9cd54119, + 0xe338b72c, 0xeecbef0a, 0x3b239d1d, 0x90fb59fc, + 0x3a34983c, 0x0399530f, 0x8082622e, 0x3f88b59c, + 0x7d42358c, 0xd49a0b4e, 0xbd6448c6, 0x12790e7a, + 0x14a1289f, 0x4a9254e0, 0x8dce08db, 0xe028f15c, + 0x92bfc22d, 0x7126b931, 0xa20e4b32, 0x3d4490a1, + 0xd2782790, 0x9ba62cd5, 0x412c5365, 0xd4da688b, + 0xebe54bbe, 0x2072bbfb, 0xe3b9f9aa, 0xc74eaa7e, + 0x11686f30, 0xd16b5eea, 0x101e34a9, 0xad67eaeb, + 0xf4270864, 0xec48dbd5, 0xd721d62f, 0x825dac1d, + 0x1d47483e, 0x1b77d264, 0xe8a377e7, 0xf87f5507, + 0x1f86b80e, 0x5e7a72aa, 0x0590c0cc, 0x880671ca, + 0x74cbe820, 0x515a490f, 0xe84f0908, 0x680c4d66, + 0x48ab1a6d, 0xee76c420, 0x5167b090, 0x22edd2a2, + 0xe7cbd936, 0x067475a0, 0xed376b1d, 0xa27789ef, + 0x6d0e3287, 0x3378e79f, 0x75eec67c, 0xd8763174, + 0x457722c3, 0x0c24138c, 0xaf6a5b6a, 0x18de8027, + 0x8b4aab64, 0x8f941c60, 0x86e1139c, 0xbf933f85, + 0x320f7acb, 0xa2f15469, 0x920bac0b, 0x767525e4, + 0x442c7330, 0x019b4724, 0x021fdb7e, 0x4dd8eb46, + 0x6cfbfcb7, 0x6ccc49eb, 0x62fa83a4, 0xce0001ac, + 0x25e8d0d2, 0x3f13db90, 0x436d0158, 0x28af7681, + 0xe823940b, 0xb0ab1540, 0x4cf64341, 0x632e81aa, + 0x1e0fa8f4, 0xfbfe12c3, 0x19ff0563, 0xb8a8da95, + 0xc72db188, 0x97cdc50e, 0x0b4fa832, 0x4e701009, + 0x13b707a0, 0x14b608b4, 0x33304e41, 0xc935ae8b, + 0x57f495f1, 0x850b3117, 0x25d217b6, 0x38b9f25e, + 0x87c6abad, 0x3c5d1438, 0x24fe34a6, 0xc3a9edae, + 0xa3274c62, 0x7ac0fdd2, 0xc17a551d, 0x75cc9499, + 0x34b9fac9, 0x344835af, 0x098d8328, 0x1ea621cc, + 0xc23e2822, 0xc227d7ca, 0x9220c07c, 0xa6f83db4, + 0x95c0f54d, 0x4ec39d38, 0x2796dbc1, 0x8ee3a2bb, + 0xe9be030b, 0x664319d0, 0x46fa2f02, 0x2c777f4a, + 0x17d50776, 0xf24d9bd5, 0xc8ef9a1b, 0x5a7a4209, + 0xbf6a8d1a, 0xe662c92c, 0x0f9a0d4e, 0xcd550b8a + +#else /* Big endian */ + 0xbfac2dbb, 0x70d8eb5b, 0x6047b27c, 0x3a639d54, + 0x73304c0f, 0x3917295b, 0x8ef99828, 0xd696a19d, + 0xedcee299, 0x62283de7, 0xb788b8c1, 0xe74b7acc, + 0xb0d43395, 0x0e4b3c74, 0x406695bd, 0x9cee4b5f, + 0xf6e7c752, 0x119293e7, 0xbdf5ad02, 0xcc7474eb, + 0x10d99525, 0x5034bbe5, 0xe473efe9, 0xf931eefd, + 0xf94afcc9, 0x6e14c673, 0x86184a11, 0xa8fd1f95, + 0x01785247, 0x18736d4c, 0x884f0804, 0x1941d59c, + 0x2cb738e3, 0x0aefcbee, 0x1d9d233b, 0xfc59fb90, + 0x3c98343a, 0x0f539903, 0x2e628280, 0x9cb5883f, + 0x8c35427d, 0x4e0b9ad4, 0xc64864bd, 0x7a0e7912, + 0x9f28a114, 0xe054924a, 0xdb08ce8d, 0x5cf128e0, + 0x2dc2bf92, 0x31b92671, 0x324b0ea2, 0xa190443d, + 0x902778d2, 0xd52ca69b, 0x65532c41, 0x8b68dad4, + 0xbe4be5eb, 0xfbbb7220, 0xaaf9b9e3, 0x7eaa4ec7, + 0x306f6811, 0xea5e6bd1, 0xa9341e10, 0xebea67ad, + 0x640827f4, 0xd5db48ec, 0x2fd621d7, 0x1dac5d82, + 0x3e48471d, 0x64d2771b, 0xe777a3e8, 0x07557ff8, + 0x0eb8861f, 0xaa727a5e, 0xccc09005, 0xca710688, + 0x20e8cb74, 0x0f495a51, 0x08094fe8, 0x664d0c68, + 0x6d1aab48, 0x20c476ee, 0x90b06751, 0xa2d2ed22, + 0x36d9cbe7, 0xa0757406, 0x1d6b37ed, 0xef8977a2, + 0x87320e6d, 0x9fe77833, 0x7cc6ee75, 0x743176d8, + 0xc3227745, 0x8c13240c, 0x6a5b6aaf, 0x2780de18, + 0x64ab4a8b, 0x601c948f, 0x9c13e186, 0x853f93bf, + 0xcb7a0f32, 0x6954f1a2, 0x0bac0b92, 0xe4257576, + 0x30732c44, 0x24479b01, 0x7edb1f02, 0x46ebd84d, + 0xb7fcfb6c, 0xeb49cc6c, 0xa483fa62, 0xac0100ce, + 0xd2d0e825, 0x90db133f, 0x58016d43, 0x8176af28, + 0x0b9423e8, 0x4015abb0, 0x4143f64c, 0xaa812e63, + 0xf4a80f1e, 0xc312fefb, 0x6305ff19, 0x95daa8b8, + 0x88b12dc7, 0x0ec5cd97, 0x32a84f0b, 0x0910704e, + 0xa007b713, 0xb408b614, 0x414e3033, 0x8bae35c9, + 0xf195f457, 0x17310b85, 0xb617d225, 0x5ef2b938, + 0xadabc687, 0x38145d3c, 0xa634fe24, 0xaeeda9c3, + 0x624c27a3, 0xd2fdc07a, 0x1d557ac1, 0x9994cc75, + 0xc9fab934, 0xaf354834, 0x28838d09, 0xcc21a61e, + 0x22283ec2, 0xcad727c2, 0x7cc02092, 0xb43df8a6, + 0x4df5c095, 0x389dc34e, 0xc1db9627, 0xbba2e38e, + 0x0b03bee9, 0xd0194366, 0x022ffa46, 0x4a7f772c, + 0x7607d517, 0xd59b4df2, 0x1b9aefc8, 0x09427a5a, + 0x1a8d6abf, 0x2cc962e6, 0x4e0d9a0f, 0x8a0b55cd +#endif /* defined __ARMEB__ */ +}; + +uint32_t const DomainParam_NIST_Ed25519[] = +{ +#ifndef __ARMEB__ /* Little endian */ + 0x8a5168e3, 0x1f15bfb2, 0xc6058792, 0xa566131b, + 0xb1227aec, 0x7369ceb9, 0xa4507daa, 0x5906f0b2, + 0x4e5bfa64, 0x3f0bf39d, 0x957795e6, 0xa92f7fba, + 0x64f39eeb, 0x56ffee6c, 0x59c6c52c, 0x06b8166f, + 0x9a5f30a0, 0xfbcc7f32, 0x6d6e5e18, 0xb2395952, + 0xfc250f89, 0x8841a96e, 0x269f5e10, 0xa8fa36fc, + 0xcec9308d, 0x8f39d79f, 0x00067775, 0x11807349, + 0xb2c2c1f8, 0xd2466dbf, 0x3edacc6b, 0x40357b3f, + 0xcfff52e2, 0x7b54ec71, 0x4c117868, 0xe647bdf1, + 0x75fb886a, 0x4099ef27, 0x02bce13e, 0x35c81aa2, + 0x6c693185, 0xb21794b7, 0x499d36b9, 0x584bd342, + 0x25e09886, 0x22e9d319, 0xd792573f, 0xfdae3a22, + 0xa73e3a7d, 0x840f34fe, 0x2ed895bf, 0x7d3eaf97, + 0x86c47e32, 0x51f5a045, 0x61c7ffab, 0x8562cd9f, + 0xe5209ccf, 0x631029fe, 0xa1617eae, 0x43b0c7b3, + 0xe2a1f52a, 0x6148da3d, 0xae933aa4, 0x4dc39302, + 0x1db2274a, 0xdf7d09ac, 0x164fc2f4, 0x41ee7a2e, + 0x1fbcce15, 0x102e106a, 0x133ceec2, 0xf6cc8102, + 0x65084667, 0x3c5e690e, 0x8a8f587b, 0x9811f94b + +#else /* Big endian */ + 0xe368518a, 0xb2bf151f, 0x928705c6, 0x1b1366a5, + 0xec7a22b1, 0xb9ce6973, 0xaa7d50a4, 0xb2f00659, + 0x64fa5b4e, 0x9df30b3f, 0xe6957795, 0xba7f2fa9, + 0xeb9ef364, 0x6ceeff56, 0x2cc5c659, 0x6f16b806, + 0xa0305f9a, 0x327fccfb, 0x185e6e6d, 0x525939b2, + 0x890f25fc, 0x6ea94188, 0x105e9f26, 0xfc36faa8, + 0x8d30c9ce, 0x9fd7398f, 0x75770600, 0x49738011, + 0xf8c1c2b2, 0xbf6d46d2, 0x6bccda3e, 0x3f7b3540, + 0xe252ffcf, 0x71ec547b, 0x6878114c, 0xf1bd47e6, + 0x6a88fb75, 0x27ef9940, 0x3ee1bc02, 0xa21ac835, + 0x8531696c, 0xb79417b2, 0xb9369d49, 0x42d34b58, + 0x8698e025, 0x19d3e922, 0x3f5792d7, 0x223aaefd, + 0x7d3a3ea7, 0xfe340f84, 0xbf95d82e, 0x97af3e7d, + 0x327ec486, 0x45a0f551, 0xabffc761, 0x9fcd6285, + 0xcf9c20e5, 0xfe291063, 0xae7e61a1, 0xb3c7b043, + 0x2af5a1e2, 0x3dda4861, 0xa43a93ae, 0x0293c34d, + 0x4a27b21d, 0xac097ddf, 0xf4c24f16, 0x2e7aee41, + 0x15cebc1f, 0x6a102e10, 0xc2ee3c13, 0x0281ccf6, + 0x67460865, 0x0e695e3c, 0x7b588f8a, 0x4bf91198 +#endif /* defined __ARMEB__ */ +}; + +uint32_t const DomainParam_Brainpool_256r1[] = +{ +#ifndef __ARMEB__ /* Little endian */ + 0xd43432bd, 0x5fb5391b, 0x77b3ee64, 0x993475b2, + 0xacd60cfe, 0x5d29b7a4, 0xfcd90541, 0x1bd605cc, + 0x644818e9, 0x3c70f039, 0x95b6c48f, 0xbc996b75, + 0xe0d26366, 0xbf745df8, 0x5b25ac82, 0x97fb1f3c, + 0x12278a9a, 0xf6468512, 0x19302bac, 0xe40dbc1d, + 0x3000f8af, 0x29e72ce0, 0x94473f6c, 0xfc953c2b, + 0x2e510d85, 0x854ee094, 0x1ff29d32, 0x273ee4a2, + 0x6a8a3111, 0x90081e2d, 0xba4cf2fb, 0x09787a35, + 0x0eac960c, 0x26c72a4d, 0x215fc5f4, 0xeb7cdaa6, + 0xf9f12153, 0xe2612ad4, 0x87d59c40, 0xbe547721, + 0xb97a79af, 0x84275cb2, 0x90a8043e, 0xf399eeb0, + 0xed4f0140, 0xabf06984, 0xb1c986bc, 0xc52a097c, + 0x6ab39eb2, 0x10b839d3, 0x1d4f8421, 0xe0acc983, + 0x642a48d3, 0x55477c83, 0xdb6a434a, 0xe16a144b, + 0x54f798a2, 0x5c4bb893, 0x7430ff0d, 0x0c148990, + 0x1dcf7a77, 0xe5eccdc8, 0x6b89978d, 0x59611b9d, + 0x7f152a6c, 0xceaf0993, 0x603f3294, 0x490493f6, + 0xfa21b3b4, 0x6eac05dc, 0xf445927a, 0x27d27aad + +#else /* Big endian */ + 0xbd3234d4, 0x1b39b55f, 0x64eeb377, 0xb2753499, + 0xfe0cd6ac, 0xa4b7295d, 0x4105d9fc, 0xcc05d61b, + 0xe9184864, 0x39f0703c, 0x8fc4b695, 0x756b99bc, + 0x6663d2e0, 0xf85d74bf, 0x82ac255b, 0x3c1ffb97, + 0x9a8a2712, 0x128546f6, 0xac2b3019, 0x1dbc0de4, + 0xaff80030, 0xe02ce729, 0x6c3f4794, 0x2b3c95fc, + 0x850d512e, 0x94e04e85, 0x329df21f, 0xa2e43e27, + 0x11318a6a, 0x2d1e0890, 0xfbf24cba, 0x357a7809, + 0x0c96ac0e, 0x4d2ac726, 0xf4c55f21, 0xa6da7ceb, + 0x5321f1f9, 0xd42a61e2, 0x409cd587, 0x217754be, + 0xaf797ab9, 0xb25c2784, 0x3e04a890, 0xb0ee99f3, + 0x40014fed, 0x8469f0ab, 0xbc86c9b1, 0x7c092ac5, + 0xb29eb36a, 0xd339b810, 0x21844f1d, 0x83c9ace0, + 0xd3482a64, 0x837c4755, 0x4a436adb, 0x4b146ae1, + 0xa298f754, 0x93b84b5c, 0x0dff3074, 0x9089140c, + 0x777acf1d, 0xc8cdece5, 0x8d97896b, 0x9d1b6159, + 0x6c2a157f, 0x9309afce, 0x94323f60, 0xf6930449, + 0xb4b321fa, 0xdc05ac6e, 0x7a9245f4, 0xad7ad227 +#endif /* defined __ARMEB__ */ +}; + +uint32_t const DomainParam_Brainpool_384r1[] = +{ +#ifndef __ARMEB__ /* Little endian */ + 0x3c6ecb49, 0xfed8c21f, 0x03abb3fb, 0x36053db2, + 0x0b56acc2, 0xe42c3a13, 0x8e3eda55, 0x3c0303b8, + 0x6d10a1ea, 0x056c5fb0, 0xeae73bd4, 0x1b210654, + 0x6b4158d3, 0x2f5cbcd3, 0x10a2526a, 0x2192b8f4, + 0x3fe8a26e, 0xe1633585, 0xc999beaf, 0xa47fbde8, + 0x86749a43, 0x3d589a94, 0x24b48495, 0xc300cd16, + 0x67e0d514, 0xc32f2e04, 0x5251537d, 0xf97ad3de, + 0x526db56d, 0xecb36dbc, 0xdaf8cfdc, 0x8fc8023a, + 0xd9761a13, 0xc328a3fa, 0xcb40468e, 0x1c034b70, + 0x4fed5260, 0x37f3949b, 0xebbd66bf, 0x3e098c74, + 0x9b46d2d3, 0x7f50df4e, 0x09e1d50c, 0x3e9e7fe9, + 0x3a6d8044, 0x5ffc8eca, 0x0a379483, 0xa631f53b, + 0xb31c40ec, 0x68f6049a, 0xa2874420, 0x675b6dfc, + 0x0f678b6e, 0x1713ae7b, 0x983740f7, 0x8517a68a, + 0x634368b8, 0x456f0ef4, 0x8825dc99, 0x43228040, + 0x057ad0e3, 0x9a3fcf9b, 0xf5edf5ec, 0x6907b863, + 0x4bbbdb88, 0x8285df62, 0x92a72a6f, 0xbae4db92, + 0x03c8140c, 0x190ca181, 0x498626d7, 0x341735de, + 0xda7a1c38, 0x2cde8027, 0x3ee499d8, 0xbac79e65, + 0xed6327ed, 0x02b0fae6, 0x9b7e7d27, 0xe20cd851, + 0x8d3c6cbe, 0xf73efa7c, 0x0ae22cad, 0x02655922, + 0xbb39e248, 0x12c5ad75, 0xc9bf9fd2, 0x7aab9ede, + 0x9d4ad3b9, 0xbd86bed0, 0xd195dd59, 0x3f40c949, + 0x170fc4ed, 0x67e8b251, 0x27cfb5bb, 0x878e086e, + 0x26978ef1, 0x5641ce60, 0x35ed9ee2, 0xf1573d78, + 0xb38c597c, 0x26eaca4a, 0x7cbb1ffc, 0x97ab5665 + +#else /* Big endian */ + 0x49cb6e3c, 0x1fc2d8fe, 0xfbb3ab03, 0xb23d0536, + 0xc2ac560b, 0x133a2ce4, 0x55da3e8e, 0xb803033c, + 0xeaa1106d, 0xb05f6c05, 0xd43be7ea, 0x5406211b, + 0xd358416b, 0xd3bc5c2f, 0x6a52a210, 0xf4b89221, + 0x6ea2e83f, 0x853563e1, 0xafbe99c9, 0xe8bd7fa4, + 0x439a7486, 0x949a583d, 0x9584b424, 0x16cd00c3, + 0x14d5e067, 0x042e2fc3, 0x7d535152, 0xded37af9, + 0x6db56d52, 0xbc6db3ec, 0xdccff8da, 0x3a02c88f, + 0x131a76d9, 0xfaa328c3, 0x8e4640cb, 0x704b031c, + 0x6052ed4f, 0x9b94f337, 0xbf66bdeb, 0x748c093e, + 0xd3d2469b, 0x4edf507f, 0x0cd5e109, 0xe97f9e3e, + 0x44806d3a, 0xca8efc5f, 0x8394370a, 0x3bf531a6, + 0xec401cb3, 0x9a04f668, 0x204487a2, 0xfc6d5b67, + 0x6e8b670f, 0x7bae1317, 0xf7403798, 0x8aa61785, + 0xb8684363, 0xf40e6f45, 0x99dc2588, 0x40802243, + 0xe3d07a05, 0x9bcf3f9a, 0xecf5edf5, 0x63b80769, + 0x88dbbb4b, 0x62df8582, 0x6f2aa792, 0x92dbe4ba, + 0x0c14c803, 0x81a10c19, 0xd7268649, 0xde351734, + 0x381c7ada, 0x2780de2c, 0xd899e43e, 0x659ec7ba, + 0xed2763ed, 0xe6fab002, 0x277d7e9b, 0x51d80ce2, + 0xbe6c3c8d, 0x7cfa3ef7, 0xad2ce20a, 0x22596502, + 0x48e239bb, 0x75adc512, 0xd29fbfc9, 0xde9eab7a, + 0xb9d34a9d, 0xd0be86bd, 0x59dd95d1, 0x49c9403f, + 0xedc40f17, 0x51b2e867, 0xbbb5cf27, 0x6e088e87, + 0xf18e9726, 0x60ce4156, 0xe29eed35, 0x783d57f1, + 0x7c598cb3, 0x4acaea26, 0xfc1fbb7c, 0x6556ab97 +#endif /* defined __ARMEB__ */ +}; + + +uint32_t const DomainParam_Brainpool_512r1[] = +{ +#ifndef __ARMEB__ /* Little endian */ + 0xf77f3895, 0xe75e3cd1, 0xa1539199, 0x2f95841b, + 0xc1c9f557, 0x0cc092d7, 0x0198ab46, 0xc715c99c, + 0xf32ea94a, 0xd238ab3c, 0xbbc72b3e, 0xd5f0c114, + 0x245069f6, 0x5b038f4e, 0xa02cefaf, 0x0d6d00ef, + 0xec0997a0, 0xebd8154a, 0xe61c2dbc, 0x03df4ad7, + 0x7691e287, 0x587c8e64, 0x26a9357b, 0xf749f82b, + 0xfd616b96, 0xee2052ba, 0xc40641cb, 0x97349e2b, + 0xbbf18705, 0xcd3b419d, 0x590d24aa, 0x20c062cb, + 0xbba6b8ad, 0x447d93ee, 0x027d5cde, 0x0b9c23e2, + 0xe3900004, 0xedaaab8b, 0xd7b38db6, 0xba844d4d, + 0x92558f8a, 0xfe621e13, 0x213cb29c, 0x29993007, + 0xb438d781, 0x0fc20d8c, 0xa09f0015, 0x3c07197c, + 0x0cefeaac, 0xd4de71e7, 0xdb26ec49, 0xc2df8c07, + 0x028fae43, 0x209ccc99, 0xa2da8940, 0xf877bfed, + 0x63a09535, 0xe1644b8f, 0x073af648, 0xf6514463, + 0x57435bcd, 0x9751d9d2, 0xd689317c, 0xf48f7e2b, + 0xa76a5318, 0x3e0af0a2, 0x61cdae90, 0x2627309c, + 0x29803090, 0xca240a7e, 0x8727b59f, 0x84a937ef, + 0x4c328f24, 0xaf8745fa, 0x3f0d11e8, 0xc5cf0654, + 0x60ff52f6, 0xfd2acc06, 0xbde069f3, 0x057ab2a2, + 0xab858324, 0x165f0e76, 0xe5cbb35c, 0xfbee56df, + 0xc38ecdbf, 0x199d6427, 0xdc225664, 0x529f5559, + 0x18a3ad06, 0x76c3beb0, 0x26f5977a, 0x9d4cda55, + 0x9b56d5fd, 0x6523056b, 0x7efd4a07, 0x76a20158, + 0xa442251f, 0x45bcf18c, 0xcf7775bc, 0x243b9895, + 0xb6a684f9, 0x9affd53c, 0x72dee665, 0xa1d56f3f, + 0x81999ff3, 0x0f24f2f2, 0x1dbc12ca, 0x3b3200c5, + 0x299738a1, 0x8b666079, 0xfa30a81a, 0x187d74b3, + 0x2b6df7c9, 0xeea35aa4, 0x2fc5e5e1, 0xb8012839, + 0x5af6c5f6, 0xf799bbe4, 0xce094606, 0x30b33ffc, + 0xb44886b1, 0xdbf56004, 0x0c40a419, 0xa0ab4bfd, + 0x124c455d, 0x61ec6909, 0x018870b3, 0xc39f9766, + 0x963872f8, 0xd42bc6d0, 0xf67f9879, 0x02cd871d, + 0xc1d5637a, 0xd6c96978, 0x529741ed, 0x44be5dd0 + +#else /* Big endian */ + 0x95387ff7, 0xd13c5ee7, 0x999153a1, 0x1b84952f, + 0x57f5c9c1, 0xd792c00c, 0x46ab9801, 0x9cc915c7, + 0x4aa92ef3, 0x3cab38d2, 0x3e2bc7bb, 0x14c1f0d5, + 0xf6695024, 0x4e8f035b, 0xafef2ca0, 0xef006d0d, + 0xa09709ec, 0x4a15d8eb, 0xbc2d1ce6, 0xd74adf03, + 0x87e29176, 0x648e7c58, 0x7b35a926, 0x2bf849f7, + 0x966b61fd, 0xba5220ee, 0xcb4106c4, 0x2b9e3497, + 0x0587f1bb, 0x9d413bcd, 0xaa240d59, 0xcb62c020, + 0xadb8a6bb, 0xee937d44, 0xde5c7d02, 0xe2239c0b, + 0x040090e3, 0x8babaaed, 0xb68db3d7, 0x4d4d84ba, + 0x8a8f5592, 0x131e62fe, 0x9cb23c21, 0x07309929, + 0x81d738b4, 0x8c0dc20f, 0x15009fa0, 0x7c19073c, + 0xaceaef0c, 0xe771ded4, 0x49ec26db, 0x078cdfc2, + 0x43ae8f02, 0x99cc9c20, 0x4089daa2, 0xedbf77f8, + 0x3595a063, 0x8f4b64e1, 0x48f63a07, 0x634451f6, + 0xcd5b4357, 0xd2d95197, 0x7c3189d6, 0x2b7e8ff4, + 0x18536aa7, 0xa2f00a3e, 0x90aecd61, 0x9c302726, + 0x90308029, 0x7e0a24ca, 0x9fb52787, 0xef37a984, + 0x248f324c, 0xfa4587af, 0xe8110d3f, 0x5406cfc5, + 0xf652ff60, 0x06cc2afd, 0xf369e0bd, 0xa2b27a05, + 0x248385ab, 0x760e5f16, 0x5cb3cbe5, 0xdf56eefb, + 0xbfcd8ec3, 0x27649d19, 0x645622dc, 0x59559f52, + 0x06ada318, 0xb0bec376, 0x7a97f526, 0x55da4c9d, + 0xfdd5569b, 0x6b052365, 0x074afd7e, 0x5801a276, + 0x1f2542a4, 0x8cf1bc45, 0xbc7577cf, 0x95983b24, + 0xf984a6b6, 0x3cd5ff9a, 0x65e6de72, 0x3f6fd5a1, + 0xf39f9981, 0xf2f2240f, 0xca12bc1d, 0xc500323b, + 0xa1389729, 0x7960668b, 0x1aa830fa, 0xb3747d18, + 0xc9f76d2b, 0xa45aa3ee, 0xe1e5c52f, 0x392801b8, + 0xf6c5f65a, 0xe4bb99f7, 0x064609ce, 0xfc3fb330, + 0xb18648b4, 0x0460f5db, 0x19a4400c, 0xfd4baba0, + 0x5d454c12, 0x0969ec61, 0xb3708801, 0x66979fc3, + 0xf8723896, 0xd0c62bd4, 0x79987ff6, 0x1d87cd02, + 0x7a63d5c1, 0x7869c9d6, 0xed419752, 0xd05dbe44 +#endif /* defined __ARMEB__ */ +}; + +uint32_t const DomainParam_Koblitz_secp256k1[] = +{ +#ifndef __ARMEB__ /* Little endian */ + 0xf3ec45eb, 0x9f376f69, 0x6973eaba, 0x25b0dba7, + 0x0637fda1, 0x8cb68991, 0xac46cb0a, 0x565158e1, + 0xb28f7c57, 0x3eb4f15a, 0x72950c88, 0x6a619bad, + 0x148b76dc, 0xa09ea3e4, 0x9c193546, 0xa25b117a, + 0x37f8bc08, 0xfd64f530, 0xcd68fc93, 0xb9e0ddd1, + 0xb5b6ff25, 0xabe2f486, 0x996a37c6, 0x7d4dce22, + 0x387fb3f5, 0x52aa26db, 0x68974e38, 0x33565eb1, + 0xb8c8da3e, 0xb6738101, 0xb4649e75, 0xcf40f52d, + 0xf284c2f5, 0x32a88e0d, 0x1c0ac5eb, 0xe7278fe9, + 0xefa1a48d, 0x86548057, 0x1b5eee70, 0xc7ae86f9, + 0xce9cc7b8, 0x051e2c9d, 0xdd51ab4b, 0xcd958b36, + 0x6684eec9, 0x36c0818b, 0x731ef23f, 0x484eb066, + 0x971ecdbc, 0x8f62ca15, 0x887b3c1f, 0x23a530f0, + 0xb8571c8d, 0xfd2e203f, 0xa4d9b532, 0x3670b7e5, + 0x48aca979, 0x5c6da253, 0xda40e623, 0xccd03cf2, + 0x7195a73c, 0x9c14664c, 0x96edf703, 0x978068ac, + 0x4de690d5, 0x82477b24, 0x0b0bbb57, 0xda6cca18, + 0x3b27980b, 0xf3420afe, 0xfe948a75, 0xc7f4bbf7 + +#else /* Big endian */ + 0xeb45ecf3, 0x696f379f, 0xbaea7369, 0xa7dbb025, + 0xa1fd3706, 0x9189b68c, 0x0acb46ac, 0xe1585156, + 0x577c8fb2, 0x5af1b43e, 0x880c9572, 0xad9b616a, + 0xdc768b14, 0xe4a39ea0, 0x4635199c, 0x7a115ba2, + 0x08bcf837, 0x30f564fd, 0x93fc68cd, 0xd1dde0b9, + 0x25ffb6b5, 0x86f4e2ab, 0xc6376a99, 0x22ce4d7d, + 0xf5b37f38, 0xdb26aa52, 0x384e9768, 0xb15e5633, + 0x3edac8b8, 0x018173b6, 0x759e64b4, 0x2df540cf, + 0xf5c284f2, 0x0d8ea832, 0xebc50a1c, 0xe98f27e7, + 0x8da4a1ef, 0x57805486, 0x70ee5e1b, 0xf986aec7, + 0xb8c79cce, 0x9d2c1e05, 0x4bab51dd, 0x368b95cd, + 0xc9ee8466, 0x8b81c036, 0x3ff21e73, 0x66b04e48, + 0xbccd1e97, 0x15ca628f, 0x1f3c7b88, 0xf030a523, + 0x8d1c57b8, 0x3f202efd, 0x32b5d9a4, 0xe5b77036, + 0x79a9ac48, 0x53a26d5c, 0x23e640da, 0xf23cd0cc, + 0x3ca79571, 0x4c66149c, 0x03f7ed96, 0xac688097, + 0xd590e64d, 0x247b4782, 0x57bb0b0b, 0x18ca6cda, + 0x0b98273b, 0xfe0a42f3, 0x758a94fe, 0xf7bbf4c7 +#endif /* defined __ARMEB__ */ +}; + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func008.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func008.c new file mode 100644 index 000000000..8763cfbab --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func008.c @@ -0,0 +1,86 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func008 (void) +{ + WR1_PROG(REG_B4H, 0x0037000fU); + WR1_PROG(REG_B8H, 0x00190005U); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x00370014U); + WR1_PROG(REG_B8H, 0x001e0005U); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x00190019U); + WR1_PROG(REG_B8H, 0x000f0005U); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x005f000fU); + WR1_PROG(REG_B8H, 0x00140005U); + + WR1_PROG(REG_A4H, 0x04040005U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x00190014U); + WR1_PROG(REG_B8H, 0x000f0005U); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x0064000fU); + WR1_PROG(REG_B8H, 0x00140005U); + + WR1_PROG(REG_A4H, 0x04040005U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x001e001eU); + WR1_PROG(REG_B8H, 0x000f0005U); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x0014000fU); + WR1_PROG(REG_B8H, 0x00230000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_40H, 0x00210000U); + + WR1_PROG(REG_B4H, 0x000f0014U); + WR1_PROG(REG_B8H, 0x00230000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_40H, 0x00210000U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func043.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func043.c new file mode 100644 index 000000000..620fb578b --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func043.c @@ -0,0 +1,93 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func043 (void) +{ + WR1_PROG(REG_A0H, 0x00010000U); + + HW_SCE_p_func100(0x8e389e5eU, 0xbf24033dU, 0x7a882180U, 0x3de84865U); + WR1_PROG(REG_B0H, 0x00001898U); + WR1_PROG(REG_D0H, 0x08000085U); + WR1_PROG(REG_00H, 0x00430011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0xc8abd055U, 0xaf022a14U, 0x43fe3a31U, 0x214b2c28U); + WR1_PROG(REG_D0H, 0x08000095U); + WR1_PROG(REG_00H, 0x00430011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0xe963a30dU, 0xfd25ea85U, 0x38a919bfU, 0xdb8ae843U); + + WR1_PROG(REG_94H, 0x000008a5U); + + WR1_PROG(REG_D0H, 0x080000c5U); + WR1_PROG(REG_B0H, 0x00000893U); + WR1_PROG(REG_00H, 0x00430009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_B0H, 0x00000894U); + WR1_PROG(REG_00H, 0x00430009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_D0H, 0x0b040104U); + WR1_PROG(REG_9CH, 0x810100c0U); + WR1_PROG(REG_00H, 0x00490005U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_9CH, 0x80840005U); + WR1_PROG(REG_00H, 0x03410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_94H, 0x00003845U); + WR1_PROG(REG_94H, 0x00008c40U); + WR1_PROG(REG_94H, 0x00ffffffU); + WR1_PROG(REG_94H, 0x00009040U); + WR1_PROG(REG_94H, 0x01000000U); + WR1_PROG(REG_94H, 0x00003c45U); + + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x30009105U); + WR1_PROG(REG_9CH, 0x81840005U); + WR1_PROG(REG_00H, 0x00490011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_94H, 0x00008c40U); + WR1_PROG(REG_94H, 0x00ffffffU); + WR1_PROG(REG_94H, 0x00009040U); + WR1_PROG(REG_94H, 0x02000000U); + WR1_PROG(REG_94H, 0x00003c45U); + + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x30009045U); + WR1_PROG(REG_9CH, 0x81840005U); + WR1_PROG(REG_00H, 0x00490011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0x9aa1b558U, 0x89ec1951U, 0x26740fe4U, 0x27381492U); + WR1_PROG(REG_D0H, 0x08000085U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0x82844ed4U, 0xbf7a5757U, 0xd337bbabU, 0xf8008d6bU); + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c000094U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_94H, 0x00007c07U); + WR1_PROG(REG_40H, 0x00602000U); + WR1_PROG(REG_24H, 0x00000000U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func044.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func044.c new file mode 100644 index 000000000..c3445b1a1 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func044.c @@ -0,0 +1,50 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func044 (void) +{ + WR1_PROG(REG_94H, 0x00008cc0U); + WR1_PROG(REG_94H, 0x00ffffffU); + WR1_PROG(REG_94H, 0x000090c0U); + WR1_PROG(REG_94H, 0x01000000U); + + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x30009104U); + WR1_PROG(REG_9CH, 0x810100c0U); + WR1_PROG(REG_00H, 0x00490005U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_94H, 0x00008cc0U); + WR1_PROG(REG_94H, 0x00ffffffU); + WR1_PROG(REG_94H, 0x000090c0U); + WR1_PROG(REG_94H, 0x02000000U); + + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x30009044U); + WR1_PROG(REG_9CH, 0x810100c0U); + WR1_PROG(REG_00H, 0x00490005U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0x557291dfU, 0xab11119fU, 0x8e2ea344U, 0x6ec6e690U); + WR1_PROG(REG_D0H, 0x08000085U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0xd49ae696U, 0x6384130bU, 0xb60237f3U, 0x6cb3510aU); + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c000094U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_94H, 0x00007c07U); + WR1_PROG(REG_40H, 0x00602000U); + WR1_PROG(REG_24H, 0x00000000U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func048.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func048.c new file mode 100644 index 000000000..36eaf0fb0 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func048.c @@ -0,0 +1,16 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func048 (const uint32_t ARG1[]) +{ + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x80010000U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(ARG1[0])); + WR1_PROG(REG_24H, 0x00000000U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func049.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func049.c new file mode 100644 index 000000000..00e0c5b76 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func049.c @@ -0,0 +1,16 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func049 (const uint32_t ARG1[]) +{ + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x80010080U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, ARG1[0]); + WR1_PROG(REG_24H, 0x00000000U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func056.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func056.c new file mode 100644 index 000000000..7b06b733e --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func056.c @@ -0,0 +1,19 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func056 (void) +{ + WR1_PROG(REG_94H, 0x38005844U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + WR1_PROG(REG_94H, 0x3420a880U); + WR1_PROG(REG_94H, 0x00000020U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00A60000U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func057.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func057.c new file mode 100644 index 000000000..7d92259c3 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func057.c @@ -0,0 +1,113 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func057 (const uint32_t ARG1[], const uint32_t ARG2[], uint32_t ARG3[]) +{ + uint32_t iLoop = 0U; + uint32_t oLoop = 0U; + + WR1_PROG(REG_94H, 0x00003467U); + + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D0H, 0x08000065U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG1[0]); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x08000074U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_94H, 0x000034c0U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x0000f057U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0x4c437ef4U, 0xf183082bU, 0x036cbc0bU, 0xb2679d51U); + HW_SCE_p_func043(); + + WR1_PROG(REG_94H, 0x000034c4U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x0000f057U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0xf06e7e8fU, 0xcd47bb6eU, 0xcb0f84e9U, 0x2caf947aU); + HW_SCE_p_func044(); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x08000044U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x08000054U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + oLoop = 0U; + for (iLoop = 0U; iLoop < (INST_DATA_SIZE - 4); ) + { + HW_SCE_p_func100(0x3cb9c1e8U, 0xe3a43a93U, 0xdc4c8215U, 0x835fe270U); + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D0H, 0xd922090dU); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG2[iLoop]); + + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0xe7008d05U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_08H, 0x00001012U); + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &ARG3[1 + iLoop]); + + HW_SCE_p_func101(0x38335429U, 0x6f036347U, 0x64ebe0a6U, 0x729068d1U); + iLoop = iLoop + 4U; + } + + oLoop = iLoop; + + HW_SCE_p_func100(0x1f39ac92U, 0xcb5c9da3U, 0x4559a597U, 0x6f7a7f61U); + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c000104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x09108105U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_08H, 0x00001012U); + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &ARG3[1 + oLoop]); + + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D0H, 0x0922090dU); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG2[iLoop]); + + WR1_PROG(REG_D0H, 0x9c300005U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_94H, 0x000034e3U); + + WR1_PROG(REG_94H, 0x00007c07U); + WR1_PROG(REG_40H, 0x00602000U); + WR1_PROG(REG_24H, 0x00000000U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func058.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func058.c new file mode 100644 index 000000000..3cd36e635 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func058.c @@ -0,0 +1,63 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func058 (const uint32_t ARG1[], uint32_t ARG2) +{ + HW_SCE_p_func100(0xbbbfda21U, 0x17944ed0U, 0x0a552a41U, 0x49492666U); + WR1_PROG(REG_D0H, 0x4a070044U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_D0H, 0x0e0704c4U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x017a1b82U)); + + HW_SCE_p_func100(0x789979acU, 0x30731f75U, 0x9f18dd36U, 0xa2776335U); + WR1_PROG(REG_94H, 0x00009020U); + WR1_PROG(REG_94H, 0x01000000U); + + WR1_PROG(REG_D0H, 0x4a040044U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_D0H, 0x0e0404c4U); + WR1_PROG(REG_9CH, 0x81010020U); + WR1_PROG(REG_00H, 0x00490005U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0x607b3f38U, 0xd59a5b21U, 0x23c741c9U, 0xabb8971dU); + WR1_PROG(REG_D0H, 0xf7041c85U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &S_FLASH[ARG2]); + + HW_SCE_p_func100(0x40cc7015U, 0x5f864117U, 0x59d85843U, 0x9823a95dU); + WR1_PROG(REG_D0H, 0x07040d05U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &S_FLASH[ARG2 + 4]); + + WR1_PROG(REG_D0H, 0x8c100005U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D0H, 0x0a0000adU); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG1[0]); + + HW_SCE_p_func100(0xc37244c7U, 0x3ef27430U, 0xe87665dfU, 0x12ce27fbU); + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D0H, 0x0a0000bdU); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG1[4]); + + WR1_PROG(REG_94H, 0x00007c07U); + WR1_PROG(REG_40H, 0x00602000U); + WR1_PROG(REG_24H, 0x00000000U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func070.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func070.c new file mode 100644 index 000000000..c1aef775a --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func070.c @@ -0,0 +1,82 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func070 (const uint32_t ARG1[]) +{ + WR1_PROG(REG_D0H, 0x300710c4U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x01d65d11U)); + + WR1_PROG(REG_A0H, 0x20010000U); + WR1_PROG(REG_B0H, 0x00001405U); + WR1_PROG(REG_14H, 0x00002fc1U); + WR1_PROG(REG_D4H, 0x00000b00U); + WR1_PROG(REG_D0H, 0xf7049d07U); + + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG1[20]); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG1[24]); + WR1_PROG(REG_00H, 0x00c10021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_B0H, 0x00001437U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG1[28]); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG1[32]); + WR1_PROG(REG_00H, 0x00c10021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_B0H, 0x0000145fU); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG1[36]); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG1[40]); + WR1_PROG(REG_00H, 0x00c10021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_B0H, 0x00001464U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG1[44]); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG1[48]); + WR1_PROG(REG_00H, 0x00c10021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_B0H, 0x0000140aU); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG1[52]); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG1[56]); + WR1_PROG(REG_00H, 0x00c10021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_B0H, 0x0000145aU); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG1[60]); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG1[64]); + WR1_PROG(REG_00H, 0x00c10021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_D0H, 0x07040d05U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG1[68]); + + WR1_PROG(REG_D0H, 0x8c100005U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func071.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func071.c new file mode 100644 index 000000000..3a089a3ee --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func071.c @@ -0,0 +1,45 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func071 (const uint32_t ARG1[]) +{ + WR1_PROG(REG_D0H, 0x300710c4U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x01b03468U)); + + WR1_PROG(REG_A0H, 0x20010000U); + WR1_PROG(REG_B0H, 0x00001419U); + WR1_PROG(REG_14H, 0x00000fc1U); + WR1_PROG(REG_D4H, 0x00000300U); + WR1_PROG(REG_D0H, 0xf7049d07U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG1[0]); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG1[4]); + WR1_PROG(REG_00H, 0x00c10021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_B0H, 0x0000141eU); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG1[8]); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG1[12]); + WR1_PROG(REG_00H, 0x00c10021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_D0H, 0x07040d05U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG1[16]); + + WR1_PROG(REG_D0H, 0x8c100005U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func073.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func073.c new file mode 100644 index 000000000..58a4eb278 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func073.c @@ -0,0 +1,572 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func073 (const uint32_t ARG1[]) +{ + HW_SCE_p_func070(ARG1); + + WR1_PROG(REG_A0H, 0x20010000U); + + WR1_PROG(REG_B8H, 0x0000000aU); + + WR1_PROG(REG_A4H, 0x04040010U); + + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B0H, 0x0000141eU); + WR1_PROG(REG_00H, 0x00c0001dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_14H, 0x000000a5U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000001U)); + + WR1_PROG(REG_B4H, 0x001e000aU); + WR1_PROG(REG_B8H, 0x00140000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x00690014U); + WR1_PROG(REG_B8H, 0x00190000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_40H, 0x00210000U); + + WR1_PROG(REG_B4H, 0x001e0069U); + WR1_PROG(REG_B8H, 0x00190000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + WR1_PROG(REG_40H, 0x00210000U); + + WR1_PROG(REG_B4H, 0x006e0014U); + WR1_PROG(REG_B8H, 0x00190000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_40H, 0x00210000U); + + WR1_PROG(REG_B4H, 0x001e006eU); + WR1_PROG(REG_B8H, 0x00190000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_40H, 0x00210000U); + + HW_SCE_p_func100(0x056e32b7U, 0x2da176dcU, 0x8f1aa02fU, 0x1d084950U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + WR1_PROG(REG_94H, 0x00000800U); + + HW_SCE_p_func101(0xb54cbd3dU, 0xf17d8352U, 0x1166b7ccU, 0xe38eed20U); + } + else + { + HW_SCE_p_func100(0xfefd37f9U, 0x512acb6bU, 0x0dd874ecU, 0x99e8df0fU); + + WR1_PROG(REG_B4H, 0x001e0014U); + WR1_PROG(REG_B8H, 0x00190000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x0019006eU); + WR1_PROG(REG_B8H, 0x000f000aU); + + WR1_PROG(REG_A4H, 0x04040000U); + WR1_PROG(REG_08H, 0x00020000U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + WR1_PROG(REG_40H, 0x00000d00U); + + WR1_PROG(REG_B4H, 0x005a000fU); + WR1_PROG(REG_B8H, 0x0014000aU); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B0H, 0x00001423U); + WR1_PROG(REG_00H, 0x00c00021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_B4H, 0x00230072U); + WR1_PROG(REG_B8H, 0x000f0000U); + + WR1_PROG(REG_A4H, 0x04040009U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x0014000fU); + WR1_PROG(REG_B8H, 0x000f000aU); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x00140069U); + WR1_PROG(REG_B8H, 0x0032000aU); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B8H, 0x00000005U); + + WR1_PROG(REG_A4H, 0x04040010U); + + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x00370076U); + WR1_PROG(REG_B8H, 0x00190005U); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x0037007aU); + WR1_PROG(REG_B8H, 0x001e0005U); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B0H, 0x00001414U); + WR1_PROG(REG_00H, 0x00c0001dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_14H, 0x000000a5U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000001U)); + + WR1_PROG(REG_B4H, 0x00140037U); + WR1_PROG(REG_B8H, 0x00230005U); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B0H, 0x00001414U); + WR1_PROG(REG_00H, 0x00c00021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_B4H, 0x0014005fU); + WR1_PROG(REG_B8H, 0x00280000U); + + WR1_PROG(REG_A4H, 0x04040009U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + HW_SCE_p_func100(0xbde8b68cU, 0xfab07457U, 0x2493fbcaU, 0xa60008d2U); + WR1_PROG(REG_B4H, 0x00140005U); + WR1_PROG(REG_B8H, 0x002d0000U); + + WR1_PROG(REG_A4H, 0x04040009U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x00320023U); + WR1_PROG(REG_B8H, 0x0055002dU); + + WR1_PROG(REG_A4H, 0x04040015U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + WR1_PROG(REG_40H, 0x00000d00U); + + WR1_PROG(REG_B0H, 0x0000141eU); + WR1_PROG(REG_00H, 0x00c0001dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_14H, 0x000000a5U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000001U)); + + WR1_PROG(REG_B4H, 0x001e0055U); + WR1_PROG(REG_B8H, 0x00190000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_40H, 0x00210000U); + + HW_SCE_p_func100(0x70bd2501U, 0x1701aef4U, 0x928ab38cU, 0xd6acfd36U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + WR1_PROG(REG_94H, 0x00000800U); + + HW_SCE_p_func101(0x5602eec5U, 0x04c2f794U, 0x871ec4f6U, 0xe6522e43U); + } + else + { + WR1_PROG(REG_B4H, 0x001e000fU); + WR1_PROG(REG_B8H, 0x00190000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_40H, 0x00210000U); + + HW_SCE_p_func100(0x52715911U, 0x08e95d86U, 0x4a005f1bU, 0x058b1dd3U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func100(0xfdf38eb2U, 0x60ee8121U, 0x9fe25c9aU, 0x747a044bU); + WR1_PROG(REG_B4H, 0x0014004bU); + WR1_PROG(REG_B8H, 0x00190000U); + + WR1_PROG(REG_A4H, 0x04040009U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x00140050U); + WR1_PROG(REG_B8H, 0x001e0000U); + + WR1_PROG(REG_A4H, 0x04040009U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x00140055U); + WR1_PROG(REG_B8H, 0x00230000U); + + WR1_PROG(REG_A4H, 0x04040009U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B0H, 0x00001414U); + WR1_PROG(REG_00H, 0x00c0001dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_14H, 0x000000a5U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000001U)); + + WR1_PROG(REG_B4H, 0x00140023U); + WR1_PROG(REG_B8H, 0x00280005U); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B0H, 0x00001414U); + WR1_PROG(REG_00H, 0x00c0001dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_14H, 0x000000a5U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000002U)); + + WR1_PROG(REG_B4H, 0x00140005U); + WR1_PROG(REG_B8H, 0x000f0000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x000f0028U); + WR1_PROG(REG_B8H, 0x00140005U); + + WR1_PROG(REG_A4H, 0x04040000U); + WR1_PROG(REG_08H, 0x00020000U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + WR1_PROG(REG_40H, 0x00000d00U); + + WR1_PROG(REG_B4H, 0x00140019U); + WR1_PROG(REG_B8H, 0x00280005U); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x00690028U); + WR1_PROG(REG_B8H, 0x00190000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_40H, 0x00210000U); + + WR1_PROG(REG_B4H, 0x00280069U); + WR1_PROG(REG_B8H, 0x00190000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_40H, 0x00210000U); + + HW_SCE_p_func100(0x5fa71709U, 0x7eea20e0U, 0xc161149aU, 0x571cf1bbU); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + WR1_PROG(REG_94H, 0x00000800U); + + HW_SCE_p_func101(0x2d968a02U, 0xd245f367U, 0xc25fc0bfU, 0x1ab60bb6U); + } + else + { + WR1_PROG(REG_94H, 0x0000b400U); + WR1_PROG(REG_94H, 0x740d7282U); + + HW_SCE_p_func101(0x81636b7fU, 0x5cf33a57U, 0xfc42aa12U, 0xd599c1a1U); + } + } + else + { + HW_SCE_p_func100(0x32f03e83U, 0xa344f7e3U, 0xcccaa091U, 0xeac4a81bU); + WR1_PROG(REG_B4H, 0x0014000fU); + WR1_PROG(REG_B8H, 0x00320000U); + + WR1_PROG(REG_A4H, 0x04040009U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B0H, 0x00000415U); + WR1_PROG(REG_00H, 0x00c00009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_B0H, 0x0000041aU); + WR1_PROG(REG_00H, 0x00c00009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + HW_SCE_p_func071(ARG1); + + WR1_PROG(REG_B4H, 0x00320023U); + WR1_PROG(REG_B8H, 0x0046002dU); + + WR1_PROG(REG_A4H, 0x04040015U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + WR1_PROG(REG_40H, 0x00000d00U); + + WR1_PROG(REG_B0H, 0x0000141eU); + WR1_PROG(REG_00H, 0x00c0001dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_14H, 0x000000a5U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000001U)); + + WR1_PROG(REG_B4H, 0x001e0046U); + WR1_PROG(REG_B8H, 0x00190000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_40H, 0x00210000U); + + HW_SCE_p_func100(0x597ddfe8U, 0x6306ea48U, 0x5ddb1460U, 0xc8bad192U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + WR1_PROG(REG_94H, 0x00000800U); + + HW_SCE_p_func101(0x5990ee72U, 0x4b4e494bU, 0x92ff91afU, 0x82051d17U); + } + else + { + WR1_PROG(REG_B4H, 0x00550046U); + WR1_PROG(REG_B8H, 0x00230005U); + + WR1_PROG(REG_A4H, 0x04040013U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + WR1_PROG(REG_40H, 0x00000d00U); + + WR1_PROG(REG_B0H, 0x00001414U); + WR1_PROG(REG_00H, 0x00c0001dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_14H, 0x000000a5U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000001U)); + + WR1_PROG(REG_B4H, 0x00140023U); + WR1_PROG(REG_B8H, 0x002d0000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_40H, 0x00210000U); + + HW_SCE_p_func100(0x45738d33U, 0xab94d1e6U, 0xe6d6a6b1U, 0xe48b985dU); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + WR1_PROG(REG_94H, 0x00000800U); + + HW_SCE_p_func101(0x7b267b59U, 0x261e8c94U, 0x82f879e3U, 0x08a5737aU); + } + else + { + HW_SCE_p_func100(0x70668f9fU, 0x47343c20U, 0x4f6bbdd5U, 0xdbce9747U); + + WR1_PROG(REG_B4H, 0x00140023U); + WR1_PROG(REG_B8H, 0x00280005U); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B0H, 0x00001414U); + WR1_PROG(REG_00H, 0x00c0001dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_14H, 0x000000a5U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000002U)); + + WR1_PROG(REG_B4H, 0x00140005U); + WR1_PROG(REG_B8H, 0x000f0000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x000f0028U); + WR1_PROG(REG_B8H, 0x00140005U); + + WR1_PROG(REG_A4H, 0x04040000U); + WR1_PROG(REG_08H, 0x00020000U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + WR1_PROG(REG_40H, 0x00000d00U); + + WR1_PROG(REG_B4H, 0x00140019U); + WR1_PROG(REG_B8H, 0x00280005U); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x00690028U); + WR1_PROG(REG_B8H, 0x00190000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_40H, 0x00210000U); + + WR1_PROG(REG_B4H, 0x00280069U); + WR1_PROG(REG_B8H, 0x00190000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_40H, 0x00210000U); + + HW_SCE_p_func100(0x48b7d3aaU, 0x40a756c8U, 0x002446bbU, 0xae8329dcU); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + WR1_PROG(REG_94H, 0x00000800U); + + HW_SCE_p_func101(0x1b562b57U, 0x23de575aU, 0x3c426f52U, 0x24228fccU); + } + else + { + WR1_PROG(REG_94H, 0x0000b400U); + WR1_PROG(REG_94H, 0x740d7282U); + + HW_SCE_p_func101(0x6c687973U, 0x271de84aU, 0xae5cfeceU, 0xb1b41057U); + } + } + } + } + } + } + + WR1_PROG(REG_94H, 0x38008800U); + WR1_PROG(REG_94H, 0x740d7282U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00A60000U); + + WR1_PROG(REG_94H, 0x00007c07U); + WR1_PROG(REG_40H, 0x00602000U); + WR1_PROG(REG_24H, 0x00000000U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func088.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func088.c new file mode 100644 index 000000000..37b034c9f --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func088.c @@ -0,0 +1,161 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func088 (void) +{ + HW_SCE_p_func100(0xc26c2c17U, 0x81c5a08bU, 0x5fe8a41fU, 0xedddf4a8U); + WR1_PROG(REG_B0H, 0x00001428U); + WR1_PROG(REG_00H, 0x00c0001dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_14H, 0x000000a5U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000001U)); + + WR1_PROG(REG_B8H, 0x00000005U); + + WR1_PROG(REG_A4H, 0x04040010U); + + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x00280037U); + WR1_PROG(REG_B8H, 0x00230005U); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B0H, 0x0000143cU); + WR1_PROG(REG_00H, 0x00c00021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_B4H, 0x003c005fU); + WR1_PROG(REG_B8H, 0x00280000U); + + WR1_PROG(REG_A4H, 0x04040009U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x003c0005U); + WR1_PROG(REG_B8H, 0x002d0000U); + + WR1_PROG(REG_A4H, 0x04040009U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x00320023U); + WR1_PROG(REG_B8H, 0x0055002dU); + + WR1_PROG(REG_A4H, 0x04040015U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + WR1_PROG(REG_40H, 0x00000d00U); + + WR1_PROG(REG_B0H, 0x0000140fU); + WR1_PROG(REG_00H, 0x00c0001dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_14H, 0x000000a5U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000001U)); + + WR1_PROG(REG_B4H, 0x000f0055U); + WR1_PROG(REG_B8H, 0x00190000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_40H, 0x00210000U); + + HW_SCE_p_func100(0xba0b2e66U, 0x0052c35fU, 0x8674892aU, 0x952cad34U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + WR1_PROG(REG_94H, 0x00000800U); + + HW_SCE_p_func101(0x8139d9c5U, 0x723cf07eU, 0x0db00ea9U, 0x277f3f2cU); + } + else + { + HW_SCE_p_func100(0x154c81b6U, 0xf96842c4U, 0x63bfabddU, 0xf778ec0bU); + WR1_PROG(REG_B4H, 0x000f0055U); + WR1_PROG(REG_B8H, 0x00230005U); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B0H, 0x00001414U); + WR1_PROG(REG_00H, 0x00c0001dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_14H, 0x000000a5U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000002U)); + + WR1_PROG(REG_B4H, 0x00140005U); + WR1_PROG(REG_B8H, 0x000f0000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x000f0023U); + WR1_PROG(REG_B8H, 0x00140005U); + + WR1_PROG(REG_A4H, 0x04040000U); + WR1_PROG(REG_08H, 0x00020000U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + WR1_PROG(REG_40H, 0x00000d00U); + + WR1_PROG(REG_B4H, 0x0014004bU); + WR1_PROG(REG_B8H, 0x00280005U); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x00140050U); + WR1_PROG(REG_B8H, 0x002d0005U); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_94H, 0x0000b400U); + WR1_PROG(REG_94H, 0xc9b7be57U); + + HW_SCE_p_func101(0x4f70857fU, 0xf4fc55d8U, 0x2eb242acU, 0x02c09f48U); + } + + WR1_PROG(REG_94H, 0x38008800U); + WR1_PROG(REG_94H, 0xc9b7be57U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00A60000U); + + WR1_PROG(REG_94H, 0x00007c07U); + WR1_PROG(REG_40H, 0x00602000U); + WR1_PROG(REG_24H, 0x00000000U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func093.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func093.c new file mode 100644 index 000000000..a4ac1ba99 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func093.c @@ -0,0 +1,108 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func093 (const uint32_t ARG1[], uint32_t ARG2[]) +{ + uint32_t iLoop = 0U; + uint32_t oLoop = 0U; + + WR1_PROG(REG_94H, 0x00003467U); + + HW_SCE_p_func100(0xf26d692cU, 0xcf9189b9U, 0x4a2543f1U, 0xef34ef74U); + HW_SCE_p_func103(); + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c200104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_9CH, 0x80010000U); + WR1_PROG(REG_00H, 0x03410005U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_00H, 0x0001000dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_94H, 0x000034c0U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x0000f093U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0x882ddb8fU, 0xa82250e6U, 0x8421c22dU, 0xae30cc4cU); + HW_SCE_p_func043(); + + WR1_PROG(REG_94H, 0x000034c4U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x0000f093U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0xa95fe062U, 0xe0f1a48eU, 0xabeba203U, 0x95c81036U); + HW_SCE_p_func044(); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x08000044U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x08000054U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + oLoop = 0U; + for (iLoop = 0U; iLoop < (INST_DATA_SIZE); ) + { + HW_SCE_p_func100(0x72bfa833U, 0xff8cb213U, 0x8112c7cfU, 0x7fc571aaU); + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D0H, 0x08000105U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &ARG1[iLoop]); + + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0xe7008d05U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_08H, 0x00001012U); + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &ARG2[1 + iLoop]); + + HW_SCE_p_func101(0xfa2b8363U, 0xfef991bdU, 0xf1631ffaU, 0xaa454934U); + iLoop = iLoop + 4U; + } + + oLoop = iLoop; + + HW_SCE_p_func100(0xdd637773U, 0x4456a2f1U, 0xf4152398U, 0x895bad4dU); + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c000104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x09108105U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_08H, 0x00001012U); + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &ARG2[1 + oLoop]); + + WR1_PROG(REG_94H, 0x000034e3U); + + WR1_PROG(REG_94H, 0x00007c07U); + WR1_PROG(REG_40H, 0x00602000U); + WR1_PROG(REG_24H, 0x00000000U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func100.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func100.c new file mode 100644 index 000000000..5b429d12d --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func100.c @@ -0,0 +1,16 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func100 (uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4) +{ + WR1_PROG(REG_D0H, 0x0a0701f5U); + WAIT_STS(REG_14H, 31, 1); + WR4_PROG(REG_2CH, change_endian_long(ARG1), change_endian_long(ARG2), change_endian_long(ARG3), + change_endian_long(ARG4)); + WAIT_STS(REG_C8H, 16, 0); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func101.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func101.c new file mode 100644 index 000000000..a47772fa9 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func101.c @@ -0,0 +1,16 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func101 (uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4) +{ + WR1_PROG(REG_D0H, 0x0a0701e5U); + WAIT_STS(REG_14H, 31, 1); + WR4_PROG(REG_2CH, change_endian_long(ARG1), change_endian_long(ARG2), change_endian_long(ARG3), + change_endian_long(ARG4)); + WAIT_STS(REG_C8H, 17, 0); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func102.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func102.c new file mode 100644 index 000000000..b0ab62631 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func102.c @@ -0,0 +1,15 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func102 (uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4) +{ + WR1_PROG(REG_D0H, 0x0a0701d5U); + WAIT_STS(REG_14H, 31, 1); + WR4_PROG(REG_2CH, change_endian_long(ARG1), change_endian_long(ARG2), change_endian_long(ARG3), + change_endian_long(ARG4)); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func103.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func103.c new file mode 100644 index 000000000..b45480a80 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func103.c @@ -0,0 +1,38 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func103 (void) +{ + WR1_PROG(REG_14H, 0x000002a1U); + WR1_PROG(REG_D0H, 0x07330c04U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_D0H, 0x07330d04U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_D0H, 0x07330d04U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_D0H, 0x08000065U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x06330074U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_D0H, 0x080000b5U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func205.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func205.c new file mode 100644 index 000000000..968401c53 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func205.c @@ -0,0 +1,17 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func205_r1 (void) +{ + WR1_PROG(REG_14H, 0x00000000U); + WAIT_STS(REG_C8H, 6, 0); + WR1_PROG(REG_40H, 0x00000400U); + WR1_PROG(REG_40H, 0x00000600U); + WR1_PROG(REG_40H, 0x00000500U); + WR1_PROG(REG_D0H, 0x00000000U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func206.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func206.c new file mode 100644 index 000000000..eda7c2336 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_func206.c @@ -0,0 +1,18 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func206 (void) +{ + WR1_PROG(REG_08H, 0x00000000U); + WR1_PROG(REG_14H, 0x00000000U); + WAIT_STS(REG_C8H, 6, 0); + WR1_PROG(REG_40H, 0x00000400U); + WR1_PROG(REG_40H, 0x00000600U); + WR1_PROG(REG_40H, 0x00000500U); + WR1_PROG(REG_D0H, 0x00000000U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p00.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p00.c new file mode 100644 index 000000000..bd2ec2c23 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p00.c @@ -0,0 +1,15 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_SoftwareResetSub (void) +{ + WR1_PROG(REG_0CH, 0x00000000U); + WR1_PROG(REG_24H, 0x00000000U); + WR1_PROG(REG_24H, 0x00000000U); + WR1_PROG(REG_24H, 0x00000000U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p07.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p07.c new file mode 100644 index 000000000..c764299f5 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p07.c @@ -0,0 +1,110 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_GenerateAes128RandomKeyIndexSub (uint32_t OutData_KeyIndex[]) +{ + if (RD1_MASK(REG_6CH, 0x00000017U) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_70H, 0x00070001U); + WR1_PROG(REG_4CH, 0x00000000U); + + HW_SCE_p_func100(0xa126d95eU, 0x7c9b58c2U, 0xa08a31b9U, 0x776770c8U); + HW_SCE_p_func103(); + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c200104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_9CH, 0x80010000U); + WR1_PROG(REG_00H, 0x03410005U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_00H, 0x0001000dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_94H, 0x000034c0U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000007U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0x26c31b4bU, 0x74230415U, 0x4b5fbd5cU, 0xb822f63fU); + HW_SCE_p_func043(); + + WR1_PROG(REG_94H, 0x0000b4c0U); + WR1_PROG(REG_94H, 0x00000005U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000007U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0x6872c9c2U, 0xae0ba78dU, 0x22315bbeU, 0x8a9aabbcU); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0xdb310a39U, 0x303ac451U, 0x485052c9U, 0x228508faU); + HW_SCE_p_func103(); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c200104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + WR1_PROG(REG_94H, 0x00000821U); + WR1_PROG(REG_9CH, 0x80840001U); + WR1_PROG(REG_00H, 0x03410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0xcec3a6afU, 0x2dd7d901U, 0x456fd12bU, 0x510f32fcU); + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0xe7009d05U); + WR1_PROG(REG_94H, 0x00000821U); + WR1_PROG(REG_9CH, 0x81840001U); + WR1_PROG(REG_00H, 0x00490011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_08H, 0x00001012U); + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_KeyIndex[1]); + + HW_SCE_p_func100(0x2e95ffa8U, 0x6600abafU, 0xe836fcabU, 0xb6a5e1f3U); + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c000104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x09108105U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_08H, 0x00001012U); + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_KeyIndex[5]); + + HW_SCE_p_func100(0x1345978aU, 0x84f650e5U, 0xdbcbe8a5U, 0x9ba76eb2U); + WR1_PROG(REG_9CH, 0x81010000U); + WR1_PROG(REG_08H, 0x00005006U); + WAIT_STS(REG_08H, 30, 1); + RD1_ADDR(REG_2CH, &OutData_KeyIndex[0]); + + HW_SCE_p_func102(0xe61be1ddU, 0x5cf527e7U, 0x1980189cU, 0xb587fe80U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_SUCCESS; +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p08.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p08.c new file mode 100644 index 000000000..38c851d48 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p08.c @@ -0,0 +1,126 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_GenerateAes256RandomKeyIndexSub (uint32_t OutData_KeyIndex[]) +{ + if (RD1_MASK(REG_6CH, 0x00000017U) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_70H, 0x00080001U); + WR1_PROG(REG_4CH, 0x00000000U); + + HW_SCE_p_func100(0xe627f5a6U, 0x13a2dc85U, 0xdd7be0dbU, 0x30af1342U); + HW_SCE_p_func103(); + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c200104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_9CH, 0x80010000U); + WR1_PROG(REG_00H, 0x03410005U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_00H, 0x0001000dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_94H, 0x000034c0U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000008U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0x265be13fU, 0xf09fafc2U, 0x77c46b81U, 0xa217f390U); + HW_SCE_p_func043(); + + WR1_PROG(REG_94H, 0x0000b4c0U); + WR1_PROG(REG_94H, 0x00000007U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000008U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0x54df670aU, 0xa46ec8a6U, 0xb093a26aU, 0x1b46d340U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0x766ee5c4U, 0xd369993cU, 0x92bc35ecU, 0x944b73f3U); + HW_SCE_p_func103(); + + HW_SCE_p_func100(0x2ff8cbefU, 0x49373096U, 0x65de3d45U, 0x845a80f1U); + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c200104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + WR1_PROG(REG_94H, 0x00000821U); + WR1_PROG(REG_9CH, 0x80840001U); + WR1_PROG(REG_00H, 0x03410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func103(); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c200104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + WR1_PROG(REG_94H, 0x0000b420U); + WR1_PROG(REG_94H, 0x00000010U); + WR1_PROG(REG_9CH, 0x80840001U); + WR1_PROG(REG_00H, 0x03410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0xd9c764b6U, 0xe9e9cf44U, 0x74c8234cU, 0xbbf87a30U); + WR1_PROG(REG_D4H, 0x40000100U); + WR1_PROG(REG_D0H, 0xe7009d07U); + WR1_PROG(REG_94H, 0x00000821U); + WR1_PROG(REG_9CH, 0x81880001U); + WR1_PROG(REG_00H, 0x00490021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_08H, 0x00001022U); + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_KeyIndex[1]); + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_KeyIndex[5]); + + HW_SCE_p_func100(0xf83c4765U, 0xd0918766U, 0xcbe6b4cdU, 0x58eb7b12U); + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c000104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x09108105U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_08H, 0x00001012U); + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_KeyIndex[9]); + + HW_SCE_p_func100(0xff07558eU, 0xf23fc230U, 0xbc66b4e3U, 0x34807c94U); + WR1_PROG(REG_9CH, 0x81010000U); + WR1_PROG(REG_08H, 0x00005006U); + WAIT_STS(REG_08H, 30, 1); + RD1_ADDR(REG_2CH, &OutData_KeyIndex[0]); + + HW_SCE_p_func102(0xec72d13eU, 0xc399374cU, 0x448595cdU, 0xb5da4e36U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_SUCCESS; +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p20.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p20.c new file mode 100644 index 000000000..a6a9e15fc --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p20.c @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_GenerateRandomNumberSub (uint32_t OutData_Text[]) +{ + if (RD1_MASK(REG_6CH, 0x00000017U) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_70H, 0x00200002U); + WR1_PROG(REG_4CH, 0x00000000U); + + HW_SCE_p_func100(0x56354e4dU, 0x73681bfaU, 0xcceafa1fU, 0x06822720U); + HW_SCE_p_func103(); + HW_SCE_p_func100(0xf14f56feU, 0xd8705df0U, 0xe1d6ef6fU, 0xc7223d71U); + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c200104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_08H, 0x00001012U); + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_Text[0]); + + HW_SCE_p_func102(0x0e247ba8U, 0x4b4177beU, 0x27ceab9eU, 0xdbb4d6feU); + + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_SUCCESS; +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p21.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p21.c new file mode 100644 index 000000000..1debecfee --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p21.c @@ -0,0 +1,63 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_GhashSub (const uint32_t InData_HV[], + const uint32_t InData_IV[], + const uint32_t InData_Text[], + uint32_t OutData_DataT[], + const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_68H, 0x00000016U) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_70H, 0x00210001U); + WR1_PROG(REG_4CH, 0x00000000U); + + HW_SCE_p_func100(0x9a60b099U, 0xc2c6d059U, 0x07528517U, 0x9b76f3b3U); + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D0H, 0x080000a5U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_HV[0]); + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D0H, 0x08000055U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_IV[0]); + + WR1_PROG(REG_14H, 0x00020061U); + WR1_PROG(REG_D4H, 0x00008000U); + WR1_PROG(REG_D0H, 0x0e128456U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_Text[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func205_r1(); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c100104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + HW_SCE_p_func100(0xef3b40c4U, 0x3abdff90U, 0x94d7da1fU, 0xe43630cfU); + WR1_PROG(REG_08H, 0x00001012U); + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_DataT[0]); + + HW_SCE_p_func102(0x56624e05U, 0xf357e2c7U, 0x98236fcaU, 0x4e06fbbcU); + WR1_PROG(REG_68H, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_SUCCESS; +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p29a.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p29a.c new file mode 100644 index 000000000..0d123e564 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p29a.c @@ -0,0 +1,27 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes128GcmEncryptUpdateAADSub (const uint32_t InData_DataA[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_14H, 0x00020061U); + WR1_PROG(REG_D4H, 0x00008000U); + WR1_PROG(REG_D0H, 0x0e128456U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_DataA[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func205_r1(); + + HW_SCE_p_func101(0xa45745faU, 0x4ae1358cU, 0xab44bc49U, 0xe53bb307U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p29f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p29f.c new file mode 100644 index 000000000..727c97aac --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p29f.c @@ -0,0 +1,150 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128GcmEncryptFinalSub (const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_DataALen[], + uint32_t OutData_Text[], + uint32_t OutData_DataT[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_14H, 0x000001c7U); + WR1_PROG(REG_9CH, 0x80020040U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_TextLen[0]); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_TextLen[1]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_94H, 0x0000b400U); + WR1_PROG(REG_94H, 0x0000007FU); + WR1_PROG(REG_94H, 0x0000b420U); + WR1_PROG(REG_94H, 0xFFFFFF00U); + WR1_PROG(REG_94H, 0x0c002823U); + WR1_PROG(REG_94H, 0x04a02802U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + HW_SCE_p_func100(0x88894300U, 0x1bccb8c3U, 0xec0432dbU, 0x54099e76U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0x5ed35366U, 0x60a441a3U, 0xc2ca981cU, 0x84ee1ba4U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_94H, 0x00003403U); + WR1_PROG(REG_94H, 0x00036800U); + + WR1_PROG(REG_94H, 0x08008c00U); + WR1_PROG(REG_94H, 0x0000000fU); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00A60000U); + + HW_SCE_p_func100(0xf67fa0dbU, 0xa532d818U, 0x6cb68751U, 0x863dce91U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func100(0xca3feb6eU, 0x5f8c5dc1U, 0x196966d6U, 0xefc37e08U); + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D4H, 0x00000020U); + WR1_PROG(REG_D0H, 0x07008d05U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_Text[0]); + + WR1_PROG(REG_94H, 0x00000821U); + WR1_PROG(REG_9CH, 0x80840001U); + WR1_PROG(REG_00H, 0x03410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_94H, 0x00000884U); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_94H, 0x3c002820U); + WR1_PROG(REG_94H, 0x12003c81U); + WR1_PROG(REG_94H, 0x00002c20U); + } + + WR1_PROG(REG_D4H, 0x00008000U); + WR1_PROG(REG_D0H, 0x0e128455U); + WR1_PROG(REG_94H, 0x00000821U); + WR1_PROG(REG_9CH, 0x81840001U); + WR1_PROG(REG_00H, 0x00490011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WAIT_STS(REG_C8H, 6, 0); + WR1_PROG(REG_40H, 0x00000400U); + WR1_PROG(REG_40H, 0x00000500U); + + WR1_PROG(REG_9CH, 0x81840001U); + WR1_PROG(REG_08H, 0x00005012U); + WAIT_STS(REG_08H, 30, 1); + RD1_ADDR(REG_2CH, &OutData_Text[0]); + WAIT_STS(REG_08H, 30, 1); + RD1_ADDR(REG_2CH, &OutData_Text[1]); + WAIT_STS(REG_08H, 30, 1); + RD1_ADDR(REG_2CH, &OutData_Text[2]); + WAIT_STS(REG_08H, 30, 1); + RD1_ADDR(REG_2CH, &OutData_Text[3]); + + HW_SCE_p_func101(0x19464602U, 0xcde619edU, 0x4896fc96U, 0xe7edecd2U); + } + + HW_SCE_p_func100(0x81b5f1c2U, 0xc3fffe77U, 0xbf3d7fb9U, 0x06f56007U); + WR1_PROG(REG_14H, 0x000001c1U); + WR1_PROG(REG_D4H, 0x00008000U); + WR1_PROG(REG_D0H, 0x0e128455U); + WAIT_STS(REG_14H, 31, 1); + WR2_ADDR(REG_2CH, &InData_DataALen[0]); + + WR1_PROG(REG_9CH, 0x81020040U); + WR1_PROG(REG_00H, 0x00490009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_D0H, 0x08000045U); + WR1_PROG(REG_94H, 0x0000b420U); + WR1_PROG(REG_94H, 0x00000010U); + WR1_PROG(REG_9CH, 0x81840001U); + WR1_PROG(REG_00H, 0x00490011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c100104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_D4H, 0x00000020U); + WR1_PROG(REG_D0H, 0x07008d05U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_08H, 0x00001012U); + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_DataT[0]); + + HW_SCE_p_func102(0x1a085af7U, 0x4e8e3030U, 0x1c77694dU, 0x7604c6b6U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_SUCCESS; + } +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p29i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p29i.c new file mode 100644 index 000000000..56529ae56 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p29i.c @@ -0,0 +1,161 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128GcmEncryptInitSub (const uint32_t InData_KeyMode[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_6CH, 0x00000017U) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_70H, 0x00290001U); + WR1_PROG(REG_4CH, 0x00000000U); + + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x80010000U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_KeyMode[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_94H, 0x38000c00U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + HW_SCE_p_func100(0xe34b4cfbU, 0xa6fd3ba9U, 0xa42bdc25U, 0x8a41f36cU); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x800100c0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_KeyIndex[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000029U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0x1fce8aedU, 0x8d40f9e3U, 0x07694d54U, 0x71763db1U); + HW_SCE_p_func043(); + + WR1_PROG(REG_94H, 0x0000b4c0U); + WR1_PROG(REG_94H, 0x00000005U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000029U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0x4fe6cb86U, 0xbcfa40e3U, 0x5fb69566U, 0xe13e79c2U); + HW_SCE_p_func044(); + + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0xf7009d05U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_KeyIndex[1]); + + WR1_PROG(REG_B0H, 0x00000401U); + WR1_PROG(REG_00H, 0x00c10009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_B0H, 0x00000402U); + WR1_PROG(REG_00H, 0x00c10009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x07008d05U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_KeyIndex[5]); + + WR1_PROG(REG_D0H, 0x9c100005U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func101(0xfad003b3U, 0xdc0e4becU, 0x6f4a4299U, 0xac317411U); + } + else + { + WR1_PROG(REG_14H, 0x000003c5U); + WR1_PROG(REG_B0H, 0x00000401U); + WAIT_STS(REG_14H, 31, 1); + WR2_ADDR(REG_2CH, &InData_Key[0]); + WR1_PROG(REG_B0H, 0x00000402U); + WAIT_STS(REG_14H, 31, 1); + WR2_ADDR(REG_2CH, &InData_Key[2]); + + HW_SCE_p_func101(0x9cc93e55U, 0x95c2e696U, 0x01d5f5adU, 0xfea87701U); + } + + HW_SCE_p_func100(0xd145bd85U, 0x42a9434cU, 0xdf4d1a63U, 0x10f51c1cU); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0x7ca21ab6U, 0xa0ffd120U, 0xac0d5eb1U, 0xb349ba04U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0x74567fcbU, 0xd4d04a56U, 0x0bf57e4bU, 0x56506eb2U); + WR1_PROG(REG_D0H, 0x08000085U); + WR1_PROG(REG_B0H, 0x00000801U); + WR1_PROG(REG_00H, 0x00430009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_B0H, 0x00000802U); + WR1_PROG(REG_00H, 0x00430009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0x585dbf03U, 0xba484ea9U, 0xb0d9fda4U, 0x4d6e6c18U); + WR1_PROG(REG_14H, 0x000003c7U); + WR1_PROG(REG_94H, 0x0000b420U); + WR1_PROG(REG_94H, 0x00000010U); + WR1_PROG(REG_9CH, 0x80840001U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_IV[0]); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_IV[1]); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_IV[2]); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_IV[3]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x08000054U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0a0000a4U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + HW_SCE_p_func101(0x4c333a0eU, 0xa66b8fa6U, 0x9b08e719U, 0x3b528231U); + + return FSP_SUCCESS; + } +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p29t.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p29t.c new file mode 100644 index 000000000..e9c13ccb0 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p29t.c @@ -0,0 +1,24 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes128GcmEncryptUpdateTransitionSub (void) +{ + WR1_PROG(REG_D0H, 0x08000045U); + WR1_PROG(REG_94H, 0x0000b420U); + WR1_PROG(REG_94H, 0x00000010U); + WR1_PROG(REG_9CH, 0x81840001U); + WR1_PROG(REG_00H, 0x00490011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D4H, 0x00000020U); + WR1_PROG(REG_D0H, 0x07008c04U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p29u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p29u.c new file mode 100644 index 000000000..7519fbc5e --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p29u.c @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes128GcmEncryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0xc823248aU, 0xadb052b2U, 0x3b276407U, 0xce9c5fbfU); + + WR1_PROG(REG_14H, 0x00020061U); + WR1_PROG(REG_D4H, 0x00000020U); + WR1_PROG(REG_D0H, 0x20008d06U); + WR1_PROG(REG_08H, 0x000c1000U); + + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_Text[0]); + for (iLoop = 4; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_Text[iLoop]); + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_Text[iLoop - 4]); + + HW_SCE_p_func206(); + + HW_SCE_p_func101(0xe741318cU, 0x301998bfU, 0x5e3e5769U, 0x5f68ac70U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p32a.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p32a.c new file mode 100644 index 000000000..9433c8682 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p32a.c @@ -0,0 +1,27 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes128GcmDecryptUpdateAADSub (const uint32_t InData_DataA[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_14H, 0x00020061U); + WR1_PROG(REG_D4H, 0x00008000U); + WR1_PROG(REG_D0H, 0x0e128456U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_DataA[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func205_r1(); + + HW_SCE_p_func101(0x31ef703fU, 0x4562e5c1U, 0x5a02294fU, 0x2ebf61efU); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p32f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p32f.c new file mode 100644 index 000000000..613b1e006 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p32f.c @@ -0,0 +1,194 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128GcmDecryptFinalSub (const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_DataALen[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_14H, 0x000001c7U); + WR1_PROG(REG_9CH, 0x80020040U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_TextLen[0]); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_TextLen[1]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_94H, 0x0000b400U); + WR1_PROG(REG_94H, 0x0000007FU); + WR1_PROG(REG_94H, 0x0000b420U); + WR1_PROG(REG_94H, 0xFFFFFF00U); + WR1_PROG(REG_94H, 0x0c002823U); + WR1_PROG(REG_94H, 0x04a02802U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x800100a0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_DataTLen[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_94H, 0x380088a0U); + WR1_PROG(REG_94H, 0x00000000U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + WR1_PROG(REG_94H, 0x0000b420U); + WR1_PROG(REG_94H, 0x00000010U); + WR1_PROG(REG_94H, 0x34202825U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + HW_SCE_p_func100(0x27de1cffU, 0xe5e8df64U, 0xedcd99a0U, 0x034a46f3U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0x094b802eU, 0x846e3f9cU, 0xe7445d0eU, 0x1f89b48fU); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_94H, 0x00003403U); + WR1_PROG(REG_94H, 0x00036800U); + + WR1_PROG(REG_94H, 0x08008c00U); + WR1_PROG(REG_94H, 0x0000000fU); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00A60000U); + + HW_SCE_p_func100(0xcc50a9e5U, 0xe9cea62eU, 0xb52f25f5U, 0xbb2cfc33U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func100(0x0e276017U, 0xfe30a68aU, 0x11096f8cU, 0x366678c4U); + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D4H, 0x00008020U); + WR1_PROG(REG_D0H, 0x20008d05U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_Text[0]); + + WR1_PROG(REG_94H, 0x00000821U); + WR1_PROG(REG_9CH, 0x80840001U); + WR1_PROG(REG_00H, 0x03410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_94H, 0x00000884U); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_94H, 0x3c002820U); + WR1_PROG(REG_94H, 0x12003c81U); + WR1_PROG(REG_94H, 0x00002c20U); + } + + WR1_PROG(REG_94H, 0x00000821U); + WR1_PROG(REG_9CH, 0x81840001U); + + WR1_PROG(REG_08H, 0x00005012U); + WAIT_STS(REG_08H, 30, 1); + RD1_ADDR(REG_2CH, &OutData_Text[0]); + WAIT_STS(REG_08H, 30, 1); + RD1_ADDR(REG_2CH, &OutData_Text[1]); + WAIT_STS(REG_08H, 30, 1); + RD1_ADDR(REG_2CH, &OutData_Text[2]); + WAIT_STS(REG_08H, 30, 1); + RD1_ADDR(REG_2CH, &OutData_Text[3]); + + HW_SCE_p_func101(0x4b2001d1U, 0xeb1423c4U, 0xc3fc5ff5U, 0x0909c9ecU); + } + + WR1_PROG(REG_14H, 0x000001c1U); + WR1_PROG(REG_D4H, 0x00008000U); + WR1_PROG(REG_D0H, 0x0e128455U); + WAIT_STS(REG_14H, 31, 1); + WR2_ADDR(REG_2CH, &InData_DataALen[0]); + + WR1_PROG(REG_9CH, 0x81020040U); + WR1_PROG(REG_00H, 0x00490009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_D0H, 0x08000045U); + WR1_PROG(REG_94H, 0x0000b420U); + WR1_PROG(REG_94H, 0x00000010U); + WR1_PROG(REG_9CH, 0x81840001U); + WR1_PROG(REG_00H, 0x00490011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c100104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_D4H, 0x00000020U); + WR1_PROG(REG_D0H, 0x07008d05U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_94H, 0x00000821U); + WR1_PROG(REG_9CH, 0x80840001U); + WR1_PROG(REG_00H, 0x03410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_94H, 0x00000884U); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_94H, 0x3c002825U); + WR1_PROG(REG_94H, 0x12003c81U); + WR1_PROG(REG_94H, 0x00002c20U); + } + + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D0H, 0x08000055U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_DataT[0]); + + WR1_PROG(REG_D0H, 0x9c100005U); + WR1_PROG(REG_94H, 0x00000821U); + WR1_PROG(REG_9CH, 0x81840001U); + WR1_PROG(REG_00H, 0x00490011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0xc0ff796aU, 0xc4051af6U, 0x2eb84008U, 0x8fd50da4U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0x8c6ea52fU, 0x8ad24963U, 0x626bddb3U, 0xb92fe7b0U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + else + { + HW_SCE_p_func102(0xcd6451f1U, 0x0c2a34b4U, 0x6bf17242U, 0xe73b701eU); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_SUCCESS; + } + } +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p32i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p32i.c new file mode 100644 index 000000000..221f29920 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p32i.c @@ -0,0 +1,160 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128GcmDecryptInitSub (const uint32_t InData_KeyMode[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_6CH, 0x00000017U) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_70H, 0x00320001U); + WR1_PROG(REG_4CH, 0x00000000U); + + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x80010000U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_KeyMode[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_94H, 0x38000c00U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + HW_SCE_p_func100(0x7d1f864dU, 0xe7d24222U, 0x0bf6f030U, 0xcab1f68fU); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + if (CHCK_STS(REG_40H, 22, 1)) + { + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x800100c0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_KeyIndex[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000032U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0xd63ad49dU, 0x2154a066U, 0x2b1d8c94U, 0x2d2c8ac8U); + HW_SCE_p_func043(); + + WR1_PROG(REG_94H, 0x0000b4c0U); + WR1_PROG(REG_94H, 0x00000005U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000032U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0x25f46300U, 0xea684069U, 0x0c44336dU, 0xc4b3cb88U); + HW_SCE_p_func044(); + + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0xf7009d05U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_KeyIndex[1]); + + WR1_PROG(REG_B0H, 0x00000401U); + WR1_PROG(REG_00H, 0x00c10009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_B0H, 0x00000402U); + WR1_PROG(REG_00H, 0x00c10009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x07008d05U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_KeyIndex[5]); + + WR1_PROG(REG_D0H, 0x9c100005U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func101(0x9e797ecaU, 0x22391318U, 0x957c5739U, 0x32e2ff7dU); + } + else + { + WR1_PROG(REG_14H, 0x000003c5U); + WR1_PROG(REG_B0H, 0x00000401U); + WAIT_STS(REG_14H, 31, 1); + WR2_ADDR(REG_2CH, &InData_Key[0]); + WR1_PROG(REG_B0H, 0x00000402U); + WAIT_STS(REG_14H, 31, 1); + WR2_ADDR(REG_2CH, &InData_Key[2]); + + HW_SCE_p_func101(0xd35c160dU, 0x394ccf1cU, 0x98d99d8cU, 0x98767837U); + } + + HW_SCE_p_func100(0x2fd0f192U, 0xa3a9e912U, 0x4f422c92U, 0x9ad84a07U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0x1dd3150fU, 0xff34644dU, 0x0a5d8ae8U, 0xbc549f34U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0xac920c8aU, 0x79f3e7dfU, 0xbdf3f7c6U, 0x80a991a3U); + WR1_PROG(REG_D0H, 0x08000085U); + WR1_PROG(REG_B0H, 0x00000801U); + WR1_PROG(REG_00H, 0x00430009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_B0H, 0x00000802U); + WR1_PROG(REG_00H, 0x00430009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0x6812549aU, 0xc5550413U, 0xe3d665a9U, 0xea253d86U); + WR1_PROG(REG_14H, 0x000003c7U); + WR1_PROG(REG_94H, 0x0000b420U); + WR1_PROG(REG_94H, 0x00000010U); + WR1_PROG(REG_9CH, 0x80840001U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_IV[0]); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_IV[1]); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_IV[2]); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_IV[3]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x08000054U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0a0000a4U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + HW_SCE_p_func101(0xa44f29b4U, 0x60ed07d8U, 0xc5d59b93U, 0x611e51efU); + + return FSP_SUCCESS; + } +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p32t.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p32t.c new file mode 100644 index 000000000..72fad8cfc --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p32t.c @@ -0,0 +1,24 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes128GcmDecryptUpdateTransitionSub (void) +{ + WR1_PROG(REG_D0H, 0x08000045U); + WR1_PROG(REG_94H, 0x0000b420U); + WR1_PROG(REG_94H, 0x00000010U); + WR1_PROG(REG_9CH, 0x81840001U); + WR1_PROG(REG_00H, 0x00490011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D4H, 0x00000020U); + WR1_PROG(REG_D0H, 0x07008c04U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p32u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p32u.c new file mode 100644 index 000000000..7ec1357ff --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p32u.c @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes128GcmDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0xb68f91c7U, 0x7c632c14U, 0xee796680U, 0xe5f582d0U); + + WR1_PROG(REG_14H, 0x00020061U); + WR1_PROG(REG_D4H, 0x00008020U); + WR1_PROG(REG_D0H, 0x20008d06U); + WR1_PROG(REG_08H, 0x000c1000U); + + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_Text[0]); + for (iLoop = 4; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_Text[iLoop]); + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_Text[iLoop - 4]); + + HW_SCE_p_func206(); + + HW_SCE_p_func101(0x3aa84aa5U, 0x3252be50U, 0xfe8a3232U, 0xca833f57U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p34a.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p34a.c new file mode 100644 index 000000000..8eb1c7af3 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p34a.c @@ -0,0 +1,27 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes256GcmEncryptUpdateAADSub (const uint32_t InData_DataA[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_14H, 0x00020061U); + WR1_PROG(REG_D4H, 0x00008000U); + WR1_PROG(REG_D0H, 0x0e128456U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_DataA[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func205_r1(); + + HW_SCE_p_func101(0x744d192aU, 0xc2cc649eU, 0x4da8c0acU, 0x379102c4U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p34f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p34f.c new file mode 100644 index 000000000..4c95da755 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p34f.c @@ -0,0 +1,150 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256GcmEncryptFinalSub (const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_DataALen[], + uint32_t OutData_Text[], + uint32_t OutData_DataT[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_14H, 0x000001c7U); + WR1_PROG(REG_9CH, 0x80020040U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_TextLen[0]); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_TextLen[1]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_94H, 0x0000b400U); + WR1_PROG(REG_94H, 0x0000007FU); + WR1_PROG(REG_94H, 0x0000b420U); + WR1_PROG(REG_94H, 0xFFFFFF00U); + WR1_PROG(REG_94H, 0x0c002823U); + WR1_PROG(REG_94H, 0x04a02802U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + HW_SCE_p_func100(0x14bbdd67U, 0x7839bf3bU, 0x53eb419fU, 0x2e398e35U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0xe3fc264bU, 0xfdea1122U, 0x02402b59U, 0x6fd16b08U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_94H, 0x00003403U); + WR1_PROG(REG_94H, 0x00036800U); + + WR1_PROG(REG_94H, 0x08008c00U); + WR1_PROG(REG_94H, 0x0000000fU); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00A60000U); + + HW_SCE_p_func100(0x9cb6ff8eU, 0x622d029eU, 0x9d8413b4U, 0x1a6bb5efU); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func100(0xb8bffe43U, 0x2ae86e82U, 0x9f854f58U, 0x81c72fa6U); + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D4H, 0x40000020U); + WR1_PROG(REG_D0H, 0x07008d05U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_Text[0]); + + WR1_PROG(REG_94H, 0x00000821U); + WR1_PROG(REG_9CH, 0x80840001U); + WR1_PROG(REG_00H, 0x03410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_94H, 0x00000884U); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_94H, 0x3c002820U); + WR1_PROG(REG_94H, 0x12003c81U); + WR1_PROG(REG_94H, 0x00002c20U); + } + + WR1_PROG(REG_D4H, 0x00008000U); + WR1_PROG(REG_D0H, 0x0e128455U); + WR1_PROG(REG_94H, 0x00000821U); + WR1_PROG(REG_9CH, 0x81840001U); + WR1_PROG(REG_00H, 0x00490011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WAIT_STS(REG_C8H, 6, 0); + WR1_PROG(REG_40H, 0x00000400U); + WR1_PROG(REG_40H, 0x00000500U); + + WR1_PROG(REG_9CH, 0x81840001U); + WR1_PROG(REG_08H, 0x00005012U); + WAIT_STS(REG_08H, 30, 1); + RD1_ADDR(REG_2CH, &OutData_Text[0]); + WAIT_STS(REG_08H, 30, 1); + RD1_ADDR(REG_2CH, &OutData_Text[1]); + WAIT_STS(REG_08H, 30, 1); + RD1_ADDR(REG_2CH, &OutData_Text[2]); + WAIT_STS(REG_08H, 30, 1); + RD1_ADDR(REG_2CH, &OutData_Text[3]); + + HW_SCE_p_func101(0x2baa7ddeU, 0xb760ef47U, 0xe5376311U, 0x32ea06c6U); + } + + HW_SCE_p_func100(0xf78fa061U, 0x612507b3U, 0x0fb55e68U, 0xdc0602f5U); + WR1_PROG(REG_14H, 0x000001c1U); + WR1_PROG(REG_D4H, 0x00008000U); + WR1_PROG(REG_D0H, 0x0e128455U); + WAIT_STS(REG_14H, 31, 1); + WR2_ADDR(REG_2CH, &InData_DataALen[0]); + + WR1_PROG(REG_9CH, 0x81020040U); + WR1_PROG(REG_00H, 0x00490009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_D0H, 0x08000045U); + WR1_PROG(REG_94H, 0x0000b420U); + WR1_PROG(REG_94H, 0x00000010U); + WR1_PROG(REG_9CH, 0x81840001U); + WR1_PROG(REG_00H, 0x00490011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c100104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_D4H, 0x40000020U); + WR1_PROG(REG_D0H, 0x07008d05U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_08H, 0x00001012U); + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_DataT[0]); + + HW_SCE_p_func102(0xa636f20dU, 0xf821e6bcU, 0xa5693fd9U, 0xdafcce12U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_SUCCESS; + } +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p34i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p34i.c new file mode 100644 index 000000000..49f36bbf2 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p34i.c @@ -0,0 +1,159 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256GcmEncryptInitSub (const uint32_t InData_KeyMode[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_6CH, 0x00000017U) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_70H, 0x00340001U); + WR1_PROG(REG_4CH, 0x00000000U); + + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x80010000U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_KeyMode[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_94H, 0x38000c00U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + HW_SCE_p_func100(0x4fd5ae69U, 0x5f6ec402U, 0xfe81511fU, 0xdf952ac1U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + if (CHCK_STS(REG_40H, 22, 1)) + { + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x800100c0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_KeyIndex[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000034U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0xe3cd825eU, 0xcc330afcU, 0x983f21f0U, 0x8c34bf93U); + HW_SCE_p_func043(); + + WR1_PROG(REG_94H, 0x0000b4c0U); + WR1_PROG(REG_94H, 0x00000007U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000034U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0x3a6f81e7U, 0xf19e583bU, 0x4f812070U, 0xdf5c52a9U); + HW_SCE_p_func044(); + + WR1_PROG(REG_14H, 0x000007c1U); + WR1_PROG(REG_D4H, 0x40000100U); + WR1_PROG(REG_D0H, 0xf7009d07U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_KeyIndex[1]); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_KeyIndex[5]); + + WR1_PROG(REG_B0H, 0x00001404U); + WR1_PROG(REG_00H, 0x00c10021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x07008d05U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_KeyIndex[9]); + + WR1_PROG(REG_D0H, 0x9c100005U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func101(0x5792d6b5U, 0x2265e7a0U, 0x0c80f00aU, 0x9a852ed3U); + } + else + { + WR1_PROG(REG_14H, 0x000007c5U); + WR1_PROG(REG_B0H, 0x00001404U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_Key[0]); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_Key[4]); + + HW_SCE_p_func101(0xcea5c980U, 0x22a95d55U, 0x7e2ae13aU, 0xe200293fU); + } + + HW_SCE_p_func100(0x6fdfa963U, 0x32c8ec3aU, 0xf6c71582U, 0x0bfc91a4U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0x02623e4eU, 0x6d7ca91cU, 0x7dac2f61U, 0xbc8d8d9aU); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0x8e5ff2b1U, 0x58a95174U, 0x1d617956U, 0xe9497e37U); + WR1_PROG(REG_D0H, 0x08000085U); + WR1_PROG(REG_B0H, 0x00001804U); + WR1_PROG(REG_00H, 0x00430011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0x1d25046bU, 0x4c9a6a0eU, 0x2f547da1U, 0x3a0a7632U); + WR1_PROG(REG_D0H, 0x08000095U); + WR1_PROG(REG_00H, 0x00430011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0x85945b56U, 0xfc624298U, 0xbf678b5dU, 0xfba9666dU); + WR1_PROG(REG_14H, 0x000003c7U); + WR1_PROG(REG_94H, 0x0000b420U); + WR1_PROG(REG_94H, 0x00000010U); + WR1_PROG(REG_9CH, 0x80840001U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_IV[0]); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_IV[1]); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_IV[2]); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_IV[3]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x08000054U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x0a0080a4U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + HW_SCE_p_func101(0x7fbcd911U, 0x6f168d22U, 0xbe14170cU, 0x9e02c39aU); + + return FSP_SUCCESS; + } +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p34t.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p34t.c new file mode 100644 index 000000000..c802458fc --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p34t.c @@ -0,0 +1,24 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes256GcmEncryptUpdateTransitionSub (void) +{ + WR1_PROG(REG_D0H, 0x08000045U); + WR1_PROG(REG_94H, 0x0000b420U); + WR1_PROG(REG_94H, 0x00000010U); + WR1_PROG(REG_9CH, 0x81840001U); + WR1_PROG(REG_00H, 0x00490011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D4H, 0x40000020U); + WR1_PROG(REG_D0H, 0x07008c04U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p34u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p34u.c new file mode 100644 index 000000000..cb2806826 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p34u.c @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes256GcmEncryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0x7f063147U, 0x75d56eefU, 0x03e15b02U, 0x2d561473U); + + WR1_PROG(REG_14H, 0x00020061U); + WR1_PROG(REG_D4H, 0x40000020U); + WR1_PROG(REG_D0H, 0x20008d06U); + WR1_PROG(REG_08H, 0x000c1000U); + + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_Text[0]); + for (iLoop = 4; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_Text[iLoop]); + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_Text[iLoop - 4]); + + HW_SCE_p_func206(); + + HW_SCE_p_func101(0x2968ebfaU, 0xeb3c47e6U, 0x099fef85U, 0x05da0d73U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p36a.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p36a.c new file mode 100644 index 000000000..7a63b23f6 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p36a.c @@ -0,0 +1,27 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes256GcmDecryptUpdateAADSub (const uint32_t InData_DataA[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_14H, 0x00020061U); + WR1_PROG(REG_D4H, 0x00008000U); + WR1_PROG(REG_D0H, 0x0e128456U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_DataA[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func205_r1(); + + HW_SCE_p_func101(0xb3a96391U, 0xd8c1af1cU, 0x78e1b419U, 0xcbeb9ff5U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p36f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p36f.c new file mode 100644 index 000000000..d3064a379 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p36f.c @@ -0,0 +1,194 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256GcmDecryptFinalSub (const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_DataALen[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_14H, 0x000001c7U); + WR1_PROG(REG_9CH, 0x80020040U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_TextLen[0]); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_TextLen[1]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_94H, 0x0000b400U); + WR1_PROG(REG_94H, 0x0000007FU); + WR1_PROG(REG_94H, 0x0000b420U); + WR1_PROG(REG_94H, 0xFFFFFF00U); + WR1_PROG(REG_94H, 0x0c002823U); + WR1_PROG(REG_94H, 0x04a02802U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x800100a0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_DataTLen[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_94H, 0x380088a0U); + WR1_PROG(REG_94H, 0x00000000U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + WR1_PROG(REG_94H, 0x0000b420U); + WR1_PROG(REG_94H, 0x00000010U); + WR1_PROG(REG_94H, 0x34202825U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + HW_SCE_p_func100(0x0a7bbb4cU, 0x9b4b282dU, 0xe4bfde31U, 0x99317942U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0xd6e0c9b2U, 0xee7ec6fbU, 0x5b284e3cU, 0x5c29f785U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_94H, 0x00003403U); + WR1_PROG(REG_94H, 0x00036800U); + + WR1_PROG(REG_94H, 0x08008c00U); + WR1_PROG(REG_94H, 0x0000000fU); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00A60000U); + + HW_SCE_p_func100(0x708ff5e5U, 0x28b76394U, 0x6159a5e9U, 0x93890982U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func100(0x36ac832aU, 0x172664dbU, 0x03d685a0U, 0xd41de23bU); + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D4H, 0x40008020U); + WR1_PROG(REG_D0H, 0x20008d05U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_Text[0]); + + WR1_PROG(REG_94H, 0x00000821U); + WR1_PROG(REG_9CH, 0x80840001U); + WR1_PROG(REG_00H, 0x03410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_94H, 0x00000884U); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_94H, 0x3c002820U); + WR1_PROG(REG_94H, 0x12003c81U); + WR1_PROG(REG_94H, 0x00002c20U); + } + + WR1_PROG(REG_94H, 0x00000821U); + WR1_PROG(REG_9CH, 0x81840001U); + + WR1_PROG(REG_08H, 0x00005012U); + WAIT_STS(REG_08H, 30, 1); + RD1_ADDR(REG_2CH, &OutData_Text[0]); + WAIT_STS(REG_08H, 30, 1); + RD1_ADDR(REG_2CH, &OutData_Text[1]); + WAIT_STS(REG_08H, 30, 1); + RD1_ADDR(REG_2CH, &OutData_Text[2]); + WAIT_STS(REG_08H, 30, 1); + RD1_ADDR(REG_2CH, &OutData_Text[3]); + + HW_SCE_p_func101(0x7dfd4f3fU, 0x50e26958U, 0x3c632e22U, 0xe04fddb2U); + } + + WR1_PROG(REG_14H, 0x000001c1U); + WR1_PROG(REG_D4H, 0x00008000U); + WR1_PROG(REG_D0H, 0x0e128455U); + WAIT_STS(REG_14H, 31, 1); + WR2_ADDR(REG_2CH, &InData_DataALen[0]); + + WR1_PROG(REG_9CH, 0x81020040U); + WR1_PROG(REG_00H, 0x00490009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_D0H, 0x08000045U); + WR1_PROG(REG_94H, 0x0000b420U); + WR1_PROG(REG_94H, 0x00000010U); + WR1_PROG(REG_9CH, 0x81840001U); + WR1_PROG(REG_00H, 0x00490011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c100104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_D4H, 0x40000020U); + WR1_PROG(REG_D0H, 0x07008d05U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_94H, 0x00000821U); + WR1_PROG(REG_9CH, 0x80840001U); + WR1_PROG(REG_00H, 0x03410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_94H, 0x00000884U); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_94H, 0x3c002825U); + WR1_PROG(REG_94H, 0x12003c81U); + WR1_PROG(REG_94H, 0x00002c20U); + } + + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D0H, 0x08000055U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_DataT[0]); + + WR1_PROG(REG_D0H, 0x9c100005U); + WR1_PROG(REG_94H, 0x00000821U); + WR1_PROG(REG_9CH, 0x81840001U); + WR1_PROG(REG_00H, 0x00490011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0x0e9b1cadU, 0xe6703475U, 0x79886489U, 0xacbd8f93U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0x9b2fa038U, 0xb7a2f88dU, 0x19cbcd85U, 0x9587dcdcU); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + else + { + HW_SCE_p_func102(0x3c9f5a65U, 0x8b1fc43aU, 0x8cf39b33U, 0x043abf7fU); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_SUCCESS; + } + } +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p36i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p36i.c new file mode 100644 index 000000000..889119d8c --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p36i.c @@ -0,0 +1,159 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256GcmDecryptInitSub (const uint32_t InData_KeyMode[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_6CH, 0x00000017U) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_70H, 0x00360001U); + WR1_PROG(REG_4CH, 0x00000000U); + + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x80010000U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_KeyMode[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_94H, 0x38000c00U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + HW_SCE_p_func100(0x130b8d7dU, 0xd1e377f3U, 0x591805f7U, 0xca753078U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + if (CHCK_STS(REG_40H, 22, 1)) + { + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x800100c0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_KeyIndex[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000036U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0x2c9886e8U, 0xa1a90c29U, 0xbf46ad2fU, 0x24785387U); + HW_SCE_p_func043(); + + WR1_PROG(REG_94H, 0x0000b4c0U); + WR1_PROG(REG_94H, 0x00000007U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000036U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0x90c84b07U, 0xea96cf39U, 0x541f1840U, 0xa59e19e7U); + HW_SCE_p_func044(); + + WR1_PROG(REG_14H, 0x000007c1U); + WR1_PROG(REG_D4H, 0x40000100U); + WR1_PROG(REG_D0H, 0xf7009d07U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_KeyIndex[1]); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_KeyIndex[5]); + + WR1_PROG(REG_B0H, 0x00001404U); + WR1_PROG(REG_00H, 0x00c10021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x07008d05U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_KeyIndex[9]); + + WR1_PROG(REG_D0H, 0x9c100005U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func101(0x03aeedf8U, 0xad2a9905U, 0xc73b742cU, 0x51e4401cU); + } + else + { + WR1_PROG(REG_14H, 0x000007c5U); + WR1_PROG(REG_B0H, 0x00001404U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_Key[0]); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_Key[4]); + + HW_SCE_p_func101(0x11120467U, 0xd72b5073U, 0x2cd91955U, 0x86575729U); + } + + HW_SCE_p_func100(0xdc40e2adU, 0x7bcbc57aU, 0x87c3e35fU, 0xb907a52eU); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0x1a889988U, 0x7eb3839bU, 0xa42cca2eU, 0x84ec8e22U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0x08659bbfU, 0xbd50c9beU, 0x73795e49U, 0xe0a60ad8U); + WR1_PROG(REG_D0H, 0x08000085U); + WR1_PROG(REG_B0H, 0x00001804U); + WR1_PROG(REG_00H, 0x00430011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0x7217cfebU, 0xbd3e925fU, 0x864654c8U, 0x3793af01U); + WR1_PROG(REG_D0H, 0x08000095U); + WR1_PROG(REG_00H, 0x00430011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0xad801bfeU, 0x5c7d1d96U, 0x9686cc8bU, 0x0798d72dU); + WR1_PROG(REG_14H, 0x000003c7U); + WR1_PROG(REG_94H, 0x0000b420U); + WR1_PROG(REG_94H, 0x00000010U); + WR1_PROG(REG_9CH, 0x80840001U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_IV[0]); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_IV[1]); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_IV[2]); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_IV[3]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x08000054U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x0a0080a4U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + HW_SCE_p_func101(0x09223120U, 0xb2dd6770U, 0x6cbbae50U, 0x18f26dbcU); + + return FSP_SUCCESS; + } +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p36t.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p36t.c new file mode 100644 index 000000000..2bfb9d9da --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p36t.c @@ -0,0 +1,24 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes256GcmDecryptUpdateTransitionSub (void) +{ + WR1_PROG(REG_D0H, 0x08000045U); + WR1_PROG(REG_94H, 0x0000b420U); + WR1_PROG(REG_94H, 0x00000010U); + WR1_PROG(REG_9CH, 0x81840001U); + WR1_PROG(REG_00H, 0x00490011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D4H, 0x40000020U); + WR1_PROG(REG_D0H, 0x07008c04U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p36u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p36u.c new file mode 100644 index 000000000..a21280c63 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p36u.c @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes256GcmDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0xabe58f91U, 0xd18d43c2U, 0xcb4b0c75U, 0x542e4923U); + + WR1_PROG(REG_14H, 0x00020061U); + WR1_PROG(REG_D4H, 0x40008020U); + WR1_PROG(REG_D0H, 0x20008d06U); + WR1_PROG(REG_08H, 0x000c1000U); + + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_Text[0]); + for (iLoop = 4; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_Text[iLoop]); + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_Text[iLoop - 4]); + + HW_SCE_p_func206(); + + HW_SCE_p_func101(0x1a7f937bU, 0xb0ac1460U, 0xe768f927U, 0x335c2dd4U); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p40.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p40.c new file mode 100644 index 000000000..f8e89f9b9 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p40.c @@ -0,0 +1,247 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_LoadHukSub (const uint32_t InData_LC[]) +{ + if (RD1_MASK(REG_6CH, 0x00000017U) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_70H, 0x00400001U); + WR1_PROG(REG_4CH, 0x00000000U); + + HW_SCE_p_func048(InData_LC); + + WR1_PROG(REG_94H, 0x0000b420U); + WR1_PROG(REG_94H, 0x00000009U); + WR1_PROG(REG_94H, 0x34202801U); + WR1_PROG(REG_94H, 0x20003401U); + + WR1_PROG(REG_94H, 0x00007c00U); + WR1_PROG(REG_40H, 0x00602000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (InData_LC[0] == 0x00000000U) + { + WR1_PROG(REG_40H, 0x00b00000U); + + HW_SCE_p_func101(0x399b3355U, 0x69a5994eU, 0x6f4f82beU, 0x7cdb80bbU); + } + else if (InData_LC[0] == 0x00000001U) + { + WR1_PROG(REG_40H, 0x00b10000U); + + HW_SCE_p_func101(0x06014c3aU, 0x828be8fbU, 0xf23cea72U, 0xdca0f318U); + } + else if (InData_LC[0] == 0x00000002U) + { + WR1_PROG(REG_40H, 0x00b20000U); + + HW_SCE_p_func101(0x4a0b603eU, 0x2caa0248U, 0x84f54389U, 0xfb2d9d8bU); + } + else if (InData_LC[0] == 0x00000003U) + { + WR1_PROG(REG_40H, 0x00b30000U); + + HW_SCE_p_func101(0xf65e1250U, 0x698a4573U, 0x4d70cd6dU, 0xf1df75c0U); + } + else if (InData_LC[0] == 0x00000004U) + { + WR1_PROG(REG_40H, 0x00b40000U); + + HW_SCE_p_func101(0x73b39312U, 0x9a94d935U, 0x61c3ec9cU, 0x25bbbeb0U); + } + else if (InData_LC[0] == 0x00000005U) + { + WR1_PROG(REG_40H, 0x00b50000U); + + HW_SCE_p_func101(0x26f0499bU, 0x20fd5bdcU, 0x4f9bb5b6U, 0xfbffeb9bU); + } + else if (InData_LC[0] == 0x00000006U) + { + WR1_PROG(REG_40H, 0x00b60000U); + + HW_SCE_p_func101(0x155ad156U, 0xb6ce6493U, 0x20cd7b9fU, 0xeba67dacU); + } + else if (InData_LC[0] == 0x00000007U) + { + WR1_PROG(REG_40H, 0x00b70000U); + + HW_SCE_p_func101(0xc35ac31dU, 0x5d0eddebU, 0x4ea7686eU, 0xac86af8dU); + } + else if (InData_LC[0] == 0x00000008U) + { + WR1_PROG(REG_40H, 0x00b80000U); + + HW_SCE_p_func101(0x859a7728U, 0x4c61f1e8U, 0xa9692a5aU, 0x97a77a14U); + } + else + { + WR1_PROG(REG_94H, 0x38000c00U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00A60000U); + + HW_SCE_p_func101(0x8f4361a7U, 0x4f55fa93U, 0x6c256098U, 0x91f05044U); + } + + HW_SCE_p_func100(0x2a3cbb58U, 0x75f9c1abU, 0x7d6552eaU, 0xd9a42065U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0x2be01237U, 0x26d430f9U, 0x5e052767U, 0x461d8d2cU); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_14H, 0x000003a1U); + WR1_PROG(REG_D0H, 0x0a0700f5U); + WAIT_STS(REG_14H, 31, 1); + WR4_PROG(REG_2CH, change_endian_long(0xfd32ed95U), change_endian_long(0xc0adaf20U), + change_endian_long(0x61f7d366U), change_endian_long(0x1a13aa80U)); + + HW_SCE_p_func100(0x75d292f4U, 0x33520d7cU, 0xa3e35cf1U, 0xd501a8c9U); + WR1_PROG(REG_D0H, 0x4a470044U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_D0H, 0x0e470484U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x015cfefdU)); + + HW_SCE_p_func100(0xf801104cU, 0x3066ec10U, 0x133ee623U, 0xd724d94cU); + WR1_PROG(REG_D0H, 0x4a470044U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_D0H, 0x0e470494U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x025cfefdU)); + + WR1_PROG(REG_14H, 0x000003a1U); + WR1_PROG(REG_D0H, 0x0a0700f5U); + WAIT_STS(REG_14H, 31, 1); + WR4_PROG(REG_2CH, change_endian_long(0xb6803eb9U), change_endian_long(0x31b4dd4aU), + change_endian_long(0xfc5cdeaeU), change_endian_long(0xdb3d1dfdU)); + + HW_SCE_p_func100(0x7947ad55U, 0x9c701c5fU, 0x4341e36cU, 0x99b8d05dU); + WR1_PROG(REG_D4H, 0x40000100U); + WR1_PROG(REG_D0H, 0xf7009d05U); + WR1_PROG(REG_D8H, 0x20000000U); + WR1_PROG(REG_00H, 0x00480011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0xf7008d05U); + WR1_PROG(REG_D8H, 0x20000010U); + WR1_PROG(REG_00H, 0x00480011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_94H, 0x00000821U); + WR1_PROG(REG_9CH, 0x80880001U); + WR1_PROG(REG_00H, 0x03410021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x07008d05U); + WR1_PROG(REG_D8H, 0x20000020U); + WR1_PROG(REG_00H, 0x00480011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_D0H, 0x8c100005U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_D0H, 0x08000085U); + WR1_PROG(REG_9CH, 0x81880001U); + WR1_PROG(REG_00H, 0x00490011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0x1a4a6a5dU, 0x9f3c2a50U, 0xa5e46326U, 0x5bebb764U); + WR1_PROG(REG_D0H, 0x08000095U); + WR1_PROG(REG_00H, 0x00490011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_A0H, 0x00010000U); + + WR1_PROG(REG_B0H, 0x00000492U); + WR1_PROG(REG_00H, 0x00c00005U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_9CH, 0x81010000U); + WR1_PROG(REG_00H, 0x00c90005U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_14H, 0x000002a1U); + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x4a008044U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x0e008104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x01d65991U)); + + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x0e008104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x02d65991U)); + + WR1_PROG(REG_B0H, 0x00001498U); + WR1_PROG(REG_00H, 0x00c10021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0x215a41c2U, 0xd0d54e4bU, 0x73da3375U, 0x7c1ce3efU); + WR1_PROG(REG_D0H, 0x4a470044U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_D0H, 0x0e4704c4U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x0152db38U)); + + WR1_PROG(REG_D0H, 0x4a040044U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_D0H, 0x0e040504U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x010daaebU)); + + WR1_PROG(REG_B0H, 0x00000493U); + WR1_PROG(REG_00H, 0x00c10009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_B0H, 0x00000494U); + WR1_PROG(REG_00H, 0x00c10009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_78H, 0x00000202U); + + HW_SCE_p_func102(0xb5de2ba1U, 0x85465aa0U, 0x30d01d96U, 0xd9d05b11U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_SUCCESS; + } +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p47f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p47f.c new file mode 100644 index 000000000..3645850b2 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p47f.c @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub (void) +{ + if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000000U) + { + HW_SCE_p_func101(0xa9559b66U, 0x156b47bcU, 0xc0b4e84cU, 0xbcd053a0U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000001U) + { + HW_SCE_p_func101(0xdffb3428U, 0x817d47aaU, 0xc4234844U, 0x1a7eab9cU); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000002U) + { + HW_SCE_p_func101(0x9577d73cU, 0xa18dd8cbU, 0xf769491aU, 0x007a991eU); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000003U) + { + HW_SCE_p_func101(0xae8d48cfU, 0xa816d95bU, 0x7b55232fU, 0xd32f64b0U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000004U) + { + HW_SCE_p_func101(0xeca9b298U, 0x24cee46aU, 0x9e640167U, 0xb0df14f6U); + } + + HW_SCE_p_func102(0x2ed698bcU, 0x3b2e1938U, 0x41ea3d5aU, 0x86cac3a4U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_SUCCESS; +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p47i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p47i.c new file mode 100644 index 000000000..789629ffe --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p47i.c @@ -0,0 +1,193 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_6CH, 0x00000017U) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_70H, 0x00470001U); + WR1_PROG(REG_4CH, 0x00000000U); + + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x80010080U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_Cmd[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_94H, 0x3000a880U); + WR1_PROG(REG_94H, 0x00000004U); + WR1_PROG(REG_94H, 0x00010020U); + WR1_PROG(REG_94H, 0x0000b480U); + WR1_PROG(REG_94H, 0x00000004U); + WR1_PROG(REG_94H, 0x00000080U); + + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x80010000U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_KeyMode[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_94H, 0x38000c00U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + HW_SCE_p_func100(0x5bb01efeU, 0xff57d48eU, 0x92ae6b88U, 0x4feeb7efU); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x800100c0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_KeyIndex[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000047U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0xf8a8800fU, 0xf20c41c6U, 0xc3dbd55eU, 0x3bf67e8eU); + HW_SCE_p_func043(); + + WR1_PROG(REG_94H, 0x0000b4c0U); + WR1_PROG(REG_94H, 0x00000005U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000047U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0x906b9351U, 0x95a3f705U, 0xf7893af5U, 0x35fb3834U); + HW_SCE_p_func044(); + + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0xf7009d05U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_KeyIndex[1]); + + WR1_PROG(REG_B0H, 0x00000401U); + WR1_PROG(REG_00H, 0x00c10009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_B0H, 0x00000402U); + WR1_PROG(REG_00H, 0x00c10009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x07008d05U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_KeyIndex[5]); + + WR1_PROG(REG_D0H, 0x9c100005U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func101(0x262e52a0U, 0x08c7e57eU, 0xf5739e53U, 0x0b4b14f6U); + } + else + { + WR1_PROG(REG_14H, 0x000003c5U); + WR1_PROG(REG_B0H, 0x00000401U); + WAIT_STS(REG_14H, 31, 1); + WR2_ADDR(REG_2CH, &InData_Key[0]); + WR1_PROG(REG_B0H, 0x00000402U); + WAIT_STS(REG_14H, 31, 1); + WR2_ADDR(REG_2CH, &InData_Key[2]); + + HW_SCE_p_func101(0x5e977c8eU, 0x225836d1U, 0x3259e6fdU, 0x2ba5b5e9U); + } + + HW_SCE_p_func100(0x323153b0U, 0x5a8ea4bfU, 0x6efe2f15U, 0x7e221345U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0x409f4db3U, 0xa52e87a4U, 0xa1b9d6b0U, 0xe00307ecU); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0x70346a8bU, 0xe4db9705U, 0x4ac62cc0U, 0x4799913fU); + + WR1_PROG(REG_D0H, 0x08000085U); + WR1_PROG(REG_B0H, 0x00000801U); + WR1_PROG(REG_00H, 0x00430009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_B0H, 0x00000802U); + WR1_PROG(REG_00H, 0x00430009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0xd844b852U, 0x1228b1b3U, 0x6c245004U, 0x02a8f215U); + WR1_PROG(REG_94H, 0x00007c04U); + WR1_PROG(REG_40H, 0x00600000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000000U) + { + HW_SCE_p_func101(0x3be31c9aU, 0x8724f055U, 0xf502c3a0U, 0xad4927e8U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000001U) + { + HW_SCE_p_func101(0xea99bfdcU, 0x1834c4baU, 0x7b25585aU, 0x6dfeebb1U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D0H, 0x08000045U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_IV[0]); + + HW_SCE_p_func101(0x5ad8e600U, 0xd66c96deU, 0x1da80fc7U, 0x1392f195U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000003U) + { + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D0H, 0x08000045U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_IV[0]); + + HW_SCE_p_func101(0xb7ee85c3U, 0xea6b9239U, 0x7835bac5U, 0x6d438e59U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000004U) + { + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D0H, 0x08000045U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_IV[0]); + + HW_SCE_p_func101(0xe1d5735dU, 0xfa86aa73U, 0xe9e7bf31U, 0x92537a04U); + } + else + { + } + + return FSP_SUCCESS; + } +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p47u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p47u.c new file mode 100644 index 000000000..009104af8 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p47u.c @@ -0,0 +1,103 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes128EncryptDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_14H, 0x000003c1U); + HW_SCE_p_func100(0xe328c699U, 0x2070b45dU, 0x8161cc79U, 0xf4afa3c4U); + + WR1_PROG(REG_14H, 0x00020061U); + WR1_PROG(REG_D0H, 0x0a000106U); + WR1_PROG(REG_08H, 0x000c1000U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_14H, 0x000003c1U); + HW_SCE_p_func100(0x90259b20U, 0xa8c5acaeU, 0x7eee33fdU, 0xc6c727d1U); + + WR1_PROG(REG_14H, 0x00020061U); + WR1_PROG(REG_D0H, 0x0a00010eU); + WR1_PROG(REG_08H, 0x000c1000U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_14H, 0x000003c1U); + HW_SCE_p_func100(0x5657f6eeU, 0x39dd13afU, 0x878296eeU, 0x7a03a2f7U); + + WR1_PROG(REG_14H, 0x00020061U); + WR1_PROG(REG_D0H, 0x0e000506U); + WR1_PROG(REG_08H, 0x000c1000U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000003U) + { + WR1_PROG(REG_14H, 0x000003c1U); + HW_SCE_p_func100(0x20411ef4U, 0x1d42cab4U, 0xf097d414U, 0xc9f5d68fU); + + WR1_PROG(REG_14H, 0x00020061U); + WR1_PROG(REG_D0H, 0x0900090eU); + WR1_PROG(REG_08H, 0x000c1000U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000004U) + { + WR1_PROG(REG_14H, 0x000003c1U); + HW_SCE_p_func100(0xdde79ba4U, 0xa80c7752U, 0xb8f3c5beU, 0x0bda82a4U); + + WR1_PROG(REG_14H, 0x00020061U); + WR1_PROG(REG_D0H, 0x07000d06U); + WR1_PROG(REG_08H, 0x000c1000U); + } + + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_Text[0]); + for (iLoop = 4; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_Text[iLoop]); + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_Text[MAX_CNT - 4]); + + if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000000U) + { + HW_SCE_p_func206(); + + HW_SCE_p_func101(0x49f6dcb5U, 0x325fca2fU, 0x623f62a9U, 0xa5f0b6acU); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000001U) + { + HW_SCE_p_func206(); + + HW_SCE_p_func101(0xecbe6b1eU, 0x87d413dbU, 0xf3016614U, 0xd2d38e2fU); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000002U) + { + HW_SCE_p_func206(); + + HW_SCE_p_func101(0xae7cd1f2U, 0x4a9b9d1cU, 0xc2a7bcfcU, 0x80eaf6f7U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000003U) + { + HW_SCE_p_func206(); + + HW_SCE_p_func101(0x352fb80cU, 0xef79e6f2U, 0xd4032798U, 0x60b5c291U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000004U) + { + HW_SCE_p_func206(); + + HW_SCE_p_func101(0xd4b626beU, 0x3cb7ed93U, 0x794aa619U, 0xb378a9c8U); + } +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p50f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p50f.c new file mode 100644 index 000000000..2e8cfd033 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p50f.c @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256EncryptDecryptFinalSub (void) +{ + if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000000U) + { + HW_SCE_p_func101(0xf5ed4b89U, 0xc35d7813U, 0x6077b61fU, 0x2454cdacU); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000001U) + { + HW_SCE_p_func101(0xc356f587U, 0xb892e933U, 0xfdd4816eU, 0x9c286438U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000002U) + { + HW_SCE_p_func101(0x87e6e6aeU, 0x6de43fe6U, 0x040fe532U, 0xa2c67e23U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000003U) + { + HW_SCE_p_func101(0x9ee1cb73U, 0x263a4efeU, 0xf338601aU, 0xd8ac1517U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000004U) + { + HW_SCE_p_func101(0xda0befdcU, 0xeada4bb9U, 0x07ab6353U, 0xe6653c81U); + } + + HW_SCE_p_func102(0x191bbdcdU, 0xe6b5fd44U, 0x0a44793dU, 0xec04dd68U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_SUCCESS; +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p50i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p50i.c new file mode 100644 index 000000000..f6653a15f --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p50i.c @@ -0,0 +1,188 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_6CH, 0x00000017U) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_70H, 0x00500001U); + WR1_PROG(REG_4CH, 0x00000000U); + + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x80010080U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_Cmd[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_94H, 0x3000a880U); + WR1_PROG(REG_94H, 0x00000004U); + WR1_PROG(REG_94H, 0x00010020U); + WR1_PROG(REG_94H, 0x0000b480U); + WR1_PROG(REG_94H, 0x00000004U); + WR1_PROG(REG_94H, 0x00000080U); + + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x80010000U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_KeyMode[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_94H, 0x38000c00U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + HW_SCE_p_func100(0xd2fcfefaU, 0x403853eaU, 0x9b79e301U, 0x19f794acU); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + if (CHCK_STS(REG_40H, 22, 1)) + { + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x800100c0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_KeyIndex[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000050U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0xf9132459U, 0x0ef7b7abU, 0x03518109U, 0x8a5c98f7U); + HW_SCE_p_func043(); + + WR1_PROG(REG_94H, 0x0000b4c0U); + WR1_PROG(REG_94H, 0x00000007U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000050U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0x0806dce3U, 0x9c0f4efeU, 0x3f1c04a5U, 0xd908a8efU); + HW_SCE_p_func044(); + + WR1_PROG(REG_14H, 0x000007c1U); + WR1_PROG(REG_D4H, 0x40000100U); + WR1_PROG(REG_D0H, 0xf7009d07U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_KeyIndex[1]); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_KeyIndex[5]); + + WR1_PROG(REG_B0H, 0x00001404U); + WR1_PROG(REG_00H, 0x00c10021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x07008d05U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_KeyIndex[9]); + + WR1_PROG(REG_D0H, 0x9c100005U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + HW_SCE_p_func101(0xbcebbe64U, 0x1f8a76b0U, 0x96ee50faU, 0xbe7298c7U); + } + else + { + WR1_PROG(REG_14H, 0x000007c5U); + WR1_PROG(REG_B0H, 0x00001404U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_Key[0]); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_Key[4]); + + HW_SCE_p_func101(0x164479c8U, 0x27eaa4ccU, 0x3559bea4U, 0xa5ba099dU); + } + + HW_SCE_p_func100(0x25ec5f4cU, 0x2117b1b3U, 0xf8c67c31U, 0x949a1cb2U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0xbb5bd2f9U, 0x90c164efU, 0xfc703f4dU, 0x096e6efdU); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0x58e0046cU, 0x71d34cf6U, 0x846dd938U, 0x61c59eadU); + WR1_PROG(REG_D0H, 0x08000085U); + WR1_PROG(REG_B0H, 0x00001804U); + WR1_PROG(REG_00H, 0x00430011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0x3b8d46feU, 0x6fbdd644U, 0x0f66a504U, 0xdbf9b0d2U); + WR1_PROG(REG_D0H, 0x08000095U); + WR1_PROG(REG_00H, 0x00430011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0xb09cf081U, 0x2c51db0aU, 0x10b93c6dU, 0xe149f9e4U); + WR1_PROG(REG_94H, 0x00007c04U); + WR1_PROG(REG_40H, 0x00600000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000000U) + { + HW_SCE_p_func101(0x0b47efa9U, 0x27152b5dU, 0xc876dd75U, 0x523e0d80U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000001U) + { + HW_SCE_p_func101(0xe62072d5U, 0x36995d48U, 0x3d74fa76U, 0xe4404164U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D0H, 0x08000045U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_IV[0]); + + HW_SCE_p_func101(0x3a9f257fU, 0x5919ba60U, 0x9676b2b6U, 0xa65084a4U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000003U) + { + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D0H, 0x08000045U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_IV[0]); + + HW_SCE_p_func101(0x955f3141U, 0xbad8b4f0U, 0xb0edd69cU, 0x3afd94f8U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000004U) + { + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D0H, 0x08000045U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_IV[0]); + + HW_SCE_p_func101(0xec765abdU, 0xc48110e5U, 0xc7ed046aU, 0x0d3915bdU); + } + else + { + } + + return FSP_SUCCESS; + } +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p50u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p50u.c new file mode 100644 index 000000000..5e9184ee3 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p50u.c @@ -0,0 +1,108 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes256EncryptDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_14H, 0x000003c1U); + HW_SCE_p_func100(0x72c4ba36U, 0xcbe3d0f6U, 0x9b50c9adU, 0x523ffd06U); + + WR1_PROG(REG_14H, 0x00020061U); + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x0a008106U); + WR1_PROG(REG_08H, 0x000c1000U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_14H, 0x000003c1U); + HW_SCE_p_func100(0x1e865a2bU, 0x61f06fd0U, 0x21c29d7eU, 0x5f88a3c7U); + + WR1_PROG(REG_14H, 0x00020061U); + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x0a00810eU); + WR1_PROG(REG_08H, 0x000c1000U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_14H, 0x000003c1U); + HW_SCE_p_func100(0x5016a475U, 0xcf53c48fU, 0xa51069beU, 0x3dc35bc8U); + + WR1_PROG(REG_14H, 0x00020061U); + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x0e008506U); + WR1_PROG(REG_08H, 0x000c1000U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000003U) + { + WR1_PROG(REG_14H, 0x000003c1U); + HW_SCE_p_func100(0x61354aecU, 0xac26e9f7U, 0xf5b5ca46U, 0xfe8aa518U); + + WR1_PROG(REG_14H, 0x00020061U); + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x0900890eU); + WR1_PROG(REG_08H, 0x000c1000U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000004U) + { + WR1_PROG(REG_14H, 0x000003c1U); + HW_SCE_p_func100(0x4dd8adefU, 0xb518cfa1U, 0x12669286U, 0x50b0d680U); + + WR1_PROG(REG_14H, 0x00020061U); + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x07008d06U); + WR1_PROG(REG_08H, 0x000c1000U); + } + + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_Text[0]); + for (iLoop = 4; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_Text[iLoop]); + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_Text[MAX_CNT - 4]); + + if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000000U) + { + HW_SCE_p_func206(); + + HW_SCE_p_func101(0xa3743bffU, 0x616e8d2cU, 0x91b488f6U, 0x9464b7a2U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000001U) + { + HW_SCE_p_func206(); + + HW_SCE_p_func101(0xfc2a2e62U, 0x69d664c1U, 0xad395df5U, 0x4b23da0cU); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000002U) + { + HW_SCE_p_func206(); + + HW_SCE_p_func101(0x8db9f0d5U, 0x19326f36U, 0x5f0c15e8U, 0x80427851U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000003U) + { + HW_SCE_p_func206(); + + HW_SCE_p_func101(0x4323e847U, 0x27b8654aU, 0x31cf7f97U, 0x7cce9ed1U); + } + else if (RD1_MASK(REG_44H, 0xffffffffU) == 0x00000004U) + { + HW_SCE_p_func206(); + + HW_SCE_p_func101(0x8500ea92U, 0x77b723caU, 0x9e8734ffU, 0x595b20a1U); + } +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p6e.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p6e.c new file mode 100644 index 000000000..7b4883892 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p6e.c @@ -0,0 +1,208 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_GenerateOemKeyIndexSub (const uint32_t InData_KeyType[], + const uint32_t InData_Cmd[], + const uint32_t InData_SharedKeyIndex[], + const uint32_t InData_SessionKey[], + const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t OFS_ADR = 0U; + + if (RD1_MASK(REG_6CH, 0x00000017U) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_70H, 0x006e0001U); + WR1_PROG(REG_4CH, 0x00000000U); + + HW_SCE_p_func048(InData_KeyType); + + WR1_PROG(REG_94H, 0x38000c00U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + HW_SCE_p_func100(0x82d3e31bU, 0xb0db125dU, 0x5c939002U, 0xdafa96d1U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func049(InData_Cmd); + + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x80010020U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(InData_SharedKeyIndex[0])); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_94H, 0x0000b440U); + WR1_PROG(REG_94H, 0x0C8003A0U); + + HW_SCE_p_func056(); + + WR1_PROG(REG_94H, 0x3420a820U); + WR1_PROG(REG_94H, 0x00000010U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00A60000U); + + HW_SCE_p_func100(0xbd376714U, 0x19a0b46fU, 0xa00b8e68U, 0x8d81a3d3U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0xf518f0baU, 0xb934a424U, 0x6d8c55a1U, 0xd1f64305U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_14H, 0x000001a1U); + WR1_PROG(REG_D0H, 0x07330c04U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_D0H, 0x07330d04U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_9CH, 0x80010000U); + WR1_PROG(REG_00H, 0x03410005U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_00H, 0x0001000dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_14H, 0x000001a1U); + WR1_PROG(REG_D0H, 0x07330d04U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_D0H, 0x06330104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_B0H, 0x00001404U); + WR1_PROG(REG_00H, 0x00c10021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + OFS_ADR = InData_SharedKeyIndex[0] << 3; + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x0000006eU)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0xf4ecbae2U, 0xd356ec96U, 0x039dd3e2U, 0xf553cbf0U); + HW_SCE_p_func058(InData_SessionKey, OFS_ADR); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x0000006eU)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0xd9282a6eU, 0x9aacc76eU, 0x79afa223U, 0xa556a55eU); + HW_SCE_p_func057(InData_IV, InData_InstData, OutData_KeyIndex); + + HW_SCE_p_func100(0xf4246079U, 0xb6319a3aU, 0x510a498dU, 0x93f08a44U); + WR1_PROG(REG_B0H, 0x00001804U); + + WR1_PROG(REG_D0H, 0x080000b5U); + WR1_PROG(REG_00H, 0x00430011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_D0H, 0x08000075U); + WR1_PROG(REG_00H, 0x00430011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0x920d6209U, 0x6e79e57bU, 0xf703150cU, 0xa172f769U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0x9775d67fU, 0x396d0f81U, 0x7ecbfb5fU, 0xf1fa5ac9U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xcf11713cU, 0xcbb3e7c3U, 0xcb64262eU, 0x9d3106c1U); + WR1_PROG(REG_9CH, 0x81010000U); + WR1_PROG(REG_08H, 0x00005006U); + WAIT_STS(REG_08H, 30, 1); + RD1_ADDR(REG_2CH, &OutData_KeyIndex[0]); + + HW_SCE_p_func102(0x465ecbceU, 0x7403c973U, 0x8187197aU, 0x05bcbc44U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_SUCCESS; + } + } + } + else + { + HW_SCE_p_func049(InData_Cmd); + + WR1_PROG(REG_94H, 0x0000b440U); + WR1_PROG(REG_94H, 0x0C8003A0U); + + HW_SCE_p_func056(); + + HW_SCE_p_func100(0x2f320995U, 0xf01bd8deU, 0x134332cbU, 0xb8e171dfU); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0xda71f61dU, 0xaa8f6948U, 0xf6566a76U, 0xe4231745U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x0000006eU)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0x36e893b5U, 0x062c17e1U, 0xa6f6085aU, 0xe4ceb753U); + HW_SCE_p_func093(InData_InstData, OutData_KeyIndex); + + HW_SCE_p_func100(0x9f5926edU, 0xe3766cd5U, 0xbbaca6dfU, 0x0bc5888aU); + WR1_PROG(REG_9CH, 0x81010000U); + WR1_PROG(REG_08H, 0x00005006U); + WAIT_STS(REG_08H, 30, 1); + RD1_ADDR(REG_2CH, &OutData_KeyIndex[0]); + + HW_SCE_p_func102(0x32fb2a21U, 0x5302162eU, 0xffe2a878U, 0xeb5cc9feU); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_SUCCESS; + } + } +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p70.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p70.c new file mode 100644 index 000000000..28d91f9da --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p70.c @@ -0,0 +1,118 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_OemKeyIndexValidationSub (const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_6CH, 0x00000017U) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_70H, 0x00700001U); + WR1_PROG(REG_4CH, 0x00000000U); + + HW_SCE_p_func049(InData_Cmd); + + WR1_PROG(REG_94H, 0x0000b440U); + WR1_PROG(REG_94H, 0x0C8003A0U); + + HW_SCE_p_func056(); + + HW_SCE_p_func100(0x744eb698U, 0x3978b211U, 0x0a8c0a57U, 0xdd149f18U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0x63759f6dU, 0xc5be6001U, 0x7992cee5U, 0x2f7df327U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x800100c0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(InData_KeyIndex[0])); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000070U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0x9cfc8e22U, 0x544594f6U, 0x3093dff4U, 0x38ef497fU); + HW_SCE_p_func043(); + + WR1_PROG(REG_94H, 0x000034c4U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000070U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0xe8c1278cU, 0x9eca8bc2U, 0x7ab4a6a5U, 0xc409e0feU); + HW_SCE_p_func044(); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x08000044U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_14H, 0x00020061U); + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0xf7009c06U); + + for (iLoop = 0U; iLoop < (KEY_INDEX_SIZE - 5); ) + { + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_KeyIndex[1 + iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func205_r1(); + + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x07008d05U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_KeyIndex[1 + iLoop]); + + WR1_PROG(REG_D0H, 0x9c100005U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0x44514f8dU, 0x3e29cbabU, 0xd634c0e3U, 0x402c3a89U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0xf521f8d8U, 0x762fd3a9U, 0x21105bd1U, 0xfb66ead9U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func102(0xabdb91cdU, 0xd5d27b10U, 0xe306bc34U, 0xfd5edb91U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_SUCCESS; + } + } +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p72.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p72.c new file mode 100644 index 000000000..bb03dfc44 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p72.c @@ -0,0 +1,64 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_ShaGenerateMessageDigestSub (const uint32_t InData_InitVal[], + const uint32_t InData_PaddedMsg[], + uint32_t OutData_MsgDigest[], + const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_68H, 0x00000016U) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_70H, 0x00720001U); + WR1_PROG(REG_4CH, 0x00000000U); + + WR1_PROG(REG_F4H, 0x00000010U); + + WAIT_STS(REG_F8H, 0, 1); + + WR1_PROG(REG_14H, 0x000007c4U); + WAIT_STS(REG_14H, 31, 1); + WR8_ADDR(REG_2CH, &InData_InitVal[0]); + + WR1_PROG(REG_F4H, 0x00000011U); + + WAIT_STS(REG_F8H, 0, 1); + + WR1_PROG(REG_14H, 0x00000064U); + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_14H, 31, 1); + WR16_ADDR(REG_2CH, &InData_PaddedMsg[iLoop]); + iLoop = iLoop + 16U; + } + + WAIT_STS(REG_F8H, 2, 0); + + WR1_PROG(REG_14H, 0x00000000U); + + WR1_PROG(REG_F4H, 0x00000100U); + + WR1_PROG(REG_F4H, 0x00000020U); + + WAIT_STS(REG_F8H, 1, 1); + + HW_SCE_p_func100(0x345f6e95U, 0xd7b24623U, 0x9a61bfd4U, 0x8761df09U); + WR1_PROG(REG_08H, 0x00004022U); + WAIT_STS(REG_08H, 30, 1); + RD8_ADDR(REG_2CH, &OutData_MsgDigest[0]); + + HW_SCE_p_func102(0xb6abe216U, 0xcdc58683U, 0x8c62c3dfU, 0x3b148ae0U); + WR1_PROG(REG_68H, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_SUCCESS; +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p81.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p81.c new file mode 100644 index 000000000..512386275 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p81.c @@ -0,0 +1,80 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_SelfCheck1Sub (void) +{ + WR1_PROG(REG_8CH, 0x00000001U); + + WAIT_STS(REG_8CH, 1, 0); + + if (RD1_MASK(REG_90H, 0xFFFFFFFFU) != 0x00047C00U) + { + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_0CH, 0x38c60eedU); + WR1_PROG(REG_24H, 0x00000000U); + WR1_PROG(REG_24H, 0x00000000U); + WR1_PROG(REG_48H, 0x00000000U); + + WR1_PROG(REG_08H, 0x00000001U); + WR1_PROG(REG_10H, 0x00001601U); + WR1_PROG(REG_24H, 0x00000000U); + WR1_PROG(REG_24H, 0x00000000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (RD1_MASK(REG_6CH, 0x00000017U) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_C0H, 0x00000001U); + WR1_PROG(REG_E0H, 0x00000001U); + WR1_PROG(REG_F0H, 0x00000001U); + + WR1_PROG(REG_70H, 0x00818001U); + WR1_PROG(REG_78H, 0x00000d00U); + + WR1_PROG(REG_C4H, 0x00008003U); + + WR1_PROG(REG_14H, 0x000003a1U); + HW_SCE_p_func101(change_endian_long(0xf0ff457fU), change_endian_long(0x2fe0cbe8U), change_endian_long(0x190e0f4aU), change_endian_long(0xb0f9c579U)); + WR1_PROG(REG_C4H, 0x00000000U); + + WR1_PROG(REG_14H, 0x000003a1U); + WR1_PROG(REG_D0H, 0x0a0700f5U); + WAIT_STS(REG_14H, 31, 1); + WR4_PROG(REG_2CH, 0x1863d378U, 0xf60d1643U, 0xfc1f44bdU, 0x46335a7cU); + + HW_SCE_p_func101(change_endian_long(0x7b2dcda0U), change_endian_long(0x8e1de57bU), change_endian_long(0xfe9947d0U), change_endian_long(0x9c241705U)); + + HW_SCE_p_func100(change_endian_long(0x17f7cbc4U), change_endian_long(0xf4585f39U), change_endian_long(0xe0f297abU), change_endian_long(0xf225d9daU)); + + WR1_PROG(REG_08H, 0x00020000U); + + if (CHCK_STS(REG_20H, 13, 0)) + { + WR1_PROG(REG_6CH, 0x00000020U); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_38H, 0x000000F1U); + + WR1_PROG(REG_78H, 0x00000220U); + + HW_SCE_p_func102(change_endian_long(0xc8930ce0U), change_endian_long(0x63e5b4ecU), change_endian_long(0x5fb76a71U), change_endian_long(0xe7971d26U)); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_SUCCESS; + } + } +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p82.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p82.c new file mode 100644 index 000000000..e4577bca3 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p82.c @@ -0,0 +1,415 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_SelfCheck2Sub (void) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + if (RD1_MASK(REG_6CH, 0x00000017U) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_70H, 0x00820001U); + WR1_PROG(REG_4CH, 0x00000000U); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0b0700c4U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x013e68caU)); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x08000074U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_94H, 0x3000a820U); + WR1_PROG(REG_94H, 0x00000003U); + WR1_PROG(REG_94H, 0x00010020U); + WR1_PROG(REG_94H, 0x00000821U); + WR1_PROG(REG_94H, 0x00000080U); + + WAIT_STS(REG_E8H, 0, 0); + + HW_SCE_p_func100(0x55d73436U, 0x03cb094dU, 0x01316a96U, 0x9e88f677U); + WR1_PROG(REG_94H, 0x00007c01U); + WR1_PROG(REG_40H, 0x00600000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (RD1_MASK(REG_44H, 0x0000ffffU) == 0x00000000U) + { + WAIT_STS(REG_E8H, 0, 0); + WR1_PROG(REG_E4H, 0x00200003U); + + HW_SCE_p_func101(0xf9fb1361U, 0x8c6fe7ffU, 0x567aafc3U, 0xa8b0b397U); + } + else if (RD1_MASK(REG_44H, 0x0000ffffU) == 0x00000001U) + { + WAIT_STS(REG_E8H, 0, 0); + WR1_PROG(REG_E4H, 0x00200001U); + + HW_SCE_p_func101(0x44a06a62U, 0x96362a25U, 0x8e01b304U, 0x1c5a5978U); + } + else if (RD1_MASK(REG_44H, 0x0000ffffU) == 0x00000002U) + { + WAIT_STS(REG_E8H, 0, 0); + WR1_PROG(REG_E4H, 0x00200002U); + + HW_SCE_p_func101(0x884c99e4U, 0x9a8e7fa1U, 0x92819604U, 0xb2025e49U); + } + + WR1_PROG(REG_D0H, 0x08000044U); + WR1_PROG(REG_9CH, 0x81010020U); + WR1_PROG(REG_00H, 0x00490005U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_94H, 0x00000800U); + WR1_PROG(REG_9CH, 0x80880000U); + WR1_PROG(REG_00H, 0x03400021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_94H, 0x000008e7U); + + WR1_PROG(REG_94H, 0x0000b480U); + WR1_PROG(REG_94H, 0xffffffffU); + + WR1_PROG(REG_94H, 0x0000b4c0U); + WR1_PROG(REG_94H, 0x00000001U); + + WR1_PROG(REG_D0H, 0x0e340406U); + + for (iLoop = 0U; iLoop < 32U; iLoop++) + { + WR1_PROG(REG_9CH, 0x80010000U); + WR1_PROG(REG_00H, 0x03440005U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_9CH, 0x81010000U); + WR1_PROG(REG_00H, 0x00490005U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_94H, 0x00003420U); + + for (jLoop = 0U; jLoop < 8U; jLoop++) + { + WR1_PROG(REG_94H, 0x00003441U); + + WR1_PROG(REG_94H, 0x00008c40U); + WR1_PROG(REG_94H, 0x0000000fU); + + WR1_PROG(REG_94H, 0x00016c42U); + + WR1_PROG(REG_94H, 0x01003862U); + + WR1_PROG(REG_94H, 0x00002c60U); + + WR1_PROG(REG_94H, 0x01003c62U); + + WR1_PROG(REG_94H, 0x00046821U); + } + + WR1_PROG(REG_94H, 0x00003420U); + + WR1_PROG(REG_94H, 0x00003441U); + + WR1_PROG(REG_94H, 0x00008c40U); + WR1_PROG(REG_94H, 0x80000000U); + + WR1_PROG(REG_94H, 0x38000882U); + WR1_PROG(REG_94H, 0x00030020U); + + WR1_PROG(REG_94H, 0x00002ca0U); + + WR1_PROG(REG_94H, 0x342028c5U); + WR1_PROG(REG_94H, 0x100034c5U); + + WR1_PROG(REG_94H, 0x00000060U); + + WR1_PROG(REG_94H, 0x0000b4a0U); + WR1_PROG(REG_94H, 0x00000001U); + + WR1_PROG(REG_94H, 0x00000080U); + + for (jLoop = 0U; jLoop < 31; jLoop++) + { + WR1_PROG(REG_94H, 0x00016c21U); + + WR1_PROG(REG_94H, 0x00003481U); + + WR1_PROG(REG_94H, 0x00008c80U); + WR1_PROG(REG_94H, 0x80000000U); + + WR1_PROG(REG_94H, 0x38000882U); + WR1_PROG(REG_94H, 0x00030020U); + + WR1_PROG(REG_94H, 0x00002ca0U); + + WR1_PROG(REG_94H, 0x342028c5U); + WR1_PROG(REG_94H, 0x100034c5U); + + WR1_PROG(REG_94H, 0x00000060U); + + WR1_PROG(REG_94H, 0x00003444U); + + WR1_PROG(REG_94H, 0x0000b4a0U); + WR1_PROG(REG_94H, 0x00000001U); + + WR1_PROG(REG_94H, 0x00000080U); + } + + WR1_PROG(REG_94H, 0x00003420U); + + for (jLoop = 0U; jLoop < 32U; jLoop++) + { + WR1_PROG(REG_94H, 0x38008c20U); + WR1_PROG(REG_94H, 0x00000001U); + WR1_PROG(REG_94H, 0x00020020U); + + WR1_PROG(REG_94H, 0x00002ce0U); + + WR1_PROG(REG_94H, 0x00000060U); + + WR1_PROG(REG_94H, 0x0000a4e0U); + WR1_PROG(REG_94H, 0x00010000U); + + WR1_PROG(REG_94H, 0x00000080U); + + WR1_PROG(REG_94H, 0x00016821U); + } + } + + WR1_PROG(REG_40H, 0x00001200U); + WAIT_STS(REG_C8H, 6, 0); + WR1_PROG(REG_D0H, 0x00000000U); + WR1_PROG(REG_40H, 0x00000400U); + + WR1_PROG(REG_94H, 0x00000800U); + + WR1_PROG(REG_94H, 0x0000b420U); + WR1_PROG(REG_94H, 0x00000033U); + + WR1_PROG(REG_94H, 0x342028c1U); + WR1_PROG(REG_94H, 0x2000d011U); + + WR1_PROG(REG_94H, 0x0000b4a0U); + WR1_PROG(REG_94H, 0x00000348U); + + WR1_PROG(REG_94H, 0x0000b4c0U); + WR1_PROG(REG_94H, 0x000000b7U); + + WR1_PROG(REG_94H, 0x00003467U); + WR1_PROG(REG_94H, 0x00008c60U); + WR1_PROG(REG_94H, 0x0000ffffU); + + WR1_PROG(REG_94H, 0x34202865U); + WR1_PROG(REG_94H, 0x2000d012U); + + WR1_PROG(REG_94H, 0x342028c3U); + WR1_PROG(REG_94H, 0x2000d012U); + + WR1_PROG(REG_94H, 0x001068e7U); + + WR1_PROG(REG_94H, 0x342028e5U); + WR1_PROG(REG_94H, 0x2000d013U); + + WR1_PROG(REG_94H, 0x342028c7U); + WR1_PROG(REG_94H, 0x2000d013U); + + WR1_PROG(REG_94H, 0x00002467U); + + HW_SCE_p_func100(0xb0c2b455U, 0x67a42c02U, 0xb91fb3cbU, 0x117e44d0U); + WR1_PROG(REG_94H, 0x38008860U); + WR1_PROG(REG_94H, 0x00000400U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + WR1_PROG(REG_40H, 0x00402000U); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_08H, 0x00020000U); + + WR1_PROG(REG_94H, 0x0000b420U); + WR1_PROG(REG_94H, 0x0000005AU); + + WR1_PROG(REG_94H, 0x00000842U); + + WR1_PROG(REG_94H, 0x00000863U); + + WR1_PROG(REG_94H, 0x00000884U); + + WR1_PROG(REG_94H, 0x0000b4a0U); + WR1_PROG(REG_94H, 0x00000002U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_94H, 0x010038c4U); + + WR1_PROG(REG_94H, 0x34202826U); + WR1_PROG(REG_94H, 0x10005002U); + + WR1_PROG(REG_94H, 0x00002466U); + + WR1_PROG(REG_94H, 0x00002c40U); + + WR1_PROG(REG_94H, 0x00002485U); + } + + HW_SCE_p_func100(0xbef2e50aU, 0x69999e1dU, 0x290ca8c4U, 0xad8c7d17U); + WR1_PROG(REG_94H, 0x38008860U); + WR1_PROG(REG_94H, 0x00000100U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + WR1_PROG(REG_40H, 0x00402000U); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_08H, 0x00020000U); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c000104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + WR1_PROG(REG_9CH, 0x80010020U); + WR1_PROG(REG_00H, 0x03410005U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_00H, 0x0001000dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_94H, 0x00002c20U); + + WR1_PROG(REG_94H, 0x38000c00U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00A60000U); + + HW_SCE_p_func100(0x3e5c36f5U, 0x7e22cb6eU, 0x625146beU, 0xa98518dbU); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0xbe37cd78U, 0xf2ebfe39U, 0xb6417257U, 0x614e402cU); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_RETRY; + } + else + { + HW_SCE_p_func100(0x9d47a042U, 0xe7c53d1dU, 0xb8d416d4U, 0x2511452cU); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c300104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + WR1_PROG(REG_9CH, 0x80040000U); + WR1_PROG(REG_00H, 0x03410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_D4H, 0x00000600U); + WR1_PROG(REG_D0H, 0x0e349407U); + WAIT_STS(REG_E8H, 0, 0); + WR1_PROG(REG_E4H, 0x00200003U); + WR1_PROG(REG_00H, 0x00440071U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_D0H, 0x0e340505U); + WR1_PROG(REG_00H, 0x00440011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WAIT_STS(REG_E8H, 3, 0); + WR1_PROG(REG_E0H, 0x00000000U); + WR1_PROG(REG_9CH, 0x80040080U); + WR1_PROG(REG_00H, 0x03410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x080000b4U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + HW_SCE_p_func100(0x0380c24dU, 0x8960d168U, 0xa4457366U, 0x24fcd105U); + WR1_PROG(REG_14H, 0x000003a1U); + WR1_PROG(REG_D0H, 0x08000075U); + WAIT_STS(REG_14H, 31, 1); + WR4_PROG(REG_2CH, change_endian_long(0x00000000U), change_endian_long(0x00000000U), + change_endian_long(0x00000000U), change_endian_long(0x00000001U)); + + WR1_PROG(REG_D4H, 0x00000100U); + WR1_PROG(REG_D0H, 0x07338d07U); + WR1_PROG(REG_9CH, 0x81080000U); + WR1_PROG(REG_00H, 0x00490021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_D0H, 0x080000b5U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func100(0x6c62d004U, 0xa627ba76U, 0x44932a89U, 0x7fadbba0U); + WR1_PROG(REG_D0H, 0x08000075U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func103(); + HW_SCE_p_func100(0xa48af824U, 0x0bd286a5U, 0xc8fa2f14U, 0x95f3f5b6U); + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c2000d4U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + HW_SCE_p_func100(0x85a3279fU, 0x254914e6U, 0x9cf14f75U, 0xaccd6503U); + HW_SCE_p_func103(); + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c200104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_A0H, 0x00030000U); + WR1_PROG(REG_04H, 0x20000000U); + WR1_PROG(REG_B0H, 0x00000401U); + + WR1_PROG(REG_00H, 0x00c10009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_00H, 0x00010009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_04H, 0x00000000U); + WR1_PROG(REG_A0H, 0x00030000U); + WR1_PROG(REG_B0H, 0x000074c0U); + WR1_PROG(REG_00H, 0x00c00601U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_70H, 0x00008002U); + WR1_PROG(REG_78H, 0x00000d01U); + + WR1_PROG(REG_70H, 0x00008001U); + + WR1_PROG(REG_78H, 0x00000214U); + + HW_SCE_p_func102(0x8b8e2f4cU, 0x973198f0U, 0x23fcc132U, 0xa090def0U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_SUCCESS; + } +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p9a.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p9a.c new file mode 100644 index 000000000..94cf32d3f --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_p9a.c @@ -0,0 +1,222 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Ecc256ScalarMultiplicationSub (const uint32_t InData_CurveType[], + const uint32_t InData_KeyMode[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_PubKey[], + const uint32_t InData_DomainParam[], + uint32_t OutData_R[]) +{ + if (RD1_MASK(REG_6CH, 0x00000017U) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_70H, 0x009a0001U); + WR1_PROG(REG_4CH, 0x00000000U); + + WR1_PROG(REG_A0H, 0x20010000U); + + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x80010000U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_CurveType[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_94H, 0x38000c00U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00A60000U); + + HW_SCE_p_func100(0x04dd6ff0U, 0x0d454f9bU, 0xc9394c13U, 0x595afb72U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0xc64170cdU, 0x7817b7ebU, 0xbfa5f1e2U, 0x79584773U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x80010000U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_KeyMode[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_94H, 0x38000c00U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + HW_SCE_p_func100(0x88f96129U, 0x5b131016U, 0x99354542U, 0xf8778698U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + if (CHCK_STS(REG_40H, 22, 1)) + { + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x800100c0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_KeyIndex[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x0000009aU)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0x83c6a382U, 0x806d1a0cU, 0x12d68ad5U, 0xf6a03e8cU); + HW_SCE_p_func043(); + + WR1_PROG(REG_94H, 0x0000b4c0U); + WR1_PROG(REG_94H, 0x00000017U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x0000009aU)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0x2a36536cU, 0xae2fd4f9U, 0xa180c82fU, 0x4dca39c2U); + HW_SCE_p_func044(); + + WR1_PROG(REG_14H, 0x000007c1U); + WR1_PROG(REG_D4H, 0x40000100U); + WR1_PROG(REG_D0H, 0xf7009d07U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_KeyIndex[1]); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_KeyIndex[5]); + + WR1_PROG(REG_B0H, 0x00001432U); + WR1_PROG(REG_00H, 0x00c10021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x07008d05U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_KeyIndex[9]); + + WR1_PROG(REG_D0H, 0x9c100005U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func101(0xb93bb137U, 0x93dcee7eU, 0x545a76f0U, 0x49638153U); + } + else + { + WR1_PROG(REG_14H, 0x000007c5U); + WR1_PROG(REG_B0H, 0x00001432U); + WAIT_STS(REG_14H, 31, 1); + WR8_ADDR(REG_2CH, &InData_Key[0]); + + HW_SCE_p_func101(0x769108e3U, 0x03fd16f6U, 0xeda8433aU, 0x49d938ceU); + } + + HW_SCE_p_func100(0xedc1957aU, 0xa790b1ffU, 0x9196da75U, 0x6b36a4eeU); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0x50ccc8dcU, 0x6cf7177fU, 0xb36f3fe0U, 0x1fc6940bU); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func070(InData_DomainParam); + + WR1_PROG(REG_B8H, 0x00000005U); + + WR1_PROG(REG_A4H, 0x04040010U); + + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_14H, 0x00000fc5U); + WR1_PROG(REG_B0H, 0x0000140fU); + WAIT_STS(REG_14H, 31, 1); + WR8_ADDR(REG_2CH, &InData_PubKey[0]); + + WR1_PROG(REG_B0H, 0x00001414U); + WAIT_STS(REG_14H, 31, 1); + WR8_ADDR(REG_2CH, &InData_PubKey[8]); + + HW_SCE_p_func008(); + + HW_SCE_p_func100(0xb6523c98U, 0xc695978dU, 0x23496e84U, 0x305ff6ceU); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0x6f711c3bU, 0x366fa6d9U, 0x3eeb03c8U, 0x3521d7eeU); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x0000009aU)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0x977507deU, 0x6fec17afU, 0x022e279aU, 0x7d888ef5U); + HW_SCE_p_func088(); + + HW_SCE_p_func100(0x9aa56be7U, 0xec4a4a90U, 0x931c1ecbU, 0x9fb2602fU); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0xbada36b6U, 0xb1a266faU, 0x803c7b19U, 0x766f38c2U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xe8cc660aU, 0xd5b85404U, 0x088acd67U, 0x2159f401U); + WR1_PROG(REG_B0H, 0x00001828U); + WR1_PROG(REG_08H, 0x00006022U); + WAIT_STS(REG_08H, 30, 1); + RD8_ADDR(REG_2CH, &OutData_R[0]); + + HW_SCE_p_func100(0xdcc2a953U, 0x8e3ff986U, 0xa917da34U, 0xec3ce9e1U); + WR1_PROG(REG_B0H, 0x0000182dU); + WR1_PROG(REG_08H, 0x00006022U); + WAIT_STS(REG_08H, 30, 1); + RD8_ADDR(REG_2CH, &OutData_R[8]); + + HW_SCE_p_func102(0x9707deccU, 0x41dffacfU, 0xde1c9557U, 0xf7e46917U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_SUCCESS; + } + } + } + } +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_pf0.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_pf0.c new file mode 100644 index 000000000..53ec3dfc1 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_pf0.c @@ -0,0 +1,421 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_EcdsaSignatureGenerateSub (const uint32_t InData_CurveType[], + const uint32_t InData_KeyMode[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_DomainParam[], + uint32_t OutData_Signature[]) +{ + if (RD1_MASK(REG_6CH, 0x00000017U) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_70H, 0x00f00001U); + WR1_PROG(REG_4CH, 0x00000000U); + + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x80010000U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_CurveType[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_94H, 0x38000c00U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00A60000U); + + HW_SCE_p_func100(0xfd930acbU, 0x5f7dae3eU, 0xdb481737U, 0x02b3719cU); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0x0dbefb02U, 0xf58d669dU, 0x9fe89dedU, 0x87108f6aU); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func070(InData_DomainParam); + + HW_SCE_p_func100(0x88a198d6U, 0x40267339U, 0xc4747ec4U, 0xcf0adae9U); + + WR1_PROG(REG_B0H, 0x0000140fU); + HW_SCE_p_func103(); + HW_SCE_p_func100(0x7eacebe1U, 0x0a53c92eU, 0x6b4bb952U, 0x7e6b3ca7U); + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c200104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + WR1_PROG(REG_00H, 0x00c10011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func103(); + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c200104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + WR1_PROG(REG_00H, 0x00c10011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_B0H, 0x00001428U); + WR1_PROG(REG_00H, 0x00c0001dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_14H, 0x000000a5U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000001U)); + + WR1_PROG(REG_B0H, 0x00001419U); + WR1_PROG(REG_00H, 0x00c0001dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_14H, 0x000000a5U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000002U)); + + WR1_PROG(REG_B4H, 0x0019000aU); + WR1_PROG(REG_B8H, 0x00140000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_A0H, 0x20010000U); + WR1_PROG(REG_B8H, 0x00000014U); + + WR1_PROG(REG_A4H, 0x04040010U); + + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x0028000fU); + WR1_PROG(REG_B8H, 0x002d0014U); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x0028002dU); + WR1_PROG(REG_B8H, 0x00320000U); + + WR1_PROG(REG_A4H, 0x04040009U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + HW_SCE_p_func071(InData_DomainParam); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x000000f0U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0xb57d02d9U, 0xd7e8754eU, 0xfa62fd94U, 0x15262966U); + HW_SCE_p_func088(); + + HW_SCE_p_func100(0xaaf87e98U, 0xe8e3ec7eU, 0xce77ae89U, 0x9572cbaeU); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0xc815d4cfU, 0xf1790d98U, 0xa66a0668U, 0x3b5401e7U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_B8H, 0x0000000aU); + + WR1_PROG(REG_A4H, 0x04040010U); + + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x005a0028U); + WR1_PROG(REG_B8H, 0x002d000aU); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_14H, 0x000000a5U); + WR1_PROG(REG_B0H, 0x0000140fU); + WR1_PROG(REG_00H, 0x00c0001dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000001U)); + + WR1_PROG(REG_B4H, 0x000f002dU); + WR1_PROG(REG_B8H, 0x0028000aU); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x000f0028U); + WR1_PROG(REG_B8H, 0x00140000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_40H, 0x00210000U); + + HW_SCE_p_func100(0xfdbaed1cU, 0xd56ce5beU, 0x639635d2U, 0xcacc94b9U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0xd2c4ec5dU, 0x25fc2807U, 0xc3e3dac8U, 0xb2c34828U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xaf54dd06U, 0x6f470315U, 0x0e2b326dU, 0xa4ee0942U); + WR1_PROG(REG_B0H, 0x00001414U); + WR1_PROG(REG_00H, 0x00c0001dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_14H, 0x000000a5U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000002U)); + + WR1_PROG(REG_B4H, 0x0014000aU); + WR1_PROG(REG_B8H, 0x000f0000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x000f0032U); + WR1_PROG(REG_B8H, 0x0014000aU); + + WR1_PROG(REG_A4H, 0x04040000U); + WR1_PROG(REG_08H, 0x00020000U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + WR1_PROG(REG_40H, 0x00000d00U); + + WR1_PROG(REG_B4H, 0x005a0014U); + WR1_PROG(REG_B8H, 0x000f000aU); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_14H, 0x000007c5U); + WR1_PROG(REG_B0H, 0x00001414U); + WAIT_STS(REG_14H, 31, 1); + WR8_ADDR(REG_2CH, &InData_MsgDgst[0]); + + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x80010000U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_KeyMode[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_94H, 0x38000c00U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + HW_SCE_p_func100(0x533eeeeeU, 0x8b40ae27U, 0x3299f79cU, 0x86fe532dU); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + if (CHCK_STS(REG_40H, 22, 1)) + { + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x800100c0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_KeyIndex[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x000000f0U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0x6c37c3f9U, 0x5ab97345U, 0xb744f508U, 0x2b081a6eU); + HW_SCE_p_func043(); + + WR1_PROG(REG_94H, 0x0000b4c0U); + WR1_PROG(REG_94H, 0x00000017U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x000000f0U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0x395dfcbfU, 0x9de1b66dU, 0x1d5c144eU, 0xabbe75e3U); + HW_SCE_p_func044(); + + WR1_PROG(REG_14H, 0x000007c1U); + WR1_PROG(REG_D4H, 0x40000100U); + WR1_PROG(REG_D0H, 0xf7009d07U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_KeyIndex[1]); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_KeyIndex[5]); + + WR1_PROG(REG_B0H, 0x0000141eU); + WR1_PROG(REG_00H, 0x00c10021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_14H, 0x000003c1U); + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x07008d05U); + WAIT_STS(REG_14H, 31, 1); + WR4_ADDR(REG_2CH, &InData_KeyIndex[9]); + + WR1_PROG(REG_D0H, 0x9c100005U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func101(0x53e20bf4U, 0xedfd1779U, 0x099a4fd8U, 0x51a8b7d1U); + } + else + { + WR1_PROG(REG_14H, 0x000007c5U); + WR1_PROG(REG_B0H, 0x0000141eU); + WAIT_STS(REG_14H, 31, 1); + WR8_ADDR(REG_2CH, &InData_Key[0]); + + HW_SCE_p_func101(0x1d013a9eU, 0x16120328U, 0xc822b330U, 0xb50d0c07U); + } + + HW_SCE_p_func100(0xe9fcbeceU, 0x076b959bU, 0xb316972fU, 0xbb7bc321U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0x5ab4eafdU, 0xe84d02b0U, 0xd6ba5b5eU, 0xf69185c1U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_B4H, 0x005a001eU); + WR1_PROG(REG_B8H, 0x0019000aU); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x00280019U); + WR1_PROG(REG_B8H, 0x001e000aU); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x001e0014U); + WR1_PROG(REG_B8H, 0x0019000aU); + + WR1_PROG(REG_A4H, 0x04040005U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x0019000fU); + WR1_PROG(REG_B8H, 0x001e000aU); + + WR1_PROG(REG_A4H, 0x04040002U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B0H, 0x0000140fU); + WR1_PROG(REG_00H, 0x00c0001dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_14H, 0x000000a5U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000001U)); + + WR1_PROG(REG_B4H, 0x000f001eU); + WR1_PROG(REG_B8H, 0x00140000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_40H, 0x00210000U); + + HW_SCE_p_func100(0xfdf98537U, 0x88686999U, 0x5dbdc03fU, 0x7a51cf04U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0x958994e2U, 0x31cd8014U, 0x83b5923dU, 0xf77c8004U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x014a78bcU, 0x323cfaaeU, 0x1c1adda2U, 0xae02aec1U); + WR1_PROG(REG_B0H, 0x00001828U); + WR1_PROG(REG_08H, 0x00006022U); + WAIT_STS(REG_08H, 30, 1); + RD8_ADDR(REG_2CH, &OutData_Signature[0]); + + HW_SCE_p_func100(0x4494f1a1U, 0xdce6128fU, 0x80f2a930U, 0xb4ebaf68U); + WR1_PROG(REG_B0H, 0x0000181eU); + WR1_PROG(REG_08H, 0x00006022U); + WAIT_STS(REG_08H, 30, 1); + RD8_ADDR(REG_2CH, &OutData_Signature[8]); + + HW_SCE_p_func102(0x33b7c3a5U, 0xcbf88c64U, 0x98226388U, 0x44c14fbdU); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_SUCCESS; + } + } + } + } + } +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_pf1.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_pf1.c new file mode 100644 index 000000000..2d02c1789 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_pf1.c @@ -0,0 +1,97 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_EcdsaSignatureVerificationSub (const uint32_t InData_CurveType[], + const uint32_t InData_Key[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[]) +{ + if (RD1_MASK(REG_6CH, 0x00000017U) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_70H, 0x00f10001U); + WR1_PROG(REG_4CH, 0x00000000U); + + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x80010000U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_CurveType[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_94H, 0x38000c00U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00A60000U); + + HW_SCE_p_func100(0x039aa74bU, 0x8948d1e2U, 0x1ce8804aU, 0xa2e1286dU); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0x653ec71bU, 0x5233fe8bU, 0x9fc522ddU, 0x11847f47U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_A0H, 0x20010000U); + WR1_PROG(REG_14H, 0x00000fc5U); + WR1_PROG(REG_B0H, 0x00001469U); + WAIT_STS(REG_14H, 31, 1); + WR8_ADDR(REG_2CH, &InData_Signature[0]); + + WR1_PROG(REG_B0H, 0x0000146eU); + WAIT_STS(REG_14H, 31, 1); + WR8_ADDR(REG_2CH, &InData_Signature[8]); + + WR1_PROG(REG_14H, 0x000007c5U); + WR1_PROG(REG_B0H, 0x00001472U); + WAIT_STS(REG_14H, 31, 1); + WR8_ADDR(REG_2CH, &InData_MsgDgst[0]); + + WR1_PROG(REG_14H, 0x00000fc5U); + WR1_PROG(REG_B0H, 0x0000347aU); + WAIT_STS(REG_14H, 31, 1); + WR16_ADDR(REG_2CH, &InData_Key[0]); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x000000f1U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0xb44a7995U, 0x825fc4d4U, 0xf3f3d9d1U, 0x0cf371e0U); + HW_SCE_p_func073(InData_DomainParam); + + HW_SCE_p_func100(0x749dea76U, 0x6dd8bc9fU, 0x9bc7dc61U, 0x0d10e1edU); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0x95ee8092U, 0x0652b63dU, 0x2f5889d3U, 0xa339c87aU); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func102(0x503b44dbU, 0x5473c356U, 0xe59db169U, 0xa579f328U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_SUCCESS; + } + } +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_pf4.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_pf4.c new file mode 100644 index 000000000..bc5988149 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/hw_sce_p_pf4.c @@ -0,0 +1,441 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_GenerateEccRandomKeyIndexSub (const uint32_t InData_KeyMode[], + const uint32_t InData_CurveType[], + const uint32_t InData_DomainParam[], + uint32_t OutData_PubKey[], + uint32_t OutData_PrivKeyIndex[], + uint32_t OutData_PrivKey[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_6CH, 0x00000017U) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_70H, 0x00f40001U); + WR1_PROG(REG_4CH, 0x00000000U); + + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x80010000U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_CurveType[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_94H, 0x38000c00U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00A60000U); + + HW_SCE_p_func100(0xe1655fa9U, 0x10cb5f07U, 0x5e631d58U, 0xe8449f6cU); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0xb83e9ab0U, 0x987328edU, 0xceca149bU, 0x1ef0a176U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func070(InData_DomainParam); + + WR1_PROG(REG_A0H, 0x20010000U); + WR1_PROG(REG_B0H, 0x00002428U); + + HW_SCE_p_func100(0xa09dae7cU, 0xdc3771b6U, 0x67cedc83U, 0x75e3b6ceU); + HW_SCE_p_func103(); + HW_SCE_p_func100(0x370c5e16U, 0x6dbab032U, 0xf97621dbU, 0xec47788bU); + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c200104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + WR1_PROG(REG_00H, 0x00c10009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_00H, 0x00010009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func103(); + HW_SCE_p_func100(0x3eb27e2dU, 0x4ca3bc36U, 0x287a15e6U, 0x871cc18dU); + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c200104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + WR1_PROG(REG_00H, 0x00c10011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + HW_SCE_p_func103(); + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c200104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + WR1_PROG(REG_00H, 0x00c10011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_B0H, 0x0000140fU); + WR1_PROG(REG_00H, 0x00c0001dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_14H, 0x000000a5U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000001U)); + + WR1_PROG(REG_B4H, 0x000f000aU); + WR1_PROG(REG_B8H, 0x00140000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B0H, 0x0000143cU); + WR1_PROG(REG_00H, 0x00c0001dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_14H, 0x000000a5U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000002U)); + + WR1_PROG(REG_B0H, 0x00001419U); + WR1_PROG(REG_00H, 0x00c00021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_94H, 0x00000821U); + WR1_PROG(REG_94H, 0x00000863U); + WR1_PROG(REG_94H, 0x000008a5U); + + for (iLoop = 0U; iLoop < 64U; iLoop++) + { + WR1_PROG(REG_B4H, 0x00140027U); + WR1_PROG(REG_B8H, 0x001e0000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B0H, 0x0000081aU); + WR1_PROG(REG_9CH, 0x80020000U); + WR1_PROG(REG_00H, 0x03430009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_94H, 0x00000884U); + + WR1_PROG(REG_94H, 0x38000c21U); + WR1_PROG(REG_94H, 0x2000d080U); + + WR1_PROG(REG_94H, 0x38000c63U); + WR1_PROG(REG_94H, 0x1000d081U); + + WR1_PROG(REG_94H, 0x38008880U); + WR1_PROG(REG_94H, 0x00000003U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + HW_SCE_p_func100(0x136e4fd0U, 0x2a3d4709U, 0xe229ac61U, 0x3df6b00eU); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + WR1_PROG(REG_B4H, 0x0019001eU); + WR1_PROG(REG_B8H, 0x004b0000U); + + WR1_PROG(REG_A4H, 0x04040009U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + HW_SCE_p_func101(0xbe35432dU, 0x19b4ccb6U, 0xdd428c97U, 0x4020f0e9U); + } + else + { + WR1_PROG(REG_B4H, 0x0019001eU); + WR1_PROG(REG_B8H, 0x00270000U); + + WR1_PROG(REG_A4H, 0x04040009U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + HW_SCE_p_func101(0xe8d967ceU, 0xd5fb32d9U, 0xd2d066f7U, 0x08f7babaU); + } + + WR1_PROG(REG_B4H, 0x003c002bU); + WR1_PROG(REG_B8H, 0x001e0000U); + + WR1_PROG(REG_A4H, 0x04040007U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x003c0027U); + WR1_PROG(REG_B8H, 0x00230000U); + + WR1_PROG(REG_A4H, 0x04040007U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B0H, 0x0000081fU); + WR1_PROG(REG_9CH, 0x80020040U); + WR1_PROG(REG_00H, 0x03430009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_B4H, 0x0019001eU); + WR1_PROG(REG_B8H, 0x002b0000U); + + WR1_PROG(REG_A4H, 0x04040009U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B4H, 0x001a0023U); + WR1_PROG(REG_B8H, 0x00270000U); + + WR1_PROG(REG_A4H, 0x04040009U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_94H, 0x00002ca0U); + + HW_SCE_p_func101(0xe2c56e03U, 0xa85e461bU, 0x367e12e0U, 0x31c60900U); + } + + WR1_PROG(REG_94H, 0x380088a0U); + WR1_PROG(REG_94H, 0x00000040U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + WR1_PROG(REG_40H, 0x00402000U); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_B4H, 0x00140027U); + WR1_PROG(REG_B8H, 0x001e0000U); + + WR1_PROG(REG_A4H, 0x0404000aU); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + WR1_PROG(REG_B0H, 0x0000081aU); + WR1_PROG(REG_9CH, 0x80020000U); + WR1_PROG(REG_00H, 0x03430009U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_94H, 0x00000884U); + + WR1_PROG(REG_94H, 0x38000c21U); + WR1_PROG(REG_94H, 0x2000d080U); + + WR1_PROG(REG_94H, 0x38000c63U); + WR1_PROG(REG_94H, 0x1000d081U); + + WR1_PROG(REG_94H, 0x38008880U); + WR1_PROG(REG_94H, 0x00000003U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + HW_SCE_p_func100(0x83026fa5U, 0x88c9d714U, 0x6e07060dU, 0x8066febbU); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + WR1_PROG(REG_B4H, 0x0019001eU); + WR1_PROG(REG_B8H, 0x004b0000U); + + WR1_PROG(REG_A4H, 0x04040009U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + HW_SCE_p_func101(0x83faaa75U, 0x8b66b906U, 0x057f0ce1U, 0xcf1ea8abU); + } + else + { + WR1_PROG(REG_B4H, 0x0019001eU); + WR1_PROG(REG_B8H, 0x00270000U); + + WR1_PROG(REG_A4H, 0x04040009U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + HW_SCE_p_func101(0x3f065c13U, 0x1630f2d1U, 0x850fd28eU, 0x983ec30aU); + } + + WR1_PROG(REG_B4H, 0x000f0027U); + WR1_PROG(REG_B8H, 0x00320000U); + + WR1_PROG(REG_A4H, 0x04040009U); + WR1_PROG(REG_A0H, 0x20010001U); + WAIT_STS(REG_A8H, 0, 1); + WR1_PROG(REG_ACH, 0x00000001U); + + HW_SCE_p_func071(InData_DomainParam); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x000000f4U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0xdd1eee67U, 0xd8f080dfU, 0x192fa9f0U, 0xcd5f776cU); + HW_SCE_p_func088(); + + HW_SCE_p_func100(0xcb83c991U, 0xd0e8b383U, 0xa9aa384cU, 0xfce6e1a7U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func102(0xf8b93f4bU, 0xf90039dcU, 0x82807fd8U, 0xae8f365cU); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_14H, 0x000000c7U); + WR1_PROG(REG_9CH, 0x80010000U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, InData_KeyMode[0]); + WR1_PROG(REG_24H, 0x00000000U); + + WR1_PROG(REG_94H, 0x38000c00U); + WR1_PROG(REG_9CH, 0x00000080U); + WR1_PROG(REG_40H, 0x00260000U); + + HW_SCE_p_func100(0x17e3b02bU, 0xc25d4013U, 0x2b23b657U, 0x1f764db1U); + WR1_PROG(REG_40H, 0x00400000U); + WR1_PROG(REG_24H, 0x00000000U); + if (CHCK_STS(REG_40H, 22, 1)) + { + HW_SCE_p_func100(0xc3e968a1U, 0xa0e12941U, 0x30a4b25eU, 0x674fcc09U); + HW_SCE_p_func103(); + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c200104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_9CH, 0x80010000U); + WR1_PROG(REG_00H, 0x03410005U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + WR1_PROG(REG_00H, 0x0001000dU); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_94H, 0x000034c0U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x000000f4U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0x291a0ca3U, 0x28a82454U, 0x476b77b1U, 0xf6c53132U); + HW_SCE_p_func043(); + + WR1_PROG(REG_94H, 0x0000b4c0U); + WR1_PROG(REG_94H, 0x00000017U); + + WR1_PROG(REG_14H, 0x000000a7U); + WR1_PROG(REG_9CH, 0x800100e0U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x000000f4U)); + WR1_PROG(REG_24H, 0x00000000U); + + HW_SCE_p_func101(0x7897f6a1U, 0x43fbffa6U, 0xeb4ac5e4U, 0x16faea81U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0x2b316d31U, 0xd922edaaU, 0x79ce9339U, 0x46be6298U); + WR1_PROG(REG_B0H, 0x00001832U); + + WR1_PROG(REG_D4H, 0x40000100U); + WR1_PROG(REG_D0H, 0xe7009d07U); + WR1_PROG(REG_00H, 0x00430021U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_08H, 0x00001022U); + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_PrivKeyIndex[1]); + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_PrivKeyIndex[5]); + + HW_SCE_p_func100(0xce5dbb96U, 0xae78b31cU, 0x1cf6e125U, 0x835302f5U); + WR1_PROG(REG_14H, 0x000000a1U); + WR1_PROG(REG_D0H, 0x0c000104U); + WAIT_STS(REG_14H, 31, 1); + WR1_PROG(REG_2CH, change_endian_long(0x00000000U)); + + WR1_PROG(REG_D4H, 0x40000000U); + WR1_PROG(REG_D0H, 0x09108105U); + WR1_PROG(REG_00H, 0x00410011U); + WAIT_STS(REG_04H, 30, 0); + WR1_PROG(REG_40H, 0x00001800U); + + WR1_PROG(REG_08H, 0x00001012U); + WAIT_STS(REG_08H, 30, 1); + RD4_ADDR(REG_2CH, &OutData_PrivKeyIndex[9]); + + HW_SCE_p_func100(0x4b4722e5U, 0x76edacf2U, 0xbba4e3d1U, 0xa5d9f0c8U); + WR1_PROG(REG_9CH, 0x81010000U); + WR1_PROG(REG_08H, 0x00005006U); + WAIT_STS(REG_08H, 30, 1); + RD1_ADDR(REG_2CH, &OutData_PrivKeyIndex[0]); + + HW_SCE_p_func101(0x8844ca5aU, 0x1aa078c2U, 0xf1c8b4dcU, 0x476d2b6cU); + } + else + { + HW_SCE_p_func100(0x2c009193U, 0x29108391U, 0x139489cdU, 0x1e5f9a02U); + WR1_PROG(REG_B0H, 0x00001832U); + WR1_PROG(REG_08H, 0x00006022U); + WAIT_STS(REG_08H, 30, 1); + RD8_ADDR(REG_2CH, &OutData_PrivKey[0]); + + HW_SCE_p_func101(0x451b2d83U, 0xd6e99100U, 0xc636adf1U, 0x71b67122U); + } + + HW_SCE_p_func100(0xe5a0067bU, 0xccd9c8efU, 0x3d6bc5e4U, 0x24eacce3U); + WR1_PROG(REG_B0H, 0x00001828U); + WR1_PROG(REG_08H, 0x00006022U); + WAIT_STS(REG_08H, 30, 1); + RD8_ADDR(REG_2CH, &OutData_PubKey[0]); + + HW_SCE_p_func100(0x1b40fbfeU, 0x83c7061eU, 0x6aca4c74U, 0x6e5e3705U); + WR1_PROG(REG_B0H, 0x0000182dU); + WR1_PROG(REG_08H, 0x00006022U); + WAIT_STS(REG_08H, 30, 1); + RD8_ADDR(REG_2CH, &OutData_PubKey[8]); + + HW_SCE_p_func102(0x35653737U, 0x731875a7U, 0xf3dd8235U, 0x5c852523U); + WR1_PROG(REG_6CH, 0x00000040U); + WAIT_STS(REG_20H, 12, 0); + + return FSP_SUCCESS; + } + } +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/s_flash.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/s_flash.c new file mode 100644 index 000000000..b5dd38731 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/primitive/s_flash.c @@ -0,0 +1,81 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hw_sce_ra_private.h" + +uint32_t const S_FLASH[] = +{ +#ifndef __ARMEB__ /* Little endian */ + + 0x78f4b6c2, 0x78685c18, 0x732040f3, 0xe0b48135, + 0x4c22edd9, 0x583303a4, 0x3c4d10db, 0x7a77990e, + 0xce6b9eb0, 0x1f2162ee, 0x2085cddc, 0x98a87fa1, + 0x371ac559, 0xada5788c, 0x1b749abf, 0x763f1f1f, + 0x05033c7f, 0x51d3fe9e, 0x70ea474b, 0xe0faa0e7, + 0xf450e26f, 0xd8b69aee, 0x53e439ca, 0xf433dccc, + 0xa09325cc, 0x5a512c4e, 0x05750aa1, 0x93659e61, + 0xdbed13e3, 0x6b335ab4, 0xb4b49cfc, 0xc653259d, + 0xd3cd2495, 0x1dd1300e, 0xcfbff156, 0x46549780, + 0x971e00bb, 0x599a62ab, 0xf8cf3d09, 0x8bbeb944, + 0x100facb5, 0x60397a36, 0x34322666, 0xc82b3825, + 0x96dc194b, 0x44d02361, 0x01830527, 0x61799f40, + 0xf50a19f3, 0x0fefbe0c, 0x6fe4cbcf, 0x481c6e67, + 0x821ab352, 0x1fa152f7, 0xbd8caf6c, 0xec547313, + 0x4dc0e1d6, 0x619efae1, 0xecb87614, 0x8230f32d, + 0xe2aceb53, 0x40a003fe, 0x0e565b47, 0xf36b7900, + 0xb96b1340, 0x426d3f90, 0x4651246b, 0xab7d01df, + 0x1ce4467f, 0x65fb863e, 0x48817e46, 0x46024d7c, + 0x3ff1675e, 0xf75a637d, 0xd6514bf8, 0x562c6eb6, + 0x93e25766, 0xc785473d, 0x8a57edfe, 0x50344263, + 0xac9bb11b, 0x833098c0, 0x7c898293, 0x0e216356, + 0xb678fb85, 0x363b842e, 0xb649d49f, 0xfc9c09d4, + 0x739fb4e3, 0x02e5708e, 0x43e3ead4, 0xab4e31f9, + 0x7141339b, 0xa5967984, 0xdb970930, 0x3eeb8cbc, + 0xab09e5cf, 0x3ae2cb2b, 0xb0576373, 0xd395100e, + 0xe6be37c1, 0x323cf991, 0xc39b2e1f, 0xac9aebd2, + 0x38f6da2e, 0xfec85777, 0xbfc4d3ed, 0xbce11ab1, + 0x67e7b9a4, 0x4d991dfd, 0xdfcd9385, 0x887c11dd, + 0xe88efffc, 0xdce19885, 0xa49c6b75, 0xb7cf4b21, + 0xb598728c, 0x5249899c, 0xf5d06649, 0x2532804c, + 0x89092a04, 0x66b0e857, 0x178b5c2c, 0x825bd5a6, + 0x3cc67a1d, 0xd386c3b4, 0xd40628e0, 0x58a34df2 + +#else /* Big endian */ + 0xc2b6f478, 0x185c6878, 0xf3402073, 0x3581b4e0, + 0xd9ed224c, 0xa4033358, 0xdb104d3c, 0x0e99777a, + 0xb09e6bce, 0xee62211f, 0xdccd8520, 0xa17fa898, + 0x59c51a37, 0x8c78a5ad, 0xbf9a741b, 0x1f1f3f76, + 0x7f3c0305, 0x9efed351, 0x4b47ea70, 0xe7a0fae0, + 0x6fe250f4, 0xee9ab6d8, 0xca39e453, 0xccdc33f4, + 0xcc2593a0, 0x4e2c515a, 0xa10a7505, 0x619e6593, + 0xe313eddb, 0xb45a336b, 0xfc9cb4b4, 0x9d2553c6, + 0x9524cdd3, 0x0e30d11d, 0x56f1bfcf, 0x80975446, + 0xbb001e97, 0xab629a59, 0x093dcff8, 0x44b9be8b, + 0xb5ac0f10, 0x367a3960, 0x66263234, 0x25382bc8, + 0x4b19dc96, 0x6123d044, 0x27058301, 0x409f7961, + 0xf3190af5, 0x0cbeef0f, 0xcfcbe46f, 0x676e1c48, + 0x52b31a82, 0xf752a11f, 0x6caf8cbd, 0x137354ec, + 0xd6e1c04d, 0xe1fa9e61, 0x1476b8ec, 0x2df33082, + 0x53ebace2, 0xfe03a040, 0x475b560e, 0x00796bf3, + 0x40136bb9, 0x903f6d42, 0x6b245146, 0xdf017dab, + 0x7f46e41c, 0x3e86fb65, 0x467e8148, 0x7c4d0246, + 0x5e67f13f, 0x7d635af7, 0xf84b51d6, 0xb66e2c56, + 0x6657e293, 0x3d4785c7, 0xfeed578a, 0x63423450, + 0x1bb19bac, 0xc0983083, 0x9382897c, 0x5663210e, + 0x85fb78b6, 0x2e843b36, 0x9fd449b6, 0xd4099cfc, + 0xe3b49f73, 0x8e70e502, 0xd4eae343, 0xf9314eab, + 0x9b334171, 0x847996a5, 0x300997db, 0xbc8ceb3e, + 0xcfe509ab, 0x2bcbe23a, 0x736357b0, 0x0e1095d3, + 0xc137bee6, 0x91f93c32, 0x1f2e9bc3, 0xd2eb9aac, + 0x2edaf638, 0x7757c8fe, 0xedd3c4bf, 0xb11ae1bc, + 0xa4b9e767, 0xfd1d994d, 0x8593cddf, 0xdd117c88, + 0xfcff8ee8, 0x8598e1dc, 0x756b9ca4, 0x214bcfb7, + 0x8c7298b5, 0x9c894952, 0x4966d0f5, 0x4c803225, + 0x042a0989, 0x57e8b066, 0x2c5c8b17, 0xa6d55b82, + 0x1d7ac63c, 0xb4c386d3, 0xe02806d4, 0xf24da358 +#endif /* defined __ARMEB__ */ +}; + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/private/inc/SCE_ProcCommon.h b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/private/inc/SCE_ProcCommon.h new file mode 100644 index 000000000..a550903d0 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/private/inc/SCE_ProcCommon.h @@ -0,0 +1,93089 @@ +/*********************************************************************************************************************** + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef __SCE_ProcCommon_h__ +#define __SCE_ProcCommon_h__ + +#include + +#include "bsp_api.h" /* For Crypto Error codes */ +#include "SCE_module.h" + +/* ================================================================================ */ +/* ================ SCE ================ */ +/* ================================================================================ */ + +/** + * @brief Trusted Security IP (SCE) + */ +typedef struct +{ + union + { + __IOM uint32_t REG_00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_00H_b; + }; + union + { + __IOM uint32_t REG_04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_04H_b; + }; + union + { + __IOM uint32_t REG_08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_08H_b; + }; + union + { + __IOM uint32_t REG_0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_0CH_b; + }; + union + { + __IOM uint32_t REG_10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10H_b; + }; + union + { + __IOM uint32_t REG_14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14H_b; + }; + union + { + __IOM uint32_t REG_18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18H_b; + }; + union + { + __IOM uint32_t REG_1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CH_b; + }; + union + { + __IOM uint32_t REG_20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20H_b; + }; + union + { + __IOM uint32_t REG_24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24H_b; + }; + union + { + __IOM uint32_t REG_28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_28H_b; + }; + union + { + __IOM uint32_t REG_2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2CH_b; + }; + union + { + __IOM uint32_t REG_30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_30H_b; + }; + union + { + __IOM uint32_t REG_34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_34H_b; + }; + union + { + __IOM uint32_t REG_38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_38H_b; + }; + union + { + __IOM uint32_t REG_3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3CH_b; + }; + union + { + __IOM uint32_t REG_40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_40H_b; + }; + union + { + __IOM uint32_t REG_44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_44H_b; + }; + union + { + __IOM uint32_t REG_48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_48H_b; + }; + union + { + __IOM uint32_t REG_4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4CH_b; + }; + union + { + __IOM uint32_t REG_50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_50H_b; + }; + union + { + __IOM uint32_t REG_54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_54H_b; + }; + union + { + __IOM uint32_t REG_58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_58H_b; + }; + union + { + __IOM uint32_t REG_5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5CH_b; + }; + union + { + __IOM uint32_t REG_60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_60H_b; + }; + union + { + __IOM uint32_t REG_64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_64H_b; + }; + union + { + __IOM uint32_t REG_68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_68H_b; + }; + union + { + __IOM uint32_t REG_6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6CH_b; + }; + union + { + __IOM uint32_t REG_70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_70H_b; + }; + union + { + __IOM uint32_t REG_74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_74H_b; + }; + union + { + __IOM uint32_t REG_78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_78H_b; + }; + union + { + __IOM uint32_t REG_7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7CH_b; + }; + union + { + __IOM uint32_t REG_80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_80H_b; + }; + union + { + __IOM uint32_t REG_84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_84H_b; + }; + union + { + __IOM uint32_t REG_88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_88H_b; + }; + union + { + __IOM uint32_t REG_8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8CH_b; + }; + union + { + __IOM uint32_t REG_90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_90H_b; + }; + union + { + __IOM uint32_t REG_94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_94H_b; + }; + union + { + __IOM uint32_t REG_98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_98H_b; + }; + union + { + __IOM uint32_t REG_9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9CH_b; + }; + union + { + __IOM uint32_t REG_A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A0H_b; + }; + union + { + __IOM uint32_t REG_A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A4H_b; + }; + union + { + __IOM uint32_t REG_A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A8H_b; + }; + union + { + __IOM uint32_t REG_ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_ACH_b; + }; + union + { + __IOM uint32_t REG_B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B0H_b; + }; + union + { + __IOM uint32_t REG_B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B4H_b; + }; + union + { + __IOM uint32_t REG_B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B8H_b; + }; + union + { + __IOM uint32_t REG_BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BCH_b; + }; + union + { + __IOM uint32_t REG_C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C0H_b; + }; + union + { + __IOM uint32_t REG_C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C4H_b; + }; + union + { + __IOM uint32_t REG_C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C8H_b; + }; + union + { + __IOM uint32_t REG_CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CCH_b; + }; + union + { + __IOM uint32_t REG_D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D0H_b; + }; + union + { + __IOM uint32_t REG_D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D4H_b; + }; + union + { + __IOM uint32_t REG_D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D8H_b; + }; + union + { + __IOM uint32_t REG_DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DCH_b; + }; + union + { + __IOM uint32_t REG_E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E0H_b; + }; + union + { + __IOM uint32_t REG_E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E4H_b; + }; + union + { + __IOM uint32_t REG_E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E8H_b; + }; + union + { + __IOM uint32_t REG_ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_ECH_b; + }; + union + { + __IOM uint32_t REG_F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F0H_b; + }; + union + { + __IOM uint32_t REG_F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F4H_b; + }; + union + { + __IOM uint32_t REG_F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F8H_b; + }; + union + { + __IOM uint32_t REG_FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FCH_b; + }; + union + { + __IOM uint32_t REG_100H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_100H_b; + }; + union + { + __IOM uint32_t REG_104H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_104H_b; + }; + union + { + __IOM uint32_t REG_108H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_108H_b; + }; + union + { + __IOM uint32_t REG_10CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10CH_b; + }; + union + { + __IOM uint32_t REG_110H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_110H_b; + }; + union + { + __IOM uint32_t REG_114H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_114H_b; + }; + union + { + __IOM uint32_t REG_118H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_118H_b; + }; + union + { + __IOM uint32_t REG_11CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11CH_b; + }; + union + { + __IOM uint32_t REG_120H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_120H_b; + }; + union + { + __IOM uint32_t REG_124H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_124H_b; + }; + union + { + __IOM uint32_t REG_128H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_128H_b; + }; + union + { + __IOM uint32_t REG_12CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12CH_b; + }; + union + { + __IOM uint32_t REG_130H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_130H_b; + }; + union + { + __IOM uint32_t REG_134H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_134H_b; + }; + union + { + __IOM uint32_t REG_138H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_138H_b; + }; + union + { + __IOM uint32_t REG_13CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13CH_b; + }; + union + { + __IOM uint32_t REG_140H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_140H_b; + }; + union + { + __IOM uint32_t REG_144H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_144H_b; + }; + union + { + __IOM uint32_t REG_148H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_148H_b; + }; + union + { + __IOM uint32_t REG_14CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14CH_b; + }; + union + { + __IOM uint32_t REG_150H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_150H_b; + }; + union + { + __IOM uint32_t REG_154H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_154H_b; + }; + union + { + __IOM uint32_t REG_158H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_158H_b; + }; + union + { + __IOM uint32_t REG_15CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15CH_b; + }; + union + { + __IOM uint32_t REG_160H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_160H_b; + }; + union + { + __IOM uint32_t REG_164H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_164H_b; + }; + union + { + __IOM uint32_t REG_168H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_168H_b; + }; + union + { + __IOM uint32_t REG_16CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16CH_b; + }; + union + { + __IOM uint32_t REG_170H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_170H_b; + }; + union + { + __IOM uint32_t REG_174H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_174H_b; + }; + union + { + __IOM uint32_t REG_178H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_178H_b; + }; + union + { + __IOM uint32_t REG_17CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17CH_b; + }; + union + { + __IOM uint32_t REG_180H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_180H_b; + }; + union + { + __IOM uint32_t REG_184H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_184H_b; + }; + union + { + __IOM uint32_t REG_188H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_188H_b; + }; + union + { + __IOM uint32_t REG_18CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18CH_b; + }; + union + { + __IOM uint32_t REG_190H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_190H_b; + }; + union + { + __IOM uint32_t REG_194H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_194H_b; + }; + union + { + __IOM uint32_t REG_198H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_198H_b; + }; + union + { + __IOM uint32_t REG_19CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19CH_b; + }; + union + { + __IOM uint32_t REG_1A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A0H_b; + }; + union + { + __IOM uint32_t REG_1A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A4H_b; + }; + union + { + __IOM uint32_t REG_1A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A8H_b; + }; + union + { + __IOM uint32_t REG_1ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1ACH_b; + }; + union + { + __IOM uint32_t REG_1B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B0H_b; + }; + union + { + __IOM uint32_t REG_1B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B4H_b; + }; + union + { + __IOM uint32_t REG_1B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B8H_b; + }; + union + { + __IOM uint32_t REG_1BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BCH_b; + }; + union + { + __IOM uint32_t REG_1C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C0H_b; + }; + union + { + __IOM uint32_t REG_1C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C4H_b; + }; + union + { + __IOM uint32_t REG_1C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C8H_b; + }; + union + { + __IOM uint32_t REG_1CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CCH_b; + }; + union + { + __IOM uint32_t REG_1D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D0H_b; + }; + union + { + __IOM uint32_t REG_1D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D4H_b; + }; + union + { + __IOM uint32_t REG_1D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D8H_b; + }; + union + { + __IOM uint32_t REG_1DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DCH_b; + }; + union + { + __IOM uint32_t REG_1E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E0H_b; + }; + union + { + __IOM uint32_t REG_1E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E4H_b; + }; + union + { + __IOM uint32_t REG_1E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E8H_b; + }; + union + { + __IOM uint32_t REG_1ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1ECH_b; + }; + union + { + __IOM uint32_t REG_1F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F0H_b; + }; + union + { + __IOM uint32_t REG_1F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F4H_b; + }; + union + { + __IOM uint32_t REG_1F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F8H_b; + }; + union + { + __IOM uint32_t REG_1FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FCH_b; + }; + union + { + __IOM uint32_t REG_200H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_200H_b; + }; + union + { + __IOM uint32_t REG_204H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_204H_b; + }; + union + { + __IOM uint32_t REG_208H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_208H_b; + }; + union + { + __IOM uint32_t REG_20CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20CH_b; + }; + union + { + __IOM uint32_t REG_210H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_210H_b; + }; + union + { + __IOM uint32_t REG_214H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_214H_b; + }; + union + { + __IOM uint32_t REG_218H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_218H_b; + }; + union + { + __IOM uint32_t REG_21CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21CH_b; + }; + union + { + __IOM uint32_t REG_220H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_220H_b; + }; + union + { + __IOM uint32_t REG_224H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_224H_b; + }; + union + { + __IOM uint32_t REG_228H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_228H_b; + }; + union + { + __IOM uint32_t REG_22CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22CH_b; + }; + union + { + __IOM uint32_t REG_230H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_230H_b; + }; + union + { + __IOM uint32_t REG_234H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_234H_b; + }; + union + { + __IOM uint32_t REG_238H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_238H_b; + }; + union + { + __IOM uint32_t REG_23CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23CH_b; + }; + union + { + __IOM uint32_t REG_240H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_240H_b; + }; + union + { + __IOM uint32_t REG_244H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_244H_b; + }; + union + { + __IOM uint32_t REG_248H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_248H_b; + }; + union + { + __IOM uint32_t REG_24CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24CH_b; + }; + union + { + __IOM uint32_t REG_250H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_250H_b; + }; + union + { + __IOM uint32_t REG_254H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_254H_b; + }; + union + { + __IOM uint32_t REG_258H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_258H_b; + }; + union + { + __IOM uint32_t REG_25CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_25CH_b; + }; + union + { + __IOM uint32_t REG_260H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_260H_b; + }; + union + { + __IOM uint32_t REG_264H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_264H_b; + }; + union + { + __IOM uint32_t REG_268H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_268H_b; + }; + union + { + __IOM uint32_t REG_26CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_26CH_b; + }; + union + { + __IOM uint32_t REG_270H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_270H_b; + }; + union + { + __IOM uint32_t REG_274H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_274H_b; + }; + union + { + __IOM uint32_t REG_278H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_278H_b; + }; + union + { + __IOM uint32_t REG_27CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_27CH_b; + }; + union + { + __IOM uint32_t REG_280H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_280H_b; + }; + union + { + __IOM uint32_t REG_284H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_284H_b; + }; + union + { + __IOM uint32_t REG_288H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_288H_b; + }; + union + { + __IOM uint32_t REG_28CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_28CH_b; + }; + union + { + __IOM uint32_t REG_290H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_290H_b; + }; + union + { + __IOM uint32_t REG_294H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_294H_b; + }; + union + { + __IOM uint32_t REG_298H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_298H_b; + }; + union + { + __IOM uint32_t REG_29CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_29CH_b; + }; + union + { + __IOM uint32_t REG_2A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2A0H_b; + }; + union + { + __IOM uint32_t REG_2A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2A4H_b; + }; + union + { + __IOM uint32_t REG_2A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2A8H_b; + }; + union + { + __IOM uint32_t REG_2ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2ACH_b; + }; + union + { + __IOM uint32_t REG_2B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2B0H_b; + }; + union + { + __IOM uint32_t REG_2B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2B4H_b; + }; + union + { + __IOM uint32_t REG_2B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2B8H_b; + }; + union + { + __IOM uint32_t REG_2BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2BCH_b; + }; + union + { + __IOM uint32_t REG_2C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2C0H_b; + }; + union + { + __IOM uint32_t REG_2C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2C4H_b; + }; + union + { + __IOM uint32_t REG_2C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2C8H_b; + }; + union + { + __IOM uint32_t REG_2CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2CCH_b; + }; + union + { + __IOM uint32_t REG_2D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2D0H_b; + }; + union + { + __IOM uint32_t REG_2D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2D4H_b; + }; + union + { + __IOM uint32_t REG_2D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2D8H_b; + }; + union + { + __IOM uint32_t REG_2DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2DCH_b; + }; + union + { + __IOM uint32_t REG_2E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2E0H_b; + }; + union + { + __IOM uint32_t REG_2E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2E4H_b; + }; + union + { + __IOM uint32_t REG_2E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2E8H_b; + }; + union + { + __IOM uint32_t REG_2ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2ECH_b; + }; + union + { + __IOM uint32_t REG_2F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2F0H_b; + }; + union + { + __IOM uint32_t REG_2F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2F4H_b; + }; + union + { + __IOM uint32_t REG_2F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2F8H_b; + }; + union + { + __IOM uint32_t REG_2FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2FCH_b; + }; + union + { + __IOM uint32_t REG_300H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_300H_b; + }; + union + { + __IOM uint32_t REG_304H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_304H_b; + }; + union + { + __IOM uint32_t REG_308H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_308H_b; + }; + union + { + __IOM uint32_t REG_30CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_30CH_b; + }; + union + { + __IOM uint32_t REG_310H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_310H_b; + }; + union + { + __IOM uint32_t REG_314H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_314H_b; + }; + union + { + __IOM uint32_t REG_318H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_318H_b; + }; + union + { + __IOM uint32_t REG_31CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_31CH_b; + }; + union + { + __IOM uint32_t REG_320H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_320H_b; + }; + union + { + __IOM uint32_t REG_324H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_324H_b; + }; + union + { + __IOM uint32_t REG_328H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_328H_b; + }; + union + { + __IOM uint32_t REG_32CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_32CH_b; + }; + union + { + __IOM uint32_t REG_330H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_330H_b; + }; + union + { + __IOM uint32_t REG_334H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_334H_b; + }; + union + { + __IOM uint32_t REG_338H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_338H_b; + }; + union + { + __IOM uint32_t REG_33CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_33CH_b; + }; + union + { + __IOM uint32_t REG_340H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_340H_b; + }; + union + { + __IOM uint32_t REG_344H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_344H_b; + }; + union + { + __IOM uint32_t REG_348H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_348H_b; + }; + union + { + __IOM uint32_t REG_34CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_34CH_b; + }; + union + { + __IOM uint32_t REG_350H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_350H_b; + }; + union + { + __IOM uint32_t REG_354H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_354H_b; + }; + union + { + __IOM uint32_t REG_358H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_358H_b; + }; + union + { + __IOM uint32_t REG_35CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_35CH_b; + }; + union + { + __IOM uint32_t REG_360H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_360H_b; + }; + union + { + __IOM uint32_t REG_364H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_364H_b; + }; + union + { + __IOM uint32_t REG_368H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_368H_b; + }; + union + { + __IOM uint32_t REG_36CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_36CH_b; + }; + union + { + __IOM uint32_t REG_370H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_370H_b; + }; + union + { + __IOM uint32_t REG_374H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_374H_b; + }; + union + { + __IOM uint32_t REG_378H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_378H_b; + }; + union + { + __IOM uint32_t REG_37CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_37CH_b; + }; + union + { + __IOM uint32_t REG_380H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_380H_b; + }; + union + { + __IOM uint32_t REG_384H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_384H_b; + }; + union + { + __IOM uint32_t REG_388H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_388H_b; + }; + union + { + __IOM uint32_t REG_38CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_38CH_b; + }; + union + { + __IOM uint32_t REG_390H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_390H_b; + }; + union + { + __IOM uint32_t REG_394H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_394H_b; + }; + union + { + __IOM uint32_t REG_398H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_398H_b; + }; + union + { + __IOM uint32_t REG_39CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_39CH_b; + }; + union + { + __IOM uint32_t REG_3A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3A0H_b; + }; + union + { + __IOM uint32_t REG_3A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3A4H_b; + }; + union + { + __IOM uint32_t REG_3A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3A8H_b; + }; + union + { + __IOM uint32_t REG_3ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3ACH_b; + }; + union + { + __IOM uint32_t REG_3B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3B0H_b; + }; + union + { + __IOM uint32_t REG_3B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3B4H_b; + }; + union + { + __IOM uint32_t REG_3B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3B8H_b; + }; + union + { + __IOM uint32_t REG_3BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3BCH_b; + }; + union + { + __IOM uint32_t REG_3C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3C0H_b; + }; + union + { + __IOM uint32_t REG_3C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3C4H_b; + }; + union + { + __IOM uint32_t REG_3C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3C8H_b; + }; + union + { + __IOM uint32_t REG_3CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3CCH_b; + }; + union + { + __IOM uint32_t REG_3D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3D0H_b; + }; + union + { + __IOM uint32_t REG_3D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3D4H_b; + }; + union + { + __IOM uint32_t REG_3D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3D8H_b; + }; + union + { + __IOM uint32_t REG_3DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3DCH_b; + }; + union + { + __IOM uint32_t REG_3E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3E0H_b; + }; + union + { + __IOM uint32_t REG_3E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3E4H_b; + }; + union + { + __IOM uint32_t REG_3E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3E8H_b; + }; + union + { + __IOM uint32_t REG_3ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3ECH_b; + }; + union + { + __IOM uint32_t REG_3F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3F0H_b; + }; + union + { + __IOM uint32_t REG_3F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3F4H_b; + }; + union + { + __IOM uint32_t REG_3F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3F8H_b; + }; + union + { + __IOM uint32_t REG_3FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3FCH_b; + }; + union + { + __IOM uint32_t REG_400H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_400H_b; + }; + union + { + __IOM uint32_t REG_404H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_404H_b; + }; + union + { + __IOM uint32_t REG_408H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_408H_b; + }; + union + { + __IOM uint32_t REG_40CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_40CH_b; + }; + union + { + __IOM uint32_t REG_410H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_410H_b; + }; + union + { + __IOM uint32_t REG_414H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_414H_b; + }; + union + { + __IOM uint32_t REG_418H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_418H_b; + }; + union + { + __IOM uint32_t REG_41CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_41CH_b; + }; + union + { + __IOM uint32_t REG_420H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_420H_b; + }; + union + { + __IOM uint32_t REG_424H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_424H_b; + }; + union + { + __IOM uint32_t REG_428H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_428H_b; + }; + union + { + __IOM uint32_t REG_42CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_42CH_b; + }; + union + { + __IOM uint32_t REG_430H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_430H_b; + }; + union + { + __IOM uint32_t REG_434H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_434H_b; + }; + union + { + __IOM uint32_t REG_438H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_438H_b; + }; + union + { + __IOM uint32_t REG_43CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_43CH_b; + }; + union + { + __IOM uint32_t REG_440H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_440H_b; + }; + union + { + __IOM uint32_t REG_444H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_444H_b; + }; + union + { + __IOM uint32_t REG_448H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_448H_b; + }; + union + { + __IOM uint32_t REG_44CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_44CH_b; + }; + union + { + __IOM uint32_t REG_450H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_450H_b; + }; + union + { + __IOM uint32_t REG_454H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_454H_b; + }; + union + { + __IOM uint32_t REG_458H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_458H_b; + }; + union + { + __IOM uint32_t REG_45CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_45CH_b; + }; + union + { + __IOM uint32_t REG_460H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_460H_b; + }; + union + { + __IOM uint32_t REG_464H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_464H_b; + }; + union + { + __IOM uint32_t REG_468H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_468H_b; + }; + union + { + __IOM uint32_t REG_46CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_46CH_b; + }; + union + { + __IOM uint32_t REG_470H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_470H_b; + }; + union + { + __IOM uint32_t REG_474H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_474H_b; + }; + union + { + __IOM uint32_t REG_478H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_478H_b; + }; + union + { + __IOM uint32_t REG_47CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_47CH_b; + }; + union + { + __IOM uint32_t REG_480H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_480H_b; + }; + union + { + __IOM uint32_t REG_484H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_484H_b; + }; + union + { + __IOM uint32_t REG_488H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_488H_b; + }; + union + { + __IOM uint32_t REG_48CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_48CH_b; + }; + union + { + __IOM uint32_t REG_490H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_490H_b; + }; + union + { + __IOM uint32_t REG_494H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_494H_b; + }; + union + { + __IOM uint32_t REG_498H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_498H_b; + }; + union + { + __IOM uint32_t REG_49CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_49CH_b; + }; + union + { + __IOM uint32_t REG_4A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4A0H_b; + }; + union + { + __IOM uint32_t REG_4A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4A4H_b; + }; + union + { + __IOM uint32_t REG_4A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4A8H_b; + }; + union + { + __IOM uint32_t REG_4ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4ACH_b; + }; + union + { + __IOM uint32_t REG_4B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4B0H_b; + }; + union + { + __IOM uint32_t REG_4B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4B4H_b; + }; + union + { + __IOM uint32_t REG_4B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4B8H_b; + }; + union + { + __IOM uint32_t REG_4BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4BCH_b; + }; + union + { + __IOM uint32_t REG_4C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4C0H_b; + }; + union + { + __IOM uint32_t REG_4C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4C4H_b; + }; + union + { + __IOM uint32_t REG_4C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4C8H_b; + }; + union + { + __IOM uint32_t REG_4CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4CCH_b; + }; + union + { + __IOM uint32_t REG_4D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4D0H_b; + }; + union + { + __IOM uint32_t REG_4D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4D4H_b; + }; + union + { + __IOM uint32_t REG_4D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4D8H_b; + }; + union + { + __IOM uint32_t REG_4DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4DCH_b; + }; + union + { + __IOM uint32_t REG_4E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4E0H_b; + }; + union + { + __IOM uint32_t REG_4E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4E4H_b; + }; + union + { + __IOM uint32_t REG_4E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4E8H_b; + }; + union + { + __IOM uint32_t REG_4ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4ECH_b; + }; + union + { + __IOM uint32_t REG_4F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4F0H_b; + }; + union + { + __IOM uint32_t REG_4F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4F4H_b; + }; + union + { + __IOM uint32_t REG_4F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4F8H_b; + }; + union + { + __IOM uint32_t REG_4FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4FCH_b; + }; + union + { + __IOM uint32_t REG_500H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_500H_b; + }; + union + { + __IOM uint32_t REG_504H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_504H_b; + }; + union + { + __IOM uint32_t REG_508H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_508H_b; + }; + union + { + __IOM uint32_t REG_50CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_50CH_b; + }; + union + { + __IOM uint32_t REG_510H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_510H_b; + }; + union + { + __IOM uint32_t REG_514H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_514H_b; + }; + union + { + __IOM uint32_t REG_518H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_518H_b; + }; + union + { + __IOM uint32_t REG_51CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_51CH_b; + }; + union + { + __IOM uint32_t REG_520H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_520H_b; + }; + union + { + __IOM uint32_t REG_524H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_524H_b; + }; + union + { + __IOM uint32_t REG_528H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_528H_b; + }; + union + { + __IOM uint32_t REG_52CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_52CH_b; + }; + union + { + __IOM uint32_t REG_530H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_530H_b; + }; + union + { + __IOM uint32_t REG_534H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_534H_b; + }; + union + { + __IOM uint32_t REG_538H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_538H_b; + }; + union + { + __IOM uint32_t REG_53CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_53CH_b; + }; + union + { + __IOM uint32_t REG_540H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_540H_b; + }; + union + { + __IOM uint32_t REG_544H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_544H_b; + }; + union + { + __IOM uint32_t REG_548H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_548H_b; + }; + union + { + __IOM uint32_t REG_54CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_54CH_b; + }; + union + { + __IOM uint32_t REG_550H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_550H_b; + }; + union + { + __IOM uint32_t REG_554H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_554H_b; + }; + union + { + __IOM uint32_t REG_558H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_558H_b; + }; + union + { + __IOM uint32_t REG_55CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_55CH_b; + }; + union + { + __IOM uint32_t REG_560H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_560H_b; + }; + union + { + __IOM uint32_t REG_564H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_564H_b; + }; + union + { + __IOM uint32_t REG_568H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_568H_b; + }; + union + { + __IOM uint32_t REG_56CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_56CH_b; + }; + union + { + __IOM uint32_t REG_570H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_570H_b; + }; + union + { + __IOM uint32_t REG_574H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_574H_b; + }; + union + { + __IOM uint32_t REG_578H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_578H_b; + }; + union + { + __IOM uint32_t REG_57CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_57CH_b; + }; + union + { + __IOM uint32_t REG_580H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_580H_b; + }; + union + { + __IOM uint32_t REG_584H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_584H_b; + }; + union + { + __IOM uint32_t REG_588H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_588H_b; + }; + union + { + __IOM uint32_t REG_58CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_58CH_b; + }; + union + { + __IOM uint32_t REG_590H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_590H_b; + }; + union + { + __IOM uint32_t REG_594H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_594H_b; + }; + union + { + __IOM uint32_t REG_598H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_598H_b; + }; + union + { + __IOM uint32_t REG_59CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_59CH_b; + }; + union + { + __IOM uint32_t REG_5A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5A0H_b; + }; + union + { + __IOM uint32_t REG_5A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5A4H_b; + }; + union + { + __IOM uint32_t REG_5A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5A8H_b; + }; + union + { + __IOM uint32_t REG_5ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5ACH_b; + }; + union + { + __IOM uint32_t REG_5B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5B0H_b; + }; + union + { + __IOM uint32_t REG_5B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5B4H_b; + }; + union + { + __IOM uint32_t REG_5B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5B8H_b; + }; + union + { + __IOM uint32_t REG_5BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5BCH_b; + }; + union + { + __IOM uint32_t REG_5C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5C0H_b; + }; + union + { + __IOM uint32_t REG_5C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5C4H_b; + }; + union + { + __IOM uint32_t REG_5C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5C8H_b; + }; + union + { + __IOM uint32_t REG_5CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5CCH_b; + }; + union + { + __IOM uint32_t REG_5D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5D0H_b; + }; + union + { + __IOM uint32_t REG_5D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5D4H_b; + }; + union + { + __IOM uint32_t REG_5D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5D8H_b; + }; + union + { + __IOM uint32_t REG_5DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5DCH_b; + }; + union + { + __IOM uint32_t REG_5E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5E0H_b; + }; + union + { + __IOM uint32_t REG_5E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5E4H_b; + }; + union + { + __IOM uint32_t REG_5E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5E8H_b; + }; + union + { + __IOM uint32_t REG_5ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5ECH_b; + }; + union + { + __IOM uint32_t REG_5F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5F0H_b; + }; + union + { + __IOM uint32_t REG_5F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5F4H_b; + }; + union + { + __IOM uint32_t REG_5F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5F8H_b; + }; + union + { + __IOM uint32_t REG_5FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5FCH_b; + }; + union + { + __IOM uint32_t REG_600H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_600H_b; + }; + union + { + __IOM uint32_t REG_604H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_604H_b; + }; + union + { + __IOM uint32_t REG_608H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_608H_b; + }; + union + { + __IOM uint32_t REG_60CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_60CH_b; + }; + union + { + __IOM uint32_t REG_610H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_610H_b; + }; + union + { + __IOM uint32_t REG_614H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_614H_b; + }; + union + { + __IOM uint32_t REG_618H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_618H_b; + }; + union + { + __IOM uint32_t REG_61CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_61CH_b; + }; + union + { + __IOM uint32_t REG_620H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_620H_b; + }; + union + { + __IOM uint32_t REG_624H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_624H_b; + }; + union + { + __IOM uint32_t REG_628H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_628H_b; + }; + union + { + __IOM uint32_t REG_62CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_62CH_b; + }; + union + { + __IOM uint32_t REG_630H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_630H_b; + }; + union + { + __IOM uint32_t REG_634H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_634H_b; + }; + union + { + __IOM uint32_t REG_638H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_638H_b; + }; + union + { + __IOM uint32_t REG_63CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_63CH_b; + }; + union + { + __IOM uint32_t REG_640H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_640H_b; + }; + union + { + __IOM uint32_t REG_644H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_644H_b; + }; + union + { + __IOM uint32_t REG_648H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_648H_b; + }; + union + { + __IOM uint32_t REG_64CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_64CH_b; + }; + union + { + __IOM uint32_t REG_650H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_650H_b; + }; + union + { + __IOM uint32_t REG_654H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_654H_b; + }; + union + { + __IOM uint32_t REG_658H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_658H_b; + }; + union + { + __IOM uint32_t REG_65CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_65CH_b; + }; + union + { + __IOM uint32_t REG_660H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_660H_b; + }; + union + { + __IOM uint32_t REG_664H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_664H_b; + }; + union + { + __IOM uint32_t REG_668H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_668H_b; + }; + union + { + __IOM uint32_t REG_66CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_66CH_b; + }; + union + { + __IOM uint32_t REG_670H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_670H_b; + }; + union + { + __IOM uint32_t REG_674H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_674H_b; + }; + union + { + __IOM uint32_t REG_678H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_678H_b; + }; + union + { + __IOM uint32_t REG_67CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_67CH_b; + }; + union + { + __IOM uint32_t REG_680H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_680H_b; + }; + union + { + __IOM uint32_t REG_684H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_684H_b; + }; + union + { + __IOM uint32_t REG_688H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_688H_b; + }; + union + { + __IOM uint32_t REG_68CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_68CH_b; + }; + union + { + __IOM uint32_t REG_690H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_690H_b; + }; + union + { + __IOM uint32_t REG_694H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_694H_b; + }; + union + { + __IOM uint32_t REG_698H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_698H_b; + }; + union + { + __IOM uint32_t REG_69CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_69CH_b; + }; + union + { + __IOM uint32_t REG_6A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6A0H_b; + }; + union + { + __IOM uint32_t REG_6A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6A4H_b; + }; + union + { + __IOM uint32_t REG_6A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6A8H_b; + }; + union + { + __IOM uint32_t REG_6ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6ACH_b; + }; + union + { + __IOM uint32_t REG_6B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6B0H_b; + }; + union + { + __IOM uint32_t REG_6B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6B4H_b; + }; + union + { + __IOM uint32_t REG_6B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6B8H_b; + }; + union + { + __IOM uint32_t REG_6BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6BCH_b; + }; + union + { + __IOM uint32_t REG_6C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6C0H_b; + }; + union + { + __IOM uint32_t REG_6C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6C4H_b; + }; + union + { + __IOM uint32_t REG_6C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6C8H_b; + }; + union + { + __IOM uint32_t REG_6CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6CCH_b; + }; + union + { + __IOM uint32_t REG_6D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6D0H_b; + }; + union + { + __IOM uint32_t REG_6D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6D4H_b; + }; + union + { + __IOM uint32_t REG_6D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6D8H_b; + }; + union + { + __IOM uint32_t REG_6DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6DCH_b; + }; + union + { + __IOM uint32_t REG_6E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6E0H_b; + }; + union + { + __IOM uint32_t REG_6E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6E4H_b; + }; + union + { + __IOM uint32_t REG_6E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6E8H_b; + }; + union + { + __IOM uint32_t REG_6ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6ECH_b; + }; + union + { + __IOM uint32_t REG_6F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6F0H_b; + }; + union + { + __IOM uint32_t REG_6F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6F4H_b; + }; + union + { + __IOM uint32_t REG_6F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6F8H_b; + }; + union + { + __IOM uint32_t REG_6FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6FCH_b; + }; + union + { + __IOM uint32_t REG_700H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_700H_b; + }; + union + { + __IOM uint32_t REG_704H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_704H_b; + }; + union + { + __IOM uint32_t REG_708H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_708H_b; + }; + union + { + __IOM uint32_t REG_70CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_70CH_b; + }; + union + { + __IOM uint32_t REG_710H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_710H_b; + }; + union + { + __IOM uint32_t REG_714H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_714H_b; + }; + union + { + __IOM uint32_t REG_718H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_718H_b; + }; + union + { + __IOM uint32_t REG_71CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_71CH_b; + }; + union + { + __IOM uint32_t REG_720H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_720H_b; + }; + union + { + __IOM uint32_t REG_724H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_724H_b; + }; + union + { + __IOM uint32_t REG_728H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_728H_b; + }; + union + { + __IOM uint32_t REG_72CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_72CH_b; + }; + union + { + __IOM uint32_t REG_730H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_730H_b; + }; + union + { + __IOM uint32_t REG_734H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_734H_b; + }; + union + { + __IOM uint32_t REG_738H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_738H_b; + }; + union + { + __IOM uint32_t REG_73CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_73CH_b; + }; + union + { + __IOM uint32_t REG_740H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_740H_b; + }; + union + { + __IOM uint32_t REG_744H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_744H_b; + }; + union + { + __IOM uint32_t REG_748H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_748H_b; + }; + union + { + __IOM uint32_t REG_74CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_74CH_b; + }; + union + { + __IOM uint32_t REG_750H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_750H_b; + }; + union + { + __IOM uint32_t REG_754H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_754H_b; + }; + union + { + __IOM uint32_t REG_758H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_758H_b; + }; + union + { + __IOM uint32_t REG_75CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_75CH_b; + }; + union + { + __IOM uint32_t REG_760H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_760H_b; + }; + union + { + __IOM uint32_t REG_764H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_764H_b; + }; + union + { + __IOM uint32_t REG_768H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_768H_b; + }; + union + { + __IOM uint32_t REG_76CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_76CH_b; + }; + union + { + __IOM uint32_t REG_770H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_770H_b; + }; + union + { + __IOM uint32_t REG_774H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_774H_b; + }; + union + { + __IOM uint32_t REG_778H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_778H_b; + }; + union + { + __IOM uint32_t REG_77CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_77CH_b; + }; + union + { + __IOM uint32_t REG_780H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_780H_b; + }; + union + { + __IOM uint32_t REG_784H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_784H_b; + }; + union + { + __IOM uint32_t REG_788H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_788H_b; + }; + union + { + __IOM uint32_t REG_78CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_78CH_b; + }; + union + { + __IOM uint32_t REG_790H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_790H_b; + }; + union + { + __IOM uint32_t REG_794H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_794H_b; + }; + union + { + __IOM uint32_t REG_798H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_798H_b; + }; + union + { + __IOM uint32_t REG_79CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_79CH_b; + }; + union + { + __IOM uint32_t REG_7A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7A0H_b; + }; + union + { + __IOM uint32_t REG_7A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7A4H_b; + }; + union + { + __IOM uint32_t REG_7A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7A8H_b; + }; + union + { + __IOM uint32_t REG_7ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7ACH_b; + }; + union + { + __IOM uint32_t REG_7B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7B0H_b; + }; + union + { + __IOM uint32_t REG_7B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7B4H_b; + }; + union + { + __IOM uint32_t REG_7B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7B8H_b; + }; + union + { + __IOM uint32_t REG_7BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7BCH_b; + }; + union + { + __IOM uint32_t REG_7C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7C0H_b; + }; + union + { + __IOM uint32_t REG_7C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7C4H_b; + }; + union + { + __IOM uint32_t REG_7C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7C8H_b; + }; + union + { + __IOM uint32_t REG_7CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7CCH_b; + }; + union + { + __IOM uint32_t REG_7D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7D0H_b; + }; + union + { + __IOM uint32_t REG_7D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7D4H_b; + }; + union + { + __IOM uint32_t REG_7D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7D8H_b; + }; + union + { + __IOM uint32_t REG_7DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7DCH_b; + }; + union + { + __IOM uint32_t REG_7E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7E0H_b; + }; + union + { + __IOM uint32_t REG_7E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7E4H_b; + }; + union + { + __IOM uint32_t REG_7E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7E8H_b; + }; + union + { + __IOM uint32_t REG_7ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7ECH_b; + }; + union + { + __IOM uint32_t REG_7F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7F0H_b; + }; + union + { + __IOM uint32_t REG_7F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7F4H_b; + }; + union + { + __IOM uint32_t REG_7F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7F8H_b; + }; + union + { + __IOM uint32_t REG_7FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7FCH_b; + }; + union + { + __IOM uint32_t REG_800H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_800H_b; + }; + union + { + __IOM uint32_t REG_804H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_804H_b; + }; + union + { + __IOM uint32_t REG_808H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_808H_b; + }; + union + { + __IOM uint32_t REG_80CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_80CH_b; + }; + union + { + __IOM uint32_t REG_810H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_810H_b; + }; + union + { + __IOM uint32_t REG_814H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_814H_b; + }; + union + { + __IOM uint32_t REG_818H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_818H_b; + }; + union + { + __IOM uint32_t REG_81CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_81CH_b; + }; + union + { + __IOM uint32_t REG_820H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_820H_b; + }; + union + { + __IOM uint32_t REG_824H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_824H_b; + }; + union + { + __IOM uint32_t REG_828H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_828H_b; + }; + union + { + __IOM uint32_t REG_82CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_82CH_b; + }; + union + { + __IOM uint32_t REG_830H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_830H_b; + }; + union + { + __IOM uint32_t REG_834H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_834H_b; + }; + union + { + __IOM uint32_t REG_838H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_838H_b; + }; + union + { + __IOM uint32_t REG_83CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_83CH_b; + }; + union + { + __IOM uint32_t REG_840H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_840H_b; + }; + union + { + __IOM uint32_t REG_844H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_844H_b; + }; + union + { + __IOM uint32_t REG_848H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_848H_b; + }; + union + { + __IOM uint32_t REG_84CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_84CH_b; + }; + union + { + __IOM uint32_t REG_850H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_850H_b; + }; + union + { + __IOM uint32_t REG_854H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_854H_b; + }; + union + { + __IOM uint32_t REG_858H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_858H_b; + }; + union + { + __IOM uint32_t REG_85CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_85CH_b; + }; + union + { + __IOM uint32_t REG_860H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_860H_b; + }; + union + { + __IOM uint32_t REG_864H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_864H_b; + }; + union + { + __IOM uint32_t REG_868H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_868H_b; + }; + union + { + __IOM uint32_t REG_86CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_86CH_b; + }; + union + { + __IOM uint32_t REG_870H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_870H_b; + }; + union + { + __IOM uint32_t REG_874H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_874H_b; + }; + union + { + __IOM uint32_t REG_878H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_878H_b; + }; + union + { + __IOM uint32_t REG_87CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_87CH_b; + }; + union + { + __IOM uint32_t REG_880H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_880H_b; + }; + union + { + __IOM uint32_t REG_884H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_884H_b; + }; + union + { + __IOM uint32_t REG_888H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_888H_b; + }; + union + { + __IOM uint32_t REG_88CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_88CH_b; + }; + union + { + __IOM uint32_t REG_890H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_890H_b; + }; + union + { + __IOM uint32_t REG_894H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_894H_b; + }; + union + { + __IOM uint32_t REG_898H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_898H_b; + }; + union + { + __IOM uint32_t REG_89CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_89CH_b; + }; + union + { + __IOM uint32_t REG_8A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8A0H_b; + }; + union + { + __IOM uint32_t REG_8A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8A4H_b; + }; + union + { + __IOM uint32_t REG_8A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8A8H_b; + }; + union + { + __IOM uint32_t REG_8ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8ACH_b; + }; + union + { + __IOM uint32_t REG_8B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8B0H_b; + }; + union + { + __IOM uint32_t REG_8B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8B4H_b; + }; + union + { + __IOM uint32_t REG_8B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8B8H_b; + }; + union + { + __IOM uint32_t REG_8BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8BCH_b; + }; + union + { + __IOM uint32_t REG_8C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8C0H_b; + }; + union + { + __IOM uint32_t REG_8C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8C4H_b; + }; + union + { + __IOM uint32_t REG_8C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8C8H_b; + }; + union + { + __IOM uint32_t REG_8CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8CCH_b; + }; + union + { + __IOM uint32_t REG_8D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8D0H_b; + }; + union + { + __IOM uint32_t REG_8D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8D4H_b; + }; + union + { + __IOM uint32_t REG_8D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8D8H_b; + }; + union + { + __IOM uint32_t REG_8DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8DCH_b; + }; + union + { + __IOM uint32_t REG_8E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8E0H_b; + }; + union + { + __IOM uint32_t REG_8E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8E4H_b; + }; + union + { + __IOM uint32_t REG_8E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8E8H_b; + }; + union + { + __IOM uint32_t REG_8ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8ECH_b; + }; + union + { + __IOM uint32_t REG_8F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8F0H_b; + }; + union + { + __IOM uint32_t REG_8F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8F4H_b; + }; + union + { + __IOM uint32_t REG_8F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8F8H_b; + }; + union + { + __IOM uint32_t REG_8FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8FCH_b; + }; + union + { + __IOM uint32_t REG_900H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_900H_b; + }; + union + { + __IOM uint32_t REG_904H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_904H_b; + }; + union + { + __IOM uint32_t REG_908H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_908H_b; + }; + union + { + __IOM uint32_t REG_90CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_90CH_b; + }; + union + { + __IOM uint32_t REG_910H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_910H_b; + }; + union + { + __IOM uint32_t REG_914H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_914H_b; + }; + union + { + __IOM uint32_t REG_918H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_918H_b; + }; + union + { + __IOM uint32_t REG_91CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_91CH_b; + }; + union + { + __IOM uint32_t REG_920H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_920H_b; + }; + union + { + __IOM uint32_t REG_924H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_924H_b; + }; + union + { + __IOM uint32_t REG_928H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_928H_b; + }; + union + { + __IOM uint32_t REG_92CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_92CH_b; + }; + union + { + __IOM uint32_t REG_930H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_930H_b; + }; + union + { + __IOM uint32_t REG_934H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_934H_b; + }; + union + { + __IOM uint32_t REG_938H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_938H_b; + }; + union + { + __IOM uint32_t REG_93CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_93CH_b; + }; + union + { + __IOM uint32_t REG_940H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_940H_b; + }; + union + { + __IOM uint32_t REG_944H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_944H_b; + }; + union + { + __IOM uint32_t REG_948H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_948H_b; + }; + union + { + __IOM uint32_t REG_94CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_94CH_b; + }; + union + { + __IOM uint32_t REG_950H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_950H_b; + }; + union + { + __IOM uint32_t REG_954H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_954H_b; + }; + union + { + __IOM uint32_t REG_958H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_958H_b; + }; + union + { + __IOM uint32_t REG_95CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_95CH_b; + }; + union + { + __IOM uint32_t REG_960H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_960H_b; + }; + union + { + __IOM uint32_t REG_964H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_964H_b; + }; + union + { + __IOM uint32_t REG_968H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_968H_b; + }; + union + { + __IOM uint32_t REG_96CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_96CH_b; + }; + union + { + __IOM uint32_t REG_970H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_970H_b; + }; + union + { + __IOM uint32_t REG_974H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_974H_b; + }; + union + { + __IOM uint32_t REG_978H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_978H_b; + }; + union + { + __IOM uint32_t REG_97CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_97CH_b; + }; + union + { + __IOM uint32_t REG_980H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_980H_b; + }; + union + { + __IOM uint32_t REG_984H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_984H_b; + }; + union + { + __IOM uint32_t REG_988H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_988H_b; + }; + union + { + __IOM uint32_t REG_98CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_98CH_b; + }; + union + { + __IOM uint32_t REG_990H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_990H_b; + }; + union + { + __IOM uint32_t REG_994H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_994H_b; + }; + union + { + __IOM uint32_t REG_998H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_998H_b; + }; + union + { + __IOM uint32_t REG_99CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_99CH_b; + }; + union + { + __IOM uint32_t REG_9A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9A0H_b; + }; + union + { + __IOM uint32_t REG_9A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9A4H_b; + }; + union + { + __IOM uint32_t REG_9A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9A8H_b; + }; + union + { + __IOM uint32_t REG_9ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9ACH_b; + }; + union + { + __IOM uint32_t REG_9B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9B0H_b; + }; + union + { + __IOM uint32_t REG_9B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9B4H_b; + }; + union + { + __IOM uint32_t REG_9B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9B8H_b; + }; + union + { + __IOM uint32_t REG_9BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9BCH_b; + }; + union + { + __IOM uint32_t REG_9C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9C0H_b; + }; + union + { + __IOM uint32_t REG_9C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9C4H_b; + }; + union + { + __IOM uint32_t REG_9C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9C8H_b; + }; + union + { + __IOM uint32_t REG_9CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9CCH_b; + }; + union + { + __IOM uint32_t REG_9D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9D0H_b; + }; + union + { + __IOM uint32_t REG_9D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9D4H_b; + }; + union + { + __IOM uint32_t REG_9D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9D8H_b; + }; + union + { + __IOM uint32_t REG_9DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9DCH_b; + }; + union + { + __IOM uint32_t REG_9E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9E0H_b; + }; + union + { + __IOM uint32_t REG_9E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9E4H_b; + }; + union + { + __IOM uint32_t REG_9E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9E8H_b; + }; + union + { + __IOM uint32_t REG_9ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9ECH_b; + }; + union + { + __IOM uint32_t REG_9F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9F0H_b; + }; + union + { + __IOM uint32_t REG_9F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9F4H_b; + }; + union + { + __IOM uint32_t REG_9F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9F8H_b; + }; + union + { + __IOM uint32_t REG_9FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9FCH_b; + }; + union + { + __IOM uint32_t REG_A00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A00H_b; + }; + union + { + __IOM uint32_t REG_A04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A04H_b; + }; + union + { + __IOM uint32_t REG_A08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A08H_b; + }; + union + { + __IOM uint32_t REG_A0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A0CH_b; + }; + union + { + __IOM uint32_t REG_A10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A10H_b; + }; + union + { + __IOM uint32_t REG_A14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A14H_b; + }; + union + { + __IOM uint32_t REG_A18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A18H_b; + }; + union + { + __IOM uint32_t REG_A1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A1CH_b; + }; + union + { + __IOM uint32_t REG_A20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A20H_b; + }; + union + { + __IOM uint32_t REG_A24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A24H_b; + }; + union + { + __IOM uint32_t REG_A28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A28H_b; + }; + union + { + __IOM uint32_t REG_A2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A2CH_b; + }; + union + { + __IOM uint32_t REG_A30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A30H_b; + }; + union + { + __IOM uint32_t REG_A34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A34H_b; + }; + union + { + __IOM uint32_t REG_A38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A38H_b; + }; + union + { + __IOM uint32_t REG_A3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A3CH_b; + }; + union + { + __IOM uint32_t REG_A40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A40H_b; + }; + union + { + __IOM uint32_t REG_A44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A44H_b; + }; + union + { + __IOM uint32_t REG_A48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A48H_b; + }; + union + { + __IOM uint32_t REG_A4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A4CH_b; + }; + union + { + __IOM uint32_t REG_A50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A50H_b; + }; + union + { + __IOM uint32_t REG_A54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A54H_b; + }; + union + { + __IOM uint32_t REG_A58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A58H_b; + }; + union + { + __IOM uint32_t REG_A5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A5CH_b; + }; + union + { + __IOM uint32_t REG_A60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A60H_b; + }; + union + { + __IOM uint32_t REG_A64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A64H_b; + }; + union + { + __IOM uint32_t REG_A68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A68H_b; + }; + union + { + __IOM uint32_t REG_A6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A6CH_b; + }; + union + { + __IOM uint32_t REG_A70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A70H_b; + }; + union + { + __IOM uint32_t REG_A74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A74H_b; + }; + union + { + __IOM uint32_t REG_A78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A78H_b; + }; + union + { + __IOM uint32_t REG_A7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A7CH_b; + }; + union + { + __IOM uint32_t REG_A80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A80H_b; + }; + union + { + __IOM uint32_t REG_A84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A84H_b; + }; + union + { + __IOM uint32_t REG_A88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A88H_b; + }; + union + { + __IOM uint32_t REG_A8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A8CH_b; + }; + union + { + __IOM uint32_t REG_A90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A90H_b; + }; + union + { + __IOM uint32_t REG_A94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A94H_b; + }; + union + { + __IOM uint32_t REG_A98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A98H_b; + }; + union + { + __IOM uint32_t REG_A9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A9CH_b; + }; + union + { + __IOM uint32_t REG_AA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AA0H_b; + }; + union + { + __IOM uint32_t REG_AA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AA4H_b; + }; + union + { + __IOM uint32_t REG_AA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AA8H_b; + }; + union + { + __IOM uint32_t REG_AACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AACH_b; + }; + union + { + __IOM uint32_t REG_AB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AB0H_b; + }; + union + { + __IOM uint32_t REG_AB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AB4H_b; + }; + union + { + __IOM uint32_t REG_AB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AB8H_b; + }; + union + { + __IOM uint32_t REG_ABCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_ABCH_b; + }; + union + { + __IOM uint32_t REG_AC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AC0H_b; + }; + union + { + __IOM uint32_t REG_AC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AC4H_b; + }; + union + { + __IOM uint32_t REG_AC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AC8H_b; + }; + union + { + __IOM uint32_t REG_ACCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_ACCH_b; + }; + union + { + __IOM uint32_t REG_AD0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AD0H_b; + }; + union + { + __IOM uint32_t REG_AD4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AD4H_b; + }; + union + { + __IOM uint32_t REG_AD8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AD8H_b; + }; + union + { + __IOM uint32_t REG_ADCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_ADCH_b; + }; + union + { + __IOM uint32_t REG_AE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AE0H_b; + }; + union + { + __IOM uint32_t REG_AE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AE4H_b; + }; + union + { + __IOM uint32_t REG_AE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AE8H_b; + }; + union + { + __IOM uint32_t REG_AECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AECH_b; + }; + union + { + __IOM uint32_t REG_AF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AF0H_b; + }; + union + { + __IOM uint32_t REG_AF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AF4H_b; + }; + union + { + __IOM uint32_t REG_AF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AF8H_b; + }; + union + { + __IOM uint32_t REG_AFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AFCH_b; + }; + union + { + __IOM uint32_t REG_B00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B00H_b; + }; + union + { + __IOM uint32_t REG_B04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B04H_b; + }; + union + { + __IOM uint32_t REG_B08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B08H_b; + }; + union + { + __IOM uint32_t REG_B0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B0CH_b; + }; + union + { + __IOM uint32_t REG_B10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B10H_b; + }; + union + { + __IOM uint32_t REG_B14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B14H_b; + }; + union + { + __IOM uint32_t REG_B18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B18H_b; + }; + union + { + __IOM uint32_t REG_B1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B1CH_b; + }; + union + { + __IOM uint32_t REG_B20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B20H_b; + }; + union + { + __IOM uint32_t REG_B24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B24H_b; + }; + union + { + __IOM uint32_t REG_B28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B28H_b; + }; + union + { + __IOM uint32_t REG_B2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B2CH_b; + }; + union + { + __IOM uint32_t REG_B30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B30H_b; + }; + union + { + __IOM uint32_t REG_B34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B34H_b; + }; + union + { + __IOM uint32_t REG_B38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B38H_b; + }; + union + { + __IOM uint32_t REG_B3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B3CH_b; + }; + union + { + __IOM uint32_t REG_B40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B40H_b; + }; + union + { + __IOM uint32_t REG_B44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B44H_b; + }; + union + { + __IOM uint32_t REG_B48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B48H_b; + }; + union + { + __IOM uint32_t REG_B4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B4CH_b; + }; + union + { + __IOM uint32_t REG_B50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B50H_b; + }; + union + { + __IOM uint32_t REG_B54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B54H_b; + }; + union + { + __IOM uint32_t REG_B58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B58H_b; + }; + union + { + __IOM uint32_t REG_B5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B5CH_b; + }; + union + { + __IOM uint32_t REG_B60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B60H_b; + }; + union + { + __IOM uint32_t REG_B64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B64H_b; + }; + union + { + __IOM uint32_t REG_B68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B68H_b; + }; + union + { + __IOM uint32_t REG_B6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B6CH_b; + }; + union + { + __IOM uint32_t REG_B70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B70H_b; + }; + union + { + __IOM uint32_t REG_B74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B74H_b; + }; + union + { + __IOM uint32_t REG_B78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B78H_b; + }; + union + { + __IOM uint32_t REG_B7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B7CH_b; + }; + union + { + __IOM uint32_t REG_B80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B80H_b; + }; + union + { + __IOM uint32_t REG_B84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B84H_b; + }; + union + { + __IOM uint32_t REG_B88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B88H_b; + }; + union + { + __IOM uint32_t REG_B8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B8CH_b; + }; + union + { + __IOM uint32_t REG_B90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B90H_b; + }; + union + { + __IOM uint32_t REG_B94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B94H_b; + }; + union + { + __IOM uint32_t REG_B98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B98H_b; + }; + union + { + __IOM uint32_t REG_B9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B9CH_b; + }; + union + { + __IOM uint32_t REG_BA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BA0H_b; + }; + union + { + __IOM uint32_t REG_BA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BA4H_b; + }; + union + { + __IOM uint32_t REG_BA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BA8H_b; + }; + union + { + __IOM uint32_t REG_BACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BACH_b; + }; + union + { + __IOM uint32_t REG_BB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BB0H_b; + }; + union + { + __IOM uint32_t REG_BB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BB4H_b; + }; + union + { + __IOM uint32_t REG_BB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BB8H_b; + }; + union + { + __IOM uint32_t REG_BBCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BBCH_b; + }; + union + { + __IOM uint32_t REG_BC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BC0H_b; + }; + union + { + __IOM uint32_t REG_BC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BC4H_b; + }; + union + { + __IOM uint32_t REG_BC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BC8H_b; + }; + union + { + __IOM uint32_t REG_BCCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BCCH_b; + }; + union + { + __IOM uint32_t REG_BD0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BD0H_b; + }; + union + { + __IOM uint32_t REG_BD4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BD4H_b; + }; + union + { + __IOM uint32_t REG_BD8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BD8H_b; + }; + union + { + __IOM uint32_t REG_BDCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BDCH_b; + }; + union + { + __IOM uint32_t REG_BE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BE0H_b; + }; + union + { + __IOM uint32_t REG_BE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BE4H_b; + }; + union + { + __IOM uint32_t REG_BE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BE8H_b; + }; + union + { + __IOM uint32_t REG_BECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BECH_b; + }; + union + { + __IOM uint32_t REG_BF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BF0H_b; + }; + union + { + __IOM uint32_t REG_BF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BF4H_b; + }; + union + { + __IOM uint32_t REG_BF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BF8H_b; + }; + union + { + __IOM uint32_t REG_BFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BFCH_b; + }; + union + { + __IOM uint32_t REG_C00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C00H_b; + }; + union + { + __IOM uint32_t REG_C04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C04H_b; + }; + union + { + __IOM uint32_t REG_C08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C08H_b; + }; + union + { + __IOM uint32_t REG_C0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C0CH_b; + }; + union + { + __IOM uint32_t REG_C10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C10H_b; + }; + union + { + __IOM uint32_t REG_C14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C14H_b; + }; + union + { + __IOM uint32_t REG_C18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C18H_b; + }; + union + { + __IOM uint32_t REG_C1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C1CH_b; + }; + union + { + __IOM uint32_t REG_C20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C20H_b; + }; + union + { + __IOM uint32_t REG_C24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C24H_b; + }; + union + { + __IOM uint32_t REG_C28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C28H_b; + }; + union + { + __IOM uint32_t REG_C2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C2CH_b; + }; + union + { + __IOM uint32_t REG_C30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C30H_b; + }; + union + { + __IOM uint32_t REG_C34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C34H_b; + }; + union + { + __IOM uint32_t REG_C38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C38H_b; + }; + union + { + __IOM uint32_t REG_C3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C3CH_b; + }; + union + { + __IOM uint32_t REG_C40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C40H_b; + }; + union + { + __IOM uint32_t REG_C44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C44H_b; + }; + union + { + __IOM uint32_t REG_C48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C48H_b; + }; + union + { + __IOM uint32_t REG_C4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C4CH_b; + }; + union + { + __IOM uint32_t REG_C50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C50H_b; + }; + union + { + __IOM uint32_t REG_C54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C54H_b; + }; + union + { + __IOM uint32_t REG_C58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C58H_b; + }; + union + { + __IOM uint32_t REG_C5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C5CH_b; + }; + union + { + __IOM uint32_t REG_C60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C60H_b; + }; + union + { + __IOM uint32_t REG_C64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C64H_b; + }; + union + { + __IOM uint32_t REG_C68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C68H_b; + }; + union + { + __IOM uint32_t REG_C6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C6CH_b; + }; + union + { + __IOM uint32_t REG_C70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C70H_b; + }; + union + { + __IOM uint32_t REG_C74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C74H_b; + }; + union + { + __IOM uint32_t REG_C78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C78H_b; + }; + union + { + __IOM uint32_t REG_C7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C7CH_b; + }; + union + { + __IOM uint32_t REG_C80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C80H_b; + }; + union + { + __IOM uint32_t REG_C84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C84H_b; + }; + union + { + __IOM uint32_t REG_C88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C88H_b; + }; + union + { + __IOM uint32_t REG_C8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C8CH_b; + }; + union + { + __IOM uint32_t REG_C90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C90H_b; + }; + union + { + __IOM uint32_t REG_C94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C94H_b; + }; + union + { + __IOM uint32_t REG_C98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C98H_b; + }; + union + { + __IOM uint32_t REG_C9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C9CH_b; + }; + union + { + __IOM uint32_t REG_CA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CA0H_b; + }; + union + { + __IOM uint32_t REG_CA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CA4H_b; + }; + union + { + __IOM uint32_t REG_CA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CA8H_b; + }; + union + { + __IOM uint32_t REG_CACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CACH_b; + }; + union + { + __IOM uint32_t REG_CB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CB0H_b; + }; + union + { + __IOM uint32_t REG_CB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CB4H_b; + }; + union + { + __IOM uint32_t REG_CB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CB8H_b; + }; + union + { + __IOM uint32_t REG_CBCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CBCH_b; + }; + union + { + __IOM uint32_t REG_CC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CC0H_b; + }; + union + { + __IOM uint32_t REG_CC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CC4H_b; + }; + union + { + __IOM uint32_t REG_CC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CC8H_b; + }; + union + { + __IOM uint32_t REG_CCCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CCCH_b; + }; + union + { + __IOM uint32_t REG_CD0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CD0H_b; + }; + union + { + __IOM uint32_t REG_CD4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CD4H_b; + }; + union + { + __IOM uint32_t REG_CD8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CD8H_b; + }; + union + { + __IOM uint32_t REG_CDCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CDCH_b; + }; + union + { + __IOM uint32_t REG_CE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CE0H_b; + }; + union + { + __IOM uint32_t REG_CE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CE4H_b; + }; + union + { + __IOM uint32_t REG_CE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CE8H_b; + }; + union + { + __IOM uint32_t REG_CECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CECH_b; + }; + union + { + __IOM uint32_t REG_CF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CF0H_b; + }; + union + { + __IOM uint32_t REG_CF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CF4H_b; + }; + union + { + __IOM uint32_t REG_CF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CF8H_b; + }; + union + { + __IOM uint32_t REG_CFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CFCH_b; + }; + union + { + __IOM uint32_t REG_D00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D00H_b; + }; + union + { + __IOM uint32_t REG_D04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D04H_b; + }; + union + { + __IOM uint32_t REG_D08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D08H_b; + }; + union + { + __IOM uint32_t REG_D0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D0CH_b; + }; + union + { + __IOM uint32_t REG_D10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D10H_b; + }; + union + { + __IOM uint32_t REG_D14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D14H_b; + }; + union + { + __IOM uint32_t REG_D18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D18H_b; + }; + union + { + __IOM uint32_t REG_D1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D1CH_b; + }; + union + { + __IOM uint32_t REG_D20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D20H_b; + }; + union + { + __IOM uint32_t REG_D24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D24H_b; + }; + union + { + __IOM uint32_t REG_D28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D28H_b; + }; + union + { + __IOM uint32_t REG_D2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D2CH_b; + }; + union + { + __IOM uint32_t REG_D30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D30H_b; + }; + union + { + __IOM uint32_t REG_D34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D34H_b; + }; + union + { + __IOM uint32_t REG_D38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D38H_b; + }; + union + { + __IOM uint32_t REG_D3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D3CH_b; + }; + union + { + __IOM uint32_t REG_D40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D40H_b; + }; + union + { + __IOM uint32_t REG_D44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D44H_b; + }; + union + { + __IOM uint32_t REG_D48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D48H_b; + }; + union + { + __IOM uint32_t REG_D4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D4CH_b; + }; + union + { + __IOM uint32_t REG_D50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D50H_b; + }; + union + { + __IOM uint32_t REG_D54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D54H_b; + }; + union + { + __IOM uint32_t REG_D58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D58H_b; + }; + union + { + __IOM uint32_t REG_D5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D5CH_b; + }; + union + { + __IOM uint32_t REG_D60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D60H_b; + }; + union + { + __IOM uint32_t REG_D64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D64H_b; + }; + union + { + __IOM uint32_t REG_D68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D68H_b; + }; + union + { + __IOM uint32_t REG_D6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D6CH_b; + }; + union + { + __IOM uint32_t REG_D70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D70H_b; + }; + union + { + __IOM uint32_t REG_D74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D74H_b; + }; + union + { + __IOM uint32_t REG_D78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D78H_b; + }; + union + { + __IOM uint32_t REG_D7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D7CH_b; + }; + union + { + __IOM uint32_t REG_D80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D80H_b; + }; + union + { + __IOM uint32_t REG_D84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D84H_b; + }; + union + { + __IOM uint32_t REG_D88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D88H_b; + }; + union + { + __IOM uint32_t REG_D8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D8CH_b; + }; + union + { + __IOM uint32_t REG_D90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D90H_b; + }; + union + { + __IOM uint32_t REG_D94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D94H_b; + }; + union + { + __IOM uint32_t REG_D98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D98H_b; + }; + union + { + __IOM uint32_t REG_D9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D9CH_b; + }; + union + { + __IOM uint32_t REG_DA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DA0H_b; + }; + union + { + __IOM uint32_t REG_DA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DA4H_b; + }; + union + { + __IOM uint32_t REG_DA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DA8H_b; + }; + union + { + __IOM uint32_t REG_DACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DACH_b; + }; + union + { + __IOM uint32_t REG_DB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DB0H_b; + }; + union + { + __IOM uint32_t REG_DB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DB4H_b; + }; + union + { + __IOM uint32_t REG_DB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DB8H_b; + }; + union + { + __IOM uint32_t REG_DBCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DBCH_b; + }; + union + { + __IOM uint32_t REG_DC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DC0H_b; + }; + union + { + __IOM uint32_t REG_DC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DC4H_b; + }; + union + { + __IOM uint32_t REG_DC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DC8H_b; + }; + union + { + __IOM uint32_t REG_DCCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DCCH_b; + }; + union + { + __IOM uint32_t REG_DD0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DD0H_b; + }; + union + { + __IOM uint32_t REG_DD4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DD4H_b; + }; + union + { + __IOM uint32_t REG_DD8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DD8H_b; + }; + union + { + __IOM uint32_t REG_DDCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DDCH_b; + }; + union + { + __IOM uint32_t REG_DE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DE0H_b; + }; + union + { + __IOM uint32_t REG_DE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DE4H_b; + }; + union + { + __IOM uint32_t REG_DE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DE8H_b; + }; + union + { + __IOM uint32_t REG_DECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DECH_b; + }; + union + { + __IOM uint32_t REG_DF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DF0H_b; + }; + union + { + __IOM uint32_t REG_DF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DF4H_b; + }; + union + { + __IOM uint32_t REG_DF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DF8H_b; + }; + union + { + __IOM uint32_t REG_DFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DFCH_b; + }; + union + { + __IOM uint32_t REG_E00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E00H_b; + }; + union + { + __IOM uint32_t REG_E04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E04H_b; + }; + union + { + __IOM uint32_t REG_E08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E08H_b; + }; + union + { + __IOM uint32_t REG_E0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E0CH_b; + }; + union + { + __IOM uint32_t REG_E10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E10H_b; + }; + union + { + __IOM uint32_t REG_E14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E14H_b; + }; + union + { + __IOM uint32_t REG_E18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E18H_b; + }; + union + { + __IOM uint32_t REG_E1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E1CH_b; + }; + union + { + __IOM uint32_t REG_E20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E20H_b; + }; + union + { + __IOM uint32_t REG_E24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E24H_b; + }; + union + { + __IOM uint32_t REG_E28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E28H_b; + }; + union + { + __IOM uint32_t REG_E2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E2CH_b; + }; + union + { + __IOM uint32_t REG_E30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E30H_b; + }; + union + { + __IOM uint32_t REG_E34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E34H_b; + }; + union + { + __IOM uint32_t REG_E38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E38H_b; + }; + union + { + __IOM uint32_t REG_E3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E3CH_b; + }; + union + { + __IOM uint32_t REG_E40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E40H_b; + }; + union + { + __IOM uint32_t REG_E44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E44H_b; + }; + union + { + __IOM uint32_t REG_E48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E48H_b; + }; + union + { + __IOM uint32_t REG_E4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E4CH_b; + }; + union + { + __IOM uint32_t REG_E50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E50H_b; + }; + union + { + __IOM uint32_t REG_E54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E54H_b; + }; + union + { + __IOM uint32_t REG_E58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E58H_b; + }; + union + { + __IOM uint32_t REG_E5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E5CH_b; + }; + union + { + __IOM uint32_t REG_E60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E60H_b; + }; + union + { + __IOM uint32_t REG_E64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E64H_b; + }; + union + { + __IOM uint32_t REG_E68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E68H_b; + }; + union + { + __IOM uint32_t REG_E6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E6CH_b; + }; + union + { + __IOM uint32_t REG_E70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E70H_b; + }; + union + { + __IOM uint32_t REG_E74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E74H_b; + }; + union + { + __IOM uint32_t REG_E78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E78H_b; + }; + union + { + __IOM uint32_t REG_E7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E7CH_b; + }; + union + { + __IOM uint32_t REG_E80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E80H_b; + }; + union + { + __IOM uint32_t REG_E84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E84H_b; + }; + union + { + __IOM uint32_t REG_E88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E88H_b; + }; + union + { + __IOM uint32_t REG_E8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E8CH_b; + }; + union + { + __IOM uint32_t REG_E90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E90H_b; + }; + union + { + __IOM uint32_t REG_E94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E94H_b; + }; + union + { + __IOM uint32_t REG_E98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E98H_b; + }; + union + { + __IOM uint32_t REG_E9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E9CH_b; + }; + union + { + __IOM uint32_t REG_EA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EA0H_b; + }; + union + { + __IOM uint32_t REG_EA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EA4H_b; + }; + union + { + __IOM uint32_t REG_EA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EA8H_b; + }; + union + { + __IOM uint32_t REG_EACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EACH_b; + }; + union + { + __IOM uint32_t REG_EB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EB0H_b; + }; + union + { + __IOM uint32_t REG_EB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EB4H_b; + }; + union + { + __IOM uint32_t REG_EB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EB8H_b; + }; + union + { + __IOM uint32_t REG_EBCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EBCH_b; + }; + union + { + __IOM uint32_t REG_EC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EC0H_b; + }; + union + { + __IOM uint32_t REG_EC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EC4H_b; + }; + union + { + __IOM uint32_t REG_EC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EC8H_b; + }; + union + { + __IOM uint32_t REG_ECCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_ECCH_b; + }; + union + { + __IOM uint32_t REG_ED0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_ED0H_b; + }; + union + { + __IOM uint32_t REG_ED4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_ED4H_b; + }; + union + { + __IOM uint32_t REG_ED8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_ED8H_b; + }; + union + { + __IOM uint32_t REG_EDCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EDCH_b; + }; + union + { + __IOM uint32_t REG_EE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EE0H_b; + }; + union + { + __IOM uint32_t REG_EE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EE4H_b; + }; + union + { + __IOM uint32_t REG_EE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EE8H_b; + }; + union + { + __IOM uint32_t REG_EECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EECH_b; + }; + union + { + __IOM uint32_t REG_EF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EF0H_b; + }; + union + { + __IOM uint32_t REG_EF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EF4H_b; + }; + union + { + __IOM uint32_t REG_EF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EF8H_b; + }; + union + { + __IOM uint32_t REG_EFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EFCH_b; + }; + union + { + __IOM uint32_t REG_F00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F00H_b; + }; + union + { + __IOM uint32_t REG_F04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F04H_b; + }; + union + { + __IOM uint32_t REG_F08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F08H_b; + }; + union + { + __IOM uint32_t REG_F0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F0CH_b; + }; + union + { + __IOM uint32_t REG_F10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F10H_b; + }; + union + { + __IOM uint32_t REG_F14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F14H_b; + }; + union + { + __IOM uint32_t REG_F18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F18H_b; + }; + union + { + __IOM uint32_t REG_F1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F1CH_b; + }; + union + { + __IOM uint32_t REG_F20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F20H_b; + }; + union + { + __IOM uint32_t REG_F24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F24H_b; + }; + union + { + __IOM uint32_t REG_F28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F28H_b; + }; + union + { + __IOM uint32_t REG_F2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F2CH_b; + }; + union + { + __IOM uint32_t REG_F30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F30H_b; + }; + union + { + __IOM uint32_t REG_F34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F34H_b; + }; + union + { + __IOM uint32_t REG_F38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F38H_b; + }; + union + { + __IOM uint32_t REG_F3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F3CH_b; + }; + union + { + __IOM uint32_t REG_F40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F40H_b; + }; + union + { + __IOM uint32_t REG_F44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F44H_b; + }; + union + { + __IOM uint32_t REG_F48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F48H_b; + }; + union + { + __IOM uint32_t REG_F4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F4CH_b; + }; + union + { + __IOM uint32_t REG_F50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F50H_b; + }; + union + { + __IOM uint32_t REG_F54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F54H_b; + }; + union + { + __IOM uint32_t REG_F58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F58H_b; + }; + union + { + __IOM uint32_t REG_F5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F5CH_b; + }; + union + { + __IOM uint32_t REG_F60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F60H_b; + }; + union + { + __IOM uint32_t REG_F64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F64H_b; + }; + union + { + __IOM uint32_t REG_F68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F68H_b; + }; + union + { + __IOM uint32_t REG_F6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F6CH_b; + }; + union + { + __IOM uint32_t REG_F70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F70H_b; + }; + union + { + __IOM uint32_t REG_F74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F74H_b; + }; + union + { + __IOM uint32_t REG_F78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F78H_b; + }; + union + { + __IOM uint32_t REG_F7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F7CH_b; + }; + union + { + __IOM uint32_t REG_F80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F80H_b; + }; + union + { + __IOM uint32_t REG_F84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F84H_b; + }; + union + { + __IOM uint32_t REG_F88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F88H_b; + }; + union + { + __IOM uint32_t REG_F8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F8CH_b; + }; + union + { + __IOM uint32_t REG_F90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F90H_b; + }; + union + { + __IOM uint32_t REG_F94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F94H_b; + }; + union + { + __IOM uint32_t REG_F98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F98H_b; + }; + union + { + __IOM uint32_t REG_F9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F9CH_b; + }; + union + { + __IOM uint32_t REG_FA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FA0H_b; + }; + union + { + __IOM uint32_t REG_FA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FA4H_b; + }; + union + { + __IOM uint32_t REG_FA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FA8H_b; + }; + union + { + __IOM uint32_t REG_FACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FACH_b; + }; + union + { + __IOM uint32_t REG_FB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FB0H_b; + }; + union + { + __IOM uint32_t REG_FB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FB4H_b; + }; + union + { + __IOM uint32_t REG_FB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FB8H_b; + }; + union + { + __IOM uint32_t REG_FBCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FBCH_b; + }; + union + { + __IOM uint32_t REG_FC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FC0H_b; + }; + union + { + __IOM uint32_t REG_FC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FC4H_b; + }; + union + { + __IOM uint32_t REG_FC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FC8H_b; + }; + union + { + __IOM uint32_t REG_FCCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FCCH_b; + }; + union + { + __IOM uint32_t REG_FD0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FD0H_b; + }; + union + { + __IOM uint32_t REG_FD4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FD4H_b; + }; + union + { + __IOM uint32_t REG_FD8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FD8H_b; + }; + union + { + __IOM uint32_t REG_FDCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FDCH_b; + }; + union + { + __IOM uint32_t REG_FE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FE0H_b; + }; + union + { + __IOM uint32_t REG_FE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FE4H_b; + }; + union + { + __IOM uint32_t REG_FE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FE8H_b; + }; + union + { + __IOM uint32_t REG_FECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FECH_b; + }; + union + { + __IOM uint32_t REG_FF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FF0H_b; + }; + union + { + __IOM uint32_t REG_FF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FF4H_b; + }; + union + { + __IOM uint32_t REG_FF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FF8H_b; + }; + union + { + __IOM uint32_t REG_FFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FFCH_b; + }; + union + { + __IOM uint32_t REG_1000H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1000H_b; + }; + union + { + __IOM uint32_t REG_1004H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1004H_b; + }; + union + { + __IOM uint32_t REG_1008H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1008H_b; + }; + union + { + __IOM uint32_t REG_100CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_100CH_b; + }; + union + { + __IOM uint32_t REG_1010H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1010H_b; + }; + union + { + __IOM uint32_t REG_1014H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1014H_b; + }; + union + { + __IOM uint32_t REG_1018H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1018H_b; + }; + union + { + __IOM uint32_t REG_101CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_101CH_b; + }; + union + { + __IOM uint32_t REG_1020H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1020H_b; + }; + union + { + __IOM uint32_t REG_1024H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1024H_b; + }; + union + { + __IOM uint32_t REG_1028H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1028H_b; + }; + union + { + __IOM uint32_t REG_102CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_102CH_b; + }; + union + { + __IOM uint32_t REG_1030H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1030H_b; + }; + union + { + __IOM uint32_t REG_1034H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1034H_b; + }; + union + { + __IOM uint32_t REG_1038H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1038H_b; + }; + union + { + __IOM uint32_t REG_103CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_103CH_b; + }; + union + { + __IOM uint32_t REG_1040H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1040H_b; + }; + union + { + __IOM uint32_t REG_1044H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1044H_b; + }; + union + { + __IOM uint32_t REG_1048H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1048H_b; + }; + union + { + __IOM uint32_t REG_104CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_104CH_b; + }; + union + { + __IOM uint32_t REG_1050H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1050H_b; + }; + union + { + __IOM uint32_t REG_1054H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1054H_b; + }; + union + { + __IOM uint32_t REG_1058H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1058H_b; + }; + union + { + __IOM uint32_t REG_105CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_105CH_b; + }; + union + { + __IOM uint32_t REG_1060H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1060H_b; + }; + union + { + __IOM uint32_t REG_1064H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1064H_b; + }; + union + { + __IOM uint32_t REG_1068H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1068H_b; + }; + union + { + __IOM uint32_t REG_106CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_106CH_b; + }; + union + { + __IOM uint32_t REG_1070H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1070H_b; + }; + union + { + __IOM uint32_t REG_1074H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1074H_b; + }; + union + { + __IOM uint32_t REG_1078H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1078H_b; + }; + union + { + __IOM uint32_t REG_107CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_107CH_b; + }; + union + { + __IOM uint32_t REG_1080H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1080H_b; + }; + union + { + __IOM uint32_t REG_1084H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1084H_b; + }; + union + { + __IOM uint32_t REG_1088H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1088H_b; + }; + union + { + __IOM uint32_t REG_108CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_108CH_b; + }; + union + { + __IOM uint32_t REG_1090H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1090H_b; + }; + union + { + __IOM uint32_t REG_1094H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1094H_b; + }; + union + { + __IOM uint32_t REG_1098H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1098H_b; + }; + union + { + __IOM uint32_t REG_109CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_109CH_b; + }; + union + { + __IOM uint32_t REG_10A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10A0H_b; + }; + union + { + __IOM uint32_t REG_10A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10A4H_b; + }; + union + { + __IOM uint32_t REG_10A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10A8H_b; + }; + union + { + __IOM uint32_t REG_10ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10ACH_b; + }; + union + { + __IOM uint32_t REG_10B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10B0H_b; + }; + union + { + __IOM uint32_t REG_10B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10B4H_b; + }; + union + { + __IOM uint32_t REG_10B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10B8H_b; + }; + union + { + __IOM uint32_t REG_10BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10BCH_b; + }; + union + { + __IOM uint32_t REG_10C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10C0H_b; + }; + union + { + __IOM uint32_t REG_10C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10C4H_b; + }; + union + { + __IOM uint32_t REG_10C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10C8H_b; + }; + union + { + __IOM uint32_t REG_10CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10CCH_b; + }; + union + { + __IOM uint32_t REG_10D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10D0H_b; + }; + union + { + __IOM uint32_t REG_10D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10D4H_b; + }; + union + { + __IOM uint32_t REG_10D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10D8H_b; + }; + union + { + __IOM uint32_t REG_10DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10DCH_b; + }; + union + { + __IOM uint32_t REG_10E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10E0H_b; + }; + union + { + __IOM uint32_t REG_10E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10E4H_b; + }; + union + { + __IOM uint32_t REG_10E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10E8H_b; + }; + union + { + __IOM uint32_t REG_10ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10ECH_b; + }; + union + { + __IOM uint32_t REG_10F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10F0H_b; + }; + union + { + __IOM uint32_t REG_10F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10F4H_b; + }; + union + { + __IOM uint32_t REG_10F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10F8H_b; + }; + union + { + __IOM uint32_t REG_10FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10FCH_b; + }; + union + { + __IOM uint32_t REG_1100H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1100H_b; + }; + union + { + __IOM uint32_t REG_1104H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1104H_b; + }; + union + { + __IOM uint32_t REG_1108H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1108H_b; + }; + union + { + __IOM uint32_t REG_110CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_110CH_b; + }; + union + { + __IOM uint32_t REG_1110H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1110H_b; + }; + union + { + __IOM uint32_t REG_1114H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1114H_b; + }; + union + { + __IOM uint32_t REG_1118H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1118H_b; + }; + union + { + __IOM uint32_t REG_111CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_111CH_b; + }; + union + { + __IOM uint32_t REG_1120H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1120H_b; + }; + union + { + __IOM uint32_t REG_1124H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1124H_b; + }; + union + { + __IOM uint32_t REG_1128H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1128H_b; + }; + union + { + __IOM uint32_t REG_112CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_112CH_b; + }; + union + { + __IOM uint32_t REG_1130H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1130H_b; + }; + union + { + __IOM uint32_t REG_1134H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1134H_b; + }; + union + { + __IOM uint32_t REG_1138H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1138H_b; + }; + union + { + __IOM uint32_t REG_113CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_113CH_b; + }; + union + { + __IOM uint32_t REG_1140H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1140H_b; + }; + union + { + __IOM uint32_t REG_1144H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1144H_b; + }; + union + { + __IOM uint32_t REG_1148H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1148H_b; + }; + union + { + __IOM uint32_t REG_114CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_114CH_b; + }; + union + { + __IOM uint32_t REG_1150H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1150H_b; + }; + union + { + __IOM uint32_t REG_1154H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1154H_b; + }; + union + { + __IOM uint32_t REG_1158H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1158H_b; + }; + union + { + __IOM uint32_t REG_115CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_115CH_b; + }; + union + { + __IOM uint32_t REG_1160H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1160H_b; + }; + union + { + __IOM uint32_t REG_1164H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1164H_b; + }; + union + { + __IOM uint32_t REG_1168H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1168H_b; + }; + union + { + __IOM uint32_t REG_116CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_116CH_b; + }; + union + { + __IOM uint32_t REG_1170H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1170H_b; + }; + union + { + __IOM uint32_t REG_1174H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1174H_b; + }; + union + { + __IOM uint32_t REG_1178H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1178H_b; + }; + union + { + __IOM uint32_t REG_117CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_117CH_b; + }; + union + { + __IOM uint32_t REG_1180H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1180H_b; + }; + union + { + __IOM uint32_t REG_1184H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1184H_b; + }; + union + { + __IOM uint32_t REG_1188H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1188H_b; + }; + union + { + __IOM uint32_t REG_118CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_118CH_b; + }; + union + { + __IOM uint32_t REG_1190H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1190H_b; + }; + union + { + __IOM uint32_t REG_1194H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1194H_b; + }; + union + { + __IOM uint32_t REG_1198H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1198H_b; + }; + union + { + __IOM uint32_t REG_119CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_119CH_b; + }; + union + { + __IOM uint32_t REG_11A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11A0H_b; + }; + union + { + __IOM uint32_t REG_11A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11A4H_b; + }; + union + { + __IOM uint32_t REG_11A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11A8H_b; + }; + union + { + __IOM uint32_t REG_11ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11ACH_b; + }; + union + { + __IOM uint32_t REG_11B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11B0H_b; + }; + union + { + __IOM uint32_t REG_11B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11B4H_b; + }; + union + { + __IOM uint32_t REG_11B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11B8H_b; + }; + union + { + __IOM uint32_t REG_11BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11BCH_b; + }; + union + { + __IOM uint32_t REG_11C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11C0H_b; + }; + union + { + __IOM uint32_t REG_11C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11C4H_b; + }; + union + { + __IOM uint32_t REG_11C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11C8H_b; + }; + union + { + __IOM uint32_t REG_11CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11CCH_b; + }; + union + { + __IOM uint32_t REG_11D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11D0H_b; + }; + union + { + __IOM uint32_t REG_11D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11D4H_b; + }; + union + { + __IOM uint32_t REG_11D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11D8H_b; + }; + union + { + __IOM uint32_t REG_11DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11DCH_b; + }; + union + { + __IOM uint32_t REG_11E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11E0H_b; + }; + union + { + __IOM uint32_t REG_11E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11E4H_b; + }; + union + { + __IOM uint32_t REG_11E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11E8H_b; + }; + union + { + __IOM uint32_t REG_11ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11ECH_b; + }; + union + { + __IOM uint32_t REG_11F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11F0H_b; + }; + union + { + __IOM uint32_t REG_11F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11F4H_b; + }; + union + { + __IOM uint32_t REG_11F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11F8H_b; + }; + union + { + __IOM uint32_t REG_11FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11FCH_b; + }; + union + { + __IOM uint32_t REG_1200H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1200H_b; + }; + union + { + __IOM uint32_t REG_1204H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1204H_b; + }; + union + { + __IOM uint32_t REG_1208H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1208H_b; + }; + union + { + __IOM uint32_t REG_120CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_120CH_b; + }; + union + { + __IOM uint32_t REG_1210H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1210H_b; + }; + union + { + __IOM uint32_t REG_1214H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1214H_b; + }; + union + { + __IOM uint32_t REG_1218H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1218H_b; + }; + union + { + __IOM uint32_t REG_121CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_121CH_b; + }; + union + { + __IOM uint32_t REG_1220H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1220H_b; + }; + union + { + __IOM uint32_t REG_1224H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1224H_b; + }; + union + { + __IOM uint32_t REG_1228H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1228H_b; + }; + union + { + __IOM uint32_t REG_122CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_122CH_b; + }; + union + { + __IOM uint32_t REG_1230H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1230H_b; + }; + union + { + __IOM uint32_t REG_1234H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1234H_b; + }; + union + { + __IOM uint32_t REG_1238H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1238H_b; + }; + union + { + __IOM uint32_t REG_123CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_123CH_b; + }; + union + { + __IOM uint32_t REG_1240H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1240H_b; + }; + union + { + __IOM uint32_t REG_1244H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1244H_b; + }; + union + { + __IOM uint32_t REG_1248H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1248H_b; + }; + union + { + __IOM uint32_t REG_124CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_124CH_b; + }; + union + { + __IOM uint32_t REG_1250H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1250H_b; + }; + union + { + __IOM uint32_t REG_1254H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1254H_b; + }; + union + { + __IOM uint32_t REG_1258H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1258H_b; + }; + union + { + __IOM uint32_t REG_125CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_125CH_b; + }; + union + { + __IOM uint32_t REG_1260H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1260H_b; + }; + union + { + __IOM uint32_t REG_1264H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1264H_b; + }; + union + { + __IOM uint32_t REG_1268H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1268H_b; + }; + union + { + __IOM uint32_t REG_126CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_126CH_b; + }; + union + { + __IOM uint32_t REG_1270H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1270H_b; + }; + union + { + __IOM uint32_t REG_1274H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1274H_b; + }; + union + { + __IOM uint32_t REG_1278H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1278H_b; + }; + union + { + __IOM uint32_t REG_127CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_127CH_b; + }; + union + { + __IOM uint32_t REG_1280H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1280H_b; + }; + union + { + __IOM uint32_t REG_1284H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1284H_b; + }; + union + { + __IOM uint32_t REG_1288H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1288H_b; + }; + union + { + __IOM uint32_t REG_128CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_128CH_b; + }; + union + { + __IOM uint32_t REG_1290H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1290H_b; + }; + union + { + __IOM uint32_t REG_1294H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1294H_b; + }; + union + { + __IOM uint32_t REG_1298H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1298H_b; + }; + union + { + __IOM uint32_t REG_129CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_129CH_b; + }; + union + { + __IOM uint32_t REG_12A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12A0H_b; + }; + union + { + __IOM uint32_t REG_12A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12A4H_b; + }; + union + { + __IOM uint32_t REG_12A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12A8H_b; + }; + union + { + __IOM uint32_t REG_12ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12ACH_b; + }; + union + { + __IOM uint32_t REG_12B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12B0H_b; + }; + union + { + __IOM uint32_t REG_12B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12B4H_b; + }; + union + { + __IOM uint32_t REG_12B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12B8H_b; + }; + union + { + __IOM uint32_t REG_12BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12BCH_b; + }; + union + { + __IOM uint32_t REG_12C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12C0H_b; + }; + union + { + __IOM uint32_t REG_12C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12C4H_b; + }; + union + { + __IOM uint32_t REG_12C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12C8H_b; + }; + union + { + __IOM uint32_t REG_12CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12CCH_b; + }; + union + { + __IOM uint32_t REG_12D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12D0H_b; + }; + union + { + __IOM uint32_t REG_12D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12D4H_b; + }; + union + { + __IOM uint32_t REG_12D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12D8H_b; + }; + union + { + __IOM uint32_t REG_12DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12DCH_b; + }; + union + { + __IOM uint32_t REG_12E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12E0H_b; + }; + union + { + __IOM uint32_t REG_12E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12E4H_b; + }; + union + { + __IOM uint32_t REG_12E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12E8H_b; + }; + union + { + __IOM uint32_t REG_12ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12ECH_b; + }; + union + { + __IOM uint32_t REG_12F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12F0H_b; + }; + union + { + __IOM uint32_t REG_12F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12F4H_b; + }; + union + { + __IOM uint32_t REG_12F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12F8H_b; + }; + union + { + __IOM uint32_t REG_12FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12FCH_b; + }; + union + { + __IOM uint32_t REG_1300H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1300H_b; + }; + union + { + __IOM uint32_t REG_1304H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1304H_b; + }; + union + { + __IOM uint32_t REG_1308H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1308H_b; + }; + union + { + __IOM uint32_t REG_130CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_130CH_b; + }; + union + { + __IOM uint32_t REG_1310H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1310H_b; + }; + union + { + __IOM uint32_t REG_1314H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1314H_b; + }; + union + { + __IOM uint32_t REG_1318H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1318H_b; + }; + union + { + __IOM uint32_t REG_131CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_131CH_b; + }; + union + { + __IOM uint32_t REG_1320H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1320H_b; + }; + union + { + __IOM uint32_t REG_1324H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1324H_b; + }; + union + { + __IOM uint32_t REG_1328H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1328H_b; + }; + union + { + __IOM uint32_t REG_132CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_132CH_b; + }; + union + { + __IOM uint32_t REG_1330H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1330H_b; + }; + union + { + __IOM uint32_t REG_1334H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1334H_b; + }; + union + { + __IOM uint32_t REG_1338H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1338H_b; + }; + union + { + __IOM uint32_t REG_133CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_133CH_b; + }; + union + { + __IOM uint32_t REG_1340H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1340H_b; + }; + union + { + __IOM uint32_t REG_1344H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1344H_b; + }; + union + { + __IOM uint32_t REG_1348H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1348H_b; + }; + union + { + __IOM uint32_t REG_134CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_134CH_b; + }; + union + { + __IOM uint32_t REG_1350H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1350H_b; + }; + union + { + __IOM uint32_t REG_1354H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1354H_b; + }; + union + { + __IOM uint32_t REG_1358H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1358H_b; + }; + union + { + __IOM uint32_t REG_135CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_135CH_b; + }; + union + { + __IOM uint32_t REG_1360H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1360H_b; + }; + union + { + __IOM uint32_t REG_1364H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1364H_b; + }; + union + { + __IOM uint32_t REG_1368H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1368H_b; + }; + union + { + __IOM uint32_t REG_136CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_136CH_b; + }; + union + { + __IOM uint32_t REG_1370H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1370H_b; + }; + union + { + __IOM uint32_t REG_1374H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1374H_b; + }; + union + { + __IOM uint32_t REG_1378H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1378H_b; + }; + union + { + __IOM uint32_t REG_137CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_137CH_b; + }; + union + { + __IOM uint32_t REG_1380H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1380H_b; + }; + union + { + __IOM uint32_t REG_1384H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1384H_b; + }; + union + { + __IOM uint32_t REG_1388H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1388H_b; + }; + union + { + __IOM uint32_t REG_138CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_138CH_b; + }; + union + { + __IOM uint32_t REG_1390H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1390H_b; + }; + union + { + __IOM uint32_t REG_1394H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1394H_b; + }; + union + { + __IOM uint32_t REG_1398H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1398H_b; + }; + union + { + __IOM uint32_t REG_139CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_139CH_b; + }; + union + { + __IOM uint32_t REG_13A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13A0H_b; + }; + union + { + __IOM uint32_t REG_13A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13A4H_b; + }; + union + { + __IOM uint32_t REG_13A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13A8H_b; + }; + union + { + __IOM uint32_t REG_13ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13ACH_b; + }; + union + { + __IOM uint32_t REG_13B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13B0H_b; + }; + union + { + __IOM uint32_t REG_13B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13B4H_b; + }; + union + { + __IOM uint32_t REG_13B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13B8H_b; + }; + union + { + __IOM uint32_t REG_13BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13BCH_b; + }; + union + { + __IOM uint32_t REG_13C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13C0H_b; + }; + union + { + __IOM uint32_t REG_13C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13C4H_b; + }; + union + { + __IOM uint32_t REG_13C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13C8H_b; + }; + union + { + __IOM uint32_t REG_13CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13CCH_b; + }; + union + { + __IOM uint32_t REG_13D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13D0H_b; + }; + union + { + __IOM uint32_t REG_13D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13D4H_b; + }; + union + { + __IOM uint32_t REG_13D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13D8H_b; + }; + union + { + __IOM uint32_t REG_13DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13DCH_b; + }; + union + { + __IOM uint32_t REG_13E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13E0H_b; + }; + union + { + __IOM uint32_t REG_13E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13E4H_b; + }; + union + { + __IOM uint32_t REG_13E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13E8H_b; + }; + union + { + __IOM uint32_t REG_13ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13ECH_b; + }; + union + { + __IOM uint32_t REG_13F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13F0H_b; + }; + union + { + __IOM uint32_t REG_13F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13F4H_b; + }; + union + { + __IOM uint32_t REG_13F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13F8H_b; + }; + union + { + __IOM uint32_t REG_13FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13FCH_b; + }; + union + { + __IOM uint32_t REG_1400H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1400H_b; + }; + union + { + __IOM uint32_t REG_1404H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1404H_b; + }; + union + { + __IOM uint32_t REG_1408H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1408H_b; + }; + union + { + __IOM uint32_t REG_140CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_140CH_b; + }; + union + { + __IOM uint32_t REG_1410H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1410H_b; + }; + union + { + __IOM uint32_t REG_1414H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1414H_b; + }; + union + { + __IOM uint32_t REG_1418H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1418H_b; + }; + union + { + __IOM uint32_t REG_141CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_141CH_b; + }; + union + { + __IOM uint32_t REG_1420H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1420H_b; + }; + union + { + __IOM uint32_t REG_1424H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1424H_b; + }; + union + { + __IOM uint32_t REG_1428H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1428H_b; + }; + union + { + __IOM uint32_t REG_142CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_142CH_b; + }; + union + { + __IOM uint32_t REG_1430H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1430H_b; + }; + union + { + __IOM uint32_t REG_1434H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1434H_b; + }; + union + { + __IOM uint32_t REG_1438H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1438H_b; + }; + union + { + __IOM uint32_t REG_143CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_143CH_b; + }; + union + { + __IOM uint32_t REG_1440H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1440H_b; + }; + union + { + __IOM uint32_t REG_1444H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1444H_b; + }; + union + { + __IOM uint32_t REG_1448H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1448H_b; + }; + union + { + __IOM uint32_t REG_144CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_144CH_b; + }; + union + { + __IOM uint32_t REG_1450H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1450H_b; + }; + union + { + __IOM uint32_t REG_1454H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1454H_b; + }; + union + { + __IOM uint32_t REG_1458H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1458H_b; + }; + union + { + __IOM uint32_t REG_145CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_145CH_b; + }; + union + { + __IOM uint32_t REG_1460H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1460H_b; + }; + union + { + __IOM uint32_t REG_1464H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1464H_b; + }; + union + { + __IOM uint32_t REG_1468H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1468H_b; + }; + union + { + __IOM uint32_t REG_146CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_146CH_b; + }; + union + { + __IOM uint32_t REG_1470H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1470H_b; + }; + union + { + __IOM uint32_t REG_1474H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1474H_b; + }; + union + { + __IOM uint32_t REG_1478H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1478H_b; + }; + union + { + __IOM uint32_t REG_147CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_147CH_b; + }; + union + { + __IOM uint32_t REG_1480H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1480H_b; + }; + union + { + __IOM uint32_t REG_1484H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1484H_b; + }; + union + { + __IOM uint32_t REG_1488H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1488H_b; + }; + union + { + __IOM uint32_t REG_148CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_148CH_b; + }; + union + { + __IOM uint32_t REG_1490H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1490H_b; + }; + union + { + __IOM uint32_t REG_1494H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1494H_b; + }; + union + { + __IOM uint32_t REG_1498H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1498H_b; + }; + union + { + __IOM uint32_t REG_149CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_149CH_b; + }; + union + { + __IOM uint32_t REG_14A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14A0H_b; + }; + union + { + __IOM uint32_t REG_14A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14A4H_b; + }; + union + { + __IOM uint32_t REG_14A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14A8H_b; + }; + union + { + __IOM uint32_t REG_14ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14ACH_b; + }; + union + { + __IOM uint32_t REG_14B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14B0H_b; + }; + union + { + __IOM uint32_t REG_14B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14B4H_b; + }; + union + { + __IOM uint32_t REG_14B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14B8H_b; + }; + union + { + __IOM uint32_t REG_14BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14BCH_b; + }; + union + { + __IOM uint32_t REG_14C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14C0H_b; + }; + union + { + __IOM uint32_t REG_14C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14C4H_b; + }; + union + { + __IOM uint32_t REG_14C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14C8H_b; + }; + union + { + __IOM uint32_t REG_14CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14CCH_b; + }; + union + { + __IOM uint32_t REG_14D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14D0H_b; + }; + union + { + __IOM uint32_t REG_14D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14D4H_b; + }; + union + { + __IOM uint32_t REG_14D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14D8H_b; + }; + union + { + __IOM uint32_t REG_14DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14DCH_b; + }; + union + { + __IOM uint32_t REG_14E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14E0H_b; + }; + union + { + __IOM uint32_t REG_14E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14E4H_b; + }; + union + { + __IOM uint32_t REG_14E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14E8H_b; + }; + union + { + __IOM uint32_t REG_14ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14ECH_b; + }; + union + { + __IOM uint32_t REG_14F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14F0H_b; + }; + union + { + __IOM uint32_t REG_14F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14F4H_b; + }; + union + { + __IOM uint32_t REG_14F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14F8H_b; + }; + union + { + __IOM uint32_t REG_14FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14FCH_b; + }; + union + { + __IOM uint32_t REG_1500H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1500H_b; + }; + union + { + __IOM uint32_t REG_1504H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1504H_b; + }; + union + { + __IOM uint32_t REG_1508H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1508H_b; + }; + union + { + __IOM uint32_t REG_150CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_150CH_b; + }; + union + { + __IOM uint32_t REG_1510H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1510H_b; + }; + union + { + __IOM uint32_t REG_1514H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1514H_b; + }; + union + { + __IOM uint32_t REG_1518H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1518H_b; + }; + union + { + __IOM uint32_t REG_151CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_151CH_b; + }; + union + { + __IOM uint32_t REG_1520H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1520H_b; + }; + union + { + __IOM uint32_t REG_1524H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1524H_b; + }; + union + { + __IOM uint32_t REG_1528H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1528H_b; + }; + union + { + __IOM uint32_t REG_152CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_152CH_b; + }; + union + { + __IOM uint32_t REG_1530H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1530H_b; + }; + union + { + __IOM uint32_t REG_1534H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1534H_b; + }; + union + { + __IOM uint32_t REG_1538H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1538H_b; + }; + union + { + __IOM uint32_t REG_153CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_153CH_b; + }; + union + { + __IOM uint32_t REG_1540H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1540H_b; + }; + union + { + __IOM uint32_t REG_1544H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1544H_b; + }; + union + { + __IOM uint32_t REG_1548H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1548H_b; + }; + union + { + __IOM uint32_t REG_154CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_154CH_b; + }; + union + { + __IOM uint32_t REG_1550H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1550H_b; + }; + union + { + __IOM uint32_t REG_1554H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1554H_b; + }; + union + { + __IOM uint32_t REG_1558H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1558H_b; + }; + union + { + __IOM uint32_t REG_155CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_155CH_b; + }; + union + { + __IOM uint32_t REG_1560H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1560H_b; + }; + union + { + __IOM uint32_t REG_1564H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1564H_b; + }; + union + { + __IOM uint32_t REG_1568H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1568H_b; + }; + union + { + __IOM uint32_t REG_156CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_156CH_b; + }; + union + { + __IOM uint32_t REG_1570H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1570H_b; + }; + union + { + __IOM uint32_t REG_1574H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1574H_b; + }; + union + { + __IOM uint32_t REG_1578H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1578H_b; + }; + union + { + __IOM uint32_t REG_157CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_157CH_b; + }; + union + { + __IOM uint32_t REG_1580H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1580H_b; + }; + union + { + __IOM uint32_t REG_1584H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1584H_b; + }; + union + { + __IOM uint32_t REG_1588H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1588H_b; + }; + union + { + __IOM uint32_t REG_158CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_158CH_b; + }; + union + { + __IOM uint32_t REG_1590H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1590H_b; + }; + union + { + __IOM uint32_t REG_1594H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1594H_b; + }; + union + { + __IOM uint32_t REG_1598H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1598H_b; + }; + union + { + __IOM uint32_t REG_159CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_159CH_b; + }; + union + { + __IOM uint32_t REG_15A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15A0H_b; + }; + union + { + __IOM uint32_t REG_15A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15A4H_b; + }; + union + { + __IOM uint32_t REG_15A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15A8H_b; + }; + union + { + __IOM uint32_t REG_15ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15ACH_b; + }; + union + { + __IOM uint32_t REG_15B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15B0H_b; + }; + union + { + __IOM uint32_t REG_15B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15B4H_b; + }; + union + { + __IOM uint32_t REG_15B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15B8H_b; + }; + union + { + __IOM uint32_t REG_15BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15BCH_b; + }; + union + { + __IOM uint32_t REG_15C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15C0H_b; + }; + union + { + __IOM uint32_t REG_15C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15C4H_b; + }; + union + { + __IOM uint32_t REG_15C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15C8H_b; + }; + union + { + __IOM uint32_t REG_15CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15CCH_b; + }; + union + { + __IOM uint32_t REG_15D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15D0H_b; + }; + union + { + __IOM uint32_t REG_15D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15D4H_b; + }; + union + { + __IOM uint32_t REG_15D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15D8H_b; + }; + union + { + __IOM uint32_t REG_15DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15DCH_b; + }; + union + { + __IOM uint32_t REG_15E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15E0H_b; + }; + union + { + __IOM uint32_t REG_15E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15E4H_b; + }; + union + { + __IOM uint32_t REG_15E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15E8H_b; + }; + union + { + __IOM uint32_t REG_15ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15ECH_b; + }; + union + { + __IOM uint32_t REG_15F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15F0H_b; + }; + union + { + __IOM uint32_t REG_15F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15F4H_b; + }; + union + { + __IOM uint32_t REG_15F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15F8H_b; + }; + union + { + __IOM uint32_t REG_15FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15FCH_b; + }; + union + { + __IOM uint32_t REG_1600H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1600H_b; + }; + union + { + __IOM uint32_t REG_1604H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1604H_b; + }; + union + { + __IOM uint32_t REG_1608H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1608H_b; + }; + union + { + __IOM uint32_t REG_160CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_160CH_b; + }; + union + { + __IOM uint32_t REG_1610H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1610H_b; + }; + union + { + __IOM uint32_t REG_1614H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1614H_b; + }; + union + { + __IOM uint32_t REG_1618H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1618H_b; + }; + union + { + __IOM uint32_t REG_161CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_161CH_b; + }; + union + { + __IOM uint32_t REG_1620H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1620H_b; + }; + union + { + __IOM uint32_t REG_1624H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1624H_b; + }; + union + { + __IOM uint32_t REG_1628H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1628H_b; + }; + union + { + __IOM uint32_t REG_162CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_162CH_b; + }; + union + { + __IOM uint32_t REG_1630H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1630H_b; + }; + union + { + __IOM uint32_t REG_1634H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1634H_b; + }; + union + { + __IOM uint32_t REG_1638H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1638H_b; + }; + union + { + __IOM uint32_t REG_163CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_163CH_b; + }; + union + { + __IOM uint32_t REG_1640H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1640H_b; + }; + union + { + __IOM uint32_t REG_1644H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1644H_b; + }; + union + { + __IOM uint32_t REG_1648H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1648H_b; + }; + union + { + __IOM uint32_t REG_164CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_164CH_b; + }; + union + { + __IOM uint32_t REG_1650H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1650H_b; + }; + union + { + __IOM uint32_t REG_1654H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1654H_b; + }; + union + { + __IOM uint32_t REG_1658H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1658H_b; + }; + union + { + __IOM uint32_t REG_165CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_165CH_b; + }; + union + { + __IOM uint32_t REG_1660H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1660H_b; + }; + union + { + __IOM uint32_t REG_1664H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1664H_b; + }; + union + { + __IOM uint32_t REG_1668H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1668H_b; + }; + union + { + __IOM uint32_t REG_166CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_166CH_b; + }; + union + { + __IOM uint32_t REG_1670H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1670H_b; + }; + union + { + __IOM uint32_t REG_1674H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1674H_b; + }; + union + { + __IOM uint32_t REG_1678H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1678H_b; + }; + union + { + __IOM uint32_t REG_167CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_167CH_b; + }; + union + { + __IOM uint32_t REG_1680H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1680H_b; + }; + union + { + __IOM uint32_t REG_1684H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1684H_b; + }; + union + { + __IOM uint32_t REG_1688H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1688H_b; + }; + union + { + __IOM uint32_t REG_168CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_168CH_b; + }; + union + { + __IOM uint32_t REG_1690H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1690H_b; + }; + union + { + __IOM uint32_t REG_1694H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1694H_b; + }; + union + { + __IOM uint32_t REG_1698H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1698H_b; + }; + union + { + __IOM uint32_t REG_169CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_169CH_b; + }; + union + { + __IOM uint32_t REG_16A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16A0H_b; + }; + union + { + __IOM uint32_t REG_16A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16A4H_b; + }; + union + { + __IOM uint32_t REG_16A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16A8H_b; + }; + union + { + __IOM uint32_t REG_16ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16ACH_b; + }; + union + { + __IOM uint32_t REG_16B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16B0H_b; + }; + union + { + __IOM uint32_t REG_16B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16B4H_b; + }; + union + { + __IOM uint32_t REG_16B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16B8H_b; + }; + union + { + __IOM uint32_t REG_16BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16BCH_b; + }; + union + { + __IOM uint32_t REG_16C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16C0H_b; + }; + union + { + __IOM uint32_t REG_16C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16C4H_b; + }; + union + { + __IOM uint32_t REG_16C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16C8H_b; + }; + union + { + __IOM uint32_t REG_16CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16CCH_b; + }; + union + { + __IOM uint32_t REG_16D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16D0H_b; + }; + union + { + __IOM uint32_t REG_16D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16D4H_b; + }; + union + { + __IOM uint32_t REG_16D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16D8H_b; + }; + union + { + __IOM uint32_t REG_16DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16DCH_b; + }; + union + { + __IOM uint32_t REG_16E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16E0H_b; + }; + union + { + __IOM uint32_t REG_16E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16E4H_b; + }; + union + { + __IOM uint32_t REG_16E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16E8H_b; + }; + union + { + __IOM uint32_t REG_16ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16ECH_b; + }; + union + { + __IOM uint32_t REG_16F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16F0H_b; + }; + union + { + __IOM uint32_t REG_16F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16F4H_b; + }; + union + { + __IOM uint32_t REG_16F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16F8H_b; + }; + union + { + __IOM uint32_t REG_16FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16FCH_b; + }; + union + { + __IOM uint32_t REG_1700H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1700H_b; + }; + union + { + __IOM uint32_t REG_1704H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1704H_b; + }; + union + { + __IOM uint32_t REG_1708H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1708H_b; + }; + union + { + __IOM uint32_t REG_170CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_170CH_b; + }; + union + { + __IOM uint32_t REG_1710H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1710H_b; + }; + union + { + __IOM uint32_t REG_1714H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1714H_b; + }; + union + { + __IOM uint32_t REG_1718H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1718H_b; + }; + union + { + __IOM uint32_t REG_171CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_171CH_b; + }; + union + { + __IOM uint32_t REG_1720H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1720H_b; + }; + union + { + __IOM uint32_t REG_1724H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1724H_b; + }; + union + { + __IOM uint32_t REG_1728H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1728H_b; + }; + union + { + __IOM uint32_t REG_172CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_172CH_b; + }; + union + { + __IOM uint32_t REG_1730H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1730H_b; + }; + union + { + __IOM uint32_t REG_1734H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1734H_b; + }; + union + { + __IOM uint32_t REG_1738H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1738H_b; + }; + union + { + __IOM uint32_t REG_173CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_173CH_b; + }; + union + { + __IOM uint32_t REG_1740H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1740H_b; + }; + union + { + __IOM uint32_t REG_1744H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1744H_b; + }; + union + { + __IOM uint32_t REG_1748H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1748H_b; + }; + union + { + __IOM uint32_t REG_174CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_174CH_b; + }; + union + { + __IOM uint32_t REG_1750H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1750H_b; + }; + union + { + __IOM uint32_t REG_1754H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1754H_b; + }; + union + { + __IOM uint32_t REG_1758H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1758H_b; + }; + union + { + __IOM uint32_t REG_175CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_175CH_b; + }; + union + { + __IOM uint32_t REG_1760H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1760H_b; + }; + union + { + __IOM uint32_t REG_1764H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1764H_b; + }; + union + { + __IOM uint32_t REG_1768H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1768H_b; + }; + union + { + __IOM uint32_t REG_176CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_176CH_b; + }; + union + { + __IOM uint32_t REG_1770H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1770H_b; + }; + union + { + __IOM uint32_t REG_1774H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1774H_b; + }; + union + { + __IOM uint32_t REG_1778H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1778H_b; + }; + union + { + __IOM uint32_t REG_177CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_177CH_b; + }; + union + { + __IOM uint32_t REG_1780H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1780H_b; + }; + union + { + __IOM uint32_t REG_1784H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1784H_b; + }; + union + { + __IOM uint32_t REG_1788H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1788H_b; + }; + union + { + __IOM uint32_t REG_178CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_178CH_b; + }; + union + { + __IOM uint32_t REG_1790H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1790H_b; + }; + union + { + __IOM uint32_t REG_1794H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1794H_b; + }; + union + { + __IOM uint32_t REG_1798H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1798H_b; + }; + union + { + __IOM uint32_t REG_179CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_179CH_b; + }; + union + { + __IOM uint32_t REG_17A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17A0H_b; + }; + union + { + __IOM uint32_t REG_17A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17A4H_b; + }; + union + { + __IOM uint32_t REG_17A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17A8H_b; + }; + union + { + __IOM uint32_t REG_17ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17ACH_b; + }; + union + { + __IOM uint32_t REG_17B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17B0H_b; + }; + union + { + __IOM uint32_t REG_17B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17B4H_b; + }; + union + { + __IOM uint32_t REG_17B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17B8H_b; + }; + union + { + __IOM uint32_t REG_17BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17BCH_b; + }; + union + { + __IOM uint32_t REG_17C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17C0H_b; + }; + union + { + __IOM uint32_t REG_17C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17C4H_b; + }; + union + { + __IOM uint32_t REG_17C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17C8H_b; + }; + union + { + __IOM uint32_t REG_17CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17CCH_b; + }; + union + { + __IOM uint32_t REG_17D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17D0H_b; + }; + union + { + __IOM uint32_t REG_17D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17D4H_b; + }; + union + { + __IOM uint32_t REG_17D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17D8H_b; + }; + union + { + __IOM uint32_t REG_17DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17DCH_b; + }; + union + { + __IOM uint32_t REG_17E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17E0H_b; + }; + union + { + __IOM uint32_t REG_17E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17E4H_b; + }; + union + { + __IOM uint32_t REG_17E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17E8H_b; + }; + union + { + __IOM uint32_t REG_17ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17ECH_b; + }; + union + { + __IOM uint32_t REG_17F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17F0H_b; + }; + union + { + __IOM uint32_t REG_17F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17F4H_b; + }; + union + { + __IOM uint32_t REG_17F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17F8H_b; + }; + union + { + __IOM uint32_t REG_17FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17FCH_b; + }; + union + { + __IOM uint32_t REG_1800H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1800H_b; + }; + union + { + __IOM uint32_t REG_1804H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1804H_b; + }; + union + { + __IOM uint32_t REG_1808H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1808H_b; + }; + union + { + __IOM uint32_t REG_180CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_180CH_b; + }; + union + { + __IOM uint32_t REG_1810H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1810H_b; + }; + union + { + __IOM uint32_t REG_1814H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1814H_b; + }; + union + { + __IOM uint32_t REG_1818H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1818H_b; + }; + union + { + __IOM uint32_t REG_181CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_181CH_b; + }; + union + { + __IOM uint32_t REG_1820H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1820H_b; + }; + union + { + __IOM uint32_t REG_1824H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1824H_b; + }; + union + { + __IOM uint32_t REG_1828H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1828H_b; + }; + union + { + __IOM uint32_t REG_182CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_182CH_b; + }; + union + { + __IOM uint32_t REG_1830H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1830H_b; + }; + union + { + __IOM uint32_t REG_1834H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1834H_b; + }; + union + { + __IOM uint32_t REG_1838H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1838H_b; + }; + union + { + __IOM uint32_t REG_183CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_183CH_b; + }; + union + { + __IOM uint32_t REG_1840H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1840H_b; + }; + union + { + __IOM uint32_t REG_1844H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1844H_b; + }; + union + { + __IOM uint32_t REG_1848H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1848H_b; + }; + union + { + __IOM uint32_t REG_184CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_184CH_b; + }; + union + { + __IOM uint32_t REG_1850H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1850H_b; + }; + union + { + __IOM uint32_t REG_1854H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1854H_b; + }; + union + { + __IOM uint32_t REG_1858H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1858H_b; + }; + union + { + __IOM uint32_t REG_185CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_185CH_b; + }; + union + { + __IOM uint32_t REG_1860H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1860H_b; + }; + union + { + __IOM uint32_t REG_1864H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1864H_b; + }; + union + { + __IOM uint32_t REG_1868H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1868H_b; + }; + union + { + __IOM uint32_t REG_186CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_186CH_b; + }; + union + { + __IOM uint32_t REG_1870H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1870H_b; + }; + union + { + __IOM uint32_t REG_1874H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1874H_b; + }; + union + { + __IOM uint32_t REG_1878H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1878H_b; + }; + union + { + __IOM uint32_t REG_187CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_187CH_b; + }; + union + { + __IOM uint32_t REG_1880H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1880H_b; + }; + union + { + __IOM uint32_t REG_1884H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1884H_b; + }; + union + { + __IOM uint32_t REG_1888H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1888H_b; + }; + union + { + __IOM uint32_t REG_188CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_188CH_b; + }; + union + { + __IOM uint32_t REG_1890H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1890H_b; + }; + union + { + __IOM uint32_t REG_1894H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1894H_b; + }; + union + { + __IOM uint32_t REG_1898H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1898H_b; + }; + union + { + __IOM uint32_t REG_189CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_189CH_b; + }; + union + { + __IOM uint32_t REG_18A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18A0H_b; + }; + union + { + __IOM uint32_t REG_18A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18A4H_b; + }; + union + { + __IOM uint32_t REG_18A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18A8H_b; + }; + union + { + __IOM uint32_t REG_18ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18ACH_b; + }; + union + { + __IOM uint32_t REG_18B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18B0H_b; + }; + union + { + __IOM uint32_t REG_18B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18B4H_b; + }; + union + { + __IOM uint32_t REG_18B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18B8H_b; + }; + union + { + __IOM uint32_t REG_18BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18BCH_b; + }; + union + { + __IOM uint32_t REG_18C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18C0H_b; + }; + union + { + __IOM uint32_t REG_18C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18C4H_b; + }; + union + { + __IOM uint32_t REG_18C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18C8H_b; + }; + union + { + __IOM uint32_t REG_18CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18CCH_b; + }; + union + { + __IOM uint32_t REG_18D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18D0H_b; + }; + union + { + __IOM uint32_t REG_18D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18D4H_b; + }; + union + { + __IOM uint32_t REG_18D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18D8H_b; + }; + union + { + __IOM uint32_t REG_18DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18DCH_b; + }; + union + { + __IOM uint32_t REG_18E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18E0H_b; + }; + union + { + __IOM uint32_t REG_18E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18E4H_b; + }; + union + { + __IOM uint32_t REG_18E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18E8H_b; + }; + union + { + __IOM uint32_t REG_18ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18ECH_b; + }; + union + { + __IOM uint32_t REG_18F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18F0H_b; + }; + union + { + __IOM uint32_t REG_18F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18F4H_b; + }; + union + { + __IOM uint32_t REG_18F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18F8H_b; + }; + union + { + __IOM uint32_t REG_18FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18FCH_b; + }; + union + { + __IOM uint32_t REG_1900H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1900H_b; + }; + union + { + __IOM uint32_t REG_1904H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1904H_b; + }; + union + { + __IOM uint32_t REG_1908H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1908H_b; + }; + union + { + __IOM uint32_t REG_190CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_190CH_b; + }; + union + { + __IOM uint32_t REG_1910H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1910H_b; + }; + union + { + __IOM uint32_t REG_1914H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1914H_b; + }; + union + { + __IOM uint32_t REG_1918H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1918H_b; + }; + union + { + __IOM uint32_t REG_191CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_191CH_b; + }; + union + { + __IOM uint32_t REG_1920H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1920H_b; + }; + union + { + __IOM uint32_t REG_1924H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1924H_b; + }; + union + { + __IOM uint32_t REG_1928H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1928H_b; + }; + union + { + __IOM uint32_t REG_192CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_192CH_b; + }; + union + { + __IOM uint32_t REG_1930H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1930H_b; + }; + union + { + __IOM uint32_t REG_1934H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1934H_b; + }; + union + { + __IOM uint32_t REG_1938H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1938H_b; + }; + union + { + __IOM uint32_t REG_193CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_193CH_b; + }; + union + { + __IOM uint32_t REG_1940H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1940H_b; + }; + union + { + __IOM uint32_t REG_1944H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1944H_b; + }; + union + { + __IOM uint32_t REG_1948H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1948H_b; + }; + union + { + __IOM uint32_t REG_194CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_194CH_b; + }; + union + { + __IOM uint32_t REG_1950H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1950H_b; + }; + union + { + __IOM uint32_t REG_1954H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1954H_b; + }; + union + { + __IOM uint32_t REG_1958H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1958H_b; + }; + union + { + __IOM uint32_t REG_195CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_195CH_b; + }; + union + { + __IOM uint32_t REG_1960H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1960H_b; + }; + union + { + __IOM uint32_t REG_1964H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1964H_b; + }; + union + { + __IOM uint32_t REG_1968H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1968H_b; + }; + union + { + __IOM uint32_t REG_196CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_196CH_b; + }; + union + { + __IOM uint32_t REG_1970H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1970H_b; + }; + union + { + __IOM uint32_t REG_1974H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1974H_b; + }; + union + { + __IOM uint32_t REG_1978H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1978H_b; + }; + union + { + __IOM uint32_t REG_197CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_197CH_b; + }; + union + { + __IOM uint32_t REG_1980H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1980H_b; + }; + union + { + __IOM uint32_t REG_1984H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1984H_b; + }; + union + { + __IOM uint32_t REG_1988H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1988H_b; + }; + union + { + __IOM uint32_t REG_198CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_198CH_b; + }; + union + { + __IOM uint32_t REG_1990H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1990H_b; + }; + union + { + __IOM uint32_t REG_1994H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1994H_b; + }; + union + { + __IOM uint32_t REG_1998H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1998H_b; + }; + union + { + __IOM uint32_t REG_199CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_199CH_b; + }; + union + { + __IOM uint32_t REG_19A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19A0H_b; + }; + union + { + __IOM uint32_t REG_19A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19A4H_b; + }; + union + { + __IOM uint32_t REG_19A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19A8H_b; + }; + union + { + __IOM uint32_t REG_19ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19ACH_b; + }; + union + { + __IOM uint32_t REG_19B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19B0H_b; + }; + union + { + __IOM uint32_t REG_19B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19B4H_b; + }; + union + { + __IOM uint32_t REG_19B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19B8H_b; + }; + union + { + __IOM uint32_t REG_19BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19BCH_b; + }; + union + { + __IOM uint32_t REG_19C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19C0H_b; + }; + union + { + __IOM uint32_t REG_19C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19C4H_b; + }; + union + { + __IOM uint32_t REG_19C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19C8H_b; + }; + union + { + __IOM uint32_t REG_19CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19CCH_b; + }; + union + { + __IOM uint32_t REG_19D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19D0H_b; + }; + union + { + __IOM uint32_t REG_19D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19D4H_b; + }; + union + { + __IOM uint32_t REG_19D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19D8H_b; + }; + union + { + __IOM uint32_t REG_19DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19DCH_b; + }; + union + { + __IOM uint32_t REG_19E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19E0H_b; + }; + union + { + __IOM uint32_t REG_19E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19E4H_b; + }; + union + { + __IOM uint32_t REG_19E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19E8H_b; + }; + union + { + __IOM uint32_t REG_19ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19ECH_b; + }; + union + { + __IOM uint32_t REG_19F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19F0H_b; + }; + union + { + __IOM uint32_t REG_19F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19F4H_b; + }; + union + { + __IOM uint32_t REG_19F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19F8H_b; + }; + union + { + __IOM uint32_t REG_19FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19FCH_b; + }; + union + { + __IOM uint32_t REG_1A00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A00H_b; + }; + union + { + __IOM uint32_t REG_1A04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A04H_b; + }; + union + { + __IOM uint32_t REG_1A08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A08H_b; + }; + union + { + __IOM uint32_t REG_1A0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A0CH_b; + }; + union + { + __IOM uint32_t REG_1A10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A10H_b; + }; + union + { + __IOM uint32_t REG_1A14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A14H_b; + }; + union + { + __IOM uint32_t REG_1A18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A18H_b; + }; + union + { + __IOM uint32_t REG_1A1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A1CH_b; + }; + union + { + __IOM uint32_t REG_1A20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A20H_b; + }; + union + { + __IOM uint32_t REG_1A24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A24H_b; + }; + union + { + __IOM uint32_t REG_1A28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A28H_b; + }; + union + { + __IOM uint32_t REG_1A2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A2CH_b; + }; + union + { + __IOM uint32_t REG_1A30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A30H_b; + }; + union + { + __IOM uint32_t REG_1A34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A34H_b; + }; + union + { + __IOM uint32_t REG_1A38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A38H_b; + }; + union + { + __IOM uint32_t REG_1A3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A3CH_b; + }; + union + { + __IOM uint32_t REG_1A40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A40H_b; + }; + union + { + __IOM uint32_t REG_1A44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A44H_b; + }; + union + { + __IOM uint32_t REG_1A48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A48H_b; + }; + union + { + __IOM uint32_t REG_1A4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A4CH_b; + }; + union + { + __IOM uint32_t REG_1A50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A50H_b; + }; + union + { + __IOM uint32_t REG_1A54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A54H_b; + }; + union + { + __IOM uint32_t REG_1A58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A58H_b; + }; + union + { + __IOM uint32_t REG_1A5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A5CH_b; + }; + union + { + __IOM uint32_t REG_1A60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A60H_b; + }; + union + { + __IOM uint32_t REG_1A64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A64H_b; + }; + union + { + __IOM uint32_t REG_1A68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A68H_b; + }; + union + { + __IOM uint32_t REG_1A6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A6CH_b; + }; + union + { + __IOM uint32_t REG_1A70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A70H_b; + }; + union + { + __IOM uint32_t REG_1A74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A74H_b; + }; + union + { + __IOM uint32_t REG_1A78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A78H_b; + }; + union + { + __IOM uint32_t REG_1A7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A7CH_b; + }; + union + { + __IOM uint32_t REG_1A80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A80H_b; + }; + union + { + __IOM uint32_t REG_1A84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A84H_b; + }; + union + { + __IOM uint32_t REG_1A88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A88H_b; + }; + union + { + __IOM uint32_t REG_1A8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A8CH_b; + }; + union + { + __IOM uint32_t REG_1A90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A90H_b; + }; + union + { + __IOM uint32_t REG_1A94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A94H_b; + }; + union + { + __IOM uint32_t REG_1A98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A98H_b; + }; + union + { + __IOM uint32_t REG_1A9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A9CH_b; + }; + union + { + __IOM uint32_t REG_1AA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AA0H_b; + }; + union + { + __IOM uint32_t REG_1AA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AA4H_b; + }; + union + { + __IOM uint32_t REG_1AA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AA8H_b; + }; + union + { + __IOM uint32_t REG_1AACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AACH_b; + }; + union + { + __IOM uint32_t REG_1AB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AB0H_b; + }; + union + { + __IOM uint32_t REG_1AB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AB4H_b; + }; + union + { + __IOM uint32_t REG_1AB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AB8H_b; + }; + union + { + __IOM uint32_t REG_1ABCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1ABCH_b; + }; + union + { + __IOM uint32_t REG_1AC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AC0H_b; + }; + union + { + __IOM uint32_t REG_1AC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AC4H_b; + }; + union + { + __IOM uint32_t REG_1AC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AC8H_b; + }; + union + { + __IOM uint32_t REG_1ACCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1ACCH_b; + }; + union + { + __IOM uint32_t REG_1AD0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AD0H_b; + }; + union + { + __IOM uint32_t REG_1AD4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AD4H_b; + }; + union + { + __IOM uint32_t REG_1AD8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AD8H_b; + }; + union + { + __IOM uint32_t REG_1ADCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1ADCH_b; + }; + union + { + __IOM uint32_t REG_1AE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AE0H_b; + }; + union + { + __IOM uint32_t REG_1AE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AE4H_b; + }; + union + { + __IOM uint32_t REG_1AE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AE8H_b; + }; + union + { + __IOM uint32_t REG_1AECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AECH_b; + }; + union + { + __IOM uint32_t REG_1AF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AF0H_b; + }; + union + { + __IOM uint32_t REG_1AF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AF4H_b; + }; + union + { + __IOM uint32_t REG_1AF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AF8H_b; + }; + union + { + __IOM uint32_t REG_1AFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AFCH_b; + }; + union + { + __IOM uint32_t REG_1B00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B00H_b; + }; + union + { + __IOM uint32_t REG_1B04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B04H_b; + }; + union + { + __IOM uint32_t REG_1B08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B08H_b; + }; + union + { + __IOM uint32_t REG_1B0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B0CH_b; + }; + union + { + __IOM uint32_t REG_1B10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B10H_b; + }; + union + { + __IOM uint32_t REG_1B14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B14H_b; + }; + union + { + __IOM uint32_t REG_1B18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B18H_b; + }; + union + { + __IOM uint32_t REG_1B1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B1CH_b; + }; + union + { + __IOM uint32_t REG_1B20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B20H_b; + }; + union + { + __IOM uint32_t REG_1B24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B24H_b; + }; + union + { + __IOM uint32_t REG_1B28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B28H_b; + }; + union + { + __IOM uint32_t REG_1B2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B2CH_b; + }; + union + { + __IOM uint32_t REG_1B30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B30H_b; + }; + union + { + __IOM uint32_t REG_1B34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B34H_b; + }; + union + { + __IOM uint32_t REG_1B38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B38H_b; + }; + union + { + __IOM uint32_t REG_1B3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B3CH_b; + }; + union + { + __IOM uint32_t REG_1B40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B40H_b; + }; + union + { + __IOM uint32_t REG_1B44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B44H_b; + }; + union + { + __IOM uint32_t REG_1B48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B48H_b; + }; + union + { + __IOM uint32_t REG_1B4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B4CH_b; + }; + union + { + __IOM uint32_t REG_1B50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B50H_b; + }; + union + { + __IOM uint32_t REG_1B54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B54H_b; + }; + union + { + __IOM uint32_t REG_1B58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B58H_b; + }; + union + { + __IOM uint32_t REG_1B5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B5CH_b; + }; + union + { + __IOM uint32_t REG_1B60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B60H_b; + }; + union + { + __IOM uint32_t REG_1B64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B64H_b; + }; + union + { + __IOM uint32_t REG_1B68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B68H_b; + }; + union + { + __IOM uint32_t REG_1B6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B6CH_b; + }; + union + { + __IOM uint32_t REG_1B70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B70H_b; + }; + union + { + __IOM uint32_t REG_1B74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B74H_b; + }; + union + { + __IOM uint32_t REG_1B78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B78H_b; + }; + union + { + __IOM uint32_t REG_1B7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B7CH_b; + }; + union + { + __IOM uint32_t REG_1B80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B80H_b; + }; + union + { + __IOM uint32_t REG_1B84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B84H_b; + }; + union + { + __IOM uint32_t REG_1B88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B88H_b; + }; + union + { + __IOM uint32_t REG_1B8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B8CH_b; + }; + union + { + __IOM uint32_t REG_1B90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B90H_b; + }; + union + { + __IOM uint32_t REG_1B94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B94H_b; + }; + union + { + __IOM uint32_t REG_1B98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B98H_b; + }; + union + { + __IOM uint32_t REG_1B9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B9CH_b; + }; + union + { + __IOM uint32_t REG_1BA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BA0H_b; + }; + union + { + __IOM uint32_t REG_1BA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BA4H_b; + }; + union + { + __IOM uint32_t REG_1BA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BA8H_b; + }; + union + { + __IOM uint32_t REG_1BACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BACH_b; + }; + union + { + __IOM uint32_t REG_1BB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BB0H_b; + }; + union + { + __IOM uint32_t REG_1BB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BB4H_b; + }; + union + { + __IOM uint32_t REG_1BB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BB8H_b; + }; + union + { + __IOM uint32_t REG_1BBCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BBCH_b; + }; + union + { + __IOM uint32_t REG_1BC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BC0H_b; + }; + union + { + __IOM uint32_t REG_1BC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BC4H_b; + }; + union + { + __IOM uint32_t REG_1BC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BC8H_b; + }; + union + { + __IOM uint32_t REG_1BCCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BCCH_b; + }; + union + { + __IOM uint32_t REG_1BD0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BD0H_b; + }; + union + { + __IOM uint32_t REG_1BD4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BD4H_b; + }; + union + { + __IOM uint32_t REG_1BD8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BD8H_b; + }; + union + { + __IOM uint32_t REG_1BDCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BDCH_b; + }; + union + { + __IOM uint32_t REG_1BE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BE0H_b; + }; + union + { + __IOM uint32_t REG_1BE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BE4H_b; + }; + union + { + __IOM uint32_t REG_1BE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BE8H_b; + }; + union + { + __IOM uint32_t REG_1BECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BECH_b; + }; + union + { + __IOM uint32_t REG_1BF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BF0H_b; + }; + union + { + __IOM uint32_t REG_1BF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BF4H_b; + }; + union + { + __IOM uint32_t REG_1BF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BF8H_b; + }; + union + { + __IOM uint32_t REG_1BFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BFCH_b; + }; + union + { + __IOM uint32_t REG_1C00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C00H_b; + }; + union + { + __IOM uint32_t REG_1C04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C04H_b; + }; + union + { + __IOM uint32_t REG_1C08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C08H_b; + }; + union + { + __IOM uint32_t REG_1C0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C0CH_b; + }; + union + { + __IOM uint32_t REG_1C10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C10H_b; + }; + union + { + __IOM uint32_t REG_1C14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C14H_b; + }; + union + { + __IOM uint32_t REG_1C18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C18H_b; + }; + union + { + __IOM uint32_t REG_1C1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C1CH_b; + }; + union + { + __IOM uint32_t REG_1C20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C20H_b; + }; + union + { + __IOM uint32_t REG_1C24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C24H_b; + }; + union + { + __IOM uint32_t REG_1C28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C28H_b; + }; + union + { + __IOM uint32_t REG_1C2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C2CH_b; + }; + union + { + __IOM uint32_t REG_1C30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C30H_b; + }; + union + { + __IOM uint32_t REG_1C34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C34H_b; + }; + union + { + __IOM uint32_t REG_1C38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C38H_b; + }; + union + { + __IOM uint32_t REG_1C3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C3CH_b; + }; + union + { + __IOM uint32_t REG_1C40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C40H_b; + }; + union + { + __IOM uint32_t REG_1C44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C44H_b; + }; + union + { + __IOM uint32_t REG_1C48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C48H_b; + }; + union + { + __IOM uint32_t REG_1C4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C4CH_b; + }; + union + { + __IOM uint32_t REG_1C50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C50H_b; + }; + union + { + __IOM uint32_t REG_1C54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C54H_b; + }; + union + { + __IOM uint32_t REG_1C58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C58H_b; + }; + union + { + __IOM uint32_t REG_1C5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C5CH_b; + }; + union + { + __IOM uint32_t REG_1C60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C60H_b; + }; + union + { + __IOM uint32_t REG_1C64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C64H_b; + }; + union + { + __IOM uint32_t REG_1C68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C68H_b; + }; + union + { + __IOM uint32_t REG_1C6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C6CH_b; + }; + union + { + __IOM uint32_t REG_1C70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C70H_b; + }; + union + { + __IOM uint32_t REG_1C74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C74H_b; + }; + union + { + __IOM uint32_t REG_1C78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C78H_b; + }; + union + { + __IOM uint32_t REG_1C7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C7CH_b; + }; + union + { + __IOM uint32_t REG_1C80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C80H_b; + }; + union + { + __IOM uint32_t REG_1C84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C84H_b; + }; + union + { + __IOM uint32_t REG_1C88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C88H_b; + }; + union + { + __IOM uint32_t REG_1C8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C8CH_b; + }; + union + { + __IOM uint32_t REG_1C90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C90H_b; + }; + union + { + __IOM uint32_t REG_1C94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C94H_b; + }; + union + { + __IOM uint32_t REG_1C98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C98H_b; + }; + union + { + __IOM uint32_t REG_1C9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C9CH_b; + }; + union + { + __IOM uint32_t REG_1CA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CA0H_b; + }; + union + { + __IOM uint32_t REG_1CA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CA4H_b; + }; + union + { + __IOM uint32_t REG_1CA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CA8H_b; + }; + union + { + __IOM uint32_t REG_1CACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CACH_b; + }; + union + { + __IOM uint32_t REG_1CB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CB0H_b; + }; + union + { + __IOM uint32_t REG_1CB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CB4H_b; + }; + union + { + __IOM uint32_t REG_1CB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CB8H_b; + }; + union + { + __IOM uint32_t REG_1CBCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CBCH_b; + }; + union + { + __IOM uint32_t REG_1CC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CC0H_b; + }; + union + { + __IOM uint32_t REG_1CC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CC4H_b; + }; + union + { + __IOM uint32_t REG_1CC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CC8H_b; + }; + union + { + __IOM uint32_t REG_1CCCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CCCH_b; + }; + union + { + __IOM uint32_t REG_1CD0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CD0H_b; + }; + union + { + __IOM uint32_t REG_1CD4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CD4H_b; + }; + union + { + __IOM uint32_t REG_1CD8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CD8H_b; + }; + union + { + __IOM uint32_t REG_1CDCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CDCH_b; + }; + union + { + __IOM uint32_t REG_1CE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CE0H_b; + }; + union + { + __IOM uint32_t REG_1CE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CE4H_b; + }; + union + { + __IOM uint32_t REG_1CE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CE8H_b; + }; + union + { + __IOM uint32_t REG_1CECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CECH_b; + }; + union + { + __IOM uint32_t REG_1CF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CF0H_b; + }; + union + { + __IOM uint32_t REG_1CF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CF4H_b; + }; + union + { + __IOM uint32_t REG_1CF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CF8H_b; + }; + union + { + __IOM uint32_t REG_1CFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CFCH_b; + }; + union + { + __IOM uint32_t REG_1D00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D00H_b; + }; + union + { + __IOM uint32_t REG_1D04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D04H_b; + }; + union + { + __IOM uint32_t REG_1D08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D08H_b; + }; + union + { + __IOM uint32_t REG_1D0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D0CH_b; + }; + union + { + __IOM uint32_t REG_1D10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D10H_b; + }; + union + { + __IOM uint32_t REG_1D14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D14H_b; + }; + union + { + __IOM uint32_t REG_1D18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D18H_b; + }; + union + { + __IOM uint32_t REG_1D1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D1CH_b; + }; + union + { + __IOM uint32_t REG_1D20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D20H_b; + }; + union + { + __IOM uint32_t REG_1D24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D24H_b; + }; + union + { + __IOM uint32_t REG_1D28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D28H_b; + }; + union + { + __IOM uint32_t REG_1D2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D2CH_b; + }; + union + { + __IOM uint32_t REG_1D30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D30H_b; + }; + union + { + __IOM uint32_t REG_1D34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D34H_b; + }; + union + { + __IOM uint32_t REG_1D38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D38H_b; + }; + union + { + __IOM uint32_t REG_1D3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D3CH_b; + }; + union + { + __IOM uint32_t REG_1D40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D40H_b; + }; + union + { + __IOM uint32_t REG_1D44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D44H_b; + }; + union + { + __IOM uint32_t REG_1D48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D48H_b; + }; + union + { + __IOM uint32_t REG_1D4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D4CH_b; + }; + union + { + __IOM uint32_t REG_1D50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D50H_b; + }; + union + { + __IOM uint32_t REG_1D54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D54H_b; + }; + union + { + __IOM uint32_t REG_1D58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D58H_b; + }; + union + { + __IOM uint32_t REG_1D5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D5CH_b; + }; + union + { + __IOM uint32_t REG_1D60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D60H_b; + }; + union + { + __IOM uint32_t REG_1D64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D64H_b; + }; + union + { + __IOM uint32_t REG_1D68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D68H_b; + }; + union + { + __IOM uint32_t REG_1D6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D6CH_b; + }; + union + { + __IOM uint32_t REG_1D70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D70H_b; + }; + union + { + __IOM uint32_t REG_1D74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D74H_b; + }; + union + { + __IOM uint32_t REG_1D78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D78H_b; + }; + union + { + __IOM uint32_t REG_1D7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D7CH_b; + }; + union + { + __IOM uint32_t REG_1D80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D80H_b; + }; + union + { + __IOM uint32_t REG_1D84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D84H_b; + }; + union + { + __IOM uint32_t REG_1D88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D88H_b; + }; + union + { + __IOM uint32_t REG_1D8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D8CH_b; + }; + union + { + __IOM uint32_t REG_1D90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D90H_b; + }; + union + { + __IOM uint32_t REG_1D94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D94H_b; + }; + union + { + __IOM uint32_t REG_1D98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D98H_b; + }; + union + { + __IOM uint32_t REG_1D9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D9CH_b; + }; + union + { + __IOM uint32_t REG_1DA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DA0H_b; + }; + union + { + __IOM uint32_t REG_1DA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DA4H_b; + }; + union + { + __IOM uint32_t REG_1DA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DA8H_b; + }; + union + { + __IOM uint32_t REG_1DACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DACH_b; + }; + union + { + __IOM uint32_t REG_1DB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DB0H_b; + }; + union + { + __IOM uint32_t REG_1DB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DB4H_b; + }; + union + { + __IOM uint32_t REG_1DB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DB8H_b; + }; + union + { + __IOM uint32_t REG_1DBCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DBCH_b; + }; + union + { + __IOM uint32_t REG_1DC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DC0H_b; + }; + union + { + __IOM uint32_t REG_1DC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DC4H_b; + }; + union + { + __IOM uint32_t REG_1DC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DC8H_b; + }; + union + { + __IOM uint32_t REG_1DCCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DCCH_b; + }; + union + { + __IOM uint32_t REG_1DD0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DD0H_b; + }; + union + { + __IOM uint32_t REG_1DD4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DD4H_b; + }; + union + { + __IOM uint32_t REG_1DD8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DD8H_b; + }; + union + { + __IOM uint32_t REG_1DDCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DDCH_b; + }; + union + { + __IOM uint32_t REG_1DE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DE0H_b; + }; + union + { + __IOM uint32_t REG_1DE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DE4H_b; + }; + union + { + __IOM uint32_t REG_1DE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DE8H_b; + }; + union + { + __IOM uint32_t REG_1DECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DECH_b; + }; + union + { + __IOM uint32_t REG_1DF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DF0H_b; + }; + union + { + __IOM uint32_t REG_1DF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DF4H_b; + }; + union + { + __IOM uint32_t REG_1DF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DF8H_b; + }; + union + { + __IOM uint32_t REG_1DFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DFCH_b; + }; + union + { + __IOM uint32_t REG_1E00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E00H_b; + }; + union + { + __IOM uint32_t REG_1E04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E04H_b; + }; + union + { + __IOM uint32_t REG_1E08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E08H_b; + }; + union + { + __IOM uint32_t REG_1E0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E0CH_b; + }; + union + { + __IOM uint32_t REG_1E10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E10H_b; + }; + union + { + __IOM uint32_t REG_1E14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E14H_b; + }; + union + { + __IOM uint32_t REG_1E18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E18H_b; + }; + union + { + __IOM uint32_t REG_1E1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E1CH_b; + }; + union + { + __IOM uint32_t REG_1E20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E20H_b; + }; + union + { + __IOM uint32_t REG_1E24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E24H_b; + }; + union + { + __IOM uint32_t REG_1E28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E28H_b; + }; + union + { + __IOM uint32_t REG_1E2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E2CH_b; + }; + union + { + __IOM uint32_t REG_1E30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E30H_b; + }; + union + { + __IOM uint32_t REG_1E34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E34H_b; + }; + union + { + __IOM uint32_t REG_1E38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E38H_b; + }; + union + { + __IOM uint32_t REG_1E3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E3CH_b; + }; + union + { + __IOM uint32_t REG_1E40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E40H_b; + }; + union + { + __IOM uint32_t REG_1E44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E44H_b; + }; + union + { + __IOM uint32_t REG_1E48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E48H_b; + }; + union + { + __IOM uint32_t REG_1E4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E4CH_b; + }; + union + { + __IOM uint32_t REG_1E50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E50H_b; + }; + union + { + __IOM uint32_t REG_1E54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E54H_b; + }; + union + { + __IOM uint32_t REG_1E58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E58H_b; + }; + union + { + __IOM uint32_t REG_1E5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E5CH_b; + }; + union + { + __IOM uint32_t REG_1E60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E60H_b; + }; + union + { + __IOM uint32_t REG_1E64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E64H_b; + }; + union + { + __IOM uint32_t REG_1E68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E68H_b; + }; + union + { + __IOM uint32_t REG_1E6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E6CH_b; + }; + union + { + __IOM uint32_t REG_1E70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E70H_b; + }; + union + { + __IOM uint32_t REG_1E74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E74H_b; + }; + union + { + __IOM uint32_t REG_1E78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E78H_b; + }; + union + { + __IOM uint32_t REG_1E7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E7CH_b; + }; + union + { + __IOM uint32_t REG_1E80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E80H_b; + }; + union + { + __IOM uint32_t REG_1E84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E84H_b; + }; + union + { + __IOM uint32_t REG_1E88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E88H_b; + }; + union + { + __IOM uint32_t REG_1E8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E8CH_b; + }; + union + { + __IOM uint32_t REG_1E90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E90H_b; + }; + union + { + __IOM uint32_t REG_1E94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E94H_b; + }; + union + { + __IOM uint32_t REG_1E98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E98H_b; + }; + union + { + __IOM uint32_t REG_1E9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E9CH_b; + }; + union + { + __IOM uint32_t REG_1EA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EA0H_b; + }; + union + { + __IOM uint32_t REG_1EA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EA4H_b; + }; + union + { + __IOM uint32_t REG_1EA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EA8H_b; + }; + union + { + __IOM uint32_t REG_1EACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EACH_b; + }; + union + { + __IOM uint32_t REG_1EB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EB0H_b; + }; + union + { + __IOM uint32_t REG_1EB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EB4H_b; + }; + union + { + __IOM uint32_t REG_1EB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EB8H_b; + }; + union + { + __IOM uint32_t REG_1EBCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EBCH_b; + }; + union + { + __IOM uint32_t REG_1EC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EC0H_b; + }; + union + { + __IOM uint32_t REG_1EC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EC4H_b; + }; + union + { + __IOM uint32_t REG_1EC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EC8H_b; + }; + union + { + __IOM uint32_t REG_1ECCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1ECCH_b; + }; + union + { + __IOM uint32_t REG_1ED0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1ED0H_b; + }; + union + { + __IOM uint32_t REG_1ED4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1ED4H_b; + }; + union + { + __IOM uint32_t REG_1ED8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1ED8H_b; + }; + union + { + __IOM uint32_t REG_1EDCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EDCH_b; + }; + union + { + __IOM uint32_t REG_1EE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EE0H_b; + }; + union + { + __IOM uint32_t REG_1EE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EE4H_b; + }; + union + { + __IOM uint32_t REG_1EE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EE8H_b; + }; + union + { + __IOM uint32_t REG_1EECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EECH_b; + }; + union + { + __IOM uint32_t REG_1EF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EF0H_b; + }; + union + { + __IOM uint32_t REG_1EF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EF4H_b; + }; + union + { + __IOM uint32_t REG_1EF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EF8H_b; + }; + union + { + __IOM uint32_t REG_1EFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EFCH_b; + }; + union + { + __IOM uint32_t REG_1F00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F00H_b; + }; + union + { + __IOM uint32_t REG_1F04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F04H_b; + }; + union + { + __IOM uint32_t REG_1F08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F08H_b; + }; + union + { + __IOM uint32_t REG_1F0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F0CH_b; + }; + union + { + __IOM uint32_t REG_1F10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F10H_b; + }; + union + { + __IOM uint32_t REG_1F14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F14H_b; + }; + union + { + __IOM uint32_t REG_1F18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F18H_b; + }; + union + { + __IOM uint32_t REG_1F1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F1CH_b; + }; + union + { + __IOM uint32_t REG_1F20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F20H_b; + }; + union + { + __IOM uint32_t REG_1F24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F24H_b; + }; + union + { + __IOM uint32_t REG_1F28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F28H_b; + }; + union + { + __IOM uint32_t REG_1F2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F2CH_b; + }; + union + { + __IOM uint32_t REG_1F30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F30H_b; + }; + union + { + __IOM uint32_t REG_1F34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F34H_b; + }; + union + { + __IOM uint32_t REG_1F38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F38H_b; + }; + union + { + __IOM uint32_t REG_1F3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F3CH_b; + }; + union + { + __IOM uint32_t REG_1F40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F40H_b; + }; + union + { + __IOM uint32_t REG_1F44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F44H_b; + }; + union + { + __IOM uint32_t REG_1F48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F48H_b; + }; + union + { + __IOM uint32_t REG_1F4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F4CH_b; + }; + union + { + __IOM uint32_t REG_1F50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F50H_b; + }; + union + { + __IOM uint32_t REG_1F54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F54H_b; + }; + union + { + __IOM uint32_t REG_1F58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F58H_b; + }; + union + { + __IOM uint32_t REG_1F5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F5CH_b; + }; + union + { + __IOM uint32_t REG_1F60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F60H_b; + }; + union + { + __IOM uint32_t REG_1F64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F64H_b; + }; + union + { + __IOM uint32_t REG_1F68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F68H_b; + }; + union + { + __IOM uint32_t REG_1F6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F6CH_b; + }; + union + { + __IOM uint32_t REG_1F70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F70H_b; + }; + union + { + __IOM uint32_t REG_1F74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F74H_b; + }; + union + { + __IOM uint32_t REG_1F78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F78H_b; + }; + union + { + __IOM uint32_t REG_1F7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F7CH_b; + }; + union + { + __IOM uint32_t REG_1F80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F80H_b; + }; + union + { + __IOM uint32_t REG_1F84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F84H_b; + }; + union + { + __IOM uint32_t REG_1F88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F88H_b; + }; + union + { + __IOM uint32_t REG_1F8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F8CH_b; + }; + union + { + __IOM uint32_t REG_1F90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F90H_b; + }; + union + { + __IOM uint32_t REG_1F94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F94H_b; + }; + union + { + __IOM uint32_t REG_1F98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F98H_b; + }; + union + { + __IOM uint32_t REG_1F9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F9CH_b; + }; + union + { + __IOM uint32_t REG_1FA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FA0H_b; + }; + union + { + __IOM uint32_t REG_1FA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FA4H_b; + }; + union + { + __IOM uint32_t REG_1FA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FA8H_b; + }; + union + { + __IOM uint32_t REG_1FACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FACH_b; + }; + union + { + __IOM uint32_t REG_1FB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FB0H_b; + }; + union + { + __IOM uint32_t REG_1FB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FB4H_b; + }; + union + { + __IOM uint32_t REG_1FB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FB8H_b; + }; + union + { + __IOM uint32_t REG_1FBCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FBCH_b; + }; + union + { + __IOM uint32_t REG_1FC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FC0H_b; + }; + union + { + __IOM uint32_t REG_1FC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FC4H_b; + }; + union + { + __IOM uint32_t REG_1FC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FC8H_b; + }; + union + { + __IOM uint32_t REG_1FCCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FCCH_b; + }; + union + { + __IOM uint32_t REG_1FD0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FD0H_b; + }; + union + { + __IOM uint32_t REG_1FD4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FD4H_b; + }; + union + { + __IOM uint32_t REG_1FD8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FD8H_b; + }; + union + { + __IOM uint32_t REG_1FDCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FDCH_b; + }; + union + { + __IOM uint32_t REG_1FE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FE0H_b; + }; + union + { + __IOM uint32_t REG_1FE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FE4H_b; + }; + union + { + __IOM uint32_t REG_1FE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FE8H_b; + }; + union + { + __IOM uint32_t REG_1FECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FECH_b; + }; + union + { + __IOM uint32_t REG_1FF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FF0H_b; + }; + union + { + __IOM uint32_t REG_1FF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FF4H_b; + }; + union + { + __IOM uint32_t REG_1FF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FF8H_b; + }; + union + { + __IOM uint32_t REG_1FFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FFCH_b; + }; + union + { + __IOM uint32_t REG_2000H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2000H_b; + }; + union + { + __IOM uint32_t REG_2004H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2004H_b; + }; + union + { + __IOM uint32_t REG_2008H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2008H_b; + }; + union + { + __IOM uint32_t REG_200CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_200CH_b; + }; + union + { + __IOM uint32_t REG_2010H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2010H_b; + }; + union + { + __IOM uint32_t REG_2014H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2014H_b; + }; + union + { + __IOM uint32_t REG_2018H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2018H_b; + }; + union + { + __IOM uint32_t REG_201CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_201CH_b; + }; + union + { + __IOM uint32_t REG_2020H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2020H_b; + }; + union + { + __IOM uint32_t REG_2024H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2024H_b; + }; + union + { + __IOM uint32_t REG_2028H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2028H_b; + }; + union + { + __IOM uint32_t REG_202CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_202CH_b; + }; + union + { + __IOM uint32_t REG_2030H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2030H_b; + }; + union + { + __IOM uint32_t REG_2034H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2034H_b; + }; + union + { + __IOM uint32_t REG_2038H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2038H_b; + }; + union + { + __IOM uint32_t REG_203CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_203CH_b; + }; + union + { + __IOM uint32_t REG_2040H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2040H_b; + }; + union + { + __IOM uint32_t REG_2044H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2044H_b; + }; + union + { + __IOM uint32_t REG_2048H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2048H_b; + }; + union + { + __IOM uint32_t REG_204CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_204CH_b; + }; + union + { + __IOM uint32_t REG_2050H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2050H_b; + }; + union + { + __IOM uint32_t REG_2054H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2054H_b; + }; + union + { + __IOM uint32_t REG_2058H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2058H_b; + }; + union + { + __IOM uint32_t REG_205CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_205CH_b; + }; + union + { + __IOM uint32_t REG_2060H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2060H_b; + }; + union + { + __IOM uint32_t REG_2064H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2064H_b; + }; + union + { + __IOM uint32_t REG_2068H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2068H_b; + }; + union + { + __IOM uint32_t REG_206CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_206CH_b; + }; + union + { + __IOM uint32_t REG_2070H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2070H_b; + }; + union + { + __IOM uint32_t REG_2074H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2074H_b; + }; + union + { + __IOM uint32_t REG_2078H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2078H_b; + }; + union + { + __IOM uint32_t REG_207CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_207CH_b; + }; + union + { + __IOM uint32_t REG_2080H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2080H_b; + }; + union + { + __IOM uint32_t REG_2084H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2084H_b; + }; + union + { + __IOM uint32_t REG_2088H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2088H_b; + }; + union + { + __IOM uint32_t REG_208CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_208CH_b; + }; + union + { + __IOM uint32_t REG_2090H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2090H_b; + }; + union + { + __IOM uint32_t REG_2094H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2094H_b; + }; + union + { + __IOM uint32_t REG_2098H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2098H_b; + }; + union + { + __IOM uint32_t REG_209CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_209CH_b; + }; + union + { + __IOM uint32_t REG_20A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20A0H_b; + }; + union + { + __IOM uint32_t REG_20A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20A4H_b; + }; + union + { + __IOM uint32_t REG_20A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20A8H_b; + }; + union + { + __IOM uint32_t REG_20ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20ACH_b; + }; + union + { + __IOM uint32_t REG_20B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20B0H_b; + }; + union + { + __IOM uint32_t REG_20B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20B4H_b; + }; + union + { + __IOM uint32_t REG_20B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20B8H_b; + }; + union + { + __IOM uint32_t REG_20BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20BCH_b; + }; + union + { + __IOM uint32_t REG_20C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20C0H_b; + }; + union + { + __IOM uint32_t REG_20C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20C4H_b; + }; + union + { + __IOM uint32_t REG_20C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20C8H_b; + }; + union + { + __IOM uint32_t REG_20CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20CCH_b; + }; + union + { + __IOM uint32_t REG_20D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20D0H_b; + }; + union + { + __IOM uint32_t REG_20D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20D4H_b; + }; + union + { + __IOM uint32_t REG_20D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20D8H_b; + }; + union + { + __IOM uint32_t REG_20DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20DCH_b; + }; + union + { + __IOM uint32_t REG_20E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20E0H_b; + }; + union + { + __IOM uint32_t REG_20E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20E4H_b; + }; + union + { + __IOM uint32_t REG_20E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20E8H_b; + }; + union + { + __IOM uint32_t REG_20ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20ECH_b; + }; + union + { + __IOM uint32_t REG_20F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20F0H_b; + }; + union + { + __IOM uint32_t REG_20F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20F4H_b; + }; + union + { + __IOM uint32_t REG_20F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20F8H_b; + }; + union + { + __IOM uint32_t REG_20FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20FCH_b; + }; + union + { + __IOM uint32_t REG_2100H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2100H_b; + }; + union + { + __IOM uint32_t REG_2104H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2104H_b; + }; + union + { + __IOM uint32_t REG_2108H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2108H_b; + }; + union + { + __IOM uint32_t REG_210CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_210CH_b; + }; + union + { + __IOM uint32_t REG_2110H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2110H_b; + }; + union + { + __IOM uint32_t REG_2114H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2114H_b; + }; + union + { + __IOM uint32_t REG_2118H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2118H_b; + }; + union + { + __IOM uint32_t REG_211CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_211CH_b; + }; + union + { + __IOM uint32_t REG_2120H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2120H_b; + }; + union + { + __IOM uint32_t REG_2124H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2124H_b; + }; + union + { + __IOM uint32_t REG_2128H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2128H_b; + }; + union + { + __IOM uint32_t REG_212CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_212CH_b; + }; + union + { + __IOM uint32_t REG_2130H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2130H_b; + }; + union + { + __IOM uint32_t REG_2134H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2134H_b; + }; + union + { + __IOM uint32_t REG_2138H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2138H_b; + }; + union + { + __IOM uint32_t REG_213CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_213CH_b; + }; + union + { + __IOM uint32_t REG_2140H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2140H_b; + }; + union + { + __IOM uint32_t REG_2144H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2144H_b; + }; + union + { + __IOM uint32_t REG_2148H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2148H_b; + }; + union + { + __IOM uint32_t REG_214CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_214CH_b; + }; + union + { + __IOM uint32_t REG_2150H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2150H_b; + }; + union + { + __IOM uint32_t REG_2154H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2154H_b; + }; + union + { + __IOM uint32_t REG_2158H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2158H_b; + }; + union + { + __IOM uint32_t REG_215CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_215CH_b; + }; + union + { + __IOM uint32_t REG_2160H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2160H_b; + }; + union + { + __IOM uint32_t REG_2164H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2164H_b; + }; + union + { + __IOM uint32_t REG_2168H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2168H_b; + }; + union + { + __IOM uint32_t REG_216CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_216CH_b; + }; + union + { + __IOM uint32_t REG_2170H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2170H_b; + }; + union + { + __IOM uint32_t REG_2174H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2174H_b; + }; + union + { + __IOM uint32_t REG_2178H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2178H_b; + }; + union + { + __IOM uint32_t REG_217CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_217CH_b; + }; + union + { + __IOM uint32_t REG_2180H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2180H_b; + }; + union + { + __IOM uint32_t REG_2184H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2184H_b; + }; + union + { + __IOM uint32_t REG_2188H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2188H_b; + }; + union + { + __IOM uint32_t REG_218CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_218CH_b; + }; + union + { + __IOM uint32_t REG_2190H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2190H_b; + }; + union + { + __IOM uint32_t REG_2194H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2194H_b; + }; + union + { + __IOM uint32_t REG_2198H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2198H_b; + }; + union + { + __IOM uint32_t REG_219CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_219CH_b; + }; + union + { + __IOM uint32_t REG_21A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21A0H_b; + }; + union + { + __IOM uint32_t REG_21A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21A4H_b; + }; + union + { + __IOM uint32_t REG_21A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21A8H_b; + }; + union + { + __IOM uint32_t REG_21ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21ACH_b; + }; + union + { + __IOM uint32_t REG_21B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21B0H_b; + }; + union + { + __IOM uint32_t REG_21B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21B4H_b; + }; + union + { + __IOM uint32_t REG_21B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21B8H_b; + }; + union + { + __IOM uint32_t REG_21BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21BCH_b; + }; + union + { + __IOM uint32_t REG_21C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21C0H_b; + }; + union + { + __IOM uint32_t REG_21C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21C4H_b; + }; + union + { + __IOM uint32_t REG_21C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21C8H_b; + }; + union + { + __IOM uint32_t REG_21CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21CCH_b; + }; + union + { + __IOM uint32_t REG_21D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21D0H_b; + }; + union + { + __IOM uint32_t REG_21D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21D4H_b; + }; + union + { + __IOM uint32_t REG_21D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21D8H_b; + }; + union + { + __IOM uint32_t REG_21DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21DCH_b; + }; + union + { + __IOM uint32_t REG_21E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21E0H_b; + }; + union + { + __IOM uint32_t REG_21E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21E4H_b; + }; + union + { + __IOM uint32_t REG_21E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21E8H_b; + }; + union + { + __IOM uint32_t REG_21ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21ECH_b; + }; + union + { + __IOM uint32_t REG_21F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21F0H_b; + }; + union + { + __IOM uint32_t REG_21F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21F4H_b; + }; + union + { + __IOM uint32_t REG_21F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21F8H_b; + }; + union + { + __IOM uint32_t REG_21FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21FCH_b; + }; + union + { + __IOM uint32_t REG_2200H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2200H_b; + }; + union + { + __IOM uint32_t REG_2204H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2204H_b; + }; + union + { + __IOM uint32_t REG_2208H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2208H_b; + }; + union + { + __IOM uint32_t REG_220CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_220CH_b; + }; + union + { + __IOM uint32_t REG_2210H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2210H_b; + }; + union + { + __IOM uint32_t REG_2214H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2214H_b; + }; + union + { + __IOM uint32_t REG_2218H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2218H_b; + }; + union + { + __IOM uint32_t REG_221CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_221CH_b; + }; + union + { + __IOM uint32_t REG_2220H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2220H_b; + }; + union + { + __IOM uint32_t REG_2224H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2224H_b; + }; + union + { + __IOM uint32_t REG_2228H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2228H_b; + }; + union + { + __IOM uint32_t REG_222CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_222CH_b; + }; + union + { + __IOM uint32_t REG_2230H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2230H_b; + }; + union + { + __IOM uint32_t REG_2234H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2234H_b; + }; + union + { + __IOM uint32_t REG_2238H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2238H_b; + }; + union + { + __IOM uint32_t REG_223CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_223CH_b; + }; + union + { + __IOM uint32_t REG_2240H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2240H_b; + }; + union + { + __IOM uint32_t REG_2244H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2244H_b; + }; + union + { + __IOM uint32_t REG_2248H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2248H_b; + }; + union + { + __IOM uint32_t REG_224CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_224CH_b; + }; + union + { + __IOM uint32_t REG_2250H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2250H_b; + }; + union + { + __IOM uint32_t REG_2254H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2254H_b; + }; + union + { + __IOM uint32_t REG_2258H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2258H_b; + }; + union + { + __IOM uint32_t REG_225CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_225CH_b; + }; + union + { + __IOM uint32_t REG_2260H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2260H_b; + }; + union + { + __IOM uint32_t REG_2264H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2264H_b; + }; + union + { + __IOM uint32_t REG_2268H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2268H_b; + }; + union + { + __IOM uint32_t REG_226CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_226CH_b; + }; + union + { + __IOM uint32_t REG_2270H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2270H_b; + }; + union + { + __IOM uint32_t REG_2274H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2274H_b; + }; + union + { + __IOM uint32_t REG_2278H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2278H_b; + }; + union + { + __IOM uint32_t REG_227CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_227CH_b; + }; + union + { + __IOM uint32_t REG_2280H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2280H_b; + }; + union + { + __IOM uint32_t REG_2284H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2284H_b; + }; + union + { + __IOM uint32_t REG_2288H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2288H_b; + }; + union + { + __IOM uint32_t REG_228CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_228CH_b; + }; + union + { + __IOM uint32_t REG_2290H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2290H_b; + }; + union + { + __IOM uint32_t REG_2294H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2294H_b; + }; + union + { + __IOM uint32_t REG_2298H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2298H_b; + }; + union + { + __IOM uint32_t REG_229CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_229CH_b; + }; + union + { + __IOM uint32_t REG_22A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22A0H_b; + }; + union + { + __IOM uint32_t REG_22A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22A4H_b; + }; + union + { + __IOM uint32_t REG_22A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22A8H_b; + }; + union + { + __IOM uint32_t REG_22ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22ACH_b; + }; + union + { + __IOM uint32_t REG_22B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22B0H_b; + }; + union + { + __IOM uint32_t REG_22B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22B4H_b; + }; + union + { + __IOM uint32_t REG_22B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22B8H_b; + }; + union + { + __IOM uint32_t REG_22BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22BCH_b; + }; + union + { + __IOM uint32_t REG_22C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22C0H_b; + }; + union + { + __IOM uint32_t REG_22C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22C4H_b; + }; + union + { + __IOM uint32_t REG_22C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22C8H_b; + }; + union + { + __IOM uint32_t REG_22CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22CCH_b; + }; + union + { + __IOM uint32_t REG_22D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22D0H_b; + }; + union + { + __IOM uint32_t REG_22D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22D4H_b; + }; + union + { + __IOM uint32_t REG_22D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22D8H_b; + }; + union + { + __IOM uint32_t REG_22DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22DCH_b; + }; + union + { + __IOM uint32_t REG_22E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22E0H_b; + }; + union + { + __IOM uint32_t REG_22E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22E4H_b; + }; + union + { + __IOM uint32_t REG_22E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22E8H_b; + }; + union + { + __IOM uint32_t REG_22ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22ECH_b; + }; + union + { + __IOM uint32_t REG_22F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22F0H_b; + }; + union + { + __IOM uint32_t REG_22F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22F4H_b; + }; + union + { + __IOM uint32_t REG_22F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22F8H_b; + }; + union + { + __IOM uint32_t REG_22FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22FCH_b; + }; + union + { + __IOM uint32_t REG_2300H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2300H_b; + }; + union + { + __IOM uint32_t REG_2304H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2304H_b; + }; + union + { + __IOM uint32_t REG_2308H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2308H_b; + }; + union + { + __IOM uint32_t REG_230CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_230CH_b; + }; + union + { + __IOM uint32_t REG_2310H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2310H_b; + }; + union + { + __IOM uint32_t REG_2314H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2314H_b; + }; + union + { + __IOM uint32_t REG_2318H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2318H_b; + }; + union + { + __IOM uint32_t REG_231CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_231CH_b; + }; + union + { + __IOM uint32_t REG_2320H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2320H_b; + }; + union + { + __IOM uint32_t REG_2324H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2324H_b; + }; + union + { + __IOM uint32_t REG_2328H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2328H_b; + }; + union + { + __IOM uint32_t REG_232CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_232CH_b; + }; + union + { + __IOM uint32_t REG_2330H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2330H_b; + }; + union + { + __IOM uint32_t REG_2334H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2334H_b; + }; + union + { + __IOM uint32_t REG_2338H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2338H_b; + }; + union + { + __IOM uint32_t REG_233CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_233CH_b; + }; + union + { + __IOM uint32_t REG_2340H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2340H_b; + }; + union + { + __IOM uint32_t REG_2344H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2344H_b; + }; + union + { + __IOM uint32_t REG_2348H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2348H_b; + }; + union + { + __IOM uint32_t REG_234CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_234CH_b; + }; + union + { + __IOM uint32_t REG_2350H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2350H_b; + }; + union + { + __IOM uint32_t REG_2354H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2354H_b; + }; + union + { + __IOM uint32_t REG_2358H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2358H_b; + }; + union + { + __IOM uint32_t REG_235CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_235CH_b; + }; + union + { + __IOM uint32_t REG_2360H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2360H_b; + }; + union + { + __IOM uint32_t REG_2364H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2364H_b; + }; + union + { + __IOM uint32_t REG_2368H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2368H_b; + }; + union + { + __IOM uint32_t REG_236CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_236CH_b; + }; + union + { + __IOM uint32_t REG_2370H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2370H_b; + }; + union + { + __IOM uint32_t REG_2374H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2374H_b; + }; + union + { + __IOM uint32_t REG_2378H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2378H_b; + }; + union + { + __IOM uint32_t REG_237CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_237CH_b; + }; + union + { + __IOM uint32_t REG_2380H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2380H_b; + }; + union + { + __IOM uint32_t REG_2384H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2384H_b; + }; + union + { + __IOM uint32_t REG_2388H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2388H_b; + }; + union + { + __IOM uint32_t REG_238CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_238CH_b; + }; + union + { + __IOM uint32_t REG_2390H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2390H_b; + }; + union + { + __IOM uint32_t REG_2394H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2394H_b; + }; + union + { + __IOM uint32_t REG_2398H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2398H_b; + }; + union + { + __IOM uint32_t REG_239CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_239CH_b; + }; + union + { + __IOM uint32_t REG_23A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23A0H_b; + }; + union + { + __IOM uint32_t REG_23A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23A4H_b; + }; + union + { + __IOM uint32_t REG_23A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23A8H_b; + }; + union + { + __IOM uint32_t REG_23ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23ACH_b; + }; + union + { + __IOM uint32_t REG_23B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23B0H_b; + }; + union + { + __IOM uint32_t REG_23B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23B4H_b; + }; + union + { + __IOM uint32_t REG_23B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23B8H_b; + }; + union + { + __IOM uint32_t REG_23BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23BCH_b; + }; + union + { + __IOM uint32_t REG_23C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23C0H_b; + }; + union + { + __IOM uint32_t REG_23C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23C4H_b; + }; + union + { + __IOM uint32_t REG_23C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23C8H_b; + }; + union + { + __IOM uint32_t REG_23CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23CCH_b; + }; + union + { + __IOM uint32_t REG_23D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23D0H_b; + }; + union + { + __IOM uint32_t REG_23D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23D4H_b; + }; + union + { + __IOM uint32_t REG_23D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23D8H_b; + }; + union + { + __IOM uint32_t REG_23DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23DCH_b; + }; + union + { + __IOM uint32_t REG_23E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23E0H_b; + }; + union + { + __IOM uint32_t REG_23E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23E4H_b; + }; + union + { + __IOM uint32_t REG_23E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23E8H_b; + }; + union + { + __IOM uint32_t REG_23ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23ECH_b; + }; + union + { + __IOM uint32_t REG_23F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23F0H_b; + }; + union + { + __IOM uint32_t REG_23F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23F4H_b; + }; + union + { + __IOM uint32_t REG_23F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23F8H_b; + }; + union + { + __IOM uint32_t REG_23FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23FCH_b; + }; + union + { + __IOM uint32_t REG_2400H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2400H_b; + }; + union + { + __IOM uint32_t REG_2404H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2404H_b; + }; + union + { + __IOM uint32_t REG_2408H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2408H_b; + }; + union + { + __IOM uint32_t REG_240CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_240CH_b; + }; + union + { + __IOM uint32_t REG_2410H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2410H_b; + }; + union + { + __IOM uint32_t REG_2414H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2414H_b; + }; + union + { + __IOM uint32_t REG_2418H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2418H_b; + }; + union + { + __IOM uint32_t REG_241CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_241CH_b; + }; + union + { + __IOM uint32_t REG_2420H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2420H_b; + }; + union + { + __IOM uint32_t REG_2424H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2424H_b; + }; + union + { + __IOM uint32_t REG_2428H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2428H_b; + }; + union + { + __IOM uint32_t REG_242CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_242CH_b; + }; + union + { + __IOM uint32_t REG_2430H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2430H_b; + }; + union + { + __IOM uint32_t REG_2434H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2434H_b; + }; + union + { + __IOM uint32_t REG_2438H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2438H_b; + }; + union + { + __IOM uint32_t REG_243CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_243CH_b; + }; + union + { + __IOM uint32_t REG_2440H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2440H_b; + }; + union + { + __IOM uint32_t REG_2444H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2444H_b; + }; + union + { + __IOM uint32_t REG_2448H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2448H_b; + }; + union + { + __IOM uint32_t REG_244CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_244CH_b; + }; + union + { + __IOM uint32_t REG_2450H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2450H_b; + }; + union + { + __IOM uint32_t REG_2454H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2454H_b; + }; + union + { + __IOM uint32_t REG_2458H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2458H_b; + }; + union + { + __IOM uint32_t REG_245CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_245CH_b; + }; + union + { + __IOM uint32_t REG_2460H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2460H_b; + }; + union + { + __IOM uint32_t REG_2464H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2464H_b; + }; + union + { + __IOM uint32_t REG_2468H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2468H_b; + }; + union + { + __IOM uint32_t REG_246CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_246CH_b; + }; + union + { + __IOM uint32_t REG_2470H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2470H_b; + }; + union + { + __IOM uint32_t REG_2474H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2474H_b; + }; + union + { + __IOM uint32_t REG_2478H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2478H_b; + }; + union + { + __IOM uint32_t REG_247CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_247CH_b; + }; + union + { + __IOM uint32_t REG_2480H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2480H_b; + }; + union + { + __IOM uint32_t REG_2484H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2484H_b; + }; + union + { + __IOM uint32_t REG_2488H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2488H_b; + }; + union + { + __IOM uint32_t REG_248CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_248CH_b; + }; + union + { + __IOM uint32_t REG_2490H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2490H_b; + }; + union + { + __IOM uint32_t REG_2494H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2494H_b; + }; + union + { + __IOM uint32_t REG_2498H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2498H_b; + }; + union + { + __IOM uint32_t REG_249CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_249CH_b; + }; + union + { + __IOM uint32_t REG_24A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24A0H_b; + }; + union + { + __IOM uint32_t REG_24A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24A4H_b; + }; + union + { + __IOM uint32_t REG_24A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24A8H_b; + }; + union + { + __IOM uint32_t REG_24ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24ACH_b; + }; + union + { + __IOM uint32_t REG_24B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24B0H_b; + }; + union + { + __IOM uint32_t REG_24B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24B4H_b; + }; + union + { + __IOM uint32_t REG_24B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24B8H_b; + }; + union + { + __IOM uint32_t REG_24BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24BCH_b; + }; + union + { + __IOM uint32_t REG_24C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24C0H_b; + }; + union + { + __IOM uint32_t REG_24C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24C4H_b; + }; + union + { + __IOM uint32_t REG_24C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24C8H_b; + }; + union + { + __IOM uint32_t REG_24CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24CCH_b; + }; + union + { + __IOM uint32_t REG_24D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24D0H_b; + }; + union + { + __IOM uint32_t REG_24D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24D4H_b; + }; + union + { + __IOM uint32_t REG_24D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24D8H_b; + }; + union + { + __IOM uint32_t REG_24DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24DCH_b; + }; + union + { + __IOM uint32_t REG_24E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24E0H_b; + }; + union + { + __IOM uint32_t REG_24E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24E4H_b; + }; + union + { + __IOM uint32_t REG_24E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24E8H_b; + }; + union + { + __IOM uint32_t REG_24ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24ECH_b; + }; + union + { + __IOM uint32_t REG_24F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24F0H_b; + }; + union + { + __IOM uint32_t REG_24F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24F4H_b; + }; + union + { + __IOM uint32_t REG_24F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24F8H_b; + }; +} SCE_Type; + +// for bit access + +/* -------------------------------- SCE.REG_xxxH -------------------------------- */ +#define SCE_REG_0_Pos 0 /*!< SCE REG_xxxH: bit 0 Position */ +#define SCE_REG_0_Msk (0x01UL << SCE_REG_0_Pos) /*!< SCE REG_xxxH: bit 0 Mask */ +#define SCE_REG_1_Pos 1 /*!< SCE REG_xxxH: bit 1 Position */ +#define SCE_REG_1_Msk (0x01UL << SCE_REG_1_Pos) /*!< SCE REG_xxxH: bit 1 Mask */ +#define SCE_REG_2_Pos 2 /*!< SCE REG_xxxH: bit 2 Position */ +#define SCE_REG_2_Msk (0x01UL << SCE_REG_2_Pos) /*!< SCE REG_xxxH: bit 2 Mask */ +#define SCE_REG_3_Pos 3 /*!< SCE REG_xxxH: bit 3 Position */ +#define SCE_REG_3_Msk (0x01UL << SCE_REG_3_Pos) /*!< SCE REG_xxxH: bit 3 Mask */ +#define SCE_REG_4_Pos 4 /*!< SCE REG_xxxH: bit 4 Position */ +#define SCE_REG_4_Msk (0x01UL << SCE_REG_4_Pos) /*!< SCE REG_xxxH: bit 4 Mask */ +#define SCE_REG_5_Pos 5 /*!< SCE REG_xxxH: bit 5 Position */ +#define SCE_REG_5_Msk (0x01UL << SCE_REG_5_Pos) /*!< SCE REG_xxxH: bit 5 Mask */ +#define SCE_REG_6_Pos 6 /*!< SCE REG_xxxH: bit 6 Position */ +#define SCE_REG_6_Msk (0x01UL << SCE_REG_6_Pos) /*!< SCE REG_xxxH: bit 6 Mask */ +#define SCE_REG_7_Pos 7 /*!< SCE REG_xxxH: bit 7 Position */ +#define SCE_REG_7_Msk (0x01UL << SCE_REG_7_Pos) /*!< SCE REG_xxxH: bit 7 Mask */ +#define SCE_REG_8_Pos 8 /*!< SCE REG_xxxH: bit 8 Position */ +#define SCE_REG_8_Msk (0x01UL << SCE_REG_8_Pos) /*!< SCE REG_xxxH: bit 8 Mask */ +#define SCE_REG_9_Pos 9 /*!< SCE REG_xxxH: bit 9 Position */ +#define SCE_REG_9_Msk (0x01UL << SCE_REG_9_Pos) /*!< SCE REG_xxxH: bit 9 Mask */ +#define SCE_REG_10_Pos 10 /*!< SCE REG_xxxH: bit 10 Position */ +#define SCE_REG_10_Msk (0x01UL << SCE_REG_10_Pos) /*!< SCE REG_xxxH: bit 10 Mask */ +#define SCE_REG_11_Pos 11 /*!< SCE REG_xxxH: bit 11 Position */ +#define SCE_REG_11_Msk (0x01UL << SCE_REG_11_Pos) /*!< SCE REG_xxxH: bit 11 Mask */ +#define SCE_REG_12_Pos 12 /*!< SCE REG_xxxH: bit 12 Position */ +#define SCE_REG_12_Msk (0x01UL << SCE_REG_12_Pos) /*!< SCE REG_xxxH: bit 12 Mask */ +#define SCE_REG_13_Pos 13 /*!< SCE REG_xxxH: bit 13 Position */ +#define SCE_REG_13_Msk (0x01UL << SCE_REG_13_Pos) /*!< SCE REG_xxxH: bit 13 Mask */ +#define SCE_REG_14_Pos 14 /*!< SCE REG_xxxH: bit 14 Position */ +#define SCE_REG_14_Msk (0x01UL << SCE_REG_14_Pos) /*!< SCE REG_xxxH: bit 14 Mask */ +#define SCE_REG_15_Pos 15 /*!< SCE REG_xxxH: bit 15 Position */ +#define SCE_REG_15_Msk (0x01UL << SCE_REG_15_Pos) /*!< SCE REG_xxxH: bit 15 Mask */ +#define SCE_REG_16_Pos 16 /*!< SCE REG_xxxH: bit 16 Position */ +#define SCE_REG_16_Msk (0x01UL << SCE_REG_16_Pos) /*!< SCE REG_xxxH: bit 16 Mask */ +#define SCE_REG_17_Pos 17 /*!< SCE REG_xxxH: bit 17 Position */ +#define SCE_REG_17_Msk (0x01UL << SCE_REG_17_Pos) /*!< SCE REG_xxxH: bit 17 Mask */ +#define SCE_REG_18_Pos 18 /*!< SCE REG_xxxH: bit 18 Position */ +#define SCE_REG_18_Msk (0x01UL << SCE_REG_18_Pos) /*!< SCE REG_xxxH: bit 18 Mask */ +#define SCE_REG_19_Pos 19 /*!< SCE REG_xxxH: bit 19 Position */ +#define SCE_REG_19_Msk (0x01UL << SCE_REG_19_Pos) /*!< SCE REG_xxxH: bit 19 Mask */ +#define SCE_REG_20_Pos 20 /*!< SCE REG_xxxH: bit 20 Position */ +#define SCE_REG_20_Msk (0x01UL << SCE_REG_20_Pos) /*!< SCE REG_xxxH: bit 20 Mask */ +#define SCE_REG_21_Pos 21 /*!< SCE REG_xxxH: bit 21 Position */ +#define SCE_REG_21_Msk (0x01UL << SCE_REG_21_Pos) /*!< SCE REG_xxxH: bit 21 Mask */ +#define SCE_REG_22_Pos 22 /*!< SCE REG_xxxH: bit 22 Position */ +#define SCE_REG_22_Msk (0x01UL << SCE_REG_22_Pos) /*!< SCE REG_xxxH: bit 22 Mask */ +#define SCE_REG_23_Pos 23 /*!< SCE REG_xxxH: bit 23 Position */ +#define SCE_REG_23_Msk (0x01UL << SCE_REG_23_Pos) /*!< SCE REG_xxxH: bit 23 Mask */ +#define SCE_REG_24_Pos 24 /*!< SCE REG_xxxH: bit 24 Position */ +#define SCE_REG_24_Msk (0x01UL << SCE_REG_24_Pos) /*!< SCE REG_xxxH: bit 24 Mask */ +#define SCE_REG_25_Pos 25 /*!< SCE REG_xxxH: bit 25 Position */ +#define SCE_REG_25_Msk (0x01UL << SCE_REG_25_Pos) /*!< SCE REG_xxxH: bit 25 Mask */ +#define SCE_REG_26_Pos 26 /*!< SCE REG_xxxH: bit 26 Position */ +#define SCE_REG_26_Msk (0x01UL << SCE_REG_26_Pos) /*!< SCE REG_xxxH: bit 26 Mask */ +#define SCE_REG_27_Pos 27 /*!< SCE REG_xxxH: bit 27 Position */ +#define SCE_REG_27_Msk (0x01UL << SCE_REG_27_Pos) /*!< SCE REG_xxxH: bit 27 Mask */ +#define SCE_REG_28_Pos 28 /*!< SCE REG_xxxH: bit 28 Position */ +#define SCE_REG_28_Msk (0x01UL << SCE_REG_28_Pos) /*!< SCE REG_xxxH: bit 28 Mask */ +#define SCE_REG_29_Pos 29 /*!< SCE REG_xxxH: bit 29 Position */ +#define SCE_REG_29_Msk (0x01UL << SCE_REG_29_Pos) /*!< SCE REG_xxxH: bit 29 Mask */ +#define SCE_REG_30_Pos 30 /*!< SCE REG_xxxH: bit 30 Position */ +#define SCE_REG_30_Msk (0x01UL << SCE_REG_30_Pos) /*!< SCE REG_xxxH: bit 30 Mask */ +#define SCE_REG_31_Pos 31 /*!< SCE REG_xxxH: bit 31 Position */ +#define SCE_REG_31_Msk (0x01UL << SCE_REG_31_Pos) /*!< SCE REG_xxxH: bit 31 Mask */ + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define SCE ((SCE_Type *) SCE_BASE) + +// macro definishion + +#define SCE_DELAY(delay) \ + for (volatile uint32_t count = 0; count < delay; count++) \ + { \ + ; \ + } + +// [R RD 1 B] +#define RD1_PROG(regName) \ + (SCE->regName) + +// [R WR 1 B] +#define WR1_PROG(regName, value) \ + SCE->regName = value + +// [R WR 2 B0 B1] +#define WR2_PROG(regName, value0, value1) \ + WR1_PROG(regName, value0); \ + WR1_PROG(regName, value1); + +// [R WR 3 B0 B1 B2] +#define WR3_PROG(regName, value0, value1, value2) \ + WR1_PROG(regName, value0); \ + WR1_PROG(regName, value1); \ + WR1_PROG(regName, value2) + +// [R WR 4 B0 B1 B2 B3] +#define WR4_PROG(regName, value0, value1, value2, value3) \ + WR1_PROG(regName, value0); \ + WR1_PROG(regName, value1); \ + WR1_PROG(regName, value2); \ + WR1_PROG(regName, value3) + +// [R WR 16 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15] +#define WR16_PROG(regName, \ + value0, \ + value1, \ + value2, \ + value3, \ + value4, \ + value5, \ + value6, \ + value7, \ + value8, \ + value9, \ + value10, \ + value11, \ + value12, \ + value13, \ + value14, \ + value15) \ + WR1_PROG(regName, value0); \ + WR1_PROG(regName, value1); \ + WR1_PROG(regName, value2); \ + WR1_PROG(regName, value3); \ + WR1_PROG(regName, value4); \ + WR1_PROG(regName, value5); \ + WR1_PROG(regName, value6); \ + WR1_PROG(regName, value7); \ + WR1_PROG(regName, value8); \ + WR1_PROG(regName, value9); \ + WR1_PROG(regName, value10); \ + WR1_PROG(regName, value11); \ + WR1_PROG(regName, value12); \ + WR1_PROG(regName, value13); \ + WR1_PROG(regName, value14); \ + WR1_PROG(regName, value15) + +// [R RD 1 B] +#define RD1_EVAL(regName, value) \ + if (SCE->regname != value) \ + return FSP_ERR_CRYPTO_SCE_FAIL + +// [R CHK_STATUS A B] +#define CHCK_STS(regName, bitPos, value) \ + (((SCE->regName & (0x01UL << bitPos)) >> bitPos) == value) + +// [R CHK_REG A (!= B)] +#define RD1_MASK(regName, maskValue) \ + (SCE->regName & maskValue) + +// [R WAIT_STATUS A B] +#define WAIT_STS(regName, bitPos, value) \ + while (!CHCK_STS(regName, bitPos, value)) + +// [R WR 1 MEM[Ofs]] +#define WR1_ADDR(regName, addr) \ + SCE->regName = *(addr) + +// [R WR 2 MEM[Ofs]] +#define WR2_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); + +// [R WR 3 MEM[Ofs]] +#define WR3_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); + +// [R WR 4 MEM[Ofs]] +#define WR4_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3) + +// [R WR 5 MEM[Ofs]] +#define WR5_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4) + +// [R WR 6 MEM[Ofs]] +#define WR6_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4); \ + WR1_ADDR(regName, (addr) + 5) + +// [R WR 7 MEM[Ofs]] +#define WR7_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4); \ + WR1_ADDR(regName, (addr) + 5); \ + WR1_ADDR(regName, (addr) + 6) + +// [R WR 8 MEM[Ofs]] +#define WR8_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4); \ + WR1_ADDR(regName, (addr) + 5); \ + WR1_ADDR(regName, (addr) + 6); \ + WR1_ADDR(regName, (addr) + 7) + +// [R WR 12 MEM[Ofs]] +#define WR12_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4); \ + WR1_ADDR(regName, (addr) + 5); \ + WR1_ADDR(regName, (addr) + 6); \ + WR1_ADDR(regName, (addr) + 7); \ + WR1_ADDR(regName, (addr) + 8); \ + WR1_ADDR(regName, (addr) + 9); \ + WR1_ADDR(regName, (addr) + 10); \ + WR1_ADDR(regName, (addr) + 11) + +// [R WR 16 MEM[Ofs]] +#define WR16_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4); \ + WR1_ADDR(regName, (addr) + 5); \ + WR1_ADDR(regName, (addr) + 6); \ + WR1_ADDR(regName, (addr) + 7); \ + WR1_ADDR(regName, (addr) + 8); \ + WR1_ADDR(regName, (addr) + 9); \ + WR1_ADDR(regName, (addr) + 10); \ + WR1_ADDR(regName, (addr) + 11); \ + WR1_ADDR(regName, (addr) + 12); \ + WR1_ADDR(regName, (addr) + 13); \ + WR1_ADDR(regName, (addr) + 14); \ + WR1_ADDR(regName, (addr) + 15) + +// [R WR 32 MEM[Ofs]] +#define WR32_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4); \ + WR1_ADDR(regName, (addr) + 5); \ + WR1_ADDR(regName, (addr) + 6); \ + WR1_ADDR(regName, (addr) + 7); \ + WR1_ADDR(regName, (addr) + 8); \ + WR1_ADDR(regName, (addr) + 9); \ + WR1_ADDR(regName, (addr) + 10); \ + WR1_ADDR(regName, (addr) + 11); \ + WR1_ADDR(regName, (addr) + 12); \ + WR1_ADDR(regName, (addr) + 13); \ + WR1_ADDR(regName, (addr) + 14); \ + WR1_ADDR(regName, (addr) + 15); \ + WR1_ADDR(regName, (addr) + 16); \ + WR1_ADDR(regName, (addr) + 17); \ + WR1_ADDR(regName, (addr) + 18); \ + WR1_ADDR(regName, (addr) + 19); \ + WR1_ADDR(regName, (addr) + 20); \ + WR1_ADDR(regName, (addr) + 21); \ + WR1_ADDR(regName, (addr) + 22); \ + WR1_ADDR(regName, (addr) + 23); \ + WR1_ADDR(regName, (addr) + 24); \ + WR1_ADDR(regName, (addr) + 25); \ + WR1_ADDR(regName, (addr) + 26); \ + WR1_ADDR(regName, (addr) + 27); \ + WR1_ADDR(regName, (addr) + 28); \ + WR1_ADDR(regName, (addr) + 29); \ + WR1_ADDR(regName, (addr) + 30); \ + WR1_ADDR(regName, (addr) + 31) + +// [R WR 64 MEM[Ofs]] +#define WR64_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4); \ + WR1_ADDR(regName, (addr) + 5); \ + WR1_ADDR(regName, (addr) + 6); \ + WR1_ADDR(regName, (addr) + 7); \ + WR1_ADDR(regName, (addr) + 8); \ + WR1_ADDR(regName, (addr) + 9); \ + WR1_ADDR(regName, (addr) + 10); \ + WR1_ADDR(regName, (addr) + 11); \ + WR1_ADDR(regName, (addr) + 12); \ + WR1_ADDR(regName, (addr) + 13); \ + WR1_ADDR(regName, (addr) + 14); \ + WR1_ADDR(regName, (addr) + 15); \ + WR1_ADDR(regName, (addr) + 16); \ + WR1_ADDR(regName, (addr) + 17); \ + WR1_ADDR(regName, (addr) + 18); \ + WR1_ADDR(regName, (addr) + 19); \ + WR1_ADDR(regName, (addr) + 20); \ + WR1_ADDR(regName, (addr) + 21); \ + WR1_ADDR(regName, (addr) + 22); \ + WR1_ADDR(regName, (addr) + 23); \ + WR1_ADDR(regName, (addr) + 24); \ + WR1_ADDR(regName, (addr) + 25); \ + WR1_ADDR(regName, (addr) + 26); \ + WR1_ADDR(regName, (addr) + 27); \ + WR1_ADDR(regName, (addr) + 28); \ + WR1_ADDR(regName, (addr) + 29); \ + WR1_ADDR(regName, (addr) + 30); \ + WR1_ADDR(regName, (addr) + 31); \ + WR1_ADDR(regName, (addr) + 32); \ + WR1_ADDR(regName, (addr) + 33); \ + WR1_ADDR(regName, (addr) + 34); \ + WR1_ADDR(regName, (addr) + 35); \ + WR1_ADDR(regName, (addr) + 36); \ + WR1_ADDR(regName, (addr) + 37); \ + WR1_ADDR(regName, (addr) + 38); \ + WR1_ADDR(regName, (addr) + 39); \ + WR1_ADDR(regName, (addr) + 40); \ + WR1_ADDR(regName, (addr) + 41); \ + WR1_ADDR(regName, (addr) + 42); \ + WR1_ADDR(regName, (addr) + 43); \ + WR1_ADDR(regName, (addr) + 44); \ + WR1_ADDR(regName, (addr) + 45); \ + WR1_ADDR(regName, (addr) + 46); \ + WR1_ADDR(regName, (addr) + 47); \ + WR1_ADDR(regName, (addr) + 48); \ + WR1_ADDR(regName, (addr) + 49); \ + WR1_ADDR(regName, (addr) + 50); \ + WR1_ADDR(regName, (addr) + 51); \ + WR1_ADDR(regName, (addr) + 52); \ + WR1_ADDR(regName, (addr) + 53); \ + WR1_ADDR(regName, (addr) + 54); \ + WR1_ADDR(regName, (addr) + 55); \ + WR1_ADDR(regName, (addr) + 56); \ + WR1_ADDR(regName, (addr) + 57); \ + WR1_ADDR(regName, (addr) + 58); \ + WR1_ADDR(regName, (addr) + 59); \ + WR1_ADDR(regName, (addr) + 60); \ + WR1_ADDR(regName, (addr) + 61); \ + WR1_ADDR(regName, (addr) + 62); \ + WR1_ADDR(regName, (addr) + 63) + +// [R RD 1 MEM[Ofs]] +#define RD1_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; + +// [R RD 2 MEM[Ofs]] +#define RD2_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; + +// [R RD 3 MEM[Ofs]] +#define RD3_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; + +// [R RD 4 MEM[Ofs]] +#define RD4_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName + +// [R RD 5 MEM[Ofs]] +#define RD5_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName + +// [R RD 6 MEM[Ofs]] +#define RD6_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName; \ + *((addr) + 5) = SCE->regName + +// [R RD 7 MEM[Ofs]] +#define RD7_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName; \ + *((addr) + 5) = SCE->regName; \ + *((addr) + 6) = SCE->regName + +// [R RD 8 MEM[Ofs]] +#define RD8_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName; \ + *((addr) + 5) = SCE->regName; \ + *((addr) + 6) = SCE->regName; \ + *((addr) + 7) = SCE->regName + +// [R RD 12 MEM[Ofs]] +#define RD12_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName; \ + *((addr) + 5) = SCE->regName; \ + *((addr) + 6) = SCE->regName; \ + *((addr) + 7) = SCE->regName; \ + *((addr) + 8) = SCE->regName; \ + *((addr) + 9) = SCE->regName; \ + *((addr) + 10) = SCE->regName; \ + *((addr) + 11) = SCE->regName + +// [R RD 16 MEM[Ofs]] +#define RD16_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName; \ + *((addr) + 5) = SCE->regName; \ + *((addr) + 6) = SCE->regName; \ + *((addr) + 7) = SCE->regName; \ + *((addr) + 8) = SCE->regName; \ + *((addr) + 9) = SCE->regName; \ + *((addr) + 10) = SCE->regName; \ + *((addr) + 11) = SCE->regName; \ + *((addr) + 12) = SCE->regName; \ + *((addr) + 13) = SCE->regName; \ + *((addr) + 14) = SCE->regName; \ + *((addr) + 15) = SCE->regName + +// [R RD 32 MEM[Ofs]] +#define RD32_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName; \ + *((addr) + 5) = SCE->regName; \ + *((addr) + 6) = SCE->regName; \ + *((addr) + 7) = SCE->regName; \ + *((addr) + 8) = SCE->regName; \ + *((addr) + 9) = SCE->regName; \ + *((addr) + 10) = SCE->regName; \ + *((addr) + 11) = SCE->regName; \ + *((addr) + 12) = SCE->regName; \ + *((addr) + 13) = SCE->regName; \ + *((addr) + 14) = SCE->regName; \ + *((addr) + 15) = SCE->regName; \ + *((addr) + 16) = SCE->regName; \ + *((addr) + 17) = SCE->regName; \ + *((addr) + 18) = SCE->regName; \ + *((addr) + 19) = SCE->regName; \ + *((addr) + 20) = SCE->regName; \ + *((addr) + 21) = SCE->regName; \ + *((addr) + 22) = SCE->regName; \ + *((addr) + 23) = SCE->regName; \ + *((addr) + 24) = SCE->regName; \ + *((addr) + 25) = SCE->regName; \ + *((addr) + 26) = SCE->regName; \ + *((addr) + 27) = SCE->regName; \ + *((addr) + 28) = SCE->regName; \ + *((addr) + 29) = SCE->regName; \ + *((addr) + 30) = SCE->regName; \ + *((addr) + 31) = SCE->regName + +// [R RD 64 MEM[Ofs]] +#define RD64_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName; \ + *((addr) + 5) = SCE->regName; \ + *((addr) + 6) = SCE->regName; \ + *((addr) + 7) = SCE->regName; \ + *((addr) + 8) = SCE->regName; \ + *((addr) + 9) = SCE->regName; \ + *((addr) + 10) = SCE->regName; \ + *((addr) + 11) = SCE->regName; \ + *((addr) + 12) = SCE->regName; \ + *((addr) + 13) = SCE->regName; \ + *((addr) + 14) = SCE->regName; \ + *((addr) + 15) = SCE->regName; \ + *((addr) + 16) = SCE->regName; \ + *((addr) + 17) = SCE->regName; \ + *((addr) + 18) = SCE->regName; \ + *((addr) + 19) = SCE->regName; \ + *((addr) + 20) = SCE->regName; \ + *((addr) + 21) = SCE->regName; \ + *((addr) + 22) = SCE->regName; \ + *((addr) + 23) = SCE->regName; \ + *((addr) + 24) = SCE->regName; \ + *((addr) + 25) = SCE->regName; \ + *((addr) + 26) = SCE->regName; \ + *((addr) + 27) = SCE->regName; \ + *((addr) + 28) = SCE->regName; \ + *((addr) + 29) = SCE->regName; \ + *((addr) + 30) = SCE->regName; \ + *((addr) + 31) = SCE->regName; \ + *((addr) + 32) = SCE->regName; \ + *((addr) + 33) = SCE->regName; \ + *((addr) + 34) = SCE->regName; \ + *((addr) + 35) = SCE->regName; \ + *((addr) + 36) = SCE->regName; \ + *((addr) + 37) = SCE->regName; \ + *((addr) + 38) = SCE->regName; \ + *((addr) + 39) = SCE->regName; \ + *((addr) + 40) = SCE->regName; \ + *((addr) + 41) = SCE->regName; \ + *((addr) + 42) = SCE->regName; \ + *((addr) + 43) = SCE->regName; \ + *((addr) + 44) = SCE->regName; \ + *((addr) + 45) = SCE->regName; \ + *((addr) + 46) = SCE->regName; \ + *((addr) + 47) = SCE->regName; \ + *((addr) + 48) = SCE->regName; \ + *((addr) + 49) = SCE->regName; \ + *((addr) + 50) = SCE->regName; \ + *((addr) + 51) = SCE->regName; \ + *((addr) + 52) = SCE->regName; \ + *((addr) + 53) = SCE->regName; \ + *((addr) + 54) = SCE->regName; \ + *((addr) + 55) = SCE->regName; \ + *((addr) + 56) = SCE->regName; \ + *((addr) + 57) = SCE->regName; \ + *((addr) + 58) = SCE->regName; \ + *((addr) + 59) = SCE->regName; \ + *((addr) + 60) = SCE->regName; \ + *((addr) + 61) = SCE->regName; \ + *((addr) + 62) = SCE->regName; \ + *((addr) + 63) = SCE->regName + +// [TEST_BUSY WAIT A] +#define WAI_BUSY(value) \ + WAIT_STS(SCE->REG_00H, 31, value) + +void SC32_function001(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void SC32_function002(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void SC32_function003(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); + +void SC327_function001(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void SC327_function002(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void SC327_function003(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); + +// [R WR 32 B0 B1 B2 B3 B4 .... B31] +#define WR32_PROG(regName, \ + value0, value1, value2, value3, value4, value5, value6, value7, value8, value9, \ + value10, value11, value12, value13, value14, value15, value16, value17, value18, value19, \ + value20, value21, value22, value23, value24, value25, value26, value27, value28, value29, \ + value30, value31 \ + ) \ + WR1_PROG(regName, value0); \ + WR1_PROG(regName, value1); \ + WR1_PROG(regName, value2); \ + WR1_PROG(regName, value3); \ + WR1_PROG(regName, value4); \ + WR1_PROG(regName, value5); \ + WR1_PROG(regName, value6); \ + WR1_PROG(regName, value7); \ + WR1_PROG(regName, value8); \ + WR1_PROG(regName, value9); \ + WR1_PROG(regName, value10); \ + WR1_PROG(regName, value11); \ + WR1_PROG(regName, value12); \ + WR1_PROG(regName, value13); \ + WR1_PROG(regName, value14); \ + WR1_PROG(regName, value15); \ + WR1_PROG(regName, value16); \ + WR1_PROG(regName, value17); \ + WR1_PROG(regName, value18); \ + WR1_PROG(regName, value19); \ + WR1_PROG(regName, value20); \ + WR1_PROG(regName, value21); \ + WR1_PROG(regName, value22); \ + WR1_PROG(regName, value23); \ + WR1_PROG(regName, value24); \ + WR1_PROG(regName, value25); \ + WR1_PROG(regName, value26); \ + WR1_PROG(regName, value27); \ + WR1_PROG(regName, value28); \ + WR1_PROG(regName, value29); \ + WR1_PROG(regName, value30); \ + WR1_PROG(regName, value31) + +// [R WR 48 B0 B1 B2 B3 B4 .... B47] +#define WR48_PROG(regName, \ + value0, value1, value2, value3, value4, value5, value6, value7, value8, value9, \ + value10, value11, value12, value13, value14, value15, value16, value17, value18, value19, \ + value20, value21, value22, value23, value24, value25, value26, value27, value28, value29, \ + value30, value31, value32, value33, value34, value35, value36, value37, value38, value39, \ + value40, value41, value42, value43, value44, value45, value46, value47 \ + ) \ + WR1_PROG(regName, value0); \ + WR1_PROG(regName, value1); \ + WR1_PROG(regName, value2); \ + WR1_PROG(regName, value3); \ + WR1_PROG(regName, value4); \ + WR1_PROG(regName, value5); \ + WR1_PROG(regName, value6); \ + WR1_PROG(regName, value7); \ + WR1_PROG(regName, value8); \ + WR1_PROG(regName, value9); \ + WR1_PROG(regName, value10); \ + WR1_PROG(regName, value11); \ + WR1_PROG(regName, value12); \ + WR1_PROG(regName, value13); \ + WR1_PROG(regName, value14); \ + WR1_PROG(regName, value15); \ + WR1_PROG(regName, value16); \ + WR1_PROG(regName, value17); \ + WR1_PROG(regName, value18); \ + WR1_PROG(regName, value19); \ + WR1_PROG(regName, value20); \ + WR1_PROG(regName, value21); \ + WR1_PROG(regName, value22); \ + WR1_PROG(regName, value23); \ + WR1_PROG(regName, value24); \ + WR1_PROG(regName, value25); \ + WR1_PROG(regName, value26); \ + WR1_PROG(regName, value27); \ + WR1_PROG(regName, value28); \ + WR1_PROG(regName, value29); \ + WR1_PROG(regName, value30); \ + WR1_PROG(regName, value31); \ + WR1_PROG(regName, value32); \ + WR1_PROG(regName, value33); \ + WR1_PROG(regName, value34); \ + WR1_PROG(regName, value35); \ + WR1_PROG(regName, value36); \ + WR1_PROG(regName, value37); \ + WR1_PROG(regName, value38); \ + WR1_PROG(regName, value39); \ + WR1_PROG(regName, value40); \ + WR1_PROG(regName, value41); \ + WR1_PROG(regName, value42); \ + WR1_PROG(regName, value43); \ + WR1_PROG(regName, value44); \ + WR1_PROG(regName, value45); \ + WR1_PROG(regName, value46); \ + WR1_PROG(regName, value47) + +// [R WR 48 B0 B1 B2 B3 B4 .... B47] +#define WR64_PROG(regName, \ + value0, value1, value2, value3, value4, value5, value6, value7, value8, value9, \ + value10, value11, value12, value13, value14, value15, value16, value17, value18, value19, \ + value20, value21, value22, value23, value24, value25, value26, value27, value28, value29, \ + value30, value31, value32, value33, value34, value35, value36, value37, value38, value39, \ + value40, value41, value42, value43, value44, value45, value46, value47, value48, value49, \ + value50, value51, value52, value53, value54, value55, value56, value57, value58, value59, \ + value60, value61, value62, value63 \ + ) \ + WR1_PROG(regName, value0); \ + WR1_PROG(regName, value1); \ + WR1_PROG(regName, value2); \ + WR1_PROG(regName, value3); \ + WR1_PROG(regName, value4); \ + WR1_PROG(regName, value5); \ + WR1_PROG(regName, value6); \ + WR1_PROG(regName, value7); \ + WR1_PROG(regName, value8); \ + WR1_PROG(regName, value9); \ + WR1_PROG(regName, value10); \ + WR1_PROG(regName, value11); \ + WR1_PROG(regName, value12); \ + WR1_PROG(regName, value13); \ + WR1_PROG(regName, value14); \ + WR1_PROG(regName, value15); \ + WR1_PROG(regName, value16); \ + WR1_PROG(regName, value17); \ + WR1_PROG(regName, value18); \ + WR1_PROG(regName, value19); \ + WR1_PROG(regName, value20); \ + WR1_PROG(regName, value21); \ + WR1_PROG(regName, value22); \ + WR1_PROG(regName, value23); \ + WR1_PROG(regName, value24); \ + WR1_PROG(regName, value25); \ + WR1_PROG(regName, value26); \ + WR1_PROG(regName, value27); \ + WR1_PROG(regName, value28); \ + WR1_PROG(regName, value29); \ + WR1_PROG(regName, value30); \ + WR1_PROG(regName, value31); \ + WR1_PROG(regName, value32); \ + WR1_PROG(regName, value33); \ + WR1_PROG(regName, value34); \ + WR1_PROG(regName, value35); \ + WR1_PROG(regName, value36); \ + WR1_PROG(regName, value37); \ + WR1_PROG(regName, value38); \ + WR1_PROG(regName, value39); \ + WR1_PROG(regName, value40); \ + WR1_PROG(regName, value41); \ + WR1_PROG(regName, value42); \ + WR1_PROG(regName, value43); \ + WR1_PROG(regName, value44); \ + WR1_PROG(regName, value45); \ + WR1_PROG(regName, value46); \ + WR1_PROG(regName, value47); \ + WR1_PROG(regName, value48); \ + WR1_PROG(regName, value49); \ + WR1_PROG(regName, value50); \ + WR1_PROG(regName, value51); \ + WR1_PROG(regName, value52); \ + WR1_PROG(regName, value53); \ + WR1_PROG(regName, value54); \ + WR1_PROG(regName, value55); \ + WR1_PROG(regName, value56); \ + WR1_PROG(regName, value57); \ + WR1_PROG(regName, value58); \ + WR1_PROG(regName, value59); \ + WR1_PROG(regName, value60); \ + WR1_PROG(regName, value61); \ + WR1_PROG(regName, value62); \ + WR1_PROG(regName, value63) + +#endif // __SCE_ProcCommon_h__ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/private/inc/SCE_module.h b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/private/inc/SCE_module.h new file mode 100644 index 000000000..3e11bc3d6 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/private/inc/SCE_module.h @@ -0,0 +1,30 @@ +/*********************************************************************************************************************** + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef HW_SCE_MODULE_H +#define HW_SCE_MODULE_H + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define SCE_BASE 0x400E3000UL + +#endif // HW_SCE_MODULE_H diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/private/inc/hw_sce_ra_private.h b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/private/inc/hw_sce_ra_private.h new file mode 100644 index 000000000..f8e8dc0d0 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/private/inc/hw_sce_ra_private.h @@ -0,0 +1,356 @@ +#include "r_sce_if.h" +#include "SCE_ProcCommon.h" + +#ifndef HW_SCE_RA_PRIVATE_HEADER_FILE +#define HW_SCE_RA_PRIVATE_HEADER_FILE + +/********************************************************************************************************************** + Macro definitions + *********************************************************************************************************************/ + +/* Return code */ +#define FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT (0x10100) ///< Hardware resource is busy +#define FSP_ERR_CRYPTO_RSIP_FATAL (0x10101) ///< Hardware fatal error or unexpected return +#define FSP_ERR_CRYPTO_RSIP_FAIL (0x10102) ///< Internal error +#define FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL (0x10103) ///< Input key type is illegal +#define FSP_ERR_CRYPTO_RSIP_AUTHENTICATION (0x10104) ///< Authentication failed + +/* Various information. */ +#define HW_SCE_SRAM_WORD_SIZE (32U) +#define HW_SCE_SINST_WORD_SIZE (140U) +#define HW_SCE_SINST2_WORD_SIZE (16U) +#define HW_SCE_SHEAP_WORD_SIZE (1504U) +#define HW_SCE_MAC_SIZE (16U) + +// TODO: Replace these in the code +#define SIZE_AES_128BIT_KEYLEN_WORDS_WRAPPED (HW_SCE_AES128_KEY_INDEX_WORD_SIZE) +#define SIZE_AES_128BIT_KEYLEN_BITS_WRAPPED (SIZE_AES_128BIT_KEYLEN_WORDS_WRAPPED * 32U) +#define SIZE_AES_128BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_128BIT_KEYLEN_BITS_WRAPPED) / 8U) + +#define SIZE_AES_192BIT_KEYLEN_WORDS_WRAPPED (HW_SCE_AES192_KEY_INDEX_WORD_SIZE + 1U) /* Added 32 bits here to differentiate 192 wrapped key from 256 wrapped key in the psa_crypto stack. */ +#define SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED (SIZE_AES_192BIT_KEYLEN_WORDS_WRAPPED * 32U) +#define SIZE_AES_192BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED) / 8U) + +#define SIZE_AES_256BIT_KEYLEN_WORDS_WRAPPED (HW_SCE_AES256_KEY_INDEX_WORD_SIZE) +#define SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED (SIZE_AES_256BIT_KEYLEN_WORDS_WRAPPED * 32U) +#define SIZE_AES_256BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED) / 8U) + +#define SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED (416) +#define SIZE_AES_XTS_128BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED) / 8) +#define SIZE_AES_XTS_128BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED) / 32) + +#define SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED (672) +#define SIZE_AES_XTS_256BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED) / 8) +#define SIZE_AES_XTS_256BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED) / 32) +#define ECC_DUMMY_DOMAIN_PARAM_SIZE (1) + +/** DER encoded size for wrapped RSA key */ + #define RSA_WRAPPED_2048_EXPORTED_DER_SIZE_BYTES (1600U) + #define RSA_WRAPPED_3072_EXPORTED_DER_SIZE_BYTES (1500U) + #define RSA_WRAPPED_4096_EXPORTED_DER_SIZE_BYTES (1700U) + + #define ECC_256_FORMATTED_PUBLIC_KEY_LENGTH_WORDS (24U) + #define ECC_384_FORMATTED_PUBLIC_KEY_LENGTH_WORDS (32U) + #define ECC_521_FORMATTED_PUBLIC_KEY_LENGTH_WORDS (45U) + + #define ECC_256_PRIVATE_KEY_HRK_LENGTH_WORDS (13U) + #define ECC_256_PRIVATE_KEY_HRK_LENGTH_BITS (416U) + + #define ECC_384_PRIVATE_KEY_HRK_LENGTH_WORDS (17U) + #define ECC_384_PRIVATE_KEY_HRK_LENGTH_BITS (544U) + + #define ECC_521_PRIVATE_KEY_HRK_LENGTH_WORDS (25U) + #define ECC_521_PRIVATE_KEY_HRK_LENGTH_BITS (800U) + +/********************************************************************************************************************** + External global variables + *********************************************************************************************************************/ +extern uint32_t const S_FLASH[]; +extern uint32_t S_INST[HW_SCE_SINST_WORD_SIZE]; +extern uint32_t S_INST2[HW_SCE_SINST2_WORD_SIZE]; +extern uint32_t S_RAM[HW_SCE_SRAM_WORD_SIZE]; +extern uint32_t S_HEAP[HW_SCE_SHEAP_WORD_SIZE];extern uint32_t const DomainParam_NIST_P256[RSIP_PRV_WORD_SIZE_DOMAINPARAM_NIST_P256]; +extern uint32_t const DomainParam_NIST_P384[RSIP_PRV_WORD_SIZE_DOMAINPARAM_NIST_P384]; +extern uint32_t const DomainParam_Brainpool_256r1[RSIP_PRV_WORD_SIZE_DOMAINPARAM_BRAINPOOL_256R1]; +extern uint32_t const DomainParam_Brainpool_384r1[RSIP_PRV_WORD_SIZE_DOMAINPARAM_BRAINPOOL_384R1]; +extern uint32_t const DomainParam_Koblitz_secp256k1[RSIP_PRV_WORD_SIZE_DOMAINPARAM_KOBLITZ_SECP256K1]; + +extern uint32_t INST_DATA_SIZE; +extern uint32_t KEY_INDEX_SIZE; +/* ---------------------- control procedure related ---------------------- */ +void HW_SCE_p_func008 (void); +void HW_SCE_p_func043 (void); +void HW_SCE_p_func044 (void); +void HW_SCE_p_func048 (const uint32_t ARG1[]); +void HW_SCE_p_func049 (const uint32_t ARG1[]); +void HW_SCE_p_func056 (void); +void HW_SCE_p_func057 (const uint32_t ARG1[], const uint32_t ARG2[], uint32_t ARG3[]); +void HW_SCE_p_func058 (const uint32_t ARG1[], uint32_t ARG2); +void HW_SCE_p_func070 (const uint32_t ARG1[]); +void HW_SCE_p_func071 (const uint32_t ARG1[]); +void HW_SCE_p_func073 (const uint32_t ARG1[]); +void HW_SCE_p_func088 (void); +void HW_SCE_p_func093 (const uint32_t ARG1[], uint32_t ARG2[]); +void HW_SCE_p_func100 (uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void HW_SCE_p_func101 (uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void HW_SCE_p_func102 (uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void HW_SCE_p_func103 (void); +void HW_SCE_p_func205_r1 (void); +void HW_SCE_p_func206 (void); + +void HW_SCE_SoftwareResetSub (void); +fsp_err_t HW_SCE_SelfCheck1Sub (void); +fsp_err_t HW_SCE_SelfCheck2Sub (void); +fsp_err_t HW_SCE_LoadHukSub (const uint32_t InData_LC[]); +fsp_err_t HW_SCE_GenerateOemKeyIndexSub (const uint32_t InData_KeyType[], const uint32_t InData_Cmd[], const uint32_t InData_SharedKeyIndex[], const uint32_t InData_SessionKey[], const uint32_t InData_IV[], const uint32_t InData_InstData[], uint32_t OutData_KeyIndex[]); +fsp_err_t HW_SCE_OemKeyIndexValidationSub (const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[]); +fsp_err_t HW_SCE_GenerateAes128RandomKeyIndexSub (uint32_t OutData_KeyIndex[]); +fsp_err_t HW_SCE_GenerateAes256RandomKeyIndexSub (uint32_t OutData_KeyIndex[]); +fsp_err_t HW_SCE_GenerateEccRandomKeyIndexSub (const uint32_t InData_KeyMode[], const uint32_t InData_CurveType[], const uint32_t InData_DomainParam[], uint32_t OutData_PubKey[], uint32_t OutData_PrivKeyIndex[], uint32_t OutData_PrivKey[]); +fsp_err_t HW_SCE_GenerateRandomNumberSub (uint32_t OutData_Text[]); +fsp_err_t HW_SCE_ShaGenerateMessageDigestSub (const uint32_t InData_InitVal[], const uint32_t InData_PaddedMsg[], uint32_t OutData_MsgDigest[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_GhashSub (const uint32_t InData_HV[], const uint32_t InData_IV[], const uint32_t InData_Text[], uint32_t OutData_DataT[], const uint32_t MAX_CNT); +void HW_SCE_Aes128EncryptDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub (void); +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub (const uint32_t InData_KeyMode[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_Key[], const uint32_t InData_IV[]); +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_Key[], const uint32_t InData_IV[]); +void HW_SCE_Aes256EncryptDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256EncryptDecryptFinalSub (void); +fsp_err_t HW_SCE_Aes128GcmEncryptInitSub (const uint32_t InData_KeyMode[], const uint32_t InData_KeyIndex[], const uint32_t InData_Key[], const uint32_t InData_IV[]); +void HW_SCE_Aes128GcmEncryptUpdateAADSub (const uint32_t InData_DataA[], const uint32_t MAX_CNT); +void HW_SCE_Aes128GcmEncryptUpdateTransitionSub (void); +void HW_SCE_Aes128GcmEncryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128GcmEncryptFinalSub (const uint32_t InData_Text[], const uint32_t InData_TextLen[], const uint32_t InData_DataALen[], uint32_t OutData_Text[], uint32_t OutData_DataT[]); +fsp_err_t HW_SCE_Aes128GcmDecryptInitSub (const uint32_t InData_KeyMode[], const uint32_t InData_KeyIndex[], const uint32_t InData_Key[], const uint32_t InData_IV[]); +void HW_SCE_Aes128GcmDecryptUpdateAADSub (const uint32_t InData_DataA[], const uint32_t MAX_CNT); +void HW_SCE_Aes128GcmDecryptUpdateTransitionSub (void); +void HW_SCE_Aes128GcmDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128GcmDecryptFinalSub (const uint32_t InData_Text[], const uint32_t InData_TextLen[], const uint32_t InData_DataALen[], const uint32_t InData_DataT[], const uint32_t InData_DataTLen[], uint32_t OutData_Text[]); +fsp_err_t HW_SCE_Aes256GcmEncryptInitSub (const uint32_t InData_KeyMode[], const uint32_t InData_KeyIndex[], const uint32_t InData_Key[], const uint32_t InData_IV[]); +void HW_SCE_Aes256GcmEncryptUpdateAADSub (const uint32_t InData_DataA[], const uint32_t MAX_CNT); +void HW_SCE_Aes256GcmEncryptUpdateTransitionSub (void); +void HW_SCE_Aes256GcmEncryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256GcmEncryptFinalSub (const uint32_t InData_Text[], const uint32_t InData_TextLen[], const uint32_t InData_DataALen[], uint32_t OutData_Text[],uint32_t OutData_DataT[]); +fsp_err_t HW_SCE_Aes256GcmDecryptInitSub (const uint32_t InData_KeyMode[], const uint32_t InData_KeyIndex[], const uint32_t InData_Key[], const uint32_t InData_IV[]); +void HW_SCE_Aes256GcmDecryptUpdateAADSub (const uint32_t InData_DataA[], const uint32_t MAX_CNT); +void HW_SCE_Aes256GcmDecryptUpdateTransitionSub (void); +void HW_SCE_Aes256GcmDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256GcmDecryptFinalSub (const uint32_t InData_Text[], const uint32_t InData_TextLen[], const uint32_t InData_DataALen[], const uint32_t InData_DataT[], const uint32_t InData_DataTLen[], uint32_t OutData_Text[]); +fsp_err_t HW_SCE_EcdsaSignatureGenerateSub (const uint32_t InData_CurveType[], const uint32_t InData_KeyMode[], const uint32_t InData_KeyIndex[], const uint32_t InData_Key[], const uint32_t InData_MsgDgst[], const uint32_t InData_DomainParam[], uint32_t OutData_Signature[]); +fsp_err_t HW_SCE_EcdsaSignatureVerificationSub (const uint32_t InData_CurveType[], const uint32_t InData_Key[], const uint32_t InData_MsgDgst[], const uint32_t InData_Signature[], const uint32_t InData_DomainParam[]); +fsp_err_t HW_SCE_Ecc256ScalarMultiplicationSub (const uint32_t InData_CurveType[], const uint32_t InData_KeyMode[], const uint32_t InData_KeyIndex[], const uint32_t InData_Key[], const uint32_t InData_PubKey[], const uint32_t InData_DomainParam[], uint32_t OutData_R[]); +fsp_err_t HW_SCE_Ecc384ScalarMultiplicationSubAdaptor(const uint32_t InData_CurveType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_PubKey[], + const uint32_t InData_DomainParam[], + uint32_t OutData_R[]); +fsp_err_t HW_SCE_Ecc521ScalarMultiplicationSubAdaptor(const uint32_t InData_CurveType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_PubKey[], + const uint32_t InData_DomainParam[], + uint32_t OutData_R[]); +fsp_err_t HW_SCE_Aes128CcmDecryptFinalSubGeneral(const uint32_t *InData_Text, + const uint32_t *InData_TextLen, + const uint32_t *InData_MAC, + const uint32_t *InData_MACLength, + uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes128CcmEncryptInitSubGeneral (uint32_t InData_KeyType[], + uint32_t InData_DataType[], + uint32_t InData_Cmd[], + uint32_t InData_TextLen[], + uint32_t InData_KeyIndex[], + uint32_t InData_IV[], + uint32_t InData_Header[], + uint32_t InData_SeqNum[], + uint32_t Header_Len); +fsp_err_t HW_SCE_Aes192CcmEncryptInitSubGeneral (uint32_t InData_KeyType[], + uint32_t InData_DataType[], + uint32_t InData_Cmd[], + uint32_t InData_TextLen[], + uint32_t InData_KeyIndex[], + uint32_t InData_IV[], + uint32_t InData_Header[], + uint32_t InData_SeqNum[], + uint32_t Header_Len); +fsp_err_t HW_SCE_Aes256CcmEncryptInitSubGeneral (uint32_t InData_KeyType[], + uint32_t InData_DataType[], + uint32_t InData_Cmd[], + uint32_t InData_TextLen[], + uint32_t InData_KeyIndex[], + uint32_t InData_IV[], + uint32_t InData_Header[], + uint32_t InData_SeqNum[], + uint32_t Header_Len); +fsp_err_t HW_SCE_Aes128CcmDecryptInitSubGeneral (uint32_t InData_KeyType[], + uint32_t InData_DataType[], + uint32_t InData_Cmd[], + uint32_t InData_TextLen[], + uint32_t InData_MACLength[], + uint32_t InData_KeyIndex[], + uint32_t InData_IV[], + uint32_t InData_Header[], + uint32_t InData_SeqNum[], + uint32_t Header_Len); +fsp_err_t HW_SCE_Aes192CcmDecryptInitSubGeneral (uint32_t InData_KeyType[], + uint32_t InData_DataType[], + uint32_t InData_Cmd[], + uint32_t InData_TextLen[], + uint32_t InData_MACLength[], + uint32_t InData_KeyIndex[], + uint32_t InData_IV[], + uint32_t InData_Header[], + uint32_t InData_SeqNum[], + uint32_t Header_Len); +fsp_err_t HW_SCE_Aes256CcmDecryptInitSubGeneral (uint32_t InData_KeyType[],uint32_t InData_DataType[], + uint32_t InData_Cmd[],uint32_t InData_TextLen[],uint32_t InData_MACLength[],uint32_t InData_KeyIndex[], + uint32_t InData_IV[],uint32_t InData_Header[],uint32_t InData_SeqNum[],uint32_t Header_Len); +void HW_SCE_Aes128CcmEncryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +void HW_SCE_Aes128CcmDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +void HW_SCE_Aes192CcmEncryptUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128CcmEncryptFinalSubGeneral (const uint32_t *InData_Text, const uint32_t *InData_TextLen, + uint32_t *OutData_Text, uint32_t *OutData_MAC); +fsp_err_t HW_SCE_Aes128CmacFinal(const uint32_t InData_Cmd[], + const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_DataT[]); +fsp_err_t HW_SCE_Aes128CmacInit(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[]); +void HW_SCE_Aes128CmacUpdate(const uint32_t InData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128GcmDecryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes128GcmEncryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes192GcmDecryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes192GcmEncryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes256GcmDecryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_AesGcmEncryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes192CcmDecryptFinalSub(const uint32_t InData_Text[], const uint32_t InData_TextLen[], const uint32_t InData_MAC[], const uint32_t InData_MACLength[], uint32_t OutData_Text[]); +void HW_SCE_Aes192CcmDecryptUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +void HW_SCE_Aes192CcmDecryptUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192CcmEncryptFinalSub(const uint32_t InData_Text[], const uint32_t InData_TextLen[], uint32_t OutData_Text[], uint32_t OutData_MAC[]); +fsp_err_t HW_SCE_Aes192CmacFinal(const uint32_t InData_Cmd[], + const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_DataT[]); +fsp_err_t HW_SCE_Aes192CmacInit(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[]); +void HW_SCE_Aes192CmacUpdate(const uint32_t InData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192GcmDecryptFinalSub(const uint32_t InData_Text[], const uint32_t InData_TextLen[], const uint32_t InData_DataALen[], const uint32_t InData_DataT[], const uint32_t InData_DataTLen[], uint32_t OutData_Text[]); +fsp_err_t HW_SCE_Aes192GcmDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV); +void HW_SCE_Aes192GcmDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +void HW_SCE_Aes192GcmDecryptUpdateAADSub (const uint32_t InData_DataA[], const uint32_t MAX_CNT); +void HW_SCE_Aes192GcmDecryptUpdateTransitionSub (void); +fsp_err_t HW_SCE_Aes192GcmEncryptInitSub (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +fsp_err_t HW_SCE_Aes192GcmEncryptFinalSub(const uint32_t InData_Text[], const uint32_t InData_TextLen[], const uint32_t InData_DataALen[], uint32_t OutData_Text[], uint32_t OutData_DataT[]); +void HW_SCE_Aes192GcmEncryptUpdateAADSub(const uint32_t InData_DataA[], const uint32_t MAX_CNT); +void HW_SCE_Aes192GcmEncryptUpdateTransitionSub (void); +fsp_err_t HW_SCE_Aes256CcmDecryptFinalSub(const uint32_t InData_Text[], const uint32_t InData_TextLen[], const uint32_t InData_MAC[], const uint32_t InData_MACLength[], uint32_t OutData_Text[]); +void HW_SCE_Aes192GcmEncryptUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +void HW_SCE_Aes256CcmDecryptUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CcmEncryptFinalSub(const uint32_t InData_Text[], const uint32_t InData_TextLen[], uint32_t OutData_Text[], uint32_t OutData_MAC[]); +void HW_SCE_Aes256CcmEncryptUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CmacFinal(const uint32_t InData_Cmd[], + const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_DataT[]); +fsp_err_t HW_SCE_Aes256CmacInit(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[]); +void HW_SCE_Aes256CmacUpdate(const uint32_t InData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128XtsDecryptInitSub(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +fsp_err_t HW_SCE_Aes128XtsDecryptFinalSub(const uint32_t InData_TextBitLen[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +void HW_SCE_Aes128XtsDecryptUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128XtsEncryptFinalSub(const uint32_t InData_TextBitLen[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +fsp_err_t HW_SCE_Aes128XtsEncryptInitSub(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +void HW_SCE_Aes128XtsEncryptUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192EncryptDecryptFinalSub(void); +fsp_err_t HW_SCE_Aes192EncryptDecryptInitSub (const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +void HW_SCE_Aes192EncryptDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub (const uint32_t InData_KeyType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_Key[], const uint32_t InData_IV[]); +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]); + +fsp_err_t HW_SCE_Ecc256ScalarMultiplicationSub (const uint32_t InData_CurveType[], + const uint32_t InData_KeyMode[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_PubKey[], + const uint32_t InData_DomainParam[], + uint32_t OutData_R[]); +fsp_err_t HW_SCE_Ecc256ScalarMultiplicationSubAdaptor(const uint32_t InData_CurveType[], + const uint32_t InData_KeyMode[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_PubKey[], + const uint32_t InData_DomainParam[], + uint32_t OutData_R[]); +fsp_err_t HW_SCE_GenerateEccRandomKeyIndexSubAdaptor(const uint32_t *InData_CurveType, + const uint32_t *InData_Cmd, + const uint32_t *InData_KeyType, + const uint32_t InData_DomainParam[], + uint32_t *OutData_PubKeyIndex, + uint32_t *OutData_PubKey, + uint32_t *OutData_PrivKeyIndex, + uint32_t *OutData_PrivKey); +fsp_err_t HW_SCE_EcdsaSignatureGenerateSubAdaptor(const uint32_t InData_CurveType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_DomainParam[], + uint32_t OutData_Signature[]); +fsp_err_t HW_SCE_EcdsaSignatureVerificationSubAdaptor(const uint32_t InData_CurveType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[]); +fsp_err_t HW_SCE_EcdsaP384SignatureGenerateSubAdaptor(const uint32_t InData_CurveType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_DomainParam[], + uint32_t OutData_Signature[]); +fsp_err_t HW_SCE_EcdsaP521SignatureGenerateSubAdaptor(const uint32_t InData_CurveType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_DomainParam[], + uint32_t OutData_Signature[]); +fsp_err_t HW_SCE_EcdsaP384SignatureVerificationSubAdaptor(const uint32_t InData_CurveType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[]); +fsp_err_t HW_SCE_EcdsaP521SignatureVerificationSubAdaptor(const uint32_t InData_CurveType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[]); +fsp_err_t HW_SCE_GenerateEccP384RandomKeyIndexSubAdaptor(const uint32_t *InData_CurveType, + const uint32_t *InData_KeyType, + const uint32_t InData_DomainParam[], + uint32_t *OutData_PubKeyIndex, + uint32_t *OutData_PubKey, + uint32_t *OutData_PrivKeyIndex, + uint32_t *OutData_PrivKey); +fsp_err_t HW_SCE_Aes256GcmEncryptInitSubGeneral(uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum); +fsp_err_t HW_SCE_Aes256GcmDecryptInitSubGeneral(uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum); +uint32_t change_endian_long (uint32_t data); +fsp_err_t HW_SCE_EccEd25519ScalarMultiplicationSubAdaptor(const uint32_t InData_CurveType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_PubKey[], const uint32_t InData_DomainParam[], uint32_t OutData_R[]); + +#endif /* HW_SCE_RA_PRIVATE_HEADER_FILE */ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/public/inc/r_sce_if.h b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/public/inc/r_sce_if.h new file mode 100644 index 000000000..e9c73a6ea --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip_e11a/plainkey/public/inc/r_sce_if.h @@ -0,0 +1,1703 @@ +/********************************************************************************************************************** + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No + * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all + * applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM + * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES + * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO + * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of + * this software. By using this software, you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * + * Copyright (C) 2015-2020 Renesas Electronics Corporation. All rights reserved. + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * File Name : r_sce_if.h + * Version : 1.09 + * Description : Interface definition for the r_sce module. + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Includes , "Project Includes" + *********************************************************************************************************************/ + +// added for RA6M4 start +// #include "platform.h" +#include "bsp_api.h" + +// added for RA6M4 end + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ + +#ifndef R_SCE_IF_HEADER_FILE + #define R_SCE_IF_HEADER_FILE + +// added for RA6M4 start + #if 0 + +// added for RA6M4 end + + #if R_BSP_VERSION_MAJOR < 5 + #error "This module must use BSP module of Rev.5.00 or higher. Please use the BSP module of Rev.5.00 or higher." + #endif + #if (defined BSP_MCU_RX231 || defined BSP_MCU_RX23W) && (BSP_CFG_MCU_PART_VERSION == 0xB) /* B */ + #elif (defined BSP_MCU_RX66T || defined BSP_MCU_RX72T) && ((BSP_CFG_MCU_PART_FUNCTION == 0xE /* E */) || \ + (BSP_CFG_MCU_PART_FUNCTION == 0xF /* F */) || (BSP_CFG_MCU_PART_FUNCTION == 0x10 /* G */)) + #elif (defined BSP_MCU_RX65N || defined BSP_MCU_RX651) && (BSP_CFG_MCU_PART_ENCRYPTION_INCLUDED == true) + #elif (defined BSP_MCU_RX72M || defined BSP_MCU_RX72N || defined BSP_MCU_RX66N) && \ + (BSP_CFG_MCU_PART_FUNCTION == 0x11 /* H */) + #else + #error "Your MCU does not support SCE functions. Please confirm BSP_MCU_xxx macro in r_bsp_config.h." + #endif /* defined BSP_MCU_RX231 || defined BSP_MCU_RX23W && BSP_CFG_MCU_PART_VERSION == 0xB */ + +// added for RA6M4 start + #endif + +// added for RA6M4 end + +/* Version Number of API. */ + #define SCE_VERSION_MAJOR (1U) + #define SCE_VERSION_MINOR (9U) + +/* Various information. */ + #define HW_SCE_SRAM_WORD_SIZE (32U) + #define HW_SCE_SINST_WORD_SIZE (140U) + #define HW_SCE_SINST2_WORD_SIZE (16U) + #define HW_SCE_SHEAP_WORD_SIZE (1504U) + #define HW_SCE_MAC_SIZE (16U) + +/* For AES operation. */ + #define HW_SCE_AES128_KEY_INDEX_WORD_SIZE (12U) + #define HW_SCE_AES192_KEY_INDEX_WORD_SIZE (16U) + #define HW_SCE_AES256_KEY_INDEX_WORD_SIZE (16U) + #define HW_SCE_AES128_KEY_WORD_SIZE (4U) + #define HW_SCE_AES192_KEY_WORD_SIZE (8U) + #define HW_SCE_AES256_KEY_WORD_SIZE (8U) + #define HW_SCE_AES128_KEY_BYTE_SIZE (16U) + #define HW_SCE_AES192_KEY_BYTE_SIZE (32U) + #define HW_SCE_AES256_KEY_BYTE_SIZE (32U) + #define HW_SCE_AES_BLOCK_BYTE_SIZE (16U) + #define HW_SCE_AES_BLOCK_BIT_SIZE (128U) + #define HW_SCE_AES_CBC_IV_BYTE_SIZE (16U) + #define HW_SCE_AES_CTR_ICOUNTER_BYTE_SIZE (16U) + #define HW_SCE_AES_GCM_AAD_BLOCK_BYTE_SIZE (16U) + #define HW_SCE_AES_CCM_B_FORMAT_BYTE_SIZE (128U) + #define HW_SCE_AES_CCM_COUNTER_BYTE_SIZE (16U) + #define HW_SCE_AES128XTS_KEY_BYTE_SIZE (32U) + #define HW_SCE_AES256XTS_KEY_BYTE_SIZE (64U) + #define HW_SCE_AES128XTS_KEY_BIT_SIZE (256U) + #define HW_SCE_AES256XTS_KEY_BIT_SIZE (512U) + #define HW_SCE_AES_XTS_IV_BYTE_SIZE (16U) + #define HW_SCE_AES128XTS_KEY_INDEX_WORD_SIZE (13U) + #define HW_SCE_AES256XTS_KEY_INDEX_WORD_SIZE (21U) + +/* For TDES operation. */ + #define HW_SCE_TDES_KEY_INDEX_WORD_SIZE (16U) + #define HW_SCE_TDES_BLOCK_BYTE_SIZE (8U) + #define HW_SCE_TDES_CBC_IV_BYTE_SIZE (8U) + #define HW_SCE_TDES_KEY_WORD_SIZE (8U) + #define HW_SCE_TDES_KEY_BYTE_SIZE (32U) + +/* For ARC4 operation. */ +#define HW_SCE_ARC4_KEY_INDEX_WORD_SIZE (72U) +#define HW_SCE_ARC4_KEY_WORD_SIZE (64U) +#define HW_SCE_ARC4_KEY_BYTE_SIZE (256U) +#define HW_SCE_ARC4_BLOCK_BYTE_SIZE (16U) + +/* For SHA operation. */ +#define HW_SCE_SHA1_HASH_LENGTH_BYTE_SIZE (20U) +#define HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE (32U) +#define HW_SCE_SHA384_HASH_LENGTH_BYTE_SIZE (48U) +#define HW_SCE_SHA512_HASH_LENGTH_BYTE_SIZE (64U) +#define HW_SCE_SHA256_HASH_STATE_BUFFER_SIZE (8U) +#define HW_SCE_SHA384_HASH_STATE_BUFFER_SIZE (12U) +#define HW_SCE_SHA512_HASH_STATE_BUFFER_SIZE (16U) + +/* For MD5 operation. */ + #define HW_SCE_MD5_HASH_LENGTH_BYTE_SIZE (16U) + +/* For HMAC operation. */ + #define HW_SCE_HMAC_KEY_BYTE_SIZE (32U) + #define HW_SCE_HMAC_KEY_INDEX_BYTE_SIZE (32U) + #define HW_SCE_HMAC_KEY_INDEX_WORD_SIZE (8U) + + /* For RSA operation. */ + #define HW_SCE_RSA_1024_KEY_N_LENGTH_BYTE_SIZE (128U) + #define HW_SCE_RSA_1024_KEY_E_LENGTH_BYTE_SIZE (4U) + #define HW_SCE_RSA_1024_KEY_D_LENGTH_BYTE_SIZE (128U) + #define HW_SCE_RSA_2048_KEY_N_LENGTH_BYTE_SIZE (256U) + #define HW_SCE_RSA_2048_KEY_E_LENGTH_BYTE_SIZE (4U) + #define HW_SCE_RSA_2048_KEY_D_LENGTH_BYTE_SIZE (256U) + #define HW_SCE_RSA_3072_KEY_N_LENGTH_BYTE_SIZE (96 * 4U) + #define HW_SCE_RSA_3072_KEY_E_LENGTH_BYTE_SIZE (4U) + #define HW_SCE_RSA_3072_KEY_D_LENGTH_BYTE_SIZE (96 * 4U) + #define HW_SCE_RSA_4096_KEY_N_LENGTH_BYTE_SIZE (128 * 4U) + #define HW_SCE_RSA_4096_KEY_E_LENGTH_BYTE_SIZE (4U) + #define HW_SCE_RSA_4096_KEY_D_LENGTH_BYTE_SIZE (128 * 4U) + #define HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) + #define HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (36U) + #define HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) + #define HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (68U) + #define HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) + #define HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (68U) + #define HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) + #define HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (132U) + #define HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) + #define HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (19U) + #define HW_SCE_RSA_3072_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) + #define HW_SCE_RSA_3072_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (132U) + #define HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) + #define HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (19U) + #define HW_SCE_RSA_4096_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) + #define HW_SCE_RSA_4096_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (132U) + #define HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE (12U) + #define HW_SCE_RSA1024_NE_KEY_BYTE_SIZE (144U) + #define HW_SCE_RSA1024_ND_KEY_BYTE_SIZE (256U) + #define HW_SCE_RSA2048_NE_KEY_BYTE_SIZE (272U) + #define HW_SCE_RSA2048_ND_KEY_BYTE_SIZE (512U) + #define HW_SCE_RSA3072_NE_KEY_BYTE_SIZE (96 * 4 + 16U) + #define HW_SCE_RSA3072_ND_KEY_BYTE_SIZE (192 * 4U) + #define HW_SCE_RSA4096_NE_KEY_BYTE_SIZE (128 * 4 + 16U) + #define HW_SCE_RSA4096_ND_KEY_BYTE_SIZE (256 * 4U) + #define HW_SCE_RSA1024_NE_KEY_INDEX_WORD_SIZE (73U) + #define HW_SCE_RSA1024_ND_KEY_INDEX_WORD_SIZE (101U) + #define HW_SCE_RSA2048_NE_KEY_INDEX_WORD_SIZE (137U) + #define HW_SCE_RSA2048_ND_KEY_INDEX_WORD_SIZE (197U) + #define HW_SCE_RSA3072_NE_KEY_INDEX_WORD_SIZE (137U) + #define HW_SCE_RSA3072_ND_KEY_INDEX_WORD_SIZE (197U) + #define HW_SCE_RSA4096_NE_KEY_INDEX_WORD_SIZE (137U) + #define HW_SCE_RSA4096_ND_KEY_INDEX_WORD_SIZE (197U) + #define HW_SCE_RSA1024_RANDOM_PUBLIC_KEY_INDEX_WORD_SIZE (76U) + #define HW_SCE_RSA1024_RANDOM_PRIVATE_KEY_INDEX_WORD_SIZE (104U) + #define HW_SCE_RSA2048_RANDOM_PUBLIC_KEY_INDEX_WORD_SIZE (140U) + #define HW_SCE_RSA2048_RANDOM_PRIVATE_KEY_INDEX_WORD_SIZE (200U) + #define HW_SCE_RSA_RSAES_PKCS_MIN_KEY_N_BYTE_SIZE (11U) + #define HW_SCE_RSA_1024_DATA_BYTE_SIZE (128U) + #define HW_SCE_RSA_2048_DATA_BYTE_SIZE (256U) + #define HW_SCE_RSA_3072_DATA_BYTE_SIZE (96 * 4U) + #define HW_SCE_RSA_4096_DATA_BYTE_SIZE (128 * 4U) + + /* RSA HASH type. */ + #define HW_SCE_RSA_HASH_MD5 (0x01) /* MD5 */ + #define HW_SCE_RSA_HASH_SHA1 (0x02) /* SHA-1 */ + #define HW_SCE_RSA_HASH_SHA256 (0x03) /* SHA-256 */ + +/* For ECC operation. */ + #define HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) + #define HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (4U) + #define HW_SCE_ECC_KEY_LENGTH_BYTE_SIZE (112U) + #define HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO_WORD_SIZE (4U) + #define HW_SCE_ECC_PRIVATE_KEY_MANAGEMENT_INFO_WORD_SIZE (20U) + #define HW_SCE_ECC_PUBLIC_KEY_BYTE_SIZE (64U) + #define HW_SCE_ECC_P384_PUBLIC_KEY_BYTE_SIZE (96U) + #define HW_SCE_ECC_PRIVATE_KEY_BYTE_SIZE (32U) + #define HW_SCE_ECC_P384_PRIVATE_KEY_BYTE_SIZE (48U) + #define HW_SCE_ECDSA_DATA_BYTE_SIZE (64U) + #define HW_SCE_ECDSA_P384_DATA_BYTE_SIZE (96U) + #define HW_SCE_ECC_P521_PUBLIC_KEY_BYTE_SIZE (160U) + #define HW_SCE_ECDSA_P521_DATA_BYTE_SIZE (160U) + #define HW_SCE_SHARED_SECRET_KEY_INDEX_WORD_SIZE (16U) + #define HW_SCE_ALGORITHM_ID_ENCODED_DATA_BYTE_SIZE (7U) + #define HW_SCE_PRIVATE_KEY_WRAPPING_WORD_SIZE (5U) + +/* For KeyWrap. */ + #define HW_SCE_KEYWRAP_AES128 (0U) + #define HW_SCE_KEYWRAP_AES256 (2U) + +/* For TLS. */ +#define HW_SCE_TLS_RSA_NE_KEY_BYTE_SIZE (272U) +#define HW_SCE_TLS_RSA_NE_KEY_INDEX_WORD_SIZE (140U) +#define HW_SCE_TLS_ROOT_PUBLIC_KEY_WORD_SIZE (140U) +#define HW_SCE_TLS_P256_ECC_KEY_WORD_SIZE (16U) +#define HW_SCE_TLS_EPHEMERAL_ECDH_PUBLIC_KEY_WORD_SIZE (16U) +#define HW_SCE_TLS_MASTER_SECRET_WORD_SIZE (20U) +#define HW_SCE_TLS_GENERATE_MAC_KEY_WORD_SIZE (16U) +#define HW_SCE_TLS_GENERATE_AES128_CRYPTO_KEY_WORD_SIZE (12U) +#define HW_SCE_TLS_GENERATE_AES256_CRYPTO_KEY_WORD_SIZE (16U) +#define HW_SCE_TLS_GENERATE_VERIFY_DATA_BYTE_SIZE (12U) +#define HW_SCE_TLS_RSA_WITH_AES_128_CBC_SHA (0U) +#define HW_SCE_TLS_RSA_WITH_AES_256_CBC_SHA (1U) +#define HW_SCE_TLS_RSA_WITH_AES_128_CBC_SHA256 (2U) +#define HW_SCE_TLS_RSA_WITH_AES_256_CBC_SHA256 (3U) +#define HW_SCE_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 (4U) +#define HW_SCE_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 (5U) +#define HW_SCE_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 (6U) +#define HW_SCE_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (7U) +#define HW_SCE_TLS_GENERATE_CLIENT_VERIFY (0U) +#define HW_SCE_TLS_GENERATE_SERVER_VERIFY (1U) +#define HW_SCE_TLS_PUBLIC_KEY_TYPE_RSA2048 (0U) +#define HW_SCE_TLS_PUBLIC_KEY_TYPE_ECDSA_P256 (2U) + +/* TLS-HMAC. */ +#define HW_SCE_TLS_HMAC_KEY_INDEX_BYTE_SIZE (64U) +#define HW_SCE_TLS_HMAC_KEY_INDEX_WORD_SIZE (16U) + +/* TLS-AES. */ +#define HW_SCE_TLS_AES128_KEY_INDEX_WORD_SIZE (12U) +#define HW_SCE_TLS_AES256_KEY_INDEX_WORD_SIZE (16U) + +/* Key update. */ + #define HW_SCE_UPDATE_KEY_RING_INDEX_WORD_SIZE (16U) + + +/* Firmware update. */ +#define HW_SCE_FIRMWARE_MAC_BYTE_SIZE (16U) +#if defined BSP_MCU_RX231 || defined BSP_MCU_RX23W +#define HW_SCE_SECURE_BOOT_AREA_TOP (0xFFFF8000) +#else +#define HW_SCE_SECURE_BOOT_AREA_TOP (0xFFFF0000) +#endif /* defined BSP_MCU_RX231 || defined BSP_MCU_RX23W */ + +#define SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD (0) +#define SCE_OEM_KEY_SIZE_AES128_INST_DATA_WORD (8) +#define SCE_OEM_KEY_SIZE_AES192_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_AES256_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_AES128_XTS_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_AES256_XTS_INST_DATA_WORD (20) + +#define SCE_OEM_KEY_SIZE_RSA1024_PUBLICK_KEY_INST_DATA_WORD (40) +#define SCE_OEM_KEY_SIZE_RSA1024_PRIVATE_KEY_INST_DATA_WORD (68) +#define SCE_OEM_KEY_SIZE_RSA2048_PUBLICK_KEY_INST_DATA_WORD (72) +#define SCE_OEM_KEY_SIZE_RSA2048_PRIVATE_KEY_INST_DATA_WORD (132) +#define SCE_OEM_KEY_SIZE_RSA3072_PUBLICK_KEY_INST_DATA_WORD (104) +#define SCE_OEM_KEY_SIZE_RSA3072_PRIVATE_KEY_INST_DATA_WORD (196) +#define SCE_OEM_KEY_SIZE_RSA4096_PUBLICK_KEY_INST_DATA_WORD (136) +#define SCE_OEM_KEY_SIZE_RSA4096_PRIVATE_KEY_INST_DATA_WORD (260) + +#define SCE_OEM_KEY_SIZE_ECCP192_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCP192_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP224_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCP224_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP256_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCP256_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP384_PUBLICK_KEY_INST_DATA_WORD (28) +#define SCE_OEM_KEY_SIZE_ECCP384_PRIVATE_KEY_INST_DATA_WORD (16) +#define SCE_OEM_KEY_SIZE_HMAC_SHA224_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_HMAC_SHA256_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP256R1_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCP256R1_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP384R1_PUBLICK_KEY_INST_DATA_WORD (28) +#define SCE_OEM_KEY_SIZE_ECCP384R1_PRIVATE_KEY_INST_DATA_WORD (16) +#define SCE_OEM_KEY_SIZE_ECCP512R1_PUBLICK_KEY_INST_DATA_WORD (36) +#define SCE_OEM_KEY_SIZE_ECCP512R1_PRIVATE_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCSECP256K1_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCSECP256K1_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP521_PUBLICK_KEY_INST_DATA_WORD (44) +#define SCE_OEM_KEY_SIZE_ECCP521_PRIVATE_KEY_INST_DATA_WORD (24) +#define SCE_OEM_KEY_SIZE_HMAC_SHA384_INST_DATA_WORD (16) +#define SCE_OEM_KEY_SIZE_HMAC_SHA512_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_HMAC_SHA512_224_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_HMAC_SHA512_256_INST_DATA_WORD (20) + +/* DomainParams */ +#define RSIP_PRV_WORD_SIZE_DOMAINPARAM_NIST_P192 (72U) +#define RSIP_PRV_WORD_SIZE_DOMAINPARAM_NIST_P224 (72U) +#define RSIP_PRV_WORD_SIZE_DOMAINPARAM_NIST_P256 (72U) +#define RSIP_PRV_WORD_SIZE_DOMAINPARAM_NIST_P384 (104U) +#define RSIP_PRV_WORD_SIZE_DOMAINPARAM_NIST_P521 (168U) +#define RSIP_PRV_WORD_SIZE_DOMAINPARAM_NIST_ED25519 (76U) +#define RSIP_PRV_WORD_SIZE_DOMAINPARAM_BRAINPOOL_256R1 (72U) +#define RSIP_PRV_WORD_SIZE_DOMAINPARAM_BRAINPOOL_384R1 (104U) +#define RSIP_PRV_WORD_SIZE_DOMAINPARAM_BRAINPOOL_512R1 (136U) +#define RSIP_PRV_WORD_SIZE_DOMAINPARAM_KOBLITZ_SECP256K1 (72U) + +/********************************************************************************************************************** + * Global Typedef definitions + *********************************************************************************************************************/ + +/* request type for Callback of firmware update */ +typedef enum +{ + SCE_FW_CB_REQ_PRG_WT = 0U, + SCE_FW_CB_REQ_PRG_RD, + SCE_FW_CB_REQ_BUFF_CNT, + SCE_FW_CB_REQ_PRG_WT_LAST_BLK, + SCE_FW_CB_REQ_GET_UPDATE_PRG_CHKSUM, + SCE_FW_CB_REQ_STORE_MAC, +} SCE_FW_CB_REQ_TYPE; + +/* key index type */ +typedef enum +{ + SCE_KEY_INDEX_TYPE_INVALID = 0U, + SCE_KEY_INDEX_TYPE_AES128, + SCE_KEY_INDEX_TYPE_AES192, + SCE_KEY_INDEX_TYPE_AES256, + SCE_KEY_INDEX_TYPE_TDES, + SCE_KEY_INDEX_TYPE_HMAC_SHA1, + SCE_KEY_INDEX_TYPE_HMAC_SHA256, + SCE_KEY_INDEX_TYPE_RSA1024_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA1024_PRIVATE, + SCE_KEY_INDEX_TYPE_RSA2048_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA2048_PRIVATE, + SCE_KEY_INDEX_TYPE_RSA3072_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA3072_PRIVATE, + SCE_KEY_INDEX_TYPE_RSA4096_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA4096_PRIVATE, + SCE_KEY_INDEX_TYPE_AES128_FOR_TLS, + SCE_KEY_INDEX_TYPE_AES192_FOR_TLS, + SCE_KEY_INDEX_TYPE_AES256_FOR_TLS, + SCE_KEY_INDEX_TYPE_HMAC_SHA1_FOR_TLS, + SCE_KEY_INDEX_TYPE_HMAC_SHA256_FOR_TLS, + SCE_KEY_INDEX_TYPE_UPDATE_KEY_RING, + SCE_KEY_INDEX_TYPE_TLS_CA_CERTIFICATION_PUBLIC_KEY, + SCE_KEY_INDEX_TYPE_TLS_P256_ECC_KEY, + SCE_KEY_INDEX_TYPE_ECC_P192_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P224_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P256_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P384_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P192_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P224_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P256_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P384_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P256R1_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P384R1_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P256R1_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P384R1_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_SECP256K1_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_SECP256K1_PRIVATE, + SCE_KEY_INDEX_TYPE_ECDH_SHARED_SECRET, + SCE_KEY_INDEX_TYPE_AES128_XTS, + SCE_KEY_INDEX_TYPE_AES256_XTS, + SCE_KEY_INDEX_TYPE_AES128_GCM_FOR_DLMS_COSEM, + SCE_KEY_INDEX_TYPE_AES128_KEY_WRAP_FOR_DLMS_COSEM, + SCE_KEY_INDEX_TYPE_AES192_GCM_FOR_DLMS_COSEM, + SCE_KEY_INDEX_TYPE_AES192_KEY_WRAP_FOR_DLMS_COSEM, +} SCE_KEY_INDEX_TYPE; + +// added for RA6M4 start + + +typedef enum e_sce_hash_type +{ + SCE_OEM_CMD_HASH_TYPE_SHA1 = 0, + SCE_OEM_CMD_HASH_TYPE_SHA224 = 1, + SCE_OEM_CMD_HASH_TYPE_SHA256 = 2, + SCE_OEM_CMD_HASH_TYPE_SHA512_224 = 3, + SCE_OEM_CMD_HASH_TYPE_SHA512_256 = 4, + SCE_OEM_CMD_HASH_TYPE_SHA384 = 5, + SCE_OEM_CMD_HASH_TYPE_SHA512 = 6 +} sce_hash_type_t; + +typedef enum e_sce_hash_cmd +{ + SCE_OEM_CMD_HASH_ONESHOT = 0, + SCE_OEM_CMD_HASH_INIT_TO_SUSPEND = 1, + SCE_OEM_CMD_HASH_RESUME_TO_SUSPEND = 2, + SCE_OEM_CMD_HASH_RESUME_TO_FINAL = 3 +} sce_hash_cmd_t; + +typedef struct sce_hash_user_ctx +{ + uint32_t hash_data_state[HW_SCE_SHA256_HASH_STATE_BUFFER_SIZE]; + sce_hash_cmd_t operation_cmd; +}sce_hash_user_ctx_t; + +/* LIFE CYCLE */ +typedef enum +{ + SCE_CM1 = 0, + SCE_CM2, + SCE_SSD, + SCE_NSECSD, + SCE_DPL, + SCE_LCK_DBG, + SCE_LCK_BOOT, + SCE_RMA_REQ, + SCE_RMA_ACK, +} lifecycle_t; + + /* OEM Command */ + typedef enum e_sce_oem_cmd + { + SCE_OEM_CMD_AES128 = 5, + SCE_OEM_CMD_AES192, + SCE_OEM_CMD_AES256, + SCE_OEM_CMD_AES128_XTS, + SCE_OEM_CMD_AES256_XTS, + SCE_OEM_CMD_RSA1024_PUBLIC, + SCE_OEM_CMD_RSA1024_PRIVATE, + SCE_OEM_CMD_RSA2048_PUBLIC, + SCE_OEM_CMD_RSA2048_PRIVATE, + SCE_OEM_CMD_RSA3072_PUBLIC, + SCE_OEM_CMD_RSA3072_PRIVATE, + SCE_OEM_CMD_RSA4096_PUBLIC, + SCE_OEM_CMD_RSA4096_PRIVATE, + SCE_OEM_CMD_ECC_P192_PUBLIC, + SCE_OEM_CMD_ECC_P192_PRIVATE, + SCE_OEM_CMD_ECC_P224_PUBLIC, + SCE_OEM_CMD_ECC_P224_PRIVATE, + SCE_OEM_CMD_ECC_P256_PUBLIC, + SCE_OEM_CMD_ECC_P256_PRIVATE, + SCE_OEM_CMD_ECC_P384_PUBLIC, + SCE_OEM_CMD_ECC_P384_PRIVATE, + SCE_OEM_CMD_HMAC_SHA224, + SCE_OEM_CMD_HMAC_SHA256, + SCE_OEM_CMD_ECC_P256R1_PUBLIC, + SCE_OEM_CMD_ECC_P256R1_PRIVATE, + SCE_OEM_CMD_ECC_P384R1_PUBLIC, + SCE_OEM_CMD_ECC_P384R1_PRIVATE, + SCE_OEM_CMD_ECC_P512R1_PUBLIC, + SCE_OEM_CMD_ECC_P512R1_PRIVATE, + SCE_OEM_CMD_ECC_SECP256K1_PUBLIC, + SCE_OEM_CMD_ECC_SECP256K1_PRIVATE, + SCE_OEM_CMD_ECC_P521_PUBLIC, + SCE_OEM_CMD_ECC_P521_PRIVATE, + SCE_OEM_CMD_ED25519_PUBLIC, + SCE_OEM_CMD_ED25519_PRIVATE, + SCE_OEM_CMD_HMAC_SHA384, + SCE_OEM_CMD_HMAC_SHA512, + SCE_OEM_CMD_HMAC_SHA512_224, + SCE_OEM_CMD_HMAC_SHA512_256, + SCE_OEM_CMD_RSA2048_PUBLIC_FOR_TLS = 254, + SCE_OEM_CMD_NUM + } sce_oem_cmd_t; + + typedef enum e_sce_oem_key_type +{ + SCE_OEM_KEY_TYPE_ENCRYPTED = 0, + SCE_OEM_KEY_TYPE_PLAIN = 1 +} sce_oem_key_type_t; + +// added for RA6M4 end + +/* Byte data structure */ +typedef struct sce_byte_data +{ + uint8_t * pdata; + uint32_t data_length; + uint32_t data_type; +} sce_byte_data_t; + +/* RSA byte data structure */ +typedef sce_byte_data_t sce_rsa_byte_data_t; + +/* ECDSA byte data structure */ +typedef sce_byte_data_t sce_ecdsa_byte_data_t; + +/* AES key index data structure */ +typedef struct sce_aes_key_index +{ + uint32_t type; + + /* AES128, AES192, AES256, AES128 for TLS, AES256 for TLS, AES128 for XTS, AES256 for XTS are supported */ + uint32_t value[HW_SCE_AES256XTS_KEY_INDEX_WORD_SIZE]; +} sce_aes_key_index_t; + +/* TDES key index data structure */ +typedef struct sce_tdes_key_index +{ + uint32_t type; + uint32_t value[HW_SCE_TDES_KEY_INDEX_WORD_SIZE]; /* DES/TDES are supported */ +} sce_tdes_key_index_t; + +/* HMAC-SHA key index data structure */ +typedef struct sce_hmac_sha_key_index +{ + uint32_t type; + + /* HMAC-SHA1, HMAC-SHA256, HMAC-SHA for TLS, HMAC-SHA256 for TLS are supported */ + uint32_t value[HW_SCE_TLS_HMAC_KEY_INDEX_WORD_SIZE]; +} sce_hmac_sha_key_index_t; + +/* RSA 1024bit public key index data structure */ +typedef struct sce_rsa1024_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_1024_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t key_e[HW_SCE_RSA_1024_KEY_E_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; /* dummy data */ + uint32_t key_management_info2[HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; +} sce_rsa1024_public_key_index_t; + +/* RSA 1024bit private key index data structure */ +typedef struct sce_rsa1024_private_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_1024_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint32_t key_management_info2[HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; +} sce_rsa1024_private_key_index_t; + +/* RSA 2048bit public key index data structure */ +typedef struct sce_rsa2048_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_2048_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t key_e[HW_SCE_RSA_2048_KEY_E_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; /* dummy data */ + uint32_t key_management_info2[HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; +} sce_rsa2048_public_key_index_t; + +/* RSA 2048bit private key index data structure */ +typedef struct sce_rsa2048_private_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_2048_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint32_t key_management_info2[HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; +} sce_rsa2048_private_key_index_t; + +/* RSA 3072bit public key index data structure */ +typedef struct sce_rsa3072_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_3072_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t key_e[HW_SCE_RSA_3072_KEY_E_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; /* dummy data */ + uint32_t key_management_info2[HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; +} sce_rsa3072_public_key_index_t; + +/* RSA 3072bit private key index data structure */ +typedef struct sce_rsa3072_private_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_3072_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_3072_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint32_t key_management_info2[HW_SCE_RSA_3072_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; +} sce_rsa3072_private_key_index_t; + +/* RSA 4096bit public key index data structure */ +typedef struct sce_rsa4096_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_4096_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t key_e[HW_SCE_RSA_4096_KEY_E_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; /* dummy data */ + uint32_t key_management_info2[HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; +} sce_rsa4096_public_key_index_t; + +/* RSA 4096bit private key index data structure */ +typedef struct sce_rsa4096_private_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_4096_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_4096_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint32_t key_management_info2[HW_SCE_RSA_4096_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; +} sce_rsa4096_private_key_index_t; + +/* RSA 1024bit key index pair structure */ +typedef struct sce_rsa1024_key_pair_index +{ + sce_rsa1024_private_key_index_t priv_key; + sce_rsa1024_public_key_index_t pub_key; +} sce_rsa1024_key_pair_index_t; + +/* RSA 2048bit key index pair structure */ +typedef struct sce_rsa2048_key_pair_index +{ + sce_rsa2048_private_key_index_t priv_key; + sce_rsa2048_public_key_index_t pub_key; +} sce_rsa2048_key_pair_index_t; + +/* RSA 3072bit key index pair structure */ +typedef struct sce_rsa3072_key_pair_index +{ + sce_rsa3072_private_key_index_t priv_key; + sce_rsa3072_public_key_index_t pub_key; +} sce_rsa3072_key_pair_index_t; + +/* RSA 4096bit key index pair structure */ +typedef struct sce_rsa4096_key_pair_index +{ + sce_rsa4096_private_key_index_t priv_key; + sce_rsa4096_public_key_index_t pub_key; +} sce_rsa4096_key_pair_index_t; + +/* ECC P-192/224/256 public key index data structure */ +typedef struct sce_ecc_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_q[HW_SCE_ECC_PUBLIC_KEY_BYTE_SIZE]; + uint32_t key_management_info2[HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; + struct + { + uint8_t key[HW_SCE_ECC_PUBLIC_KEY_BYTE_SIZE]; + } plain_value; +} sce_ecc_public_key_index_t; + +/* ECC P-384 public key index data structure */ +typedef struct sce_ecc384_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_q[HW_SCE_ECC_P384_PUBLIC_KEY_BYTE_SIZE]; + uint32_t key_management_info2[HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; + struct + { + uint8_t key[HW_SCE_ECC_P384_PUBLIC_KEY_BYTE_SIZE]; + } plain_value; +} sce_ecc384_public_key_index_t; + +/* ECC P-521 public key index data structure */ +typedef struct sce_ecc521_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_q[HW_SCE_ECC_P521_PUBLIC_KEY_BYTE_SIZE]; + uint32_t key_management_info2[HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; + struct + { + uint8_t key[HW_SCE_ECC_P521_PUBLIC_KEY_BYTE_SIZE]; + } plain_value; +} sce_ecc521_public_key_index_t; + +/* ECC P-192/224/256 private key index data structure */ +typedef struct sce_ecc_private_key_index +{ + uint32_t type; + uint32_t value[HW_SCE_ECC_PRIVATE_KEY_MANAGEMENT_INFO_WORD_SIZE]; +} sce_ecc_private_key_index_t; + +/* ECC P-192/224/256 key index pair structure */ +typedef struct sce_ecc_key_pair_index +{ + sce_ecc_private_key_index_t priv_key; + sce_ecc_public_key_index_t pub_key; +} sce_ecc_key_pair_index_t; + +/* ECDH key index data structure */ +typedef struct sce_ecdh_key_index +{ + uint32_t type; + uint32_t value[HW_SCE_SHARED_SECRET_KEY_INDEX_WORD_SIZE]; +} sce_ecdh_key_index_t; + +/* TLS CA certification public key index data structure */ +typedef struct sce_tls_ca_certification_public_key_index +{ + uint32_t type; + uint32_t value[HW_SCE_TLS_ROOT_PUBLIC_KEY_WORD_SIZE]; +} sce_tls_ca_certification_public_key_index_t; + +/* TLS P-256 ECC key index data structure */ +typedef struct sce_tls_p256_ecc_key_index +{ + uint32_t type; + uint32_t value[HW_SCE_TLS_P256_ECC_KEY_WORD_SIZE]; +} sce_tls_p256_ecc_key_index_t; + +/* Update key ring index data structure */ +typedef struct sce_update_key_ring +{ + uint32_t type; + uint32_t value[HW_SCE_UPDATE_KEY_RING_INDEX_WORD_SIZE]; +} sce_update_key_ring_t; + +/* The work area for AES */ +typedef struct sce_aes_handle +{ + uint32_t id; + sce_aes_key_index_t key_index; + uint32_t current_input_data_size; + uint8_t last_1_block_as_fraction[HW_SCE_AES_BLOCK_BYTE_SIZE]; + uint8_t last_2_block_as_fraction[HW_SCE_AES_BLOCK_BYTE_SIZE * 2]; + uint8_t current_ivec[HW_SCE_AES_CBC_IV_BYTE_SIZE]; + uint8_t current_icounter[HW_SCE_AES_CTR_ICOUNTER_BYTE_SIZE]; + uint8_t flag_call_init; +} sce_aes_handle_t; + +/* The work area for TDES */ +typedef struct sce_tdes_handle +{ + uint32_t id; + sce_tdes_key_index_t key_index; + uint32_t current_input_data_size; + uint8_t last_1_block_as_fraction[HW_SCE_TDES_BLOCK_BYTE_SIZE]; + uint8_t current_ivec[HW_SCE_TDES_CBC_IV_BYTE_SIZE * 2]; + uint8_t flag_call_init; +} sce_tdes_handle_t; + +/* The work area for MD5 */ +typedef struct sce_sha_md5_handle +{ + uint32_t id; + uint8_t sha_buffer[HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE * 4]; + uint32_t all_received_length; + uint32_t buffering_length; + + /* SHA1(20byte), SHA256(32byte), MD5(16byte) are supported */ + uint8_t current_hash[HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE]; + uint8_t flag_call_init; +} sce_sha_md5_handle_t; + +/* The work area for HMAC-SHA */ +typedef struct sce_hmac_sha_handle +{ + uint32_t id; + sce_hmac_sha_key_index_t key_index; + uint8_t hmac_buffer[HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE * 4]; + uint32_t all_received_length; + uint32_t buffering_length; + uint8_t flag_call_init; +} sce_hmac_sha_handle_t; + +/* The work area for CMAC */ +typedef struct sce_cmac_handle +{ + uint32_t id; + sce_aes_key_index_t key_index; + uint8_t cmac_buffer[HW_SCE_AES_BLOCK_BYTE_SIZE]; + uint32_t all_received_length; + uint32_t buffering_length; + uint8_t flag_call_init; +} sce_cmac_handle_t; + +/* The work area for GCM */ +typedef struct sce_gcm_handle +{ + uint32_t id; + sce_aes_key_index_t key_index; + uint8_t gcm_buffer[HW_SCE_AES_BLOCK_BYTE_SIZE]; + uint8_t gcm_aad_buffer[HW_SCE_AES_GCM_AAD_BLOCK_BYTE_SIZE]; + uint32_t all_received_length; + uint32_t all_received_aad_length; + uint32_t buffering_length; + uint32_t buffering_aad_length; + uint8_t flag_call_init; + uint8_t flag_update_input_data; +} sce_gcm_handle_t; + +/* The work area for CCM */ +typedef struct sce_ccm_handle +{ + uint32_t id; + sce_aes_key_index_t key_index; + uint8_t formatted_data[HW_SCE_AES_CCM_B_FORMAT_BYTE_SIZE]; + uint8_t counter[HW_SCE_AES_CCM_COUNTER_BYTE_SIZE]; + uint8_t ccm_buffer[HW_SCE_AES_BLOCK_BYTE_SIZE]; + uint32_t all_received_length; + uint32_t buffering_length; + uint8_t flag_call_init; +} sce_ccm_handle_t; + +/* The work area for ECDH */ +typedef struct sce_ecdh_handle +{ + uint32_t id; + uint32_t flag_use_key_id; + uint32_t key_id; + uint32_t key_type; + uint8_t flag_call_init; + uint8_t flag_call_make_public; + uint8_t flag_call_read_public; + uint8_t flag_call_shared_secret; +} sce_ecdh_handle_t; + +/* The work area for firmware update */ +typedef struct sce_firmware_generate_mac_resume_handle +{ + uint32_t iLoop; + uint32_t counter; + uint32_t previous_counter; + bool use_resume_flag; +} sce_firmware_generate_mac_resume_handle_t; + +/* The callback function pointer type for HW_SCE_GenerateFirmwareMAC */ +typedef void (* SCE_GEN_MAC_CB_FUNC_T)(SCE_FW_CB_REQ_TYPE req_type, uint32_t iLoop, uint32_t * counter, + uint32_t * InData_UpProgram, uint32_t * OutData_Program, uint32_t MAX_CNT); + +/********************************************************************************************************************** + * External global variables + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Exported global functions + *********************************************************************************************************************/ +fsp_err_t HW_SCE_Open(lifecycle_t lifecycle, + sce_tls_ca_certification_public_key_index_t * key_index_1, + sce_update_key_ring_t * key_index_2); +fsp_err_t HW_SCE_Close(void); +void HW_SCE_SoftwareReset(void); +fsp_err_t HW_SCE_SelfCheck2(void); +fsp_err_t HW_SCE_SelfCheck3(void); +fsp_err_t HW_SCE_McuSpecificInit (void); + +// added for RA6M4 start +fsp_err_t HW_SCE_FwIntegrityCheck(void); +fsp_err_t HW_SCE_UpdateOemKeyIndex(lifecycle_t lifecycle, + sce_oem_cmd_t key_type, + uint8_t * iv, + uint8_t * encrypted_oem_key, + uint32_t * key_index); + +// added for RA6M4 end + +fsp_err_t HW_SCE_GenerateAes128KeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateAes192KeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateAes256KeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateTdesKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_tdes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa1024PublicKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa1024_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa1024PrivateKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa1024_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa2048PublicKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa2048_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa2048PrivateKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa2048_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa3072PublicKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa3072_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa3072PrivateKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa3072_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa4096PublicKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa4096_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa4096PrivateKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa4096_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateTlsRsaPublicKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_tls_ca_certification_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP192PublicKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP224PublicKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP256PublicKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP384PublicKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP192PrivateKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP224PrivateKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP256PrivateKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP384PrivateKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateSha1HmacKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_hmac_sha_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateSha256HmacKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_hmac_sha_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateTlsP256EccKeyIndex(sce_tls_p256_ecc_key_index_t * tls_p256_ecc_key_index, + uint8_t * ephemeral_ecdh_public_key); +fsp_err_t HW_SCE_GenerateAes128RandomKeyIndex(sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateAes192RandomKeyIndex(sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateAes256RandomKeyIndex(sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateAes128XtsRandomKeyIndex(sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateAes256XtsRandomKeyIndex(sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa1024RandomKeyIndex(sce_rsa1024_key_pair_index_t * key_pair_index); +fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndex(sce_rsa2048_key_pair_index_t * key_pair_index); +fsp_err_t HW_SCE_GenerateRsa3072RandomKeyIndex(sce_rsa3072_key_pair_index_t * key_pair_index); +fsp_err_t HW_SCE_GenerateRsa4096RandomKeyIndex(sce_rsa4096_key_pair_index_t * key_pair_index); +fsp_err_t HW_SCE_GenerateTdesRandomKeyIndex(sce_tdes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP192RandomKeyIndex(uint32_t * indata_curvetype, sce_ecc_key_pair_index_t * key_pair_index); +fsp_err_t HW_SCE_GenerateEccP224RandomKeyIndex(uint32_t * indata_curvetype, sce_ecc_key_pair_index_t * key_pair_index); +fsp_err_t HW_SCE_GenerateEccP256RandomKeyIndex(uint32_t * indata_curvetype, sce_ecc_key_pair_index_t * key_pair_index); +fsp_err_t HW_SCE_GenerateEccP384RandomKeyIndex(uint32_t * indata_curvetype, sce_ecc_key_pair_index_t * key_pair_index); +fsp_err_t HW_SCE_GenerateRandomNumber(uint32_t * random); +fsp_err_t HW_SCE_GenerateUpdateKeyRingKeyIndex(lifecycle_t lifecycle, + uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_update_key_ring_t * key_index); +uint32_t HW_SCE_GetVersion(void); + +fsp_err_t HW_SCE_GenerateAes128PlainKeyIndex(uint8_t * plain_key, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateAes192PlainKeyIndex(uint8_t * plain_key, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateAes256PlainKeyIndex(uint8_t * plain_key, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateAes128XtsPlainKeyIndex(uint8_t * plain_key, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateAes256XtsPlainKeyIndex(uint8_t * plain_key, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa2048PublicPlainKeyIndex(uint8_t * plain_key, sce_rsa2048_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa2048PrivatePlainKeyIndex(uint8_t * plain_key, sce_rsa2048_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa3072PublicPlainKeyIndex(uint8_t * plain_key, sce_rsa3072_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa3072PrivatePlainKeyIndex(uint8_t * plain_key, sce_rsa3072_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa4096PublicPlainKeyIndex(uint8_t * plain_key, sce_rsa4096_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa4096PrivatePlainKeyIndex(uint8_t * plain_key, sce_rsa4096_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP224PublicPlainKeyIndex(uint8_t * plain_key, sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP256PublicPlainKeyIndex(uint8_t * plain_key, sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP384PublicPlainKeyIndex(uint8_t * plain_key, sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP224PrivatePlainKeyIndex(uint8_t * plain_key, sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP256PrivatePlainKeyIndex(uint8_t * plain_key, sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP384PrivatePlainKeyIndex(uint8_t * plain_key, sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateSha256HmacPlainKeyIndex(uint8_t * plain_key, sce_hmac_sha_key_index_t * key_index); + +fsp_err_t HW_SCE_GenerateEccP256r1PublicPlainKeyIndex(uint8_t * plain_key, sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP384r1PublicPlainKeyIndex(uint8_t * plain_key, sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP256r1PrivatePlainKeyIndex(uint8_t * plain_key, sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP384r1PrivatePlainKeyIndex(uint8_t * plain_key, sce_ecc_private_key_index_t * key_index); + +fsp_err_t HW_SCE_GenerateEccSecp256k1PublicPlainKeyIndex(uint8_t * plain_key, sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccSecp256k1PrivatePlainKeyIndex(uint8_t * plain_key, sce_ecc_private_key_index_t * key_index); + +fsp_err_t HW_SCE_UpdateAes128KeyIndex(lifecycle_t lifecycle, + uint8_t * iv, + uint8_t * encrypted_key, + sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateAes192KeyIndex(lifecycle_t lifecycle, + uint8_t * iv, + uint8_t * encrypted_key, + sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateAes256KeyIndex(lifecycle_t lifecycle, + uint8_t * iv, + uint8_t * encrypted_key, + sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateAes128XtsKeyIndex(lifecycle_t lifecycle, + uint8_t * iv, + uint8_t * encrypted_key, + sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateAes256XtsKeyIndex(lifecycle_t lifecycle, + uint8_t * iv, + uint8_t * encrypted_key, + sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateTdesKeyIndex(uint8_t * iv, uint8_t * encrypted_key, sce_tdes_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateRsa1024PublicKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa1024_public_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateRsa1024PrivateKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa1024_private_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateRsa2048PublicKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa2048_public_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateRsa2048PrivateKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa2048_private_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateRsa3072PublicKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa3072_public_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateRsa3072PrivateKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa3072_private_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateRsa4096PublicKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa4096_public_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateRsa4096PrivateKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa4096_private_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateTlsRsaPublicKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_tls_ca_certification_public_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateEccP192PublicKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateEccP224PublicKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateEccP256PublicKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateEccP384PublicKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateEccP192PrivateKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateEccP224PrivateKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateEccP256PrivateKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateEccP384PrivateKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_Ecc256ScalarMultiplication(uint32_t * InData_CurveType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_PubKey, + uint32_t * OutData_R); +fsp_err_t HW_SCE_Ecc384ScalarMultiplication(uint32_t * InData_CurveType, + uint32_t * InData_KeyIndex, + uint32_t * InData_PubKey, + uint32_t * OutData_R); +fsp_err_t HW_SCE_UpdateSha1HmacKeyIndex(uint8_t * iv, uint8_t * encrypted_key, sce_hmac_sha_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateSha256HmacKeyIndex(uint8_t * iv, uint8_t * encrypted_key, sce_hmac_sha_key_index_t * key_index); + +fsp_err_t HW_SCE_StartUpdateFirmware(void); +fsp_err_t HW_SCE_GenerateFirmwareMAC(uint32_t * InData_KeyIndex, + uint32_t * InData_SessionKey, + uint32_t * InData_UpProgram, + uint32_t * InData_IV, + uint32_t * OutData_Program, + uint32_t MAX_CNT, + SCE_GEN_MAC_CB_FUNC_T p_callback, + sce_firmware_generate_mac_resume_handle_t * sce_firmware_generate_mac_resume_handle); +fsp_err_t HW_SCE_VerifyFirmwareMAC(uint32_t * InData_Program, uint32_t MAX_CNT, uint32_t * InData_MAC); + +fsp_err_t HW_SCE_Aes128EcbEncryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_Aes128EcbEncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes128EcbEncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t HW_SCE_Aes128EcbDecryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_Aes128EcbDecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes128EcbDecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); +fsp_err_t HW_SCE_Aes128CbcEncryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_Aes128CbcEncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes128CbcEncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t HW_SCE_Aes128CbcDecryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_Aes128CbcDecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes128CbcDecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + +fsp_err_t HW_SCE_Aes192EcbEncryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_Aes192EcbEncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes192EcbEncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t HW_SCE_Aes192EcbDecryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_Aes192EcbDecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes192EcbDecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); +fsp_err_t HW_SCE_Aes192CbcEncryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_Aes192CbcEncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes192CbcEncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t HW_SCE_Aes192CbcDecryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_Aes192CbcDecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes192CbcDecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + +fsp_err_t HW_SCE_Aes256EcbEncryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_Aes256EcbEncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes256EcbEncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t HW_SCE_Aes256EcbDecryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_Aes256EcbDecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes256EcbDecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); +fsp_err_t HW_SCE_Aes256CbcEncryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_Aes256CbcEncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes256CbcEncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t HW_SCE_Aes256CbcDecryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_Aes256CbcDecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes256CbcDecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + +fsp_err_t HW_SCE_Aes128CtrEncryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * icounter); +fsp_err_t HW_SCE_Aes128CtrEncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes128CtrEncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t HW_SCE_Aes128CtrDecryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * icounter); +fsp_err_t HW_SCE_Aes128CtrDecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes128CtrDecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + +fsp_err_t HW_SCE_Aes192CtrEncryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * icounter); +fsp_err_t HW_SCE_Aes192CtrEncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes192CtrEncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t HW_SCE_Aes192CtrDecryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * icounter); +fsp_err_t HW_SCE_Aes192CtrDecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes192CtrDecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + +fsp_err_t HW_SCE_Aes256CtrEncryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * icounter); +fsp_err_t HW_SCE_Aes256CtrEncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes256CtrEncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t HW_SCE_Aes256CtrDecryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * icounter); +fsp_err_t HW_SCE_Aes256CtrDecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes256CtrDecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + +fsp_err_t HW_SCE_Aes128XtsEncryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_Aes128XtsEncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t text_bitlen); +fsp_err_t HW_SCE_Aes128XtsEncryptFinal(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t text_bitlen); +fsp_err_t HW_SCE_Aes128XtsDecryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_Aes128XtsDecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t text_bitlen); +fsp_err_t HW_SCE_Aes128XtsDecryptFinal(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t text_bitlen); +fsp_err_t HW_SCE_Aes256XtsEncryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_Aes256XtsEncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t text_bitlen); +fsp_err_t HW_SCE_Aes256XtsEncryptFinal(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t text_bitlen); +fsp_err_t HW_SCE_Aes256XtsDecryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_Aes256XtsDecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t text_bitlen); +fsp_err_t HW_SCE_Aes256XtsDecryptFinal(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t text_bitlen); + +fsp_err_t HW_SCE_Aes128GcmEncryptInit(sce_gcm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * ivec, + uint32_t ivec_len); +fsp_err_t HW_SCE_Aes128GcmEncryptUpdate(sce_gcm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_data_len, + uint8_t * aad, + uint32_t aad_len); +fsp_err_t HW_SCE_Aes128GcmEncryptFinal(sce_gcm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_data_len, + uint8_t * atag); +fsp_err_t HW_SCE_Aes128GcmDecryptInit(sce_gcm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * ivec, + uint32_t ivec_len); +fsp_err_t HW_SCE_Aes128GcmDecryptUpdate(sce_gcm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_data_len, + uint8_t * aad, + uint32_t aad_len); +fsp_err_t HW_SCE_Aes128GcmDecryptFinal(sce_gcm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_data_len, + uint8_t * atag, + uint32_t atag_len); + +fsp_err_t HW_SCE_Aes192GcmEncryptInit(sce_gcm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * ivec, + uint32_t ivec_len); +fsp_err_t HW_SCE_Aes192GcmEncryptUpdate(sce_gcm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_data_len, + uint8_t * aad, + uint32_t aad_len); +fsp_err_t HW_SCE_Aes192GcmEncryptFinal(sce_gcm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_data_len, + uint8_t * atag); +fsp_err_t HW_SCE_Aes192GcmDecryptInit(sce_gcm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * ivec, + uint32_t ivec_len); +fsp_err_t HW_SCE_Aes192GcmDecryptUpdate(sce_gcm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_data_len, + uint8_t * aad, + uint32_t aad_len); +fsp_err_t HW_SCE_Aes192GcmDecryptFinal(sce_gcm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_data_len, + uint8_t * atag, + uint32_t atag_len); + +fsp_err_t HW_SCE_Aes256GcmEncryptInit(sce_gcm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * ivec, + uint32_t ivec_len); +fsp_err_t HW_SCE_Aes256GcmEncryptUpdate(sce_gcm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_data_len, + uint8_t * aad, + uint32_t aad_len); +fsp_err_t HW_SCE_Aes256GcmEncryptFinal(sce_gcm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_data_len, + uint8_t * atag); +fsp_err_t HW_SCE_Aes256GcmDecryptInit(sce_gcm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * ivec, + uint32_t ivec_len); +fsp_err_t HW_SCE_Aes256GcmDecryptUpdate(sce_gcm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_data_len, + uint8_t * aad, + uint32_t aad_len); +fsp_err_t HW_SCE_Aes256GcmDecryptFinal(sce_gcm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_data_len, + uint8_t * atag, + uint32_t atag_len); + +fsp_err_t HW_SCE_Aes128CcmEncryptInit(sce_ccm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * nonce, + uint32_t nonce_len, + uint8_t * adata, + uint8_t a_len, + uint32_t payload_len, + uint32_t mac_len); +fsp_err_t HW_SCE_Aes128CcmEncryptUpdate(sce_ccm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes128CcmEncryptFinal(sce_ccm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_length, + uint8_t * mac, + uint32_t mac_length); +fsp_err_t HW_SCE_Aes128CcmDecryptInit(sce_ccm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * nonce, + uint32_t nonce_len, + uint8_t * adata, + uint8_t a_len, + uint32_t payload_len, + uint32_t mac_len); +fsp_err_t HW_SCE_Aes128CcmDecryptUpdate(sce_ccm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes128CcmDecryptFinal(sce_ccm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_length, + uint8_t * mac, + uint32_t mac_length); + +fsp_err_t HW_SCE_Aes192CcmEncryptInit(sce_ccm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * nonce, + uint32_t nonce_len, + uint8_t * adata, + uint8_t a_len, + uint32_t payload_len, + uint32_t mac_len); +fsp_err_t HW_SCE_Aes192CcmEncryptUpdate(sce_ccm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes192CcmEncryptFinal(sce_ccm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_length, + uint8_t * mac, + uint32_t mac_length); +fsp_err_t HW_SCE_Aes192CcmDecryptInit(sce_ccm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * nonce, + uint32_t nonce_len, + uint8_t * adata, + uint8_t a_len, + uint32_t payload_len, + uint32_t mac_len); +fsp_err_t HW_SCE_Aes192CcmDecryptUpdate(sce_ccm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes192CcmDecryptFinal(sce_ccm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_length, + uint8_t * mac, + uint32_t mac_length); + +fsp_err_t HW_SCE_Aes256CcmEncryptInit(sce_ccm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * nonce, + uint32_t nonce_len, + uint8_t * adata, + uint8_t a_len, + uint32_t payload_len, + uint32_t mac_len); +fsp_err_t HW_SCE_Aes256CcmEncryptUpdate(sce_ccm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes256CcmEncryptFinal(sce_ccm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_length, + uint8_t * mac, + uint32_t mac_length); +fsp_err_t HW_SCE_Aes256CcmDecryptInit(sce_ccm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * nonce, + uint32_t nonce_len, + uint8_t * adata, + uint8_t a_len, + uint32_t payload_len, + uint32_t mac_len); +fsp_err_t HW_SCE_Aes256CcmDecryptUpdate(sce_ccm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes256CcmDecryptFinal(sce_ccm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_length, + uint8_t * mac, + uint32_t mac_length); + +fsp_err_t HW_SCE_Aes128CmacGenerateInit(sce_cmac_handle_t * handle, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_Aes128CmacGenerateUpdate(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t HW_SCE_Aes128CmacGenerateFinal(sce_cmac_handle_t * handle, uint8_t * mac); +fsp_err_t HW_SCE_Aes128CmacVerifyInit(sce_cmac_handle_t * handle, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_Aes128CmacVerifyUpdate(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t HW_SCE_Aes128CmacVerifyFinal(sce_cmac_handle_t * handle, uint8_t * mac, uint32_t mac_length); +fsp_err_t HW_SCE_Aes256CmacGenerateInit(sce_cmac_handle_t * handle, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_Aes256CmacGenerateUpdate(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t HW_SCE_Aes256CmacGenerateFinal(sce_cmac_handle_t * handle, uint8_t * mac); +fsp_err_t HW_SCE_Aes256CmacVerifyInit(sce_cmac_handle_t * handle, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_Aes256CmacVerifyUpdate(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t HW_SCE_Aes256CmacVerifyFinal(sce_cmac_handle_t * handle, uint8_t * mac, uint32_t mac_length); + +fsp_err_t HW_SCE_TdesEcbEncryptInit(sce_tdes_handle_t * handle, sce_tdes_key_index_t * key_index); +fsp_err_t HW_SCE_TdesEcbEncryptUpdate(sce_tdes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_TdesEcbEncryptFinal(sce_tdes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t HW_SCE_TdesEcbDecryptInit(sce_tdes_handle_t * handle, sce_tdes_key_index_t * key_index); +fsp_err_t HW_SCE_TdesEcbDecryptUpdate(sce_tdes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_TdesEcbDecryptFinal(sce_tdes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); +fsp_err_t HW_SCE_TdesCbcEncryptInit(sce_tdes_handle_t * handle, sce_tdes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_TdesCbcEncryptUpdate(sce_tdes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_TdesCbcEncryptFinal(sce_tdes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t HW_SCE_TdesCbcDecryptInit(sce_tdes_handle_t * handle, sce_tdes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_TdesCbcDecryptUpdate(sce_tdes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_TdesCbcDecryptFinal(sce_tdes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + +fsp_err_t HW_SCE_Md5Init(sce_sha_md5_handle_t * handle); +fsp_err_t HW_SCE_Md5Update(sce_sha_md5_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t HW_SCE_Md5Final(sce_sha_md5_handle_t * handle, uint8_t * digest, uint32_t * digest_length); + +fsp_err_t HW_SCE_Sha1Init(sce_sha_md5_handle_t * handle); +fsp_err_t HW_SCE_Sha1Update(sce_sha_md5_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t HW_SCE_Sha1Final(sce_sha_md5_handle_t * handle, uint8_t * digest, uint32_t * digest_length); +fsp_err_t HW_SCE_Sha256Init(sce_sha_md5_handle_t * handle); +fsp_err_t HW_SCE_Sha256Update(sce_sha_md5_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t HW_SCE_Sha256Final(sce_sha_md5_handle_t * handle, uint8_t * digest, uint32_t * digest_length); + +fsp_err_t HW_SCE_Sha1HmacGenerateInit(sce_hmac_sha_handle_t * handle, sce_hmac_sha_key_index_t * key_index); +fsp_err_t HW_SCE_Sha1HmacGenerateUpdate(sce_hmac_sha_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t HW_SCE_Sha1HmacGenerateFinal(sce_hmac_sha_handle_t * handle, uint8_t * mac); +fsp_err_t HW_SCE_Sha256HmacGenerateInit(sce_hmac_sha_handle_t * handle, sce_hmac_sha_key_index_t * key_index); +fsp_err_t HW_SCE_Sha256HmacGenerateUpdate(sce_hmac_sha_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t HW_SCE_Sha256HmacGenerateFinal(sce_hmac_sha_handle_t * handle, uint8_t * mac); +fsp_err_t HW_SCE_Sha1HmacVerifyInit(sce_hmac_sha_handle_t * handle, sce_hmac_sha_key_index_t * key_index); +fsp_err_t HW_SCE_Sha1HmacVerifyUpdate(sce_hmac_sha_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t HW_SCE_Sha1HmacVerifyFinal(sce_hmac_sha_handle_t * handle, uint8_t * mac, uint32_t mac_length); +fsp_err_t HW_SCE_Sha256HmacVerifyInit(sce_hmac_sha_handle_t * handle, sce_hmac_sha_key_index_t * key_index); +fsp_err_t HW_SCE_Sha256HmacVerifyUpdate(sce_hmac_sha_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t HW_SCE_Sha256HmacVerifyFinal(sce_hmac_sha_handle_t * handle, uint8_t * mac, uint32_t mac_length); + +fsp_err_t HW_SCE_RsassaPkcs1024SignatureGenerate(sce_rsa_byte_data_t * message_hash, + sce_rsa_byte_data_t * signature, + sce_rsa1024_private_key_index_t * key_index, + uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs1024SignatureVerification(sce_rsa_byte_data_t * signature, + sce_rsa_byte_data_t * message_hash, + sce_rsa1024_public_key_index_t * key_index, + uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs2048SignatureGenerate(sce_rsa_byte_data_t * message_hash, + sce_rsa_byte_data_t * signature, + sce_rsa2048_private_key_index_t * key_index, + uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs2048SignatureVerification(sce_rsa_byte_data_t * signature, + sce_rsa_byte_data_t * message_hash, + sce_rsa2048_public_key_index_t * key_index, + uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs3072SignatureGenerate(sce_rsa_byte_data_t * message_hash, + sce_rsa_byte_data_t * signature, + sce_rsa3072_private_key_index_t * key_index, + uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs3072SignatureVerification(sce_rsa_byte_data_t * signature, + sce_rsa_byte_data_t * message_hash, + sce_rsa3072_public_key_index_t * key_index, + uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs4096SignatureGenerate(sce_rsa_byte_data_t * message_hash, + sce_rsa_byte_data_t * signature, + sce_rsa4096_private_key_index_t * key_index, + uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs4096SignatureVerification(sce_rsa_byte_data_t * signature, + sce_rsa_byte_data_t * message_hash, + sce_rsa4096_public_key_index_t * key_index, + uint8_t hash_type); + +fsp_err_t HW_SCE_RsaesPkcs1024Encrypt(sce_rsa_byte_data_t * plain, + sce_rsa_byte_data_t * cipher, + sce_rsa1024_public_key_index_t * key_index); +fsp_err_t HW_SCE_RsaesPkcs1024Decrypt(sce_rsa_byte_data_t * cipher, + sce_rsa_byte_data_t * plain, + sce_rsa1024_private_key_index_t * key_index); +fsp_err_t HW_SCE_RsaesPkcs2048Encrypt(sce_rsa_byte_data_t * plain, + sce_rsa_byte_data_t * cipher, + sce_rsa2048_public_key_index_t * key_index); +fsp_err_t HW_SCE_RsaesPkcs2048Decrypt(sce_rsa_byte_data_t * cipher, + sce_rsa_byte_data_t * plain, + sce_rsa2048_private_key_index_t * key_index); +fsp_err_t HW_SCE_RsaesPkcs3072Encrypt(sce_rsa_byte_data_t * plain, + sce_rsa_byte_data_t * cipher, + sce_rsa3072_public_key_index_t * key_index); +fsp_err_t HW_SCE_RsaesPkcs3072Decrypt(sce_rsa_byte_data_t * cipher, + sce_rsa_byte_data_t * plain, + sce_rsa3072_private_key_index_t * key_index); +fsp_err_t HW_SCE_RsaesPkcs4096Encrypt(sce_rsa_byte_data_t * plain, + sce_rsa_byte_data_t * cipher, + sce_rsa4096_public_key_index_t * key_index); +fsp_err_t HW_SCE_RsaesPkcs4096Decrypt(sce_rsa_byte_data_t * cipher, + sce_rsa_byte_data_t * plain, + sce_rsa4096_private_key_index_t * key_index); + +fsp_err_t HW_SCE_TlsRootCertificateVerification(uint32_t public_key_type, + uint8_t * certificate, + uint32_t certificate_length, + uint32_t public_key_n_start_position, + uint32_t public_key_n_end_position, + uint32_t public_key_e_start_position, + uint32_t public_key_e_end_position, + uint8_t * signature, + uint32_t * encrypted_root_public_key); +fsp_err_t HW_SCE_TlsCertificateVerification(uint32_t public_key_type, + uint32_t * encrypted_input_public_key, + uint8_t * certificate, + uint32_t certificate_length, + uint8_t * signature, + uint32_t public_key_n_start_position, + uint32_t public_key_n_end_position, + uint32_t public_key_e_start_position, + uint32_t public_key_e_end_position, + uint32_t * encrypted_output_public_key); +fsp_err_t HW_SCE_TlsGeneratePreMasterSecret(uint32_t * sce_pre_master_secret); +fsp_err_t HW_SCE_TlsGenerateMasterSecret(uint32_t select_cipher_suite, + uint32_t * sce_pre_master_secret, + uint8_t * client_random, + uint8_t * server_random, + uint32_t * sce_master_secret); +fsp_err_t HW_SCE_TlsEncryptPreMasterSecretWithRsa2048PublicKey(uint32_t * encrypted_public_key, + uint32_t * sce_pre_master_secret, + uint8_t * encrypted_pre_master_secret); +fsp_err_t HW_SCE_TlsGenerateSessionKey(uint32_t select_cipher_suite, + uint32_t * sce_master_secret, + uint8_t * client_random, + uint8_t * server_random, + uint8_t * nonce_explicit, + sce_hmac_sha_key_index_t * client_mac_key_index, + sce_hmac_sha_key_index_t * server_mac_key_index, + sce_aes_key_index_t * client_crypto_key_index, + sce_aes_key_index_t * server_crypto_key_index, + uint8_t * client_iv, + uint8_t * server_iv); +fsp_err_t HW_SCE_TlsGenerateVerifyData(uint32_t select_verify_data, + uint32_t * sce_master_secret, + uint8_t * hand_shake_hash, + uint8_t * verify_data); +fsp_err_t HW_SCE_TlsGeneratePreMasterSecretWithEccP256Key(uint32_t * encrypted_public_key, + sce_tls_p256_ecc_key_index_t * tls_p256_ecc_key_index, + uint32_t * sce_pre_master_secret); +fsp_err_t HW_SCE_TlsServersEphemeralEcdhPublicKeyRetrieves(uint32_t public_key_type, + uint8_t * client_random, + uint8_t * server_random, + uint8_t * server_ephemeral_ecdh_public_key, + uint8_t * server_key_exchange_signature, + uint32_t * encrypted_public_key, + uint32_t * encrypted_ephemeral_ecdh_public_key); + +fsp_err_t HW_SCE_EcdsaP192SignatureGenerate(sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_EcdsaP224SignatureGenerate(uint32_t * indata_curvetype, + sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_EcdsaP256SignatureGenerate(uint32_t * indata_curvetype, + sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_EcdsaP384SignatureGenerate(uint32_t * indata_curvetype, + sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_EcdsaP192SignatureVerification(sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_EcdsaP224SignatureVerification(uint32_t * indata_curvetype, + sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_EcdsaP256SignatureVerification(uint32_t * indata_curvetype, + sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_EcdsaP384SignatureVerification(uint32_t * indata_curvetype, + sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_key_index_t * key_index); + +fsp_err_t HW_SCE_RSA_IF_HASH(uint8_t * p_mes, uint8_t * p_hash, uint32_t mes_len, uint8_t hash_type); + +fsp_err_t HW_SCE_EcdhInit(sce_ecdh_handle_t * handle, uint32_t key_type, uint32_t use_key_id); +fsp_err_t HW_SCE_EcdhReadPublicKey(sce_ecdh_handle_t * handle, + sce_ecc_public_key_index_t * public_key_index, + uint8_t * public_key_data, + sce_ecdsa_byte_data_t * signature, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_EcdhMakePublicKey(sce_ecdh_handle_t * handle, + sce_ecc_public_key_index_t * public_key_index, + sce_ecc_private_key_index_t * private_key_index, + uint8_t * public_key, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_EcdhCalculateSharedSecretIndex(sce_ecdh_handle_t * handle, + sce_ecc_public_key_index_t * public_key_index, + sce_ecc_private_key_index_t * private_key_index, + sce_ecdh_key_index_t * shared_secret_index); +fsp_err_t HW_SCE_EcdhKeyDerivation(sce_ecdh_handle_t * handle, + sce_ecdh_key_index_t * shared_secret_index, + uint32_t algorithm_id, + uint8_t * other_info, + uint32_t other_info_length, + sce_aes_key_index_t * key_index); + +fsp_err_t HW_SCE_Aes128KeyWrap(sce_aes_key_index_t * wrap_key_index, + uint32_t target_key_type, + sce_aes_key_index_t * target_key_index, + uint32_t * wrapped_key); +fsp_err_t HW_SCE_Aes256KeyWrap(sce_aes_key_index_t * wrap_key_index, + uint32_t target_key_type, + sce_aes_key_index_t * target_key_index, + uint32_t * wrapped_key); +fsp_err_t HW_SCE_Aes128KeyUnwrap(sce_aes_key_index_t * wrap_key_index, + uint32_t target_key_type, + uint32_t * wrapped_key, + sce_aes_key_index_t * target_key_index); +fsp_err_t HW_SCE_Aes256KeyUnwrap(sce_aes_key_index_t * wrap_key_index, + uint32_t target_key_type, + uint32_t * wrapped_key, + sce_aes_key_index_t * target_key_index); + +#endif /* R_SCE_IF_HEADER_FILE */ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/adaptors/r_sce_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/adaptors/r_sce_adapt.c index 5cb4f682b..902c5f664 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/adaptors/r_sce_adapt.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/adaptors/r_sce_adapt.c @@ -180,6 +180,26 @@ uint32_t change_endian_long (uint32_t a) return __REV(a); } +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_Key); + return HW_SCE_Aes128EncryptDecryptInitSub(InData_KeyMode, InData_Cmd, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_Key); + return HW_SCE_Aes256EncryptDecryptInitSub(InData_KeyMode, InData_Cmd, InData_KeyIndex, InData_IV); +} + fsp_err_t HW_SCE_Aes192EncryptDecryptInitSub (const uint32_t * InData_Cmd, const uint32_t * InData_KeyIndex, const uint32_t * InData_IV) @@ -553,4 +573,62 @@ fsp_err_t HW_SCE_Aes128GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, FSP_PARAMETER_NOT_USED(InData_SeqNum); return (HW_SCE_Aes128GcmDecryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV)); -} \ No newline at end of file +} + +fsp_err_t HW_SCE_Aes192GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes192GcmEncryptInitSub(InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes192GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes192GcmDecryptInitSub(InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes256GcmEncryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes256GcmDecryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/private/inc/hw_sce_ra_private.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/private/inc/hw_sce_ra_private.h index 98fed8982..7a1c827a7 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/private/inc/hw_sce_ra_private.h +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/private/inc/hw_sce_ra_private.h @@ -199,7 +199,14 @@ fsp_err_t HW_SCE_Aes128GcmEncryptInitSubGeneral (uint32_t *InData_KeyType, uint3 uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); fsp_err_t HW_SCE_Aes128GcmDecryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); - +fsp_err_t HW_SCE_Aes192GcmDecryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes192GcmEncryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes256GcmDecryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes256GcmEncryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); fsp_err_t HW_SCE_Aes192EncryptDecryptInitSub(const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_IV); void HW_SCE_Aes192EncryptDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes192EncryptDecryptFinalSub(void); @@ -239,6 +246,12 @@ fsp_err_t HW_SCE_GenerateFirmwareMacSub(uint32_t *InData_KeyIndex, uint32_t *InD fsp_err_t HW_SCE_VerifyFirmwareMacSub(uint32_t *InData_Program, uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub(const uint32_t *InData_KeyType, const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]); +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_Key[], const uint32_t InData_IV[]); void HW_SCE_Aes128EncryptDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub(void); fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub(const uint32_t *InData_KeyType, const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_IV); diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/adaptors/r_sce_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/adaptors/r_sce_adapt.c index 0a7a9b307..e66525dd8 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/adaptors/r_sce_adapt.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/adaptors/r_sce_adapt.c @@ -193,6 +193,26 @@ uint32_t change_endian_long (uint32_t a) return __REV(a); } +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_Key); + return HW_SCE_Aes128EncryptDecryptInitSub(InData_KeyMode, InData_Cmd, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_Key); + return HW_SCE_Aes256EncryptDecryptInitSub(InData_KeyMode, InData_Cmd, InData_KeyIndex, InData_IV); +} + fsp_err_t HW_SCE_Aes192EncryptDecryptInitSub (const uint32_t * InData_Cmd, const uint32_t * InData_KeyIndex, const uint32_t * InData_IV) @@ -566,4 +586,62 @@ fsp_err_t HW_SCE_Aes128GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, FSP_PARAMETER_NOT_USED(InData_SeqNum); return (HW_SCE_Aes128GcmDecryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV)); -} \ No newline at end of file +} + +fsp_err_t HW_SCE_Aes192GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes192GcmEncryptInitSub(InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes192GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes192GcmDecryptInitSub(InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes256GcmEncryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes256GcmDecryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/private/inc/hw_sce_ra_private.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/private/inc/hw_sce_ra_private.h index baeff7a7d..b2decf261 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/private/inc/hw_sce_ra_private.h +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/private/inc/hw_sce_ra_private.h @@ -450,6 +450,12 @@ fsp_err_t HW_SCE_GenerateFirmwareMacSub(uint32_t *InData_KeyIndex, uint32_t *InD fsp_err_t HW_SCE_VerifyFirmwareMacSub(uint32_t *InData_Program, uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub(const uint32_t *InData_KeyType, const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]); +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_Key[], const uint32_t InData_IV[]); void HW_SCE_Aes128EncryptDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub(void); fsp_err_t HW_SCE_Aes192EncryptDecryptInitSub(const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_IV); @@ -575,6 +581,14 @@ fsp_err_t HW_SCE_Aes128GcmEncryptInitSubGeneral (uint32_t *InData_KeyType, uint3 uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); fsp_err_t HW_SCE_Aes128GcmDecryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes192GcmDecryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes192GcmEncryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes256GcmDecryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes256GcmEncryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); fsp_err_t HW_SCE_Aes128CmacInitSub(uint32_t *InData_KeyIndex); void HW_SCE_Aes128CmacUpdateSub(uint32_t *InData_Text, uint32_t MAX_CNT); diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/adaptors/r_sce_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/adaptors/r_sce_adapt.c index efd859891..99e89e5f3 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/adaptors/r_sce_adapt.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/adaptors/r_sce_adapt.c @@ -289,6 +289,26 @@ uint32_t change_endian_long (uint32_t a) return __REV(a); } +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_Key); + return HW_SCE_Aes128EncryptDecryptInitSub(InData_KeyMode, InData_Cmd, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_Key); + return HW_SCE_Aes256EncryptDecryptInitSub(InData_KeyMode, InData_Cmd, InData_KeyIndex, InData_IV); +} + fsp_err_t HW_SCE_Aes128CmacInit(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[]) { return HW_SCE_Aes128CmacInitSub((uint32_t *)InData_KeyType, (uint32_t *)InData_KeyIndex); @@ -516,6 +536,64 @@ fsp_err_t HW_SCE_Aes128GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, return (HW_SCE_Aes128GcmDecryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV)); } +fsp_err_t HW_SCE_Aes192GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes192GcmEncryptInitSub(InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes192GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes192GcmDecryptInitSub(InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes256GcmEncryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes256GcmDecryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} + fsp_err_t HW_SCE_Ecc256ScalarMultiplicationSubAdaptor(const uint32_t InData_CurveType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], @@ -627,4 +705,4 @@ fsp_err_t HW_SCE_GenerateEccP384RandomKeyIndexSubAdaptor(const uint32_t *InData_ FSP_PARAMETER_NOT_USED (InData_DomainParam); return (HW_SCE_GenerateEccP384RandomKeyIndexSub(InData_CurveType, InData_KeyType, OutData_PubKeyIndex, OutData_PubKey, OutData_PrivKeyIndex, OutData_PrivKey)); -} \ No newline at end of file +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/private/inc/hw_sce_ra_private.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/private/inc/hw_sce_ra_private.h index 1129cfd46..3c4aaf980 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/private/inc/hw_sce_ra_private.h +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/private/inc/hw_sce_ra_private.h @@ -514,6 +514,12 @@ fsp_err_t HW_SCE_GenerateFirmwareMacSub(uint32_t *InData_KeyIndex, uint32_t *InD fsp_err_t HW_SCE_VerifyFirmwareMacSub(uint32_t *InData_Program, uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub(const uint32_t *InData_KeyType, const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]); +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_Key[], const uint32_t InData_IV[]); void HW_SCE_Aes128EncryptDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub(void); fsp_err_t HW_SCE_Aes192EncryptDecryptInitSub(const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_IV); @@ -640,6 +646,14 @@ fsp_err_t HW_SCE_Aes128GcmEncryptInitSubGeneral (uint32_t *InData_KeyType, uint3 uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); fsp_err_t HW_SCE_Aes128GcmDecryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes192GcmDecryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes192GcmEncryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes256GcmDecryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes256GcmEncryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); fsp_err_t HW_SCE_Aes128CmacInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex); void HW_SCE_Aes128CmacUpdateSub(uint32_t *InData_Text, uint32_t MAX_CNT); diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_adapt.c index e27a92138..89f96042e 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_adapt.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_adapt.c @@ -212,6 +212,25 @@ uint32_t change_endian_long (uint32_t a) { return __REV(a); } +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_Key); + return HW_SCE_Aes128EncryptDecryptInitSub(InData_KeyMode, InData_Cmd, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_Key); + return HW_SCE_Aes256EncryptDecryptInitSub(InData_KeyMode, InData_Cmd, InData_KeyIndex, InData_IV); +} fsp_err_t HW_SCE_Aes128CmacInit(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[]) { @@ -437,6 +456,64 @@ fsp_err_t HW_SCE_Aes128GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, return (HW_SCE_Aes128GcmDecryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV)); } +fsp_err_t HW_SCE_Aes192GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes192GcmEncryptInitSub(InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes192GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes192GcmDecryptInitSub(InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes256GcmEncryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes256GcmDecryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} + fsp_err_t HW_SCE_Ecc256ScalarMultiplicationSubAdaptor(const uint32_t InData_CurveType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], @@ -542,4 +619,4 @@ fsp_err_t HW_SCE_GenerateEccP384RandomKeyIndexSubAdaptor(const uint32_t *InData_ FSP_PARAMETER_NOT_USED (InData_DomainParam); return (HW_SCE_GenerateEccP384RandomKeyIndexSub(InData_CurveType, InData_KeyType, OutData_PubKeyIndex, OutData_PubKey, OutData_PrivKeyIndex, OutData_PrivKey)); -} \ No newline at end of file +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/hw_sce_ra_private.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/hw_sce_ra_private.h index c26af607c..9ec873791 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/hw_sce_ra_private.h +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/hw_sce_ra_private.h @@ -502,6 +502,12 @@ fsp_err_t HW_SCE_GenerateFirmwareMacSub(uint32_t *InData_KeyIndex, uint32_t *InD fsp_err_t HW_SCE_VerifyFirmwareMacSub(uint32_t *InData_Program, uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub(const uint32_t *InData_KeyType, const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]); +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_Key[], const uint32_t InData_IV[]); void HW_SCE_Aes128EncryptDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub(void); fsp_err_t HW_SCE_Aes192EncryptDecryptInitSub(const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_IV); @@ -629,7 +635,14 @@ fsp_err_t HW_SCE_Aes128GcmEncryptInitSubGeneral (uint32_t *InData_KeyType, uint3 uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); fsp_err_t HW_SCE_Aes128GcmDecryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); - +fsp_err_t HW_SCE_Aes192GcmDecryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes192GcmEncryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes256GcmDecryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes256GcmEncryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); fsp_err_t HW_SCE_Aes128CmacInitSub(uint32_t *InData_KeyIndex); void HW_SCE_Aes128CmacUpdateSub(uint32_t *InData_Text, uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes128CmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_Text, uint32_t *InData_DataT, diff --git a/ra/fsp/src/r_sce/hw_sce_aes_private.h b/ra/fsp/src/r_sce/hw_sce_aes_private.h index 33a606902..7723ca819 100644 --- a/ra/fsp/src/r_sce/hw_sce_aes_private.h +++ b/ra/fsp/src/r_sce/hw_sce_aes_private.h @@ -358,11 +358,6 @@ fsp_err_t HW_SCE_Aes192CtrEncryptDecryptInitSubGeneral(uint32_t * InData_KeyInde fsp_err_t HW_SCE_Aes256CtrEncryptDecryptInitSubGeneral(uint32_t * InData_KeyIndex, uint32_t * InData_IV); -fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub(const uint32_t * InData_KeyType, - const uint32_t * InData_Cmd, - const uint32_t * InData_KeyIndex, - const uint32_t * InData_IV); - void HW_SCE_Aes128EncryptDecryptUpdateSub(const uint32_t * InData_Text, uint32_t * OutData_Text, const uint32_t MAX_CNT); diff --git a/ra/fsp/src/r_sce/hw_sce_ecc_private.h b/ra/fsp/src/r_sce/hw_sce_ecc_private.h index 820072505..694a4fce4 100644 --- a/ra/fsp/src/r_sce/hw_sce_ecc_private.h +++ b/ra/fsp/src/r_sce/hw_sce_ecc_private.h @@ -47,14 +47,15 @@ #define ECC_521_PRIVATE_KEY_LENGTH_WORDS (20U) /* ECC ED-25519 */ -#define ECC_25519_PRIVATE_KEY_LENGTH_BITS (256U) +#define ECC_25519_PRIVATE_KEY_LENGTH_BITS (255U) #define ECC_25519_PRIVATE_KEY_LENGTH_WORDS (8U) /* SCE based wrapped keys are at most 20/32 bytes larger than corresponding plain private keys */ #define HW_SCE_ECC_WRAPPED_KEY_ADJUST(x) ((x) + ((HW_SCE_PRIVATE_KEY_WRAPPING_WORD_SIZE) * 4)) /* Function pointer declarations */ -#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 +#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 || \ + BSP_FEATURE_CRYPTO_HAS_RSIP_E11A #define ECC_PUBLIC_KEY_SIZE_BYTES(curve_size) (curve_size * 2 + 20U) typedef fsp_err_t (* hw_sce_ecc_scalarmultiplication_t)(const uint32_t * InData_CurveType, const uint32_t * InData_Cmd, const uint32_t * InData_K, const uint32_t * InData_P, @@ -166,12 +167,6 @@ fsp_err_t HW_SCE_ECC_384HrkScalarMultiplication(const uint32_t * InData_DomainPa const uint32_t * InData_KeyIndex, const uint32_t * InData_P, uint32_t * OutData_R); -fsp_err_t HW_SCE_ECC_384WrappedScalarMultiplication(const uint32_t * InData_CurveType, - const uint32_t * InData_Cmd, - const uint32_t * InData_KeyIndex, - const uint32_t * InData_P, - const uint32_t * Domain_Param, - uint32_t * OutData_R); #if BSP_FEATURE_CRYPTO_HAS_RSIP7 fsp_err_t HW_SCE_ECC_521GenerateSign(const uint32_t * InData_CurveType, @@ -218,6 +213,13 @@ fsp_err_t HW_SCE_ECC_255HrkGenerateSign(const uint32_t * InData_DomainParam, #endif +fsp_err_t HW_SCE_ECC_384WrappedScalarMultiplication(const uint32_t * InData_CurveType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_P, + const uint32_t * Domain_Param, + uint32_t * OutData_R); + fsp_err_t HW_SCE_ECC_ED25519WrappedScalarMultiplication(const uint32_t * InData_CurveType, const uint32_t * InData_Cmd, const uint32_t * InData_KeyIndex, diff --git a/ra/fsp/src/r_sce/hw_sce_hash_private.h b/ra/fsp/src/r_sce/hw_sce_hash_private.h index 177ae7675..11597b87f 100644 --- a/ra/fsp/src/r_sce/hw_sce_hash_private.h +++ b/ra/fsp/src/r_sce/hw_sce_hash_private.h @@ -37,6 +37,14 @@ extern fsp_err_t HW_SCE_Sha224256GenerateMessageDigestSub(const uint32_t * InDat const uint32_t * InData_PaddedMsg, const uint32_t MAX_CNT, uint32_t * OutData_MsgDigest); + +#if BSP_FEATURE_CRYPTO_HAS_RSIP_E11A +extern fsp_err_t HW_SCE_ShaGenerateMessageDigestSub(const uint32_t InData_InitVal[], + const uint32_t InData_PaddedMsg[], + uint32_t OutData_MsgDigest[], + const uint32_t MAX_CNT); + +#else extern fsp_err_t HW_SCE_ShaGenerateMessageDigestSub(const uint32_t InData_HashType[], const uint32_t InData_Cmd[], const uint32_t InData_Msg[], @@ -46,4 +54,5 @@ extern fsp_err_t HW_SCE_ShaGenerateMessageDigestSub(const uint32_t InData_HashTy uint32_t OutData_State[], const uint32_t MAX_CNT); +#endif #endif /* HW_SCE_HASH_PRIVATE_H */ diff --git a/ra/fsp/src/r_sce/ra2/adaptors/hw_sce_ra_private.h b/ra/fsp/src/r_sce/ra2/adaptors/hw_sce_ra_private.h index b1afc60b1..a5247ec16 100644 --- a/ra/fsp/src/r_sce/ra2/adaptors/hw_sce_ra_private.h +++ b/ra/fsp/src/r_sce/ra2/adaptors/hw_sce_ra_private.h @@ -66,6 +66,18 @@ void HW_SCE_Aes128EncryptDecryptUpdateSub(const uint32_t * InData_Text, const uint32_t MAX_CNT); fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub(void); +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSubAdaptor(const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]); + +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSubAdaptor(const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]); + fsp_err_t HW_SCE_Aes192EncryptDecryptInitSub(const uint32_t * InData_Cmd, const uint32_t * InData_KeyIndex, const uint32_t * InData_IV); diff --git a/ra/fsp/src/r_sce/ra2/adaptors/r_sce_AES_adapt.c b/ra/fsp/src/r_sce/ra2/adaptors/r_sce_AES_adapt.c index 6a720398e..c291a2076 100644 --- a/ra/fsp/src/r_sce/ra2/adaptors/r_sce_AES_adapt.c +++ b/ra/fsp/src/r_sce/ra2/adaptors/r_sce_AES_adapt.c @@ -248,3 +248,25 @@ fsp_err_t HW_SCE_Aes256EncryptDecryptFinalSub (void) return FSP_SUCCESS; } + +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_Key); + + return HW_SCE_Aes128EncryptDecryptInitSub(InData_KeyMode, InData_Cmd, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_Key); + + return HW_SCE_Aes256EncryptDecryptInitSub(InData_KeyMode, InData_Cmd, InData_KeyIndex, InData_IV); +} diff --git a/ra/fsp/src/r_sci_b_spi/r_sci_b_spi.c b/ra/fsp/src/r_sci_b_spi/r_sci_b_spi.c index 245f97032..e40b9d0fe 100644 --- a/ra/fsp/src/r_sci_b_spi/r_sci_b_spi.c +++ b/ra/fsp/src/r_sci_b_spi/r_sci_b_spi.c @@ -565,6 +565,9 @@ static void r_sci_b_spi_hw_config (sci_b_spi_instance_ctrl_t * const p_ctrl) /* Set FCR. Reset FIFO/data registers. */ p_ctrl->p_reg->FCR = R_SCI_B0_FCR_TFRST_Msk | R_SCI_B0_FCR_RFRST_Msk; + /* Write all settings except MOD[2:0] to CCR3 (See Table 26.36 in RA6T2 manual R01UH0951EJ0130). */ + p_ctrl->p_reg->CCR3 = ccr3 & ~(R_SCI_B0_CCR3_MOD_Msk); + /* Write settings to registers. */ p_ctrl->p_reg->CCR3 = ccr3; p_ctrl->p_reg->CCR2 = ccr2; diff --git a/ra/fsp/src/r_sci_uart/r_sci_uart.c b/ra/fsp/src/r_sci_uart/r_sci_uart.c index 59b46efb4..e9f6962eb 100644 --- a/ra/fsp/src/r_sci_uart/r_sci_uart.c +++ b/ra/fsp/src/r_sci_uart/r_sci_uart.c @@ -166,6 +166,14 @@ static fsp_err_t r_sci_read_write_param_check(sci_uart_instance_ctrl_t const * c #endif +#if BSP_PERIPHERAL_IRDA_PRESENT + #if SCI_UART_CFG_IRDA_SUPPORT +static void r_sci_irda_enable(sci_uart_extended_cfg_t const * const p_extended); +static void r_sci_irda_disable(sci_uart_extended_cfg_t const * const p_extended); + + #endif +#endif + static void r_sci_uart_config_set(sci_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); #if SCI_UART_CFG_DTC_SUPPORTED @@ -290,8 +298,10 @@ const uart_api_t g_uart_on_sci = * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The requested channel does not exist on this MCU. * @retval FSP_ERR_INVALID_ARGUMENT Flow control is enabled but flow control pin is not defined or selected channel * does not support "Hardware CTS and Hardware RTS" flow control. + * (or) restricted channel is selected. * @retval FSP_ERR_ALREADY_OPEN Control block has already been opened or channel is being used by another * instance. Call close() then open() to reconfigure. + * @retval FSP_ERR_INVALID_CHANNEL IrDA is requested for a channel that does not support IrDA. * * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible * return codes. This function calls: @@ -336,12 +346,26 @@ fsp_err_t R_SCI_UART_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * co } #endif + #if BSP_PERIPHERAL_IRDA_PRESENT + #if SCI_UART_CFG_IRDA_SUPPORT + if (((sci_uart_extended_cfg_t *) p_cfg->p_extend)->irda_setting.ircr_bits_b.ire) + { + FSP_ERROR_RETURN(BSP_PERIPHERAL_IRDA_CHANNEL_MASK & (1 << p_cfg->channel), FSP_ERR_INVALID_CHANNEL); + } + #endif + #endif + FSP_ASSERT(p_cfg->rxi_irq >= 0); FSP_ASSERT(p_cfg->txi_irq >= 0); FSP_ASSERT(p_cfg->tei_irq >= 0); FSP_ASSERT(p_cfg->eri_irq >= 0); #endif + /* Verify that the selected channel is not among the restricted channels when ABCSE is 1. Refer "Limitations" section of r_sci_uart module in FSP User Manual */ + FSP_ERROR_RETURN(!((BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS & (1 << p_cfg->channel)) && + ((sci_uart_extended_cfg_t *) p_cfg->p_extend)->p_baud_setting->semr_baudrate_bits_b.abcse), + FSP_ERR_INVALID_ARGUMENT); + p_ctrl->p_reg = ((R_SCI0_Type *) (R_SCI0_BASE + (SCI_REG_SIZE * p_cfg->channel))); p_ctrl->fifo_depth = 0U; @@ -380,6 +404,14 @@ fsp_err_t R_SCI_UART_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * co /* Negate driver enable if RS-485 mode is enabled. */ r_sci_negate_de_pin(p_ctrl); +#if BSP_PERIPHERAL_IRDA_PRESENT + #if SCI_UART_CFG_IRDA_SUPPORT + + /* Set the IrDA configuration settings provided in ::sci_uart_extended_cfg_t. */ + r_sci_irda_enable(p_cfg->p_extend); + #endif +#endif + /* Enable the SCI channel */ R_BSP_MODULE_START(FSP_IP_SCI, p_cfg->channel); @@ -493,6 +525,14 @@ fsp_err_t R_SCI_UART_Close (uart_ctrl_t * const p_api_ctrl) /* Negate driver enable if RS-485 mode is enabled. */ r_sci_negate_de_pin(p_ctrl); +#if BSP_PERIPHERAL_IRDA_PRESENT + #if SCI_UART_CFG_IRDA_SUPPORT + + /* To disable IrDA. */ + r_sci_irda_disable(p_ctrl->p_cfg->p_extend); + #endif +#endif + return FSP_SUCCESS; } @@ -735,7 +775,7 @@ fsp_err_t R_SCI_UART_CallbackSet (uart_ctrl_t * const p_api_ctrl, * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL or the UART is not configured to use the * internal clock. * @retval FSP_ERR_NOT_OPEN The control block has not been opened. - * @retval FSP_ERR_UNSUPPORTED A restricted channel is selected. + * @retval FSP_ERR_INVALID_ARGUMENT Restricted channel is selected. **********************************************************************************************************************/ fsp_err_t R_SCI_UART_BaudSet (uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting) { @@ -744,12 +784,16 @@ fsp_err_t R_SCI_UART_BaudSet (uart_ctrl_t * const p_api_ctrl, void const * const #if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) FSP_ASSERT(p_ctrl); FSP_ERROR_RETURN(SCI_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); - /* Verify that the selected channel is not among the restricted channels when ABCSE is 1. Refer "Limitations" section of r_sci_uart module in FSP User Manual */ - FSP_ERROR_RETURN(!((BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS & (1 << p_ctrl->p_cfg->channel)) && (((baud_setting_t*)p_baud_setting)->semr_baudrate_bits_b.abcse)),FSP_ERR_UNSUPPORTED); + /* Verify that the On-Chip baud rate generator is currently selected. */ FSP_ASSERT((p_ctrl->p_reg->SCR_b.CKE & 0x2) == 0U); #endif + /* Verify that the selected channel is not among the restricted channels when ABCSE is 1. Refer "Limitations" section of r_sci_uart module in FSP User Manual */ + FSP_ERROR_RETURN(!((BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS & (1 << p_ctrl->p_cfg->channel)) && + (((baud_setting_t *) p_baud_setting)->semr_baudrate_bits_b.abcse)), + FSP_ERR_INVALID_ARGUMENT); + /* Save SCR configurations except transmit interrupts. Resuming transmission after reconfiguring baud settings is * not supported. */ uint8_t preserved_scr = p_ctrl->p_reg->SCR & (uint8_t) ~(SCI_SCR_TIE_MASK | SCI_SCR_TEIE_MASK); @@ -1291,6 +1335,46 @@ static fsp_err_t r_sci_uart_transfer_open (sci_uart_instance_ctrl_t * const p_ct #endif +#if BSP_PERIPHERAL_IRDA_PRESENT + #if SCI_UART_CFG_IRDA_SUPPORT + +/*******************************************************************************************************************//** + * Init IrDA module based on user configurations. + * + * @param[in] p_extended Pointer to extended settings + **********************************************************************************************************************/ +static void r_sci_irda_enable (sci_uart_extended_cfg_t const * const p_extended) +{ + /* The ire bit should only be set for the channel that is IrDA capable */ + if (p_extended->irda_setting.ircr_bits_b.ire) + { + /* Enable the IrDA interface */ + R_BSP_MODULE_START(FSP_IP_IRDA, 0); + + R_IRDA->IRCR = p_extended->irda_setting.ircr_bits; + } +} + +/*******************************************************************************************************************//** + * Stop IrDA module. + * + * @param[in] p_extended Pointer to extended settings + **********************************************************************************************************************/ +static void r_sci_irda_disable (sci_uart_extended_cfg_t const * const p_extended) +{ + /* Only disable IrDA interface on the channel it is enabled. */ + if (p_extended->irda_setting.ircr_bits_b.ire) + { + /* Don't need to clear IRCR as interface is to be disabled. */ + + /* Disable the IrDA interface */ + R_BSP_MODULE_STOP(FSP_IP_IRDA, 0); + } +} + + #endif +#endif + /*******************************************************************************************************************//** * Configures UART related registers based on user configurations. * diff --git a/ra/fsp/src/r_tml/r_tml.c b/ra/fsp/src/r_tml/r_tml.c index d13b9466c..e55b1b42a 100644 --- a/ra/fsp/src/r_tml/r_tml.c +++ b/ra/fsp/src/r_tml/r_tml.c @@ -21,51 +21,58 @@ #define TML_PRV_ITLCMP0_UPPER_16_BIT_POS (16) #define TML_PRV_ITLCMP0_UPPER_16_BIT_CLEARED (0x0000FFFFU) -/* ITLCTL0 bit field definitions. */ -#define TML_PRV_ITLCTL0_EN_DISABLED (0U) -#define TML_PRV_ITLCTL0_EN_ENABLED (1U) - -/* ITLCC0 bit field definitions. */ -#define TML_PRV_ITLCC0_CAPEN_DISABLED (0U) -#define TML_PRV_ITLCC0_CAPEN_ENABLED (1U) - #define CHANNEL0_MASK (1U << 0) #define CHANNEL2_MASK (1U << 2) #define VALID_16_BIT_COUNTER_CHANNEL_MASK (CHANNEL0_MASK | CHANNEL2_MASK) #define VALID_16_BIT_CAPTURE_CHANNEL_MASK (CHANNEL0_MASK) #define VALID_32_BIT_COUNTER_CHANNEL_MASK (CHANNEL0_MASK) -/* ITLFDIV address. */ -#define R_TML_ITLFDIV_ADDRESS(chan) (&(R_TML->ITLFDIV00) + chan / 2) - -/* ITLFDIV mask. */ -#define R_TML_ITLFDIV_POS(chan) ((chan & 0x01) * R_TML_ITLFDIV00_FDIV1_Pos) -#define R_TML_ITLFDIV_MASK(chan) (uint8_t) (R_TML_ITLFDIV00_FDIV0_Msk << R_TML_ITLFDIV_POS(chan)) - /* Counter clock selection (ISEL) */ #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_TML_FITL0_SOURCE - #define R_TML_ITLCSEL0_ISEL_VALUE (TML_CLOCK_HOCO) + #define TML_PRV_ITLCSEL0_ISEL_VALUE (TML_CLOCK_HOCO) #elif BSP_CLOCKS_SOURCE_CLOCK_MOCO == BSP_CFG_TML_FITL0_SOURCE - #define R_TML_ITLCSEL0_ISEL_VALUE (TML_CLOCK_MOCO) + #define TML_PRV_ITLCSEL0_ISEL_VALUE (TML_CLOCK_MOCO) #elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_TML_FITL0_SOURCE - #define R_TML_ITLCSEL0_ISEL_VALUE (TML_CLOCK_MOSC) + #define TML_PRV_ITLCSEL0_ISEL_VALUE (TML_CLOCK_MOSC) #elif BSP_CFG_FSXP_SOURCE == BSP_CFG_TML_FITL0_SOURCE - #define R_TML_ITLCSEL0_ISEL_VALUE (TML_CLOCK_LOCO_SOSC) + #define TML_PRV_ITLCSEL0_ISEL_VALUE (TML_CLOCK_LOCO_SOSC) #else - #define R_TML_ITLCSEL0_ISEL_VALUE (TML_CLOCK_ELC_EVENT) + #define TML_PRV_ITLCSEL0_ISEL_VALUE (TML_CLOCK_ELC_EVENT) #endif /* Capture clock selection (CSEL) */ #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_TML_FITL1_SOURCE - #define R_TML_ITLCSEL0_CSEL_VALUE (TML_CLOCK_HOCO) + #define TML_PRV_ITLCSEL0_CSEL_VALUE (TML_CLOCK_HOCO) #elif BSP_CLOCKS_SOURCE_CLOCK_MOCO == BSP_CFG_TML_FITL1_SOURCE - #define R_TML_ITLCSEL0_CSEL_VALUE (TML_CLOCK_MOCO) + #define TML_PRV_ITLCSEL0_CSEL_VALUE (TML_CLOCK_MOCO) #elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_TML_FITL1_SOURCE - #define R_TML_ITLCSEL0_CSEL_VALUE (TML_CLOCK_MOSC) + #define TML_PRV_ITLCSEL0_CSEL_VALUE (TML_CLOCK_MOSC) #elif BSP_CFG_FSXP_SOURCE == BSP_CFG_TML_FITL1_SOURCE - #define R_TML_ITLCSEL0_CSEL_VALUE (TML_CLOCK_LOCO_SOSC) + #define TML_PRV_ITLCSEL0_CSEL_VALUE (TML_CLOCK_LOCO_SOSC) +#else + #define TML_PRV_ITLCSEL0_CSEL_VALUE (TML_CLOCK_ELC_EVENT) +#endif + +#if TML_CFG_CRITICAL_SECTION_ENABLE + #define TML_PRV_CRITICAL_SECTION_ENTER() {FSP_CRITICAL_SECTION_DEFINE; FSP_CRITICAL_SECTION_ENTER + #define TML_PRV_CRITICAL_SECTION_EXIT() FSP_CRITICAL_SECTION_EXIT;} +#else + #define TML_PRV_CRITICAL_SECTION_ENTER() + #define TML_PRV_CRITICAL_SECTION_EXIT() +#endif + +#if TML_CFG_SINGLE_CHANNEL_ENABLE + #define TML_PRV_CHANNEL (0U) + #define TML_PRV_CHANNEL_MASK (0x1U) + #define TML_PRV_ITLFDIV_ADDRESS (&(R_TML->ITLFDIV00)) + #define TML_PRV_ITLFDIV_POS (R_TML_ITLFDIV00_FDIV0_Pos) + #define TML_PRV_ITLFDIV_MASK (uint8_t) (R_TML_ITLFDIV00_FDIV0_Msk) #else - #define R_TML_ITLCSEL0_CSEL_VALUE (TML_CLOCK_ELC_EVENT) + #define TML_PRV_CHANNEL (p_instance_ctrl->p_cfg->channel) + #define TML_PRV_CHANNEL_MASK (p_instance_ctrl->channel_mask) + #define TML_PRV_ITLFDIV_ADDRESS (&(R_TML->ITLFDIV00) + TML_PRV_CHANNEL / 2) + #define TML_PRV_ITLFDIV_POS ((TML_PRV_CHANNEL & 0x01) * R_TML_ITLFDIV00_FDIV1_Pos) + #define TML_PRV_ITLFDIV_MASK (uint8_t) (R_TML_ITLFDIV00_FDIV0_Msk << TML_PRV_ITLFDIV_POS) #endif /*********************************************************************************************************************** @@ -97,6 +104,11 @@ static fsp_err_t r_tml_open_param_checking(tml_instance_ctrl_t * const p_instanc #endif +#if TML_CFG_INTERRUPT_SUPPORT_ENABLE +static fsp_err_t r_tml_enable_helper(timer_ctrl_t * const p_ctrl, bool enable); + +#endif + /*********************************************************************************************************************** * ISR prototypes **********************************************************************************************************************/ @@ -108,17 +120,20 @@ void tml_itl_or_isr(void); /*********************************************************************************************************************** * Private global variables **********************************************************************************************************************/ -#if TML_CFG_INTERRUPT_SUPPORT_ENABLE +#if TML_CFG_INTERRUPT_SUPPORT_ENABLE && (!TML_CFG_SINGLE_CHANNEL_ENABLE) /** Stored context for isr handler. */ static tml_instance_ctrl_t * gp_tml_ctrls[BSP_FEATURE_TML_NUM_CHANNELS] = {NULL}; #endif -/** modeset is to track whether the mode has been set by an active channel... incremented when a channel is opened, - * decremented when a channel is closed... this is done because the mode ITLCTL0_b.MD register doesn't have an - * "inactive" selection... and we need to make sure the mode of a channel matches the modes of currently active +#if !TML_CFG_SINGLE_CHANNEL_ENABLE + +/** g_modeset is to track whether the mode has been set by an active channel. Incremented when a channel is opened, + * decremented when a channel is closed. This is done because the mode ITLCTL0_b.MD register doesn't have an + * "inactive" selection and we need to make sure the mode of a channel matches the modes of currently active * channels. We can only set the mode on the first channel open.*/ -static uint8_t modeset = 0; +static uint8_t g_modeset = 0; +#endif /*********************************************************************************************************************** * Global Variables @@ -191,13 +206,14 @@ fsp_err_t R_TML_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_c p_instance_ctrl->p_context = p_cfg->p_context; err = r_tml_hardware_initialize(p_instance_ctrl, p_cfg); +#if TML_CFG_PARAM_CHECKING_ENABLE FSP_ERROR_RETURN(FSP_SUCCESS == err, err); -#if TML_CFG_PARAM_CHECKING_ENABLE p_instance_ctrl->open = TML_OPEN; #endif -#if TML_CFG_INTERRUPT_SUPPORT_ENABLE - gp_tml_ctrls[p_cfg->channel] = p_instance_ctrl; + +#if TML_CFG_INTERRUPT_SUPPORT_ENABLE && (!TML_CFG_SINGLE_CHANNEL_ENABLE) + gp_tml_ctrls[TML_PRV_CHANNEL] = p_instance_ctrl; #endif return err; @@ -220,16 +236,20 @@ fsp_err_t R_TML_Stop (timer_ctrl_t * const p_ctrl) #if TML_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(NULL != p_instance_ctrl); FSP_ERROR_RETURN(TML_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); - FSP_ERROR_RETURN(p_instance_ctrl->channel_mask & BSP_FEATURE_TML_VALID_CHANNEL_MASK, - FSP_ERR_IP_CHANNEL_NOT_PRESENT); + FSP_ERROR_RETURN(TML_PRV_CHANNEL_MASK & BSP_FEATURE_TML_VALID_CHANNEL_MASK, FSP_ERR_IP_CHANNEL_NOT_PRESENT); #endif - uint8_t itlctl0 = R_TML->ITLCTL0; +#if TML_CFG_SINGLE_CHANNEL_ENABLE + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif - FSP_CRITICAL_SECTION_DEFINE; + /* Critical section required because ITLCTL0 register is shared with other instances. */ + TML_PRV_CRITICAL_SECTION_ENTER(); + + uint8_t itlctl0 = R_TML->ITLCTL0; /* Stop timer */ - itlctl0 &= (uint8_t) ~(BSP_FEATURE_TML_VALID_CHANNEL_MASK & p_instance_ctrl->channel_mask); + itlctl0 &= (uint8_t) ~(TML_PRV_CHANNEL_MASK); #if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE @@ -246,13 +266,10 @@ fsp_err_t R_TML_Stop (timer_ctrl_t * const p_ctrl) } #endif - /* Critical section required because ITLCTL0 register is shared with other instances. */ - FSP_CRITICAL_SECTION_ENTER; - /* Write to registers */ R_TML->ITLCTL0 = itlctl0; - FSP_CRITICAL_SECTION_EXIT; + TML_PRV_CRITICAL_SECTION_EXIT(); return FSP_SUCCESS; } @@ -274,21 +291,25 @@ fsp_err_t R_TML_Start (timer_ctrl_t * const p_ctrl) #if TML_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(NULL != p_instance_ctrl); FSP_ERROR_RETURN(TML_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); - FSP_ERROR_RETURN(p_instance_ctrl->channel_mask & BSP_FEATURE_TML_VALID_CHANNEL_MASK, - FSP_ERR_IP_CHANNEL_NOT_PRESENT); + FSP_ERROR_RETURN(TML_PRV_CHANNEL_MASK & BSP_FEATURE_TML_VALID_CHANNEL_MASK, FSP_ERR_IP_CHANNEL_NOT_PRESENT); #endif +#if TML_CFG_SINGLE_CHANNEL_ENABLE + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + /* Critical section required because ITLCTL0 register is shared with other instances. */ + TML_PRV_CRITICAL_SECTION_ENTER(); + uint8_t itlctl0 = R_TML->ITLCTL0; uint8_t itls0 = R_TML->ITLS0; uint8_t itlmkf0 = R_TML->ITLMKF0; - FSP_CRITICAL_SECTION_DEFINE; - /* Clear the ITF0i interrupt status flags for channel used. */ - itls0 &= BSP_FEATURE_TML_VALID_CHANNEL_MASK & ((uint8_t) ~(p_instance_ctrl->channel_mask)); + itls0 &= (uint8_t) ~(TML_PRV_CHANNEL_MASK); /* Start timer */ - itlctl0 |= BSP_FEATURE_TML_VALID_CHANNEL_MASK & p_instance_ctrl->channel_mask; + itlctl0 |= TML_PRV_CHANNEL_MASK; #if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE @@ -314,15 +335,12 @@ fsp_err_t R_TML_Start (timer_ctrl_t * const p_ctrl) } #endif - /* Critical section required because ITLCTL0 register is shared with other instances. */ - FSP_CRITICAL_SECTION_ENTER; - /* Write to registers */ R_TML->ITLMKF0 = itlmkf0; R_TML->ITLS0 = itls0; R_TML->ITLCTL0 = itlctl0; - FSP_CRITICAL_SECTION_EXIT; + TML_PRV_CRITICAL_SECTION_EXIT(); return FSP_SUCCESS; } @@ -341,16 +359,17 @@ fsp_err_t R_TML_Reset (timer_ctrl_t * const p_ctrl) #if TML_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(NULL != p_instance_ctrl); FSP_ERROR_RETURN(TML_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); - FSP_ERROR_RETURN(p_instance_ctrl->channel_mask & BSP_FEATURE_TML_VALID_CHANNEL_MASK, - FSP_ERR_IP_CHANNEL_NOT_PRESENT); + FSP_ERROR_RETURN(TML_PRV_CHANNEL_MASK & BSP_FEATURE_TML_VALID_CHANNEL_MASK, FSP_ERR_IP_CHANNEL_NOT_PRESENT); #endif - uint8_t channel_in_use = BSP_FEATURE_TML_VALID_CHANNEL_MASK & (R_TML->ITLCTL0 & p_instance_ctrl->channel_mask); - - FSP_CRITICAL_SECTION_DEFINE; +#if TML_CFG_SINGLE_CHANNEL_ENABLE + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif /* Critical section required because ITLCTL0 register is shared with other instances. */ - FSP_CRITICAL_SECTION_ENTER; + TML_PRV_CRITICAL_SECTION_ENTER(); + + uint8_t channel_in_use = R_TML->ITLCTL0 & TML_PRV_CHANNEL_MASK; /* Modifying ITLCTL0:ENi from 1 to 0 clears the counter without synchronization with the count clock */ R_TML->ITLCTL0 &= ~(channel_in_use); @@ -358,7 +377,7 @@ fsp_err_t R_TML_Reset (timer_ctrl_t * const p_ctrl) /* Restart the timer */ R_TML->ITLCTL0 |= channel_in_use; - FSP_CRITICAL_SECTION_EXIT; + TML_PRV_CRITICAL_SECTION_EXIT(); return FSP_SUCCESS; } @@ -377,46 +396,8 @@ fsp_err_t R_TML_Reset (timer_ctrl_t * const p_ctrl) fsp_err_t R_TML_Enable (timer_ctrl_t * const p_ctrl) { #if TML_CFG_INTERRUPT_SUPPORT_ENABLE - tml_instance_ctrl_t * p_instance_ctrl = (tml_instance_ctrl_t *) p_ctrl; - #if TML_CFG_PARAM_CHECKING_ENABLE - FSP_ASSERT(NULL != p_instance_ctrl); - FSP_ERROR_RETURN(TML_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); - FSP_ERROR_RETURN(p_instance_ctrl->channel_mask & BSP_FEATURE_TML_VALID_CHANNEL_MASK, - FSP_ERR_IP_CHANNEL_NOT_PRESENT); - #endif - uint8_t itls0 = R_TML->ITLS0; - uint8_t itlmkf0 = R_TML->ITLMKF0; - - FSP_CRITICAL_SECTION_DEFINE; - - /* Clear the ITF0i interrupt status flags for channel used. */ - itls0 &= BSP_FEATURE_TML_VALID_CHANNEL_MASK & ((uint8_t) ~(p_instance_ctrl->channel_mask)); - - /* Enable the interrupt generation from the selected channel by clearing the mask bits . */ - itlmkf0 &= BSP_FEATURE_TML_VALID_CHANNEL_MASK & ((uint8_t) ~(p_instance_ctrl->channel_mask)); - - #if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE - if (TIMER_MODE_16_BIT_CAPTURE == p_instance_ctrl->p_cfg->mode) - { - /* Clear the ITF0C interrupt status flags. */ - itls0 &= (uint8_t) ~(R_TML_ITLS0_ITF0C_Msk); - - /* Disable the MKF0C masks of the ITF0C status flags. */ - itlmkf0 &= (uint8_t) ~(R_TML_ITLMKF0_MKF0C_Msk); - } - #endif - - /* Critical section required because ITLMKF0, ITLS0, ITLCTL0 register is shared with other instances. */ - FSP_CRITICAL_SECTION_ENTER; - - /* Write to registers */ - R_TML->ITLS0 = itls0; - R_TML->ITLMKF0 = itlmkf0; - - FSP_CRITICAL_SECTION_EXIT; - - return FSP_SUCCESS; + return r_tml_enable_helper(p_ctrl, true); #else FSP_PARAMETER_NOT_USED(p_ctrl); @@ -440,45 +421,8 @@ fsp_err_t R_TML_Enable (timer_ctrl_t * const p_ctrl) fsp_err_t R_TML_Disable (timer_ctrl_t * const p_ctrl) { #if TML_CFG_INTERRUPT_SUPPORT_ENABLE - tml_instance_ctrl_t * p_instance_ctrl = (tml_instance_ctrl_t *) p_ctrl; - #if TML_CFG_PARAM_CHECKING_ENABLE - FSP_ASSERT(NULL != p_instance_ctrl); - FSP_ERROR_RETURN(TML_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); - FSP_ERROR_RETURN(p_instance_ctrl->channel_mask & BSP_FEATURE_TML_VALID_CHANNEL_MASK, - FSP_ERR_IP_CHANNEL_NOT_PRESENT); - #endif - uint8_t itls0 = R_TML->ITLS0; - uint8_t itlmkf0 = R_TML->ITLMKF0; - - FSP_CRITICAL_SECTION_DEFINE; - - /* Critical section required because ITLMKF0, ITLS0 register is shared with other instances. */ - FSP_CRITICAL_SECTION_ENTER; - - /* Disable the interrupt generation from the selected channel by setting the mask bits . */ - itlmkf0 |= BSP_FEATURE_TML_VALID_CHANNEL_MASK & p_instance_ctrl->channel_mask; - - /* Clear the ITF0i interrupt status flags for channel used. */ - itls0 &= BSP_FEATURE_TML_VALID_CHANNEL_MASK & ((uint8_t) ~(p_instance_ctrl->channel_mask)); - - #if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE - if (TIMER_MODE_16_BIT_CAPTURE == p_instance_ctrl->p_cfg->mode) - { - /* Enable the MKF0C masks of the ITF0C status flags. */ - itlmkf0 |= R_TML_ITLMKF0_MKF0C_Msk; - - /* Clear the ITF0C interrupt status flags. */ - itls0 &= (uint8_t) ~(R_TML_ITLS0_ITF0C_Msk); - } - #endif - - /* Write to registers */ - R_TML->ITLMKF0 = itlmkf0; - R_TML->ITLS0 = itls0; - FSP_CRITICAL_SECTION_EXIT; - - return FSP_SUCCESS; + return r_tml_enable_helper(p_ctrl, false); #else FSP_PARAMETER_NOT_USED(p_ctrl); @@ -505,7 +449,7 @@ fsp_err_t R_TML_PeriodSet (timer_ctrl_t * const p_ctrl, uint32_t const period_co FSP_ASSERT(NULL != p_instance_ctrl); FSP_ERROR_RETURN(TML_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); - uint8_t channel_status = R_TML->ITLCTL0 & p_instance_ctrl->channel_mask; + uint8_t channel_status = R_TML->ITLCTL0 & TML_PRV_CHANNEL_MASK; FSP_ERROR_RETURN(0U == channel_status, FSP_ERR_IN_USE); #endif @@ -572,7 +516,7 @@ fsp_err_t R_TML_InfoGet (timer_ctrl_t * const p_ctrl, timer_info_t * const p_inf /* Get and store counter clock frequency */ #if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE - if ((TML_PRV_ITLCC0_CAPEN_ENABLED == R_TML->ITLCC0_b.CAPEN) && + if (R_TML->ITLCC0_b.CAPEN && (TIMER_MODE_16_BIT_COUNTER == p_instance_ctrl->p_cfg->mode) && (BSP_CLOCKS_CLOCK_DISABLED != BSP_CFG_TML_FITL1_SOURCE)) { @@ -612,16 +556,18 @@ fsp_err_t R_TML_StatusGet (timer_ctrl_t * const p_ctrl, timer_status_t * const p FSP_ASSERT(NULL != p_instance_ctrl); FSP_ASSERT(NULL != p_status); FSP_ERROR_RETURN(TML_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); - FSP_ERROR_RETURN(p_instance_ctrl->channel_mask & BSP_FEATURE_TML_VALID_CHANNEL_MASK, - FSP_ERR_IP_CHANNEL_NOT_PRESENT); + FSP_ERROR_RETURN(TML_PRV_CHANNEL_MASK & BSP_FEATURE_TML_VALID_CHANNEL_MASK, FSP_ERR_IP_CHANNEL_NOT_PRESENT); +#endif + +#if TML_CFG_SINGLE_CHANNEL_ENABLE + FSP_PARAMETER_NOT_USED(p_instance_ctrl); #endif /* Store 0 to current counter since cannot read the counter value. */ p_status->counter = 0; /* Get counter state. */ - p_status->state = (timer_state_t) ((R_TML->ITLCTL0 >> p_instance_ctrl->p_cfg->channel) & - TML_PRV_ITLCTL0_EN_ENABLED); + p_status->state = (timer_state_t) ((R_TML->ITLCTL0 & TML_PRV_CHANNEL_MASK) > 0); return FSP_SUCCESS; } @@ -681,11 +627,16 @@ fsp_err_t R_TML_Close (timer_ctrl_t * const p_ctrl) #if TML_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(NULL != p_instance_ctrl); FSP_ERROR_RETURN(TML_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); - FSP_ERROR_RETURN(p_instance_ctrl->channel_mask & BSP_FEATURE_TML_VALID_CHANNEL_MASK, - FSP_ERR_IP_CHANNEL_NOT_PRESENT); + FSP_ERROR_RETURN(TML_PRV_CHANNEL_MASK & BSP_FEATURE_TML_VALID_CHANNEL_MASK, FSP_ERR_IP_CHANNEL_NOT_PRESENT); #endif - FSP_CRITICAL_SECTION_DEFINE; +#if TML_CFG_SINGLE_CHANNEL_ENABLE + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + /* Critical section required because ITLMKF0, ITLS0, ITLCTL0, ITLFDIV00, ITLFDIV01 registers are shared + * with other instances. */ + TML_PRV_CRITICAL_SECTION_ENTER(); #if TML_CFG_INTERRUPT_SUPPORT_ENABLE @@ -693,7 +644,6 @@ fsp_err_t R_TML_Close (timer_ctrl_t * const p_ctrl) if (0 <= p_instance_ctrl->p_cfg->cycle_end_irq) { R_BSP_IrqDisable(p_instance_ctrl->p_cfg->cycle_end_irq); - R_FSP_IsrContextSet(p_instance_ctrl->p_cfg->cycle_end_irq, NULL); } #endif @@ -702,13 +652,13 @@ fsp_err_t R_TML_Close (timer_ctrl_t * const p_ctrl) uint8_t itlctl0 = R_TML->ITLCTL0; /* Enable the interrupt generation from the selected channel by clearing the mask bits . */ - itlmkf0 &= BSP_FEATURE_TML_VALID_CHANNEL_MASK & ((uint8_t) ~(p_instance_ctrl->channel_mask)); + itlmkf0 &= (uint8_t) ~(TML_PRV_CHANNEL_MASK); /* Clear the ITF0i interrupt status flags. */ - itls0 &= BSP_FEATURE_TML_VALID_CHANNEL_MASK & ((uint8_t) ~(p_instance_ctrl->channel_mask)); + itls0 &= (uint8_t) ~(TML_PRV_CHANNEL_MASK); /* Stop counter channel. */ - itlctl0 &= (uint8_t) ~(BSP_FEATURE_TML_VALID_CHANNEL_MASK & p_instance_ctrl->channel_mask); + itlctl0 &= (uint8_t) ~(TML_PRV_CHANNEL_MASK); #if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE if (TIMER_MODE_16_BIT_CAPTURE == p_instance_ctrl->p_cfg->mode) @@ -733,20 +683,15 @@ fsp_err_t R_TML_Close (timer_ctrl_t * const p_ctrl) } #endif - /* Critical section required because ITLMKF0, ITLS0, ITLCTL0, ITLFDIV00, ITLFDIV01 registers are shared - * with other instances. */ - FSP_CRITICAL_SECTION_ENTER; - /* Write to registers. */ R_TML->ITLMKF0 = itlmkf0; R_TML->ITLS0 = itls0; R_TML->ITLCTL0 = itlctl0; /* Clear the frequency division ratio for the count source. */ - uint8_t channel = p_instance_ctrl->p_cfg->channel; - *(R_TML_ITLFDIV_ADDRESS(channel)) &= (uint8_t) ~(R_TML_ITLFDIV_MASK(channel)); + *(TML_PRV_ITLFDIV_ADDRESS) &= (uint8_t) ~(TML_PRV_ITLFDIV_MASK); - FSP_CRITICAL_SECTION_EXIT; + TML_PRV_CRITICAL_SECTION_EXIT(); #if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE if (TIMER_MODE_16_BIT_CAPTURE == p_instance_ctrl->p_cfg->mode) @@ -755,21 +700,23 @@ fsp_err_t R_TML_Close (timer_ctrl_t * const p_ctrl) FSP_ERROR_RETURN(0U == (BSP_FEATURE_TML_VALID_CHANNEL_MASK & R_TML->ITLCTL0), FSP_ERR_IN_USE); /* Disable capturing. */ - R_TML->ITLCC0_b.CAPEN = TML_PRV_ITLCC0_CAPEN_DISABLED; + R_TML->ITLCC0 &= (uint8_t) ~(R_TML_ITLCC0_CAPEN_Msk); /* Clear the capture clock setting. */ - R_TML->ITLCSEL0_b.CSEL = TML_PRV_ITLCC0_CAPEN_DISABLED; + R_TML->ITLCSEL0 &= (uint8_t) ~(R_TML_ITLCSEL0_CSEL_Msk); } #endif -#if TML_CFG_INTERRUPT_SUPPORT_ENABLE +#if !TML_CFG_SINGLE_CHANNEL_ENABLE + #if TML_CFG_INTERRUPT_SUPPORT_ENABLE /* Clear instance. */ - gp_tml_ctrls[p_instance_ctrl->p_cfg->channel] = NULL; -#endif - if (0U < modeset) + gp_tml_ctrls[TML_PRV_CHANNEL] = NULL; + #endif + if (0U < g_modeset) { - modeset--; + g_modeset--; } +#endif #if TML_CFG_PARAM_CHECKING_ENABLE @@ -792,20 +739,23 @@ fsp_err_t R_TML_Close (timer_ctrl_t * const p_ctrl) * @param[in] p_instance_ctrl Instance control block. * @param[in] p_cfg Pointer to timer configuration. * + * @retval FSP_SUCCESS Successful initialize. * @retval FSP_ERR_IN_USE Channel is running **********************************************************************************************************************/ fsp_err_t r_tml_hardware_initialize (tml_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg) { uint8_t channel = p_cfg->channel; p_instance_ctrl->channel_mask = (uint8_t) (1U << channel); - uint8_t timer_status = R_TML->ITLCTL0 & BSP_FEATURE_TML_VALID_CHANNEL_MASK; uint8_t itlctl0; uint8_t itlcsel0; /* Enable the TML channel and take module out of stop state. */ R_BSP_MODULE_START(FSP_IP_TML, channel); - FSP_CRITICAL_SECTION_DEFINE; + /* Critical section required because ITLCTL0, ITLFDIV00, ITLFDIV01, ITLCSEL0 registers is shared with other instances. */ + TML_PRV_CRITICAL_SECTION_ENTER(); + + uint8_t timer_status = R_TML->ITLCTL0 & BSP_FEATURE_TML_VALID_CHANNEL_MASK; #if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE @@ -840,34 +790,32 @@ fsp_err_t r_tml_hardware_initialize (tml_instance_ctrl_t * const p_instance_ctrl } /* Select the count clock for the counter timer */ - itlcsel0 = R_TML_ITLCSEL0_ISEL_Msk & (uint8_t) (R_TML_ITLCSEL0_ISEL_VALUE << R_TML_ITLCSEL0_ISEL_Pos); + itlcsel0 = R_TML_ITLCSEL0_ISEL_Msk & (uint8_t) (TML_PRV_ITLCSEL0_ISEL_VALUE << R_TML_ITLCSEL0_ISEL_Pos); #if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE /* Select the count clock for the capture timer */ - if (TML_PRV_ITLCC0_CAPEN_ENABLED == R_TML->ITLCC0_b.CAPEN) + if (R_TML->ITLCC0_b.CAPEN) { - itlcsel0 |= (R_TML_ITLCSEL0_CSEL_Msk & (uint8_t) (R_TML_ITLCSEL0_CSEL_VALUE << R_TML_ITLCSEL0_CSEL_Pos)); + itlcsel0 |= (R_TML_ITLCSEL0_CSEL_Msk & (uint8_t) (TML_PRV_ITLCSEL0_CSEL_VALUE << R_TML_ITLCSEL0_CSEL_Pos)); } #endif - /* Critical section required because ITLCTL0, ITLFDIV00, ITLFDIV01, ITLCSEL0 registers is shared with other instances. */ - FSP_CRITICAL_SECTION_ENTER; - /* Write to registers to setting mode/clock. */ - if (0U == modeset) +#if !TML_CFG_SINGLE_CHANNEL_ENABLE + if (0U == g_modeset++) +#endif { R_TML->ITLCTL0 = itlctl0 | timer_status; } - modeset++; R_TML->ITLCSEL0 = itlcsel0; /* Select the frequency division ratio for the count source. */ - *(R_TML_ITLFDIV_ADDRESS(channel)) |= R_TML_ITLFDIV_MASK(channel) & - ((uint8_t) p_cfg->source_div << (R_TML_ITLFDIV_POS(channel))); + *(TML_PRV_ITLFDIV_ADDRESS) |= TML_PRV_ITLFDIV_MASK & + ((uint8_t) p_cfg->source_div << (TML_PRV_ITLFDIV_POS)); - FSP_CRITICAL_SECTION_EXIT; + TML_PRV_CRITICAL_SECTION_EXIT(); /* Specify a period value for timer channel. */ r_tml_period_counts_set(p_instance_ctrl, (p_cfg->period_counts - 1)); @@ -892,8 +840,6 @@ fsp_err_t r_tml_hardware_initialize (tml_instance_ctrl_t * const p_instance_ctrl **********************************************************************************************************************/ void r_tml_period_counts_set (tml_instance_ctrl_t * const p_instance_ctrl, uint32_t const period_counts) { - uint8_t channel = p_instance_ctrl->p_cfg->channel; - /* Specify a period value. */ switch (p_instance_ctrl->p_cfg->mode) { @@ -904,14 +850,14 @@ void r_tml_period_counts_set (tml_instance_ctrl_t * const p_instance_ctrl, uint3 * The ITLCMP01_L for channel 2 * The ITLCMP01_H for channel 3 */ - *(&(R_TML->ITLCMP00_L) + channel) = (uint8_t) (period_counts); + *(&(R_TML->ITLCMP00_L) + TML_PRV_CHANNEL) = (uint8_t) (period_counts); break; } case TIMER_MODE_16_BIT_COUNTER: { /* Set the ITLCMP0n register (n: 0, 1) */ - *(&(R_TML->ITLCMP00) + channel / 2) = (uint16_t) (period_counts); + *(&(R_TML->ITLCMP00) + TML_PRV_CHANNEL / 2) = (uint16_t) (period_counts); break; } @@ -980,12 +926,14 @@ fsp_err_t r_tml_open_param_checking (tml_instance_ctrl_t * const p_instance_ctrl FSP_ERROR_RETURN(TML_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); /* Selected channel must be disabled (ITLCTL0.ENx is 0U). */ - FSP_ERROR_RETURN(TML_PRV_ITLCTL0_EN_DISABLED == (R_TML->ITLCTL0 & channel_mask), FSP_ERR_IN_USE); + FSP_ERROR_RETURN(0U == (R_TML->ITLCTL0 & channel_mask), FSP_ERR_IN_USE); + + #if !TML_CFG_SINGLE_CHANNEL_ENABLE /* Selected mode must be the same for all instance. */ - if (0U != modeset) + if (0U != g_modeset) { - #if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE + #if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE tml_extended_cfg_t * p_cfg_ext = (tml_extended_cfg_t *) p_cfg->p_extend; /* Channels 2 and 3 can only be used in 16-bit counter mode when an interrupt on compare match with @@ -993,15 +941,16 @@ fsp_err_t r_tml_open_param_checking (tml_instance_ctrl_t * const p_instance_ctrl if (!(((TIMER_MODE_16_BIT_COUNTER == R_TML->ITLCTL0_b.MD) && (TIMER_MODE_16_BIT_CAPTURE == mode) && (TML_CAPTURE_TRIGGER_ITLCMP01 != p_cfg_ext->capture_trigger)) || - ((TML_PRV_ITLCC0_CAPEN_ENABLED == R_TML->ITLCC0_b.CAPEN) && + (R_TML->ITLCC0_b.CAPEN && (TML_CAPTURE_TRIGGER_ITLCMP01 != R_TML->ITLCC0_b.CTRS) && (TIMER_MODE_16_BIT_COUNTER == mode)))) - #endif + #endif { /* Selected mode must be the same for all instance. */ FSP_ERROR_RETURN(mode == R_TML->ITLCTL0_b.MD, FSP_ERR_INVALID_MODE); } } + #endif /* Channel selected must be in range 0:3. */ FSP_ERROR_RETURN((channel_mask & BSP_FEATURE_TML_VALID_CHANNEL_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT); @@ -1011,7 +960,7 @@ fsp_err_t r_tml_open_param_checking (tml_instance_ctrl_t * const p_instance_ctrl #if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE /* The clock source division must be 0 if 16-bit counter channel use CSEL as clock source. */ - if ((TML_PRV_ITLCC0_CAPEN_ENABLED == R_TML->ITLCC0_b.CAPEN) && (TIMER_MODE_16_BIT_COUNTER == p_cfg->mode)) + if (R_TML->ITLCC0_b.CAPEN && (TIMER_MODE_16_BIT_COUNTER == mode)) { FSP_ASSERT(TIMER_SOURCE_DIV_1 == p_cfg->source_div); } @@ -1020,6 +969,12 @@ fsp_err_t r_tml_open_param_checking (tml_instance_ctrl_t * const p_instance_ctrl /* Validate period must be configured in correct range and channel must be selected according to each mode. */ FSP_ASSERT(1 < p_cfg->period_counts); + #if TML_CFG_SINGLE_CHANNEL_ENABLE + + /* Selected channel must match the channel selected by TML_CFG_SINGLE_CHANNEL_ENABLE */ + FSP_ERROR_RETURN(0U == p_cfg->channel, FSP_ERR_INVALID_CHANNEL); + #endif + if (TIMER_MODE_8_BIT_COUNTER == mode) { FSP_ASSERT(1 < p_cfg->period_counts); @@ -1065,7 +1020,6 @@ fsp_err_t r_tml_open_param_checking (tml_instance_ctrl_t * const p_instance_ctrl uint32_t r_tml_period_counts_get (tml_instance_ctrl_t * const p_instance_ctrl) { uint32_t period_counts = 0; - uint8_t channel = p_instance_ctrl->p_cfg->channel; /* Get a period value. */ switch (p_instance_ctrl->p_cfg->mode) @@ -1077,14 +1031,14 @@ uint32_t r_tml_period_counts_get (tml_instance_ctrl_t * const p_instance_ctrl) * The ITLCMP01_L for channel 2 * The ITLCMP01_H for channel 3 */ - period_counts = *(&(R_TML->ITLCMP00_L) + channel); + period_counts = *(&(R_TML->ITLCMP00_L) + TML_PRV_CHANNEL); break; } case TIMER_MODE_16_BIT_COUNTER: { /* Set the ITLCMP0n register (n: 0, 1) */ - period_counts = *(&(R_TML->ITLCMP00) + channel / 2); + period_counts = *(&(R_TML->ITLCMP00) + TML_PRV_CHANNEL / 2); break; } @@ -1124,6 +1078,73 @@ uint32_t r_tml_period_counts_get (tml_instance_ctrl_t * const p_instance_ctrl) #if TML_CFG_INTERRUPT_SUPPORT_ENABLE +/*******************************************************************************************************************//** + * Helper for enabling or disabling interrupts + * + * @param[in] p_ctrl Instance control block. + * @param[in] enable Whether or not to enable disable interrupts. + **********************************************************************************************************************/ +static fsp_err_t r_tml_enable_helper (timer_ctrl_t * const p_ctrl, bool enable) +{ + tml_instance_ctrl_t * p_instance_ctrl = (tml_instance_ctrl_t *) p_ctrl; + #if TML_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TML_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(TML_PRV_CHANNEL_MASK & BSP_FEATURE_TML_VALID_CHANNEL_MASK, FSP_ERR_IP_CHANNEL_NOT_PRESENT); + #endif + + #if TML_CFG_SINGLE_CHANNEL_ENABLE + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + #endif + + /* Critical section required because ITLMKF0, ITLS0, ITLCTL0 register is shared with other instances. */ + TML_PRV_CRITICAL_SECTION_ENTER(); + + uint8_t itls0 = R_TML->ITLS0; + uint8_t itlmkf0 = R_TML->ITLMKF0; + + /* Clear the ITF0i interrupt status flags for channel used. */ + itls0 &= (uint8_t) ~(TML_PRV_CHANNEL_MASK); + + if (enable) + { + /* Enable the interrupt generation from the selected channel by clearing the mask bits . */ + itlmkf0 &= (uint8_t) ~(TML_PRV_CHANNEL_MASK); + } + else + { + /* Disable the interrupt generation from the selected channel by setting the mask bits . */ + itlmkf0 |= TML_PRV_CHANNEL_MASK; + } + + #if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE + if (TIMER_MODE_16_BIT_CAPTURE == p_instance_ctrl->p_cfg->mode) + { + /* Clear the ITF0C interrupt status flags. */ + itls0 &= (uint8_t) ~(R_TML_ITLS0_ITF0C_Msk); + + if (enable) + { + /* Disable the MKF0C masks of the ITF0C status flags. */ + itlmkf0 &= (uint8_t) ~(R_TML_ITLMKF0_MKF0C_Msk); + } + else + { + /* Enable the MKF0C masks of the ITF0C status flags. */ + itlmkf0 |= R_TML_ITLMKF0_MKF0C_Msk; + } + } + #endif + + /* Write to registers */ + R_TML->ITLS0 = itls0; + R_TML->ITLMKF0 = itlmkf0; + + TML_PRV_CRITICAL_SECTION_EXIT(); + + return FSP_SUCCESS; +} + /*******************************************************************************************************************//** * Interrupt triggered by a compare match or capture. * @@ -1134,11 +1155,17 @@ void tml_itl_or_isr (void) /* Save context if RTOS is used */ FSP_CONTEXT_SAVE + #if TML_CFG_SINGLE_CHANNEL_ENABLE + IRQn_Type irq = R_FSP_CurrentIrqGet(); + tml_instance_ctrl_t * p_instance_ctrl = (tml_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + #else tml_instance_ctrl_t * p_instance_ctrl = gp_tml_ctrls[TML_CHANNEL_0]; - uint8_t itls0 = R_TML->ITLS0; - uint32_t capture = 0; - timer_event_t event = TIMER_EVENT_CYCLE_END; + #endif + uint8_t itls0 = R_TML->ITLS0; + uint32_t capture = 0; + timer_event_t event = TIMER_EVENT_CYCLE_END; + #if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE if (itls0 & R_TML_ITLS0_ITF0C_Msk) { /* Clear the interrupt flag. */ @@ -1150,7 +1177,10 @@ void tml_itl_or_isr (void) capture = R_TML->ITLCAP00; } else + #endif { + #if !TML_CFG_SINGLE_CHANNEL_ENABLE + /* Due to the shared IRQ for all of the TML we need to find the stored context from the channel instance. */ for (tml_channel_t channel = TML_CHANNEL_0; channel < BSP_FEATURE_TML_NUM_CHANNELS; channel++) { @@ -1160,18 +1190,21 @@ void tml_itl_or_isr (void) break; } } + #endif /* Clear the interrupt flag. */ - R_TML->ITLS0 = itls0 & ~(BSP_FEATURE_TML_VALID_CHANNEL_MASK & p_instance_ctrl->channel_mask); + R_TML->ITLS0 = itls0 & (uint8_t) ~(TML_PRV_CHANNEL_MASK); } /* If a callback is provided, then call it with the captured counter value. */ if (NULL != p_instance_ctrl->p_callback) { - timer_callback_args_t args = {0}; - args.p_context = p_instance_ctrl->p_context; - args.event = event; - args.capture = capture; + timer_callback_args_t args = + { + .p_context = p_instance_ctrl->p_context, + .event = event, + .capture = capture, + }; /* Call the callback. */ p_instance_ctrl->p_callback(&args); diff --git a/ra/fsp/src/r_uarta/r_uarta.c b/ra/fsp/src/r_uarta/r_uarta.c index 2b3ba91c0..5a0902ebd 100644 --- a/ra/fsp/src/r_uarta/r_uarta.c +++ b/ra/fsp/src/r_uarta/r_uarta.c @@ -41,10 +41,6 @@ #define UARTA_BRGCA_MAX (255) #define UARTA_BRGCA_MIN (2) -/* Delay cycles */ -#define UARTA_DELAY_2_CYCLE_UATCK (2U) -#define UARTA_DELAY_1_CYCLE_UATCK (1U) - /* Mask 2 bit for bit UTA0CK.SEL[1:0] */ #define UARTA_UTA0SEL_MASK (0x03U) @@ -74,10 +70,6 @@ #define UARTA_MAX_BAUD_RATE (153600) #endif -#define UARTA_ERR_OVERFLOW_SHIFT_VALUE (5) -#define UARTA_ERR_FRAMING_SHIFT_VALUE (4) -#define UARTA_ERR_PARITY_SHIFT_VALUE (3) - /*********************************************************************************************************************** * Private constants **********************************************************************************************************************/ @@ -96,15 +88,22 @@ static fsp_err_t r_uarta_read_write_param_check(uarta_instance_ctrl_t const * co uint8_t const * const addr, uint32_t const bytes); + #if (BSP_FEATURE_UARTA_PCLK_RESTRICTION) +static fsp_err_t r_uarta_operation_clock_validation(uarta_baud_setting_t const * const p_baud_setting); + + #endif + #endif #if UARTA_CFG_DTC_SUPPORT_ENABLE static fsp_err_t r_uarta_transfer_configure(uarta_instance_ctrl_t * const p_ctrl); -static fsp_err_t r_uarta_transfer_configure_helper(transfer_instance_t const * p_transfer, uart_dir_t direction); +static fsp_err_t r_uarta_transfer_configure_helper(uarta_instance_ctrl_t * p_ctrl, + transfer_instance_t const * p_transfer, + uart_dir_t direction); #endif -static void r_uarta_baud_set(uarta_baud_setting_t const * const p_baud_setting); +static void r_uarta_baud_set(uarta_instance_ctrl_t * p_ctrl, uarta_baud_setting_t const * const p_baud_setting); static void r_uarta_call_callback(uarta_instance_ctrl_t * p_ctrl, uint32_t data, uart_event_t event); @@ -130,16 +129,17 @@ void uarta_txi_isr(void); /** Look-up table for parity values */ static const uint8_t uarta_parity_lut[] = { - [UART_PARITY_OFF] = UARTA_PARITY_OFF_MAPPING << R_UARTA_ASIMA01_PS_Pos, - [UART_PARITY_ZERO] = UARTA_PARITY_ZERO_MAPPING << R_UARTA_ASIMA01_PS_Pos, - [UART_PARITY_EVEN] = UARTA_PARITY_EVEN_MAPPING << R_UARTA_ASIMA01_PS_Pos, - [UART_PARITY_ODD] = UARTA_PARITY_ODD_MAPPING << R_UARTA_ASIMA01_PS_Pos + [UART_PARITY_OFF] = UARTA_PARITY_OFF_MAPPING << R_UARTA0_ASIMAn1_PS_Pos, + [UART_PARITY_ZERO] = UARTA_PARITY_ZERO_MAPPING << R_UARTA0_ASIMAn1_PS_Pos, + [UART_PARITY_EVEN] = UARTA_PARITY_EVEN_MAPPING << R_UARTA0_ASIMAn1_PS_Pos, + [UART_PARITY_ODD] = UARTA_PARITY_ODD_MAPPING << R_UARTA0_ASIMAn1_PS_Pos }; /** Look-up table for converting UARTA clock source, used to get the clock value from R_BSP_SourceClockHzGet */ static fsp_priv_source_clock_t uarta_f_uta0_sel_lut[] = { [UARTA_CLOCK_SOURCE_SOSC_LOCO] = FSP_PRIV_CLOCK_LOCO, + [UARTA_CLOCK_SOURCE_SOSC] = FSP_PRIV_CLOCK_SUBCLOCK, [UARTA_CLOCK_SOURCE_MOSC] = FSP_PRIV_CLOCK_MAIN_OSC, [UARTA_CLOCK_SOURCE_HOCO] = FSP_PRIV_CLOCK_HOCO, [UARTA_CLOCK_SOURCE_MOCO] = FSP_PRIV_CLOCK_MOCO @@ -160,7 +160,7 @@ static const uint8_t uarta_event_lut[] = [7] = UART_EVENT_ERR_OVERFLOW | UART_EVENT_ERR_FRAMING | UART_EVENT_ERR_PARITY }; - #define UARTA_ASISA_RCVR_ERR_MASK (R_UARTA_ASISA0_OVEA_Msk | R_UARTA_ASISA0_FEA_Msk | R_UARTA_ASISA0_PEA_Msk) + #define UARTA_ASISA_RCVR_ERR_MASK (R_UARTA0_ASISAn_OVEA_Msk | R_UARTA0_ASISAn_FEA_Msk | R_UARTA0_ASISAn_PEA_Msk) #endif @@ -217,7 +217,7 @@ fsp_err_t R_UARTA_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const FSP_ERROR_RETURN(UARTA_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); /* Make sure this channel exists. */ - FSP_ERROR_RETURN(0U == p_cfg->channel, FSP_ERR_IP_CHANNEL_NOT_PRESENT); + FSP_ERROR_RETURN(((1 << p_cfg->channel) & BSP_PERIPHERAL_UARTA_CHANNEL_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT); FSP_ASSERT(p_cfg->rxi_irq >= 0); FSP_ASSERT(p_cfg->txi_irq >= 0); @@ -227,12 +227,29 @@ fsp_err_t R_UARTA_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const /* UARTA0_ERRI interrupt request should be greater than 0 when Receive Error Interrupt Mode is disabled */ FSP_ASSERT(p_cfg->eri_irq >= 0); #endif + + #if (BSP_FEATURE_UARTA_PCLK_RESTRICTION) + + /* Validate the f_uta before setting the baud rate*/ + FSP_ERROR_RETURN(FSP_SUCCESS == + r_uarta_operation_clock_validation(((uarta_extended_cfg_t *) p_cfg->p_extend)->p_baud_setting), + FSP_ERR_INVALID_ARGUMENT); + #endif #endif p_ctrl->p_cfg = p_cfg; p_ctrl->p_callback = p_cfg->p_callback; p_ctrl->p_context = p_cfg->p_context; +#if (BSP_PERIPHERAL_UARTA_CHANNEL_MASK > 1) + + /* Calculate the register base address. */ + uint32_t address_gap = (uint32_t) R_UARTA1 - (uint32_t) R_UARTA0; + p_ctrl->p_reg = (R_UARTA0_Type *) ((uint32_t) R_UARTA0 + (address_gap * p_cfg->channel)); +#else + p_ctrl->p_reg = R_UARTA0; +#endif + #if UARTA_CFG_DTC_SUPPORT_ENABLE /* Configure the transfer interface for transmission and reception if provided. */ @@ -248,41 +265,41 @@ fsp_err_t R_UARTA_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const uarta_extended_cfg_t * p_extend = (uarta_extended_cfg_t *) p_ctrl->p_cfg->p_extend; /* Set the baud rate settings for the internal baud rate generator. */ - r_uarta_baud_set(p_extend->p_baud_setting); + r_uarta_baud_set(p_ctrl, p_extend->p_baud_setting); /* Setting parity, length, stop, direction, and level bit */ - R_UARTA->ASIMA01 = (uint8_t) ((uarta_parity_lut[p_cfg->parity]) | - ((uint8_t) (p_cfg->data_bits << R_UARTA_ASIMA01_CL_Pos)) | - ((uint8_t) (p_cfg->stop_bits << R_UARTA_ASIMA01_SL_Pos)) | - ((uint8_t) (p_extend->transfer_dir << R_UARTA_ASIMA01_DIR_Pos)) | - ((uint8_t) (p_extend->transfer_level << R_UARTA_ASIMA01_ALV_Pos))); + p_ctrl->p_reg->ASIMAn1 = (uint8_t) (uarta_parity_lut[p_cfg->parity] | + ((uint8_t) (p_cfg->data_bits << R_UARTA0_ASIMAn1_CL_Pos)) | + ((uint8_t) (p_cfg->stop_bits << R_UARTA0_ASIMAn1_SL_Pos)) | + ((uint8_t) (p_extend->transfer_dir << R_UARTA0_ASIMAn1_DIR_Pos)) | + ((uint8_t) (p_extend->transfer_level << R_UARTA0_ASIMAn1_ALV_Pos))); /* Setting interrupt for continuous transmission and receive interrupt mode select */ - uint8_t asima0 = (uint8_t) ((R_UARTA_ASIMA00_ISSMA_Msk) | - ((uint8_t) (UARTA_CFG_RECEIVE_ERROR_INTERRUPT_MODE << R_UARTA_ASIMA00_ISRMA_Pos))); + uint8_t asima0 = (uint8_t) ((R_UARTA0_ASIMAn0_ISSMA_Msk) | + ((uint8_t) (UARTA_CFG_RECEIVE_ERROR_INTERRUPT_MODE << R_UARTA0_ASIMAn0_ISRMA_Pos))); /* Configure for register ASIMA0 */ - R_UARTA->ASIMA00 = asima0; + p_ctrl->p_reg->ASIMAn0 = asima0; /* Enables the UARTA operation clock */ - asima0 |= R_UARTA_ASIMA00_EN_Msk; - R_UARTA->ASIMA00 = asima0; + asima0 |= R_UARTA0_ASIMAn0_EN_Msk; + p_ctrl->p_reg->ASIMAn0 = asima0; #if (UARTA_CFG_RX_ENABLE) p_ctrl->rx_dest_bytes = 0; /* If reception is enabled at build time, enable reception. */ - asima0 |= R_UARTA_ASIMA00_RXEA_Msk; + asima0 |= R_UARTA0_ASIMAn0_RXEA_Msk; #endif #if (UARTA_CFG_TX_ENABLE) p_ctrl->tx_src_bytes = 0; /* If transmission is enabled at build time, enable transmission. */ - asima0 |= R_UARTA_ASIMA00_TXEA_Msk; + asima0 |= R_UARTA0_ASIMAn0_TXEA_Msk; #endif - R_UARTA->ASIMA00 = asima0; + p_ctrl->p_reg->ASIMAn0 = asima0; #if (UARTA_CFG_RX_ENABLE) #if (UARTA_CFG_RECEIVE_ERROR_INTERRUPT_MODE == 0) @@ -328,15 +345,15 @@ fsp_err_t R_UARTA_Close (uart_ctrl_t * const p_api_ctrl) p_ctrl->open = 0; /* Disable receiver, and transmitter. */ - uint8_t current_value = R_UARTA->ASIMA00; + uint8_t current_value = p_ctrl->p_reg->ASIMAn0; /* Do read-modify-write for TXEA/RXEA */ - current_value &= (uint8_t) ~(R_UARTA_ASIMA00_TXEA_Msk | R_UARTA_ASIMA00_RXEA_Msk); + current_value &= (uint8_t) ~(R_UARTA0_ASIMAn0_TXEA_Msk | R_UARTA0_ASIMAn0_RXEA_Msk); - R_UARTA->ASIMA00 = current_value; + p_ctrl->p_reg->ASIMAn0 = current_value; /* Disable baud clock output. Must be done separately after disabling TX/RX. */ - R_UARTA->ASIMA00 = (uint8_t) (current_value & ~R_UARTA_ASIMA00_EN_Msk); + p_ctrl->p_reg->ASIMAn0 = (uint8_t) (current_value & ~R_UARTA0_ASIMAn0_EN_Msk); #if (UARTA_CFG_RX_ENABLE) #if (UARTA_CFG_RECEIVE_ERROR_INTERRUPT_MODE == 0) @@ -481,14 +498,14 @@ fsp_err_t R_UARTA_Write (uart_ctrl_t * const p_api_ctrl, uint8_t const * const p } #endif - p_ctrl->tx_src_bytes = num_transfers; - R_UARTA->ASIMA00_b.ISSMA = 1; + p_ctrl->tx_src_bytes = num_transfers; + p_ctrl->p_reg->ASIMAn0_b.ISSMA = 1; /* Enable transmit interrupt */ R_BSP_IrqEnable(p_ctrl->p_cfg->txi_irq); /* Assign to first byte */ - R_UARTA->TXBA0 = *(p_src); + p_ctrl->p_reg->TXBAn = *(p_src); return FSP_SUCCESS; #else @@ -548,19 +565,24 @@ fsp_err_t R_UARTA_BaudSet (uart_ctrl_t * const p_api_ctrl, void const * const p_ #if (UARTA_CFG_PARAM_CHECKING_ENABLE) FSP_ASSERT(p_ctrl); FSP_ERROR_RETURN(UARTA_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + #if (BSP_FEATURE_UARTA_PCLK_RESTRICTION) + FSP_ERROR_RETURN(FSP_SUCCESS == + r_uarta_operation_clock_validation(p_baud_setting), + FSP_ERR_INVALID_ARGUMENT); + #endif #endif /* Disable transmit interrupt. Resuming transmission after reconfiguring baud settings is * not supported. */ R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); - uint8_t preserved_asima00 = R_UARTA->ASIMA00; + uint8_t preserved_asiman0 = p_ctrl->p_reg->ASIMAn0; /* Modify the BRGCAn bits while the TXEAn and RXEAn bits are 0 (in the transmission/reception stopped state).*/ - R_UARTA->ASIMA00 = (preserved_asima00 & (uint8_t) (~(R_UARTA_ASIMA00_RXEA_Msk | R_UARTA_ASIMA00_TXEA_Msk))); + p_ctrl->p_reg->ASIMAn0 = (preserved_asiman0 & (uint8_t) (~(R_UARTA0_ASIMAn0_RXEA_Msk | R_UARTA0_ASIMAn0_TXEA_Msk))); /* Apply new baud rate register settings. */ - r_uarta_baud_set(p_baud_setting); + r_uarta_baud_set(p_ctrl, p_baud_setting); /* To enable transmission or reception again, set the TXEAn or RXEAn bit to 1 at least two cycles of the UARTAn * operation clock after clearing the TXEAn or RXEAn bit to 0 according to "Note" section 22.2.3 @@ -569,11 +591,11 @@ fsp_err_t R_UARTA_BaudSet (uart_ctrl_t * const p_api_ctrl, void const * const p_ R_BSP_SoftwareDelay((uint32_t) delay_time << 1U, BSP_DELAY_UNITS_MICROSECONDS); /* Restore all settings. */ - R_UARTA->ASIMA00 = preserved_asima00; + p_ctrl->p_reg->ASIMAn0 = preserved_asiman0; #if (UARTA_CFG_TX_ENABLE) /* If transmission is enabled at build time, enable transmission. */ - if (preserved_asima00 & R_UARTA_ASIMA00_TXEA_Msk) + if (preserved_asiman0 & R_UARTA0_ASIMAn0_TXEA_Msk) { /* Wait for the period of at least one cycle of the UARTA operation clock according to "Note" section 22.2.3 * "ASIMA00 : Operation Mode Setting Register 00" in the RA0E1 manual r01uh1040ej0060-ra0e1.pdf .*/ @@ -762,8 +784,12 @@ fsp_err_t R_UARTA_BaudCalculate (uint32_t baudrate, uint32_t clock_source_value = R_BSP_SourceClockHzGet(uarta_f_uta0_sel_lut[clock_source]); +#if (BSP_FEATURE_UARTA_PCLK_RESTRICTION) + uint32_t pclk_constraint = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB); +#endif + /* Go ahead and set the clock source here. It stays constant through the baud rate search. */ - p_baud_setting->uta0ck_clock_b.utasel = (uint8_t) (clock_source & UARTA_UTA0SEL_MASK); + p_baud_setting->utanck_clock_b.utasel = (uint8_t) (clock_source & UARTA_UTA0SEL_MASK); for (uarta_clock_div_t f_uta0_div = UARTA_CLOCK_DIV_1; f_uta0_div < UARTA_CLOCK_DIV_COUNT; f_uta0_div++) { @@ -775,7 +801,11 @@ fsp_err_t R_UARTA_BaudCalculate (uint32_t baudrate, * Integer round to the nearest divider. */ uint32_t divider = ((f_uta0_value + baudrate) >> 1) / baudrate; - if ((divider >= UARTA_BRGCA_MIN) && (divider <= UARTA_BRGCA_MAX)) + if ((divider >= UARTA_BRGCA_MIN) && (divider <= UARTA_BRGCA_MAX) +#if (BSP_FEATURE_UARTA_PCLK_RESTRICTION) + && (f_uta0_value <= pclk_constraint) +#endif + ) { /* Calculate actual baudrate using the divider. */ uint32_t actual_baudrate = (f_uta0_value >> 1) / divider; @@ -785,16 +815,24 @@ fsp_err_t R_UARTA_BaudCalculate (uint32_t baudrate, { delta_max = delta; p_baud_setting->brgca = (uint8_t) divider; - p_baud_setting->uta0ck_clock_b.uta0ck = (uint8_t) (f_uta0_div & R_UARTA_UTA0CK_CK_Msk); + p_baud_setting->utanck_clock_b.utanck = (uint8_t) (f_uta0_div & R_UARTA_CK_UTAnCK_CK_Msk); ret = FSP_SUCCESS; } } - if (UARTA_CLOCK_SOURCE_SOSC_LOCO == clock_source) + if (UARTA_CLOCK_SOURCE_LOCO == clock_source) { - p_baud_setting->uta0ck_clock_b.uta0ck = UARTA_UTA0CK_SOSC_LOCO_SETTING; + p_baud_setting->utanck_clock_b.utanck = UARTA_UTAnCK_LOCO_SETTING; break; } + +#if (!BSP_FEATURE_BSP_HAS_FSXP_CLOCK) + if (UARTA_CLOCK_SOURCE_SOSC == clock_source) + { + p_baud_setting->utanck_clock_b.utanck = UARTA_UTAnCK_SOSC_SETTING; + break; + } +#endif } return ret; @@ -854,7 +892,7 @@ static fsp_err_t r_uarta_transfer_configure (uarta_instance_ctrl_t * const p_ctr transfer_instance_t const * p_transfer_rx = p_ctrl->p_cfg->p_transfer_rx; /* If a transfer instance is used for reception, apply UART specific settings and open the transfer instance. */ - err = r_uarta_transfer_configure_helper(p_transfer_rx, UART_DIR_RX); + err = r_uarta_transfer_configure_helper(p_ctrl, p_transfer_rx, UART_DIR_RX); FSP_ERROR_RETURN(FSP_SUCCESS == err, err); #endif @@ -862,7 +900,7 @@ static fsp_err_t r_uarta_transfer_configure (uarta_instance_ctrl_t * const p_ctr transfer_instance_t const * p_transfer_tx = p_ctrl->p_cfg->p_transfer_tx; /* If a transfer instance is used for transmission, apply UART specific settings and open the transfer instance. */ - err = r_uarta_transfer_configure_helper(p_transfer_tx, UART_DIR_TX); + err = r_uarta_transfer_configure_helper(p_ctrl, p_transfer_tx, UART_DIR_TX); #if (UARTA_CFG_RX_ENABLE) if ((err != FSP_SUCCESS) && (NULL != p_transfer_rx)) { @@ -880,7 +918,9 @@ static fsp_err_t r_uarta_transfer_configure (uarta_instance_ctrl_t * const p_ctr * @param[in] p_transfer Pointer to transfer instance. * @param[in] direction UART_DIR_TX or UART_DIR_RX. **********************************************************************************************************************/ -static fsp_err_t r_uarta_transfer_configure_helper (transfer_instance_t const * p_transfer, uart_dir_t direction) +static fsp_err_t r_uarta_transfer_configure_helper (uarta_instance_ctrl_t * const p_ctrl, + transfer_instance_t const * p_transfer, + uart_dir_t direction) { fsp_err_t err = FSP_SUCCESS; @@ -901,12 +941,12 @@ static fsp_err_t r_uarta_transfer_configure_helper (transfer_instance_t const * if (UART_DIR_RX == direction) { p_info->transfer_settings_word = UARTA_DTC_RX_TRANSFER_SETTINGS; - p_info->p_src = (void *) &(R_UARTA->RXBA0); + p_info->p_src = (void *) &(p_ctrl->p_reg->RXBAn); } else { p_info->transfer_settings_word = UARTA_DTC_TX_TRANSFER_SETTINGS; - p_info->p_dest = (void *) &(R_UARTA->TXBA0); + p_info->p_dest = (void *) &(p_ctrl->p_reg->TXBAn); } err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg); @@ -920,19 +960,66 @@ static fsp_err_t r_uarta_transfer_configure_helper (transfer_instance_t const * /*******************************************************************************************************************//** * Changes baud rate based on predetermined register settings. * - * @param[in] p_baud_setting Pointer to baud rate settings + * @param[in] p_ctrl Pointer to instance control block. + * @param[in] p_baud_setting Pointer to other divisor related settings * * @note The transmitter and receiver (TXEA and RXEA bits in ASIMA00) must be disabled prior to calling this function. **********************************************************************************************************************/ -static void r_uarta_baud_set (uarta_baud_setting_t const * const p_baud_setting) +static void r_uarta_baud_set (uarta_instance_ctrl_t * p_ctrl, uarta_baud_setting_t const * const p_baud_setting) { /* Set BRGCA register value. */ - R_UARTA->BRGCA0 = p_baud_setting->brgca; + p_ctrl->p_reg->BRGCAn = p_baud_setting->brgca; + uint8_t utack_value = p_baud_setting->utanck_clock; + +#if (BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT) + + /* Set the UART configuration settings provided in ::uart_cfg_t and :: uarta_extended_cfg_t. */ + utack_value |= (uint8_t) (((uarta_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->clock_output << + R_UARTA_CK_UTAnCK_EN_Pos); +#endif + + /* Set UTA0CK/UTA1CK register value. */ + R_UARTA_CK->UTAnCK[p_ctrl->p_cfg->channel] = utack_value; + +#if (BSP_PERIPHERAL_UARTA_CHANNEL_MASK > 1) - /* Set UTA0CK register value. */ - R_UARTA->UTA0CK = p_baud_setting->uta0ck_clock; + /* Set fSEL clock select */ + R_UARTA_CK->UTAnCK_b[0].SEL = p_baud_setting->utanck_clock_b.utasel; +#endif } +#if (UARTA_CFG_PARAM_CHECKING_ENABLE) + #if (BSP_FEATURE_UARTA_PCLK_RESTRICTION) + +/*******************************************************************************************************************//** + * Validates the baud rate divisor for the given UARTA clock frequency against PCLK constraints. + * + * This function checks if the UARTA operation clock (derived from the frequency settings of the baud rate generator) + * is within acceptable limits as defined by the PCLK. + * + * @param[in] p_baud_setting Pointer to the baud rate settings structure which includes the UARTA clock selection. + * @retval FSP_SUCCESS The UARTA operation clock is within acceptable limits. + * @retval FSP_ERR_INVALID_ARGUMENT The UARTA operation clock exceeds PCLK constraints. + **********************************************************************************************************************/ +static fsp_err_t r_uarta_operation_clock_validation (uarta_baud_setting_t const * const p_baud_setting) +{ + /* Retrieve the PCLKB constraint and operation clock uarta value */ + uint32_t pclk_constraint = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB); + uint32_t clock_source_value = R_BSP_SourceClockHzGet(uarta_f_uta0_sel_lut[p_baud_setting->utanck_clock_b.utasel]); + uint32_t f_uta = clock_source_value >> (p_baud_setting->utanck_clock_b.utanck & UARTA_CLOCK_DIV_MASK); + + /* Check if UARTA operation clock exceeds the PCLK constraint */ + if (f_uta > pclk_constraint) + { + return FSP_ERR_INVALID_ARGUMENT; + } + + return FSP_SUCCESS; +} + + #endif +#endif + /*******************************************************************************************************************//** * This function calculates the wait time to enable TX * @@ -940,13 +1027,13 @@ static void r_uarta_baud_set (uarta_baud_setting_t const * const p_baud_setting) **********************************************************************************************************************/ static uint16_t r_uarta_calculate_wait_time (uarta_baud_setting_t const * const p_baud_setting) { - uint8_t uta0ck = p_baud_setting->uta0ck_clock_b.uta0ck; - uint8_t utasel = p_baud_setting->uta0ck_clock_b.utasel; + uint8_t utanck = p_baud_setting->utanck_clock_b.utanck; + uint8_t utasel = p_baud_setting->utanck_clock_b.utasel; /* Get UARTA clock divider shift. * Anything outside UARTA_CLOCK_DIV_MASK is not a valid divider and is probably LOCO/SOSC selection instead. */ - uint32_t divider_shift = (uint32_t) (uta0ck & UARTA_CLOCK_DIV_MASK); + uint32_t divider_shift = (uint32_t) (utanck & UARTA_CLOCK_DIV_MASK); /* Calculate frequency UARTA0 operation clock */ uint32_t f_uta0 = (R_BSP_SourceClockHzGet(uarta_f_uta0_sel_lut[utasel]) >> divider_shift); @@ -994,6 +1081,12 @@ void uarta_txi_isr (void) IRQn_Type irq = R_FSP_CurrentIrqGet(); + #if (BSP_FEATURE_ICU_HAS_IELSR) + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + #endif + /* Recover ISR context saved in open. */ uarta_instance_ctrl_t * p_ctrl = (uarta_instance_ctrl_t *) R_FSP_IsrContextGet(irq); @@ -1004,7 +1097,7 @@ void uarta_txi_isr (void) #endif { /* Write 1byte (uint8_t) data to (uint8_t) data register */ - R_UARTA->TXBA0 = *(p_ctrl->p_tx_src); + p_ctrl->p_reg->TXBAn = *(p_ctrl->p_tx_src); /* Update pointer to the next data and number of remaining bytes in the control block. */ p_ctrl->tx_src_bytes -= 1U; @@ -1018,9 +1111,9 @@ void uarta_txi_isr (void) } #endif } - else if (0U != (R_UARTA->ASIMA00 & R_UARTA_ASIMA00_ISSMA_Msk)) + else if (0U != (p_ctrl->p_reg->ASIMAn0 & R_UARTA0_ASIMAn0_ISSMA_Msk)) { - R_UARTA->ASIMA00_b.ISSMA = 0U; + p_ctrl->p_reg->ASIMAn0_b.ISSMA = 0U; } else if (0 == p_ctrl->tx_src_bytes) { @@ -1055,20 +1148,26 @@ void uarta_rxi_isr (void) IRQn_Type irq = R_FSP_CurrentIrqGet(); + #if (BSP_FEATURE_ICU_HAS_IELSR) + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + #endif + /* Recover ISR context saved in open. */ uarta_instance_ctrl_t * p_ctrl = (uarta_instance_ctrl_t *) R_FSP_IsrContextGet(irq); #if UARTA_CFG_DTC_SUPPORT_ENABLE if ((p_ctrl->p_cfg->p_transfer_rx == NULL) || (0 == p_ctrl->rx_dest_bytes)) #endif { - uint8_t data = R_UARTA->RXBA0; + uint8_t data = p_ctrl->p_reg->RXBAn; #if (UARTA_CFG_RECEIVE_ERROR_INTERRUPT_MODE != 0) /* Determine cause of error. */ - uint8_t err_type = R_UARTA->ASISA0; + uint8_t err_type = p_ctrl->p_reg->ASISAn; /* Clear error condition. */ - R_UARTA->ASCTA0 = UARTA_ASISA_RCVR_ERR_MASK; + p_ctrl->p_reg->ASCTAn = UARTA_ASISA_RCVR_ERR_MASK; err_type &= (uint8_t) UARTA_ASISA_RCVR_ERR_MASK; err_type = uarta_event_lut[err_type]; @@ -1126,17 +1225,23 @@ void uarta_eri_isr (void) /* Recover ISR context saved in open. */ uarta_instance_ctrl_t * p_ctrl = (uarta_instance_ctrl_t *) R_FSP_IsrContextGet(irq); - uint8_t data = R_UARTA->RXBA0; + uint8_t data = p_ctrl->p_reg->RXBAn; - uint8_t err_type = R_UARTA->ASISA0; + uint8_t err_type = p_ctrl->p_reg->ASISAn; /* Clear error condition. */ - R_UARTA->ASCTA0 = UARTA_ASISA_RCVR_ERR_MASK; + p_ctrl->p_reg->ASCTAn = UARTA_ASISA_RCVR_ERR_MASK; err_type &= (uint8_t) UARTA_ASISA_RCVR_ERR_MASK; err_type = uarta_event_lut[err_type]; r_uarta_call_callback(p_ctrl, data, (uart_event_t) err_type); + #if (BSP_FEATURE_ICU_HAS_IELSR) + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + #endif + /* Restore context if RTOS is used */ FSP_CONTEXT_RESTORE; #endif diff --git a/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_access.c b/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_access.c index 540bd4fe5..48266c6f8 100644 --- a/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_access.c +++ b/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_access.c @@ -834,7 +834,7 @@ void hw_usb_hmodule_init (uint8_t usb_ip) else { #if defined(USB_HIGH_SPEED_MODULE) - USB_M1->PHYSET = (USB_DIRPD | USB_CLKSEL); + USB_M1->PHYSET |= (USB_DIRPD | USB_CLKSEL); #if USB_CFG_CLKSEL == USB_CFG_48MHZ USB_M1->PHYSET &= (uint16_t) ~USB_CLKSEL; diff --git a/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_access.c b/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_access.c index a8a60a7c7..615c9fe83 100644 --- a/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_access.c +++ b/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_access.c @@ -250,7 +250,7 @@ void hw_usb_pmodule_init (uint8_t usb_ip) else { #if defined(USB_HIGH_SPEED_MODULE) - USB_M1->PHYSET = (USB_DIRPD | USB_CLKSEL); + USB_M1->PHYSET |= (USB_DIRPD | USB_CLKSEL); #if USB_CFG_CLKSEL == USB_CFG_48MHZ USB_M1->PHYSET &= (uint16_t) ~USB_CLKSEL; diff --git a/ra/fsp/src/rm_ble_abs_gtl/r_ble_gtl_api.c b/ra/fsp/src/rm_ble_abs_gtl/r_ble_gtl_api.c index 7a4f25aac..e817349fd 100644 --- a/ra/fsp/src/rm_ble_abs_gtl/r_ble_gtl_api.c +++ b/ra/fsp/src/rm_ble_abs_gtl/r_ble_gtl_api.c @@ -11,6 +11,7 @@ #include "qe_ble_profile.h" #include "r_ble_gtl.h" +#include "r_ble_gtl_security.h" /*********************************************************************************************************************** * Defines @@ -409,10 +410,17 @@ ble_status_t R_BLE_GAP_GetRemDevInfo (uint16_t conn_hdl) ble_status_t R_BLE_GAP_SetPairingParams (st_ble_gap_pairing_param_t * p_pair_param) { - FSP_PARAMETER_NOT_USED(p_pair_param); + ble_status_t status = BLE_ERR_UNSPECIFIED; - /* Functionality not yet implemented */ - return BLE_ERR_UNSUPPORTED; + status = R_BLE_GTL_GAP_SetPairingParams(p_pair_param); + + /* Generate and register keys */ + if(status == BLE_SUCCESS) + { + status = r_ble_gtl_sec_generate_and_store_ltk_keys_req(BLE_GAP_EDIV_SIZE + BLE_GAP_RAND_64_BIT_SIZE + BLE_GAP_LTK_SIZE); + } + + return status; } ble_status_t R_BLE_GAP_SetLocIdInfo (st_ble_dev_addr_t * p_lc_id_addr, uint8_t * p_lc_irk) @@ -434,19 +442,20 @@ ble_status_t R_BLE_GAP_SetLocCsrk (uint8_t * p_local_csrk) ble_status_t R_BLE_GAP_StartPairing (uint16_t conn_hdl) { - FSP_PARAMETER_NOT_USED(conn_hdl); + ble_status_t status = BLE_ERR_UNSPECIFIED; - /* Functionality not yet implemented */ - return BLE_ERR_UNSUPPORTED; + status = r_ble_gtl_security_cmd (conn_hdl); + + return status; } ble_status_t R_BLE_GAP_ReplyPairing (uint16_t conn_hdl, uint8_t response) { - FSP_PARAMETER_NOT_USED(conn_hdl); - FSP_PARAMETER_NOT_USED(response); + ble_status_t status = BLE_ERR_UNSPECIFIED; - /* Functionality not yet implemented */ - return BLE_ERR_UNSUPPORTED; + status = r_ble_gtl_send_gapc_bond_cfm(conn_hdl, R_BLE_GTL_GAPC_PAIRING_RSP, response, NULL_TK_VAL); + + return status; } ble_status_t R_BLE_GAP_StartEnc (uint16_t conn_hdl) @@ -459,12 +468,11 @@ ble_status_t R_BLE_GAP_StartEnc (uint16_t conn_hdl) ble_status_t R_BLE_GAP_ReplyPasskeyEntry (uint16_t conn_hdl, uint32_t passkey, uint8_t response) { - FSP_PARAMETER_NOT_USED(conn_hdl); - FSP_PARAMETER_NOT_USED(passkey); - FSP_PARAMETER_NOT_USED(response); + ble_status_t status = BLE_ERR_UNSPECIFIED; - /* Functionality not yet implemented */ - return BLE_ERR_UNSUPPORTED; + status = r_ble_gtl_send_gapc_bond_cfm(conn_hdl, R_BLE_GTL_GAPC_TK_EXCH, response, passkey); + + return status; } ble_status_t R_BLE_GAP_ReplyNumComp (uint16_t conn_hdl, uint8_t response) @@ -496,10 +504,21 @@ ble_status_t R_BLE_GAP_GetDevSecInfo (uint16_t conn_hdl, st_ble_gap_auth_info_t ble_status_t R_BLE_GAP_ReplyExKeyInfoReq (uint16_t conn_hdl) { - FSP_PARAMETER_NOT_USED(conn_hdl); + ble_status_t status = BLE_ERR_UNSUPPORTED; + uint8_t loc_key_dist_var = r_ble_gtl_sec_get_loc_key_dist_var(); - /* Functionality not yet implemented */ - return BLE_ERR_UNSUPPORTED; + /* Verify the keys of local device distribution*/ + if (loc_key_dist_var & BLE_GAP_KEY_DIST_ENCKEY) + { + status = r_ble_gtl_send_gapc_bond_cfm(conn_hdl, R_BLE_GTL_GAPC_LTK_EXCH, true, NULL_TK_VAL); + } + else + { + /* Functionality not yet implemented */ + status = BLE_ERR_UNSUPPORTED; + } + + return status; } ble_status_t R_BLE_GAP_SetRemOobData (st_ble_dev_addr_t * p_addr, uint8_t oob_data_flag, st_ble_gap_oob_data_t * p_oob) @@ -544,13 +563,24 @@ void R_BLE_GAP_DeleteBondInfo (int32_t local, ble_status_t R_BLE_GAP_ReplyLtkReq (uint16_t conn_hdl, uint16_t ediv, uint8_t * p_peer_rand, uint8_t response) { - FSP_PARAMETER_NOT_USED(conn_hdl); - FSP_PARAMETER_NOT_USED(ediv); - FSP_PARAMETER_NOT_USED(p_peer_rand); - FSP_PARAMETER_NOT_USED(response); + FSP_PARAMETER_NOT_USED(response); - /* Functionality not yet implemented */ - return BLE_ERR_UNSUPPORTED; + bool comp_resp = r_ble_gtl_sec_encryption_req_resp(ediv, p_peer_rand); + + if(comp_resp) + { + /* Values found in db */ + r_ble_gtl_send_gapc_encrypt_cfm(conn_hdl, BLE_GAP_LTK_REQ_ACCEPT); + } + else + { + /* Values NOT found in db */ + r_ble_gtl_send_gapc_encrypt_cfm(conn_hdl, BLE_GAP_LTK_REQ_DENY); + } + + r_ble_gtl_gapc_ltk_rsp_comp(conn_hdl, comp_resp); + + return BLE_SUCCESS; } ble_status_t R_BLE_GATT_GetMtu (uint16_t conn_hdl, uint16_t * p_mtu) diff --git a/ra/fsp/src/rm_block_media_ram/rm_block_media_ram.c b/ra/fsp/src/rm_block_media_ram/rm_block_media_ram.c index 718583f91..88e2dfa79 100644 --- a/ra/fsp/src/rm_block_media_ram/rm_block_media_ram.c +++ b/ra/fsp/src/rm_block_media_ram/rm_block_media_ram.c @@ -28,7 +28,7 @@ #define VALUE_20H (0x20) #define STRG_SECTSIZE (VALUE_512) -#define STRG_TOTALSECT (RM_BLOCK_MEIDA_RAM_CFG_MEDIA_SIZE / STRG_SECTSIZE) +#define STRG_TOTALSECT (RM_BLOCK_MEDIA_RAM_CFG_MEDIA_SIZE / STRG_SECTSIZE) #define RAMDISK_MEDIATYPE (0xF8U) #define RAMDISK_SIGNATURE (0xAA55U) @@ -421,7 +421,8 @@ static const uint8_t g_block_media_ram_rootdir[STRG_SECTSIZE * 16UL] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; -static uint8_t g_block_media_ram_area[RM_BLOCK_MEIDA_RAM_CFG_MEDIA_SIZE]; +static uint8_t BSP_PLACE_IN_SECTION(RM_BLOCK_MEDIA_RAM_CFG_SECTION) g_block_media_ram_area[ + RM_BLOCK_MEDIA_RAM_CFG_MEDIA_SIZE]; /*********************************************************************************************************************** * Global Variables @@ -523,11 +524,11 @@ fsp_err_t RM_BLOCK_MEDIA_RAM_MediaInit (rm_block_media_ctrl_t * const p_ctrl) adr += (STRG_SECTSIZE * VALUE_16); /* rootdir are size */ - memset((void *) adr, 0, (RM_BLOCK_MEIDA_RAM_CFG_MEDIA_SIZE - (adr - start_address))); /* user media area zero clear */ + memset((void *) adr, 0, (RM_BLOCK_MEDIA_RAM_CFG_MEDIA_SIZE - (adr - start_address))); /* user media area zero clear */ if (NULL != p_instance_ctrl->p_callback) { - block_media_ram_args.event = RM_BLOCK_MEDIA_EVENT_OPERATION_COMPLETE; + block_media_ram_args.event = RM_BLOCK_MEDIA_EVENT_OPERATION_COMPLETE; block_media_ram_args.p_context = p_instance_ctrl->p_context; p_instance_ctrl->p_callback(&block_media_ram_args); } @@ -576,7 +577,7 @@ fsp_err_t RM_BLOCK_MEDIA_RAM_Read (rm_block_media_ctrl_t * const p_ctrl, if (NULL != p_instance_ctrl->p_callback) { - block_media_ram_args.event = RM_BLOCK_MEDIA_EVENT_OPERATION_COMPLETE; + block_media_ram_args.event = RM_BLOCK_MEDIA_EVENT_OPERATION_COMPLETE; block_media_ram_args.p_context = p_instance_ctrl->p_context; p_instance_ctrl->p_callback(&block_media_ram_args); } @@ -623,7 +624,7 @@ fsp_err_t RM_BLOCK_MEDIA_RAM_Write (rm_block_media_ctrl_t * const p_ctrl, if (NULL != p_instance_ctrl->p_callback) { - block_media_ram_args.event = RM_BLOCK_MEDIA_EVENT_OPERATION_COMPLETE; + block_media_ram_args.event = RM_BLOCK_MEDIA_EVENT_OPERATION_COMPLETE; block_media_ram_args.p_context = p_instance_ctrl->p_context; p_instance_ctrl->p_callback(&block_media_ram_args); } @@ -668,7 +669,7 @@ fsp_err_t RM_BLOCK_MEDIA_RAM_Erase (rm_block_media_ctrl_t * const p_ctrl, if (NULL != p_instance_ctrl->p_callback) { - block_media_ram_args.event = RM_BLOCK_MEDIA_EVENT_OPERATION_COMPLETE; + block_media_ram_args.event = RM_BLOCK_MEDIA_EVENT_OPERATION_COMPLETE; block_media_ram_args.p_context = p_instance_ctrl->p_context; p_instance_ctrl->p_callback(&block_media_ram_args); } @@ -725,7 +726,7 @@ fsp_err_t RM_BLOCK_MEDIA_RAM_InfoGet (rm_block_media_ctrl_t * const p_ctrl, rm_b #endif /* RM_BLOCK_MEDIA_RAM_CFG_PARAM_CHECKING_ENABLE */ p_info->sector_size_bytes = STRG_SECTSIZE; - p_info->num_sectors = (RM_BLOCK_MEIDA_RAM_CFG_MEDIA_SIZE / STRG_SECTSIZE); + p_info->num_sectors = (RM_BLOCK_MEDIA_RAM_CFG_MEDIA_SIZE / STRG_SECTSIZE); p_info->reentrant = false; p_info->write_protected = false; @@ -733,7 +734,7 @@ fsp_err_t RM_BLOCK_MEDIA_RAM_InfoGet (rm_block_media_ctrl_t * const p_ctrl, rm_b } /*******************************************************************************************************************//** - * Closes the module. + * Closes the module. * * Implements @ref rm_block_media_api_t::close(). * diff --git a/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz.c b/ra/fsp/src/rm_cellular_gm_aws/cellular_gm.c similarity index 95% rename from ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz.c rename to ra/fsp/src/rm_cellular_gm_aws/cellular_gm.c index c364962cc..a0e541d57 100644 --- a/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz.c +++ b/ra/fsp/src/rm_cellular_gm_aws/cellular_gm.c @@ -7,7 +7,7 @@ /*********************************************************************************************************************** * Includes **********************************************************************************************************************/ -#include "cellular_ryz.h" +#include "cellular_gm.h" #include "cellular_common.h" #include "cellular_common_portable.h" @@ -15,8 +15,8 @@ /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ -#define RM_CELLULAR_RYZ_ENABLE_MODULE_UE_RETRY_COUNT (3U) -#define RM_CELLULAR_RYZ_ENABLE_MODULE_UE_RETRY_TIMEOUT (5000U) +#define RM_CELLULAR_GM_ENABLE_MODULE_UE_RETRY_COUNT (3U) +#define RM_CELLULAR_GM_ENABLE_MODULE_UE_RETRY_TIMEOUT (5000U) /*********************************************************************************************************************** * Typedef definitions @@ -62,7 +62,7 @@ CellularError_t Cellular_ModuleInit (const CellularContext_t * pContext, void ** } else { - /* RYZ has no instance-specific module context. */ + /* GM has no instance-specific module context. */ *ppModuleContext = NULL; } @@ -178,11 +178,11 @@ static CellularError_t sendAtCommandWithRetryTimeout (CellularContext_t * pConte } else { - for ( ; tryCount < RM_CELLULAR_RYZ_ENABLE_MODULE_UE_RETRY_COUNT; tryCount++) + for ( ; tryCount < RM_CELLULAR_GM_ENABLE_MODULE_UE_RETRY_COUNT; tryCount++) { pktStatus = _Cellular_TimeoutAtcmdRequestWithCallback(pContext, *pAtReq, - RM_CELLULAR_RYZ_ENABLE_MODULE_UE_RETRY_TIMEOUT); + RM_CELLULAR_GM_ENABLE_MODULE_UE_RETRY_TIMEOUT); cellularStatus = _Cellular_TranslatePktStatus(pktStatus); if (cellularStatus == CELLULAR_SUCCESS) diff --git a/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz.h b/ra/fsp/src/rm_cellular_gm_aws/cellular_gm.h similarity index 64% rename from ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz.h rename to ra/fsp/src/rm_cellular_gm_aws/cellular_gm.h index 0fff64be1..ed321b9a4 100644 --- a/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz.h +++ b/ra/fsp/src/rm_cellular_gm_aws/cellular_gm.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef CELLULAR_RYZ_H -#define CELLULAR_RYZ_H +#ifndef CELLULAR_GM_H +#define CELLULAR_GM_H /*********************************************************************************************************************** * Includes @@ -23,19 +23,19 @@ FSP_HEADER /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ -#define RM_CELLULAR_RYZ_MAX_PDP_CONTEXTS (4U) // MAX valid PDP contexts -#define RM_CELLULAR_RYZ_DEFAULT_BEARER_CONTEXT_ID (1U) -#define RM_CELLULAR_RYZ_PDN_CONTEXT_TYPE_MAX_SIZE (7U) // The length of IP type e.g. IPV4V6 +#define RM_CELLULAR_GM_MAX_PDP_CONTEXTS (4U) // MAX valid PDP contexts +#define RM_CELLULAR_GM_DEFAULT_BEARER_CONTEXT_ID (1U) +#define RM_CELLULAR_GM_PDN_CONTEXT_TYPE_MAX_SIZE (7U) // The length of IP type e.g. IPV4V6 /* +CGDCONT PDN context definition tokens */ -#define RM_CELLULAR_RYZ_PDN_STATUS_POS_CONTEXT_ID (0U) -#define RM_CELLULAR_RYZ_PDN_STATUS_POS_CONTEXT_TYPE (1U) -#define RM_CELLULAR_RYZ_PDN_STATUS_POS_APN_NAME (2U) -#define RM_CELLULAR_RYZ_PDN_STATUS_POS_IP_ADDRESS (3U) +#define RM_CELLULAR_GM_PDN_STATUS_POS_CONTEXT_ID (0U) +#define RM_CELLULAR_GM_PDN_STATUS_POS_CONTEXT_TYPE (1U) +#define RM_CELLULAR_GM_PDN_STATUS_POS_APN_NAME (2U) +#define RM_CELLULAR_GM_PDN_STATUS_POS_IP_ADDRESS (3U) /* +CGACT PDN context activation tokens */ -#define RM_CELLULAR_RYZ_PDN_ACT_STATUS_POS_CONTEXT_ID (0U) -#define RM_CELLULAR_RYZ_PDN_ACT_STATUS_POS_CONTEXT_STATE (1U) +#define RM_CELLULAR_GM_PDN_ACT_STATUS_POS_CONTEXT_ID (0U) +#define RM_CELLULAR_GM_PDN_ACT_STATUS_POS_CONTEXT_STATE (1U) /********************************************************************************************************************** * Typedef definitions @@ -44,17 +44,17 @@ FSP_HEADER /* Context info from +CGDCONT (Context IP type, APN name, IP Address) */ typedef struct CellularPdnContextInfo { - bool contextsPresent[RM_CELLULAR_RYZ_MAX_PDP_CONTEXTS]; // Context present in +CGDCONT response or not. - char ipType[RM_CELLULAR_RYZ_MAX_PDP_CONTEXTS][RM_CELLULAR_RYZ_PDN_CONTEXT_TYPE_MAX_SIZE]; // PDN Context type. - char apnName[RM_CELLULAR_RYZ_MAX_PDP_CONTEXTS][CELLULAR_APN_MAX_SIZE]; // APN name. - char ipAddress[RM_CELLULAR_RYZ_MAX_PDP_CONTEXTS][CELLULAR_IP_ADDRESS_MAX_SIZE + 1]; // IP address. + bool contextsPresent[RM_CELLULAR_GM_MAX_PDP_CONTEXTS]; // Context present in +CGDCONT response or not. + char ipType[RM_CELLULAR_GM_MAX_PDP_CONTEXTS][RM_CELLULAR_GM_PDN_CONTEXT_TYPE_MAX_SIZE]; // PDN Context type. + char apnName[RM_CELLULAR_GM_MAX_PDP_CONTEXTS][CELLULAR_APN_MAX_SIZE]; // APN name. + char ipAddress[RM_CELLULAR_GM_MAX_PDP_CONTEXTS][CELLULAR_IP_ADDRESS_MAX_SIZE + 1]; // IP address. } CellularPdnContextInfo_t; /* Context Act state from +CGACT */ typedef struct CellularPdnContextActInfo { - bool contextsPresent[RM_CELLULAR_RYZ_MAX_PDP_CONTEXTS]; // Context present in +CGACT response or not. - bool contextActState[RM_CELLULAR_RYZ_MAX_PDP_CONTEXTS]; // Context active state from +CGACT response. + bool contextsPresent[RM_CELLULAR_GM_MAX_PDP_CONTEXTS]; // Context present in +CGACT response or not. + bool contextActState[RM_CELLULAR_GM_MAX_PDP_CONTEXTS]; // Context active state from +CGACT response. } CellularPdnContextActInfo_t; /********************************************************************************************************************** diff --git a/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz_api.c b/ra/fsp/src/rm_cellular_gm_aws/cellular_gm_api.c similarity index 95% rename from ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz_api.c rename to ra/fsp/src/rm_cellular_gm_aws/cellular_gm_api.c index caee46a4c..b9d1cafef 100644 --- a/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz_api.c +++ b/ra/fsp/src/rm_cellular_gm_aws/cellular_gm_api.c @@ -10,7 +10,7 @@ #include /* Cellular module includes. */ -#include "cellular_ryz.h" +#include "cellular_gm.h" /* Cellular includes. */ #include "cellular_types.h" @@ -23,44 +23,44 @@ /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ -#ifndef RM_CELLULAR_RYZ_PDN_ACT_PACKET_REQ_TIMEOUT_MS - #define RM_CELLULAR_RYZ_PDN_ACT_PACKET_REQ_TIMEOUT_MS (150000UL) +#ifndef RM_CELLULAR_GM_PDN_ACT_PACKET_REQ_TIMEOUT_MS + #define RM_CELLULAR_GM_PDN_ACT_PACKET_REQ_TIMEOUT_MS (150000UL) #endif -#ifndef RM_CELLULAR_RYZ_PDN_DEACT_PACKET_REQ_TIMEOUT_MS - #define RM_CELLULAR_RYZ_PDN_DEACT_PACKET_REQ_TIMEOUT_MS (40000UL) +#ifndef RM_CELLULAR_GM_PDN_DEACT_PACKET_REQ_TIMEOUT_MS + #define RM_CELLULAR_GM_PDN_DEACT_PACKET_REQ_TIMEOUT_MS (40000UL) #endif -#ifndef RM_CELLULAR_RYZ_GPRS_ATTACH_REQ_TIMEOUT_MS - #define RM_CELLULAR_RYZ_GPRS_ATTACH_REQ_TIMEOUT_MS (180000UL) +#ifndef RM_CELLULAR_GM_GPRS_ATTACH_REQ_TIMEOUT_MS + #define RM_CELLULAR_GM_GPRS_ATTACH_REQ_TIMEOUT_MS (180000UL) #endif -#ifndef RM_CELLULAR_RYZ_DNS_QUERY_REQ_TIMEOUT_MS - #define RM_CELLULAR_RYZ_DNS_QUERY_REQ_TIMEOUT_MS (120000UL) +#ifndef RM_CELLULAR_GM_DNS_QUERY_REQ_TIMEOUT_MS + #define RM_CELLULAR_GM_DNS_QUERY_REQ_TIMEOUT_MS (120000UL) #endif -#ifndef RM_CELLULAR_RYZ_SOCKET_CONNECT_PACKET_REQ_TIMEOUT_MS - #define RM_CELLULAR_RYZ_SOCKET_CONNECT_PACKET_REQ_TIMEOUT_MS (120000U) +#ifndef RM_CELLULAR_GM_SOCKET_CONNECT_PACKET_REQ_TIMEOUT_MS + #define RM_CELLULAR_GM_SOCKET_CONNECT_PACKET_REQ_TIMEOUT_MS (120000U) #endif -#ifndef RM_CELLULAR_RYZ_PACKET_REQ_TIMEOUT_MS - #define RM_CELLULAR_RYZ_PACKET_REQ_TIMEOUT_MS (10000U) +#ifndef RM_CELLULAR_GM_PACKET_REQ_TIMEOUT_MS + #define RM_CELLULAR_GM_PACKET_REQ_TIMEOUT_MS (10000U) #endif -#ifndef RM_CELLULAR_RYZ_DATA_SEND_TIMEOUT_MS - #define RM_CELLULAR_RYZ_DATA_SEND_TIMEOUT_MS (10000U) +#ifndef RM_CELLULAR_GM_DATA_SEND_TIMEOUT_MS + #define RM_CELLULAR_GM_DATA_SEND_TIMEOUT_MS (10000U) #endif -#ifndef RM_CELLULAR_RYZ_DATA_SEND_INTER_DELAY_MS - #define RM_CELLULAR_RYZ_DATA_SEND_INTER_DELAY_MS (200U) +#ifndef RM_CELLULAR_GM_DATA_SEND_INTER_DELAY_MS + #define RM_CELLULAR_GM_DATA_SEND_INTER_DELAY_MS (200U) #endif -#ifndef RM_CELLULAR_RYZ_DATA_READ_TIMEOUT_MS - #define RM_CELLULAR_RYZ_DATA_READ_TIMEOUT_MS (50000UL) +#ifndef RM_CELLULAR_GM_DATA_READ_TIMEOUT_MS + #define RM_CELLULAR_GM_DATA_READ_TIMEOUT_MS (50000UL) #endif -#ifndef RM_CELLULAR_RYZ_SOCKET_DISCONNECT_PACKET_REQ_TIMEOUT_MS - #define RM_CELLULAR_RYZ_SOCKET_DISCONNECT_PACKET_REQ_TIMEOUT_MS (12000UL) +#ifndef RM_CELLULAR_GM_SOCKET_DISCONNECT_PACKET_REQ_TIMEOUT_MS + #define RM_CELLULAR_GM_SOCKET_DISCONNECT_PACKET_REQ_TIMEOUT_MS (12000UL) #endif -#define RM_CELLULAR_RYZ_SOCKET_DATA_PREFIX_TOKEN "+SQNSRECV: " -#define RM_CELLULAR_RYZ_SOCKET_DATA_PREFIX_TOKEN_LEN (11U) -#define RM_CELLULAR_RYZ_SOCKET_DATA_PREFIX_STRING_LENGTH (SOCKET_DATA_PREFIX_TOKEN_LEN + 6U) -#define RM_CELLULAR_RYZ_MAX_SQNSSRECV_STRING_PREFIX_STRING (21U) // The max data prefix string is "+SQNSRECV: 1,1500\r\n" -#define RM_CELLULAR_RYZ_DATA_PREFIX_STRING_CHANGELINE_LENGTH (2U) // The length of the change line "\r\n". -#define RM_CELLULAR_RYZ_GET_MODEM_SOCKET_ID(socket_id) ((uint16_t) socket_id + 1) // Socket ID on modem starts at index 1 -#define RM_CELLULAR_RYZ_CRSM_HPLMN_RAT_LENGTH (9U) +#define RM_CELLULAR_GM_SOCKET_DATA_PREFIX_TOKEN "+SQNSRECV: " +#define RM_CELLULAR_GM_SOCKET_DATA_PREFIX_TOKEN_LEN (11U) +#define RM_CELLULAR_GM_SOCKET_DATA_PREFIX_STRING_LENGTH (SOCKET_DATA_PREFIX_TOKEN_LEN + 6U) +#define RM_CELLULAR_GM_MAX_SQNSSRECV_STRING_PREFIX_STRING (21U) // The max data prefix string is "+SQNSRECV: 1,1500\r\n" +#define RM_CELLULAR_GM_DATA_PREFIX_STRING_CHANGELINE_LENGTH (2U) // The length of the change line "\r\n". +#define RM_CELLULAR_GM_GET_MODEM_SOCKET_ID(socket_id) ((uint16_t) socket_id + 1) // Socket ID on modem starts at index 1 +#define RM_CELLULAR_GM_CRSM_HPLMN_RAT_LENGTH (9U) /*********************************************************************************************************************** * Typedef definitions @@ -333,7 +333,7 @@ CellularError_t Cellular_GetPdnStatus (CellularHandle_t cellularHandle, if (cellularStatus == CELLULAR_SUCCESS) { - for (uint8_t i = 0; i < RM_CELLULAR_RYZ_MAX_PDP_CONTEXTS; i++) + for (uint8_t i = 0; i < RM_CELLULAR_GM_MAX_PDP_CONTEXTS; i++) { if (*pNumStatus == numStatusBuffers) { @@ -430,7 +430,7 @@ CellularError_t Cellular_ActivatePdn (CellularHandle_t cellularHandle, uint8_t c (void) snprintf(cmdBuf, CELLULAR_AT_CMD_MAX_SIZE, "%s=1,%u", "AT+CGACT", contextId); pktStatus = _Cellular_TimeoutAtcmdRequestWithCallback(pContext, atReqActPdn, - RM_CELLULAR_RYZ_PDN_ACT_PACKET_REQ_TIMEOUT_MS); + RM_CELLULAR_GM_PDN_ACT_PACKET_REQ_TIMEOUT_MS); } if (pktStatus != CELLULAR_PKT_STATUS_OK) @@ -500,7 +500,7 @@ CellularError_t Cellular_DeactivatePdn (CellularHandle_t cellularHandle, uint8_t { /* Don't deactivate LTE default bearer context */ /* Otherwise sending AT command "+CGACT=0,1" for deactivation will result in ERROR */ - if ((serviceStatus.rat >= CELLULAR_RAT_LTE) && (contextId == RM_CELLULAR_RYZ_DEFAULT_BEARER_CONTEXT_ID)) + if ((serviceStatus.rat >= CELLULAR_RAT_LTE) && (contextId == RM_CELLULAR_GM_DEFAULT_BEARER_CONTEXT_ID)) { LogInfo(("Cellular_DeactivatePdn: Default Bearer context %d Active. Not allowed to deactivate.", contextId)); @@ -511,7 +511,7 @@ CellularError_t Cellular_DeactivatePdn (CellularHandle_t cellularHandle, uint8_t (void) snprintf(cmdBuf, CELLULAR_AT_CMD_MAX_SIZE, "%s=0,%u", "AT+CGACT", contextId); pktStatus = _Cellular_TimeoutAtcmdRequestWithCallback(pContext, atReqDeactPdn, - RM_CELLULAR_RYZ_PDN_DEACT_PACKET_REQ_TIMEOUT_MS); + RM_CELLULAR_GM_PDN_DEACT_PACKET_REQ_TIMEOUT_MS); cellularStatus = _Cellular_TranslatePktStatus(pktStatus); } @@ -530,7 +530,7 @@ CellularError_t Cellular_DeactivatePdn (CellularHandle_t cellularHandle, uint8_t (void) snprintf(cmdBuf, CELLULAR_AT_CMD_MAX_SIZE, "%s", "AT+CGATT=0"); pktStatus = _Cellular_TimeoutAtcmdRequestWithCallback(pContext, atReqDeactPdn, - RM_CELLULAR_RYZ_GPRS_ATTACH_REQ_TIMEOUT_MS); + RM_CELLULAR_GM_GPRS_ATTACH_REQ_TIMEOUT_MS); cellularStatus = _Cellular_TranslatePktStatus(pktStatus); } else if (cellularStatus != CELLULAR_SUCCESS) @@ -669,7 +669,7 @@ CellularError_t Cellular_GetHostByName (CellularHandle_t cellularHandle, pktStatus = _Cellular_TimeoutAtcmdRequestWithCallback(pContext, atReqQueryDns, - RM_CELLULAR_RYZ_DNS_QUERY_REQ_TIMEOUT_MS); + RM_CELLULAR_GM_DNS_QUERY_REQ_TIMEOUT_MS); if (pktStatus != CELLULAR_PKT_STATUS_OK) { @@ -754,20 +754,20 @@ CellularError_t Cellular_SocketConnect (CellularHandle_t cellular if (cellularStatus == CELLULAR_SUCCESS) { snprintf(cmdBuf, CELLULAR_AT_CMD_MAX_SIZE, "AT+SQNSCFG=%u,%d,0,90,600,50", - RM_CELLULAR_RYZ_GET_MODEM_SOCKET_ID(socketHandle->socketId), socketHandle->contextId); + RM_CELLULAR_GM_GET_MODEM_SOCKET_ID(socketHandle->socketId), socketHandle->contextId); pktStatus = _Cellular_TimeoutAtcmdRequestWithCallback(pContext, atReqSocketConnect, - RM_CELLULAR_RYZ_SOCKET_CONNECT_PACKET_REQ_TIMEOUT_MS); + RM_CELLULAR_GM_SOCKET_CONNECT_PACKET_REQ_TIMEOUT_MS); if (pktStatus == CELLULAR_PKT_STATUS_OK) { snprintf(cmdBuf, CELLULAR_AT_CMD_MAX_SIZE, "AT+SQNSCFGEXT=%u,0,0,0", - RM_CELLULAR_RYZ_GET_MODEM_SOCKET_ID(socketHandle->socketId)); + RM_CELLULAR_GM_GET_MODEM_SOCKET_ID(socketHandle->socketId)); pktStatus = _Cellular_TimeoutAtcmdRequestWithCallback(pContext, atReqSocketConnect, - RM_CELLULAR_RYZ_SOCKET_CONNECT_PACKET_REQ_TIMEOUT_MS); + RM_CELLULAR_GM_SOCKET_CONNECT_PACKET_REQ_TIMEOUT_MS); if (pktStatus != CELLULAR_PKT_STATUS_OK) { @@ -790,7 +790,7 @@ CellularError_t Cellular_SocketConnect (CellularHandle_t cellular snprintf(cmdBuf, CELLULAR_AT_CMD_MAX_SIZE, "AT+SQNSD=%u,%d,%d,\"%s\",0,%d,1,0", - RM_CELLULAR_RYZ_GET_MODEM_SOCKET_ID(socketHandle->socketId), + RM_CELLULAR_GM_GET_MODEM_SOCKET_ID(socketHandle->socketId), protocol, socketHandle->remoteSocketAddress.port, socketHandle->remoteSocketAddress.ipAddress.ipAddress, @@ -798,7 +798,7 @@ CellularError_t Cellular_SocketConnect (CellularHandle_t cellular pktStatus = _Cellular_TimeoutAtcmdRequestWithCallback(pContext, atReqSocketConnect, - RM_CELLULAR_RYZ_SOCKET_CONNECT_PACKET_REQ_TIMEOUT_MS); + RM_CELLULAR_GM_SOCKET_CONNECT_PACKET_REQ_TIMEOUT_MS); if (pktStatus != CELLULAR_PKT_STATUS_OK) { @@ -837,7 +837,7 @@ CellularError_t Cellular_SocketSend (CellularHandle_t cellularHandle, CellularContext_t * pContext = (CellularContext_t *) cellularHandle; CellularError_t cellularStatus = CELLULAR_SUCCESS; CellularPktStatus_t pktStatus = CELLULAR_PKT_STATUS_OK; - uint32_t sendTimeout = RM_CELLULAR_RYZ_DATA_SEND_TIMEOUT_MS; + uint32_t sendTimeout = RM_CELLULAR_GM_DATA_SEND_TIMEOUT_MS; char cmdBuf[CELLULAR_AT_CMD_MAX_SIZE] = {'\0'}; CellularAtReq_t atReqSocketSend = { @@ -901,16 +901,16 @@ CellularError_t Cellular_SocketSend (CellularHandle_t cellularHandle, } snprintf(cmdBuf, CELLULAR_AT_CMD_MAX_SIZE, "AT+SQNSSENDEXT=%u,%u", - RM_CELLULAR_RYZ_GET_MODEM_SOCKET_ID(socketHandle->socketId), (uint16_t) atDataReqSocketSend.dataLen); + RM_CELLULAR_GM_GET_MODEM_SOCKET_ID(socketHandle->socketId), (uint16_t) atDataReqSocketSend.dataLen); pktStatus = _Cellular_AtcmdDataSend(pContext, atReqSocketSend, atDataReqSocketSend, socketSendDataPrefix, NULL, - RM_CELLULAR_RYZ_PACKET_REQ_TIMEOUT_MS, + RM_CELLULAR_GM_PACKET_REQ_TIMEOUT_MS, sendTimeout, - RM_CELLULAR_RYZ_DATA_SEND_INTER_DELAY_MS); + RM_CELLULAR_GM_DATA_SEND_INTER_DELAY_MS); if (pktStatus != CELLULAR_PKT_STATUS_OK) { @@ -941,7 +941,7 @@ CellularError_t Cellular_SocketRecv (CellularHandle_t cellularHandle, CellularError_t cellularStatus = CELLULAR_SUCCESS; CellularPktStatus_t pktStatus = CELLULAR_PKT_STATUS_OK; char cmdBuf[CELLULAR_AT_CMD_MAX_SIZE] = {'\0'}; - uint32_t recvTimeout = RM_CELLULAR_RYZ_DATA_READ_TIMEOUT_MS; + uint32_t recvTimeout = RM_CELLULAR_GM_DATA_READ_TIMEOUT_MS; uint32_t recvLen = bufferLength; _socketDataRecv_t dataRecv = {0}; CellularAtReq_t atReqSocketRecv = @@ -989,7 +989,7 @@ CellularError_t Cellular_SocketRecv (CellularHandle_t cellularHandle, } snprintf(cmdBuf, CELLULAR_AT_CMD_MAX_SIZE, "AT+SQNSRECV=%u,%u", - RM_CELLULAR_RYZ_GET_MODEM_SOCKET_ID(socketHandle->socketId), (uint16_t) recvLen); + RM_CELLULAR_GM_GET_MODEM_SOCKET_ID(socketHandle->socketId), (uint16_t) recvLen); pktStatus = _Cellular_TimeoutAtcmdDataRecvRequestWithCallback(pContext, atReqSocketRecv, recvTimeout, @@ -1044,10 +1044,10 @@ CellularError_t Cellular_SocketClose (CellularHandle_t cellularHandle, CellularS { /* Form the AT command. */ snprintf(cmdBuf, CELLULAR_AT_CMD_MAX_SIZE, "AT+SQNSH=%u", - RM_CELLULAR_RYZ_GET_MODEM_SOCKET_ID(socketHandle->socketId)); + RM_CELLULAR_GM_GET_MODEM_SOCKET_ID(socketHandle->socketId)); pktStatus = _Cellular_TimeoutAtcmdRequestWithCallback(pContext, atReqSockClose, - RM_CELLULAR_RYZ_SOCKET_DISCONNECT_PACKET_REQ_TIMEOUT_MS); + RM_CELLULAR_GM_SOCKET_DISCONNECT_PACKET_REQ_TIMEOUT_MS); if (pktStatus != CELLULAR_PKT_STATUS_OK) { @@ -1544,7 +1544,7 @@ static CellularPktStatus_t _Cellular_RecvFuncGetPdpContextActState (CellularCont { switch (tokenIndex) { - case (RM_CELLULAR_RYZ_PDN_ACT_STATUS_POS_CONTEXT_ID): + case (RM_CELLULAR_GM_PDN_ACT_STATUS_POS_CONTEXT_ID): { LogDebug(("_Cellular_RecvFuncGetPdpContextActState: Context Id pToken: %s", pToken)); atCoreStatus = Cellular_ATStrtoi(pToken, 10, &tempValue); @@ -1552,7 +1552,7 @@ static CellularPktStatus_t _Cellular_RecvFuncGetPdpContextActState (CellularCont if (atCoreStatus == CELLULAR_AT_SUCCESS) { if ((tempValue >= (int32_t) CELLULAR_PDN_CONTEXT_ID_MIN) && - (tempValue <= (int32_t) RM_CELLULAR_RYZ_MAX_PDP_CONTEXTS)) + (tempValue <= (int32_t) RM_CELLULAR_GM_MAX_PDP_CONTEXTS)) { contextId = (uint8_t) tempValue; pPDPContextsActInfo->contextsPresent[contextId - 1] = true; @@ -1571,7 +1571,7 @@ static CellularPktStatus_t _Cellular_RecvFuncGetPdpContextActState (CellularCont break; } - case (RM_CELLULAR_RYZ_PDN_ACT_STATUS_POS_CONTEXT_STATE): + case (RM_CELLULAR_GM_PDN_ACT_STATUS_POS_CONTEXT_STATE): { LogDebug(("_Cellular_RecvFuncGetPdpContextActState: Context pToken: %s", pToken)); atCoreStatus = Cellular_ATStrtoi(pToken, 10, &tempValue); @@ -1643,7 +1643,7 @@ static CellularError_t _Cellular_GetPacketSwitchStatus (CellularHandle_t cellula /* Internal function. Callee check parameters. */ pktStatus = _Cellular_TimeoutAtcmdRequestWithCallback(pContext, atReqPacketSwitchStatus, - RM_CELLULAR_RYZ_PDN_ACT_PACKET_REQ_TIMEOUT_MS); + RM_CELLULAR_GM_PDN_ACT_PACKET_REQ_TIMEOUT_MS); cellularStatus = _Cellular_TranslatePktStatus(pktStatus); return cellularStatus; @@ -1805,7 +1805,7 @@ static CellularPktStatus_t _Cellular_RecvFuncGetPdpContextSettings (CellularCont { switch (tokenIndex) { - case (RM_CELLULAR_RYZ_PDN_STATUS_POS_CONTEXT_ID): + case (RM_CELLULAR_GM_PDN_STATUS_POS_CONTEXT_ID): { LogDebug(("_Cellular_RecvFuncGetPdpContextSettings: Context Id pToken: %s", pToken)); atCoreStatus = Cellular_ATStrtoi(pToken, 10, &tempValue); @@ -1813,7 +1813,7 @@ static CellularPktStatus_t _Cellular_RecvFuncGetPdpContextSettings (CellularCont if (atCoreStatus == CELLULAR_AT_SUCCESS) { if ((tempValue >= (int32_t) CELLULAR_PDN_CONTEXT_ID_MIN) && - (tempValue <= (int32_t) RM_CELLULAR_RYZ_MAX_PDP_CONTEXTS)) + (tempValue <= (int32_t) RM_CELLULAR_GM_MAX_PDP_CONTEXTS)) { contextId = (uint8_t) tempValue; pPDPContextsInfo->contextsPresent[contextId - 1] = true; @@ -1832,17 +1832,17 @@ static CellularPktStatus_t _Cellular_RecvFuncGetPdpContextSettings (CellularCont break; } - case (RM_CELLULAR_RYZ_PDN_STATUS_POS_CONTEXT_TYPE): + case (RM_CELLULAR_GM_PDN_STATUS_POS_CONTEXT_TYPE): { LogDebug(("_Cellular_RecvFuncGetPdpContextSettings: Context Type pToken: %s", pToken)); (void) memcpy((void *) pPDPContextsInfo->ipType[contextId - 1], (void *) pToken, - RM_CELLULAR_RYZ_PDN_CONTEXT_TYPE_MAX_SIZE); + RM_CELLULAR_GM_PDN_CONTEXT_TYPE_MAX_SIZE); break; } - case (RM_CELLULAR_RYZ_PDN_STATUS_POS_APN_NAME): + case (RM_CELLULAR_GM_PDN_STATUS_POS_APN_NAME): { LogDebug(("_Cellular_RecvFuncGetPdpContextSettings: Context APN name pToken: %s", pToken)); @@ -1853,7 +1853,7 @@ static CellularPktStatus_t _Cellular_RecvFuncGetPdpContextSettings (CellularCont break; } - case (RM_CELLULAR_RYZ_PDN_STATUS_POS_IP_ADDRESS): + case (RM_CELLULAR_GM_PDN_STATUS_POS_IP_ADDRESS): { LogDebug(("_Cellular_RecvFuncGetPdpContextSettings: Context IP address pToken: %s", pToken)); @@ -2343,8 +2343,8 @@ static CellularPktStatus_t _Cellular_RecvFuncData (CellularContext_t pInputLine = pAtResp->pItm->pLine; /* The first item is the data prefix. */ /* Check the data prefix token "+SQNSRECV: ". */ - if (strncmp(pInputLine, RM_CELLULAR_RYZ_SOCKET_DATA_PREFIX_TOKEN, - RM_CELLULAR_RYZ_SOCKET_DATA_PREFIX_TOKEN_LEN) != 0) + if (strncmp(pInputLine, RM_CELLULAR_GM_SOCKET_DATA_PREFIX_TOKEN, + RM_CELLULAR_GM_SOCKET_DATA_PREFIX_TOKEN_LEN) != 0) { LogError(("response item error in prefix")); atCoreStatus = CELLULAR_AT_ERROR; @@ -2444,9 +2444,9 @@ static CellularPktStatus_t socketRecvDataPrefix (void * pCallbackContext, CellularATError_t atResult = CELLULAR_AT_SUCCESS; CellularPktStatus_t pktStatus = CELLULAR_PKT_STATUS_OK; uint32_t i = 0; - char pLocalLine[RM_CELLULAR_RYZ_MAX_SQNSSRECV_STRING_PREFIX_STRING + 1] = "\0"; - uint32_t localLineLength = RM_CELLULAR_RYZ_MAX_SQNSSRECV_STRING_PREFIX_STRING > - lineLength ? lineLength : RM_CELLULAR_RYZ_MAX_SQNSSRECV_STRING_PREFIX_STRING; + char pLocalLine[RM_CELLULAR_GM_MAX_SQNSSRECV_STRING_PREFIX_STRING + 1] = "\0"; + uint32_t localLineLength = RM_CELLULAR_GM_MAX_SQNSSRECV_STRING_PREFIX_STRING > + lineLength ? lineLength : RM_CELLULAR_GM_MAX_SQNSSRECV_STRING_PREFIX_STRING; (void) pCallbackContext; @@ -2457,10 +2457,10 @@ static CellularPktStatus_t socketRecvDataPrefix (void * pCallbackContext, else { /* Check if the message is a data response. */ - if (strncmp(pLine, RM_CELLULAR_RYZ_SOCKET_DATA_PREFIX_TOKEN, RM_CELLULAR_RYZ_SOCKET_DATA_PREFIX_TOKEN_LEN) == 0) + if (strncmp(pLine, RM_CELLULAR_GM_SOCKET_DATA_PREFIX_TOKEN, RM_CELLULAR_GM_SOCKET_DATA_PREFIX_TOKEN_LEN) == 0) { - strncpy(pLocalLine, pLine, RM_CELLULAR_RYZ_MAX_SQNSSRECV_STRING_PREFIX_STRING); - pLocalLine[RM_CELLULAR_RYZ_MAX_SQNSSRECV_STRING_PREFIX_STRING] = '\0'; + strncpy(pLocalLine, pLine, RM_CELLULAR_GM_MAX_SQNSSRECV_STRING_PREFIX_STRING); + pLocalLine[RM_CELLULAR_GM_MAX_SQNSSRECV_STRING_PREFIX_STRING] = '\0'; pDataStart = pLocalLine; /* Add a '\0' char at the end of the line. */ @@ -2488,7 +2488,7 @@ static CellularPktStatus_t socketRecvDataPrefix (void * pCallbackContext, if ((atResult == CELLULAR_AT_SUCCESS) && (tempValue >= 0) && (tempValue <= (int32_t) CELLULAR_MAX_RECV_DATA_LEN)) { - if ((prefixLineLength + RM_CELLULAR_RYZ_DATA_PREFIX_STRING_CHANGELINE_LENGTH) > lineLength) + if ((prefixLineLength + RM_CELLULAR_GM_DATA_PREFIX_STRING_CHANGELINE_LENGTH) > lineLength) { /* More data is required. */ *pDataLength = 0; @@ -2499,7 +2499,7 @@ static CellularPktStatus_t socketRecvDataPrefix (void * pCallbackContext, { pDataStart = &pLine[prefixLineLength]; pDataStart[0] = '\0'; - pDataStart = &pDataStart[RM_CELLULAR_RYZ_DATA_PREFIX_STRING_CHANGELINE_LENGTH]; + pDataStart = &pDataStart[RM_CELLULAR_GM_DATA_PREFIX_STRING_CHANGELINE_LENGTH]; *pDataLength = (uint32_t) tempValue; } @@ -2583,7 +2583,7 @@ static bool _parseHplmn (char * pToken, void * pData) LogError(("_parseHplmn: pToken is NULL or pData is NULL")); parseStatus = false; } - else if (strlen(pToken) < (RM_CELLULAR_RYZ_CRSM_HPLMN_RAT_LENGTH)) + else if (strlen(pToken) < (RM_CELLULAR_GM_CRSM_HPLMN_RAT_LENGTH)) { LogError(("_parseHplmn: Error in processing HPLMN invalid token %s", pToken)); parseStatus = false; diff --git a/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz_urc_handler.c b/ra/fsp/src/rm_cellular_gm_aws/cellular_gm_urc_handler.c similarity index 73% rename from ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz_urc_handler.c rename to ra/fsp/src/rm_cellular_gm_aws/cellular_gm_urc_handler.c index 16ef0801f..2cfa9ce7f 100644 --- a/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz_urc_handler.c +++ b/ra/fsp/src/rm_cellular_gm_aws/cellular_gm_urc_handler.c @@ -9,7 +9,7 @@ **********************************************************************************************************************/ /* Cellular module includes. */ -#include "cellular_ryz.h" +#include "cellular_gm.h" #include "cellular_types.h" #include "cellular_common.h" @@ -27,13 +27,13 @@ /*********************************************************************************************************************** * Private function prototypes **********************************************************************************************************************/ -static void cellular_ryz_urc_process_sqnsring(CellularContext_t * pContext, char * pInputLine); -static void cellular_ryz_urc_process_sysstart(CellularContext_t * pContext, char * pInputLine); -static void cellular_ryz_urc_process_shutdown(CellularContext_t * pContext, char * pInputLine); -static void cellular_ryz_urc_process_socket_shutdown(CellularContext_t * pContext, char * pInputLine); +static void cellular_gm_urc_process_sqnsring(CellularContext_t * pContext, char * pInputLine); +static void cellular_gm_urc_process_sysstart(CellularContext_t * pContext, char * pInputLine); +static void cellular_gm_urc_process_shutdown(CellularContext_t * pContext, char * pInputLine); +static void cellular_gm_urc_process_socket_shutdown(CellularContext_t * pContext, char * pInputLine); /* Remapping these common functions because function pointer in CellularAtParseTokenMap_t doesn't match */ -static void cellular_ryz_urc_process_cereg(CellularContext_t * pContext, char * pInputLine); +static void cellular_gm_urc_process_cereg(CellularContext_t * pContext, char * pInputLine); /*********************************************************************************************************************** * Private global variables @@ -63,11 +63,11 @@ static void cellular_ryz_urc_process_cereg(CellularContext_t * pContext, char * */ CellularAtParseTokenMap_t cellular_urc_handler_table[] = { - {"CEREG", cellular_ryz_urc_process_cereg }, - {"SHUTDOWN", cellular_ryz_urc_process_shutdown }, // Power down completed, safe to turn cut power supply - {"SQNSH", cellular_ryz_urc_process_socket_shutdown}, // Socket closed - {"SQNSRING", cellular_ryz_urc_process_sqnsring }, // Socket notification (receive) - {"SYSSTART", cellular_ryz_urc_process_sysstart }, // System start/restarted notification + {"CEREG", cellular_gm_urc_process_cereg }, + {"SHUTDOWN", cellular_gm_urc_process_shutdown }, // Power down completed, safe to turn cut power supply + {"SQNSH", cellular_gm_urc_process_socket_shutdown}, // Socket closed + {"SQNSRING", cellular_gm_urc_process_sqnsring }, // Socket notification (receive) + {"SYSSTART", cellular_gm_urc_process_sysstart }, // System start/restarted notification }; uint32_t cellular_urc_handler_table_size = sizeof(cellular_urc_handler_table) / sizeof(CellularAtParseTokenMap_t); @@ -76,7 +76,7 @@ uint32_t cellular_urc_handler_table_size = sizeof(cellular_urc_handler_table) / * Functions **********************************************************************************************************************/ -static void cellular_ryz_urc_process_sqnsring (CellularContext_t * pContext, char * pInputLine) +static void cellular_gm_urc_process_sqnsring (CellularContext_t * pContext, char * pInputLine) { CellularATError_t atCoreStatus = CELLULAR_AT_SUCCESS; char * pLocalInputLine = pInputLine; @@ -101,7 +101,7 @@ static void cellular_ryz_urc_process_sqnsring (CellularContext_t * pContext, cha if (pSocketData == NULL) { - LogError(("cellular_ryz_urc_process_socket_shutdown : invalid socket index %d", (int) socketId - 1)); + LogError(("cellular_gm_urc_process_socket_shutdown : invalid socket index %d", (int) socketId - 1)); } else { @@ -112,14 +112,14 @@ static void cellular_ryz_urc_process_sqnsring (CellularContext_t * pContext, cha } else { - LogDebug(("cellular_ryz_urc_process_socket_shutdown: Data ready callback not set!!")); + LogDebug(("cellular_gm_urc_process_socket_shutdown: Data ready callback not set!!")); } } } } } -static void cellular_ryz_urc_process_socket_shutdown (CellularContext_t * pContext, char * pInputLine) +static void cellular_gm_urc_process_socket_shutdown (CellularContext_t * pContext, char * pInputLine) { CellularATError_t atCoreStatus = CELLULAR_AT_SUCCESS; char * pLocalInputLine = pInputLine; @@ -144,7 +144,7 @@ static void cellular_ryz_urc_process_socket_shutdown (CellularContext_t * pConte if (pSocketData == NULL) { - LogError(("cellular_ryz_urc_process_socket_shutdown : invalid socket index %d", (int) socketId - 1)); + LogError(("cellular_gm_urc_process_socket_shutdown : invalid socket index %d", (int) socketId - 1)); } else { @@ -155,46 +155,46 @@ static void cellular_ryz_urc_process_socket_shutdown (CellularContext_t * pConte } else { - LogDebug(("cellular_ryz_urc_process_socket_shutdown: socket close callback not set!!")); + LogDebug(("cellular_gm_urc_process_socket_shutdown: socket close callback not set!!")); } } } } } -static void cellular_ryz_urc_process_sysstart (CellularContext_t * pContext, char * pInputLine) +static void cellular_gm_urc_process_sysstart (CellularContext_t * pContext, char * pInputLine) { /* The token is the pInputLine. No need to process the pInputLine. */ FSP_PARAMETER_NOT_USED(pInputLine); if (pContext == NULL) { - LogWarn(("cellular_ryz_urc_process_sysstart: Context not set")); + LogWarn(("cellular_gm_urc_process_sysstart: Context not set")); } else { - LogDebug(("cellular_ryz_urc_process_sysstart: Modem Ready event received")); + LogDebug(("cellular_gm_urc_process_sysstart: Modem Ready event received")); _Cellular_ModemEventCallback(pContext, CELLULAR_MODEM_EVENT_BOOTUP_OR_REBOOT); } } -static void cellular_ryz_urc_process_shutdown (CellularContext_t * pContext, char * pInputLine) +static void cellular_gm_urc_process_shutdown (CellularContext_t * pContext, char * pInputLine) { /* The token is the pInputLine. No need to process the pInputLine. */ FSP_PARAMETER_NOT_USED(pInputLine); if (pContext == NULL) { - LogWarn(("cellular_ryz_urc_process_sqnsshdn: Context not set")); + LogWarn(("cellular_gm_urc_process_sqnsshdn: Context not set")); } else { - LogDebug(("cellular_ryz_urc_process_sqnsshdn: Modem Shutdown event received")); + LogDebug(("cellular_gm_urc_process_sqnsshdn: Modem Shutdown event received")); _Cellular_ModemEventCallback(pContext, CELLULAR_MODEM_EVENT_POWERED_DOWN); } } -static void cellular_ryz_urc_process_cereg (CellularContext_t * pContext, char * pInputLine) +static void cellular_gm_urc_process_cereg (CellularContext_t * pContext, char * pInputLine) { Cellular_CommonUrcProcessCereg(pContext, pInputLine); } diff --git a/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz_wrapper.c b/ra/fsp/src/rm_cellular_gm_aws/cellular_gm_wrapper.c similarity index 99% rename from ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz_wrapper.c rename to ra/fsp/src/rm_cellular_gm_aws/cellular_gm_wrapper.c index 54e232687..16ba5c6e7 100644 --- a/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz_wrapper.c +++ b/ra/fsp/src/rm_cellular_gm_aws/cellular_gm_wrapper.c @@ -13,7 +13,7 @@ #include "cellular_common_api.h" /* Cellular module includes. */ -#include "cellular_ryz.h" +#include "cellular_gm.h" /*********************************************************************************************************************** * Macro definitions diff --git a/ra/fsp/src/rm_comms_smbus/rm_comms_smbus.c b/ra/fsp/src/rm_comms_smbus/rm_comms_smbus.c index 686549e7c..b6a76264d 100644 --- a/ra/fsp/src/rm_comms_smbus/rm_comms_smbus.c +++ b/ra/fsp/src/rm_comms_smbus/rm_comms_smbus.c @@ -663,6 +663,7 @@ void rm_comms_smbus_transmission_callback (i2c_master_callback_args_t * p_args) (rm_comms_smbus_instance_ctrl_t *) (p_comms_i2c_ctrl->p_context); rm_comms_callback_args_t comms_smbus_args; + rm_comms_smbus_error_t smbus_error; bool transition_complete_flag = false; /* Initialize the event */ @@ -671,6 +672,9 @@ void rm_comms_smbus_transmission_callback (i2c_master_callback_args_t * p_args) /* Set context */ comms_smbus_args.p_context = p_ctrl->p_context; + /* Initialize the error block */ + smbus_error.smbus_event = RM_COMMS_SMBUS_NO_ERROR; + /* Set event */ switch (p_args->event) { @@ -716,7 +720,8 @@ void rm_comms_smbus_transmission_callback (i2c_master_callback_args_t * p_args) /* Compare PEC byte and return event */ if (ref_pec != data_pec) { - comms_smbus_args.event = RM_COMMS_EVENT_ERROR; + comms_smbus_args.event = RM_COMMS_EVENT_ERROR; + smbus_error.smbus_event = RM_COMMS_SMBUS_DATA_CORRUPT; } } @@ -748,6 +753,7 @@ void rm_comms_smbus_transmission_callback (i2c_master_callback_args_t * p_args) { transition_complete_flag = true; comms_smbus_args.event = RM_COMMS_EVENT_ERROR; + smbus_error.smbus_event = RM_COMMS_SMBUS_MISC_ERROR; } else { @@ -764,6 +770,7 @@ void rm_comms_smbus_transmission_callback (i2c_master_callback_args_t * p_args) { transition_complete_flag = true; comms_smbus_args.event = RM_COMMS_EVENT_ERROR; + smbus_error.smbus_event = RM_COMMS_SMBUS_MISC_ERROR; } else { @@ -786,6 +793,7 @@ void rm_comms_smbus_transmission_callback (i2c_master_callback_args_t * p_args) { transition_complete_flag = true; comms_smbus_args.event = RM_COMMS_EVENT_ERROR; + smbus_error.smbus_event = RM_COMMS_SMBUS_MISC_ERROR; } break; @@ -799,6 +807,7 @@ void rm_comms_smbus_transmission_callback (i2c_master_callback_args_t * p_args) { transition_complete_flag = true; comms_smbus_args.event = RM_COMMS_EVENT_ERROR; + smbus_error.smbus_event = RM_COMMS_SMBUS_MISC_ERROR; } break; @@ -825,7 +834,8 @@ void rm_comms_smbus_transmission_callback (i2c_master_callback_args_t * p_args) transition_complete_flag = true; /* Update the event which returned to user's callback */ - comms_smbus_args.event = RM_COMMS_EVENT_ERROR; + comms_smbus_args.event = RM_COMMS_EVENT_ERROR; + smbus_error.smbus_event = RM_COMMS_SMBUS_MISC_ERROR; break; } @@ -838,6 +848,9 @@ void rm_comms_smbus_transmission_callback (i2c_master_callback_args_t * p_args) if (transition_complete_flag) { + /* Assign error control block of current context to callback args */ + comms_smbus_args.p_instance_args = &smbus_error; + rm_comms_i2c_process_in_callback(p_comms_i2c_ctrl, &comms_smbus_args); } } @@ -852,10 +865,12 @@ void rm_comms_smbus_timeout_callback (timer_callback_args_t * p_args) rm_comms_i2c_instance_ctrl_t * p_comms_i2c = p_ctrl->p_comms_i2c_ctrl; rm_comms_callback_args_t comms_smbus_args; + rm_comms_smbus_error_t smbus_error; /* Set context and return event */ comms_smbus_args.p_context = p_comms_i2c->p_context; comms_smbus_args.event = RM_COMMS_EVENT_ERROR; + smbus_error.smbus_event = RM_COMMS_SMBUS_NO_ERROR; i2c_master_instance_t const * p_iic_instance = p_comms_i2c->p_bus->p_driver_instance; @@ -867,8 +882,22 @@ void rm_comms_smbus_timeout_callback (timer_callback_args_t * p_args) { timer_instance_t * p_timer_instance = (timer_instance_t *) p_comms_i2c->p_bus->p_timer; + smbus_error.smbus_event = RM_COMMS_SMBUS_MEXT_TIMEOUT; p_timer_instance->p_api->stop(p_timer_instance->p_ctrl); } + else if (TIMER_EVENT_CYCLE_END == p_args->event) + { + smbus_error.smbus_event = RM_COMMS_SMBUS_SEXT_TIMEOUT; + } + else + { + /* Remain events of timer will be treated as miscellaneous error to SMBus because they're not expected + * to be raised. */ + smbus_error.smbus_event = RM_COMMS_SMBUS_MISC_ERROR; + } + + /* Assign error control block of current context to callback args */ + comms_smbus_args.p_instance_args = &smbus_error; rm_comms_i2c_process_in_callback(p_comms_i2c, &comms_smbus_args); } diff --git a/ra/fsp/src/rm_freertos_plus_tcp/NetworkInterface.c b/ra/fsp/src/rm_freertos_plus_tcp/NetworkInterface.c index 2212be9e9..5e3c16caf 100644 --- a/ra/fsp/src/rm_freertos_plus_tcp/NetworkInterface.c +++ b/ra/fsp/src/rm_freertos_plus_tcp/NetworkInterface.c @@ -38,7 +38,7 @@ #include "NetworkBufferManagement.h" /* Renesas includes. */ -#include "r_ether.h" +#include "r_ether_api.h" /*********************************************************************************************************************** * Macro definitions diff --git a/ra/fsp/src/rm_littlefs_flash/rm_littlefs_flash.c b/ra/fsp/src/rm_littlefs_flash/rm_littlefs_flash.c index 041cbc22a..e284c6005 100644 --- a/ra/fsp/src/rm_littlefs_flash/rm_littlefs_flash.c +++ b/ra/fsp/src/rm_littlefs_flash/rm_littlefs_flash.c @@ -92,7 +92,7 @@ fsp_err_t RM_LITTLEFS_FLASH_Open (rm_littlefs_ctrl_t * const p_ctrl, rm_littlefs fsp_err_t err = p_flash->p_api->open(p_flash->p_ctrl, p_flash->p_cfg); FSP_ERROR_RETURN(FSP_SUCCESS == err, err); -#if LFS_THREAD_SAFE +#ifdef LFS_THREADSAFE p_instance_ctrl->xSemaphore = xSemaphoreCreateMutexStatic(&p_instance_ctrl->xMutexBuffer); if (NULL == p_instance_ctrl->xSemaphore) @@ -137,7 +137,7 @@ fsp_err_t RM_LITTLEFS_FLASH_Close (rm_littlefs_ctrl_t * const p_ctrl) p_flash->p_api->close(p_extend->p_flash->p_ctrl); -#if LFS_THREAD_SAFE +#ifdef LFS_THREADSAFE vSemaphoreDelete(p_instance_ctrl->xSemaphore); #endif @@ -257,7 +257,7 @@ int rm_littlefs_flash_erase (const struct lfs_config * c, lfs_block_t block) **********************************************************************************************************************/ int rm_littlefs_flash_lock (const struct lfs_config * c) { -#if LFS_THREAD_SAFE +#ifdef LFS_THREADSAFE rm_littlefs_flash_instance_ctrl_t * p_instance_ctrl = (rm_littlefs_flash_instance_ctrl_t *) c->context; #if RM_LITTLEFS_FLASH_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(NULL != p_instance_ctrl); @@ -283,7 +283,7 @@ int rm_littlefs_flash_lock (const struct lfs_config * c) **********************************************************************************************************************/ int rm_littlefs_flash_unlock (const struct lfs_config * c) { -#if LFS_THREAD_SAFE +#ifdef LFS_THREADSAFE rm_littlefs_flash_instance_ctrl_t * p_instance_ctrl = (rm_littlefs_flash_instance_ctrl_t *) c->context; #if RM_LITTLEFS_FLASH_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(NULL != p_instance_ctrl); diff --git a/ra/fsp/src/rm_littlefs_spi_flash/rm_littlefs_spi_flash.c b/ra/fsp/src/rm_littlefs_spi_flash/rm_littlefs_spi_flash.c new file mode 100644 index 000000000..341beef9a --- /dev/null +++ b/ra/fsp/src/rm_littlefs_spi_flash/rm_littlefs_spi_flash.c @@ -0,0 +1,382 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/* FSP includes. */ +#include "rm_littlefs_spi_flash.h" +#include "rm_littlefs_spi_flash_cfg.h" + +#define RM_LITTLEFS_SPI_FLASH_MINIMUM_BLOCK_SIZE (104) + +#ifndef RM_LITTLEFS_SPI_FLASH_SEMAPHORE_TIMEOUT + #define RM_LITTLEFS_SPI_FLASH_SEMAPHORE_TIMEOUT UINT32_MAX +#endif + +/** "RLFS" in ASCII, used to determine if channel is open. */ +#define RM_LITTLEFS_SPI_FLASH_OPEN (0x524C4653ULL) + +#define RM_LITTLEFS_SPI_BYTES_PER_WORD (4U) +#define RM_LITTLEFS_SPI_FLASH_CLEARED (0xFF) + +/** LittleFS API mapping for LittleFS Port interface */ +const rm_littlefs_api_t g_rm_littlefs_on_flash = +{ + .open = RM_LITTLEFS_SPI_FLASH_Open, + .close = RM_LITTLEFS_SPI_FLASH_Close, +}; + +static fsp_err_t rm_littlefs_spi_flash_wait_write_erase_complete(rm_littlefs_spi_flash_instance_ctrl_t * const p_ctrl); + +/*******************************************************************************************************************//** + * @addtogroup RM_LITTLEFS_SPI_FLASH + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Opens the driver and initializes lower layer driver. + * + * Implements @ref rm_littlefs_api_t::open(). + * + * @retval FSP_SUCCESS Success. + * @retval FSP_ERR_ASSERTION An input parameter was invalid. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + * @retval FSP_ERR_INVALID_SIZE The provided block size is invalid. + * @retval FSP_ERR_INVALID_ARGUMENT Flash BGO mode must be disabled. + * @retval FSP_ERR_INTERNAL Failed to create the semaphore. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This + * function calls: + * * @ref spi_flash_api_t::open + **********************************************************************************************************************/ +fsp_err_t RM_LITTLEFS_SPI_FLASH_Open (rm_littlefs_ctrl_t * const p_ctrl, rm_littlefs_cfg_t const * const p_cfg) +{ + rm_littlefs_spi_flash_instance_ctrl_t * p_instance_ctrl = (rm_littlefs_spi_flash_instance_ctrl_t *) p_ctrl; + +#if RM_LITTLEFS_SPI_FLASH_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_lfs_cfg); + FSP_ASSERT(NULL != p_cfg->p_extend); + + rm_littlefs_spi_flash_cfg_t const * p_extend = (rm_littlefs_spi_flash_cfg_t *) p_cfg->p_extend; + FSP_ASSERT(NULL != p_extend->p_lower_lvl); + + FSP_ERROR_RETURN(RM_LITTLEFS_SPI_FLASH_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); + FSP_ERROR_RETURN(p_cfg->p_lfs_cfg->block_size >= RM_LITTLEFS_SPI_FLASH_MINIMUM_BLOCK_SIZE, FSP_ERR_INVALID_SIZE); + + spi_flash_instance_t const * p_lower_lvl = p_extend->p_lower_lvl; + FSP_ERROR_RETURN((p_cfg->p_lfs_cfg->block_size % p_lower_lvl->p_cfg->p_erase_command_list[0].size) == 0, + FSP_ERR_INVALID_SIZE); +#else + rm_littlefs_spi_flash_cfg_t const * p_extend = (rm_littlefs_spi_flash_cfg_t *) p_cfg->p_extend; + spi_flash_instance_t const * p_lower_lvl = p_extend->p_lower_lvl; +#endif + + p_instance_ctrl->p_cfg = p_cfg; + p_instance_ctrl->start_address = p_extend->base_address + p_extend->address_offset; + p_instance_ctrl->size = p_cfg->p_lfs_cfg->block_count * p_cfg->p_lfs_cfg->block_size; + + /* Open the underlying driver. */ + fsp_err_t err = p_lower_lvl->p_api->open(p_lower_lvl->p_ctrl, p_lower_lvl->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + +#ifdef LFS_THREADSAFE + p_instance_ctrl->xSemaphore = xSemaphoreCreateMutexStatic(&p_instance_ctrl->xMutexBuffer); + + if (NULL == p_instance_ctrl->xSemaphore) + { + p_lower_lvl->p_api->close(p_lower_lvl->p_ctrl); + + return FSP_ERR_INTERNAL; + } +#endif + + /* This module is now open. */ + p_instance_ctrl->open = RM_LITTLEFS_SPI_FLASH_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Closes the lower level driver. + * + * Implements @ref rm_littlefs_api_t::close(). + * + * @retval FSP_SUCCESS Media device closed. + * @retval FSP_ERR_ASSERTION An input parameter was invalid. + * @retval FSP_ERR_NOT_OPEN Module not open. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. + * This function calls: + * * @ref spi_flash_api_t::close + **********************************************************************************************************************/ +fsp_err_t RM_LITTLEFS_SPI_FLASH_Close (rm_littlefs_ctrl_t * const p_ctrl) +{ + rm_littlefs_spi_flash_instance_ctrl_t * p_instance_ctrl = (rm_littlefs_spi_flash_instance_ctrl_t *) p_ctrl; +#if RM_LITTLEFS_SPI_FLASH_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(RM_LITTLEFS_SPI_FLASH_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_instance_ctrl->open = 0; + + rm_littlefs_spi_flash_cfg_t const * p_extend = (rm_littlefs_spi_flash_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + spi_flash_instance_t const * p_lower_lvl = p_extend->p_lower_lvl; + + p_lower_lvl->p_api->close(p_extend->p_lower_lvl->p_ctrl); + +#ifdef LFS_THREADSAFE + vSemaphoreDelete(p_instance_ctrl->xSemaphore); +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup RM_LITTLEFS_SPI_FLASH) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Read from the flash driver. Negative error codes are propogated to the user. + * + * @param[in] c Pointer to the LittleFS config block. + * @param[in] block The block number + * @param[in] off Offset in bytes + * @param[out] buffer The buffer to copy data into + * @param[in] size The size in bytes + * + * @retval LFS_ERR_OK Read is complete. + * @retval LFS_ERR_IO Lower level driver is not open. + **********************************************************************************************************************/ +int rm_littlefs_spi_flash_read (const struct lfs_config * c, + lfs_block_t block, + lfs_off_t off, + void * buffer, + lfs_size_t size) +{ + rm_littlefs_spi_flash_instance_ctrl_t * p_instance_ctrl = (rm_littlefs_spi_flash_instance_ctrl_t *) c->context; +#if RM_LITTLEFS_SPI_FLASH_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(RM_LITTLEFS_SPI_FLASH_OPEN == p_instance_ctrl->open, LFS_ERR_IO); +#endif + + /* Read directly from the flash. */ + memcpy(buffer, + (uint8_t *) (p_instance_ctrl->start_address + (p_instance_ctrl->p_cfg->p_lfs_cfg->block_size * block) + off), + size); + + return LFS_ERR_OK; +} + +/*******************************************************************************************************************//** + * Writes requested bytes to flash. + * + * @param[in] c Pointer to the LittleFS config block. + * @param[in] block The block number + * @param[in] off Offset in bytes + * @param[in] buffer The buffer containing data to be written. + * @param[in] size The size in bytes + * + * @retval LFS_ERR_OK Success. + * @retval LFS_ERR_IO Lower layer is not open or failed to write the flash. + **********************************************************************************************************************/ +int rm_littlefs_spi_flash_write (const struct lfs_config * c, + lfs_block_t block, + lfs_off_t off, + const void * buffer, + lfs_size_t size) +{ + rm_littlefs_spi_flash_instance_ctrl_t * p_ctrl = (rm_littlefs_spi_flash_instance_ctrl_t *) c->context; + uint32_t current_write_size = 0; + uint8_t * p_local_src_address; + fsp_err_t err = FSP_SUCCESS; + uint8_t * p_src = (uint8_t *) buffer; + +#if RM_LITTLEFS_SPI_FLASH_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(RM_LITTLEFS_SPI_FLASH_OPEN == p_ctrl->open, LFS_ERR_IO); +#endif + + rm_littlefs_spi_flash_cfg_t * p_extend = (rm_littlefs_spi_flash_cfg_t *) p_ctrl->p_cfg->p_extend; + spi_flash_instance_t * p_spi_flash_instance = (spi_flash_instance_t *) p_extend->p_lower_lvl; + uint32_t page_size = p_spi_flash_instance->p_cfg->page_size_bytes; + + uint32_t byte_count = size; + uint32_t p_flash_addr = p_ctrl->start_address + (block * p_ctrl->p_cfg->p_lfs_cfg->block_size) + off; + + for (uint32_t offset = 0U; offset < byte_count; offset += current_write_size) + { + /* Calculate current write size */ + current_write_size = page_size - ((p_flash_addr + offset) % page_size); + + if (current_write_size > (byte_count - offset)) + { + current_write_size = byte_count - offset; + } + + p_local_src_address = (uint8_t *) ((uint32_t) p_src + offset); + + /* Program using underlying SPI memory driver */ + err = p_spi_flash_instance->p_api->write(p_spi_flash_instance->p_ctrl, + p_local_src_address, + (uint8_t *) p_flash_addr + offset, + current_write_size); + + /* Write failed. Return IO error. Negative error codes are propogated to the user. */ + FSP_ERROR_RETURN(FSP_SUCCESS == err, LFS_ERR_IO); + + err = rm_littlefs_spi_flash_wait_write_erase_complete(p_ctrl); + + /* Write failed. Return IO error. Negative error codes are propogated to the user. */ + FSP_ERROR_RETURN(FSP_SUCCESS == err, LFS_ERR_IO); + } + + return LFS_ERR_OK; +} + +/*******************************************************************************************************************//** + * Erase the logical block. The location and number of blocks to be erased will depend on block size. + * + * @param[in] c Pointer to the LittleFS config block. + * @param[in] block The logical block number + * + * @retval LFS_ERR_OK Success. + * @retval LFS_ERR_IO Lower layer is not open or failed to erase the flash. + **********************************************************************************************************************/ +int rm_littlefs_spi_flash_erase (const struct lfs_config * c, lfs_block_t block) +{ + rm_littlefs_spi_flash_instance_ctrl_t * p_instance_ctrl = (rm_littlefs_spi_flash_instance_ctrl_t *) c->context; +#if RM_LITTLEFS_SPI_FLASH_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(RM_LITTLEFS_SPI_FLASH_OPEN == p_instance_ctrl->open, LFS_ERR_IO); +#endif + rm_littlefs_spi_flash_cfg_t const * p_extend = (rm_littlefs_spi_flash_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + spi_flash_instance_t const * p_lower_lvl = p_extend->p_lower_lvl; + + /* Call the underlying driver. */ + fsp_err_t err = + p_lower_lvl->p_api->erase(p_lower_lvl->p_ctrl, + (uint8_t *) (p_instance_ctrl->start_address + + (p_instance_ctrl->p_cfg->p_lfs_cfg->block_size * block)), + p_instance_ctrl->p_cfg->p_lfs_cfg->block_size); + + /* Erase failed. Return IO error. Negative error codes are propogated to the user. */ + FSP_ERROR_RETURN(FSP_SUCCESS == err, LFS_ERR_IO); + + err = rm_littlefs_spi_flash_wait_write_erase_complete(p_instance_ctrl); + + /* Write failed. Return IO error. Negative error codes are propogated to the user. */ + FSP_ERROR_RETURN(FSP_SUCCESS == err, LFS_ERR_IO); + + return LFS_ERR_OK; +} + +/*******************************************************************************************************************//** + * Returns the version of this module. + * + * @retval LFS_ERR_OK Success. + * @retval LFS_ERR_IO Lower layer is not open or failed to lock the flash. + **********************************************************************************************************************/ +int rm_littlefs_spi_flash_lock (const struct lfs_config * c) +{ +#ifdef LFS_THREADSAFE + rm_littlefs_spi_flash_instance_ctrl_t * p_instance_ctrl = (rm_littlefs_spi_flash_instance_ctrl_t *) c->context; + #if RM_LITTLEFS_SPI_FLASH_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(RM_LITTLEFS_SPI_FLASH_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + #endif + BaseType_t err = xSemaphoreTake(p_instance_ctrl->xSemaphore, RM_LITTLEFS_SPI_FLASH_SEMAPHORE_TIMEOUT); + + FSP_ERROR_RETURN(true == err, LFS_ERR_IO); + + return LFS_ERR_OK; +#else + FSP_PARAMETER_NOT_USED(c); + + return LFS_ERR_IO; +#endif +} + +/*******************************************************************************************************************//** + * Returns the version of this module. + * + * @retval LFS_ERR_OK Success. + * @retval LFS_ERR_IO Lower layer is not open or failed to unlock the flash. + **********************************************************************************************************************/ +int rm_littlefs_spi_flash_unlock (const struct lfs_config * c) +{ +#ifdef LFS_THREADSAFE + rm_littlefs_spi_flash_instance_ctrl_t * p_instance_ctrl = (rm_littlefs_spi_flash_instance_ctrl_t *) c->context; + #if RM_LITTLEFS_SPI_FLASH_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(RM_LITTLEFS_SPI_FLASH_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + #endif + BaseType_t err = xSemaphoreGive(p_instance_ctrl->xSemaphore); + + FSP_ERROR_RETURN(true == err, LFS_ERR_IO); + + return LFS_ERR_OK; +#else + FSP_PARAMETER_NOT_USED(c); + + return LFS_ERR_IO; +#endif +} + +/*******************************************************************************************************************//** + * Stub function required by LittleFS. All calls immedialy write/erase the lower layer. + * @param[in] c Pointer to the LittleFS config block. + * @retval LFS_ERR_OK Success. + **********************************************************************************************************************/ +int rm_littlefs_spi_flash_sync (const struct lfs_config * c) +{ + FSP_PARAMETER_NOT_USED(c); + + return LFS_ERR_OK; +} + +/*******************************************************************************************************************//** + * @brief Wait until the current program or erase operation completes. + * @param p_ctrl The instance control block + * @retval FSP_SUCCESS Successfully waited. + * @retval FSP_ERR_TIMEOUT Wait timed out. + * @return See @ref Common_Error_Codes or HAL driver for other possible return codes or + * causes. + * This function calls + * * spi_flash_api_t::statusGet + **********************************************************************************************************************/ +static fsp_err_t rm_littlefs_spi_flash_wait_write_erase_complete (rm_littlefs_spi_flash_instance_ctrl_t * const p_ctrl) +{ + spi_flash_status_t status; + fsp_err_t err; + rm_littlefs_spi_flash_cfg_t * p_extend = (rm_littlefs_spi_flash_cfg_t *) p_ctrl->p_cfg->p_extend; + const spi_flash_instance_t * p_spi_flash_instance = p_extend->p_lower_lvl; + uint32_t status_polls_remaining = p_extend->poll_status_count; + rm_littlefs_spi_flash_callback_args_t args; + + status.write_in_progress = true; + + /* While the SPI driver is busy call the delay callback if defined. If timeout return error. */ + do + { + err = p_spi_flash_instance->p_api->statusGet(p_spi_flash_instance->p_ctrl, &status); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* If write in progress call the user defined callback function. */ + if (status.write_in_progress) + { + if (NULL != p_extend->p_callback) + { + args.event = RM_LITTLEFS_SPI_FLASH_EVENT_BUSY; + args.p_context = p_extend->p_context; + p_extend->p_callback(&args); + } + + status_polls_remaining--; + } + } while (status.write_in_progress && (status_polls_remaining > 0U)); + + /* Check whether write completed */ + FSP_ERROR_RETURN(!status.write_in_progress, FSP_ERR_TIMEOUT); + + return FSP_SUCCESS; +} diff --git a/ra/fsp/src/rm_lwip_ether/rm_lwip_ether.c b/ra/fsp/src/rm_lwip_ether/rm_lwip_ether.c new file mode 100644 index 000000000..5dedd3972 --- /dev/null +++ b/ra/fsp/src/rm_lwip_ether/rm_lwip_ether.c @@ -0,0 +1,434 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + ***********************************************************************************************************************/ +#include "rm_lwip_ether.h" + +#include "netif/etharp.h" +#include "lwip/sys.h" +#include "lwip/timeouts.h" +#include "lwip/priv/memp_priv.h" + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ +#define LWIP_ETHER_MINIMUM_FRAME_SIZE (60U) /* Minimum number of transmitted data */ + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global function + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + ***********************************************************************************************************************/ + +/* Static functions */ +static err_t rm_lwip_ether_output(struct netif * p_netif, struct pbuf * p_pbuf); +static void rm_lwip_ether_buffer_init(rm_lwip_ether_instance_t * p_lwip_instance); +static void rm_lwip_ether_check_link_status(void * p_lwip_instance); +static void rm_lwip_ether_free(struct pbuf * p_pbuf); +static void rm_lwip_ether_input(rm_lwip_ether_instance_t * p_lwip_instance); +static void rm_lwip_ether_remove(struct netif * p_netif); + +#if !NO_SYS +static void rm_lwip_ether_input_thread(void * arg); + +#endif + +/*******************************************************************************************************************//** + * @addtogroup RM_LWIP_ETHER + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/********************************************************************************************************************//** + * Initialize ethernet hardware and lwIP network interface. + * This function is passed to netif_add() + ***********************************************************************************************************************/ +err_t rm_lwip_ether_init (struct netif * p_netif) +{ + fsp_err_t fsp_err; + err_t lwip_err; + + rm_lwip_ether_instance_t * p_lwip_instance; + ether_instance_t * p_ether_instance; + + FSP_ERROR_RETURN(NULL != p_netif, ERR_IF); + FSP_ERROR_RETURN(NULL != p_netif->state, ERR_IF); + FSP_ERROR_RETURN(NULL != ((rm_lwip_ether_instance_t *) (p_netif->state))->p_cfg->p_ether_instance, ERR_IF); + + p_lwip_instance = (rm_lwip_ether_instance_t *) (p_netif->state); + p_ether_instance = p_lwip_instance->p_cfg->p_ether_instance; + + /* Set netif to lwIP port instance */ + p_lwip_instance->p_ctrl->p_netif = p_netif; + + /* Set flags indicating the capability of the interface. */ + p_netif->flags = p_lwip_instance->p_cfg->flags; + + /* Set maximum transfer unit. */ + p_netif->mtu = p_lwip_instance->p_cfg->mtu; + + /* Set MAC hardware address */ + memcpy(&p_netif->hwaddr[0], &p_ether_instance->p_cfg->p_mac_address[0], sizeof(p_netif->hwaddr)); + + /* Set hardware address length of Ethernet. */ + p_netif->hwaddr_len = ETH_HWADDR_LEN; + + /* Set output function that support ARP. */ + p_netif->output = etharp_output; + + /* Set function to send a Ethernet frame */ + p_netif->linkoutput = rm_lwip_ether_output; + + /* Set interface name as channel number. e.g. "c1" */ + p_netif->name[0] = 'c'; + p_netif->name[1] = (char) (p_ether_instance->p_cfg->channel + '0'); + + /* Set end process */ + netif_set_remove_callback(p_netif, rm_lwip_ether_remove); + + /* Initialize Ethernet module */ + fsp_err = p_ether_instance->p_api->open(p_ether_instance->p_ctrl, p_ether_instance->p_cfg); + + if (FSP_SUCCESS == fsp_err) + { + lwip_err = ERR_OK; + + /* Check link status periodically.*/ + rm_lwip_ether_check_link_status(p_lwip_instance); + +#if !NO_SYS + if (0 == p_lwip_instance->p_ctrl->input_thread_exist) + { +/* GCC compilier occur aggregate-return warning on FreeRTOS port. */ + #if defined(__GNUC__) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Waggregate-return" + #endif + + /* Start input thread. */ + sys_thread_new("lwip_ether_input_thread", + rm_lwip_ether_input_thread, + p_lwip_instance, + p_lwip_instance->p_cfg->input_thread_stacksize, + p_lwip_instance->p_cfg->input_thread_priority); + #if defined(__GNUC__) + #pragma GCC diagnostic pop + #endif + + p_lwip_instance->p_ctrl->input_thread_exist = true; + } +#endif + } + else + { + lwip_err = ERR_IF; + } + + return lwip_err; +} + +/********************************************************************************************************************//** + * Callback of Ethernet interrupt subroutine. + * This function is set to ethernet driver callback by configurator. + ***********************************************************************************************************************/ +void rm_lwip_ether_callback (ether_callback_args_t * p_args) +{ + rm_lwip_ether_instance_t * p_lwip_instance = (rm_lwip_ether_instance_t *) p_args->p_context; + struct netif * p_netif = p_lwip_instance->p_ctrl->p_netif; + + switch (p_args->event) + { + /* When a frame is received. This includes the case when the receive buffer is full. */ + case ETHER_EVENT_RX_COMPLETE: + case ETHER_EVENT_RX_MESSAGE_LOST: + { +#if !NO_SYS + + /* Send a message to input thread. */ + sys_mbox_trypost_fromisr(p_lwip_instance->p_ctrl->p_read_complete_mbox, + &p_lwip_instance->p_ctrl->read_complete_message); +#else + + /* Notify packet to lwIP. */ + rm_lwip_ether_input(p_lwip_instance); +#endif + break; + } + + case ETHER_EVENT_LINK_ON: + { + netif_set_link_up(p_netif); + + /* Initialize RX buffers. It is necessary that buffers are initialized in linkup callback. */ + rm_lwip_ether_buffer_init(p_lwip_instance); + break; + } + + case ETHER_EVENT_LINK_OFF: + { + netif_set_link_down(p_netif); + break; + } + + default: + { + break; + } + } +} + +/** @} (end addtogroup GPT) */ + +/*******************************************************************************************************************//** + * Private Functions + **********************************************************************************************************************/ + +/** + * Send frame of pbuf. + */ +static err_t rm_lwip_ether_output (struct netif * p_netif, struct pbuf * p_pbuf) +{ + fsp_err_t fsp_err; + ether_instance_t * p_ether_instance = ((rm_lwip_ether_instance_t *) p_netif->state)->p_cfg->p_ether_instance; + err_t lwip_err = ERR_OK; + struct pbuf * temp = p_pbuf; + + while (NULL != temp) + { + /* Sending frame buffer for the frame shorter than 60bytes. */ + uint8_t minimum_frame[LWIP_ETHER_MINIMUM_FRAME_SIZE] = {0}; + + if (temp->len < LWIP_ETHER_MINIMUM_FRAME_SIZE) + { + /* Add padding when shorter than 60bytes. */ + memcpy(minimum_frame, (char *) temp->payload, temp->len); + fsp_err = + p_ether_instance->p_api->write(p_ether_instance->p_ctrl, minimum_frame, LWIP_ETHER_MINIMUM_FRAME_SIZE); + } + else + { + fsp_err = p_ether_instance->p_api->write(p_ether_instance->p_ctrl, temp->payload, temp->len); + } + + /* If the write operation fails, the remaining pbufs are not output .*/ + if (fsp_err != FSP_SUCCESS) + { + lwip_err = ERR_IF; + break; + } + + temp = temp->next; + } + + return lwip_err; +} + +/** + * Receive frame and notify it to lwIP. + */ +static void rm_lwip_ether_input (rm_lwip_ether_instance_t * p_lwip_instance) +{ + struct pbuf * p_pbuf; + rm_lwip_rx_pbuf_t * p_custom_pbuf = NULL; + uint32_t read_buffer_length = 0; + void * p_rx_buffer = NULL; + + /* When p_netif is NULL, this driver is uninitialized or terminated. */ + FSP_ERROR_RETURN(NULL != p_lwip_instance->p_ctrl->p_netif, ); + + ether_instance_t * p_ether_instance = p_lwip_instance->p_cfg->p_ether_instance; + fsp_err_t err = FSP_SUCCESS; + + /* Read all RX descriptors that received a frame. */ + do + { + /* Allocate a custom pbuf. */ + p_custom_pbuf = (rm_lwip_rx_pbuf_t *) memp_malloc_pool(p_lwip_instance->p_cfg->p_rx_pbuf_mempool); + if (NULL == p_custom_pbuf) + { + break; + } + + /* Allocate a buffer that store received frame. */ + p_rx_buffer = memp_malloc_pool(p_lwip_instance->p_cfg->p_rx_buffers_mempool); + if (NULL == p_rx_buffer) + { + memp_free_pool(p_custom_pbuf->p_lwip_instance->p_cfg->p_rx_pbuf_mempool, p_custom_pbuf); + break; + } + + /* Set custom pbuf members. */ + p_custom_pbuf->p_lwip_instance = p_lwip_instance; + p_custom_pbuf->pbuf.custom_free_function = rm_lwip_ether_free; + p_pbuf = pbuf_alloced_custom(PBUF_RAW, + 0, + PBUF_REF, + &p_custom_pbuf->pbuf, + NULL, + (uint16_t) p_ether_instance->p_cfg->ether_buffer_size); + + if (ETHER_ZEROCOPY_ENABLE == p_ether_instance->p_cfg->zerocopy) + { + err = p_ether_instance->p_api->read(p_ether_instance->p_ctrl, &p_pbuf->payload, &read_buffer_length); + if (FSP_SUCCESS == err) + { + /* Update the buffer of Ethernet descriptor to new one. */ + p_ether_instance->p_api->rxBufferUpdate(p_ether_instance->p_ctrl, p_rx_buffer); + } + else if (FSP_ERR_ETHER_ERROR_NO_DATA != err) + { + /* Release new buffer. */ + memp_free_pool(p_custom_pbuf->p_lwip_instance->p_cfg->p_rx_buffers_mempool, p_rx_buffer); + + /* Release current buffer that set to the descriptor. */ + p_ether_instance->p_api->bufferRelease(p_ether_instance->p_ctrl); + } + else + { + /* Release new buffer. */ + memp_free_pool(p_custom_pbuf->p_lwip_instance->p_cfg->p_rx_buffers_mempool, p_rx_buffer); + } + } + else /* ETHER_ZEROCOPY_ENABLE == p_ether_instance->p_cfg->zerocopy */ + { + /* Read data. */ + err = p_ether_instance->p_api->read(p_ether_instance->p_ctrl, p_rx_buffer, &read_buffer_length); + + /* Copy data to pbuf. */ + p_pbuf->payload = p_rx_buffer; + } + + /* Store the buffer address. It need to release the buffer. */ + p_custom_pbuf->p_buffer = p_pbuf->payload; + + if (FSP_SUCCESS == err) + { + /* Set packet length */ + p_pbuf->len = (uint16_t) read_buffer_length; + p_pbuf->tot_len = (uint16_t) read_buffer_length; + + /* Notify packet */ + if (p_lwip_instance->p_ctrl->p_netif->input(p_pbuf, p_lwip_instance->p_ctrl->p_netif) != ERR_OK) + { + pbuf_free(p_pbuf); + } + } + else + { + /* When the receive error is happened, release the buffer. */ + pbuf_free(p_pbuf); + } + + /* Continue until all received buffers are read. */ + } while (FSP_ERR_ETHER_ERROR_NO_DATA != err); +} + +/** + * Free buffer for RX. + */ +static void rm_lwip_ether_free (struct pbuf * p_pbuf) +{ + rm_lwip_rx_pbuf_t * p_custom_pbuf = (rm_lwip_rx_pbuf_t *) p_pbuf; + + /* Release RX buffer and custom pbuf. */ + if (NULL != p_custom_pbuf->p_buffer) + { + memp_free_pool(p_custom_pbuf->p_lwip_instance->p_cfg->p_rx_buffers_mempool, p_custom_pbuf->p_buffer); + } + + memp_free_pool(p_custom_pbuf->p_lwip_instance->p_cfg->p_rx_pbuf_mempool, p_custom_pbuf); +} + +/** + * Terminating network driver. + */ +static void rm_lwip_ether_remove (struct netif * p_netif) +{ + rm_lwip_ether_instance_t * p_lwip_instance = (rm_lwip_ether_instance_t *) p_netif->state; + ether_instance_t * p_ether_instance = p_lwip_instance->p_cfg->p_ether_instance; + + /* Remove lwip timer for link check. */ + sys_untimeout(rm_lwip_ether_check_link_status, p_lwip_instance); + + /* Remove the pointer to netif. */ + p_lwip_instance->p_ctrl->p_netif = NULL; + + /* Close Ethernet driver. */ + p_ether_instance->p_api->close(p_ether_instance->p_ctrl); +} + +/** + * Checking link status periodically. + */ +static void rm_lwip_ether_check_link_status (void * p_lwip_instance) +{ + ether_instance_t * p_ether_instance = ((rm_lwip_ether_instance_t *) p_lwip_instance)->p_cfg->p_ether_instance; + + /* Check link status. If link status change detected, change the lwIP status in link callback. */ + p_ether_instance->p_api->linkProcess(p_ether_instance->p_ctrl); + sys_timeout(((rm_lwip_ether_instance_t *) p_lwip_instance)->p_cfg->link_check_interval, + rm_lwip_ether_check_link_status, + p_lwip_instance); +} + +/** + * Initialize RX buffers. + */ +static void rm_lwip_ether_buffer_init (rm_lwip_ether_instance_t * p_lwip_instance) +{ + ether_instance_t * p_ether_instance = p_lwip_instance->p_cfg->p_ether_instance; + void * p_rx_buffer; + + memp_init_pool(p_lwip_instance->p_cfg->p_rx_pbuf_mempool); + memp_init_pool(p_lwip_instance->p_cfg->p_rx_buffers_mempool); + + if (ETHER_ZEROCOPY_ENABLE == p_ether_instance->p_cfg->zerocopy) + { + /* If zerocopy mode, set RX buffers to Ethernet descriptors. */ + for (int i = 0; i < p_ether_instance->p_cfg->num_rx_descriptors; i++) + { + p_rx_buffer = memp_malloc_pool(p_lwip_instance->p_cfg->p_rx_buffers_mempool); + p_ether_instance->p_api->rxBufferUpdate(p_ether_instance->p_ctrl, p_rx_buffer); + } + } +} + +/** + * Thread for receiving process. + */ +#if !NO_SYS +static void rm_lwip_ether_input_thread (void * arg) +{ + rm_lwip_ether_instance_t * p_lwip_instance = (rm_lwip_ether_instance_t *) arg; + uint32_t * p_read_complete_flag; + + /* Create new mbox for checking read complete. */ + p_lwip_instance->p_ctrl->p_read_complete_mbox = (sys_mbox_t *) mem_malloc(sizeof(sys_mbox_t)); + sys_mbox_new(p_lwip_instance->p_ctrl->p_read_complete_mbox, 1); + + while (true) + { + sys_mbox_fetch(p_lwip_instance->p_ctrl->p_read_complete_mbox, (void **) &p_read_complete_flag); + rm_lwip_ether_input(p_lwip_instance); + } +} + +#endif diff --git a/ra/fsp/src/rm_lwip_ether/rm_lwip_ether.h b/ra/fsp/src/rm_lwip_ether/rm_lwip_ether.h new file mode 100644 index 000000000..8a64e2e4a --- /dev/null +++ b/ra/fsp/src/rm_lwip_ether/rm_lwip_ether.h @@ -0,0 +1,82 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef RM_LWIP_ETHER_H +#define RM_LWIP_ETHER_H + +#include "lwip/netif.h" +#include "r_ether_api.h" +#include "lwip/sys.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +typedef struct st_rm_lwip_ether_ctrl +{ + /* lwIP Netwrok interface. */ + struct netif * p_netif; + + /* Whether the input thread is alive or not. */ + bool input_thread_exist; + + /* Mbox for notifing read complete. */ + sys_mbox_t * p_read_complete_mbox; + + /* Message to notify that the read process is complete. */ + bool read_complete_message; +} rm_lwip_ether_ctrl_t; + +typedef struct st_rm_lwip_ether_cfg +{ + /* Ethenet driver */ + ether_instance_t * p_ether_instance; + + /* Set flags indicating the capability of the netif. The meaning of each flag is defined in lwIP. */ + uint8_t flags; + + /* Set maximum transfer unit. */ + uint16_t mtu; + + /* Memory pool for receive buffer. */ + void const * p_rx_buffers_mempool; + + /* Memory pool for RX pbuf. */ + void const * p_rx_pbuf_mempool; + + /* Interval of processing to check link status */ + uint32_t link_check_interval; + + /* Stack size for input thread. */ + int32_t input_thread_stacksize; + + /* Priority for input thread. */ + int32_t input_thread_priority; + + void const * p_context; + void const * p_extend; +} rm_lwip_ether_cfg_t; + +typedef struct st_rm_lwip_ether_instance +{ + rm_lwip_ether_ctrl_t * p_ctrl; + rm_lwip_ether_cfg_t * p_cfg; +} rm_lwip_ether_instance_t; + +/* Pbuf customized for RX usage. */ +typedef struct st_rm_lwip_rx_pbuf +{ + struct pbuf_custom pbuf; + void * p_buffer; + rm_lwip_ether_instance_t * p_lwip_instance; +} rm_lwip_rx_pbuf_t; + +err_t rm_lwip_ether_init(struct netif * netif); +void rm_lwip_ether_callback(ether_callback_args_t * p_args); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/ra/fsp/src/rm_lwip_sys_port/arch/cc.h b/ra/fsp/src/rm_lwip_sys_port/arch/cc.h new file mode 100644 index 000000000..88ab08aea --- /dev/null +++ b/ra/fsp/src/rm_lwip_sys_port/arch/cc.h @@ -0,0 +1,16 @@ +#ifndef LWIP_HDR_CC_H +#define LWIP_HDR_CC_H + +#include "bsp_api.h" + +/* Platform specific assertion handling. */ +#ifndef LWIP_PLATFORM_ASSERT + #define LWIP_PLATFORM_ASSERT(x) do {FSP_LOG_PRINT(x); BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(0);} while (0) +#endif + +/* Support packed structures for IAR. */ +#if defined(__ICCARM__) + #define PACK_STRUCT_BEGIN __packed +#endif + +#endif /* LWIP_HDR_CC_H */ diff --git a/ra/fsp/src/rm_lwip_sys_port/baremetal/arch/sys_arch.h b/ra/fsp/src/rm_lwip_sys_port/baremetal/arch/sys_arch.h new file mode 100644 index 000000000..e964aa4e3 --- /dev/null +++ b/ra/fsp/src/rm_lwip_sys_port/baremetal/arch/sys_arch.h @@ -0,0 +1,10 @@ +#ifndef LWIP_ARCH_SYS_ARCH_H +#define LWIP_ARCH_SYS_ARCH_H + +#include "bsp_api.h" + +#define SYS_ARCH_DECL_PROTECT(lev) FSP_CRITICAL_SECTION_DEFINE; +#define SYS_ARCH_PROTECT(lev) FSP_CRITICAL_SECTION_ENTER; +#define SYS_ARCH_UNPROTECT(lev) FSP_CRITICAL_SECTION_EXIT; + +#endif /* LWIP_ARCH_SYS_ARCH_H */ diff --git a/ra/fsp/src/rm_lwip_sys_port/baremetal/rm_lwip_sys_baremetal.c b/ra/fsp/src/rm_lwip_sys_port/baremetal/rm_lwip_sys_baremetal.c new file mode 100644 index 000000000..b27030219 --- /dev/null +++ b/ra/fsp/src/rm_lwip_sys_port/baremetal/rm_lwip_sys_baremetal.c @@ -0,0 +1,440 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + ***********************************************************************************************************************/ +#include "lwip/memp.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" +#include "lwip/timeouts.h" +#include "netif/ppp/ppp_opts.h" + +#include "rm_lwip_sys_baremetal.h" + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ +#if LWIP_DEBUG_TIMERNAMES + #define HANDLER(x) x, #x +#else /* LWIP_DEBUG_TIMERNAMES */ + #define HANDLER(x) x +#endif /* LWIP_DEBUG_TIMERNAMES */ + +#define LWIP_MAX_TIMEOUT 0x7fffffff + +/* Check if timer's expiry time is greater than time and care about u32_t wraparounds */ +#define TIME_LESS_THAN(t, compare_to) ((((u32_t) ((t) - (compare_to))) > LWIP_MAX_TIMEOUT) ? 1 : 0) + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global function + ***********************************************************************************************************************/ +extern rm_lwip_sys_baremetal_instance_t * rm_lwip_sys_baremetal_set_instance(void); +void rm_lwip_sys_baremetal_timer_callback(timer_callback_args_t * p_args); + +/*********************************************************************************************************************** + * Private global variables and functions + ***********************************************************************************************************************/ +static void rm_lwip_sys_baremetal_timer_setup(void); + +/* Declare memory pool for sys_timeouts. */ +LWIP_MEMPOOL_DECLARE(SYS_TIMEOUT, MEMP_NUM_SYS_TIMEOUT, sizeof(struct sys_timeo), "SYS_TIMEOUT"); + +static rm_lwip_sys_baremetal_instance_t * gp_lwip_sys_baremetal_instance; + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/* + * Return current count in raw. + */ +u32_t sys_jiffies (void) +{ + return gp_lwip_sys_baremetal_instance->p_ctrl->timer_count; +} + +/* + * Return current count in milliseconds. + * This funcition is called by lwIP timeouts. + */ +u32_t sys_now (void) +{ + return sys_jiffies(); +} + +static void +#if LWIP_DEBUG_TIMERNAMES +sys_timeout_abs (u32_t abs_time, sys_timeout_handler handler, void * arg, const char * handler_name) +#else /* LWIP_DEBUG_TIMERNAMES */ +sys_timeout_abs(u32_t abs_time, sys_timeout_handler handler, void * arg) +#endif +{ + struct sys_timeo * timeout; + struct sys_timeo * t; + + timeout = (struct sys_timeo *) LWIP_MEMPOOL_ALLOC(SYS_TIMEOUT); + if (timeout == NULL) + { + LWIP_ASSERT("sys_timeout: timeout != NULL, pool MEMP_SYS_TIMEOUT is empty", timeout != NULL); + + return; + } + + timeout->next = NULL; + timeout->h = handler; + timeout->arg = arg; + timeout->time = abs_time; + +#if LWIP_DEBUG_TIMERNAMES + timeout->handler_name = handler_name; + LWIP_DEBUGF(TIMERS_DEBUG, + ("sys_timeout: %p abs_time=%"U32_F " handler=%s arg=%p\n", + (void *) timeout, abs_time, handler_name, (void *) arg)); +#endif /* LWIP_DEBUG_TIMERNAMES */ + + if (gp_lwip_sys_baremetal_instance->p_ctrl->p_next_timeout == NULL) + { + gp_lwip_sys_baremetal_instance->p_ctrl->p_next_timeout = timeout; + + return; + } + + if (TIME_LESS_THAN(timeout->time, gp_lwip_sys_baremetal_instance->p_ctrl->p_next_timeout->time)) + { + timeout->next = gp_lwip_sys_baremetal_instance->p_ctrl->p_next_timeout; + gp_lwip_sys_baremetal_instance->p_ctrl->p_next_timeout = timeout; + } + else + { + t = gp_lwip_sys_baremetal_instance->p_ctrl->p_next_timeout; + while (t != NULL) + { + if ((t->next == NULL) || TIME_LESS_THAN(timeout->time, t->next->time)) + { + timeout->next = t->next; + t->next = timeout; + break; + } + + t = t->next; + } + } +} + +/* + * Timer callback function that calls cyclic->handler() and reschedules itself. + * + * @param arg unused argument + */ +static +void lwip_cyclic_timer (void * arg) +{ + u32_t now; + u32_t next_timeout_time; + const struct lwip_cyclic_timer * cyclic = (const struct lwip_cyclic_timer *) arg; + +#if LWIP_DEBUG_TIMERNAMES + LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: %s()\n", cyclic->handler_name)); +#endif + cyclic->handler(); + + now = sys_now(); + next_timeout_time = + (u32_t) (gp_lwip_sys_baremetal_instance->p_ctrl->current_timeout_due_time + cyclic->interval_ms); /* overflow handled by TIME_LESS_THAN macro */ + if (TIME_LESS_THAN(next_timeout_time, now)) + { + /* timer would immediately expire again -> "overload" -> restart without any correction */ +#if LWIP_DEBUG_TIMERNAMES + sys_timeout_abs((u32_t) (now + cyclic->interval_ms), lwip_cyclic_timer, arg, cyclic->handler_name); +#else + sys_timeout_abs((u32_t) (now + cyclic->interval_ms), lwip_cyclic_timer, arg); +#endif + } + else + { + /* correct cyclic interval with handler execution delay and sys_check_timeouts jitter */ +#if LWIP_DEBUG_TIMERNAMES + sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg, cyclic->handler_name); +#else + sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg); +#endif + } +} + +/* Initialize this module */ +void sys_timeouts_init (void) +{ + int i; + + /* Initialize memory pool for sys_timeouts. */ + LWIP_MEMPOOL_INIT(SYS_TIMEOUT); + + /* Initialize FSP timer. */ + rm_lwip_sys_baremetal_timer_setup(); + + for (i = 0; i < lwip_num_cyclic_timers; i++) + { + /* we have to cast via size_t to get rid of const warning + * (this is OK as cyclic_timer() casts back to const* */ + sys_timeout(lwip_cyclic_timers[i].interval_ms, + lwip_cyclic_timer, + LWIP_CONST_CAST(void *, &lwip_cyclic_timers[i])); + } +} + +/* + * Create a one-shot timer (aka timeout). Timeouts are processed in the + * following cases: + * - while waiting for a message using sys_timeouts_mbox_fetch() + * - by calling sys_check_timeouts() (NO_SYS==1 only) + * + * @param msecs time in milliseconds after that the timer should expire + * @param handler callback function to call when msecs have elapsed + * @param arg argument to pass to the callback function + */ +#if LWIP_DEBUG_TIMERNAMES +void sys_timeout_debug (u32_t msecs, sys_timeout_handler handler, void * arg, const char * handler_name) +#else /* LWIP_DEBUG_TIMERNAMES */ +void sys_timeout (u32_t msecs, sys_timeout_handler handler, void * arg) +#endif /* LWIP_DEBUG_TIMERNAMES */ +{ + u32_t next_timeout_time; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ASSERT("Timeout time too long, max is LWIP_UINT32_MAX/4 msecs", msecs <= (LWIP_UINT32_MAX / 4)); + + next_timeout_time = (u32_t) (sys_now() + msecs); /* overflow handled by TIME_LESS_THAN macro */ + +#if LWIP_DEBUG_TIMERNAMES + sys_timeout_abs(next_timeout_time, handler, arg, handler_name); +#else + sys_timeout_abs(next_timeout_time, handler, arg); +#endif +} + +/* + * Go through timeout list (for this task only) and remove the first matching + * entry (subsequent entries remain untouched), even though the timeout has not + * triggered yet. + * + * @param handler callback function that would be called by the timeout + * @param arg callback argument that would be passed to handler + */ +void sys_untimeout (sys_timeout_handler handler, void * arg) +{ + struct sys_timeo * prev_t; + struct sys_timeo * t; + + LWIP_ASSERT_CORE_LOCKED(); + + if (gp_lwip_sys_baremetal_instance->p_ctrl->p_next_timeout == NULL) + { + return; + } + + prev_t = NULL; + t = gp_lwip_sys_baremetal_instance->p_ctrl->p_next_timeout; + while (t != NULL) + { + if ((t->h == handler) && (t->arg == arg)) + { + /* We have a match */ + /* Unlink from previous in list */ + if (prev_t == NULL) + { + gp_lwip_sys_baremetal_instance->p_ctrl->p_next_timeout = t->next; + } + else + { + prev_t->next = t->next; + } + + LWIP_MEMPOOL_FREE(SYS_TIMEOUT, t); + + return; + } + + prev_t = t; + t = t->next; + } +} + +/* + * @ingroup lwip_nosys + * Handle timeouts for NO_SYS==1 (i.e. without using + * tcpip_thread/sys_timeouts_mbox_fetch(). Uses sys_now() to call timeout + * handler functions when timeouts expire. + * + * Must be called periodically from your main loop. + */ +void sys_check_timeouts (void) +{ + u32_t now; + + LWIP_ASSERT_CORE_LOCKED(); + + /* Process only timers expired at the start of the function. */ + now = sys_now(); + + do + { + struct sys_timeo * tmptimeout; + sys_timeout_handler handler; + void * arg; + + PBUF_CHECK_FREE_OOSEQ(); + + tmptimeout = gp_lwip_sys_baremetal_instance->p_ctrl->p_next_timeout; + if (tmptimeout == NULL) + { + return; + } + + if (TIME_LESS_THAN(now, tmptimeout->time)) + { + return; + } + + /* Timeout has expired */ + gp_lwip_sys_baremetal_instance->p_ctrl->p_next_timeout = tmptimeout->next; + handler = tmptimeout->h; + arg = tmptimeout->arg; + gp_lwip_sys_baremetal_instance->p_ctrl->current_timeout_due_time = tmptimeout->time; +#if LWIP_DEBUG_TIMERNAMES + if (handler != NULL) + { + LWIP_DEBUGF(TIMERS_DEBUG, + ("sct calling h=%s t=%"U32_F " arg=%p\n", + tmptimeout->handler_name, sys_now() - tmptimeout->time, arg)); + } +#endif /* LWIP_DEBUG_TIMERNAMES */ + LWIP_MEMPOOL_FREE(SYS_TIMEOUT, tmptimeout); + if (handler != NULL) + { + handler(arg); + } + + LWIP_TCPIP_THREAD_ALIVE(); + + /* Repeat until all expired timers have been called */ + } while (1); +} + +/* Rebase the timeout times to the current time. + * This is necessary if sys_check_timeouts() hasn't been called for a long + * time (e.g. while saving energy) to prevent all timer functions of that + * period being called. + */ +void sys_restart_timeouts (void) +{ + u32_t now; + u32_t base; + struct sys_timeo * t; + + if (gp_lwip_sys_baremetal_instance->p_ctrl->p_next_timeout == NULL) + { + return; + } + + now = sys_now(); + base = gp_lwip_sys_baremetal_instance->p_ctrl->p_next_timeout->time; + + t = gp_lwip_sys_baremetal_instance->p_ctrl->p_next_timeout; + while (t != NULL) + { + t->time = (t->time - base) + now; + t = t->next; + } +} + +/* Return the time left before the next timeout is due. If no timeouts are + * enqueued, returns 0xffffffff + */ +u32_t sys_timeouts_sleeptime (void) +{ + u32_t now; + u32_t ret; + + LWIP_ASSERT_CORE_LOCKED(); + + if (gp_lwip_sys_baremetal_instance->p_ctrl->p_next_timeout == NULL) + { + return SYS_TIMEOUTS_SLEEPTIME_INFINITE; + } + + now = sys_now(); + if (TIME_LESS_THAN(gp_lwip_sys_baremetal_instance->p_ctrl->p_next_timeout->time, now)) + { + ret = 0; + } + else + { + ret = (u32_t) (gp_lwip_sys_baremetal_instance->p_ctrl->p_next_timeout->time - now); + LWIP_ASSERT("invalid sleeptime", ret <= LWIP_MAX_TIMEOUT); + } + + return ret; +} + +/*********************************************************************************************************************** + * Increments system time. + **********************************************************************************************************************/ +void rm_lwip_sys_baremetal_timer_callback (timer_callback_args_t * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); + + gp_lwip_sys_baremetal_instance->p_ctrl->timer_count += 1; +} + +/*********************************************************************************************************************** + * Return an instance of this porting layer. + **********************************************************************************************************************/ +BSP_WEAK_REFERENCE rm_lwip_sys_baremetal_instance_t * rm_lwip_sys_baremetal_set_instance (void) +{ + /* Not implemented in this code and must be generated by configuration. */ + BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(0); + + return NULL; +} + +/*********************************************************************************************************************** + * Initialize and start timers used by the lwIP timeouts features. + * This function is called from sys_timeouts_init. + **********************************************************************************************************************/ +static void rm_lwip_sys_baremetal_timer_setup (void) +{ + const timer_instance_t * p_timer_instance; + + /* Get instance of baremetal porting layer. */ + gp_lwip_sys_baremetal_instance = rm_lwip_sys_baremetal_set_instance(); + + /* Null check for each parameters. */ + FSP_ERROR_RETURN(NULL != gp_lwip_sys_baremetal_instance, ); + FSP_ERROR_RETURN(NULL != gp_lwip_sys_baremetal_instance->p_cfg, ); + FSP_ERROR_RETURN(NULL != gp_lwip_sys_baremetal_instance->p_ctrl, ); + FSP_ERROR_RETURN(NULL != gp_lwip_sys_baremetal_instance->p_cfg->p_timer_instance, ); + + /* Initialize control block. */ + gp_lwip_sys_baremetal_instance->p_ctrl->current_timeout_due_time = 0; + gp_lwip_sys_baremetal_instance->p_ctrl->p_next_timeout = NULL; + gp_lwip_sys_baremetal_instance->p_ctrl->timer_count = 0; + + /* Start timer. */ + p_timer_instance = gp_lwip_sys_baremetal_instance->p_cfg->p_timer_instance; + p_timer_instance->p_api->open(p_timer_instance->p_ctrl, p_timer_instance->p_cfg); + p_timer_instance->p_api->callbackSet(p_timer_instance->p_ctrl, rm_lwip_sys_baremetal_timer_callback, NULL, NULL); + p_timer_instance->p_api->start(p_timer_instance->p_ctrl); +} diff --git a/ra/fsp/src/rm_lwip_sys_port/baremetal/rm_lwip_sys_baremetal.h b/ra/fsp/src/rm_lwip_sys_port/baremetal/rm_lwip_sys_baremetal.h new file mode 100644 index 000000000..43cd3f311 --- /dev/null +++ b/ra/fsp/src/rm_lwip_sys_port/baremetal/rm_lwip_sys_baremetal.h @@ -0,0 +1,43 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef RM_LWIP_SYS_BAREMETAL_H +#define RM_LWIP_SYS_BAREMETAL_H + +#include "lwip/sys.h" +#include "r_timer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +typedef struct st_rm_lwip_sys_baremetal_ctrl +{ + /* The one and only timeout list. */ + struct sys_timeo * p_next_timeout; + + /* Current timeout duration. */ + uint32_t current_timeout_due_time; + + /* Current system time [ms]. */ + uint32_t timer_count; +} rm_lwip_sys_baremetal_ctrl_t; + +typedef struct st_rm_lwip_sys_baremetal_cfg +{ + /* Timer driver */ + const timer_instance_t * p_timer_instance; +} rm_lwip_sys_baremetal_cfg_t; + +typedef struct st_rm_lwip_sys_baremetal_instance +{ + rm_lwip_sys_baremetal_ctrl_t * p_ctrl; + rm_lwip_sys_baremetal_cfg_t * p_cfg; +} rm_lwip_sys_baremetal_instance_t; + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/ra/fsp/src/rm_mbedtls/x509_crt.c b/ra/fsp/src/rm_mbedtls/x509_crt.c index 5b53a7c47..34908b08e 100644 --- a/ra/fsp/src/rm_mbedtls/x509_crt.c +++ b/ra/fsp/src/rm_mbedtls/x509_crt.c @@ -2,21 +2,7 @@ * X.509 certificate parsing and verification * * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * This file is part of mbed TLS (https://tls.mbed.org) v3.1 () d65aeb37349ad1a50e0f6c9b694d4b5290d60e49 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later */ /* * The ITU-T X.509 standard defines a certificate format for PKI. @@ -36,6 +22,7 @@ #if defined(MBEDTLS_X509_CRT_PARSE_C) #include "mbedtls/x509_crt.h" +#include "x509_internal.h" #include "mbedtls/error.h" #include "mbedtls/oid.h" #include "mbedtls/platform_util.h" @@ -49,7 +36,7 @@ #if defined(MBEDTLS_USE_PSA_CRYPTO) #include "psa/crypto.h" #include "psa_util_internal.h" -#include "md_psa.h" +#include "mbedtls/psa_util.h" #endif /* MBEDTLS_USE_PSA_CRYPTO */ #include "pk_internal.h" @@ -238,7 +225,7 @@ static int x509_profile_check_key(const mbedtls_x509_crt_profile *profile, if (pk_alg == MBEDTLS_PK_ECDSA || pk_alg == MBEDTLS_PK_ECKEY || pk_alg == MBEDTLS_PK_ECKEY_DH) { - const mbedtls_ecp_group_id gid = mbedtls_pk_get_group_id(pk); + const mbedtls_ecp_group_id gid = mbedtls_pk_get_ec_group_id(pk); if (gid == MBEDTLS_ECP_DP_NONE) { return -1; @@ -1124,7 +1111,7 @@ static int x509_crt_parse_der_core(mbedtls_x509_crt *crt, } end = crt_end = p + len; - crt->raw.len = crt_end - buf; + crt->raw.len = (size_t) (crt_end - buf); if (make_copy != 0) { /* Create and populate a new buffer for the raw field. */ crt->raw.p = p = mbedtls_calloc(1, crt->raw.len); @@ -1154,7 +1141,7 @@ static int x509_crt_parse_der_core(mbedtls_x509_crt *crt, } end = p + len; - crt->tbs.len = end - crt->tbs.p; + crt->tbs.len = (size_t) (end - crt->tbs.p); /* * Version ::= INTEGER { v1(0), v2(1), v3(2) } @@ -1201,7 +1188,7 @@ static int x509_crt_parse_der_core(mbedtls_x509_crt *crt, return ret; } - crt->issuer_raw.len = p - crt->issuer_raw.p; + crt->issuer_raw.len = (size_t) (p - crt->issuer_raw.p); /* * Validity ::= SEQUENCE { @@ -1231,7 +1218,7 @@ static int x509_crt_parse_der_core(mbedtls_x509_crt *crt, return ret; } - crt->subject_raw.len = p - crt->subject_raw.p; + crt->subject_raw.len = (size_t) (p - crt->subject_raw.p); /* * SubjectPublicKeyInfo @@ -1241,7 +1228,7 @@ static int x509_crt_parse_der_core(mbedtls_x509_crt *crt, mbedtls_x509_crt_free(crt); return ret; } - crt->pk_raw.len = p - crt->pk_raw.p; + crt->pk_raw.len = (size_t) (p - crt->pk_raw.p); /* * issuerUniqueID [1] IMPLICIT UniqueIdentifier OPTIONAL, @@ -3307,4 +3294,12 @@ void mbedtls_x509_crt_restart_free(mbedtls_x509_crt_restart_ctx *ctx) } #endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ +int mbedtls_x509_crt_get_ca_istrue(const mbedtls_x509_crt *crt) +{ + if ((crt->ext_types & MBEDTLS_X509_EXT_BASIC_CONSTRAINTS) != 0) { + return crt->MBEDTLS_PRIVATE(ca_istrue); + } + return MBEDTLS_ERR_X509_INVALID_EXTENSIONS; +} + #endif /* MBEDTLS_X509_CRT_PARSE_C */ diff --git a/ra/fsp/src/rm_mcuboot_port/rm_mcuboot_port.c b/ra/fsp/src/rm_mcuboot_port/rm_mcuboot_port.c index 638bb6c7b..b1cc01523 100644 --- a/ra/fsp/src/rm_mcuboot_port/rm_mcuboot_port.c +++ b/ra/fsp/src/rm_mcuboot_port/rm_mcuboot_port.c @@ -6,7 +6,18 @@ #include "flash_map_backend/flash_map_backend.h" #include "sysflash/sysflash.h" #if RM_MCUBOOT_DUAL_BANK_ENABLED - #include "r_flash_hp.h" + #if BSP_FEATURE_FLASH_HP_VERSION > 0 + #include "r_flash_hp.h" + #else + #include "r_flash_lp.h" + #endif +#endif + +/* Definitions for different flash implementation. */ +#if BSP_FEATURE_FLASH_HP_VERSION > 0 + #define R_FLASH_BankSwap R_FLASH_HP_BankSwap +#else + #define R_FLASH_BankSwap R_FLASH_LP_BankSwap #endif #if defined(__GNUC__) && !defined(__ARMCC_VERSION) && !defined(__clang_analyzer__) @@ -46,13 +57,13 @@ void RM_MCUBOOT_PORT_BootApp (struct boot_rsp * rsp) { uint32_t vector_table = rsp->br_image_off + rsp->br_hdr->ih_hdr_size; #if RM_MCUBOOT_DUAL_BANK_ENABLED -#if BSP_FEATURE_CRYPTO_HAS_RSIP7 + #if BSP_FEATURE_CRYPTO_HAS_RSIP7 if (vector_table & (BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START - BSP_FEATURE_FLASH_CODE_FLASH_START)) -#else - if (vector_table & BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START) -#endif + #else + if (vector_table & (BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START | BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START)) + #endif { - R_FLASH_HP_BankSwap(gp_mcuboot_flash_ctrl); + R_FLASH_BankSwap(gp_mcuboot_flash_ctrl); /* Reset the MCU to swap to the other bank */ __NVIC_SystemReset(); diff --git a/ra/fsp/src/rm_motor_120_driver/rm_motor_120_driver.c b/ra/fsp/src/rm_motor_120_driver/rm_motor_120_driver.c index 0cbca822a..e18696694 100644 --- a/ra/fsp/src/rm_motor_120_driver/rm_motor_120_driver.c +++ b/ra/fsp/src/rm_motor_120_driver/rm_motor_120_driver.c @@ -133,7 +133,7 @@ fsp_err_t RM_MOTOR_120_DRIVER_Open (motor_120_driver_ctrl_t * const p_ctrl, moto motor_120_driver_extended_cfg_t * p_extended_cfg = (motor_120_driver_extended_cfg_t *) p_cfg->p_extend; #if MOTOR_120_DRIVER_CFG_PARAM_CHECKING_ENABLE - MOTOR_120_DRIVER_ERROR_RETURN(p_extended_cfg->u4_pwm_carrier_freq > 0, FSP_ERR_INVALID_ARGUMENT); + MOTOR_120_DRIVER_ERROR_RETURN(p_extended_cfg->pwm_carrier_freq > 0, FSP_ERR_INVALID_ARGUMENT); MOTOR_120_DRIVER_ERROR_RETURN(p_extended_cfg->f_ad_resolution > 0, FSP_ERR_INVALID_ARGUMENT); MOTOR_120_DRIVER_ERROR_RETURN(p_extended_cfg->u4_deadtime > 0, FSP_ERR_INVALID_ARGUMENT); MOTOR_120_DRIVER_ERROR_RETURN(p_extended_cfg->u4_pwm_timer_freq > 0, FSP_ERR_INVALID_ARGUMENT); @@ -147,7 +147,7 @@ fsp_err_t RM_MOTOR_120_DRIVER_Open (motor_120_driver_ctrl_t * const p_ctrl, moto p_instance_ctrl->u4_carrier_base = (uint32_t) ((float) p_extended_cfg->u4_pwm_timer_freq * (float) MOTOR_120_DRIVER_KHZ_TRANS / - (float) p_extended_cfg->u4_pwm_carrier_freq * MOTOR_120_DRIVER_DEV_HALF); + p_extended_cfg->pwm_carrier_freq * MOTOR_120_DRIVER_DEV_HALF); p_instance_ctrl->u4_deadtime_count = p_extended_cfg->u4_deadtime; p_instance_ctrl->st_modulation = p_extended_cfg->mod_param; @@ -1383,7 +1383,7 @@ fsp_err_t RM_MOTOR_120_DRIVER_ParameterUpdate (motor_120_driver_ctrl_t * const motor_120_driver_extended_cfg_t * p_extended_cfg = (motor_120_driver_extended_cfg_t *) p_cfg->p_extend; #if MOTOR_120_DRIVER_CFG_PARAM_CHECKING_ENABLE - MOTOR_120_DRIVER_ERROR_RETURN(p_extended_cfg->u4_pwm_carrier_freq > 0, FSP_ERR_INVALID_ARGUMENT); + MOTOR_120_DRIVER_ERROR_RETURN(p_extended_cfg->pwm_carrier_freq > 0, FSP_ERR_INVALID_ARGUMENT); MOTOR_120_DRIVER_ERROR_RETURN(p_extended_cfg->f_ad_resolution > 0.0F, FSP_ERR_INVALID_ARGUMENT); MOTOR_120_DRIVER_ERROR_RETURN(p_extended_cfg->u4_deadtime > 0, FSP_ERR_INVALID_ARGUMENT); MOTOR_120_DRIVER_ERROR_RETURN(p_extended_cfg->u4_pwm_timer_freq > 0, FSP_ERR_INVALID_ARGUMENT); @@ -1393,7 +1393,7 @@ fsp_err_t RM_MOTOR_120_DRIVER_ParameterUpdate (motor_120_driver_ctrl_t * const p_instance_ctrl->u4_carrier_base = (uint32_t) ((float) p_extended_cfg->u4_pwm_timer_freq * (float) MOTOR_120_DRIVER_KHZ_TRANS / - (float) p_extended_cfg->u4_pwm_carrier_freq * MOTOR_120_DRIVER_DEV_HALF); + p_extended_cfg->pwm_carrier_freq * MOTOR_120_DRIVER_DEV_HALF); p_instance_ctrl->u4_deadtime_count = p_extended_cfg->u4_deadtime; p_instance_ctrl->st_modulation = p_extended_cfg->mod_param; diff --git a/ra/fsp/src/rm_motor_driver/rm_motor_driver.c b/ra/fsp/src/rm_motor_driver/rm_motor_driver.c index e9bc222f4..c17f786d2 100644 --- a/ra/fsp/src/rm_motor_driver/rm_motor_driver.c +++ b/ra/fsp/src/rm_motor_driver/rm_motor_driver.c @@ -160,7 +160,7 @@ fsp_err_t RM_MOTOR_DRIVER_Open (motor_driver_ctrl_t * const p_ctrl, motor_driver p_instance_ctrl->u2_carrier_base = (uint16_t) (p_extended_cfg->u2_pwm_timer_freq * MOTOR_DRIVER_KHZ_TRANS / - p_extended_cfg->u2_pwm_carrier_freq / (uint16_t) MOTOR_DRIVER_MULTIPLE_TWO); + p_extended_cfg->pwm_carrier_freq / (uint16_t) MOTOR_DRIVER_MULTIPLE_TWO); p_instance_ctrl->u2_deadtime_count = p_extended_cfg->u2_deadtime; rm_motor_driver_reset(p_instance_ctrl); @@ -522,7 +522,7 @@ fsp_err_t RM_MOTOR_DRIVER_ParameterUpdate (motor_driver_ctrl_t * const p_ctrl, m p_instance_ctrl->u2_carrier_base = (uint16_t) (p_extended_cfg->u2_pwm_timer_freq * MOTOR_DRIVER_KHZ_TRANS / - p_extended_cfg->u2_pwm_carrier_freq / (uint16_t) MOTOR_DRIVER_MULTIPLE_TWO); + p_extended_cfg->pwm_carrier_freq / (uint16_t) MOTOR_DRIVER_MULTIPLE_TWO); p_instance_ctrl->u2_deadtime_count = p_extended_cfg->u2_deadtime; p_instance_ctrl->st_modulation = p_extended_cfg->mod_param; diff --git a/ra/fsp/src/rm_psa_crypto/aes_alt.c b/ra/fsp/src/rm_psa_crypto/aes_alt.c index 6b815ea07..41e8672bc 100644 --- a/ra/fsp/src/rm_psa_crypto/aes_alt.c +++ b/ra/fsp/src/rm_psa_crypto/aes_alt.c @@ -2,7 +2,7 @@ * FIPS-197 compliant AES implementation * * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -37,23 +37,15 @@ #include "mbedtls/platform_util.h" #include "mbedtls/error.h" -#if defined(MBEDTLS_ARCH_IS_ARM64) -#if !defined(MBEDTLS_AESCE_C) && defined(MBEDTLS_AES_USE_HARDWARE_ONLY) -#error "MBEDTLS_AES_USE_HARDWARE_ONLY defined, but not all prerequisites" -#endif -#endif - -#if defined(MBEDTLS_ARCH_IS_X64) -#if !defined(MBEDTLS_AESNI_C) && defined(MBEDTLS_AES_USE_HARDWARE_ONLY) +#if defined(MBEDTLS_AES_USE_HARDWARE_ONLY) +#if !((defined(MBEDTLS_ARCH_IS_ARMV8_A) && defined(MBEDTLS_AESCE_C)) || \ + (defined(MBEDTLS_ARCH_IS_X64) && defined(MBEDTLS_AESNI_C)) || \ + (defined(MBEDTLS_ARCH_IS_X86) && defined(MBEDTLS_AESNI_C))) #error "MBEDTLS_AES_USE_HARDWARE_ONLY defined, but not all prerequisites" #endif #endif #if defined(MBEDTLS_ARCH_IS_X86) -#if defined(MBEDTLS_AES_USE_HARDWARE_ONLY) && !defined(MBEDTLS_AESNI_C) -#error "MBEDTLS_AES_USE_HARDWARE_ONLY defined, but not all prerequisites" -#endif - #if defined(MBEDTLS_PADLOCK_C) #if !defined(MBEDTLS_HAVE_ASM) #error "MBEDTLS_PADLOCK_C defined, but not all prerequisites" @@ -72,11 +64,21 @@ #include "mbedtls/aesni.h" #endif #if defined(MBEDTLS_AESCE_C) -#include "aesce.h" +#include "aesce.h" #endif #include "mbedtls/platform.h" +#include "ctr.h" +/* + * This is a convenience shorthand macro to check if we need reverse S-box and + * reverse tables. It's private and only defined in this file. + */ +#if (!defined(MBEDTLS_AES_DECRYPT_ALT) || \ + (!defined(MBEDTLS_AES_SETKEY_DEC_ALT) && !defined(MBEDTLS_AES_USE_HARDWARE_ONLY))) && \ + !defined(MBEDTLS_BLOCK_CIPHER_NO_DECRYPT) +#define MBEDTLS_AES_NEED_REVERSE_TABLES +#endif #if defined(MBEDTLS_AES_ALT) /* @@ -110,9 +112,7 @@ static int aes_padlock_ace = -1; /* * Forward S-box */ - #if !defined(MBEDTLS_AES_ENCRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_ENC_ALT) || \ - !defined(MBEDTLS_AES_SETKEY_DEC_ALT) -static const unsigned char FSb[256] = +MBEDTLS_MAYBE_UNUSED static const unsigned char FSb[256] = { 0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5, 0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76, @@ -147,8 +147,6 @@ static const unsigned char FSb[256] = 0x8C, 0xA1, 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68, 0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16 }; -#endif /* !defined(MBEDTLS_AES_ENCRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_ENC_ALT) || \ - !defined(MBEDTLS_AES_SETKEY_DEC_ALT) */ /* * Forward tables @@ -220,15 +218,12 @@ static const unsigned char FSb[256] = V(C3, 41, 41, 82), V(B0, 99, 99, 29), V(77, 2D, 2D, 5A), V(11, 0F, 0F, 1E), \ V(CB, B0, B0, 7B), V(FC, 54, 54, A8), V(D6, BB, BB, 6D), V(3A, 16, 16, 2C) -#if !defined(MBEDTLS_AES_ENCRYPT_ALT) #define V(a, b, c, d) 0x##a##b##c##d -static const uint32_t FT0[256] = { FT }; +MBEDTLS_MAYBE_UNUSED static const uint32_t FT0[256] = { FT }; #undef V -#if !defined(MBEDTLS_AES_FEWER_TABLES) - #define V(a, b, c, d) 0x##b##c##d##a -static const uint32_t FT1[256] = { FT }; +MBEDTLS_MAYBE_UNUSED static const uint32_t FT1[256] = { FT }; #undef V #define V(a, b, c, d) 0x##c##d##a##b @@ -239,17 +234,12 @@ static const uint32_t FT2[256] = { FT }; static const uint32_t FT3[256] = { FT }; #undef V -#endif /* !MBEDTLS_AES_FEWER_TABLES */ - -#endif /* !defined(MBEDTLS_AES_ENCRYPT_ALT) */ - #undef FT -#if !defined(MBEDTLS_AES_DECRYPT_ALT) /* * Reverse S-box */ -static const unsigned char RSb[256] = +MBEDTLS_MAYBE_UNUSED static const unsigned char RSb[256] = { 0x52, 0x09, 0x6A, 0xD5, 0x30, 0x36, 0xA5, 0x38, 0xBF, 0x40, 0xA3, 0x9E, 0x81, 0xF3, 0xD7, 0xFB, @@ -284,7 +274,6 @@ static const unsigned char RSb[256] = 0x17, 0x2B, 0x04, 0x7E, 0xBA, 0x77, 0xD6, 0x26, 0xE1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0C, 0x7D }; -#endif /* defined(MBEDTLS_AES_DECRYPT_ALT)) */ /* * Reverse tables @@ -356,84 +345,60 @@ static const unsigned char RSb[256] = V(71, 01, A8, 39), V(DE, B3, 0C, 08), V(9C, E4, B4, D8), V(90, C1, 56, 64), \ V(61, 84, CB, 7B), V(70, B6, 32, D5), V(74, 5C, 6C, 48), V(42, 57, B8, D0) -#if !defined(MBEDTLS_AES_DECRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_DEC_ALT) #define V(a, b, c, d) 0x##a##b##c##d -static const uint32_t RT0[256] = { RT }; +MBEDTLS_MAYBE_UNUSED static const uint32_t RT0[256] = { RT }; #undef V -#if !defined(MBEDTLS_AES_FEWER_TABLES) - #define V(a, b, c, d) 0x##b##c##d##a -static const uint32_t RT1[256] = { RT }; +MBEDTLS_MAYBE_UNUSED static const uint32_t RT1[256] = { RT }; #undef V #define V(a, b, c, d) 0x##c##d##a##b -static const uint32_t RT2[256] = { RT }; +MBEDTLS_MAYBE_UNUSED static const uint32_t RT2[256] = { RT }; #undef V #define V(a, b, c, d) 0x##d##a##b##c -static const uint32_t RT3[256] = { RT }; +MBEDTLS_MAYBE_UNUSED static const uint32_t RT3[256] = { RT }; #undef V -#endif /* !MBEDTLS_AES_FEWER_TABLES */ - -#endif /* !defined(MBEDTLS_AES_DECRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_DEC_ALT) */ - #undef RT -#if !defined(MBEDTLS_AES_SETKEY_ENC_ALT) /* * Round constants */ -static const uint32_t RCON[10] = +MBEDTLS_MAYBE_UNUSED static const uint32_t round_constants[10] = { 0x00000001, 0x00000002, 0x00000004, 0x00000008, 0x00000010, 0x00000020, 0x00000040, 0x00000080, 0x0000001B, 0x00000036 }; -#endif /* !defined(MBEDTLS_AES_SETKEY_ENC_ALT) */ #else /* MBEDTLS_AES_ROM_TABLES */ /* * Forward S-box & tables */ -#if !defined(MBEDTLS_AES_ENCRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_ENC_ALT) || \ - !defined(MBEDTLS_AES_SETKEY_DEC_ALT) -static unsigned char FSb[256]; -#endif /* !defined(MBEDTLS_AES_ENCRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_ENC_ALT) || \ - !defined(MBEDTLS_AES_SETKEY_DEC_ALT) */ -#if !defined(MBEDTLS_AES_ENCRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_ENC_ALT) -static uint32_t FT0[256]; -#if !defined(MBEDTLS_AES_FEWER_TABLES) -static uint32_t FT1[256]; -static uint32_t FT2[256]; -static uint32_t FT3[256]; -#endif /* !MBEDTLS_AES_FEWER_TABLES */ -#endif /* !defined(MBEDTLS_AES_ENCRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_ENC_ALT) */ +MBEDTLS_MAYBE_UNUSED static unsigned char FSb[256]; +MBEDTLS_MAYBE_UNUSED static uint32_t FT0[256]; +MBEDTLS_MAYBE_UNUSED static uint32_t FT1[256]; +MBEDTLS_MAYBE_UNUSED static uint32_t FT2[256]; +MBEDTLS_MAYBE_UNUSED static uint32_t FT3[256]; /* * Reverse S-box & tables */ -#if !(defined(MBEDTLS_AES_SETKEY_ENC_ALT) && defined(MBEDTLS_AES_DECRYPT_ALT)) -static unsigned char RSb[256]; -#endif /* !(defined(MBEDTLS_AES_SETKEY_ENC_ALT) && defined(MBEDTLS_AES_DECRYPT_ALT)) */ +MBEDTLS_MAYBE_UNUSED static unsigned char RSb[256]; -#if !defined(MBEDTLS_AES_DECRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_DEC_ALT) -static uint32_t RT0[256]; -#if !defined(MBEDTLS_AES_FEWER_TABLES) -static uint32_t RT1[256]; -static uint32_t RT2[256]; -static uint32_t RT3[256]; -#endif /* !MBEDTLS_AES_FEWER_TABLES */ -#endif /* !defined(MBEDTLS_AES_DECRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_DEC_ALT) */ +MBEDTLS_MAYBE_UNUSED static uint32_t RT0[256]; +MBEDTLS_MAYBE_UNUSED static uint32_t RT1[256]; +MBEDTLS_MAYBE_UNUSED static uint32_t RT2[256]; +MBEDTLS_MAYBE_UNUSED static uint32_t RT3[256]; -#if !defined(MBEDTLS_AES_SETKEY_ENC_ALT) /* * Round constants */ -static uint32_t RCON[10]; +MBEDTLS_MAYBE_UNUSED static uint32_t round_constants[10]; /* * Tables generation code @@ -442,9 +407,9 @@ static uint32_t RCON[10]; #define XTIME(x) (((x) << 1) ^ (((x) & 0x80) ? 0x1B : 0x00)) #define MUL(x, y) (((x) && (y)) ? pow[(log[(x)]+log[(y)]) % 255] : 0) -static int aes_init_done = 0; +MBEDTLS_MAYBE_UNUSED static int aes_init_done = 0; -static void aes_gen_tables(void) +MBEDTLS_MAYBE_UNUSED static void aes_gen_tables(void) { int i; uint8_t x, y, z; @@ -464,7 +429,7 @@ static void aes_gen_tables(void) * calculate the round constants */ for (i = 0, x = 1; i < 10; i++) { - RCON[i] = x; + round_constants[i] = x; x = XTIME(x); } @@ -472,7 +437,9 @@ static void aes_gen_tables(void) * generate the forward and reverse S-boxes */ FSb[0x00] = 0x63; +#if defined(MBEDTLS_AES_NEED_REVERSE_TABLES) RSb[0x63] = 0x00; +#endif for (i = 1; i < 256; i++) { x = pow[255 - log[i]]; @@ -484,7 +451,9 @@ static void aes_gen_tables(void) x ^= y ^ 0x63; FSb[i] = x; +#if defined(MBEDTLS_AES_NEED_REVERSE_TABLES) RSb[x] = (unsigned char) i; +#endif } /* @@ -506,9 +475,9 @@ static void aes_gen_tables(void) FT3[i] = ROTL8(FT2[i]); #endif /* !MBEDTLS_AES_FEWER_TABLES */ +#if defined(MBEDTLS_AES_NEED_REVERSE_TABLES) x = RSb[i]; -#if !defined(MBEDTLS_AES_DECRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_DEC_ALT) RT0[i] = ((uint32_t) MUL(0x0E, x)) ^ ((uint32_t) MUL(0x09, x) << 8) ^ ((uint32_t) MUL(0x0D, x) << 16) ^ @@ -519,12 +488,10 @@ static void aes_gen_tables(void) RT2[i] = ROTL8(RT1[i]); RT3[i] = ROTL8(RT2[i]); #endif /* !MBEDTLS_AES_FEWER_TABLES */ -#endif /* !defined(MBEDTLS_AES_DECRYPT_ALT) || !defined(MBEDTLS_AES_SETKEY_DEC_ALT) */ +#endif /* MBEDTLS_AES_NEED_REVERSE_TABLES */ } } -#endif /* !defined(MBEDTLS_AES_SETKEY_ENC_ALT) */ - #undef ROTL8 #endif /* MBEDTLS_AES_ROM_TABLES */ @@ -604,9 +571,7 @@ void mbedtls_aes_xts_free(mbedtls_aes_xts_context *ctx) #define MAY_NEED_TO_ALIGN #endif -#if defined(MAY_NEED_TO_ALIGN) || !defined(MBEDTLS_AES_SETKEY_DEC_ALT) || \ - !defined(MBEDTLS_AES_SETKEY_ENC_ALT) -static unsigned mbedtls_aes_rk_offset(uint32_t *buf) +MBEDTLS_MAYBE_UNUSED static unsigned mbedtls_aes_rk_offset(uint32_t *buf) { #if defined(MAY_NEED_TO_ALIGN) int align_16_bytes = 0; @@ -642,8 +607,6 @@ static unsigned mbedtls_aes_rk_offset(uint32_t *buf) return 0; } -#endif /* defined(MAY_NEED_TO_ALIGN) || !defined(MBEDTLS_AES_SETKEY_DEC_ALT) || \ - !defined(MBEDTLS_AES_SETKEY_ENC_ALT) */ #ifdef FSP_NOT_DEFINED /* @@ -695,7 +658,7 @@ int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key, case 10: for (unsigned int i = 0; i < 10; i++, RK += 4) { - RK[4] = RK[0] ^ RCON[i] ^ + RK[4] = RK[0] ^ round_constants[i] ^ ((uint32_t) FSb[MBEDTLS_BYTE_1(RK[3])]) ^ ((uint32_t) FSb[MBEDTLS_BYTE_2(RK[3])] << 8) ^ ((uint32_t) FSb[MBEDTLS_BYTE_3(RK[3])] << 16) ^ @@ -711,7 +674,7 @@ int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key, case 12: for (unsigned int i = 0; i < 8; i++, RK += 6) { - RK[6] = RK[0] ^ RCON[i] ^ + RK[6] = RK[0] ^ round_constants[i] ^ ((uint32_t) FSb[MBEDTLS_BYTE_1(RK[5])]) ^ ((uint32_t) FSb[MBEDTLS_BYTE_2(RK[5])] << 8) ^ ((uint32_t) FSb[MBEDTLS_BYTE_3(RK[5])] << 16) ^ @@ -728,7 +691,7 @@ int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key, case 14: for (unsigned int i = 0; i < 7; i++, RK += 8) { - RK[8] = RK[0] ^ RCON[i] ^ + RK[8] = RK[0] ^ round_constants[i] ^ ((uint32_t) FSb[MBEDTLS_BYTE_1(RK[7])]) ^ ((uint32_t) FSb[MBEDTLS_BYTE_2(RK[7])] << 8) ^ ((uint32_t) FSb[MBEDTLS_BYTE_3(RK[7])] << 16) ^ @@ -760,7 +723,7 @@ int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key, /* * AES key schedule (decryption) */ -#if !defined(MBEDTLS_AES_SETKEY_DEC_ALT) +#if !defined(MBEDTLS_AES_SETKEY_DEC_ALT) && !defined(MBEDTLS_BLOCK_CIPHER_NO_DECRYPT) int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits) { @@ -770,7 +733,7 @@ int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, const unsigned char *key, int ret; mbedtls_aes_context cty; uint32_t *RK; - + mbedtls_aes_init(&cty); @@ -829,6 +792,7 @@ SK -= 8; return ret; } +#endif /* !MBEDTLS_AES_SETKEY_DEC_ALT && !MBEDTLS_BLOCK_CIPHER_NO_DECRYPT */ #if defined(MBEDTLS_CIPHER_MODE_XTS) static int mbedtls_aes_xts_decode_keys(const unsigned char *key, @@ -903,7 +867,6 @@ int mbedtls_aes_xts_setkey_dec(mbedtls_aes_xts_context *ctx, return mbedtls_aes_setkey_dec(&ctx->crypt, key1, key1bits); } #endif /* MBEDTLS_CIPHER_MODE_XTS */ -#endif /* !MBEDTLS_AES_SETKEY_DEC_ALT */ #define AES_FROUND(X0, X1, X2, X3, Y0, Y1, Y2, Y3) \ do \ @@ -1010,8 +973,7 @@ int mbedtls_internal_aes_encrypt(mbedtls_aes_context *ctx, MBEDTLS_PUT_UINT32_LE(t.X[3], output, 12); mbedtls_platform_zeroize(&t, sizeof(t)); - - mbedtls_platform_zeroize(&t, sizeof(t)); + return 0; } #endif /* !MBEDTLS_AES_ENCRYPT_ALT */ @@ -1019,7 +981,7 @@ int mbedtls_internal_aes_encrypt(mbedtls_aes_context *ctx, /* * AES-ECB block decryption */ -#if !defined(MBEDTLS_AES_DECRYPT_ALT) +#if !defined(MBEDTLS_AES_DECRYPT_ALT) && !defined(MBEDTLS_BLOCK_CIPHER_NO_DECRYPT) int mbedtls_internal_aes_decrypt(mbedtls_aes_context *ctx, const unsigned char input[16], unsigned char output[16]) @@ -1076,9 +1038,8 @@ int mbedtls_internal_aes_decrypt(mbedtls_aes_context *ctx, return 0; } -#endif /* !MBEDTLS_AES_DECRYPT_ALT */ +#endif /* !MBEDTLS_AES_DECRYPT_ALT && !MBEDTLS_BLOCK_CIPHER_NO_DECRYPT */ -#if defined(MAY_NEED_TO_ALIGN) /* VIA Padlock and our intrinsics-based implementation of AESNI require * the round keys to be aligned on a 16-byte boundary. We take care of this * before creating them, but the AES context may have moved (this can happen @@ -1086,7 +1047,7 @@ int mbedtls_internal_aes_decrypt(mbedtls_aes_context *ctx, * calls it might have a different alignment with respect to 16-byte memory. * So we may need to realign. */ -static void aes_maybe_realign(mbedtls_aes_context *ctx) +MBEDTLS_MAYBE_UNUSED static void aes_maybe_realign(mbedtls_aes_context *ctx) { unsigned new_offset = mbedtls_aes_rk_offset(ctx->buf); if (new_offset != ctx->rk_offset) { @@ -1096,7 +1057,6 @@ static void aes_maybe_realign(mbedtls_aes_context *ctx) ctx->rk_offset = new_offset; } } -#endif #endif // FSP_NOT_DEFINED /* @@ -1134,13 +1094,15 @@ int mbedtls_aes_crypt_ecb(mbedtls_aes_context *ctx, #endif #if !defined(MBEDTLS_AES_USE_HARDWARE_ONLY) - if (mode == MBEDTLS_AES_ENCRYPT) { - return mbedtls_internal_aes_encrypt(ctx, input, output); - } else { +#if !defined(MBEDTLS_BLOCK_CIPHER_NO_DECRYPT) + if (mode == MBEDTLS_AES_DECRYPT) { return mbedtls_internal_aes_decrypt(ctx, input, output); - } + } else #endif - + { + return mbedtls_internal_aes_encrypt(ctx, input, output); + } +#endif /* !MBEDTLS_AES_USE_HARDWARE_ONLY */ } #if defined(MBEDTLS_CIPHER_MODE_CBC) @@ -1155,6 +1117,8 @@ int mbedtls_aes_crypt_cbc(mbedtls_aes_context *ctx, const unsigned char *input, unsigned char *output) { + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + unsigned char temp[16]; if (mode != MBEDTLS_AES_ENCRYPT && mode != MBEDTLS_AES_DECRYPT) { return MBEDTLS_ERR_AES_BAD_INPUT_DATA; @@ -1566,6 +1530,7 @@ int mbedtls_aes_crypt_ctr(mbedtls_aes_context *ctx, * * http://csrc.nist.gov/archive/aes/rijndael/rijndael-vals.zip */ +#if !defined(MBEDTLS_BLOCK_CIPHER_NO_DECRYPT) static const unsigned char aes_test_ecb_dec[][16] = { { 0x44, 0x41, 0x6A, 0xC2, 0xD1, 0xF5, 0x3C, 0x58, @@ -1577,6 +1542,7 @@ static const unsigned char aes_test_ecb_dec[][16] = 0x1F, 0x6F, 0x56, 0x58, 0x5D, 0x8A, 0x4A, 0xDE } #endif }; +#endif static const unsigned char aes_test_ecb_enc[][16] = { @@ -1920,7 +1886,7 @@ int mbedtls_aes_self_test(int verbose) mbedtls_aes_init(&ctx); if (verbose != 0) { -#if defined(MBEDTLS_AES_ALT) +#if !defined(MBEDTLS_AES_ALT) mbedtls_printf(" AES note: alternative implementation.\n"); #else /* MBEDTLS_AES_ALT */ #if defined(MBEDTLS_AESNI_HAVE_CODE) @@ -1958,7 +1924,7 @@ int mbedtls_aes_self_test(int verbose) */ { static const int num_tests = - sizeof(aes_test_ecb_dec) / sizeof(*aes_test_ecb_dec); + sizeof(aes_test_ecb_enc) / sizeof(*aes_test_ecb_enc); for (i = 0; i < num_tests << 1; i++) { u = i >> 1; @@ -1969,13 +1935,24 @@ int mbedtls_aes_self_test(int verbose) mbedtls_printf(" AES-ECB-%3u (%s): ", keybits, (mode == MBEDTLS_AES_DECRYPT) ? "dec" : "enc"); } +#if defined(MBEDTLS_BLOCK_CIPHER_NO_DECRYPT) + if (mode == MBEDTLS_AES_DECRYPT) { + if (verbose != 0) { + mbedtls_printf("skipped\n"); + } + continue; + } +#endif memset(buf, 0, 16); +#if !defined(MBEDTLS_BLOCK_CIPHER_NO_DECRYPT) if (mode == MBEDTLS_AES_DECRYPT) { ret = mbedtls_aes_setkey_dec(&ctx, key, keybits); aes_tests = aes_test_ecb_dec[u]; - } else { + } else +#endif + { ret = mbedtls_aes_setkey_enc(&ctx, key, keybits); aes_tests = aes_test_ecb_enc[u]; } diff --git a/ra/fsp/src/rm_psa_crypto/aes_alt_process.c b/ra/fsp/src/rm_psa_crypto/aes_alt_process.c index 1580f9dc6..8787425b7 100644 --- a/ra/fsp/src/rm_psa_crypto/aes_alt_process.c +++ b/ra/fsp/src/rm_psa_crypto/aes_alt_process.c @@ -136,7 +136,7 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un unsigned int local_keybits = 0; const unsigned char * p_internal_key = key; #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || \ - BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 + BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 || BSP_FEATURE_CRYPTO_HAS_RSIP_E11A /* Create storage to hold the generated OEM key index. Size = Largest key size possible. */ uint8_t encrypted_aes_key[SIZE_AES_192BIT_KEYLEN_BYTES_WRAPPED] = {0}; @@ -146,7 +146,7 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un case SIZE_AES_128BIT_KEYLEN_BITS: { #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || \ - BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 + BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 || BSP_FEATURE_CRYPTO_HAS_RSIP_E11A local_keybits = SIZE_AES_128BIT_KEYLEN_BITS_WRAPPED; ctx->nr = 10; if (false == (bool) ctx->vendor_ctx) @@ -175,10 +175,10 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un break; } -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) + #if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) case SIZE_AES_192BIT_KEYLEN_BITS: { - #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || \ + #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || \ BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 local_keybits = SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED; ctx->nr = 12; @@ -194,7 +194,7 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un ctx->vendor_ctx = (bool *) true; } - #else + #else if (true == (bool) ctx->vendor_ctx) { local_keybits = SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED; @@ -204,14 +204,15 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un local_keybits = keybits; } ctx->nr = 12; - #endif + #endif break; } case SIZE_AES_256BIT_KEYLEN_BITS: { - #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || \ - BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 + #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || \ + BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 || BSP_FEATURE_CRYPTO_HAS_RSIP_E11A + local_keybits = SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED; ctx->nr = 14; if (false == (bool) ctx->vendor_ctx) @@ -226,7 +227,7 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un ctx->vendor_ctx = (bool *) true; } - #else + #else if (true == (bool) ctx->vendor_ctx) { local_keybits = SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED; @@ -236,11 +237,11 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un local_keybits = keybits; } ctx->nr = 14; - #endif + #endif break; } -#endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ + #endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ default: @@ -433,8 +434,8 @@ int mbedtls_internal_aes_encrypt (mbedtls_aes_context * ctx, const unsigned char if (ctx->nr == 10) { - err = - HW_SCE_Aes128EncryptDecryptInitSub(&indata_key_type, &indata_cmd, ctx->buf, dummy_iv); + err = HW_SCE_Aes128EncryptDecryptInitSubAdaptor(&indata_key_type, &indata_cmd, ctx->buf, NULL, dummy_iv); + if (err == FSP_SUCCESS) { HW_SCE_Aes128EncryptDecryptUpdateSub((uint32_t *) &input[0], (uint32_t *) &output[0], SIZE_AES_BLOCK_WORDS); @@ -443,8 +444,8 @@ int mbedtls_internal_aes_encrypt (mbedtls_aes_context * ctx, const unsigned char err = HW_SCE_Aes128EncryptDecryptFinalSub(); } -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) - #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 + #if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) + #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 else if (ctx->nr == 12) { err = HW_SCE_Aes192EncryptDecryptInitSub(&indata_cmd, ctx->buf, dummy_iv); @@ -455,10 +456,10 @@ int mbedtls_internal_aes_encrypt (mbedtls_aes_context * ctx, const unsigned char err = HW_SCE_Aes192EncryptDecryptFinalSub(); } - #endif + #endif else if (ctx->nr == 14) { - err = HW_SCE_Aes256EncryptDecryptInitSub(&indata_key_type, &indata_cmd, ctx->buf, dummy_iv); + err = HW_SCE_Aes256EncryptDecryptInitSubAdaptor(&indata_key_type, &indata_cmd, ctx->buf, NULL, dummy_iv); if (err == FSP_SUCCESS) { HW_SCE_Aes256EncryptDecryptUpdateSub((uint32_t *) &input[0], (uint32_t *) &output[0], SIZE_AES_BLOCK_WORDS); @@ -466,7 +467,7 @@ int mbedtls_internal_aes_encrypt (mbedtls_aes_context * ctx, const unsigned char err = HW_SCE_Aes256EncryptDecryptFinalSub(); } -#endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ + #endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ else { @@ -497,7 +498,11 @@ int mbedtls_internal_aes_encrypt_cbc (mbedtls_aes_context * ctx, { if (SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT == ctx->state) { - err = HW_SCE_Aes128EncryptDecryptInitSub(&indata_key_type, &indata_cmd, ctx->buf, (uint32_t *) &iv[0]); + err = HW_SCE_Aes128EncryptDecryptInitSubAdaptor(&indata_key_type, + &indata_cmd, + ctx->buf, + NULL, + (uint32_t *) &iv[0]); if (FSP_SUCCESS != err) { return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; @@ -509,7 +514,7 @@ int mbedtls_internal_aes_encrypt_cbc (mbedtls_aes_context * ctx, HW_SCE_Aes128EncryptDecryptUpdateSub((uint32_t *) &input[0], (uint32_t *) &output[0], (length / 4U)); } -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) + #if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) else if (ctx->nr == 12) { if (SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT == ctx->state) @@ -529,7 +534,12 @@ int mbedtls_internal_aes_encrypt_cbc (mbedtls_aes_context * ctx, { if (SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT == ctx->state) { - err = HW_SCE_Aes256EncryptDecryptInitSub(&indata_key_type, &indata_cmd, ctx->buf, (uint32_t *) &iv[0]); + err = HW_SCE_Aes256EncryptDecryptInitSubAdaptor(&indata_key_type, + &indata_cmd, + ctx->buf, + NULL, + (uint32_t *) &iv[0]); + if (FSP_SUCCESS != err) { return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; @@ -540,7 +550,7 @@ int mbedtls_internal_aes_encrypt_cbc (mbedtls_aes_context * ctx, HW_SCE_Aes256EncryptDecryptUpdateSub((uint32_t *) &input[0], (uint32_t *) &output[0], (length / 4U)); } -#endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ + #endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ else { @@ -692,7 +702,8 @@ int mbedtls_internal_aes_decrypt (mbedtls_aes_context * ctx, const unsigned char if (ctx->nr == 10) { - err = HW_SCE_Aes128EncryptDecryptInitSub(&indata_key_type, &indata_cmd, ctx->buf, dummy_iv); + err = HW_SCE_Aes128EncryptDecryptInitSubAdaptor(&indata_key_type, &indata_cmd, ctx->buf, NULL, dummy_iv); + if (err == FSP_SUCCESS) { HW_SCE_Aes128EncryptDecryptUpdateSub((uint32_t *) &input[0], (uint32_t *) &output[0], SIZE_AES_BLOCK_WORDS); @@ -701,8 +712,8 @@ int mbedtls_internal_aes_decrypt (mbedtls_aes_context * ctx, const unsigned char err = HW_SCE_Aes128EncryptDecryptFinalSub(); } -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) - #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 + #if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) + #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 else if (ctx->nr == 12) { err = HW_SCE_Aes192EncryptDecryptInitSub(&indata_cmd, ctx->buf, dummy_iv); @@ -713,10 +724,11 @@ int mbedtls_internal_aes_decrypt (mbedtls_aes_context * ctx, const unsigned char err = HW_SCE_Aes192EncryptDecryptFinalSub(); } - #endif + #endif else if (ctx->nr == 14) { - err = HW_SCE_Aes256EncryptDecryptInitSub(&indata_key_type, &indata_cmd, ctx->buf, dummy_iv); + err = HW_SCE_Aes256EncryptDecryptInitSubAdaptor(&indata_key_type, &indata_cmd, ctx->buf, NULL, dummy_iv); + if (err == FSP_SUCCESS) { HW_SCE_Aes256EncryptDecryptUpdateSub((uint32_t *) &input[0], (uint32_t *) &output[0], SIZE_AES_BLOCK_WORDS); @@ -724,7 +736,7 @@ int mbedtls_internal_aes_decrypt (mbedtls_aes_context * ctx, const unsigned char err = HW_SCE_Aes256EncryptDecryptFinalSub(); } -#endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ + #endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ else { @@ -754,7 +766,12 @@ int mbedtls_internal_aes_decrypt_cbc (mbedtls_aes_context * ctx, { if (SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT == ctx->state) { - err = HW_SCE_Aes128EncryptDecryptInitSub(&indata_key_type, &indata_cmd, ctx->buf, (uint32_t *) &iv[0]); + err = HW_SCE_Aes128EncryptDecryptInitSubAdaptor(&indata_key_type, + &indata_cmd, + ctx->buf, + NULL, + (uint32_t *) &iv[0]); + if (FSP_SUCCESS != err) { return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; @@ -766,7 +783,7 @@ int mbedtls_internal_aes_decrypt_cbc (mbedtls_aes_context * ctx, HW_SCE_Aes128EncryptDecryptUpdateSub((uint32_t *) &input[0], (uint32_t *) &output[0], (length / 4U)); } -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) + #if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) else if (ctx->nr == 12) { if (SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT == ctx->state) @@ -786,7 +803,11 @@ int mbedtls_internal_aes_decrypt_cbc (mbedtls_aes_context * ctx, { if (SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT == ctx->state) { - err = HW_SCE_Aes256EncryptDecryptInitSub(&indata_key_type, &indata_cmd, ctx->buf, (uint32_t *) &iv[0]); + err = HW_SCE_Aes256EncryptDecryptInitSubAdaptor(&indata_key_type, + &indata_cmd, + ctx->buf, + NULL, + (uint32_t *) &iv[0]); if (FSP_SUCCESS != err) { return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; @@ -797,7 +818,7 @@ int mbedtls_internal_aes_decrypt_cbc (mbedtls_aes_context * ctx, HW_SCE_Aes256EncryptDecryptUpdateSub((uint32_t *) &input[0], (uint32_t *) &output[0], (length / 4U)); } -#endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ + #endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ else { @@ -939,7 +960,11 @@ int mbedtls_internal_aes_encrypt_decrypt_ctr (mbedtls_aes_context * ctx, { if (SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT == ctx->state) { - err = HW_SCE_Aes128EncryptDecryptInitSub(&indata_key_type, &indata_cmd, ctx->buf, (uint32_t *) &iv[0]); + err = HW_SCE_Aes128EncryptDecryptInitSubAdaptor(&indata_key_type, + &indata_cmd, + ctx->buf, + NULL, + (uint32_t *) &iv[0]); if (FSP_SUCCESS != err) { return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; @@ -951,7 +976,7 @@ int mbedtls_internal_aes_encrypt_decrypt_ctr (mbedtls_aes_context * ctx, HW_SCE_Aes128EncryptDecryptUpdateSub((uint32_t *) &input[0], (uint32_t *) &output[0], (length / 4U)); } -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) + #if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) else if (ctx->nr == 12) { if (SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT == ctx->state) @@ -971,7 +996,11 @@ int mbedtls_internal_aes_encrypt_decrypt_ctr (mbedtls_aes_context * ctx, { if (SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT == ctx->state) { - err = HW_SCE_Aes256EncryptDecryptInitSub(&indata_key_type, &indata_cmd, ctx->buf, (uint32_t *) &iv[0]); + err = HW_SCE_Aes256EncryptDecryptInitSubAdaptor(&indata_key_type, + &indata_cmd, + ctx->buf, + NULL, + (uint32_t *) &iv[0]); if (FSP_SUCCESS != err) { return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; @@ -982,7 +1011,7 @@ int mbedtls_internal_aes_encrypt_decrypt_ctr (mbedtls_aes_context * ctx, HW_SCE_Aes256EncryptDecryptUpdateSub((uint32_t *) &input[0], (uint32_t *) &output[0], (length / 4U)); } -#endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ + #endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ else { @@ -1006,7 +1035,8 @@ int mbedtls_internal_aes_crypt_ctr_finish (mbedtls_aes_context * ctx) { ret = HW_SCE_Aes128EncryptDecryptFinalSub(); } -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) + + #if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) else if (12 == key_rounds) { ret = HW_SCE_Aes192EncryptDecryptFinalSub(); @@ -1015,7 +1045,7 @@ int mbedtls_internal_aes_crypt_ctr_finish (mbedtls_aes_context * ctx) { ret = HW_SCE_Aes256EncryptDecryptFinalSub(); } -#endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ + #endif /* !MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ else { return -1; diff --git a/ra/fsp/src/rm_psa_crypto/asymmetric_vendor.c b/ra/fsp/src/rm_psa_crypto/asymmetric_vendor.c index 5ef5719d1..d31b8f0d1 100644 --- a/ra/fsp/src/rm_psa_crypto/asymmetric_vendor.c +++ b/ra/fsp/src/rm_psa_crypto/asymmetric_vendor.c @@ -7,6 +7,7 @@ #if defined(MBEDTLS_PSA_CRYPTO_ACCEL_DRV_C) #include "asymmetric_vendor.h" + #include "mbedtls/psa_util.h" #if defined(MBEDTLS_ECP_C) @@ -53,12 +54,11 @@ psa_status_t psa_import_ec_private_key_vendor (psa_ecc_family_t curve, { psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; mbedtls_ecp_keypair * ecp = NULL; - int explicit_bits = (data_length != 0); size_t curve_bits; curve_bits = PSA_BYTES_TO_BITS(PSA_ECC_BYTES_VENDOR_RAW(data_length)); mbedtls_ecp_group_id grp_id = - mbedtls_ecc_group_of_psa(curve, curve_bits, !explicit_bits); + mbedtls_ecc_group_from_psa(curve, curve_bits); *p_ecp = NULL; ecp = mbedtls_calloc(1, sizeof(mbedtls_ecp_keypair)); diff --git a/ra/fsp/src/rm_psa_crypto/ccm_alt.c b/ra/fsp/src/rm_psa_crypto/ccm_alt.c index 84f07f486..41287bef0 100644 --- a/ra/fsp/src/rm_psa_crypto/ccm_alt.c +++ b/ra/fsp/src/rm_psa_crypto/ccm_alt.c @@ -2,7 +2,7 @@ * NIST SP800-38C compliant CCM implementation * * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -35,6 +35,10 @@ #include "mbedtls/error.h" #include "mbedtls/constant_time.h" +#if defined(MBEDTLS_BLOCK_CIPHER_C) +#include "block_cipher_internal.h" +#endif + #include #if defined(MBEDTLS_PLATFORM_C) @@ -63,6 +67,18 @@ int mbedtls_ccm_setkey(mbedtls_ccm_context *ctx, unsigned int keybits) { int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + +#if defined(MBEDTLS_BLOCK_CIPHER_C) + mbedtls_block_cipher_free(&ctx->block_cipher_ctx); + + if ((ret = mbedtls_block_cipher_setup(&ctx->block_cipher_ctx, cipher)) != 0) { + return MBEDTLS_ERR_CCM_BAD_INPUT; + } + + if ((ret = mbedtls_block_cipher_setkey(&ctx->block_cipher_ctx, key, keybits)) != 0) { + return MBEDTLS_ERR_CCM_BAD_INPUT; + } +#else const mbedtls_cipher_info_t *cipher_info; cipher_info = mbedtls_cipher_info_from_values(cipher, keybits, @@ -90,8 +106,9 @@ int mbedtls_ccm_setkey(mbedtls_ccm_context *ctx, MBEDTLS_ENCRYPT)) != 0) { return ret; } +#endif - return 0; + return ret; } /* @@ -102,7 +119,11 @@ void mbedtls_ccm_free(mbedtls_ccm_context *ctx) if (ctx == NULL) { return; } +#if defined(MBEDTLS_BLOCK_CIPHER_C) + mbedtls_block_cipher_free(&ctx->block_cipher_ctx); +#else mbedtls_cipher_free(&ctx->cipher_ctx); +#endif mbedtls_platform_zeroize(ctx, sizeof(mbedtls_ccm_context)); } @@ -122,19 +143,22 @@ static int mbedtls_ccm_crypt(mbedtls_ccm_context *ctx, unsigned char *output) { size_t i; - size_t olen = 0; int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char tmp_buf[16] = { 0 }; - if ((ret = mbedtls_cipher_update(&ctx->cipher_ctx, ctx->ctr, 16, tmp_buf, - &olen)) != 0) { +#if defined(MBEDTLS_BLOCK_CIPHER_C) + ret = mbedtls_block_cipher_encrypt(&ctx->block_cipher_ctx, ctx->ctr, tmp_buf); +#else + size_t olen = 0; + ret = mbedtls_cipher_update(&ctx->cipher_ctx, ctx->ctr, 16, tmp_buf, &olen); +#endif + if (ret != 0) { ctx->state |= CCM_STATE__ERROR; mbedtls_platform_zeroize(tmp_buf, sizeof(tmp_buf)); return ret; } - for( i = 0; i < use_len; i++ ) - output[i] = input[i] ^ tmp_buf[offset + i]; + mbedtls_xor(output, input, tmp_buf + offset, use_len); mbedtls_platform_zeroize(tmp_buf, sizeof(tmp_buf)); return ret; @@ -151,7 +175,10 @@ static int ccm_calculate_first_block_if_ready(mbedtls_ccm_context *ctx) { int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char i; - size_t len_left, olen; + size_t len_left; +#if !defined(MBEDTLS_BLOCK_CIPHER_C) + size_t olen; +#endif /* length calculation can be done only after both * mbedtls_ccm_starts() and mbedtls_ccm_set_lengths() have been executed @@ -197,7 +224,12 @@ static int ccm_calculate_first_block_if_ready(mbedtls_ccm_context *ctx) } /* Start CBC-MAC with first block*/ - if ((ret = mbedtls_cipher_update(&ctx->cipher_ctx, ctx->y, 16, ctx->y, &olen)) != 0) { +#if defined(MBEDTLS_BLOCK_CIPHER_C) + ret = mbedtls_block_cipher_encrypt(&ctx->block_cipher_ctx, ctx->y, ctx->y); +#else + ret = mbedtls_cipher_update(&ctx->cipher_ctx, ctx->y, 16, ctx->y, &olen); +#endif + if (ret != 0) { ctx->state |= CCM_STATE__ERROR; return ret; } @@ -277,8 +309,10 @@ int mbedtls_ccm_update_ad(mbedtls_ccm_context *ctx, size_t add_len) { int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - unsigned char i; - size_t olen, use_len, offset; + size_t use_len, offset; +#if !defined(MBEDTLS_BLOCK_CIPHER_C) + size_t olen; +#endif if (ctx->state & CCM_STATE__ERROR) { return MBEDTLS_ERR_CCM_BAD_INPUT; @@ -311,16 +345,19 @@ int mbedtls_ccm_update_ad(mbedtls_ccm_context *ctx, use_len = add_len; } - for( i = 0; i < use_len; i++ ) - ctx->y[i + offset] ^= add[i]; + mbedtls_xor(ctx->y + offset, ctx->y + offset, add, use_len); ctx->processed += use_len; add_len -= use_len; add += use_len; if (use_len + offset == 16 || ctx->processed == ctx->add_len) { - if ((ret = - mbedtls_cipher_update(&ctx->cipher_ctx, ctx->y, 16, ctx->y, &olen)) != 0) { +#if defined(MBEDTLS_BLOCK_CIPHER_C) + ret = mbedtls_block_cipher_encrypt(&ctx->block_cipher_ctx, ctx->y, ctx->y); +#else + ret = mbedtls_cipher_update(&ctx->cipher_ctx, ctx->y, 16, ctx->y, &olen); +#endif + if (ret != 0) { ctx->state |= CCM_STATE__ERROR; return ret; } @@ -343,7 +380,10 @@ int mbedtls_ccm_update(mbedtls_ccm_context *ctx, { int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char i; - size_t use_len, offset, olen; + size_t use_len, offset; +#if !defined(MBEDTLS_BLOCK_CIPHER_C) + size_t olen; +#endif unsigned char local_output[16]; @@ -378,12 +418,15 @@ int mbedtls_ccm_update(mbedtls_ccm_context *ctx, if (ctx->mode == MBEDTLS_CCM_ENCRYPT || \ ctx->mode == MBEDTLS_CCM_STAR_ENCRYPT) { - for( i = 0; i < use_len; i++ ) - ctx->y[i + offset] ^= input[i]; + mbedtls_xor(ctx->y + offset, ctx->y + offset, input, use_len); if (use_len + offset == 16 || ctx->processed == ctx->plaintext_len) { - if ((ret = - mbedtls_cipher_update(&ctx->cipher_ctx, ctx->y, 16, ctx->y, &olen)) != 0) { +#if defined(MBEDTLS_BLOCK_CIPHER_C) + ret = mbedtls_block_cipher_encrypt(&ctx->block_cipher_ctx, ctx->y, ctx->y); +#else + ret = mbedtls_cipher_update(&ctx->cipher_ctx, ctx->y, 16, ctx->y, &olen); +#endif + if (ret != 0) { ctx->state |= CCM_STATE__ERROR; goto exit; } @@ -408,14 +451,17 @@ int mbedtls_ccm_update(mbedtls_ccm_context *ctx, goto exit; } - for( i = 0; i < use_len; i++ ) - ctx->y[i + offset] ^= local_output[i]; + mbedtls_xor(ctx->y + offset, ctx->y + offset, local_output, use_len); memcpy(output, local_output, use_len); if (use_len + offset == 16 || ctx->processed == ctx->plaintext_len) { - if ((ret = - mbedtls_cipher_update(&ctx->cipher_ctx, ctx->y, 16, ctx->y, &olen)) != 0) { +#if defined(MBEDTLS_BLOCK_CIPHER_C) + ret = mbedtls_block_cipher_encrypt(&ctx->block_cipher_ctx, ctx->y, ctx->y); +#else + ret = mbedtls_cipher_update(&ctx->cipher_ctx, ctx->y, 16, ctx->y, &olen); +#endif + if (ret != 0) { ctx->state |= CCM_STATE__ERROR; goto exit; } @@ -487,7 +533,7 @@ static int ccm_auth_crypt(mbedtls_ccm_context *ctx, int mode, size_t length, const unsigned char *input, unsigned char *output, unsigned char *tag, size_t tag_len) { - return (sce_ccm_crypt_and_tag(ctx, mode, length, iv, iv_len, add, + return (sce_ccm_crypt_and_tag(ctx, mode, length, iv, iv_len, add, add_len, input, output, tag_len, tag)); } @@ -573,7 +619,7 @@ int mbedtls_ccm_auth_decrypt(mbedtls_ccm_context *ctx, size_t length, input, output, tag, tag_len); } -#if defined(MBEDTLS_SELF_TEST) && defined(MBEDTLS_AES_C) +#if defined(MBEDTLS_SELF_TEST) && defined(MBEDTLS_CCM_GCM_CAN_AES) /* * Examples 1 to 3 from SP800-38C Appendix C */ diff --git a/ra/fsp/src/rm_psa_crypto/ccm_alt_process.c b/ra/fsp/src/rm_psa_crypto/ccm_alt_process.c index a68241f8f..52c05b378 100644 --- a/ra/fsp/src/rm_psa_crypto/ccm_alt_process.c +++ b/ra/fsp/src/rm_psa_crypto/ccm_alt_process.c @@ -34,12 +34,6 @@ #include "aes_alt.h" #include "platform_alt.h" -/* Parameter validation macros */ - #define CCM_VALIDATE_RET(cond) \ - MBEDTLS_INTERNAL_VALIDATE_RET(cond, MBEDTLS_ERR_CCM_BAD_INPUT) - #define CCM_VALIDATE(cond) \ - MBEDTLS_INTERNAL_VALIDATE(cond) - #define SCE9_AES_CCM_KEY_TYPE_GENERAL (0) #define ROUNDOFF_TO_BLOCK_SIZE(BLOCK_SIZE, DATA_SIZE) (BLOCK_SIZE * ((DATA_SIZE + (BLOCK_SIZE - 1)) / BLOCK_SIZE)) @@ -201,7 +195,7 @@ static int ccm_authetication_block_format (mbedtls_ccm_context * ctx, } header_size += HW_SCE_AES_BLOCK_BYTE_SIZE; - + if(ctx->add_len > 0U) { b_format_buffer[header_size] = (unsigned char) ((ctx->add_len >> 8) & 0xFF); @@ -235,13 +229,6 @@ int sce_ccm_crypt_and_tag (mbedtls_ccm_context * ctx, { int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - CCM_VALIDATE_RET(ctx != NULL); - CCM_VALIDATE_RET(iv != NULL); - CCM_VALIDATE_RET(aad_len == 0 || aad != NULL); - CCM_VALIDATE_RET(length == 0 || input != NULL); - CCM_VALIDATE_RET(length == 0 || output != NULL); - CCM_VALIDATE_RET(tag != NULL); - uint32_t key_len_idx = RM_PSA_CRYPTO_AES_LOOKUP_INDEX(ctx->cipher_ctx.key_bitlen); mbedtls_aes_context * aes_ctx = (mbedtls_aes_context *) ctx->cipher_ctx.cipher_ctx; fsp_err_t err = FSP_SUCCESS; diff --git a/ra/fsp/src/rm_psa_crypto/cipher_alt.c b/ra/fsp/src/rm_psa_crypto/cipher_alt.c index 12486c53c..f64b7897e 100644 --- a/ra/fsp/src/rm_psa_crypto/cipher_alt.c +++ b/ra/fsp/src/rm_psa_crypto/cipher_alt.c @@ -6,19 +6,7 @@ * \author Adriaan de Jong * * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later * * This file is part of mbed TLS (https://tls.mbed.org) */ @@ -69,7 +57,7 @@ #include "hw_sce_ra_private.h" -#if (BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7) && defined(MBEDTLS_AES_C) && defined(MBEDTLS_AES_ALT) +#if (BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 || BSP_FEATURE_CRYPTO_HAS_RSIP_E11A) && defined(MBEDTLS_AES_C) && defined(MBEDTLS_AES_ALT) static int sce_aes_cipher_final( mbedtls_cipher_context_t *ctx ) { fsp_err_t ret = FSP_SUCCESS; @@ -95,14 +83,14 @@ static int sce_aes_cipher_final( mbedtls_cipher_context_t *ctx ) if (FSP_SUCCESS != ret) return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - /* Once final is successful, change operation state back to SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT to allow same AES key to + /* Once final is successful, change operation state back to SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT to allow same AES key to * be used for subsequent operations */ ((mbedtls_aes_context *)(ctx->cipher_ctx))->state = SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT; return( 0 ); } -#endif /* (BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || BSP_FEATURE_CRYPTO_HAS_SCE7) && MBEDTLS_AES_C && MBEDTLS_AES_ALT */ +#endif /* (BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 || BSP_FEATURE_CRYPTO_HAS_RSIP_E11A ) && MBEDTLS_AES_C && MBEDTLS_AES_ALT */ static int supported_init = 0; @@ -302,8 +290,11 @@ int mbedtls_cipher_setup(mbedtls_cipher_context_t *ctx, memset(ctx, 0, sizeof(mbedtls_cipher_context_t)); - if (NULL == (ctx->cipher_ctx = mbedtls_cipher_get_base(cipher_info)->ctx_alloc_func())) { + if (mbedtls_cipher_get_base(cipher_info)->ctx_alloc_func != NULL) { + ctx->cipher_ctx = mbedtls_cipher_get_base(cipher_info)->ctx_alloc_func(); + if (ctx->cipher_ctx == NULL) { return MBEDTLS_ERR_CIPHER_ALLOC_FAILED; + } } ctx->cipher_info = cipher_info; @@ -358,6 +349,12 @@ int mbedtls_cipher_setkey(mbedtls_cipher_context_t *ctx, if (ctx->cipher_info == NULL) { return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; } +#if defined(MBEDTLS_BLOCK_CIPHER_NO_DECRYPT) + if (MBEDTLS_MODE_ECB == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) && + MBEDTLS_DECRYPT == operation) { + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; + } +#endif #if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) if (ctx->psa_enabled == 1) { @@ -425,6 +422,7 @@ int mbedtls_cipher_setkey(mbedtls_cipher_context_t *ctx, ctx->key_bitlen = key_bitlen; ctx->operation = operation; +#if !defined(MBEDTLS_BLOCK_CIPHER_NO_DECRYPT) /* * For OFB, CFB and CTR mode always use the encryption key schedule */ @@ -440,6 +438,12 @@ int mbedtls_cipher_setkey(mbedtls_cipher_context_t *ctx, return mbedtls_cipher_get_base(ctx->cipher_info)->setkey_dec_func(ctx->cipher_ctx, key, ctx->key_bitlen); } +#else + if (operation == MBEDTLS_ENCRYPT || operation == MBEDTLS_DECRYPT) { + return mbedtls_cipher_get_base(ctx->cipher_info)->setkey_enc_func(ctx->cipher_ctx, key, + ctx->key_bitlen); + } +#endif return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; } @@ -498,7 +502,7 @@ int mbedtls_cipher_set_iv(mbedtls_cipher_context_t *ctx, iv_len != 12) { return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; } -#endif +#endif #endif #if defined(MBEDTLS_GCM_C) @@ -827,7 +831,7 @@ int mbedtls_cipher_update(mbedtls_cipher_context_t *ctx, const unsigned char *in copy_len ); if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->ctr_func(ctx->cipher_ctx, - block_size, + block_size, NULL, ctx->iv, NULL, ctx->unprocessed_data, output))) { return ret; @@ -986,7 +990,7 @@ static int get_one_and_zeros_padding(unsigned char *input, size_t input_len, mbedtls_ct_condition_t bad = MBEDTLS_CT_TRUE; *data_len = 0; - + for (ptrdiff_t i = (ptrdiff_t) (input_len) - 1; i >= 0; i--) { mbedtls_ct_condition_t is_nonzero = mbedtls_ct_bool(input[i]); @@ -1160,7 +1164,7 @@ int mbedtls_cipher_finish(mbedtls_cipher_context_t *ctx, if (0 != ctx->unprocessed_len) { return MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED; } -#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 +#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 || BSP_FEATURE_CRYPTO_HAS_RSIP_E11A return sce_aes_cipher_final( ctx ); #else return 0; @@ -1176,7 +1180,7 @@ int mbedtls_cipher_finish(mbedtls_cipher_context_t *ctx, */ if (NULL == ctx->add_padding && 0 == ctx->unprocessed_len) { -#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 +#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 || BSP_FEATURE_CRYPTO_HAS_RSIP_E11A return sce_aes_cipher_final( ctx ); #else return 0; @@ -1199,7 +1203,7 @@ int mbedtls_cipher_finish(mbedtls_cipher_context_t *ctx, /* Set output size for decryption */ if (MBEDTLS_DECRYPT == ctx->operation) { -#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 +#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 || BSP_FEATURE_CRYPTO_HAS_RSIP_E11A if( 0 != ( ret = sce_aes_cipher_final( ctx ))) { return( ret ); @@ -1212,7 +1216,7 @@ int mbedtls_cipher_finish(mbedtls_cipher_context_t *ctx, /* Set output size for encryption */ *olen = mbedtls_cipher_get_block_size(ctx); -#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 +#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 || BSP_FEATURE_CRYPTO_HAS_RSIP_E11A return sce_aes_cipher_final( ctx ); #else return 0; @@ -1245,7 +1249,7 @@ int mbedtls_cipher_finish(mbedtls_cipher_context_t *ctx, *olen = ctx->unprocessed_len; } -#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 +#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || BSP_FEATURE_CRYPTO_HAS_SCE7 || BSP_FEATURE_CRYPTO_HAS_RSIP7 || BSP_FEATURE_CRYPTO_HAS_RSIP_E11A return sce_aes_cipher_final( ctx ); #else return 0; diff --git a/ra/fsp/src/rm_psa_crypto/cmac_alt.c b/ra/fsp/src/rm_psa_crypto/cmac_alt.c index 5d9a35ded..2702cb973 100644 --- a/ra/fsp/src/rm_psa_crypto/cmac_alt.c +++ b/ra/fsp/src/rm_psa_crypto/cmac_alt.c @@ -4,19 +4,7 @@ * \brief NIST SP800-38B compliant CMAC implementation for AES and 3DES * * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later */ /* @@ -46,6 +34,7 @@ #include "mbedtls/platform_util.h" #include "mbedtls/error.h" #include "mbedtls/platform.h" +#include "constant_time_internal.h" #include @@ -69,39 +58,33 @@ static int cmac_multiply_by_u(unsigned char *output, size_t blocksize) { const unsigned char R_128 = 0x87; - const unsigned char R_64 = 0x1B; - unsigned char R_n, mask; - unsigned char overflow = 0x00; + unsigned char R_n; + uint32_t overflow = 0x00; int i; if (blocksize == MBEDTLS_AES_BLOCK_SIZE) { R_n = R_128; - } else if (blocksize == MBEDTLS_DES3_BLOCK_SIZE) { + } +#if defined(MBEDTLS_DES_C) + else if (blocksize == MBEDTLS_DES3_BLOCK_SIZE) { + const unsigned char R_64 = 0x1B; R_n = R_64; - } else { + } +#endif + else { return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; } - for (i = (int) blocksize - 1; i >= 0; i--) { - output[i] = input[i] << 1 | overflow; - overflow = input[i] >> 7; + for (i = (int) blocksize - 4; i >= 0; i -= 4) { + uint32_t i32 = MBEDTLS_GET_UINT32_BE(&input[i], 0); + uint32_t new_overflow = i32 >> 31; + i32 = (i32 << 1) | overflow; + MBEDTLS_PUT_UINT32_BE(i32, &output[i], 0); + overflow = new_overflow; } - /* mask = ( input[0] >> 7 ) ? 0xff : 0x00 - * using bit operations to avoid branches */ - - /* MSVC has a warning about unary minus on unsigned, but this is - * well-defined and precisely what we want to do here */ -#if defined(_MSC_VER) -#pragma warning( push ) -#pragma warning( disable : 4146 ) -#endif - mask = -(input[0] >> 7); -#if defined(_MSC_VER) -#pragma warning( pop ) -#endif - - output[blocksize - 1] ^= R_n & mask; + R_n = (unsigned char) mbedtls_ct_uint_if_else_0(mbedtls_ct_bool(input[0] >> 7), R_n); + output[blocksize - 1] ^= R_n; return 0; } @@ -215,7 +198,7 @@ static const hw_sce_cmac_final_t g_sce_cmac_final[] = int mbedtls_cipher_cmac_starts(mbedtls_cipher_context_t *ctx, const unsigned char *key, size_t keybits) -{ +{ mbedtls_cipher_type_t type; mbedtls_cmac_context_t *cmac_ctx; int retval; @@ -278,6 +261,10 @@ int mbedtls_cipher_cmac_update(mbedtls_cipher_context_t *ctx, cmac_ctx = ctx->cmac_ctx; block_size = mbedtls_cipher_info_get_block_size(ctx->cipher_info); + /* Without the MBEDTLS_ASSUME below, gcc -O3 will generate a warning of the form + * error: writing 16 bytes into a region of size 0 [-Werror=stringop-overflow=] */ + MBEDTLS_ASSUME(block_size <= MBEDTLS_CMAC_MAX_BLOCK_SIZE); + if (SCE_MBEDTLS_CMAC_OPERATION_STATE_INIT == cmac_ctx->vendor_state) { return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; @@ -327,6 +314,7 @@ int mbedtls_cipher_cmac_finish(mbedtls_cipher_context_t *ctx, cmac_ctx = ctx->cmac_ctx; block_size = mbedtls_cipher_info_get_block_size(ctx->cipher_info); + MBEDTLS_ASSUME(block_size <= MBEDTLS_CMAC_MAX_BLOCK_SIZE); // silence GCC warning if (SCE_MBEDTLS_CMAC_OPERATION_STATE_INIT == cmac_ctx->vendor_state) { diff --git a/ra/fsp/src/rm_psa_crypto/ctr_drbg_alt.c b/ra/fsp/src/rm_psa_crypto/ctr_drbg_alt.c index 977adf610..ac5d5c829 100644 --- a/ra/fsp/src/rm_psa_crypto/ctr_drbg_alt.c +++ b/ra/fsp/src/rm_psa_crypto/ctr_drbg_alt.c @@ -2,21 +2,7 @@ * CTR_DRBG implementation based on AES-256 (NIST SP 800-90) * * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * This file is part of mbed TLS (https://tls.mbed.org) + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later */ /* * The NIST SP 800-90 DRBGs are described in the following publication. @@ -28,6 +14,7 @@ #if defined(MBEDTLS_CTR_DRBG_C_ALT) +#include "ctr.h" #include "ctr_drbg_alt.h" #include "mbedtls/platform_util.h" #include "mbedtls/error.h" @@ -38,8 +25,48 @@ #include #endif +/* Using error translation functions from PSA to MbedTLS */ +#if !defined(MBEDTLS_AES_C) +#include "psa_util_internal.h" +#endif + #include "mbedtls/platform.h" +#if !defined(MBEDTLS_AES_C) +static psa_status_t ctr_drbg_setup_psa_context(mbedtls_ctr_drbg_psa_context *psa_ctx, + unsigned char *key, size_t key_len) +{ + psa_key_attributes_t key_attr = PSA_KEY_ATTRIBUTES_INIT; + psa_status_t status; + + psa_set_key_usage_flags(&key_attr, PSA_KEY_USAGE_ENCRYPT); + psa_set_key_algorithm(&key_attr, PSA_ALG_ECB_NO_PADDING); + psa_set_key_type(&key_attr, PSA_KEY_TYPE_AES); + status = psa_import_key(&key_attr, key, key_len, &psa_ctx->key_id); + if (status != PSA_SUCCESS) { + goto exit; + } + + status = psa_cipher_encrypt_setup(&psa_ctx->operation, psa_ctx->key_id, PSA_ALG_ECB_NO_PADDING); + if (status != PSA_SUCCESS) { + goto exit; + } + +exit: + psa_reset_key_attributes(&key_attr); + return status; +} + +static void ctr_drbg_destroy_psa_contex(mbedtls_ctr_drbg_psa_context *psa_ctx) +{ + psa_cipher_abort(&psa_ctx->operation); + psa_destroy_key(psa_ctx->key_id); + + psa_ctx->operation = psa_cipher_operation_init(); + psa_ctx->key_id = MBEDTLS_SVC_KEY_ID_INIT; +} +#endif + /* Macros from mbedtls/aes.h */ #define MBEDTLS_AES_ENCRYPT 1 /**< AES encryption. */ #define MBEDTLS_AES_DECRYPT 0 /**< AES decryption. */ @@ -68,11 +95,17 @@ int ferror (FILE * f) void mbedtls_ctr_drbg_init(mbedtls_ctr_drbg_context *ctx) { memset(ctx, 0, sizeof(mbedtls_ctr_drbg_context)); +#if defined(MBEDTLS_AES_C) mbedtls_aes_init(&ctx->aes_ctx); +#else + ctx->psa_ctx.key_id = MBEDTLS_SVC_KEY_ID_INIT; + ctx->psa_ctx.operation = psa_cipher_operation_init(); +#endif /* Indicate that the entropy nonce length is not set explicitly. * See mbedtls_ctr_drbg_set_nonce_len(). */ ctx->reseed_counter = -1; + #if defined(MBEDTLS_THREADING_C) mbedtls_mutex_init( &ctx->mutex ); #endif @@ -91,7 +124,11 @@ void mbedtls_ctr_drbg_free(mbedtls_ctr_drbg_context *ctx) #if defined(MBEDTLS_THREADING_C) mbedtls_mutex_free(&ctx->mutex); #endif +#if defined(MBEDTLS_AES_C) mbedtls_aes_free(&ctx->aes_ctx); +#else + ctr_drbg_destroy_psa_contex(&ctx->psa_ctx); +#endif mbedtls_platform_zeroize(ctx, sizeof(mbedtls_ctr_drbg_context)); } @@ -150,8 +187,17 @@ static int block_cipher_df(unsigned char *output, unsigned char key[MBEDTLS_CTR_DRBG_KEYSIZE]; unsigned char chain[MBEDTLS_CTR_DRBG_BLOCKSIZE]; unsigned char *p, *iv; - mbedtls_aes_context aes_ctx; int ret = 0; +#if defined(MBEDTLS_AES_C) + mbedtls_aes_context aes_ctx; +#else + psa_status_t status; + size_t tmp_len; + mbedtls_ctr_drbg_psa_context psa_ctx; + + psa_ctx.key_id = MBEDTLS_SVC_KEY_ID_INIT; + psa_ctx.operation = psa_cipher_operation_init(); +#endif int i, j; size_t buf_len, use_len; @@ -162,7 +208,6 @@ static int block_cipher_df(unsigned char *output, memset(buf, 0, MBEDTLS_CTR_DRBG_MAX_SEED_INPUT + MBEDTLS_CTR_DRBG_BLOCKSIZE + 16); - mbedtls_aes_init(&aes_ctx); /* * Construct IV (16 bytes) and S in buffer @@ -186,11 +231,20 @@ static int block_cipher_df(unsigned char *output, for (i = 0; i < MBEDTLS_CTR_DRBG_KEYSIZE; i++) { key[i] = (uint8_t) i; } +#if defined(MBEDTLS_AES_C) + mbedtls_aes_init(&aes_ctx); if ((ret = mbedtls_aes_setkey_enc(&aes_ctx, key, MBEDTLS_CTR_DRBG_KEYBITS)) != 0) { goto exit; } +#else + status = ctr_drbg_setup_psa_context(&psa_ctx, key, sizeof(key)); + if (status != PSA_SUCCESS) { + ret = psa_generic_status_to_mbedtls(status); + goto exit; + } +#endif /* * Reduce data to MBEDTLS_CTR_DRBG_SEEDLEN bytes of data @@ -205,11 +259,19 @@ static int block_cipher_df(unsigned char *output, p += MBEDTLS_CTR_DRBG_BLOCKSIZE; use_len -= (use_len >= MBEDTLS_CTR_DRBG_BLOCKSIZE) ? MBEDTLS_CTR_DRBG_BLOCKSIZE : use_len; - +#if defined(MBEDTLS_AES_C) if ((ret = mbedtls_aes_crypt_ecb(&aes_ctx, MBEDTLS_AES_ENCRYPT, chain, chain)) != 0) { goto exit; } +#else + status = psa_cipher_update(&psa_ctx.operation, chain, MBEDTLS_CTR_DRBG_BLOCKSIZE, + chain, MBEDTLS_CTR_DRBG_BLOCKSIZE, &tmp_len); + if (status != PSA_SUCCESS) { + ret = psa_generic_status_to_mbedtls(status); + goto exit; + } +#endif } memcpy(tmp + j, chain, MBEDTLS_CTR_DRBG_BLOCKSIZE); @@ -223,23 +285,46 @@ static int block_cipher_df(unsigned char *output, /* * Do final encryption with reduced data */ +#if defined(MBEDTLS_AES_C) if ((ret = mbedtls_aes_setkey_enc(&aes_ctx, tmp, MBEDTLS_CTR_DRBG_KEYBITS)) != 0) { goto exit; } +#else + ctr_drbg_destroy_psa_contex(&psa_ctx); + + status = ctr_drbg_setup_psa_context(&psa_ctx, tmp, MBEDTLS_CTR_DRBG_KEYSIZE); + if (status != PSA_SUCCESS) { + ret = psa_generic_status_to_mbedtls(status); + goto exit; + } +#endif iv = tmp + MBEDTLS_CTR_DRBG_KEYSIZE; p = output; for (j = 0; j < MBEDTLS_CTR_DRBG_SEEDLEN; j += MBEDTLS_CTR_DRBG_BLOCKSIZE) { +#if defined(MBEDTLS_AES_C) if ((ret = mbedtls_aes_crypt_ecb(&aes_ctx, MBEDTLS_AES_ENCRYPT, iv, iv)) != 0) { goto exit; } +#else + status = psa_cipher_update(&psa_ctx.operation, iv, MBEDTLS_CTR_DRBG_BLOCKSIZE, + iv, MBEDTLS_CTR_DRBG_BLOCKSIZE, &tmp_len); + if (status != PSA_SUCCESS) { + ret = psa_generic_status_to_mbedtls(status); + goto exit; + } +#endif memcpy(p, iv, MBEDTLS_CTR_DRBG_BLOCKSIZE); p += MBEDTLS_CTR_DRBG_BLOCKSIZE; } exit: +#if defined(MBEDTLS_AES_C) mbedtls_aes_free(&aes_ctx); +#else + ctr_drbg_destroy_psa_contex(&psa_ctx); +#endif /* * tidy up the stack */ @@ -272,6 +357,10 @@ static int ctr_drbg_update_internal(mbedtls_ctr_drbg_context *ctx, unsigned char *p = tmp; int i, j; int ret = 0; +#if !defined(MBEDTLS_AES_C) + psa_status_t status; + size_t tmp_len; +#endif memset(tmp, 0, MBEDTLS_CTR_DRBG_SEEDLEN); @@ -279,34 +368,47 @@ static int ctr_drbg_update_internal(mbedtls_ctr_drbg_context *ctx, /* * Increase counter */ - for (i = MBEDTLS_CTR_DRBG_BLOCKSIZE; i > 0; i--) { - if (++ctx->counter[i - 1] != 0) { - break; - } - } + mbedtls_ctr_increment_counter(ctx->counter); /* * Crypt counter block */ +#if defined(MBEDTLS_AES_C) if ((ret = mbedtls_aes_crypt_ecb(&ctx->aes_ctx, MBEDTLS_AES_ENCRYPT, ctx->counter, p)) != 0) { goto exit; } +#else + status = psa_cipher_update(&ctx->psa_ctx.operation, ctx->counter, sizeof(ctx->counter), + p, MBEDTLS_CTR_DRBG_BLOCKSIZE, &tmp_len); + if (status != PSA_SUCCESS) { + ret = psa_generic_status_to_mbedtls(status); + goto exit; + } +#endif p += MBEDTLS_CTR_DRBG_BLOCKSIZE; } - for (i = 0; i < MBEDTLS_CTR_DRBG_SEEDLEN; i++) { - tmp[i] ^= data[i]; - } + mbedtls_xor(tmp, tmp, data, MBEDTLS_CTR_DRBG_SEEDLEN); /* * Update key and counter */ +#if defined(MBEDTLS_AES_C) if ((ret = mbedtls_aes_setkey_enc(&ctx->aes_ctx, tmp, MBEDTLS_CTR_DRBG_KEYBITS)) != 0) { goto exit; } +#else + ctr_drbg_destroy_psa_contex(&ctx->psa_ctx); + + status = ctr_drbg_setup_psa_context(&ctx->psa_ctx, tmp, MBEDTLS_CTR_DRBG_KEYSIZE); + if (status != PSA_SUCCESS) { + ret = psa_generic_status_to_mbedtls(status); + goto exit; + } +#endif memcpy(ctx->counter, tmp + MBEDTLS_CTR_DRBG_KEYSIZE, MBEDTLS_CTR_DRBG_BLOCKSIZE); @@ -493,10 +595,20 @@ int mbedtls_ctr_drbg_seed(mbedtls_ctr_drbg_context *ctx, ctx->reseed_interval = MBEDTLS_CTR_DRBG_RESEED_INTERVAL; /* Initialize with an empty key. */ +#if defined(MBEDTLS_AES_C) if ((ret = mbedtls_aes_setkey_enc(&ctx->aes_ctx, key, MBEDTLS_CTR_DRBG_KEYBITS)) != 0) { return ret; } +#else + psa_status_t status; + + status = ctr_drbg_setup_psa_context(&ctx->psa_ctx, key, MBEDTLS_CTR_DRBG_KEYSIZE); + if (status != PSA_SUCCESS) { + ret = psa_generic_status_to_mbedtls(status); + return status; + } +#endif /* Do the initial seeding. */ if ((ret = mbedtls_ctr_drbg_reseed_internal(ctx, custom, len, @@ -531,10 +643,11 @@ int mbedtls_ctr_drbg_random_with_add(void *p_rng, { int ret = 0; mbedtls_ctr_drbg_context *ctx = (mbedtls_ctr_drbg_context *) p_rng; - unsigned char add_input[MBEDTLS_CTR_DRBG_SEEDLEN]; unsigned char *p = output; - unsigned char tmp[MBEDTLS_CTR_DRBG_BLOCKSIZE]; - int i; + struct { + unsigned char add_input[MBEDTLS_CTR_DRBG_SEEDLEN]; + unsigned char tmp[MBEDTLS_CTR_DRBG_BLOCKSIZE]; + } locals; size_t use_len; if (output_len > MBEDTLS_CTR_DRBG_MAX_REQUEST) { @@ -545,7 +658,7 @@ int mbedtls_ctr_drbg_random_with_add(void *p_rng, return MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG; } - memset(add_input, 0, MBEDTLS_CTR_DRBG_SEEDLEN); + memset(locals.add_input, 0, MBEDTLS_CTR_DRBG_SEEDLEN); if (ctx->reseed_counter > ctx->reseed_interval || ctx->prediction_resistance) { @@ -556,51 +669,58 @@ int mbedtls_ctr_drbg_random_with_add(void *p_rng, } if (add_len > 0) { - if ((ret = block_cipher_df(add_input, additional, add_len)) != 0) { + if ((ret = block_cipher_df(locals.add_input, additional, add_len)) != 0) { goto exit; } - if ((ret = ctr_drbg_update_internal(ctx, add_input)) != 0) { + if ((ret = ctr_drbg_update_internal(ctx, locals.add_input)) != 0) { goto exit; } } while (output_len > 0) { /* - * Increase counter + * Increase counter (treat it as a 128-bit big-endian integer). */ - for (i = MBEDTLS_CTR_DRBG_BLOCKSIZE; i > 0; i--) { - if (++ctx->counter[i - 1] != 0) { - break; - } - } + mbedtls_ctr_increment_counter(ctx->counter); /* * Crypt counter block */ +#if defined(MBEDTLS_AES_C) if ((ret = mbedtls_aes_crypt_ecb(&ctx->aes_ctx, MBEDTLS_AES_ENCRYPT, - ctx->counter, tmp)) != 0) { + ctx->counter, locals.tmp)) != 0) { + goto exit; + } +#else + psa_status_t status; + size_t tmp_len; + + status = psa_cipher_update(&ctx->psa_ctx.operation, ctx->counter, sizeof(ctx->counter), + locals.tmp, MBEDTLS_CTR_DRBG_BLOCKSIZE, &tmp_len); + if (status != PSA_SUCCESS) { + ret = psa_generic_status_to_mbedtls(status); goto exit; } +#endif use_len = (output_len > MBEDTLS_CTR_DRBG_BLOCKSIZE) ? MBEDTLS_CTR_DRBG_BLOCKSIZE : output_len; /* * Copy random block to destination */ - memcpy(p, tmp, use_len); + memcpy(p, locals.tmp, use_len); p += use_len; output_len -= use_len; } - if ((ret = ctr_drbg_update_internal(ctx, add_input)) != 0) { + if ((ret = ctr_drbg_update_internal(ctx, locals.add_input)) != 0) { goto exit; } ctx->reseed_counter++; exit: - mbedtls_platform_zeroize(add_input, sizeof(add_input)); - mbedtls_platform_zeroize(tmp, sizeof(tmp)); + mbedtls_platform_zeroize(&locals, sizeof(locals)); return ret; } @@ -854,12 +974,6 @@ int mbedtls_ctr_drbg_self_test(int verbose) #endif #define MBEDTLS_AES_FEWER_TABLES (1) -/* Parameter validation macros based on platform_util.h */ - #define AES_VALIDATE_RET(cond) \ - MBEDTLS_INTERNAL_VALIDATE_RET(cond, MBEDTLS_ERR_AES_BAD_INPUT_DATA) - #define AES_VALIDATE(cond) \ - MBEDTLS_INTERNAL_VALIDATE(cond) - /* * 32-bit integer manipulation macros (little endian) */ @@ -1322,8 +1436,6 @@ static void aes_gen_tables (void) static void mbedtls_aes_init (mbedtls_aes_context * ctx) { - AES_VALIDATE(ctx != NULL); - memset(ctx, 0, sizeof(mbedtls_aes_context)); } @@ -1347,8 +1459,6 @@ static int mbedtls_aes_setkey_enc (mbedtls_aes_context * ctx, const unsigned cha unsigned int i; uint32_t * RK; - AES_VALIDATE_RET(ctx != NULL); - AES_VALIDATE_RET(key != NULL); ctx->nr = 14; #if !defined(MBEDTLS_AES_ROM_TABLES) @@ -1553,11 +1663,6 @@ static int mbedtls_aes_crypt_ecb (mbedtls_aes_context * ctx, const unsigned char input[16], unsigned char output[16]) { - AES_VALIDATE_RET(ctx != NULL); - AES_VALIDATE_RET(input != NULL); - AES_VALIDATE_RET(output != NULL); - AES_VALIDATE_RET(mode == MBEDTLS_AES_ENCRYPT || - mode == MBEDTLS_AES_DECRYPT); (void) mode; // Unused in some build configurations #if defined(MBEDTLS_AESNI_C) && defined(MBEDTLS_HAVE_X86_64) diff --git a/ra/fsp/src/rm_psa_crypto/ecdh_alt.c b/ra/fsp/src/rm_psa_crypto/ecdh_alt.c index 9e962590b..40eb7ddc3 100644 --- a/ra/fsp/src/rm_psa_crypto/ecdh_alt.c +++ b/ra/fsp/src/rm_psa_crypto/ecdh_alt.c @@ -2,21 +2,7 @@ * Elliptic curve Diffie-Hellman * * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * This file is part of mbed TLS (https://tls.mbed.org) + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later */ /* @@ -166,6 +152,15 @@ static void ecdh_init_internal(mbedtls_ecdh_context_mbed *ctx) #endif } +mbedtls_ecp_group_id mbedtls_ecdh_get_grp_id(mbedtls_ecdh_context *ctx) +{ +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) + return ctx->MBEDTLS_PRIVATE(grp).id; +#else + return ctx->MBEDTLS_PRIVATE(grp_id); +#endif +} + /* * Initialize context */ @@ -385,7 +380,7 @@ static int ecdh_read_params_internal(mbedtls_ecdh_context_mbed *ctx, const unsigned char *end) { return mbedtls_ecp_tls_read_point(&ctx->grp, &ctx->Qp, buf, - end - *buf); + (size_t) (end - *buf)); } /* @@ -401,7 +396,7 @@ int mbedtls_ecdh_read_params(mbedtls_ecdh_context *ctx, { int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ecp_group_id grp_id; - if ((ret = mbedtls_ecp_tls_read_group_id(&grp_id, buf, end - *buf)) + if ((ret = mbedtls_ecp_tls_read_group_id(&grp_id, buf, (size_t) (end - *buf))) != 0) { return ret; } diff --git a/ra/fsp/src/rm_psa_crypto/ecdsa_alt.c b/ra/fsp/src/rm_psa_crypto/ecdsa_alt.c index 0c10eeee4..60fd3ad8b 100644 --- a/ra/fsp/src/rm_psa_crypto/ecdsa_alt.c +++ b/ra/fsp/src/rm_psa_crypto/ecdsa_alt.c @@ -57,8 +57,9 @@ static const hw_sce_ecc_generatesign_t g_ecdsa_generate_sign_lookup[][2] = HW_SCE_ECC_256HrkGenerateSign, #endif #endif - #if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) || defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) - #if PSA_CRYPTO_IS_PLAINTEXT_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) + #if !BSP_FEATURE_CRYPTO_HAS_RSIP_E11A + #if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) || defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) + #if PSA_CRYPTO_IS_PLAINTEXT_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_384_PRIVATE_KEY_LENGTH_BITS)][RM_PSA_CRYPTO_ECC_KEY_PLAINTEXT] = HW_SCE_ECC_384GenerateSign, #endif @@ -77,6 +78,7 @@ static const hw_sce_ecc_generatesign_t g_ecdsa_generate_sign_lookup[][2] = HW_SCE_ECC_521HrkGenerateSign, #endif #endif +#endif }; static const hw_sce_ecc_generatesign_t g_ed_ecdsa_generate_sign_lookup[][2] = @@ -103,12 +105,14 @@ static const hw_sce_ecc_verifysign_t g_ecdsa_verify_sign_lookup[] = defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_256_PRIVATE_KEY_LENGTH_BITS)] = HW_SCE_ECC_256VerifySign, #endif - #if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) || defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) + #if !BSP_FEATURE_CRYPTO_HAS_RSIP_E11A + #if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) || defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_384_PRIVATE_KEY_LENGTH_BITS)] = HW_SCE_ECC_384VerifySign, #endif #if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_521_PRIVATE_KEY_LENGTH_BITS)] = HW_SCE_ECC_521VerifySign, #endif + #endif }; /* @@ -400,6 +404,7 @@ int ecp_load_curve_attributes_sce (const mbedtls_ecp_group * grp, break; } +#if !BSP_FEATURE_CRYPTO_HAS_RSIP_E11A case MBEDTLS_ECP_DP_SECP384R1: { *p_curve_type = SCE_ECC_CURVE_TYPE_NIST; @@ -455,7 +460,7 @@ int ecp_load_curve_attributes_sce (const mbedtls_ecp_group * grp, *pp_domain_param = (uint32_t *) &DomainParam_Brainpool_384r1[0]; break; } - +#endif default: { ret = -1; diff --git a/ra/fsp/src/rm_psa_crypto/ecdsa_alt_process.c b/ra/fsp/src/rm_psa_crypto/ecdsa_alt_process.c index eabe40090..cd1314313 100644 --- a/ra/fsp/src/rm_psa_crypto/ecdsa_alt_process.c +++ b/ra/fsp/src/rm_psa_crypto/ecdsa_alt_process.c @@ -107,6 +107,7 @@ fsp_err_t HW_SCE_ECC_256HrkGenerateSign (const uint32_t * InData_CurveType, return err; } + #if (!BSP_FEATURE_CRYPTO_HAS_RSIP_E11A) fsp_err_t HW_SCE_ECC_384GenerateSign (const uint32_t * InData_CurveType, const uint32_t * InData_G, const uint32_t * InData_PrivKey, @@ -199,6 +200,7 @@ fsp_err_t HW_SCE_ECC_384HrkGenerateSign (const uint32_t * InData_CurveType, return err; } + #endif #if BSP_FEATURE_CRYPTO_HAS_RSIP7 fsp_err_t HW_SCE_ECC_521GenerateSign (const uint32_t * InData_CurveType, const uint32_t * InData_G, @@ -293,7 +295,9 @@ fsp_err_t HW_SCE_ECC_256VerifySign (const uint32_t * InData_CurveType, const uint32_t * InData_S) { uint32_t signature[HW_SCE_ECDSA_DATA_BYTE_SIZE / 4U] = {0}; + #if (!BSP_FEATURE_CRYPTO_HAS_RSIP_E11A) uint32_t formatted_public_key[ECC_256_FORMATTED_PUBLIC_KEY_LENGTH_WORDS]; + #endif memcpy(signature, InData_R, (HW_SCE_ECDSA_DATA_BYTE_SIZE / 2U)); memcpy(&signature[(HW_SCE_ECDSA_DATA_BYTE_SIZE / 4U) / 2U], InData_S, (HW_SCE_ECDSA_DATA_BYTE_SIZE / 2U)); sce_oem_cmd_t key_command; @@ -318,6 +322,16 @@ fsp_err_t HW_SCE_ECC_256VerifySign (const uint32_t * InData_CurveType, p_domain_param = DomainParam_Koblitz_secp256k1; } + #if (BSP_FEATURE_CRYPTO_HAS_RSIP_E11A) + FSP_PARAMETER_NOT_USED(key_command); + fsp_err_t err = HW_SCE_EcdsaSignatureVerificationSubAdaptor(InData_CurveType, + InData_G, + InData_PubKey, + InData_MsgDgst, + signature, + p_domain_param); + #else + /* Install the plaintext public key to get the formatted public key */ fsp_err_t err = HW_SCE_GenerateOemKeyIndexPrivate(SCE_OEM_KEY_TYPE_PLAIN, key_command, @@ -335,10 +349,11 @@ fsp_err_t HW_SCE_ECC_256VerifySign (const uint32_t * InData_CurveType, signature, p_domain_param); } - +#endif return err; } + #if (!BSP_FEATURE_CRYPTO_HAS_RSIP_E11A) fsp_err_t HW_SCE_ECC_384VerifySign (const uint32_t * InData_CurveType, const uint32_t * InData_G, const uint32_t * InData_PubKey, @@ -392,6 +407,8 @@ fsp_err_t HW_SCE_ECC_384VerifySign (const uint32_t * InData_CurveType, return err; } +#endif + #if BSP_FEATURE_CRYPTO_HAS_RSIP7 fsp_err_t HW_SCE_ECC_255GenerateSign (const uint32_t * InData_CurveType, const uint32_t * InData_G, diff --git a/ra/fsp/src/rm_psa_crypto/ecp_alt.c b/ra/fsp/src/rm_psa_crypto/ecp_alt.c index 0999e61b5..12b9238e7 100644 --- a/ra/fsp/src/rm_psa_crypto/ecp_alt.c +++ b/ra/fsp/src/rm_psa_crypto/ecp_alt.c @@ -2,19 +2,7 @@ * Elliptic curves over GF(p): generic functions * * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later */ /* @@ -24,9 +12,9 @@ * GECC = Guide to Elliptic Curve Cryptography - Hankerson, Menezes, Vanstone * FIPS 186-3 http://csrc.nist.gov/publications/fips/fips186-3/fips_186-3.pdf * RFC 4492 for the related TLS structures and constants -* - https://www.rfc-editor.org/rfc/rfc4492 + * - https://www.rfc-editor.org/rfc/rfc4492 * RFC 7748 for the Curve448 and Curve25519 curve definitions -* - https://www.rfc-editor.org/rfc/rfc7748 + * - https://www.rfc-editor.org/rfc/rfc7748 * * [Curve25519] https://cr.yp.to/ecdh/curve25519-20060209.pdf * @@ -1094,13 +1082,7 @@ static inline int mbedtls_mpi_mul_mod(const mbedtls_ecp_group *grp, MBEDTLS_MPI_CHK(mbedtls_mpi_add_mpi((N), (N), &grp->P)); \ } while (0) -#if (defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) && \ - !(defined(MBEDTLS_ECP_NO_FALLBACK) && \ - defined(MBEDTLS_ECP_DOUBLE_JAC_ALT) && \ - defined(MBEDTLS_ECP_ADD_MIXED_ALT))) || \ - (defined(MBEDTLS_ECP_MONTGOMERY_ENABLED) && \ - !(defined(MBEDTLS_ECP_NO_FALLBACK) && \ - defined(MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT))) +MBEDTLS_MAYBE_UNUSED static inline int mbedtls_mpi_sub_mod(const mbedtls_ecp_group *grp, mbedtls_mpi *X, const mbedtls_mpi *A, @@ -1112,7 +1094,6 @@ static inline int mbedtls_mpi_sub_mod(const mbedtls_ecp_group *grp, cleanup: return ret; } -#endif /* All functions referencing mbedtls_mpi_sub_mod() are alt-implemented without fallback */ /* * Reduce a mbedtls_mpi mod p in-place, to use after mbedtls_mpi_add_mpi and mbedtls_mpi_mul_int. @@ -1135,6 +1116,7 @@ static inline int mbedtls_mpi_add_mod(const mbedtls_ecp_group *grp, return ret; } +MBEDTLS_MAYBE_UNUSED static inline int mbedtls_mpi_mul_int_mod(const mbedtls_ecp_group *grp, mbedtls_mpi *X, const mbedtls_mpi *A, @@ -1148,6 +1130,7 @@ static inline int mbedtls_mpi_mul_int_mod(const mbedtls_ecp_group *grp, return ret; } +MBEDTLS_MAYBE_UNUSED static inline int mbedtls_mpi_sub_int_mod(const mbedtls_ecp_group *grp, mbedtls_mpi *X, const mbedtls_mpi *A, @@ -1164,10 +1147,7 @@ static inline int mbedtls_mpi_sub_int_mod(const mbedtls_ecp_group *grp, #define MPI_ECP_SUB_INT(X, A, c) \ MBEDTLS_MPI_CHK(mbedtls_mpi_sub_int_mod(grp, X, A, c)) -#if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) && \ - !(defined(MBEDTLS_ECP_NO_FALLBACK) && \ - defined(MBEDTLS_ECP_DOUBLE_JAC_ALT) && \ - defined(MBEDTLS_ECP_ADD_MIXED_ALT)) +MBEDTLS_MAYBE_UNUSED static inline int mbedtls_mpi_shift_l_mod(const mbedtls_ecp_group *grp, mbedtls_mpi *X, size_t count) @@ -1178,7 +1158,6 @@ static inline int mbedtls_mpi_shift_l_mod(const mbedtls_ecp_group *grp, cleanup: return ret; } -#endif \ /* All functions referencing mbedtls_mpi_shift_l_mod() are alt-implemented without fallback */ /* @@ -3236,6 +3215,25 @@ int mbedtls_ecp_gen_key(mbedtls_ecp_group_id grp_id, mbedtls_ecp_keypair *key, } #endif /* MBEDTLS_ECP_C */ +int mbedtls_ecp_set_public_key(mbedtls_ecp_group_id grp_id, + mbedtls_ecp_keypair *key, + const mbedtls_ecp_point *Q) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + if (key->grp.id == MBEDTLS_ECP_DP_NONE) { + /* Group not set yet */ + if ((ret = mbedtls_ecp_group_load(&key->grp, grp_id)) != 0) { + return ret; + } + } else if (key->grp.id != grp_id) { + /* Group mismatch */ + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + return mbedtls_ecp_copy(&key->Q, Q); +} + + #define ECP_CURVE25519_KEY_SIZE 32 #define ECP_CURVE448_KEY_SIZE 56 /* @@ -3304,10 +3302,12 @@ int mbedtls_ecp_read_key(mbedtls_ecp_group_id grp_id, mbedtls_ecp_keypair *key, MBEDTLS_MPI_CHK(mbedtls_mpi_read_binary(&key->d, buf, buflen)); } #endif - MBEDTLS_MPI_CHK(mbedtls_ecp_check_privkey(&key->grp, &key->d)); + if (ret == 0) { + MBEDTLS_MPI_CHK(mbedtls_ecp_check_privkey(&key->grp, &key->d)); + } #endif MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &key->d, buf, buflen ) ); - + cleanup: if (ret != 0) { @@ -3320,10 +3320,11 @@ int mbedtls_ecp_read_key(mbedtls_ecp_group_id grp_id, mbedtls_ecp_keypair *key, /* * Write a private key. */ +#if !defined MBEDTLS_DEPRECATED_REMOVED int mbedtls_ecp_write_key(mbedtls_ecp_keypair *key, unsigned char *buf, size_t buflen) { - int ret = MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; #if defined(MBEDTLS_ECP_MONTGOMERY_ENABLED) if (mbedtls_ecp_get_type(&key->grp) == MBEDTLS_ECP_TYPE_MONTGOMERY) { @@ -3350,6 +3351,46 @@ int mbedtls_ecp_write_key(mbedtls_ecp_keypair *key, return ret; } +#endif /* MBEDTLS_DEPRECATED_REMOVED */ + +int mbedtls_ecp_write_key_ext(const mbedtls_ecp_keypair *key, + size_t *olen, unsigned char *buf, size_t buflen) +{ + size_t len = (key->grp.nbits + 7) / 8; + + *olen = len; + + /* Private key not set */ + if (key->d.n == 0) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + +#if defined(MBEDTLS_ECP_MONTGOMERY_ENABLED) + if (mbedtls_ecp_get_type(&key->grp) == MBEDTLS_ECP_TYPE_MONTGOMERY) { + return mbedtls_mpi_write_binary_le(&key->d, buf, buflen); + } +#endif + +#if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) + if (mbedtls_ecp_get_type(&key->grp) == MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS) { + return mbedtls_mpi_write_binary(&key->d, buf, buflen); + } +#endif + + /* Private key set but no recognized curve type? This shouldn't happen. */ + return MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; +} + +/* + * Write a public key. + */ +int mbedtls_ecp_write_public_key(const mbedtls_ecp_keypair *key, + int format, size_t *olen, + unsigned char *buf, size_t buflen) +{ + return mbedtls_ecp_point_write_binary(&key->grp, &key->Q, + format, olen, buf, buflen); +} #if defined(MBEDTLS_ECP_C) /* @@ -3392,8 +3433,22 @@ int mbedtls_ecp_check_pub_priv( return ret; } + +int mbedtls_ecp_keypair_calc_public(mbedtls_ecp_keypair *key, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng) +{ + return mbedtls_ecp_mul(&key->grp, &key->Q, &key->d, &key->grp.G, + f_rng, p_rng); +} #endif /* MBEDTLS_ECP_C */ +mbedtls_ecp_group_id mbedtls_ecp_keypair_get_group_id( + const mbedtls_ecp_keypair *key) +{ + return key->grp.id; +} + /* * Export generic key-pair parameters. */ @@ -3402,15 +3457,15 @@ int mbedtls_ecp_export(const mbedtls_ecp_keypair *key, mbedtls_ecp_group *grp, { int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - if ((ret = mbedtls_ecp_group_copy(grp, &key->grp)) != 0) { + if (grp != NULL && (ret = mbedtls_ecp_group_copy(grp, &key->grp)) != 0) { return ret; } - if ((ret = mbedtls_mpi_copy(d, &key->d)) != 0) { + if (d != NULL && (ret = mbedtls_mpi_copy(d, &key->d)) != 0) { return ret; } - if ((ret = mbedtls_ecp_copy(Q, &key->Q)) != 0) { + if (Q != NULL && (ret = mbedtls_ecp_copy(Q, &key->Q)) != 0) { return ret; } diff --git a/ra/fsp/src/rm_psa_crypto/ecp_alt_process.c b/ra/fsp/src/rm_psa_crypto/ecp_alt_process.c index 51743ff8e..99237f7ba 100644 --- a/ra/fsp/src/rm_psa_crypto/ecp_alt_process.c +++ b/ra/fsp/src/rm_psa_crypto/ecp_alt_process.c @@ -46,12 +46,6 @@ #if defined(MBEDTLS_ECP_ALT) -/* Parameter validation macros based on platform_util.h */ - #define ECP_VALIDATE_RET(cond) \ - MBEDTLS_INTERNAL_VALIDATE_RET(cond, MBEDTLS_ERR_ECP_BAD_INPUT_DATA) - #define ECP_VALIDATE(cond) \ - MBEDTLS_INTERNAL_VALIDATE(cond) - #if defined(MBEDTLS_PLATFORM_C) #include "mbedtls/platform.h" #else @@ -97,7 +91,7 @@ fsp_err_t HW_SCE_ECC_384WrappedScalarMultiplication (const uint32_t * InData_Cur OutData_R); } -#if BSP_FEATURE_CRYPTO_HAS_RSIP7 + #if BSP_FEATURE_CRYPTO_HAS_RSIP7 fsp_err_t HW_SCE_ECC_521WrappedScalarMultiplication (const uint32_t * InData_CurveType, const uint32_t * InData_Cmd, const uint32_t * InData_KeyIndex, @@ -113,21 +107,21 @@ fsp_err_t HW_SCE_ECC_521WrappedScalarMultiplication (const uint32_t * InData_Cur OutData_R); } -#endif + #endif fsp_err_t HW_SCE_ECC_ED25519WrappedScalarMultiplication (const uint32_t * InData_CurveType, - const uint32_t * InData_Cmd, - const uint32_t * InData_KeyIndex, - const uint32_t * InData_P, - const uint32_t * Domain_Param, - uint32_t * OutData_R) + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_P, + const uint32_t * Domain_Param, + uint32_t * OutData_R) { return HW_SCE_EccEd25519ScalarMultiplicationSubAdaptor(InData_CurveType, - InData_Cmd, - InData_KeyIndex, - InData_P, - Domain_Param, - OutData_R); + InData_Cmd, + InData_KeyIndex, + InData_P, + Domain_Param, + OutData_R); } static const hw_sce_ecc_scalarmultiplication_t g_ecp_scalar_multiplication_lookup[][2] = @@ -143,42 +137,44 @@ static const hw_sce_ecc_scalarmultiplication_t g_ecp_scalar_multiplication_looku HW_SCE_ECC_256WrappedScalarMultiplication, #endif #endif - #if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) || defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) - #if PSA_CRYPTO_IS_PLAINTEXT_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) + #if !BSP_FEATURE_CRYPTO_HAS_RSIP_E11A + #if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) || defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) + #if PSA_CRYPTO_IS_PLAINTEXT_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_384_PRIVATE_KEY_LENGTH_BITS)][RM_PSA_CRYPTO_ECC_KEY_PLAINTEXT] = HW_SCE_ECC_384WrappedScalarMultiplication, - #endif - #if PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) + #endif + #if PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_384_PRIVATE_KEY_LENGTH_BITS)][RM_PSA_CRYPTO_ECC_KEY_WRAPPED] = HW_SCE_ECC_384WrappedScalarMultiplication, + #endif #endif - #endif - #if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) + #if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) #if PSA_CRYPTO_IS_PLAINTEXT_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) - [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_521_PRIVATE_KEY_LENGTH_BITS)][RM_PSA_CRYPTO_ECC_KEY_PLAINTEXT] = - HW_SCE_ECC_521WrappedScalarMultiplication, + [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_521_PRIVATE_KEY_LENGTH_BITS)][RM_PSA_CRYPTO_ECC_KEY_PLAINTEXT] = + HW_SCE_ECC_521WrappedScalarMultiplication, #endif #if PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) - [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_521_PRIVATE_KEY_LENGTH_BITS)][RM_PSA_CRYPTO_ECC_KEY_WRAPPED] = - HW_SCE_ECC_521WrappedScalarMultiplication, + [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_521_PRIVATE_KEY_LENGTH_BITS)][RM_PSA_CRYPTO_ECC_KEY_WRAPPED] = + HW_SCE_ECC_521WrappedScalarMultiplication, #endif #endif + #endif }; static const hw_sce_ecc_scalarmultiplication_t g_ecp_edscalar_multiplication_lookup[][2] = { - #if PSA_CRYPTO_IS_PLAINTEXT_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) - [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_25519_PRIVATE_KEY_LENGTH_BITS)][RM_PSA_CRYPTO_ECC_KEY_PLAINTEXT] = - HW_SCE_ECC_ED25519WrappedScalarMultiplication, - [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX((ECC_25519_PRIVATE_KEY_LENGTH_BITS - 1U))][RM_PSA_CRYPTO_ECC_KEY_PLAINTEXT] = - HW_SCE_ECC_ED25519WrappedScalarMultiplication, - #endif - #if PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) - [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_25519_PRIVATE_KEY_LENGTH_BITS)][RM_PSA_CRYPTO_ECC_KEY_WRAPPED] = - HW_SCE_ECC_ED25519WrappedScalarMultiplication, - [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX((ECC_25519_PRIVATE_KEY_LENGTH_BITS - 1U))][RM_PSA_CRYPTO_ECC_KEY_WRAPPED] = - HW_SCE_ECC_ED25519WrappedScalarMultiplication, - #endif + #if PSA_CRYPTO_IS_PLAINTEXT_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) + [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_25519_PRIVATE_KEY_LENGTH_BITS + 1U)][RM_PSA_CRYPTO_ECC_KEY_PLAINTEXT] = + HW_SCE_ECC_ED25519WrappedScalarMultiplication, + [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX((ECC_25519_PRIVATE_KEY_LENGTH_BITS))][RM_PSA_CRYPTO_ECC_KEY_PLAINTEXT] = + HW_SCE_ECC_ED25519WrappedScalarMultiplication, + #endif + #if PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) + [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_25519_PRIVATE_KEY_LENGTH_BITS + 1U)][RM_PSA_CRYPTO_ECC_KEY_WRAPPED] = + HW_SCE_ECC_ED25519WrappedScalarMultiplication, + [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX((ECC_25519_PRIVATE_KEY_LENGTH_BITS))][RM_PSA_CRYPTO_ECC_KEY_WRAPPED] = + HW_SCE_ECC_ED25519WrappedScalarMultiplication, + #endif }; /* @@ -235,42 +231,42 @@ uint32_t ecp_load_key_size (bool wrapped_mode_ctx, const mbedtls_ecp_group * grp } else #endif -#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) - if (ECC_521_PRIVATE_KEY_LENGTH_BITS == grp->pbits) - { - if (wrapped_mode_ctx == true) - { - /* Store size of wrapped private key */ - key_size_words = - R_SCE_BYTES_TO_WORDS(HW_SCE_ECC_WRAPPED_KEY_ADJUST(R_SCE_WORDS_TO_BYTES( - ECC_521_PRIVATE_KEY_LENGTH_WORDS))); - ; - } - else - { - key_size_words = curve_bytes / 4; - } - } - else -#endif -#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) - if ((ECC_25519_PRIVATE_KEY_LENGTH_BITS == grp->pbits) || ((ECC_25519_PRIVATE_KEY_LENGTH_BITS - 1) == grp->pbits)) - { - if (wrapped_mode_ctx == true) - { - /* Store size of wrapped private key */ - key_size_words = - R_SCE_BYTES_TO_WORDS(HW_SCE_ECC_WRAPPED_KEY_ADJUST(R_SCE_WORDS_TO_BYTES( - ECC_25519_PRIVATE_KEY_LENGTH_WORDS))); - ; - } - else - { - key_size_words = curve_bytes / 4; - } - } - else -#endif + #if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) + if (ECC_521_PRIVATE_KEY_LENGTH_BITS == grp->pbits) + { + if (wrapped_mode_ctx == true) + { + /* Store size of wrapped private key */ + key_size_words = + R_SCE_BYTES_TO_WORDS(HW_SCE_ECC_WRAPPED_KEY_ADJUST(R_SCE_WORDS_TO_BYTES( + ECC_521_PRIVATE_KEY_LENGTH_WORDS))); + ; + } + else + { + key_size_words = curve_bytes / 4; + } + } + else + #endif + #if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) + if ((ECC_25519_PRIVATE_KEY_LENGTH_BITS == grp->pbits) || ((ECC_25519_PRIVATE_KEY_LENGTH_BITS - 1) == grp->pbits)) + { + if (wrapped_mode_ctx == true) + { + /* Store size of wrapped private key */ + key_size_words = + R_SCE_BYTES_TO_WORDS(HW_SCE_ECC_WRAPPED_KEY_ADJUST(R_SCE_WORDS_TO_BYTES( + ECC_25519_PRIVATE_KEY_LENGTH_WORDS))); + ; + } + else + { + key_size_words = curve_bytes / 4; + } + } + else + #endif { key_size_words = 0; } @@ -281,24 +277,24 @@ uint32_t ecp_load_key_size (bool wrapped_mode_ctx, const mbedtls_ecp_group * grp uint32_t ed_ecp_load_key_size (bool wrapped_mode_ctx, const mbedtls_ecp_group * grp) { uint32_t key_size_words = 0; -#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) - size_t curve_bytes = PSA_BITS_TO_BYTES(grp->pbits); + #if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) + size_t curve_bytes = PSA_BITS_TO_BYTES(grp->pbits); if (wrapped_mode_ctx == true) { /* Store size of wrapped private key */ - key_size_words = - R_SCE_BYTES_TO_WORDS(HW_SCE_ECC_WRAPPED_KEY_ADJUST(R_SCE_WORDS_TO_BYTES( - ECC_25519_PRIVATE_KEY_LENGTH_WORDS))); - ; + key_size_words = + R_SCE_BYTES_TO_WORDS(HW_SCE_ECC_WRAPPED_KEY_ADJUST(R_SCE_WORDS_TO_BYTES(ECC_25519_PRIVATE_KEY_LENGTH_WORDS))); + ; } else { key_size_words = curve_bytes / 4; } -#else + + #else (void) wrapped_mode_ctx; (void) grp; -#endif + #endif return key_size_words; // NOLINT(readability-misleading-indentation) } @@ -313,23 +309,21 @@ int mbedtls_ecp_gen_privkey (const mbedtls_ecp_group * grp, int ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; - ECP_VALIDATE_RET(grp != NULL); - ECP_VALIDATE_RET(d != NULL); - uint32_t * p_private_key_buff_32; uint32_t * p_common_buff_32; uint32_t private_key_size_words = 0; uint32_t wrapped_key[RM_PSA_CRYPTO_LARGEST_WRAPPED_ECC_PRIVATE_KEY_WORDS] = {0}; uint32_t indata_key_type = 0; - uint8_t padding = 0U; + uint8_t padding = 0U; -#if !BSP_FEATURE_CRYPTO_HAS_SCE7 - if((bool)(grp->vendor_ctx) == false) + #if !BSP_FEATURE_CRYPTO_HAS_SCE7 + if ((bool) (grp->vendor_ctx) == false) { - /* ECC plaintext key generation is not supported currently. */ - return MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; + + /* ECC plaintext key generation is not supported currently. */ + return MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; } -#endif + #endif /* Fail cleanly on curves that HW doesn't support */ if ((!ecp_can_do_sce(grp->id)) || (grp->N.p == NULL)) @@ -338,18 +332,20 @@ int mbedtls_ecp_gen_privkey (const mbedtls_ecp_group * grp, } #if defined(MBEDTLS_CHECK_PARAMS) -#if BSP_FEATURE_CRYPTO_HAS_RSIP7 + #if BSP_FEATURE_CRYPTO_HAS_RSIP7 if ((ECC_256_PRIVATE_KEY_LENGTH_BITS != grp->pbits) && (ECC_384_PRIVATE_KEY_LENGTH_BITS != grp->pbits) && - (ECC_521_PRIVATE_KEY_LENGTH_BITS != grp->pbits) && (ECC_25519_PRIVATE_KEY_LENGTH_BITS != grp->pbits)) -#else + (ECC_521_PRIVATE_KEY_LENGTH_BITS != grp->pbits) && (ECC_25519_PRIVATE_KEY_LENGTH_BITS != grp->pbits)) + #elif BSP_FEATURE_CRYPTO_HAS_RSIP_E11A + if ((ECC_256_PRIVATE_KEY_LENGTH_BITS != grp->pbits)) + #else if ((ECC_256_PRIVATE_KEY_LENGTH_BITS != grp->pbits) && (ECC_384_PRIVATE_KEY_LENGTH_BITS != grp->pbits)) -#endif + #endif { return MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; } #endif - if(MBEDTLS_ECP_DP_CURVE25519 == grp->id) + if (MBEDTLS_ECP_DP_CURVE25519 == grp->id) { private_key_size_words = ed_ecp_load_key_size((bool) grp->vendor_ctx, grp); } @@ -357,6 +353,7 @@ int mbedtls_ecp_gen_privkey (const mbedtls_ecp_group * grp, { private_key_size_words = ecp_load_key_size((bool) grp->vendor_ctx, grp); } + if (0 == private_key_size_words) { return MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; @@ -366,13 +363,15 @@ int mbedtls_ecp_gen_privkey (const mbedtls_ecp_group * grp, if (ECC_521_PRIVATE_KEY_LENGTH_BITS == grp->pbits) { - padding = 14U; /* 14bytes of padding is required for ECC 521 */ + padding = 14U; /* 14bytes of padding is required for ECC 521 */ } + /* Obtain a common 32-bit aligned buffer. It will be used for all the following items in this order: * Private Key (D) of size private_key_size_words * Public Key (Q) of size ECC_PUBLIC_KEY_SIZE_BYTES */ p_common_buff_32 = - mbedtls_calloc((((ECC_PUBLIC_KEY_SIZE_BYTES(curve_bytes) + (padding * 2U))) / 4) + private_key_size_words, sizeof(uint32_t)); + mbedtls_calloc((((ECC_PUBLIC_KEY_SIZE_BYTES(curve_bytes) + (padding * 2U))) / 4) + private_key_size_words, + sizeof(uint32_t)); if (NULL == p_common_buff_32) { @@ -403,7 +402,8 @@ int mbedtls_ecp_gen_privkey (const mbedtls_ecp_group * grp, } } - #if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) || defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) + #if !BSP_FEATURE_CRYPTO_HAS_RSIP_E11A + #if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) || defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) else if (ECC_384_PRIVATE_KEY_LENGTH_BITS == grp->pbits) { sce_ecc384_public_key_index_t public_key = {0}; @@ -421,16 +421,15 @@ int mbedtls_ecp_gen_privkey (const mbedtls_ecp_group * grp, memcpy(p_private_key_buff_32, wrapped_key, private_key_size_words * 4U); } } - #endif + #endif - #if BSP_FEATURE_CRYPTO_HAS_RSIP7 - #if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) + #if BSP_FEATURE_CRYPTO_HAS_RSIP7 + #if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) else if (ECC_521_PRIVATE_KEY_LENGTH_BITS == grp->pbits) { sce_ecc521_public_key_index_t public_key = {0}; if (FSP_SUCCESS != - HW_SCE_GenerateEccP521RandomKeyIndexSub(p_domain_param, - (uint32_t *) &public_key.value, + HW_SCE_GenerateEccP521RandomKeyIndexSub(p_domain_param, (uint32_t *) &public_key.value, (uint32_t *) wrapped_key)) { ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; @@ -440,9 +439,10 @@ int mbedtls_ecp_gen_privkey (const mbedtls_ecp_group * grp, memcpy(p_private_key_buff_32, wrapped_key, private_key_size_words * 4U); } } - #endif - #if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) -// else if (ECC_25519_PRIVATE_KEY_LENGTH_BITS == grp->pbits) + #endif + #if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) + +// else if (ECC_25519_PRIVATE_KEY_LENGTH_BITS == grp->pbits) else if (MBEDTLS_ECP_DP_CURVE25519 == grp->id) { sce_ecc25519_public_key_index_t public_key = {0}; @@ -458,7 +458,8 @@ int mbedtls_ecp_gen_privkey (const mbedtls_ecp_group * grp, memcpy(p_private_key_buff_32, wrapped_key, private_key_size_words * 4U); } } - #endif + #endif + #endif #endif else @@ -501,20 +502,18 @@ int mbedtls_ecp_mul_restartable (mbedtls_ecp_group * grp, (void) p_rng; (void) rs_ctx; - ECP_VALIDATE_RET(grp != NULL); - ECP_VALIDATE_RET(R != NULL); - ECP_VALIDATE_RET(m != NULL); - ECP_VALIDATE_RET(P != NULL); - int ret = 0; fsp_err_t err = FSP_SUCCESS; hw_sce_ecc_scalarmultiplication_t p_hw_sce_ecc_scalarmultiplication = NULL; - uint32_t * p_point_buff_P_32; - uint32_t * p_integer_buff_m_32; - uint32_t * p_point_result_buff_R_32; - uint32_t * p_common_buff_32; + uint32_t * p_point_buff_P_32; + uint32_t * p_integer_buff_m_32; + uint32_t * p_point_result_buff_R_32; + uint32_t * p_common_buff_32; uint8_t padding = 0U; + #if BSP_FEATURE_CRYPTO_HAS_RSIP_E11A + uint32_t indata_key_type = 0; + #endif /* Fail cleanly on curves that HW doesn't support. * Fail if the point co-ordinates are in Jacobian format (only Affine is supported). @@ -525,16 +524,17 @@ int mbedtls_ecp_mul_restartable (mbedtls_ecp_group * grp, return MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; } - if(MBEDTLS_ECP_DP_CURVE25519 == grp->id) + if (MBEDTLS_ECP_DP_CURVE25519 == grp->id) { - p_hw_sce_ecc_scalarmultiplication = - g_ecp_edscalar_multiplication_lookup[RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(grp->pbits)][(bool) grp->vendor_ctx]; + p_hw_sce_ecc_scalarmultiplication = + g_ecp_edscalar_multiplication_lookup[RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(grp->pbits)][(bool) grp->vendor_ctx]; } else { - p_hw_sce_ecc_scalarmultiplication = - g_ecp_scalar_multiplication_lookup[RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(grp->pbits)][(bool) grp->vendor_ctx]; + p_hw_sce_ecc_scalarmultiplication = + g_ecp_scalar_multiplication_lookup[RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(grp->pbits)][(bool) grp->vendor_ctx]; } + if (NULL == p_hw_sce_ecc_scalarmultiplication) { return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; @@ -557,7 +557,7 @@ int mbedtls_ecp_mul_restartable (mbedtls_ecp_group * grp, if (ECC_521_PRIVATE_KEY_LENGTH_BITS == grp->pbits) { - padding = 14U; /* 14bytes of padding is required for HW ECC 521 */ + padding = 14U; /* 14bytes of padding is required for HW ECC 521 */ } /* Obtain a common 32-bit aligned buffer. It will be used for all the following items in this order: @@ -565,7 +565,8 @@ int mbedtls_ecp_mul_restartable (mbedtls_ecp_group * grp, * Multiplication result (R) of size curve_bytes * 2 in format (Rx|Ry) * Input scalar (m) of size m_size_words * Input wrapped scalar (m) of size m_size_wrapped_words */ - p_common_buff_32 = mbedtls_calloc((((curve_bytes + padding) * 4) / 4) + m_size_wrapped_words + m_size_words, sizeof(uint32_t)); + p_common_buff_32 = + mbedtls_calloc((((curve_bytes + padding) * 4) / 4) + m_size_wrapped_words + m_size_words, sizeof(uint32_t)); if (NULL == p_common_buff_32) { @@ -573,8 +574,8 @@ int mbedtls_ecp_mul_restartable (mbedtls_ecp_group * grp, } p_point_buff_P_32 = p_common_buff_32; - p_point_result_buff_R_32 = (uint32_t *)(((uint8_t *)p_point_buff_P_32) + ((curve_bytes + padding) * 2)); - p_integer_buff_m_32 = (uint32_t *)(((uint8_t *)p_point_result_buff_R_32) + ((curve_bytes + padding) * 2)); + p_point_result_buff_R_32 = (uint32_t *) (((uint8_t *) p_point_buff_P_32) + ((curve_bytes + padding) * 2)); + p_integer_buff_m_32 = (uint32_t *) (((uint8_t *) p_point_result_buff_R_32) + ((curve_bytes + padding) * 2)); uint32_t * p_integer_buff_m_wrapped_32 = p_integer_buff_m_32 + m_size_words; uint32_t curve_type; @@ -608,29 +609,38 @@ int mbedtls_ecp_mul_restartable (mbedtls_ecp_group * grp, } /* Write Px into the buffer in reverse */ else if (0 != - mbedtls_mpi_write_binary(&P->X, (((uint8_t *)p_point_buff_P_32) + padding), curve_bytes)) + mbedtls_mpi_write_binary(&P->X, (((uint8_t *) p_point_buff_P_32) + padding), curve_bytes)) { ret = MBEDTLS_ERR_ECP_ALLOC_FAILED; } /* Write Py into the buffer in reverse */ else if (0 != - mbedtls_mpi_write_binary(&P->Y, (((uint8_t *)p_point_buff_P_32) + (curve_bytes + (padding * 2))), curve_bytes)) + mbedtls_mpi_write_binary(&P->Y, (((uint8_t *) p_point_buff_P_32) + (curve_bytes + (padding * 2))), + curve_bytes)) { ret = MBEDTLS_ERR_ECP_ALLOC_FAILED; } + + #if BSP_FEATURE_CRYPTO_HAS_RSIP_E11A + else if (FSP_SUCCESS != + p_hw_sce_ecc_scalarmultiplication(&curve_type, &indata_key_type, p_integer_buff_m_wrapped_32, + p_point_buff_P_32, p_domain_param, p_point_result_buff_R_32)) + #else else if (FSP_SUCCESS != p_hw_sce_ecc_scalarmultiplication(&curve_type, &cmd, p_integer_buff_m_wrapped_32, p_point_buff_P_32, p_domain_param, p_point_result_buff_R_32)) + #endif { ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; } else if (0 != - mbedtls_mpi_read_binary(&R->X, ((uint8_t *)p_point_result_buff_R_32) + padding, curve_bytes)) + mbedtls_mpi_read_binary(&R->X, ((uint8_t *) p_point_result_buff_R_32) + padding, curve_bytes)) { ret = MBEDTLS_ERR_MPI_ALLOC_FAILED; } else if (0 != - mbedtls_mpi_read_binary(&R->Y, (((uint8_t *)p_point_result_buff_R_32) + curve_bytes + (padding * 2)), curve_bytes)) + mbedtls_mpi_read_binary(&R->Y, (((uint8_t *) p_point_result_buff_R_32) + curve_bytes + (padding * 2)), + curve_bytes)) { ret = MBEDTLS_ERR_MPI_ALLOC_FAILED; } diff --git a/ra/fsp/src/rm_psa_crypto/ecp_curves_alt.c b/ra/fsp/src/rm_psa_crypto/ecp_curves_alt.c index ea9324a87..e0f1af6b8 100644 --- a/ra/fsp/src/rm_psa_crypto/ecp_curves_alt.c +++ b/ra/fsp/src/rm_psa_crypto/ecp_curves_alt.c @@ -2,22 +2,8 @@ * This file is a copy of the ecp_curves.c file from mbedCrypto * Elliptic curves over GF(p): curve-specific data and functions * - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * This file is part of mbed TLS (https://tls.mbed.org) + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later */ #include "common.h" @@ -30,55 +16,37 @@ #include "mbedtls/platform_util.h" #include "mbedtls/error.h" +#include "bn_mul.h" #include "bignum_core.h" #include #if defined(MBEDTLS_ECP_ALT) -/* Parameter validation macros based on platform_util.h */ -#define ECP_VALIDATE_RET(cond) \ - MBEDTLS_INTERNAL_VALIDATE_RET(cond, MBEDTLS_ERR_ECP_BAD_INPUT_DATA) -#define ECP_VALIDATE(cond) \ - MBEDTLS_INTERNAL_VALIDATE(cond) - -/* - * Conversion macros for embedded constants: - * build lists of mbedtls_mpi_uint's from lists of unsigned char's grouped by 8, 4 or 2 - */ -#if defined(MBEDTLS_HAVE_INT32) - -#define BYTES_TO_T_UINT_4( a, b, c, d ) \ - ( (mbedtls_mpi_uint) (a) << 0 ) | \ - ( (mbedtls_mpi_uint) (b) << 8 ) | \ - ( (mbedtls_mpi_uint) (c) << 16 ) | \ - ( (mbedtls_mpi_uint) (d) << 24 ) +#define ECP_MPI_INIT(_p, _n) { .p = (mbedtls_mpi_uint *) (_p), .s = 1, .n = (_n) } -#define BYTES_TO_T_UINT_2( a, b ) \ - BYTES_TO_T_UINT_4( a, b, 0, 0 ) +#define ECP_MPI_INIT_ARRAY(x) \ + ECP_MPI_INIT(x, sizeof(x) / sizeof(mbedtls_mpi_uint)) -#define BYTES_TO_T_UINT_8( a, b, c, d, e, f, g, h ) \ - BYTES_TO_T_UINT_4( a, b, c, d ), \ - BYTES_TO_T_UINT_4( e, f, g, h ) +#define ECP_POINT_INIT_XY_Z0(x, y) { \ + ECP_MPI_INIT_ARRAY(x), ECP_MPI_INIT_ARRAY(y), ECP_MPI_INIT(NULL, 0) } +#define ECP_POINT_INIT_XY_Z1(x, y) { \ + ECP_MPI_INIT_ARRAY(x), ECP_MPI_INIT_ARRAY(y), ECP_MPI_INIT(mpi_one, 1) } -#else /* 64-bits */ - -#define BYTES_TO_T_UINT_8( a, b, c, d, e, f, g, h ) \ - ( (mbedtls_mpi_uint) (a) << 0 ) | \ - ( (mbedtls_mpi_uint) (b) << 8 ) | \ - ( (mbedtls_mpi_uint) (c) << 16 ) | \ - ( (mbedtls_mpi_uint) (d) << 24 ) | \ - ( (mbedtls_mpi_uint) (e) << 32 ) | \ - ( (mbedtls_mpi_uint) (f) << 40 ) | \ - ( (mbedtls_mpi_uint) (g) << 48 ) | \ - ( (mbedtls_mpi_uint) (h) << 56 ) - -#define BYTES_TO_T_UINT_4( a, b, c, d ) \ - BYTES_TO_T_UINT_8( a, b, c, d, 0, 0, 0, 0 ) - -#define BYTES_TO_T_UINT_2( a, b ) \ - BYTES_TO_T_UINT_8( a, b, 0, 0, 0, 0, 0, 0 ) - -#endif /* bits in mbedtls_mpi_uint */ +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +/* For these curves, we build the group parameters dynamically. */ +#define ECP_LOAD_GROUP +static const mbedtls_mpi_uint mpi_one[] = { 1 }; +#endif /* * Note: the constants are in little-endian order @@ -90,29 +58,29 @@ */ #if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) static const mbedtls_mpi_uint secp192r1_p[] = { - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), }; static const mbedtls_mpi_uint secp192r1_b[] = { - BYTES_TO_T_UINT_8( 0xB1, 0xB9, 0x46, 0xC1, 0xEC, 0xDE, 0xB8, 0xFE ), - BYTES_TO_T_UINT_8( 0x49, 0x30, 0x24, 0x72, 0xAB, 0xE9, 0xA7, 0x0F ), - BYTES_TO_T_UINT_8( 0xE7, 0x80, 0x9C, 0xE5, 0x19, 0x05, 0x21, 0x64 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xB1, 0xB9, 0x46, 0xC1, 0xEC, 0xDE, 0xB8, 0xFE ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x49, 0x30, 0x24, 0x72, 0xAB, 0xE9, 0xA7, 0x0F ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xE7, 0x80, 0x9C, 0xE5, 0x19, 0x05, 0x21, 0x64 ), }; static const mbedtls_mpi_uint secp192r1_gx[] = { - BYTES_TO_T_UINT_8( 0x12, 0x10, 0xFF, 0x82, 0xFD, 0x0A, 0xFF, 0xF4 ), - BYTES_TO_T_UINT_8( 0x00, 0x88, 0xA1, 0x43, 0xEB, 0x20, 0xBF, 0x7C ), - BYTES_TO_T_UINT_8( 0xF6, 0x90, 0x30, 0xB0, 0x0E, 0xA8, 0x8D, 0x18 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x12, 0x10, 0xFF, 0x82, 0xFD, 0x0A, 0xFF, 0xF4 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x00, 0x88, 0xA1, 0x43, 0xEB, 0x20, 0xBF, 0x7C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xF6, 0x90, 0x30, 0xB0, 0x0E, 0xA8, 0x8D, 0x18 ), }; static const mbedtls_mpi_uint secp192r1_gy[] = { - BYTES_TO_T_UINT_8( 0x11, 0x48, 0x79, 0x1E, 0xA1, 0x77, 0xF9, 0x73 ), - BYTES_TO_T_UINT_8( 0xD5, 0xCD, 0x24, 0x6B, 0xED, 0x11, 0x10, 0x63 ), - BYTES_TO_T_UINT_8( 0x78, 0xDA, 0xC8, 0xFF, 0x95, 0x2B, 0x19, 0x07 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x11, 0x48, 0x79, 0x1E, 0xA1, 0x77, 0xF9, 0x73 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xD5, 0xCD, 0x24, 0x6B, 0xED, 0x11, 0x10, 0x63 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x78, 0xDA, 0xC8, 0xFF, 0x95, 0x2B, 0x19, 0x07 ), }; static const mbedtls_mpi_uint secp192r1_n[] = { - BYTES_TO_T_UINT_8( 0x31, 0x28, 0xD2, 0xB4, 0xB1, 0xC9, 0x6B, 0x14 ), - BYTES_TO_T_UINT_8( 0x36, 0xF8, 0xDE, 0x99, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x31, 0x28, 0xD2, 0xB4, 0xB1, 0xC9, 0x6B, 0x14 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x36, 0xF8, 0xDE, 0x99, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), }; #endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */ @@ -121,34 +89,34 @@ static const mbedtls_mpi_uint secp192r1_n[] = { */ #if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) static const mbedtls_mpi_uint secp224r1_p[] = { - BYTES_TO_T_UINT_8( 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ), - BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 ), }; static const mbedtls_mpi_uint secp224r1_b[] = { - BYTES_TO_T_UINT_8( 0xB4, 0xFF, 0x55, 0x23, 0x43, 0x39, 0x0B, 0x27 ), - BYTES_TO_T_UINT_8( 0xBA, 0xD8, 0xBF, 0xD7, 0xB7, 0xB0, 0x44, 0x50 ), - BYTES_TO_T_UINT_8( 0x56, 0x32, 0x41, 0xF5, 0xAB, 0xB3, 0x04, 0x0C ), - BYTES_TO_T_UINT_4( 0x85, 0x0A, 0x05, 0xB4 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xB4, 0xFF, 0x55, 0x23, 0x43, 0x39, 0x0B, 0x27 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xBA, 0xD8, 0xBF, 0xD7, 0xB7, 0xB0, 0x44, 0x50 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x56, 0x32, 0x41, 0xF5, 0xAB, 0xB3, 0x04, 0x0C ), + MBEDTLS_BYTES_TO_T_UINT_4( 0x85, 0x0A, 0x05, 0xB4 ), }; static const mbedtls_mpi_uint secp224r1_gx[] = { - BYTES_TO_T_UINT_8( 0x21, 0x1D, 0x5C, 0x11, 0xD6, 0x80, 0x32, 0x34 ), - BYTES_TO_T_UINT_8( 0x22, 0x11, 0xC2, 0x56, 0xD3, 0xC1, 0x03, 0x4A ), - BYTES_TO_T_UINT_8( 0xB9, 0x90, 0x13, 0x32, 0x7F, 0xBF, 0xB4, 0x6B ), - BYTES_TO_T_UINT_4( 0xBD, 0x0C, 0x0E, 0xB7 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x21, 0x1D, 0x5C, 0x11, 0xD6, 0x80, 0x32, 0x34 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x22, 0x11, 0xC2, 0x56, 0xD3, 0xC1, 0x03, 0x4A ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xB9, 0x90, 0x13, 0x32, 0x7F, 0xBF, 0xB4, 0x6B ), + MBEDTLS_BYTES_TO_T_UINT_4( 0xBD, 0x0C, 0x0E, 0xB7 ), }; static const mbedtls_mpi_uint secp224r1_gy[] = { - BYTES_TO_T_UINT_8( 0x34, 0x7E, 0x00, 0x85, 0x99, 0x81, 0xD5, 0x44 ), - BYTES_TO_T_UINT_8( 0x64, 0x47, 0x07, 0x5A, 0xA0, 0x75, 0x43, 0xCD ), - BYTES_TO_T_UINT_8( 0xE6, 0xDF, 0x22, 0x4C, 0xFB, 0x23, 0xF7, 0xB5 ), - BYTES_TO_T_UINT_4( 0x88, 0x63, 0x37, 0xBD ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x34, 0x7E, 0x00, 0x85, 0x99, 0x81, 0xD5, 0x44 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x64, 0x47, 0x07, 0x5A, 0xA0, 0x75, 0x43, 0xCD ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xE6, 0xDF, 0x22, 0x4C, 0xFB, 0x23, 0xF7, 0xB5 ), + MBEDTLS_BYTES_TO_T_UINT_4( 0x88, 0x63, 0x37, 0xBD ), }; static const mbedtls_mpi_uint secp224r1_n[] = { - BYTES_TO_T_UINT_8( 0x3D, 0x2A, 0x5C, 0x5C, 0x45, 0x29, 0xDD, 0x13 ), - BYTES_TO_T_UINT_8( 0x3E, 0xF0, 0xB8, 0xE0, 0xA2, 0x16, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_4( 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x3D, 0x2A, 0x5C, 0x5C, 0x45, 0x29, 0xDD, 0x13 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x3E, 0xF0, 0xB8, 0xE0, 0xA2, 0x16, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_4( 0xFF, 0xFF, 0xFF, 0xFF ), }; #endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ @@ -157,34 +125,34 @@ static const mbedtls_mpi_uint secp224r1_n[] = { */ #if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) static const mbedtls_mpi_uint secp256r1_p[] = { - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 ), - BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ), - BYTES_TO_T_UINT_8( 0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), }; static const mbedtls_mpi_uint secp256r1_b[] = { - BYTES_TO_T_UINT_8( 0x4B, 0x60, 0xD2, 0x27, 0x3E, 0x3C, 0xCE, 0x3B ), - BYTES_TO_T_UINT_8( 0xF6, 0xB0, 0x53, 0xCC, 0xB0, 0x06, 0x1D, 0x65 ), - BYTES_TO_T_UINT_8( 0xBC, 0x86, 0x98, 0x76, 0x55, 0xBD, 0xEB, 0xB3 ), - BYTES_TO_T_UINT_8( 0xE7, 0x93, 0x3A, 0xAA, 0xD8, 0x35, 0xC6, 0x5A ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x4B, 0x60, 0xD2, 0x27, 0x3E, 0x3C, 0xCE, 0x3B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xF6, 0xB0, 0x53, 0xCC, 0xB0, 0x06, 0x1D, 0x65 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xBC, 0x86, 0x98, 0x76, 0x55, 0xBD, 0xEB, 0xB3 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xE7, 0x93, 0x3A, 0xAA, 0xD8, 0x35, 0xC6, 0x5A ), }; static const mbedtls_mpi_uint secp256r1_gx[] = { - BYTES_TO_T_UINT_8( 0x96, 0xC2, 0x98, 0xD8, 0x45, 0x39, 0xA1, 0xF4 ), - BYTES_TO_T_UINT_8( 0xA0, 0x33, 0xEB, 0x2D, 0x81, 0x7D, 0x03, 0x77 ), - BYTES_TO_T_UINT_8( 0xF2, 0x40, 0xA4, 0x63, 0xE5, 0xE6, 0xBC, 0xF8 ), - BYTES_TO_T_UINT_8( 0x47, 0x42, 0x2C, 0xE1, 0xF2, 0xD1, 0x17, 0x6B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x96, 0xC2, 0x98, 0xD8, 0x45, 0x39, 0xA1, 0xF4 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA0, 0x33, 0xEB, 0x2D, 0x81, 0x7D, 0x03, 0x77 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xF2, 0x40, 0xA4, 0x63, 0xE5, 0xE6, 0xBC, 0xF8 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x47, 0x42, 0x2C, 0xE1, 0xF2, 0xD1, 0x17, 0x6B ), }; static const mbedtls_mpi_uint secp256r1_gy[] = { - BYTES_TO_T_UINT_8( 0xF5, 0x51, 0xBF, 0x37, 0x68, 0x40, 0xB6, 0xCB ), - BYTES_TO_T_UINT_8( 0xCE, 0x5E, 0x31, 0x6B, 0x57, 0x33, 0xCE, 0x2B ), - BYTES_TO_T_UINT_8( 0x16, 0x9E, 0x0F, 0x7C, 0x4A, 0xEB, 0xE7, 0x8E ), - BYTES_TO_T_UINT_8( 0x9B, 0x7F, 0x1A, 0xFE, 0xE2, 0x42, 0xE3, 0x4F ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xF5, 0x51, 0xBF, 0x37, 0x68, 0x40, 0xB6, 0xCB ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xCE, 0x5E, 0x31, 0x6B, 0x57, 0x33, 0xCE, 0x2B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x16, 0x9E, 0x0F, 0x7C, 0x4A, 0xEB, 0xE7, 0x8E ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x9B, 0x7F, 0x1A, 0xFE, 0xE2, 0x42, 0xE3, 0x4F ), }; static const mbedtls_mpi_uint secp256r1_n[] = { - BYTES_TO_T_UINT_8( 0x51, 0x25, 0x63, 0xFC, 0xC2, 0xCA, 0xB9, 0xF3 ), - BYTES_TO_T_UINT_8( 0x84, 0x9E, 0x17, 0xA7, 0xAD, 0xFA, 0xE6, 0xBC ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x51, 0x25, 0x63, 0xFC, 0xC2, 0xCA, 0xB9, 0xF3 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x84, 0x9E, 0x17, 0xA7, 0xAD, 0xFA, 0xE6, 0xBC ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), }; #endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */ @@ -193,44 +161,44 @@ static const mbedtls_mpi_uint secp256r1_n[] = { */ #if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) static const mbedtls_mpi_uint secp384r1_p[] = { - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 ), - BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), }; static const mbedtls_mpi_uint secp384r1_b[] = { - BYTES_TO_T_UINT_8( 0xEF, 0x2A, 0xEC, 0xD3, 0xED, 0xC8, 0x85, 0x2A ), - BYTES_TO_T_UINT_8( 0x9D, 0xD1, 0x2E, 0x8A, 0x8D, 0x39, 0x56, 0xC6 ), - BYTES_TO_T_UINT_8( 0x5A, 0x87, 0x13, 0x50, 0x8F, 0x08, 0x14, 0x03 ), - BYTES_TO_T_UINT_8( 0x12, 0x41, 0x81, 0xFE, 0x6E, 0x9C, 0x1D, 0x18 ), - BYTES_TO_T_UINT_8( 0x19, 0x2D, 0xF8, 0xE3, 0x6B, 0x05, 0x8E, 0x98 ), - BYTES_TO_T_UINT_8( 0xE4, 0xE7, 0x3E, 0xE2, 0xA7, 0x2F, 0x31, 0xB3 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xEF, 0x2A, 0xEC, 0xD3, 0xED, 0xC8, 0x85, 0x2A ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x9D, 0xD1, 0x2E, 0x8A, 0x8D, 0x39, 0x56, 0xC6 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x5A, 0x87, 0x13, 0x50, 0x8F, 0x08, 0x14, 0x03 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x12, 0x41, 0x81, 0xFE, 0x6E, 0x9C, 0x1D, 0x18 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x19, 0x2D, 0xF8, 0xE3, 0x6B, 0x05, 0x8E, 0x98 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xE4, 0xE7, 0x3E, 0xE2, 0xA7, 0x2F, 0x31, 0xB3 ), }; static const mbedtls_mpi_uint secp384r1_gx[] = { - BYTES_TO_T_UINT_8( 0xB7, 0x0A, 0x76, 0x72, 0x38, 0x5E, 0x54, 0x3A ), - BYTES_TO_T_UINT_8( 0x6C, 0x29, 0x55, 0xBF, 0x5D, 0xF2, 0x02, 0x55 ), - BYTES_TO_T_UINT_8( 0x38, 0x2A, 0x54, 0x82, 0xE0, 0x41, 0xF7, 0x59 ), - BYTES_TO_T_UINT_8( 0x98, 0x9B, 0xA7, 0x8B, 0x62, 0x3B, 0x1D, 0x6E ), - BYTES_TO_T_UINT_8( 0x74, 0xAD, 0x20, 0xF3, 0x1E, 0xC7, 0xB1, 0x8E ), - BYTES_TO_T_UINT_8( 0x37, 0x05, 0x8B, 0xBE, 0x22, 0xCA, 0x87, 0xAA ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xB7, 0x0A, 0x76, 0x72, 0x38, 0x5E, 0x54, 0x3A ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x6C, 0x29, 0x55, 0xBF, 0x5D, 0xF2, 0x02, 0x55 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x38, 0x2A, 0x54, 0x82, 0xE0, 0x41, 0xF7, 0x59 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x98, 0x9B, 0xA7, 0x8B, 0x62, 0x3B, 0x1D, 0x6E ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x74, 0xAD, 0x20, 0xF3, 0x1E, 0xC7, 0xB1, 0x8E ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x37, 0x05, 0x8B, 0xBE, 0x22, 0xCA, 0x87, 0xAA ), }; static const mbedtls_mpi_uint secp384r1_gy[] = { - BYTES_TO_T_UINT_8( 0x5F, 0x0E, 0xEA, 0x90, 0x7C, 0x1D, 0x43, 0x7A ), - BYTES_TO_T_UINT_8( 0x9D, 0x81, 0x7E, 0x1D, 0xCE, 0xB1, 0x60, 0x0A ), - BYTES_TO_T_UINT_8( 0xC0, 0xB8, 0xF0, 0xB5, 0x13, 0x31, 0xDA, 0xE9 ), - BYTES_TO_T_UINT_8( 0x7C, 0x14, 0x9A, 0x28, 0xBD, 0x1D, 0xF4, 0xF8 ), - BYTES_TO_T_UINT_8( 0x29, 0xDC, 0x92, 0x92, 0xBF, 0x98, 0x9E, 0x5D ), - BYTES_TO_T_UINT_8( 0x6F, 0x2C, 0x26, 0x96, 0x4A, 0xDE, 0x17, 0x36 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x5F, 0x0E, 0xEA, 0x90, 0x7C, 0x1D, 0x43, 0x7A ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x9D, 0x81, 0x7E, 0x1D, 0xCE, 0xB1, 0x60, 0x0A ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xC0, 0xB8, 0xF0, 0xB5, 0x13, 0x31, 0xDA, 0xE9 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x7C, 0x14, 0x9A, 0x28, 0xBD, 0x1D, 0xF4, 0xF8 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x29, 0xDC, 0x92, 0x92, 0xBF, 0x98, 0x9E, 0x5D ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x6F, 0x2C, 0x26, 0x96, 0x4A, 0xDE, 0x17, 0x36 ), }; static const mbedtls_mpi_uint secp384r1_n[] = { - BYTES_TO_T_UINT_8( 0x73, 0x29, 0xC5, 0xCC, 0x6A, 0x19, 0xEC, 0xEC ), - BYTES_TO_T_UINT_8( 0x7A, 0xA7, 0xB0, 0x48, 0xB2, 0x0D, 0x1A, 0x58 ), - BYTES_TO_T_UINT_8( 0xDF, 0x2D, 0x37, 0xF4, 0x81, 0x4D, 0x63, 0xC7 ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x73, 0x29, 0xC5, 0xCC, 0x6A, 0x19, 0xEC, 0xEC ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x7A, 0xA7, 0xB0, 0x48, 0xB2, 0x0D, 0x1A, 0x58 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xDF, 0x2D, 0x37, 0xF4, 0x81, 0x4D, 0x63, 0xC7 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), }; #endif /* MBEDTLS_ECP_DP_SECP384R1_ENABLED */ @@ -239,154 +207,154 @@ static const mbedtls_mpi_uint secp384r1_n[] = { */ #if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) static const mbedtls_mpi_uint secp521r1_p[] = { - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_2( 0xFF, 0x01 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_2( 0xFF, 0x01 ), }; static const mbedtls_mpi_uint secp521r1_b[] = { - BYTES_TO_T_UINT_8( 0x00, 0x3F, 0x50, 0x6B, 0xD4, 0x1F, 0x45, 0xEF ), - BYTES_TO_T_UINT_8( 0xF1, 0x34, 0x2C, 0x3D, 0x88, 0xDF, 0x73, 0x35 ), - BYTES_TO_T_UINT_8( 0x07, 0xBF, 0xB1, 0x3B, 0xBD, 0xC0, 0x52, 0x16 ), - BYTES_TO_T_UINT_8( 0x7B, 0x93, 0x7E, 0xEC, 0x51, 0x39, 0x19, 0x56 ), - BYTES_TO_T_UINT_8( 0xE1, 0x09, 0xF1, 0x8E, 0x91, 0x89, 0xB4, 0xB8 ), - BYTES_TO_T_UINT_8( 0xF3, 0x15, 0xB3, 0x99, 0x5B, 0x72, 0xDA, 0xA2 ), - BYTES_TO_T_UINT_8( 0xEE, 0x40, 0x85, 0xB6, 0xA0, 0x21, 0x9A, 0x92 ), - BYTES_TO_T_UINT_8( 0x1F, 0x9A, 0x1C, 0x8E, 0x61, 0xB9, 0x3E, 0x95 ), - BYTES_TO_T_UINT_2( 0x51, 0x00 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x00, 0x3F, 0x50, 0x6B, 0xD4, 0x1F, 0x45, 0xEF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xF1, 0x34, 0x2C, 0x3D, 0x88, 0xDF, 0x73, 0x35 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x07, 0xBF, 0xB1, 0x3B, 0xBD, 0xC0, 0x52, 0x16 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x7B, 0x93, 0x7E, 0xEC, 0x51, 0x39, 0x19, 0x56 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xE1, 0x09, 0xF1, 0x8E, 0x91, 0x89, 0xB4, 0xB8 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xF3, 0x15, 0xB3, 0x99, 0x5B, 0x72, 0xDA, 0xA2 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xEE, 0x40, 0x85, 0xB6, 0xA0, 0x21, 0x9A, 0x92 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x1F, 0x9A, 0x1C, 0x8E, 0x61, 0xB9, 0x3E, 0x95 ), + MBEDTLS_BYTES_TO_T_UINT_2( 0x51, 0x00 ), }; static const mbedtls_mpi_uint secp521r1_gx[] = { - BYTES_TO_T_UINT_8( 0x66, 0xBD, 0xE5, 0xC2, 0x31, 0x7E, 0x7E, 0xF9 ), - BYTES_TO_T_UINT_8( 0x9B, 0x42, 0x6A, 0x85, 0xC1, 0xB3, 0x48, 0x33 ), - BYTES_TO_T_UINT_8( 0xDE, 0xA8, 0xFF, 0xA2, 0x27, 0xC1, 0x1D, 0xFE ), - BYTES_TO_T_UINT_8( 0x28, 0x59, 0xE7, 0xEF, 0x77, 0x5E, 0x4B, 0xA1 ), - BYTES_TO_T_UINT_8( 0xBA, 0x3D, 0x4D, 0x6B, 0x60, 0xAF, 0x28, 0xF8 ), - BYTES_TO_T_UINT_8( 0x21, 0xB5, 0x3F, 0x05, 0x39, 0x81, 0x64, 0x9C ), - BYTES_TO_T_UINT_8( 0x42, 0xB4, 0x95, 0x23, 0x66, 0xCB, 0x3E, 0x9E ), - BYTES_TO_T_UINT_8( 0xCD, 0xE9, 0x04, 0x04, 0xB7, 0x06, 0x8E, 0x85 ), - BYTES_TO_T_UINT_2( 0xC6, 0x00 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x66, 0xBD, 0xE5, 0xC2, 0x31, 0x7E, 0x7E, 0xF9 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x9B, 0x42, 0x6A, 0x85, 0xC1, 0xB3, 0x48, 0x33 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xDE, 0xA8, 0xFF, 0xA2, 0x27, 0xC1, 0x1D, 0xFE ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x28, 0x59, 0xE7, 0xEF, 0x77, 0x5E, 0x4B, 0xA1 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xBA, 0x3D, 0x4D, 0x6B, 0x60, 0xAF, 0x28, 0xF8 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x21, 0xB5, 0x3F, 0x05, 0x39, 0x81, 0x64, 0x9C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x42, 0xB4, 0x95, 0x23, 0x66, 0xCB, 0x3E, 0x9E ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xCD, 0xE9, 0x04, 0x04, 0xB7, 0x06, 0x8E, 0x85 ), + MBEDTLS_BYTES_TO_T_UINT_2( 0xC6, 0x00 ), }; static const mbedtls_mpi_uint secp521r1_gy[] = { - BYTES_TO_T_UINT_8( 0x50, 0x66, 0xD1, 0x9F, 0x76, 0x94, 0xBE, 0x88 ), - BYTES_TO_T_UINT_8( 0x40, 0xC2, 0x72, 0xA2, 0x86, 0x70, 0x3C, 0x35 ), - BYTES_TO_T_UINT_8( 0x61, 0x07, 0xAD, 0x3F, 0x01, 0xB9, 0x50, 0xC5 ), - BYTES_TO_T_UINT_8( 0x40, 0x26, 0xF4, 0x5E, 0x99, 0x72, 0xEE, 0x97 ), - BYTES_TO_T_UINT_8( 0x2C, 0x66, 0x3E, 0x27, 0x17, 0xBD, 0xAF, 0x17 ), - BYTES_TO_T_UINT_8( 0x68, 0x44, 0x9B, 0x57, 0x49, 0x44, 0xF5, 0x98 ), - BYTES_TO_T_UINT_8( 0xD9, 0x1B, 0x7D, 0x2C, 0xB4, 0x5F, 0x8A, 0x5C ), - BYTES_TO_T_UINT_8( 0x04, 0xC0, 0x3B, 0x9A, 0x78, 0x6A, 0x29, 0x39 ), - BYTES_TO_T_UINT_2( 0x18, 0x01 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x50, 0x66, 0xD1, 0x9F, 0x76, 0x94, 0xBE, 0x88 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x40, 0xC2, 0x72, 0xA2, 0x86, 0x70, 0x3C, 0x35 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x61, 0x07, 0xAD, 0x3F, 0x01, 0xB9, 0x50, 0xC5 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x40, 0x26, 0xF4, 0x5E, 0x99, 0x72, 0xEE, 0x97 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x2C, 0x66, 0x3E, 0x27, 0x17, 0xBD, 0xAF, 0x17 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x68, 0x44, 0x9B, 0x57, 0x49, 0x44, 0xF5, 0x98 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xD9, 0x1B, 0x7D, 0x2C, 0xB4, 0x5F, 0x8A, 0x5C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x04, 0xC0, 0x3B, 0x9A, 0x78, 0x6A, 0x29, 0x39 ), + MBEDTLS_BYTES_TO_T_UINT_2( 0x18, 0x01 ), }; static const mbedtls_mpi_uint secp521r1_n[] = { - BYTES_TO_T_UINT_8( 0x09, 0x64, 0x38, 0x91, 0x1E, 0xB7, 0x6F, 0xBB ), - BYTES_TO_T_UINT_8( 0xAE, 0x47, 0x9C, 0x89, 0xB8, 0xC9, 0xB5, 0x3B ), - BYTES_TO_T_UINT_8( 0xD0, 0xA5, 0x09, 0xF7, 0x48, 0x01, 0xCC, 0x7F ), - BYTES_TO_T_UINT_8( 0x6B, 0x96, 0x2F, 0xBF, 0x83, 0x87, 0x86, 0x51 ), - BYTES_TO_T_UINT_8( 0xFA, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_2( 0xFF, 0x01 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x09, 0x64, 0x38, 0x91, 0x1E, 0xB7, 0x6F, 0xBB ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xAE, 0x47, 0x9C, 0x89, 0xB8, 0xC9, 0xB5, 0x3B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xD0, 0xA5, 0x09, 0xF7, 0x48, 0x01, 0xCC, 0x7F ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x6B, 0x96, 0x2F, 0xBF, 0x83, 0x87, 0x86, 0x51 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFA, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_2( 0xFF, 0x01 ), }; #endif /* MBEDTLS_ECP_DP_SECP521R1_ENABLED */ #if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) static const mbedtls_mpi_uint secp192k1_p[] = { - BYTES_TO_T_UINT_8( 0x37, 0xEE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x37, 0xEE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), }; static const mbedtls_mpi_uint secp192k1_a[] = { - BYTES_TO_T_UINT_2( 0x00, 0x00 ), + MBEDTLS_BYTES_TO_T_UINT_2( 0x00, 0x00 ), }; static const mbedtls_mpi_uint secp192k1_b[] = { - BYTES_TO_T_UINT_2( 0x03, 0x00 ), + MBEDTLS_BYTES_TO_T_UINT_2( 0x03, 0x00 ), }; static const mbedtls_mpi_uint secp192k1_gx[] = { - BYTES_TO_T_UINT_8( 0x7D, 0x6C, 0xE0, 0xEA, 0xB1, 0xD1, 0xA5, 0x1D ), - BYTES_TO_T_UINT_8( 0x34, 0xF4, 0xB7, 0x80, 0x02, 0x7D, 0xB0, 0x26 ), - BYTES_TO_T_UINT_8( 0xAE, 0xE9, 0x57, 0xC0, 0x0E, 0xF1, 0x4F, 0xDB ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x7D, 0x6C, 0xE0, 0xEA, 0xB1, 0xD1, 0xA5, 0x1D ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x34, 0xF4, 0xB7, 0x80, 0x02, 0x7D, 0xB0, 0x26 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xAE, 0xE9, 0x57, 0xC0, 0x0E, 0xF1, 0x4F, 0xDB ), }; static const mbedtls_mpi_uint secp192k1_gy[] = { - BYTES_TO_T_UINT_8( 0x9D, 0x2F, 0x5E, 0xD9, 0x88, 0xAA, 0x82, 0x40 ), - BYTES_TO_T_UINT_8( 0x34, 0x86, 0xBE, 0x15, 0xD0, 0x63, 0x41, 0x84 ), - BYTES_TO_T_UINT_8( 0xA7, 0x28, 0x56, 0x9C, 0x6D, 0x2F, 0x2F, 0x9B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x9D, 0x2F, 0x5E, 0xD9, 0x88, 0xAA, 0x82, 0x40 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x34, 0x86, 0xBE, 0x15, 0xD0, 0x63, 0x41, 0x84 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA7, 0x28, 0x56, 0x9C, 0x6D, 0x2F, 0x2F, 0x9B ), }; static const mbedtls_mpi_uint secp192k1_n[] = { - BYTES_TO_T_UINT_8( 0x8D, 0xFD, 0xDE, 0x74, 0x6A, 0x46, 0x69, 0x0F ), - BYTES_TO_T_UINT_8( 0x17, 0xFC, 0xF2, 0x26, 0xFE, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x8D, 0xFD, 0xDE, 0x74, 0x6A, 0x46, 0x69, 0x0F ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x17, 0xFC, 0xF2, 0x26, 0xFE, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), }; #endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED */ #if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) static const mbedtls_mpi_uint secp224k1_p[] = { - BYTES_TO_T_UINT_8( 0x6D, 0xE5, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_4( 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x6D, 0xE5, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_4( 0xFF, 0xFF, 0xFF, 0xFF ), }; static const mbedtls_mpi_uint secp224k1_a[] = { - BYTES_TO_T_UINT_2( 0x00, 0x00 ), + MBEDTLS_BYTES_TO_T_UINT_2( 0x00, 0x00 ), }; static const mbedtls_mpi_uint secp224k1_b[] = { - BYTES_TO_T_UINT_2( 0x05, 0x00 ), + MBEDTLS_BYTES_TO_T_UINT_2( 0x05, 0x00 ), }; static const mbedtls_mpi_uint secp224k1_gx[] = { - BYTES_TO_T_UINT_8( 0x5C, 0xA4, 0xB7, 0xB6, 0x0E, 0x65, 0x7E, 0x0F ), - BYTES_TO_T_UINT_8( 0xA9, 0x75, 0x70, 0xE4, 0xE9, 0x67, 0xA4, 0x69 ), - BYTES_TO_T_UINT_8( 0xA1, 0x28, 0xFC, 0x30, 0xDF, 0x99, 0xF0, 0x4D ), - BYTES_TO_T_UINT_4( 0x33, 0x5B, 0x45, 0xA1 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x5C, 0xA4, 0xB7, 0xB6, 0x0E, 0x65, 0x7E, 0x0F ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA9, 0x75, 0x70, 0xE4, 0xE9, 0x67, 0xA4, 0x69 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA1, 0x28, 0xFC, 0x30, 0xDF, 0x99, 0xF0, 0x4D ), + MBEDTLS_BYTES_TO_T_UINT_4( 0x33, 0x5B, 0x45, 0xA1 ), }; static const mbedtls_mpi_uint secp224k1_gy[] = { - BYTES_TO_T_UINT_8( 0xA5, 0x61, 0x6D, 0x55, 0xDB, 0x4B, 0xCA, 0xE2 ), - BYTES_TO_T_UINT_8( 0x59, 0xBD, 0xB0, 0xC0, 0xF7, 0x19, 0xE3, 0xF7 ), - BYTES_TO_T_UINT_8( 0xD6, 0xFB, 0xCA, 0x82, 0x42, 0x34, 0xBA, 0x7F ), - BYTES_TO_T_UINT_4( 0xED, 0x9F, 0x08, 0x7E ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA5, 0x61, 0x6D, 0x55, 0xDB, 0x4B, 0xCA, 0xE2 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x59, 0xBD, 0xB0, 0xC0, 0xF7, 0x19, 0xE3, 0xF7 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xD6, 0xFB, 0xCA, 0x82, 0x42, 0x34, 0xBA, 0x7F ), + MBEDTLS_BYTES_TO_T_UINT_4( 0xED, 0x9F, 0x08, 0x7E ), }; static const mbedtls_mpi_uint secp224k1_n[] = { - BYTES_TO_T_UINT_8( 0xF7, 0xB1, 0x9F, 0x76, 0x71, 0xA9, 0xF0, 0xCA ), - BYTES_TO_T_UINT_8( 0x84, 0x61, 0xEC, 0xD2, 0xE8, 0xDC, 0x01, 0x00 ), - BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ), - BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xF7, 0xB1, 0x9F, 0x76, 0x71, 0xA9, 0xF0, 0xCA ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x84, 0x61, 0xEC, 0xD2, 0xE8, 0xDC, 0x01, 0x00 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 ), }; #endif /* MBEDTLS_ECP_DP_SECP224K1_ENABLED */ #if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) static const mbedtls_mpi_uint secp256k1_p[] = { - BYTES_TO_T_UINT_8( 0x2F, 0xFC, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x2F, 0xFC, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), }; static const mbedtls_mpi_uint secp256k1_a[] = { - BYTES_TO_T_UINT_2( 0x00, 0x00 ), + MBEDTLS_BYTES_TO_T_UINT_2( 0x00, 0x00 ), }; static const mbedtls_mpi_uint secp256k1_b[] = { - BYTES_TO_T_UINT_2( 0x07, 0x00 ), + MBEDTLS_BYTES_TO_T_UINT_2( 0x07, 0x00 ), }; static const mbedtls_mpi_uint secp256k1_gx[] = { - BYTES_TO_T_UINT_8( 0x98, 0x17, 0xF8, 0x16, 0x5B, 0x81, 0xF2, 0x59 ), - BYTES_TO_T_UINT_8( 0xD9, 0x28, 0xCE, 0x2D, 0xDB, 0xFC, 0x9B, 0x02 ), - BYTES_TO_T_UINT_8( 0x07, 0x0B, 0x87, 0xCE, 0x95, 0x62, 0xA0, 0x55 ), - BYTES_TO_T_UINT_8( 0xAC, 0xBB, 0xDC, 0xF9, 0x7E, 0x66, 0xBE, 0x79 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x98, 0x17, 0xF8, 0x16, 0x5B, 0x81, 0xF2, 0x59 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xD9, 0x28, 0xCE, 0x2D, 0xDB, 0xFC, 0x9B, 0x02 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x07, 0x0B, 0x87, 0xCE, 0x95, 0x62, 0xA0, 0x55 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xAC, 0xBB, 0xDC, 0xF9, 0x7E, 0x66, 0xBE, 0x79 ), }; static const mbedtls_mpi_uint secp256k1_gy[] = { - BYTES_TO_T_UINT_8( 0xB8, 0xD4, 0x10, 0xFB, 0x8F, 0xD0, 0x47, 0x9C ), - BYTES_TO_T_UINT_8( 0x19, 0x54, 0x85, 0xA6, 0x48, 0xB4, 0x17, 0xFD ), - BYTES_TO_T_UINT_8( 0xA8, 0x08, 0x11, 0x0E, 0xFC, 0xFB, 0xA4, 0x5D ), - BYTES_TO_T_UINT_8( 0x65, 0xC4, 0xA3, 0x26, 0x77, 0xDA, 0x3A, 0x48 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xB8, 0xD4, 0x10, 0xFB, 0x8F, 0xD0, 0x47, 0x9C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x19, 0x54, 0x85, 0xA6, 0x48, 0xB4, 0x17, 0xFD ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA8, 0x08, 0x11, 0x0E, 0xFC, 0xFB, 0xA4, 0x5D ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x65, 0xC4, 0xA3, 0x26, 0x77, 0xDA, 0x3A, 0x48 ), }; static const mbedtls_mpi_uint secp256k1_n[] = { - BYTES_TO_T_UINT_8( 0x41, 0x41, 0x36, 0xD0, 0x8C, 0x5E, 0xD2, 0xBF ), - BYTES_TO_T_UINT_8( 0x3B, 0xA0, 0x48, 0xAF, 0xE6, 0xDC, 0xAE, 0xBA ), - BYTES_TO_T_UINT_8( 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), - BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x41, 0x41, 0x36, 0xD0, 0x8C, 0x5E, 0xD2, 0xBF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x3B, 0xA0, 0x48, 0xAF, 0xE6, 0xDC, 0xAE, 0xBA ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), }; #endif /* MBEDTLS_ECP_DP_SECP256K1_ENABLED */ @@ -395,40 +363,40 @@ static const mbedtls_mpi_uint secp256k1_n[] = { */ #if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) static const mbedtls_mpi_uint brainpoolP256r1_p[] = { - BYTES_TO_T_UINT_8( 0x77, 0x53, 0x6E, 0x1F, 0x1D, 0x48, 0x13, 0x20 ), - BYTES_TO_T_UINT_8( 0x28, 0x20, 0x26, 0xD5, 0x23, 0xF6, 0x3B, 0x6E ), - BYTES_TO_T_UINT_8( 0x72, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E ), - BYTES_TO_T_UINT_8( 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x77, 0x53, 0x6E, 0x1F, 0x1D, 0x48, 0x13, 0x20 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x28, 0x20, 0x26, 0xD5, 0x23, 0xF6, 0x3B, 0x6E ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x72, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9 ), }; static const mbedtls_mpi_uint brainpoolP256r1_a[] = { - BYTES_TO_T_UINT_8( 0xD9, 0xB5, 0x30, 0xF3, 0x44, 0x4B, 0x4A, 0xE9 ), - BYTES_TO_T_UINT_8( 0x6C, 0x5C, 0xDC, 0x26, 0xC1, 0x55, 0x80, 0xFB ), - BYTES_TO_T_UINT_8( 0xE7, 0xFF, 0x7A, 0x41, 0x30, 0x75, 0xF6, 0xEE ), - BYTES_TO_T_UINT_8( 0x57, 0x30, 0x2C, 0xFC, 0x75, 0x09, 0x5A, 0x7D ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xD9, 0xB5, 0x30, 0xF3, 0x44, 0x4B, 0x4A, 0xE9 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x6C, 0x5C, 0xDC, 0x26, 0xC1, 0x55, 0x80, 0xFB ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xE7, 0xFF, 0x7A, 0x41, 0x30, 0x75, 0xF6, 0xEE ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x57, 0x30, 0x2C, 0xFC, 0x75, 0x09, 0x5A, 0x7D ), }; static const mbedtls_mpi_uint brainpoolP256r1_b[] = { - BYTES_TO_T_UINT_8( 0xB6, 0x07, 0x8C, 0xFF, 0x18, 0xDC, 0xCC, 0x6B ), - BYTES_TO_T_UINT_8( 0xCE, 0xE1, 0xF7, 0x5C, 0x29, 0x16, 0x84, 0x95 ), - BYTES_TO_T_UINT_8( 0xBF, 0x7C, 0xD7, 0xBB, 0xD9, 0xB5, 0x30, 0xF3 ), - BYTES_TO_T_UINT_8( 0x44, 0x4B, 0x4A, 0xE9, 0x6C, 0x5C, 0xDC, 0x26 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xB6, 0x07, 0x8C, 0xFF, 0x18, 0xDC, 0xCC, 0x6B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xCE, 0xE1, 0xF7, 0x5C, 0x29, 0x16, 0x84, 0x95 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xBF, 0x7C, 0xD7, 0xBB, 0xD9, 0xB5, 0x30, 0xF3 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x44, 0x4B, 0x4A, 0xE9, 0x6C, 0x5C, 0xDC, 0x26 ), }; static const mbedtls_mpi_uint brainpoolP256r1_gx[] = { - BYTES_TO_T_UINT_8( 0x62, 0x32, 0xCE, 0x9A, 0xBD, 0x53, 0x44, 0x3A ), - BYTES_TO_T_UINT_8( 0xC2, 0x23, 0xBD, 0xE3, 0xE1, 0x27, 0xDE, 0xB9 ), - BYTES_TO_T_UINT_8( 0xAF, 0xB7, 0x81, 0xFC, 0x2F, 0x48, 0x4B, 0x2C ), - BYTES_TO_T_UINT_8( 0xCB, 0x57, 0x7E, 0xCB, 0xB9, 0xAE, 0xD2, 0x8B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x62, 0x32, 0xCE, 0x9A, 0xBD, 0x53, 0x44, 0x3A ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xC2, 0x23, 0xBD, 0xE3, 0xE1, 0x27, 0xDE, 0xB9 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xAF, 0xB7, 0x81, 0xFC, 0x2F, 0x48, 0x4B, 0x2C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xCB, 0x57, 0x7E, 0xCB, 0xB9, 0xAE, 0xD2, 0x8B ), }; static const mbedtls_mpi_uint brainpoolP256r1_gy[] = { - BYTES_TO_T_UINT_8( 0x97, 0x69, 0x04, 0x2F, 0xC7, 0x54, 0x1D, 0x5C ), - BYTES_TO_T_UINT_8( 0x54, 0x8E, 0xED, 0x2D, 0x13, 0x45, 0x77, 0xC2 ), - BYTES_TO_T_UINT_8( 0xC9, 0x1D, 0x61, 0x14, 0x1A, 0x46, 0xF8, 0x97 ), - BYTES_TO_T_UINT_8( 0xFD, 0xC4, 0xDA, 0xC3, 0x35, 0xF8, 0x7E, 0x54 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x97, 0x69, 0x04, 0x2F, 0xC7, 0x54, 0x1D, 0x5C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x54, 0x8E, 0xED, 0x2D, 0x13, 0x45, 0x77, 0xC2 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xC9, 0x1D, 0x61, 0x14, 0x1A, 0x46, 0xF8, 0x97 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFD, 0xC4, 0xDA, 0xC3, 0x35, 0xF8, 0x7E, 0x54 ), }; static const mbedtls_mpi_uint brainpoolP256r1_n[] = { - BYTES_TO_T_UINT_8( 0xA7, 0x56, 0x48, 0x97, 0x82, 0x0E, 0x1E, 0x90 ), - BYTES_TO_T_UINT_8( 0xF7, 0xA6, 0x61, 0xB5, 0xA3, 0x7A, 0x39, 0x8C ), - BYTES_TO_T_UINT_8( 0x71, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E ), - BYTES_TO_T_UINT_8( 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA7, 0x56, 0x48, 0x97, 0x82, 0x0E, 0x1E, 0x90 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xF7, 0xA6, 0x61, 0xB5, 0xA3, 0x7A, 0x39, 0x8C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x71, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9 ), }; #endif /* MBEDTLS_ECP_DP_BP256R1_ENABLED */ @@ -437,52 +405,52 @@ static const mbedtls_mpi_uint brainpoolP256r1_n[] = { */ #if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) static const mbedtls_mpi_uint brainpoolP384r1_p[] = { - BYTES_TO_T_UINT_8( 0x53, 0xEC, 0x07, 0x31, 0x13, 0x00, 0x47, 0x87 ), - BYTES_TO_T_UINT_8( 0x71, 0x1A, 0x1D, 0x90, 0x29, 0xA7, 0xD3, 0xAC ), - BYTES_TO_T_UINT_8( 0x23, 0x11, 0xB7, 0x7F, 0x19, 0xDA, 0xB1, 0x12 ), - BYTES_TO_T_UINT_8( 0xB4, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15 ), - BYTES_TO_T_UINT_8( 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F ), - BYTES_TO_T_UINT_8( 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x53, 0xEC, 0x07, 0x31, 0x13, 0x00, 0x47, 0x87 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x71, 0x1A, 0x1D, 0x90, 0x29, 0xA7, 0xD3, 0xAC ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x23, 0x11, 0xB7, 0x7F, 0x19, 0xDA, 0xB1, 0x12 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xB4, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C ), }; static const mbedtls_mpi_uint brainpoolP384r1_a[] = { - BYTES_TO_T_UINT_8( 0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04 ), - BYTES_TO_T_UINT_8( 0xEB, 0xD4, 0x3A, 0x50, 0x4A, 0x81, 0xA5, 0x8A ), - BYTES_TO_T_UINT_8( 0x0F, 0xF9, 0x91, 0xBA, 0xEF, 0x65, 0x91, 0x13 ), - BYTES_TO_T_UINT_8( 0x87, 0x27, 0xB2, 0x4F, 0x8E, 0xA2, 0xBE, 0xC2 ), - BYTES_TO_T_UINT_8( 0xA0, 0xAF, 0x05, 0xCE, 0x0A, 0x08, 0x72, 0x3C ), - BYTES_TO_T_UINT_8( 0x0C, 0x15, 0x8C, 0x3D, 0xC6, 0x82, 0xC3, 0x7B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xEB, 0xD4, 0x3A, 0x50, 0x4A, 0x81, 0xA5, 0x8A ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x0F, 0xF9, 0x91, 0xBA, 0xEF, 0x65, 0x91, 0x13 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x87, 0x27, 0xB2, 0x4F, 0x8E, 0xA2, 0xBE, 0xC2 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA0, 0xAF, 0x05, 0xCE, 0x0A, 0x08, 0x72, 0x3C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x0C, 0x15, 0x8C, 0x3D, 0xC6, 0x82, 0xC3, 0x7B ), }; static const mbedtls_mpi_uint brainpoolP384r1_b[] = { - BYTES_TO_T_UINT_8( 0x11, 0x4C, 0x50, 0xFA, 0x96, 0x86, 0xB7, 0x3A ), - BYTES_TO_T_UINT_8( 0x94, 0xC9, 0xDB, 0x95, 0x02, 0x39, 0xB4, 0x7C ), - BYTES_TO_T_UINT_8( 0xD5, 0x62, 0xEB, 0x3E, 0xA5, 0x0E, 0x88, 0x2E ), - BYTES_TO_T_UINT_8( 0xA6, 0xD2, 0xDC, 0x07, 0xE1, 0x7D, 0xB7, 0x2F ), - BYTES_TO_T_UINT_8( 0x7C, 0x44, 0xF0, 0x16, 0x54, 0xB5, 0x39, 0x8B ), - BYTES_TO_T_UINT_8( 0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x11, 0x4C, 0x50, 0xFA, 0x96, 0x86, 0xB7, 0x3A ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x94, 0xC9, 0xDB, 0x95, 0x02, 0x39, 0xB4, 0x7C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xD5, 0x62, 0xEB, 0x3E, 0xA5, 0x0E, 0x88, 0x2E ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA6, 0xD2, 0xDC, 0x07, 0xE1, 0x7D, 0xB7, 0x2F ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x7C, 0x44, 0xF0, 0x16, 0x54, 0xB5, 0x39, 0x8B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04 ), }; static const mbedtls_mpi_uint brainpoolP384r1_gx[] = { - BYTES_TO_T_UINT_8( 0x1E, 0xAF, 0xD4, 0x47, 0xE2, 0xB2, 0x87, 0xEF ), - BYTES_TO_T_UINT_8( 0xAA, 0x46, 0xD6, 0x36, 0x34, 0xE0, 0x26, 0xE8 ), - BYTES_TO_T_UINT_8( 0xE8, 0x10, 0xBD, 0x0C, 0xFE, 0xCA, 0x7F, 0xDB ), - BYTES_TO_T_UINT_8( 0xE3, 0x4F, 0xF1, 0x7E, 0xE7, 0xA3, 0x47, 0x88 ), - BYTES_TO_T_UINT_8( 0x6B, 0x3F, 0xC1, 0xB7, 0x81, 0x3A, 0xA6, 0xA2 ), - BYTES_TO_T_UINT_8( 0xFF, 0x45, 0xCF, 0x68, 0xF0, 0x64, 0x1C, 0x1D ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x1E, 0xAF, 0xD4, 0x47, 0xE2, 0xB2, 0x87, 0xEF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xAA, 0x46, 0xD6, 0x36, 0x34, 0xE0, 0x26, 0xE8 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xE8, 0x10, 0xBD, 0x0C, 0xFE, 0xCA, 0x7F, 0xDB ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xE3, 0x4F, 0xF1, 0x7E, 0xE7, 0xA3, 0x47, 0x88 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x6B, 0x3F, 0xC1, 0xB7, 0x81, 0x3A, 0xA6, 0xA2 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0x45, 0xCF, 0x68, 0xF0, 0x64, 0x1C, 0x1D ), }; static const mbedtls_mpi_uint brainpoolP384r1_gy[] = { - BYTES_TO_T_UINT_8( 0x15, 0x53, 0x3C, 0x26, 0x41, 0x03, 0x82, 0x42 ), - BYTES_TO_T_UINT_8( 0x11, 0x81, 0x91, 0x77, 0x21, 0x46, 0x46, 0x0E ), - BYTES_TO_T_UINT_8( 0x28, 0x29, 0x91, 0xF9, 0x4F, 0x05, 0x9C, 0xE1 ), - BYTES_TO_T_UINT_8( 0x64, 0x58, 0xEC, 0xFE, 0x29, 0x0B, 0xB7, 0x62 ), - BYTES_TO_T_UINT_8( 0x52, 0xD5, 0xCF, 0x95, 0x8E, 0xEB, 0xB1, 0x5C ), - BYTES_TO_T_UINT_8( 0xA4, 0xC2, 0xF9, 0x20, 0x75, 0x1D, 0xBE, 0x8A ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x15, 0x53, 0x3C, 0x26, 0x41, 0x03, 0x82, 0x42 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x11, 0x81, 0x91, 0x77, 0x21, 0x46, 0x46, 0x0E ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x28, 0x29, 0x91, 0xF9, 0x4F, 0x05, 0x9C, 0xE1 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x64, 0x58, 0xEC, 0xFE, 0x29, 0x0B, 0xB7, 0x62 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x52, 0xD5, 0xCF, 0x95, 0x8E, 0xEB, 0xB1, 0x5C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA4, 0xC2, 0xF9, 0x20, 0x75, 0x1D, 0xBE, 0x8A ), }; static const mbedtls_mpi_uint brainpoolP384r1_n[] = { - BYTES_TO_T_UINT_8( 0x65, 0x65, 0x04, 0xE9, 0x02, 0x32, 0x88, 0x3B ), - BYTES_TO_T_UINT_8( 0x10, 0xC3, 0x7F, 0x6B, 0xAF, 0xB6, 0x3A, 0xCF ), - BYTES_TO_T_UINT_8( 0xA7, 0x25, 0x04, 0xAC, 0x6C, 0x6E, 0x16, 0x1F ), - BYTES_TO_T_UINT_8( 0xB3, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15 ), - BYTES_TO_T_UINT_8( 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F ), - BYTES_TO_T_UINT_8( 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x65, 0x65, 0x04, 0xE9, 0x02, 0x32, 0x88, 0x3B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x10, 0xC3, 0x7F, 0x6B, 0xAF, 0xB6, 0x3A, 0xCF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA7, 0x25, 0x04, 0xAC, 0x6C, 0x6E, 0x16, 0x1F ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xB3, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C ), }; #endif /* MBEDTLS_ECP_DP_BP384R1_ENABLED */ @@ -491,64 +459,64 @@ static const mbedtls_mpi_uint brainpoolP384r1_n[] = { */ #if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) static const mbedtls_mpi_uint brainpoolP512r1_p[] = { - BYTES_TO_T_UINT_8( 0xF3, 0x48, 0x3A, 0x58, 0x56, 0x60, 0xAA, 0x28 ), - BYTES_TO_T_UINT_8( 0x85, 0xC6, 0x82, 0x2D, 0x2F, 0xFF, 0x81, 0x28 ), - BYTES_TO_T_UINT_8( 0xE6, 0x80, 0xA3, 0xE6, 0x2A, 0xA1, 0xCD, 0xAE ), - BYTES_TO_T_UINT_8( 0x42, 0x68, 0xC6, 0x9B, 0x00, 0x9B, 0x4D, 0x7D ), - BYTES_TO_T_UINT_8( 0x71, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6 ), - BYTES_TO_T_UINT_8( 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB ), - BYTES_TO_T_UINT_8( 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F ), - BYTES_TO_T_UINT_8( 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xF3, 0x48, 0x3A, 0x58, 0x56, 0x60, 0xAA, 0x28 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x85, 0xC6, 0x82, 0x2D, 0x2F, 0xFF, 0x81, 0x28 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xE6, 0x80, 0xA3, 0xE6, 0x2A, 0xA1, 0xCD, 0xAE ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x42, 0x68, 0xC6, 0x9B, 0x00, 0x9B, 0x4D, 0x7D ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x71, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA ), }; static const mbedtls_mpi_uint brainpoolP512r1_a[] = { - BYTES_TO_T_UINT_8( 0xCA, 0x94, 0xFC, 0x77, 0x4D, 0xAC, 0xC1, 0xE7 ), - BYTES_TO_T_UINT_8( 0xB9, 0xC7, 0xF2, 0x2B, 0xA7, 0x17, 0x11, 0x7F ), - BYTES_TO_T_UINT_8( 0xB5, 0xC8, 0x9A, 0x8B, 0xC9, 0xF1, 0x2E, 0x0A ), - BYTES_TO_T_UINT_8( 0xA1, 0x3A, 0x25, 0xA8, 0x5A, 0x5D, 0xED, 0x2D ), - BYTES_TO_T_UINT_8( 0xBC, 0x63, 0x98, 0xEA, 0xCA, 0x41, 0x34, 0xA8 ), - BYTES_TO_T_UINT_8( 0x10, 0x16, 0xF9, 0x3D, 0x8D, 0xDD, 0xCB, 0x94 ), - BYTES_TO_T_UINT_8( 0xC5, 0x4C, 0x23, 0xAC, 0x45, 0x71, 0x32, 0xE2 ), - BYTES_TO_T_UINT_8( 0x89, 0x3B, 0x60, 0x8B, 0x31, 0xA3, 0x30, 0x78 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xCA, 0x94, 0xFC, 0x77, 0x4D, 0xAC, 0xC1, 0xE7 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xB9, 0xC7, 0xF2, 0x2B, 0xA7, 0x17, 0x11, 0x7F ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xB5, 0xC8, 0x9A, 0x8B, 0xC9, 0xF1, 0x2E, 0x0A ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA1, 0x3A, 0x25, 0xA8, 0x5A, 0x5D, 0xED, 0x2D ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xBC, 0x63, 0x98, 0xEA, 0xCA, 0x41, 0x34, 0xA8 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x10, 0x16, 0xF9, 0x3D, 0x8D, 0xDD, 0xCB, 0x94 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xC5, 0x4C, 0x23, 0xAC, 0x45, 0x71, 0x32, 0xE2 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x89, 0x3B, 0x60, 0x8B, 0x31, 0xA3, 0x30, 0x78 ), }; static const mbedtls_mpi_uint brainpoolP512r1_b[] = { - BYTES_TO_T_UINT_8( 0x23, 0xF7, 0x16, 0x80, 0x63, 0xBD, 0x09, 0x28 ), - BYTES_TO_T_UINT_8( 0xDD, 0xE5, 0xBA, 0x5E, 0xB7, 0x50, 0x40, 0x98 ), - BYTES_TO_T_UINT_8( 0x67, 0x3E, 0x08, 0xDC, 0xCA, 0x94, 0xFC, 0x77 ), - BYTES_TO_T_UINT_8( 0x4D, 0xAC, 0xC1, 0xE7, 0xB9, 0xC7, 0xF2, 0x2B ), - BYTES_TO_T_UINT_8( 0xA7, 0x17, 0x11, 0x7F, 0xB5, 0xC8, 0x9A, 0x8B ), - BYTES_TO_T_UINT_8( 0xC9, 0xF1, 0x2E, 0x0A, 0xA1, 0x3A, 0x25, 0xA8 ), - BYTES_TO_T_UINT_8( 0x5A, 0x5D, 0xED, 0x2D, 0xBC, 0x63, 0x98, 0xEA ), - BYTES_TO_T_UINT_8( 0xCA, 0x41, 0x34, 0xA8, 0x10, 0x16, 0xF9, 0x3D ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x23, 0xF7, 0x16, 0x80, 0x63, 0xBD, 0x09, 0x28 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xDD, 0xE5, 0xBA, 0x5E, 0xB7, 0x50, 0x40, 0x98 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x67, 0x3E, 0x08, 0xDC, 0xCA, 0x94, 0xFC, 0x77 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x4D, 0xAC, 0xC1, 0xE7, 0xB9, 0xC7, 0xF2, 0x2B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA7, 0x17, 0x11, 0x7F, 0xB5, 0xC8, 0x9A, 0x8B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xC9, 0xF1, 0x2E, 0x0A, 0xA1, 0x3A, 0x25, 0xA8 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x5A, 0x5D, 0xED, 0x2D, 0xBC, 0x63, 0x98, 0xEA ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xCA, 0x41, 0x34, 0xA8, 0x10, 0x16, 0xF9, 0x3D ), }; static const mbedtls_mpi_uint brainpoolP512r1_gx[] = { - BYTES_TO_T_UINT_8( 0x22, 0xF8, 0xB9, 0xBC, 0x09, 0x22, 0x35, 0x8B ), - BYTES_TO_T_UINT_8( 0x68, 0x5E, 0x6A, 0x40, 0x47, 0x50, 0x6D, 0x7C ), - BYTES_TO_T_UINT_8( 0x5F, 0x7D, 0xB9, 0x93, 0x7B, 0x68, 0xD1, 0x50 ), - BYTES_TO_T_UINT_8( 0x8D, 0xD4, 0xD0, 0xE2, 0x78, 0x1F, 0x3B, 0xFF ), - BYTES_TO_T_UINT_8( 0x8E, 0x09, 0xD0, 0xF4, 0xEE, 0x62, 0x3B, 0xB4 ), - BYTES_TO_T_UINT_8( 0xC1, 0x16, 0xD9, 0xB5, 0x70, 0x9F, 0xED, 0x85 ), - BYTES_TO_T_UINT_8( 0x93, 0x6A, 0x4C, 0x9C, 0x2E, 0x32, 0x21, 0x5A ), - BYTES_TO_T_UINT_8( 0x64, 0xD9, 0x2E, 0xD8, 0xBD, 0xE4, 0xAE, 0x81 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x22, 0xF8, 0xB9, 0xBC, 0x09, 0x22, 0x35, 0x8B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x68, 0x5E, 0x6A, 0x40, 0x47, 0x50, 0x6D, 0x7C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x5F, 0x7D, 0xB9, 0x93, 0x7B, 0x68, 0xD1, 0x50 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x8D, 0xD4, 0xD0, 0xE2, 0x78, 0x1F, 0x3B, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x8E, 0x09, 0xD0, 0xF4, 0xEE, 0x62, 0x3B, 0xB4 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xC1, 0x16, 0xD9, 0xB5, 0x70, 0x9F, 0xED, 0x85 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x93, 0x6A, 0x4C, 0x9C, 0x2E, 0x32, 0x21, 0x5A ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x64, 0xD9, 0x2E, 0xD8, 0xBD, 0xE4, 0xAE, 0x81 ), }; static const mbedtls_mpi_uint brainpoolP512r1_gy[] = { - BYTES_TO_T_UINT_8( 0x92, 0x08, 0xD8, 0x3A, 0x0F, 0x1E, 0xCD, 0x78 ), - BYTES_TO_T_UINT_8( 0x06, 0x54, 0xF0, 0xA8, 0x2F, 0x2B, 0xCA, 0xD1 ), - BYTES_TO_T_UINT_8( 0xAE, 0x63, 0x27, 0x8A, 0xD8, 0x4B, 0xCA, 0x5B ), - BYTES_TO_T_UINT_8( 0x5E, 0x48, 0x5F, 0x4A, 0x49, 0xDE, 0xDC, 0xB2 ), - BYTES_TO_T_UINT_8( 0x11, 0x81, 0x1F, 0x88, 0x5B, 0xC5, 0x00, 0xA0 ), - BYTES_TO_T_UINT_8( 0x1A, 0x7B, 0xA5, 0x24, 0x00, 0xF7, 0x09, 0xF2 ), - BYTES_TO_T_UINT_8( 0xFD, 0x22, 0x78, 0xCF, 0xA9, 0xBF, 0xEA, 0xC0 ), - BYTES_TO_T_UINT_8( 0xEC, 0x32, 0x63, 0x56, 0x5D, 0x38, 0xDE, 0x7D ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x92, 0x08, 0xD8, 0x3A, 0x0F, 0x1E, 0xCD, 0x78 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x06, 0x54, 0xF0, 0xA8, 0x2F, 0x2B, 0xCA, 0xD1 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xAE, 0x63, 0x27, 0x8A, 0xD8, 0x4B, 0xCA, 0x5B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x5E, 0x48, 0x5F, 0x4A, 0x49, 0xDE, 0xDC, 0xB2 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x11, 0x81, 0x1F, 0x88, 0x5B, 0xC5, 0x00, 0xA0 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x1A, 0x7B, 0xA5, 0x24, 0x00, 0xF7, 0x09, 0xF2 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFD, 0x22, 0x78, 0xCF, 0xA9, 0xBF, 0xEA, 0xC0 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xEC, 0x32, 0x63, 0x56, 0x5D, 0x38, 0xDE, 0x7D ), }; static const mbedtls_mpi_uint brainpoolP512r1_n[] = { - BYTES_TO_T_UINT_8( 0x69, 0x00, 0xA9, 0x9C, 0x82, 0x96, 0x87, 0xB5 ), - BYTES_TO_T_UINT_8( 0xDD, 0xDA, 0x5D, 0x08, 0x81, 0xD3, 0xB1, 0x1D ), - BYTES_TO_T_UINT_8( 0x47, 0x10, 0xAC, 0x7F, 0x19, 0x61, 0x86, 0x41 ), - BYTES_TO_T_UINT_8( 0x19, 0x26, 0xA9, 0x4C, 0x41, 0x5C, 0x3E, 0x55 ), - BYTES_TO_T_UINT_8( 0x70, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6 ), - BYTES_TO_T_UINT_8( 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB ), - BYTES_TO_T_UINT_8( 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F ), - BYTES_TO_T_UINT_8( 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x69, 0x00, 0xA9, 0x9C, 0x82, 0x96, 0x87, 0xB5 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xDD, 0xDA, 0x5D, 0x08, 0x81, 0xD3, 0xB1, 0x1D ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x47, 0x10, 0xAC, 0x7F, 0x19, 0x61, 0x86, 0x41 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x19, 0x26, 0xA9, 0x4C, 0x41, 0x5C, 0x3E, 0x55 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x70, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA ), }; #endif /* MBEDTLS_ECP_DP_BP512R1_ENABLED */ @@ -570,10 +538,9 @@ static inline void ecp_mpi_load(mbedtls_mpi *X, const mbedtls_mpi_uint *p, size_ */ static inline void ecp_mpi_set1(mbedtls_mpi *X) { - static mbedtls_mpi_uint one[] = { 1 }; X->s = 1; X->n = 1; - X->p = one; + X->p = (mbedtls_mpi_uint *) mpi_one; /* X->p will not be modified so the cast is safe */ } /* @@ -754,7 +721,6 @@ static int ecp_use_curve448(mbedtls_ecp_group *grp) */ int mbedtls_ecp_group_load(mbedtls_ecp_group *grp, mbedtls_ecp_group_id id) { - ECP_VALIDATE_RET(grp != NULL); mbedtls_ecp_group_free(grp); mbedtls_ecp_group_init(grp); @@ -1351,7 +1317,7 @@ static int ecp_mod_p448(mbedtls_mpi *N) */ #define P_KOBLITZ_MAX (256 / 8 / sizeof(mbedtls_mpi_uint)) // Max limbs in P #define P_KOBLITZ_R (8 / sizeof(mbedtls_mpi_uint)) // Limbs in R -static inline int ecp_mod_koblitz(mbedtls_mpi *N, mbedtls_mpi_uint *Rp, size_t p_limbs, +static inline int ecp_mod_koblitz(mbedtls_mpi *N, const mbedtls_mpi_uint *Rp, size_t p_limbs, size_t adjust, size_t shift, mbedtls_mpi_uint mask) { int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; @@ -1365,7 +1331,7 @@ static inline int ecp_mod_koblitz(mbedtls_mpi *N, mbedtls_mpi_uint *Rp, size_t p /* Init R */ R.s = 1; - R.p = Rp; + R.p = (mbedtls_mpi_uint *) Rp; /* R.p will not be modified so the cast is safe */ R.n = P_KOBLITZ_R; /* Common setup for M */ @@ -1436,8 +1402,8 @@ static inline int ecp_mod_koblitz(mbedtls_mpi *N, mbedtls_mpi_uint *Rp, size_t p */ static int ecp_mod_p192k1( mbedtls_mpi *N ) { - static mbedtls_mpi_uint Rp[] = { - BYTES_TO_T_UINT_8( 0xC9, 0x11, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 ) }; + static const mbedtls_mpi_uint Rp[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0xC9, 0x11, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 ) }; return( ecp_mod_koblitz( N, Rp, 192 / 8 / sizeof( mbedtls_mpi_uint ), 0, 0, 0 ) ); } @@ -1450,8 +1416,8 @@ static int ecp_mod_p192k1( mbedtls_mpi *N ) */ static int ecp_mod_p224k1(mbedtls_mpi *N) { - static mbedtls_mpi_uint Rp[] = { - BYTES_TO_T_UINT_8(0x93, 0x1A, 0x00, 0x00, 0x01, 0x00, 0x00, + static const mbedtls_mpi_uint Rp[] = { + MBEDTLS_BYTES_TO_T_UINT_8(0x93, 0x1A, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00) }; @@ -1472,8 +1438,8 @@ static int ecp_mod_p224k1(mbedtls_mpi *N) */ static int ecp_mod_p256k1(mbedtls_mpi *N) { - static mbedtls_mpi_uint Rp[] = { - BYTES_TO_T_UINT_8(0xD1, 0x03, 0x00, 0x00, 0x01, 0x00, 0x00, + static const mbedtls_mpi_uint Rp[] = { + MBEDTLS_BYTES_TO_T_UINT_8(0xD1, 0x03, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00) }; return ecp_mod_koblitz(N, Rp, 256 / 8 / sizeof(mbedtls_mpi_uint), 0, 0, diff --git a/ra/fsp/src/rm_psa_crypto/gcm_alt.c b/ra/fsp/src/rm_psa_crypto/gcm_alt.c index 632a92361..c4bef920e 100644 --- a/ra/fsp/src/rm_psa_crypto/gcm_alt.c +++ b/ra/fsp/src/rm_psa_crypto/gcm_alt.c @@ -2,19 +2,7 @@ * NIST SP800-38D compliant GCM implementation * * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later */ /* @@ -37,6 +25,10 @@ #include "mbedtls/error.h" #include "mbedtls/constant_time.h" +#if defined(MBEDTLS_BLOCK_CIPHER_C) +#include "block_cipher_internal.h" +#endif + #include #if defined(MBEDTLS_AESNI_C) @@ -50,6 +42,12 @@ #if defined(MBEDTLS_GCM_ALT) #include "gcm_alt.h" +/* Used to select the acceleration mechanism */ +#define MBEDTLS_GCM_ACC_SMALLTABLE 0 +#define MBEDTLS_GCM_ACC_LARGETABLE 1 +#define MBEDTLS_GCM_ACC_AESNI 2 +#define MBEDTLS_GCM_ACC_AESCE 3 + /* * Initialize a context */ @@ -58,6 +56,39 @@ void mbedtls_gcm_init(mbedtls_gcm_context *ctx) memset(ctx, 0, sizeof(mbedtls_gcm_context)); } +static inline void gcm_set_acceleration(mbedtls_gcm_context *ctx) +{ +#if defined(MBEDTLS_GCM_LARGE_TABLE) + ctx->acceleration = MBEDTLS_GCM_ACC_LARGETABLE; +#else + ctx->acceleration = MBEDTLS_GCM_ACC_SMALLTABLE; +#endif + +#if defined(MBEDTLS_AESNI_HAVE_CODE) + /* With CLMUL support, we need only h, not the rest of the table */ + if (mbedtls_aesni_has_support(MBEDTLS_AESNI_CLMUL)) { + ctx->acceleration = MBEDTLS_GCM_ACC_AESNI; + } +#endif + +#if defined(MBEDTLS_AESCE_HAVE_CODE) + if (MBEDTLS_AESCE_HAS_SUPPORT()) { + ctx->acceleration = MBEDTLS_GCM_ACC_AESCE; + } +#endif +} + +static inline void gcm_gen_table_rightshift(uint64_t dst[2], const uint64_t src[2]) +{ + uint8_t *u8Dst = (uint8_t *) dst; + uint8_t *u8Src = (uint8_t *) src; + + MBEDTLS_PUT_UINT64_BE(MBEDTLS_GET_UINT64_BE(&src[1], 0) >> 1, &dst[1], 0); + u8Dst[8] |= (u8Src[7] & 0x01) << 7; + MBEDTLS_PUT_UINT64_BE(MBEDTLS_GET_UINT64_BE(&src[0], 0) >> 1, &dst[0], 0); + u8Dst[0] ^= (u8Src[15] & 0x01) ? 0xE1 : 0; +} + /* * Precompute small multiples of H, that is set * HH[i] || HL[i] = H times i, @@ -69,63 +100,61 @@ void mbedtls_gcm_init(mbedtls_gcm_context *ctx) static int gcm_gen_table(mbedtls_gcm_context *ctx) { int ret, i, j; - uint64_t hi, lo; - uint64_t vl, vh; - unsigned char h[16]; - size_t olen = 0; + uint64_t u64h[2] = { 0 }; + uint8_t *h = (uint8_t *) u64h; - memset(h, 0, 16); - if ((ret = mbedtls_cipher_update(&ctx->cipher_ctx, h, 16, h, &olen)) != 0) { +#if defined(MBEDTLS_BLOCK_CIPHER_C) + ret = mbedtls_block_cipher_encrypt(&ctx->block_cipher_ctx, h, h); +#else + size_t olen = 0; + ret = mbedtls_cipher_update(&ctx->cipher_ctx, h, 16, h, &olen); +#endif + if (ret != 0) { return ret; } - /* pack h as two 64-bits ints, big-endian */ - hi = MBEDTLS_GET_UINT32_BE(h, 0); - lo = MBEDTLS_GET_UINT32_BE(h, 4); - vh = (uint64_t) hi << 32 | lo; - - hi = MBEDTLS_GET_UINT32_BE(h, 8); - lo = MBEDTLS_GET_UINT32_BE(h, 12); - vl = (uint64_t) hi << 32 | lo; + gcm_set_acceleration(ctx); - /* 8 = 1000 corresponds to 1 in GF(2^128) */ - ctx->HL[8] = vl; - ctx->HH[8] = vh; + /* MBEDTLS_GCM_HTABLE_SIZE/2 = 1000 corresponds to 1 in GF(2^128) */ + ctx->H[MBEDTLS_GCM_HTABLE_SIZE/2][0] = u64h[0]; + ctx->H[MBEDTLS_GCM_HTABLE_SIZE/2][1] = u64h[1]; + switch (ctx->acceleration) { #if defined(MBEDTLS_AESNI_HAVE_CODE) - /* With CLMUL support, we need only h, not the rest of the table */ - if (mbedtls_aesni_has_support(MBEDTLS_AESNI_CLMUL)) { - return 0; - } + case MBEDTLS_GCM_ACC_AESNI: + return 0; #endif #if defined(MBEDTLS_AESCE_HAVE_CODE) - if (MBEDTLS_AESCE_HAS_SUPPORT()) { - return 0; - } + case MBEDTLS_GCM_ACC_AESCE: + return 0; #endif - /* 0 corresponds to 0 in GF(2^128) */ - ctx->HH[0] = 0; - ctx->HL[0] = 0; + default: + /* 0 corresponds to 0 in GF(2^128) */ + ctx->H[0][0] = 0; + ctx->H[0][1] = 0; - for (i = 4; i > 0; i >>= 1) { - uint32_t T = (vl & 1) * 0xe1000000U; - vl = (vh << 63) | (vl >> 1); - vh = (vh >> 1) ^ ((uint64_t) T << 32); + for (i = MBEDTLS_GCM_HTABLE_SIZE/4; i > 0; i >>= 1) { + gcm_gen_table_rightshift(ctx->H[i], ctx->H[i*2]); + } - ctx->HL[i] = vl; - ctx->HH[i] = vh; - } +#if !defined(MBEDTLS_GCM_LARGE_TABLE) + /* pack elements of H as 64-bits ints, big-endian */ + for (i = MBEDTLS_GCM_HTABLE_SIZE/2; i > 0; i >>= 1) { + MBEDTLS_PUT_UINT64_BE(ctx->H[i][0], &ctx->H[i][0], 0); + MBEDTLS_PUT_UINT64_BE(ctx->H[i][1], &ctx->H[i][1], 0); + } +#endif - for (i = 2; i <= 8; i *= 2) { - uint64_t *HiL = ctx->HL + i, *HiH = ctx->HH + i; - vh = *HiH; - vl = *HiL; - for (j = 1; j < i; j++) { - HiH[j] = vh ^ ctx->HH[j]; - HiL[j] = vl ^ ctx->HL[j]; - } + for (i = 2; i < MBEDTLS_GCM_HTABLE_SIZE; i <<= 1) { + for (j = 1; j < i; j++) { + mbedtls_xor_no_simd((unsigned char *) ctx->H[i+j], + (unsigned char *) ctx->H[i], + (unsigned char *) ctx->H[j], + 16); + } + } } return 0; @@ -137,12 +166,24 @@ int mbedtls_gcm_setkey(mbedtls_gcm_context *ctx, unsigned int keybits) { int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - const mbedtls_cipher_info_t *cipher_info; if (keybits != 128 && keybits != 192 && keybits != 256) { return MBEDTLS_ERR_GCM_BAD_INPUT; } +#if defined(MBEDTLS_BLOCK_CIPHER_C) + mbedtls_block_cipher_free(&ctx->block_cipher_ctx); + + if ((ret = mbedtls_block_cipher_setup(&ctx->block_cipher_ctx, cipher)) != 0) { + return ret; + } + + if ((ret = mbedtls_block_cipher_setkey(&ctx->block_cipher_ctx, key, keybits)) != 0) { + return ret; + } +#else + const mbedtls_cipher_info_t *cipher_info; + cipher_info = mbedtls_cipher_info_from_values(cipher, keybits, MBEDTLS_MODE_ECB); if (cipher_info == NULL) { @@ -169,6 +210,7 @@ int mbedtls_gcm_setkey(mbedtls_gcm_context *ctx, MBEDTLS_ENCRYPT)) != 0) { return ret; } +#endif if ((ret = gcm_gen_table(ctx)) != 0) { return ret; @@ -177,6 +219,80 @@ int mbedtls_gcm_setkey(mbedtls_gcm_context *ctx, return 0; } +#if defined(MBEDTLS_GCM_LARGE_TABLE) +static const uint16_t last8[256] = { + 0x0000, 0xc201, 0x8403, 0x4602, 0x0807, 0xca06, 0x8c04, 0x4e05, + 0x100e, 0xd20f, 0x940d, 0x560c, 0x1809, 0xda08, 0x9c0a, 0x5e0b, + 0x201c, 0xe21d, 0xa41f, 0x661e, 0x281b, 0xea1a, 0xac18, 0x6e19, + 0x3012, 0xf213, 0xb411, 0x7610, 0x3815, 0xfa14, 0xbc16, 0x7e17, + 0x4038, 0x8239, 0xc43b, 0x063a, 0x483f, 0x8a3e, 0xcc3c, 0x0e3d, + 0x5036, 0x9237, 0xd435, 0x1634, 0x5831, 0x9a30, 0xdc32, 0x1e33, + 0x6024, 0xa225, 0xe427, 0x2626, 0x6823, 0xaa22, 0xec20, 0x2e21, + 0x702a, 0xb22b, 0xf429, 0x3628, 0x782d, 0xba2c, 0xfc2e, 0x3e2f, + 0x8070, 0x4271, 0x0473, 0xc672, 0x8877, 0x4a76, 0x0c74, 0xce75, + 0x907e, 0x527f, 0x147d, 0xd67c, 0x9879, 0x5a78, 0x1c7a, 0xde7b, + 0xa06c, 0x626d, 0x246f, 0xe66e, 0xa86b, 0x6a6a, 0x2c68, 0xee69, + 0xb062, 0x7263, 0x3461, 0xf660, 0xb865, 0x7a64, 0x3c66, 0xfe67, + 0xc048, 0x0249, 0x444b, 0x864a, 0xc84f, 0x0a4e, 0x4c4c, 0x8e4d, + 0xd046, 0x1247, 0x5445, 0x9644, 0xd841, 0x1a40, 0x5c42, 0x9e43, + 0xe054, 0x2255, 0x6457, 0xa656, 0xe853, 0x2a52, 0x6c50, 0xae51, + 0xf05a, 0x325b, 0x7459, 0xb658, 0xf85d, 0x3a5c, 0x7c5e, 0xbe5f, + 0x00e1, 0xc2e0, 0x84e2, 0x46e3, 0x08e6, 0xcae7, 0x8ce5, 0x4ee4, + 0x10ef, 0xd2ee, 0x94ec, 0x56ed, 0x18e8, 0xdae9, 0x9ceb, 0x5eea, + 0x20fd, 0xe2fc, 0xa4fe, 0x66ff, 0x28fa, 0xeafb, 0xacf9, 0x6ef8, + 0x30f3, 0xf2f2, 0xb4f0, 0x76f1, 0x38f4, 0xfaf5, 0xbcf7, 0x7ef6, + 0x40d9, 0x82d8, 0xc4da, 0x06db, 0x48de, 0x8adf, 0xccdd, 0x0edc, + 0x50d7, 0x92d6, 0xd4d4, 0x16d5, 0x58d0, 0x9ad1, 0xdcd3, 0x1ed2, + 0x60c5, 0xa2c4, 0xe4c6, 0x26c7, 0x68c2, 0xaac3, 0xecc1, 0x2ec0, + 0x70cb, 0xb2ca, 0xf4c8, 0x36c9, 0x78cc, 0xbacd, 0xfccf, 0x3ece, + 0x8091, 0x4290, 0x0492, 0xc693, 0x8896, 0x4a97, 0x0c95, 0xce94, + 0x909f, 0x529e, 0x149c, 0xd69d, 0x9898, 0x5a99, 0x1c9b, 0xde9a, + 0xa08d, 0x628c, 0x248e, 0xe68f, 0xa88a, 0x6a8b, 0x2c89, 0xee88, + 0xb083, 0x7282, 0x3480, 0xf681, 0xb884, 0x7a85, 0x3c87, 0xfe86, + 0xc0a9, 0x02a8, 0x44aa, 0x86ab, 0xc8ae, 0x0aaf, 0x4cad, 0x8eac, + 0xd0a7, 0x12a6, 0x54a4, 0x96a5, 0xd8a0, 0x1aa1, 0x5ca3, 0x9ea2, + 0xe0b5, 0x22b4, 0x64b6, 0xa6b7, 0xe8b2, 0x2ab3, 0x6cb1, 0xaeb0, + 0xf0bb, 0x32ba, 0x74b8, 0xb6b9, 0xf8bc, 0x3abd, 0x7cbf, 0xbebe +}; + +static void gcm_mult_largetable(uint8_t *output, const uint8_t *x, uint64_t H[256][2]) +{ + int i; + uint64_t u64z[2]; + uint16_t *u16z = (uint16_t *) u64z; + uint8_t *u8z = (uint8_t *) u64z; + uint8_t rem; + + u64z[0] = 0; + u64z[1] = 0; + + if (MBEDTLS_IS_BIG_ENDIAN) { + for (i = 15; i > 0; i--) { + mbedtls_xor_no_simd(u8z, u8z, (uint8_t *) H[x[i]], 16); + rem = u8z[15]; + + u64z[1] >>= 8; + u8z[8] = u8z[7]; + u64z[0] >>= 8; + + u16z[0] ^= MBEDTLS_GET_UINT16_LE(&last8[rem], 0); + } + } else { + for (i = 15; i > 0; i--) { + mbedtls_xor_no_simd(u8z, u8z, (uint8_t *) H[x[i]], 16); + rem = u8z[15]; + + u64z[1] <<= 8; + u8z[8] = u8z[7]; + u64z[0] <<= 8; + + u16z[0] ^= last8[rem]; + } + } + + mbedtls_xor_no_simd(output, u8z, (uint8_t *) H[x[0]], 16); +} +#else /* * Shoup's method for multiplication use this table with * last4[x] = x times P^128 @@ -190,78 +306,79 @@ static const uint16_t last4[16] = 0x9180, 0x8da0, 0xa9c0, 0xb5e0 }; -/* - * Sets output to x times H using the precomputed tables. - * x and output are seen as elements of GF(2^128) as in [MGV]. - */ -static void gcm_mult(mbedtls_gcm_context *ctx, const unsigned char x[16], - unsigned char output[16]) +static void gcm_mult_smalltable(uint8_t *output, const uint8_t *x, uint64_t H[16][2]) { int i = 0; unsigned char lo, hi, rem; - uint64_t zh, zl; + uint64_t u64z[2]; + const uint64_t *pu64z = NULL; + uint8_t *u8z = (uint8_t *) u64z; -#if defined(MBEDTLS_AESNI_HAVE_CODE) - if (mbedtls_aesni_has_support(MBEDTLS_AESNI_CLMUL)) { - unsigned char h[16]; - - /* mbedtls_aesni_gcm_mult needs big-endian input */ - MBEDTLS_PUT_UINT32_BE(ctx->HH[8] >> 32, h, 0); - MBEDTLS_PUT_UINT32_BE(ctx->HH[8], h, 4); - MBEDTLS_PUT_UINT32_BE(ctx->HL[8] >> 32, h, 8); - MBEDTLS_PUT_UINT32_BE(ctx->HL[8], h, 12); + lo = x[15] & 0xf; + hi = (x[15] >> 4) & 0xf; - mbedtls_aesni_gcm_mult(output, x, h); - return; - } -#endif /* MBEDTLS_AESNI_HAVE_CODE */ + pu64z = H[lo]; -#if defined(MBEDTLS_AESCE_HAVE_CODE) - if (MBEDTLS_AESCE_HAS_SUPPORT()) { - unsigned char h[16]; + rem = (unsigned char) pu64z[1] & 0xf; + u64z[1] = (pu64z[0] << 60) | (pu64z[1] >> 4); + u64z[0] = (pu64z[0] >> 4); + u64z[0] ^= (uint64_t) last4[rem] << 48; + mbedtls_xor_no_simd(u8z, u8z, (uint8_t *) H[hi], 16); - /* mbedtls_aesce_gcm_mult needs big-endian input */ - MBEDTLS_PUT_UINT32_BE(ctx->HH[8] >> 32, h, 0); - MBEDTLS_PUT_UINT32_BE(ctx->HH[8], h, 4); - MBEDTLS_PUT_UINT32_BE(ctx->HL[8] >> 32, h, 8); - MBEDTLS_PUT_UINT32_BE(ctx->HL[8], h, 12); + for (i = 14; i >= 0; i--) { + lo = x[i] & 0xf; + hi = (x[i] >> 4) & 0xf; - mbedtls_aesce_gcm_mult(output, x, h); - return; + rem = (unsigned char) u64z[1] & 0xf; + u64z[1] = (u64z[0] << 60) | (u64z[1] >> 4); + u64z[0] = (u64z[0] >> 4); + u64z[0] ^= (uint64_t) last4[rem] << 48; + mbedtls_xor_no_simd(u8z, u8z, (uint8_t *) H[lo], 16); + + rem = (unsigned char) u64z[1] & 0xf; + u64z[1] = (u64z[0] << 60) | (u64z[1] >> 4); + u64z[0] = (u64z[0] >> 4); + u64z[0] ^= (uint64_t) last4[rem] << 48; + mbedtls_xor_no_simd(u8z, u8z, (uint8_t *) H[hi], 16); } -#endif - - lo = x[15] & 0xf; - - zh = ctx->HH[lo]; - zl = ctx->HL[lo]; - for (i = 15; i >= 0; i--) { - lo = x[i] & 0xf; - hi = (x[i] >> 4) & 0xf; + MBEDTLS_PUT_UINT64_BE(u64z[0], output, 0); + MBEDTLS_PUT_UINT64_BE(u64z[1], output, 8); +} +#endif - if (i != 15) { - rem = (unsigned char) zl & 0xf; - zl = (zh << 60) | (zl >> 4); - zh = (zh >> 4); - zh ^= (uint64_t) last4[rem] << 48; - zh ^= ctx->HH[lo]; - zl ^= ctx->HL[lo]; +/* + * Sets output to x times H using the precomputed tables. + * x and output are seen as elements of GF(2^128) as in [MGV]. + */ +static void gcm_mult(mbedtls_gcm_context *ctx, const unsigned char x[16], + unsigned char output[16]) +{ + switch (ctx->acceleration) { +#if defined(MBEDTLS_AESNI_HAVE_CODE) + case MBEDTLS_GCM_ACC_AESNI: + mbedtls_aesni_gcm_mult(output, x, (uint8_t *) ctx->H[MBEDTLS_GCM_HTABLE_SIZE/2]); + break; +#endif - } +#if defined(MBEDTLS_AESCE_HAVE_CODE) + case MBEDTLS_GCM_ACC_AESCE: + mbedtls_aesce_gcm_mult(output, x, (uint8_t *) ctx->H[MBEDTLS_GCM_HTABLE_SIZE/2]); + break; +#endif - rem = (unsigned char) zl & 0xf; - zl = (zh << 60) | (zl >> 4); - zh = (zh >> 4); - zh ^= (uint64_t) last4[rem] << 48; - zh ^= ctx->HH[hi]; - zl ^= ctx->HL[hi]; +#if defined(MBEDTLS_GCM_LARGE_TABLE) + case MBEDTLS_GCM_ACC_LARGETABLE: + gcm_mult_largetable(output, x, ctx->H); + break; +#else + case MBEDTLS_GCM_ACC_SMALLTABLE: + gcm_mult_smalltable(output, x, ctx->H); + break; +#endif } - MBEDTLS_PUT_UINT32_BE(zh >> 32, output, 0); - MBEDTLS_PUT_UINT32_BE(zh, output, 4); - MBEDTLS_PUT_UINT32_BE(zl >> 32, output, 8); - MBEDTLS_PUT_UINT32_BE(zl, output, 12); + return; } int mbedtls_gcm_starts(mbedtls_gcm_context *ctx, @@ -271,8 +388,11 @@ int mbedtls_gcm_starts(mbedtls_gcm_context *ctx, int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char work_buf[16]; const unsigned char *p; - size_t use_len, olen = 0; + size_t use_len; uint64_t iv_bits; +#if !defined(MBEDTLS_BLOCK_CIPHER_C) + size_t olen = 0; +#endif /* IV is limited to 2^64 bits, so 2^61 bytes */ /* IV is not allowed to be zero length */ @@ -299,8 +419,17 @@ int mbedtls_gcm_starts(mbedtls_gcm_context *ctx, while (iv_len > 0) { use_len = (iv_len < 16) ? iv_len : 16; +#if defined(MBEDTLS_COMPILER_IS_GCC) && (MBEDTLS_GCC_VERSION >= 70110) +#pragma GCC diagnostic push +#pragma GCC diagnostic warning "-Wstringop-overflow=0" +#endif + mbedtls_xor(ctx->y, ctx->y, p, use_len); +#if defined(MBEDTLS_COMPILER_IS_GCC) && (MBEDTLS_GCC_VERSION >= 70110) +#pragma GCC diagnostic pop +#endif + gcm_mult(ctx, ctx->y, ctx->y); iv_len -= use_len; @@ -312,8 +441,13 @@ int mbedtls_gcm_starts(mbedtls_gcm_context *ctx, gcm_mult(ctx, ctx->y, ctx->y); } - if ((ret = mbedtls_cipher_update(&ctx->cipher_ctx, ctx->y, 16, - ctx->base_ectr, &olen)) != 0) { + +#if defined(MBEDTLS_BLOCK_CIPHER_C) + ret = mbedtls_block_cipher_encrypt(&ctx->block_cipher_ctx, ctx->y, ctx->base_ectr); +#else + ret = mbedtls_cipher_update(&ctx->cipher_ctx, ctx->y, 16, ctx->base_ectr, &olen); +#endif + if (ret != 0) { return ret; } @@ -342,9 +476,17 @@ int mbedtls_gcm_update_ad(mbedtls_gcm_context *ctx, { const unsigned char *p; size_t use_len, offset; + uint64_t new_add_len; - /* IV is limited to 2^64 bits, so 2^61 bytes */ - if ((uint64_t) add_len >> 61 != 0) { + /* AD is limited to 2^64 bits, ie 2^61 bytes + * Also check for possible overflow */ +#if SIZE_MAX > 0xFFFFFFFFFFFFFFFFULL + if (add_len > 0xFFFFFFFFFFFFFFFFULL) { + return MBEDTLS_ERR_GCM_BAD_INPUT; + } +#endif + new_add_len = ctx->add_len + (uint64_t) add_len; + if (new_add_len < ctx->add_len || new_add_len >> 61 != 0) { return MBEDTLS_ERR_GCM_BAD_INPUT; } @@ -389,12 +531,9 @@ int mbedtls_gcm_update_ad(mbedtls_gcm_context *ctx, /* Increment the counter. */ static void gcm_incr(unsigned char y[16]) { - size_t i; - for (i = 16; i > 12; i--) { - if (++y[i - 1] != 0) { - break; - } - } + uint32_t x = MBEDTLS_GET_UINT32_BE(y, 12); + x++; + MBEDTLS_PUT_UINT32_BE(x, y, 12); } /* Calculate and apply the encryption mask. Process use_len bytes of data, @@ -405,11 +544,15 @@ static int gcm_mask(mbedtls_gcm_context *ctx, const unsigned char *input, unsigned char *output) { - size_t olen = 0; int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - if ((ret = mbedtls_cipher_update(&ctx->cipher_ctx, ctx->y, 16, ectr, - &olen)) != 0) { +#if defined(MBEDTLS_BLOCK_CIPHER_C) + ret = mbedtls_block_cipher_encrypt(&ctx->block_cipher_ctx, ctx->y, ectr); +#else + size_t olen = 0; + ret = mbedtls_cipher_update(&ctx->cipher_ctx, ctx->y, 16, ectr, &olen); +#endif + if (ret != 0) { mbedtls_platform_zeroize(ectr, 16); return ret; } @@ -526,6 +669,9 @@ int mbedtls_gcm_finish(mbedtls_gcm_context *ctx, (void) output_size; *output_length = 0; + /* Total length is restricted to 2^39 - 256 bits, ie 2^36 - 2^5 bytes + * and AD length is restricted to 2^64 bits, ie 2^61 bytes so neither of + * the two multiplications would overflow. */ orig_len = ctx->len * 8; orig_add_len = ctx->add_len * 8; @@ -606,13 +752,17 @@ void mbedtls_gcm_free(mbedtls_gcm_context *ctx) if (ctx == NULL) { return; } +#if defined(MBEDTLS_BLOCK_CIPHER_C) + mbedtls_block_cipher_free(&ctx->block_cipher_ctx); +#else mbedtls_cipher_free(&ctx->cipher_ctx); +#endif mbedtls_platform_zeroize(ctx, sizeof(mbedtls_gcm_context)); } -#if defined(MBEDTLS_SELF_TEST) && defined(MBEDTLS_AES_C) +#if defined(MBEDTLS_SELF_TEST) && defined(MBEDTLS_CCM_GCM_CAN_AES) /* * AES-GCM test vectors from: * diff --git a/ra/fsp/src/rm_psa_crypto/gcm_alt_process.c b/ra/fsp/src/rm_psa_crypto/gcm_alt_process.c index f42b38f5f..8a022e260 100644 --- a/ra/fsp/src/rm_psa_crypto/gcm_alt_process.c +++ b/ra/fsp/src/rm_psa_crypto/gcm_alt_process.c @@ -34,100 +34,8 @@ #include "aes_alt.h" #include "platform_alt.h" -/* Parameter validation macros */ - #define GCM_VALIDATE_RET(cond) \ - MBEDTLS_INTERNAL_VALIDATE_RET(cond, MBEDTLS_ERR_GCM_BAD_INPUT) - #define GCM_VALIDATE(cond) \ - MBEDTLS_INTERNAL_VALIDATE(cond) - #define SCE9_AES_GCM_KEY_TYPE_GENERAL (0) -fsp_err_t HW_SCE_Aes192GcmEncryptInitSubGeneral(uint32_t * InData_KeyType, - uint32_t * InData_DataType, - uint32_t * InData_Cmd, - uint32_t * InData_KeyIndex, - uint32_t * InData_IV, - uint32_t * InData_SeqNum); - -fsp_err_t HW_SCE_Aes192GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, - uint32_t * InData_DataType, - uint32_t * InData_Cmd, - uint32_t * InData_KeyIndex, - uint32_t * InData_IV, - uint32_t * InData_SeqNum) -{ - FSP_PARAMETER_NOT_USED(InData_KeyType); - FSP_PARAMETER_NOT_USED(InData_DataType); - FSP_PARAMETER_NOT_USED(InData_Cmd); - FSP_PARAMETER_NOT_USED(InData_SeqNum); - - return HW_SCE_Aes192GcmEncryptInitSub(InData_KeyIndex, InData_IV); -} - -fsp_err_t HW_SCE_Aes192GcmDecryptInitSubGeneral(uint32_t * InData_KeyType, - uint32_t * InData_DataType, - uint32_t * InData_Cmd, - uint32_t * InData_KeyIndex, - uint32_t * InData_IV, - uint32_t * InData_SeqNum); - -fsp_err_t HW_SCE_Aes192GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, - uint32_t * InData_DataType, - uint32_t * InData_Cmd, - uint32_t * InData_KeyIndex, - uint32_t * InData_IV, - uint32_t * InData_SeqNum) -{ - FSP_PARAMETER_NOT_USED(InData_KeyType); - FSP_PARAMETER_NOT_USED(InData_DataType); - FSP_PARAMETER_NOT_USED(InData_Cmd); - FSP_PARAMETER_NOT_USED(InData_SeqNum); - - return HW_SCE_Aes192GcmDecryptInitSub(InData_KeyIndex, InData_IV); -} - -fsp_err_t HW_SCE_Aes256GcmEncryptInitSubGeneral(uint32_t * InData_KeyType, - uint32_t * InData_DataType, - uint32_t * InData_Cmd, - uint32_t * InData_KeyIndex, - uint32_t * InData_IV, - uint32_t * InData_SeqNum); - -fsp_err_t HW_SCE_Aes256GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, - uint32_t * InData_DataType, - uint32_t * InData_Cmd, - uint32_t * InData_KeyIndex, - uint32_t * InData_IV, - uint32_t * InData_SeqNum) -{ - FSP_PARAMETER_NOT_USED(InData_DataType); - FSP_PARAMETER_NOT_USED(InData_Cmd); - FSP_PARAMETER_NOT_USED(InData_SeqNum); - - return HW_SCE_Aes256GcmEncryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); -} - -fsp_err_t HW_SCE_Aes256GcmDecryptInitSubGeneral(uint32_t * InData_KeyType, - uint32_t * InData_DataType, - uint32_t * InData_Cmd, - uint32_t * InData_KeyIndex, - uint32_t * InData_IV, - uint32_t * InData_SeqNum); - -fsp_err_t HW_SCE_Aes256GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, - uint32_t * InData_DataType, - uint32_t * InData_Cmd, - uint32_t * InData_KeyIndex, - uint32_t * InData_IV, - uint32_t * InData_SeqNum) -{ - FSP_PARAMETER_NOT_USED(InData_DataType); - FSP_PARAMETER_NOT_USED(InData_Cmd); - FSP_PARAMETER_NOT_USED(InData_SeqNum); - - return HW_SCE_Aes256GcmDecryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); -} - /* Prepare GCM IV for encryption/decryption * Ref: https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-38d.pdf * */ @@ -168,7 +76,7 @@ static fsp_err_t prepare_gcm_iv (uint8_t * ivec, /* Encrypt 4 words (128 bit) zeros with the AES key. The generated cipher is the hash subkey used by GHASH HW API. */ if (key_index_word_size == 0U) { - err = HW_SCE_Aes128EncryptDecryptInitSub(&indata_key_type, &indata_cmd, key_index, dummy_iv); + err = HW_SCE_Aes128EncryptDecryptInitSubAdaptor(&indata_key_type, &indata_cmd, key_index, NULL, dummy_iv); if (err == FSP_SUCCESS) { @@ -194,7 +102,7 @@ static fsp_err_t prepare_gcm_iv (uint8_t * ivec, } else if (key_index_word_size == 2U) { - err = HW_SCE_Aes256EncryptDecryptInitSub(&indata_key_type, &indata_cmd, key_index, dummy_iv); + err = HW_SCE_Aes256EncryptDecryptInitSubAdaptor(&indata_key_type, &indata_cmd, key_index, NULL, dummy_iv); if (err == FSP_SUCCESS) { @@ -364,13 +272,7 @@ int sce_gcm_crypt_and_tag (mbedtls_gcm_context * ctx, size_t tag_len, unsigned char * tag) { - GCM_VALIDATE_RET(ctx != NULL); - GCM_VALIDATE_RET(iv != NULL); - GCM_VALIDATE_RET(aad_len == 0 || aad != NULL); - GCM_VALIDATE_RET(length == 0 || input != NULL); - GCM_VALIDATE_RET(length == 0 || output != NULL); - GCM_VALIDATE_RET(tag != NULL); - uint32_t key_len_idx = (uint32_t)RM_PSA_CRYPTO_AES_LOOKUP_INDEX(ctx->cipher_ctx.key_bitlen); + uint32_t key_len_idx = (uint32_t) RM_PSA_CRYPTO_AES_LOOKUP_INDEX(ctx->cipher_ctx.key_bitlen); mbedtls_aes_context * aes_ctx = (mbedtls_aes_context *) ctx->cipher_ctx.cipher_ctx; fsp_err_t err = FSP_SUCCESS; uint32_t aad_bit_size[2] = {0}; @@ -457,11 +359,12 @@ int sce_gcm_crypt_and_tag (mbedtls_gcm_context * ctx, tag_bit_size, (uint32_t *) &output[input_length]); } } + if (FSP_SUCCESS != err) { return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; } - else + else { return 0U; } diff --git a/ra/fsp/src/rm_psa_crypto/inc/ecp_alt.h b/ra/fsp/src/rm_psa_crypto/inc/ecp_alt.h index cf85893f2..d3deddf7b 100644 --- a/ra/fsp/src/rm_psa_crypto/inc/ecp_alt.h +++ b/ra/fsp/src/rm_psa_crypto/inc/ecp_alt.h @@ -39,7 +39,7 @@ extern "C" { // Alternate implementation // - #define RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(bits) ((((bits >> 7) & 1) | (bits & 8) >> 2)) + #define RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(bits) (((((bits) >> 7) & 1) | ((bits) & 8) >> 2)) #define RM_PSA_CRYPTO_ECC_KEY_PLAINTEXT (0U) #define RM_PSA_CRYPTO_ECC_KEY_WRAPPED (1U) #define RM_PSA_CRYPTO_LARGEST_WRAPPED_ECC_PRIVATE_KEY_WORDS (25U) /* Corresponding to ECC P-521 curves on RSIP */ diff --git a/ra/fsp/src/rm_psa_crypto/inc/gcm_alt.h b/ra/fsp/src/rm_psa_crypto/inc/gcm_alt.h index 85400f2b9..0f812b056 100644 --- a/ra/fsp/src/rm_psa_crypto/inc/gcm_alt.h +++ b/ra/fsp/src/rm_psa_crypto/inc/gcm_alt.h @@ -48,22 +48,32 @@ extern "C" { #endif +#if defined(MBEDTLS_GCM_LARGE_TABLE) +#define MBEDTLS_GCM_HTABLE_SIZE 256 +#else +#define MBEDTLS_GCM_HTABLE_SIZE 16 +#endif + /** * \brief The GCM context structure. */ typedef struct mbedtls_gcm_context { - mbedtls_cipher_context_t cipher_ctx; /*!< The cipher context used. */ - uint64_t HL[16]; /*!< Precalculated HTable low. */ - uint64_t HH[16]; /*!< Precalculated HTable high. */ - uint64_t len; /*!< The total length of the encrypted data. */ - uint64_t add_len; /*!< The total length of the additional data. */ - unsigned char base_ectr[16]; /*!< The first ECTR for tag. */ - unsigned char y[16]; /*!< The Y working value. */ - unsigned char buf[16]; /*!< The buf working value. */ - int mode; /*!< The operation to perform: - * MBEDTLS_GCM_ENCRYPT or - * MBEDTLS_GCM_DECRYPT. */ +#if defined(MBEDTLS_BLOCK_CIPHER_C) + mbedtls_block_cipher_context_t MBEDTLS_PRIVATE(block_cipher_ctx); /*!< The cipher context used. */ +#else + mbedtls_cipher_context_t MBEDTLS_PRIVATE(cipher_ctx); /*!< The cipher context used. */ +#endif + uint64_t MBEDTLS_PRIVATE(H)[MBEDTLS_GCM_HTABLE_SIZE][2]; /*!< Precalculated HTable. */ + uint64_t MBEDTLS_PRIVATE(len); /*!< The total length of the encrypted data. */ + uint64_t MBEDTLS_PRIVATE(add_len); /*!< The total length of the additional data. */ + unsigned char MBEDTLS_PRIVATE(base_ectr)[16]; /*!< The first ECTR for tag. */ + unsigned char MBEDTLS_PRIVATE(y)[16]; /*!< The Y working value. */ + unsigned char MBEDTLS_PRIVATE(buf)[16]; /*!< The buf working value. */ + unsigned char MBEDTLS_PRIVATE(mode); /*!< The operation to perform: + MBEDTLS_GCM_ENCRYPT or + MBEDTLS_GCM_DECRYPT. */ + unsigned char MBEDTLS_PRIVATE(acceleration); /*!< The acceleration to use. */ bool vendor_flag; } mbedtls_gcm_context; diff --git a/ra/fsp/src/rm_psa_crypto/rsa_alt.c b/ra/fsp/src/rm_psa_crypto/rsa_alt.c index 6a0c4da29..2ffb92d5a 100644 --- a/ra/fsp/src/rm_psa_crypto/rsa_alt.c +++ b/ra/fsp/src/rm_psa_crypto/rsa_alt.c @@ -2,21 +2,7 @@ * The RSA public-key cryptosystem * * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * This file is part of mbed TLS (https://tls.mbed.org) + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later */ /* @@ -43,8 +29,11 @@ #if defined(MBEDTLS_RSA_C) #include "mbedtls/rsa.h" + #include "bignum_core.h" #include "rsa_alt_helpers.h" + #include "rsa_internal.h" #include "mbedtls/oid.h" + #include "mbedtls/asn1write.h" #include "mbedtls/platform_util.h" #include "mbedtls/error.h" #include "constant_time_internal.h" @@ -59,7 +48,372 @@ #include "mbedtls/platform.h" - +#if defined(MBEDTLS_RSA_C) && defined(MBEDTLS_RSA_ALT) +/* + * Wrapper around mbedtls_asn1_get_mpi() that rejects zero. + * + * The value zero is: + * - never a valid value for an RSA parameter + * - interpreted as "omitted, please reconstruct" by mbedtls_rsa_complete(). + * + * Since values can't be omitted in PKCS#1, passing a zero value to + * rsa_complete() would be incorrect, so reject zero values early. + */ +static int asn1_get_nonzero_mpi(unsigned char **p, + const unsigned char *end, + mbedtls_mpi *X) +{ + int ret; + + ret = mbedtls_asn1_get_mpi(p, end, X); + if (ret != 0) { + return ret; + } + + if (mbedtls_mpi_cmp_int(X, 0) == 0) { + return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; + } + + return 0; +} + +int mbedtls_rsa_parse_key(mbedtls_rsa_context *rsa, const unsigned char *key, size_t keylen) +{ + int ret, version; + size_t len; + unsigned char *p, *end; + + mbedtls_mpi T; + mbedtls_mpi_init(&T); + + p = (unsigned char *) key; + end = p + keylen; + + /* + * This function parses the RSAPrivateKey (PKCS#1) + * + * RSAPrivateKey ::= SEQUENCE { + * version Version, + * modulus INTEGER, -- n + * publicExponent INTEGER, -- e + * privateExponent INTEGER, -- d + * prime1 INTEGER, -- p + * prime2 INTEGER, -- q + * exponent1 INTEGER, -- d mod (p-1) + * exponent2 INTEGER, -- d mod (q-1) + * coefficient INTEGER, -- (inverse of q) mod p + * otherPrimeInfos OtherPrimeInfos OPTIONAL + * } + */ + if ((ret = mbedtls_asn1_get_tag(&p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE)) != 0) { + return ret; + } + + if (end != p + len) { + return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; + } + + if ((ret = mbedtls_asn1_get_int(&p, end, &version)) != 0) { + return ret; + } + + if (version != 0) { + return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; + } + + /* Import N */ + if ((ret = asn1_get_nonzero_mpi(&p, end, &T)) != 0 || + (ret = mbedtls_rsa_import(rsa, &T, NULL, NULL, + NULL, NULL)) != 0) { + goto cleanup; + } + + /* Import E */ + if ((ret = asn1_get_nonzero_mpi(&p, end, &T)) != 0 || + (ret = mbedtls_rsa_import(rsa, NULL, NULL, NULL, + NULL, &T)) != 0) { + goto cleanup; + } + + /* Import D */ + if ((ret = asn1_get_nonzero_mpi(&p, end, &T)) != 0 || + (ret = mbedtls_rsa_import(rsa, NULL, NULL, NULL, + &T, NULL)) != 0) { + goto cleanup; + } + + /* Import P */ + if ((ret = asn1_get_nonzero_mpi(&p, end, &T)) != 0 || + (ret = mbedtls_rsa_import(rsa, NULL, &T, NULL, + NULL, NULL)) != 0) { + goto cleanup; + } + + /* Import Q */ + if ((ret = asn1_get_nonzero_mpi(&p, end, &T)) != 0 || + (ret = mbedtls_rsa_import(rsa, NULL, NULL, &T, + NULL, NULL)) != 0) { + goto cleanup; + } + +#if !defined(MBEDTLS_RSA_NO_CRT) && !defined(MBEDTLS_RSA_ALT) + /* + * The RSA CRT parameters DP, DQ and QP are nominally redundant, in + * that they can be easily recomputed from D, P and Q. However by + * parsing them from the PKCS1 structure it is possible to avoid + * recalculating them which both reduces the overhead of loading + * RSA private keys into memory and also avoids side channels which + * can arise when computing those values, since all of D, P, and Q + * are secret. See https://eprint.iacr.org/2020/055 for a + * description of one such attack. + */ + + /* Import DP */ + if ((ret = asn1_get_nonzero_mpi(&p, end, &T)) != 0 || + (ret = mbedtls_mpi_copy(&rsa->DP, &T)) != 0) { + goto cleanup; + } + + /* Import DQ */ + if ((ret = asn1_get_nonzero_mpi(&p, end, &T)) != 0 || + (ret = mbedtls_mpi_copy(&rsa->DQ, &T)) != 0) { + goto cleanup; + } + + /* Import QP */ + if ((ret = asn1_get_nonzero_mpi(&p, end, &T)) != 0 || + (ret = mbedtls_mpi_copy(&rsa->QP, &T)) != 0) { + goto cleanup; + } + +#else + /* Verify existence of the CRT params */ + if ((ret = asn1_get_nonzero_mpi(&p, end, &T)) != 0 || + (ret = asn1_get_nonzero_mpi(&p, end, &T)) != 0 || + (ret = asn1_get_nonzero_mpi(&p, end, &T)) != 0) { + goto cleanup; + } +#endif + + /* rsa_complete() doesn't complete anything with the default + * implementation but is still called: + * - for the benefit of alternative implementation that may want to + * pre-compute stuff beyond what's provided (eg Montgomery factors) + * - as is also sanity-checks the key + * + * Furthermore, we also check the public part for consistency with + * mbedtls_pk_parse_pubkey(), as it includes size minima for example. + */ + if ((ret = mbedtls_rsa_complete(rsa)) != 0 || + (ret = mbedtls_rsa_check_pubkey(rsa)) != 0) { + goto cleanup; + } + + if (p != end) { + ret = MBEDTLS_ERR_ASN1_LENGTH_MISMATCH; + } + +cleanup: + + mbedtls_mpi_free(&T); + + if (ret != 0) { + mbedtls_rsa_free(rsa); + } + + return ret; +} + +int mbedtls_rsa_parse_pubkey(mbedtls_rsa_context *rsa, const unsigned char *key, size_t keylen) +{ + unsigned char *p = (unsigned char *) key; + unsigned char *end = (unsigned char *) (key + keylen); + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t len; + + /* + * RSAPublicKey ::= SEQUENCE { + * modulus INTEGER, -- n + * publicExponent INTEGER -- e + * } + */ + + if ((ret = mbedtls_asn1_get_tag(&p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE)) != 0) { + return ret; + } + + if (end != p + len) { + return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; + } + + /* Import N */ + if ((ret = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_INTEGER)) != 0) { + return ret; + } + + if ((ret = mbedtls_rsa_import_raw(rsa, p, len, NULL, 0, NULL, 0, + NULL, 0, NULL, 0)) != 0) { + return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; + } + + p += len; + + /* Import E */ + if ((ret = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_INTEGER)) != 0) { + return ret; + } + + if ((ret = mbedtls_rsa_import_raw(rsa, NULL, 0, NULL, 0, NULL, 0, + NULL, 0, p, len)) != 0) { + return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; + } + + p += len; + + if (mbedtls_rsa_complete(rsa) != 0 || + mbedtls_rsa_check_pubkey(rsa) != 0) { + return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; + } + + if (p != end) { + return MBEDTLS_ERR_ASN1_LENGTH_MISMATCH; + } + + return 0; +} + +int mbedtls_rsa_write_key(const mbedtls_rsa_context *rsa, unsigned char *start, + unsigned char **p) +{ + size_t len = 0; + int ret; + + mbedtls_mpi T; /* Temporary holding the exported parameters */ + + /* + * Export the parameters one after another to avoid simultaneous copies. + */ + + mbedtls_mpi_init(&T); + + /* Export QP */ + if ((ret = mbedtls_rsa_export_crt(rsa, NULL, NULL, &T)) != 0 || + (ret = mbedtls_asn1_write_mpi(p, start, &T)) < 0) { + goto end_of_export; + } + len += ret; + + /* Export DQ */ + if ((ret = mbedtls_rsa_export_crt(rsa, NULL, &T, NULL)) != 0 || + (ret = mbedtls_asn1_write_mpi(p, start, &T)) < 0) { + goto end_of_export; + } + len += ret; + + /* Export DP */ + if ((ret = mbedtls_rsa_export_crt(rsa, &T, NULL, NULL)) != 0 || + (ret = mbedtls_asn1_write_mpi(p, start, &T)) < 0) { + goto end_of_export; + } + len += ret; + + /* Export Q */ + if ((ret = mbedtls_rsa_export(rsa, NULL, NULL, &T, NULL, NULL)) != 0 || + (ret = mbedtls_asn1_write_mpi(p, start, &T)) < 0) { + goto end_of_export; + } + len += ret; + + /* Export P */ + if ((ret = mbedtls_rsa_export(rsa, NULL, &T, NULL, NULL, NULL)) != 0 || + (ret = mbedtls_asn1_write_mpi(p, start, &T)) < 0) { + goto end_of_export; + } + len += ret; + + /* Export D */ + if ((ret = mbedtls_rsa_export(rsa, NULL, NULL, NULL, &T, NULL)) != 0 || + (ret = mbedtls_asn1_write_mpi(p, start, &T)) < 0) { + goto end_of_export; + } + len += ret; + + /* Export E */ + if ((ret = mbedtls_rsa_export(rsa, NULL, NULL, NULL, NULL, &T)) != 0 || + (ret = mbedtls_asn1_write_mpi(p, start, &T)) < 0) { + goto end_of_export; + } + len += ret; + + /* Export N */ + if ((ret = mbedtls_rsa_export(rsa, &T, NULL, NULL, NULL, NULL)) != 0 || + (ret = mbedtls_asn1_write_mpi(p, start, &T)) < 0) { + goto end_of_export; + } + len += ret; + +end_of_export: + + mbedtls_mpi_free(&T); + if (ret < 0) { + return ret; + } + + MBEDTLS_ASN1_CHK_ADD(len, mbedtls_asn1_write_int(p, start, 0)); + MBEDTLS_ASN1_CHK_ADD(len, mbedtls_asn1_write_len(p, start, len)); + MBEDTLS_ASN1_CHK_ADD(len, mbedtls_asn1_write_tag(p, start, + MBEDTLS_ASN1_CONSTRUCTED | + MBEDTLS_ASN1_SEQUENCE)); + + return (int) len; +} + +/* + * RSAPublicKey ::= SEQUENCE { + * modulus INTEGER, -- n + * publicExponent INTEGER -- e + * } + */ +int mbedtls_rsa_write_pubkey(const mbedtls_rsa_context *rsa, unsigned char *start, + unsigned char **p) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t len = 0; + mbedtls_mpi T; + + mbedtls_mpi_init(&T); + + /* Export E */ + if ((ret = mbedtls_rsa_export(rsa, NULL, NULL, NULL, NULL, &T)) != 0 || + (ret = mbedtls_asn1_write_mpi(p, start, &T)) < 0) { + goto end_of_export; + } + len += ret; + + /* Export N */ + if ((ret = mbedtls_rsa_export(rsa, &T, NULL, NULL, NULL, NULL)) != 0 || + (ret = mbedtls_asn1_write_mpi(p, start, &T)) < 0) { + goto end_of_export; + } + len += ret; + +end_of_export: + + mbedtls_mpi_free(&T); + if (ret < 0) { + return ret; + } + + MBEDTLS_ASN1_CHK_ADD(len, mbedtls_asn1_write_len(p, start, len)); + MBEDTLS_ASN1_CHK_ADD(len, mbedtls_asn1_write_tag(p, start, MBEDTLS_ASN1_CONSTRUCTED | + MBEDTLS_ASN1_SEQUENCE)); + + return (int) len; +} +#endif /* MBEDTLS_RSA_C && MBEDTLS_RSA_ALT */ + #if defined(MBEDTLS_PKCS1_V15) && defined(MBEDTLS_RSA_C) /** This function performs the unpadding part of a PKCS#1 v1.5 decryption @@ -681,6 +1035,14 @@ int mbedtls_rsa_get_md_alg(const mbedtls_rsa_context *ctx) return ctx->hash_id; } +/* + * Get length in bits of RSA modulus + */ +size_t mbedtls_rsa_get_bitlen(const mbedtls_rsa_context *ctx) +{ + return mbedtls_mpi_bitlen(&ctx->N); +} + /* * Get length in bytes of RSA modulus */ @@ -1001,6 +1363,45 @@ static int rsa_prepare_blinding(mbedtls_rsa_context *ctx, return ret; } +/* + * Unblind + * T = T * Vf mod N + */ +static int rsa_unblind(mbedtls_mpi *T, mbedtls_mpi *Vf, const mbedtls_mpi *N) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + const mbedtls_mpi_uint mm = mbedtls_mpi_core_montmul_init(N->p); + const size_t nlimbs = N->n; + const size_t tlimbs = mbedtls_mpi_core_montmul_working_limbs(nlimbs); + mbedtls_mpi RR, M_T; + + mbedtls_mpi_init(&RR); + mbedtls_mpi_init(&M_T); + + MBEDTLS_MPI_CHK(mbedtls_mpi_core_get_mont_r2_unsafe(&RR, N)); + MBEDTLS_MPI_CHK(mbedtls_mpi_grow(&M_T, tlimbs)); + + MBEDTLS_MPI_CHK(mbedtls_mpi_grow(T, nlimbs)); + MBEDTLS_MPI_CHK(mbedtls_mpi_grow(Vf, nlimbs)); + + /* T = T * Vf mod N + * Reminder: montmul(A, B, N) = A * B * R^-1 mod N + * Usually both operands are multiplied by R mod N beforehand (by calling + * `to_mont_rep()` on them), yielding a result that's also * R mod N (aka + * "in the Montgomery domain"). Here we only multiply one operand by R mod + * N, so the result is directly what we want - no need to call + * `from_mont_rep()` on it. */ + mbedtls_mpi_core_to_mont_rep(T->p, T->p, N->p, nlimbs, mm, RR.p, M_T.p); + mbedtls_mpi_core_montmul(T->p, T->p, Vf->p, nlimbs, N->p, nlimbs, mm, M_T.p); + +cleanup: + + mbedtls_mpi_free(&RR); + mbedtls_mpi_free(&M_T); + + return ret; +} + /* * Exponent blinding supposed to prevent side-channel attacks using multiple * traces of measurements to recover the RSA key. The more collisions are there, @@ -1049,22 +1450,15 @@ int mbedtls_rsa_private(mbedtls_rsa_context *ctx, * the mod p resp. mod q computation (if used). */ mbedtls_mpi DP_blind, DQ_blind; - /* Pointers to actual exponents to be used - either the unblinded - * or the blinded ones, depending on the presence of a PRNG. */ - mbedtls_mpi *DP = &ctx->DP; - mbedtls_mpi *DQ = &ctx->DQ; #else /* Temporary holding the blinded exponent (if used). */ mbedtls_mpi D_blind; - /* Pointer to actual exponent to be used - either the unblinded - * or the blinded one, depending on the presence of a PRNG. */ - mbedtls_mpi *D = &ctx->D; #endif /* MBEDTLS_RSA_NO_CRT */ /* Temporaries holding the initial input and the double * checked result; should be the same in the end. */ - mbedtls_mpi I, C; + mbedtls_mpi input_blinded, check_result_blinded; if (f_rng == NULL) { return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; @@ -1099,8 +1493,8 @@ int mbedtls_rsa_private(mbedtls_rsa_context *ctx, mbedtls_mpi_init(&TP); mbedtls_mpi_init(&TQ); #endif - mbedtls_mpi_init(&I); - mbedtls_mpi_init(&C); + mbedtls_mpi_init(&input_blinded); + mbedtls_mpi_init(&check_result_blinded); /* End of MPI initialization */ @@ -1110,7 +1504,6 @@ int mbedtls_rsa_private(mbedtls_rsa_context *ctx, goto cleanup; } - MBEDTLS_MPI_CHK(mbedtls_mpi_copy(&I, &T)); /* * Blinding @@ -1120,6 +1513,7 @@ int mbedtls_rsa_private(mbedtls_rsa_context *ctx, MBEDTLS_MPI_CHK(mbedtls_mpi_mul_mpi(&T, &T, &ctx->Vi)); MBEDTLS_MPI_CHK(mbedtls_mpi_mod_mpi(&T, &T, &ctx->N)); + MBEDTLS_MPI_CHK(mbedtls_mpi_copy(&input_blinded, &T)); /* * Exponent blinding */ @@ -1136,7 +1530,6 @@ int mbedtls_rsa_private(mbedtls_rsa_context *ctx, MBEDTLS_MPI_CHK(mbedtls_mpi_mul_mpi(&D_blind, &D_blind, &R)); MBEDTLS_MPI_CHK(mbedtls_mpi_add_mpi(&D_blind, &D_blind, &ctx->D)); - D = &D_blind; #else /* * DP_blind = ( P - 1 ) * R + DP @@ -1147,7 +1540,6 @@ int mbedtls_rsa_private(mbedtls_rsa_context *ctx, MBEDTLS_MPI_CHK(mbedtls_mpi_add_mpi(&DP_blind, &DP_blind, &ctx->DP)); - DP = &DP_blind; /* * DQ_blind = ( Q - 1 ) * R + DQ @@ -1158,11 +1550,10 @@ int mbedtls_rsa_private(mbedtls_rsa_context *ctx, MBEDTLS_MPI_CHK(mbedtls_mpi_add_mpi(&DQ_blind, &DQ_blind, &ctx->DQ)); - DQ = &DQ_blind; #endif /* MBEDTLS_RSA_NO_CRT */ #if defined(MBEDTLS_RSA_NO_CRT) - MBEDTLS_MPI_CHK(mbedtls_mpi_exp_mod(&T, &T, D, &ctx->N, &ctx->RN)); + MBEDTLS_MPI_CHK(mbedtls_mpi_exp_mod(&T, &T, &D_blind, &ctx->N, &ctx->RN)); #else /* * Faster decryption using the CRT @@ -1171,8 +1562,8 @@ int mbedtls_rsa_private(mbedtls_rsa_context *ctx, * TQ = input ^ dQ mod Q */ - MBEDTLS_MPI_CHK(mbedtls_mpi_exp_mod(&TP, &T, DP, &ctx->P, &ctx->RP)); - MBEDTLS_MPI_CHK(mbedtls_mpi_exp_mod(&TQ, &T, DQ, &ctx->Q, &ctx->RQ)); + MBEDTLS_MPI_CHK(mbedtls_mpi_exp_mod(&TP, &T, &DP_blind, &ctx->P, &ctx->RP)); + MBEDTLS_MPI_CHK(mbedtls_mpi_exp_mod(&TQ, &T, &DQ_blind, &ctx->Q, &ctx->RQ)); /* * T = (TP - TQ) * (Q^-1 mod P) mod P @@ -1188,21 +1579,20 @@ int mbedtls_rsa_private(mbedtls_rsa_context *ctx, MBEDTLS_MPI_CHK(mbedtls_mpi_add_mpi(&T, &TQ, &TP)); #endif /* MBEDTLS_RSA_NO_CRT */ - /* - * Unblind - * T = T * Vf mod N - */ - MBEDTLS_MPI_CHK(mbedtls_mpi_mul_mpi(&T, &T, &ctx->Vf)); - MBEDTLS_MPI_CHK(mbedtls_mpi_mod_mpi(&T, &T, &ctx->N)); - /* Verify the result to prevent glitching attacks. */ - MBEDTLS_MPI_CHK(mbedtls_mpi_exp_mod(&C, &T, &ctx->E, + MBEDTLS_MPI_CHK(mbedtls_mpi_exp_mod(&check_result_blinded, &T, &ctx->E, &ctx->N, &ctx->RN)); - if (mbedtls_mpi_cmp_mpi(&C, &I) != 0) { + if (mbedtls_mpi_cmp_mpi(&check_result_blinded, &input_blinded) != 0) { ret = MBEDTLS_ERR_RSA_VERIFY_FAILED; goto cleanup; } + /* + * Unblind + * T = T * Vf mod N + */ + MBEDTLS_MPI_CHK(rsa_unblind(&T, &ctx->Vf, &ctx->N)); + olen = ctx->len; MBEDTLS_MPI_CHK(mbedtls_mpi_write_binary(&T, output, olen)); @@ -1230,8 +1620,8 @@ int mbedtls_rsa_private(mbedtls_rsa_context *ctx, mbedtls_mpi_free(&TP); mbedtls_mpi_free(&TQ); #endif - mbedtls_mpi_free(&C); - mbedtls_mpi_free(&I); + mbedtls_mpi_free(&check_result_blinded); + mbedtls_mpi_free(&input_blinded); if (ret != 0 && ret >= -0x007f) { return MBEDTLS_ERROR_ADD(MBEDTLS_ERR_RSA_PRIVATE_FAILED, ret); @@ -1620,7 +2010,7 @@ int mbedtls_rsa_rsaes_oaep_decrypt(mbedtls_rsa_context *ctx, * Check contents, in "constant-time" */ p = buf; - + bad = mbedtls_ct_bool(*p++); /* First byte must be 0 */ p += hlen; /* Skip seed */ @@ -1652,12 +2042,12 @@ int mbedtls_rsa_rsaes_oaep_decrypt(mbedtls_rsa_context *ctx, goto cleanup; } - if (ilen - (p - buf) > output_max_len) { + if (ilen - ((size_t) (p - buf)) > output_max_len) { ret = MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE; goto cleanup; } - *olen = ilen - (p - buf); + *olen = ilen - ((size_t) (p - buf)); if (*olen != 0) { memcpy(output, p, *olen); } @@ -1744,14 +2134,14 @@ int mbedtls_rsa_pkcs1_decrypt(mbedtls_rsa_context *ctx, } #if defined(MBEDTLS_PKCS1_V21) -static int rsa_rsassa_pss_sign(mbedtls_rsa_context *ctx, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng, - mbedtls_md_type_t md_alg, - unsigned int hashlen, - const unsigned char *hash, - int saltlen, - unsigned char *sig) +static int rsa_rsassa_pss_sign_no_mode_check(mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + int saltlen, + unsigned char *sig) { size_t olen; unsigned char *p = sig; @@ -1759,15 +2149,12 @@ static int rsa_rsassa_pss_sign(mbedtls_rsa_context *ctx, size_t slen, min_slen, hlen, offset = 0; int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t msb; + mbedtls_md_type_t hash_id; if ((md_alg != MBEDTLS_MD_NONE || hashlen != 0) && hash == NULL) { return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; } - if (ctx->padding != MBEDTLS_RSA_PKCS_V21) { - return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; - } - if (f_rng == NULL) { return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; } @@ -1786,7 +2173,11 @@ static int rsa_rsassa_pss_sign(mbedtls_rsa_context *ctx, } } - hlen = mbedtls_md_get_size_from_type((mbedtls_md_type_t) ctx->hash_id); + hash_id = (mbedtls_md_type_t) ctx->hash_id; + if (hash_id == MBEDTLS_MD_NONE) { + hash_id = md_alg; + } + hlen = mbedtls_md_get_size_from_type(hash_id); if (hlen == 0) { return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; } @@ -1829,7 +2220,7 @@ static int rsa_rsassa_pss_sign(mbedtls_rsa_context *ctx, p += slen; /* Generate H = Hash( M' ) */ - ret = hash_mprime(hash, hashlen, salt, slen, p, (mbedtls_md_type_t) ctx->hash_id); + ret = hash_mprime(hash, hashlen, salt, slen, p, hash_id); if (ret != 0) { return ret; } @@ -1840,8 +2231,7 @@ static int rsa_rsassa_pss_sign(mbedtls_rsa_context *ctx, } /* maskedDB: Apply dbMask to DB */ - ret = mgf_mask(sig + offset, olen - hlen - 1 - offset, p, hlen, - (mbedtls_md_type_t) ctx->hash_id); + ret = mgf_mask(sig + offset, olen - hlen - 1 - offset, p, hlen, hash_id); if (ret != 0) { return ret; } @@ -1855,6 +2245,37 @@ static int rsa_rsassa_pss_sign(mbedtls_rsa_context *ctx, return mbedtls_rsa_private(ctx, f_rng, p_rng, sig, sig); } +static int rsa_rsassa_pss_sign(mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + int saltlen, + unsigned char *sig) +{ + if (ctx->padding != MBEDTLS_RSA_PKCS_V21) { + return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; + } + if ((ctx->hash_id == MBEDTLS_MD_NONE) && (md_alg == MBEDTLS_MD_NONE)) { + return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; + } + return rsa_rsassa_pss_sign_no_mode_check(ctx, f_rng, p_rng, md_alg, hashlen, hash, saltlen, + sig); +} + +int mbedtls_rsa_rsassa_pss_sign_no_mode_check(mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + unsigned char *sig) +{ + return rsa_rsassa_pss_sign_no_mode_check(ctx, f_rng, p_rng, md_alg, + hashlen, hash, MBEDTLS_RSA_SALT_LEN_ANY, sig); +} + /* * Implementation of the PKCS#1 v2.1 RSASSA-PSS-SIGN function with * the option to pass in the salt length. @@ -2087,7 +2508,7 @@ int mbedtls_rsa_rsassa_pkcs1_v15_sign(mbedtls_rsa_context *ctx, cleanup: mbedtls_zeroize_and_free(sig_try, ctx->len); mbedtls_zeroize_and_free(verif, ctx->len); - + if (ret != 0) { memset(sig, '!', ctx->len); } @@ -2223,7 +2644,7 @@ int mbedtls_rsa_rsassa_pss_verify_ext(mbedtls_rsa_context *ctx, return MBEDTLS_ERR_RSA_INVALID_PADDING; } - observed_salt_len = hash_start - p; + observed_salt_len = (size_t) (hash_start - p); if (expected_salt_len != MBEDTLS_RSA_SALT_LEN_ANY && observed_salt_len != (size_t) expected_salt_len) { @@ -2331,11 +2752,11 @@ int mbedtls_rsa_rsassa_pkcs1_v15_verify(mbedtls_rsa_context *ctx, if (encoded != NULL) { mbedtls_zeroize_and_free(encoded, sig_len); - } + } if (encoded_expected != NULL) { mbedtls_zeroize_and_free(encoded_expected, sig_len); - } + } return ret; } @@ -2449,7 +2870,6 @@ void mbedtls_rsa_free(mbedtls_rsa_context *ctx) #if defined(MBEDTLS_SELF_TEST) -#include "mbedtls/md.h" /* * Example RSA-1024 keypair, for test purposes diff --git a/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c b/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c index 7302b628b..2e108cc90 100644 --- a/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c +++ b/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c @@ -419,12 +419,6 @@ static const hw_sce_rsa_private_decrypt_t g_rsa_private_decrypt_lookup[2] = #endif }; -/* Parameter validation macros */ - #define RSA_VALIDATE_RET(cond) \ - MBEDTLS_INTERNAL_VALIDATE_RET(cond, MBEDTLS_ERR_RSA_BAD_INPUT_DATA) - #define RSA_VALIDATE(cond) \ - MBEDTLS_INTERNAL_VALIDATE(cond) - #if defined(MBEDTLS_GENPRIME) /* @@ -439,7 +433,6 @@ int mbedtls_rsa_gen_key (mbedtls_rsa_context * ctx, (void) nbits; (void) exponent; int ret = 0; - RSA_VALIDATE_RET(ctx != NULL); (void) f_rng; (void) p_rng; @@ -806,10 +799,6 @@ int mbedtls_rsa_private (mbedtls_rsa_context * ctx, uint32_t * p_calloc_temp_buff_D = NULL; uint32_t * p_common_buff_32 = NULL; - RSA_VALIDATE_RET(ctx != NULL); - RSA_VALIDATE_RET(input != NULL); - RSA_VALIDATE_RET(output != NULL); - /* If the size of N is not equal to the modulus size, then that is because of the leading 00 (sign field) from the ASN1 import * Use openssl asn1parse -in private1.pem to see asn1 format of a .pem key */ if (ctx->N.n != (ctx->len / (sizeof(mbedtls_mpi_uint)))) diff --git a/ra/fsp/src/rm_psa_crypto/sha256_alt.c b/ra/fsp/src/rm_psa_crypto/sha256_alt.c index 05de3899d..857b8902e 100644 --- a/ra/fsp/src/rm_psa_crypto/sha256_alt.c +++ b/ra/fsp/src/rm_psa_crypto/sha256_alt.c @@ -5,21 +5,7 @@ * FIPS-180-2 compliant SHA-256 implementation * * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * This file is part of mbed TLS (https://tls.mbed.org) + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later */ /* * The SHA-256 Secure Hash Standard was published by NIST in 2002. @@ -29,8 +15,17 @@ /* UNCRUSTIFY-OFF */ -#if defined(__aarch64__) && !defined(__ARM_FEATURE_CRYPTO) && \ - defined(__clang__) && __clang_major__ >= 4 +#if defined(__clang__) && (__clang_major__ >= 4) + +/* Ideally, we would simply use MBEDTLS_ARCH_IS_ARMV8_A in the following #if, + * but that is defined by build_info.h, and we need this block to happen first. */ +#if defined(__ARM_ARCH) && (__ARM_ARCH_PROFILE == 'A') +#if __ARM_ARCH >= 8 +#define MBEDTLS_SHA256_ARCH_IS_ARMV8_A +#endif +#endif + +#if defined(MBEDTLS_SHA256_ARCH_IS_ARMV8_A) && !defined(__ARM_FEATURE_CRYPTO) /* TODO: Re-consider above after https://reviews.llvm.org/D131064 merged. * * The intrinsic declaration are guarded by predefined ACLE macros in clang: @@ -38,7 +33,7 @@ * By defining the macros ourselves we gain access to those declarations without * requiring -march on the command line. * - * `arm_neon.h` could be included by any header file, so we put these defines + * `arm_neon.h` is included by common.h, so we put these defines * at the top of this file, before any includes. */ #define __ARM_FEATURE_CRYPTO 1 @@ -51,6 +46,11 @@ #define MBEDTLS_ENABLE_ARM_CRYPTO_EXTENSIONS_COMPILER_FLAG #endif +#endif /* defined(__clang__) && (__clang_major__ >= 4) */ + +/* Ensure that SIG_SETMASK is defined when -std=c99 is used. */ +#define _GNU_SOURCE + #include "common.h" #if defined(MBEDTLS_SHA256_C) || defined(MBEDTLS_SHA224_C) @@ -63,29 +63,34 @@ #include "mbedtls/platform.h" -#if defined(__aarch64__) - -# if defined(MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT) || \ - defined(MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY) +#if defined(MBEDTLS_ARCH_IS_ARMV8_A) + +# if defined(MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT) || \ + defined(MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_ONLY) +# if !defined(MBEDTLS_HAVE_NEON_INTRINSICS) +# if defined(MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT) +# warning "Target does not support NEON instructions" +# undef MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT +# else +# error "Target does not support NEON instructions" +# endif +# endif +# endif +# if defined(MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT) || \ + defined(MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_ONLY) /* *INDENT-OFF* */ -# ifdef __ARM_NEON -# include -# else -# error "Target does not support NEON instructions" -# endif - -# if !defined(__ARM_FEATURE_CRYPTO) || defined(MBEDTLS_ENABLE_ARM_CRYPTO_EXTENSIONS_COMPILER_FLAG) +# if !defined(__ARM_FEATURE_CRYPTO) || defined(MBEDTLS_ENABLE_ARM_CRYPTO_EXTENSIONS_COMPILER_FLAG) # if defined(__ARMCOMPILER_VERSION) # if __ARMCOMPILER_VERSION <= 6090000 -# error "Must use minimum -march=armv8-a+crypto for MBEDTLS_SHA256_USE_A64_CRYPTO_*" +# error "Must use minimum -march=armv8-a+crypto for MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_*" # endif # pragma clang attribute push (__attribute__((target("sha2"))), apply_to=function) # define MBEDTLS_POP_TARGET_PRAGMA # elif defined(__clang__) # if __clang_major__ < 4 -# error "A more recent Clang is required for MBEDTLS_SHA256_USE_A64_CRYPTO_*" +# error "A more recent Clang is required for MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_*" # endif # pragma clang attribute push (__attribute__((target("crypto"))), apply_to=function) # define MBEDTLS_POP_TARGET_PRAGMA @@ -94,55 +99,62 @@ * intrinsics are missing. Missing intrinsics could be worked around. */ # if __GNUC__ < 6 -# error "A more recent GCC is required for MBEDTLS_SHA256_USE_A64_CRYPTO_*" +# error "A more recent GCC is required for MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_*" # else # pragma GCC push_options # pragma GCC target ("arch=armv8-a+crypto") # define MBEDTLS_POP_TARGET_PRAGMA # endif # else -# error "Only GCC and Clang supported for MBEDTLS_SHA256_USE_A64_CRYPTO_*" +# error "Only GCC and Clang supported for MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_*" # endif # endif /* *INDENT-ON* */ # endif -# if defined(MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT) +# if defined(MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT) # if defined(__unix__) # if defined(__linux__) - /* Our preferred method of detection is getauxval() */ +/* Our preferred method of detection is getauxval() */ # include +/* These are not always defined via sys/auxv.h */ +# if !defined(HWCAP_SHA2) +# define HWCAP_SHA2 (1 << 6) +# endif +# if !defined(HWCAP2_SHA2) +# define HWCAP2_SHA2 (1 << 3) +# endif # endif - /* Use SIGILL on Unix, and fall back to it on Linux */ +/* Use SIGILL on Unix, and fall back to it on Linux */ # include # endif # endif -#elif defined(_M_ARM64) -# if defined(MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT) || \ - defined(MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY) -# include -# endif -#else -# undef MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY -# undef MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT +#elif !defined(MBEDTLS_PLATFORM_IS_WINDOWS_ON_ARM64) +# undef MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_ONLY +# undef MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT #endif -#if defined(MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT) +#if defined(MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT) /* * Capability detection code comes early, so we can disable - * MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT if no detection mechanism found + * MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT if no detection mechanism found */ -#if defined(HWCAP_SHA2) +#if defined(MBEDTLS_ARCH_IS_ARM64) && defined(HWCAP_SHA2) static int mbedtls_a64_crypto_sha256_determine_support(void) { return (getauxval(AT_HWCAP) & HWCAP_SHA2) ? 1 : 0; } +#elif defined(MBEDTLS_ARCH_IS_ARM32) && defined(HWCAP2_SHA2) +static int mbedtls_a64_crypto_sha256_determine_support(void) +{ + return (getauxval(AT_HWCAP2) & HWCAP2_SHA2) ? 1 : 0; +} #elif defined(__APPLE__) static int mbedtls_a64_crypto_sha256_determine_support(void) { return 1; } -#elif defined(_M_ARM64) +#elif defined(MBEDTLS_PLATFORM_IS_WINDOWS_ON_ARM64) #define WIN32_LEAN_AND_MEAN #include #include @@ -160,7 +172,7 @@ static int mbedtls_a64_crypto_sha256_determine_support(void) static jmp_buf return_from_sigill; /* - * A64 SHA256 support detection via SIGILL + * Armv8-A SHA256 support detection via SIGILL */ static void sigill_handler(int signal) { @@ -187,7 +199,11 @@ static int mbedtls_a64_crypto_sha256_determine_support(void) if (setjmp(return_from_sigill) == 0) { /* First return only */ /* If this traps, we will return a second time from setjmp() with 1 */ - asm ("sha256h q0, q0, v0.4s" : : : "v0"); +#if defined(MBEDTLS_ARCH_IS_ARM64) + asm volatile ("sha256h q0, q0, v0.4s" : : : "v0"); +#else + asm volatile ("sha256h.32 q0, q0, q0" : : : "q0"); +#endif ret = 1; } @@ -197,11 +213,11 @@ static int mbedtls_a64_crypto_sha256_determine_support(void) return ret; } #else -#warning "No mechanism to detect A64_CRYPTO found, using C code only" -#undef MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT +#warning "No mechanism to detect ARMV8_CRYPTO found, using C code only" +#undef MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT #endif /* HWCAP_SHA2, __APPLE__, __unix__ && SIG_SETMASK */ -#endif /* MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT */ +#endif /* MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT */ #if defined(MBEDTLS_SHA256_ALT) @@ -353,10 +369,10 @@ static const uint32_t K[] = #endif -#if defined(MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT) || \ - defined(MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY) +#if defined(MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT) || \ + defined(MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_ONLY) -#if defined(MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY) +#if defined(MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_ONLY) # define mbedtls_internal_sha256_process_many_a64_crypto mbedtls_internal_sha256_process_many # define mbedtls_internal_sha256_process_a64_crypto mbedtls_internal_sha256_process #endif @@ -379,10 +395,10 @@ static size_t mbedtls_internal_sha256_process_many_a64_crypto( uint32x4_t abcd_orig = abcd; uint32x4_t efgh_orig = efgh; - uint32x4_t sched0 = (uint32x4_t) vld1q_u8(msg + 16 * 0); - uint32x4_t sched1 = (uint32x4_t) vld1q_u8(msg + 16 * 1); - uint32x4_t sched2 = (uint32x4_t) vld1q_u8(msg + 16 * 2); - uint32x4_t sched3 = (uint32x4_t) vld1q_u8(msg + 16 * 3); + uint32x4_t sched0 = vreinterpretq_u32_u8(vld1q_u8(msg + 16 * 0)); + uint32x4_t sched1 = vreinterpretq_u32_u8(vld1q_u8(msg + 16 * 1)); + uint32x4_t sched2 = vreinterpretq_u32_u8(vld1q_u8(msg + 16 * 2)); + uint32x4_t sched3 = vreinterpretq_u32_u8(vld1q_u8(msg + 16 * 3)); #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ /* Will be true if not defined */ /* Untested on BE */ @@ -456,9 +472,9 @@ static size_t mbedtls_internal_sha256_process_many_a64_crypto( return processed; } -#if defined(MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT) +#if defined(MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT) /* - * This function is for internal use only if we are building both C and A64 + * This function is for internal use only if we are building both C and Armv8-A * versions, otherwise it is renamed to be the public mbedtls_internal_sha256_process() */ static @@ -471,7 +487,7 @@ int mbedtls_internal_sha256_process_a64_crypto(mbedtls_sha256_context *ctx, SHA256_BLOCK_SIZE) ? 0 : -1; } -#endif /* MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT || MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY */ +#endif /* MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT || MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_ONLY */ #if defined(MBEDTLS_POP_TARGET_PRAGMA) #if defined(__clang__) @@ -482,14 +498,14 @@ int mbedtls_internal_sha256_process_a64_crypto(mbedtls_sha256_context *ctx, #undef MBEDTLS_POP_TARGET_PRAGMA #endif -#if !defined(MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT) +#if !defined(MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT) #define mbedtls_internal_sha256_process_many_c mbedtls_internal_sha256_process_many #define mbedtls_internal_sha256_process_c mbedtls_internal_sha256_process #endif #if !defined(MBEDTLS_SHA256_PROCESS_ALT) && \ - !defined(MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY) + !defined(MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_ONLY) #define SHR(x, n) (((x) & 0xFFFFFFFF) >> (n)) #define ROTR(x, n) (SHR(x, n) | ((x) << (32 - (n)))) @@ -517,9 +533,9 @@ int mbedtls_internal_sha256_process_a64_crypto(mbedtls_sha256_context *ctx, (d) += local.temp1; (h) = local.temp1 + local.temp2; \ } while (0) -#if defined(MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT) +#if defined(MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT) /* - * This function is for internal use only if we are building both C and A64 + * This function is for internal use only if we are building both C and Armv8 * versions, otherwise it is renamed to be the public mbedtls_internal_sha256_process() */ static @@ -535,13 +551,13 @@ int mbedtls_internal_sha256_process_c(mbedtls_sha256_context *ctx, unsigned int i; for (i = 0; i < 8; i++) { - A[i] = ctx->state[i]; + local.A[i] = ctx->state[i]; } #if defined(MBEDTLS_SHA256_SMALLER) for (i = 0; i < 64; i++) { if (i < 16) { - GET_UINT32_BE( local.W[i], data, 4 * i); + local.W[i] = MBEDTLS_GET_UINT32_BE(data, 4 * i); } else { R(i); } @@ -557,7 +573,7 @@ int mbedtls_internal_sha256_process_c(mbedtls_sha256_context *ctx, } #else /* MBEDTLS_SHA256_SMALLER */ for (i = 0; i < 16; i++) { - GET_UINT32_BE( local.W[i], data, 4 * i); + local.W[i] = MBEDTLS_GET_UINT32_BE(data, 4 * i); } for (i = 0; i < 16; i += 8) { @@ -609,10 +625,10 @@ int mbedtls_internal_sha256_process_c(mbedtls_sha256_context *ctx, return 0; } -#endif /* !MBEDTLS_SHA256_PROCESS_ALT && !MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY */ +#endif /* !MBEDTLS_SHA256_PROCESS_ALT && !MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_ONLY */ -#if !defined(MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY) +#if !defined(MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_ONLY) static size_t mbedtls_internal_sha256_process_many_c( mbedtls_sha256_context *ctx, const uint8_t *data, size_t len) @@ -633,10 +649,10 @@ static size_t mbedtls_internal_sha256_process_many_c( return processed; } -#endif /* !MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY */ +#endif /* !MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_ONLY */ -#if defined(MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT) +#if defined(MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT) static int mbedtls_a64_crypto_sha256_has_support(void) { @@ -671,7 +687,7 @@ int mbedtls_internal_sha256_process(mbedtls_sha256_context *ctx, } } -#endif /* MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT */ +#endif /* MBEDTLS_SHA256_USE_ARMV8_A_CRYPTO_IF_PRESENT */ /* diff --git a/ra/fsp/src/rm_psa_crypto/sha256_alt_process.c b/ra/fsp/src/rm_psa_crypto/sha256_alt_process.c index 5e4b31682..2e4115904 100644 --- a/ra/fsp/src/rm_psa_crypto/sha256_alt_process.c +++ b/ra/fsp/src/rm_psa_crypto/sha256_alt_process.c @@ -23,10 +23,6 @@ #define mbedtls_free free #endif /* MBEDTLS_PLATFORM_C */ - #define SHA256_VALIDATE_RET(cond) \ - MBEDTLS_INTERNAL_VALIDATE_RET(cond, MBEDTLS_ERR_SHA256_BAD_INPUT_DATA) - #define SHA256_VALIDATE(cond) MBEDTLS_INTERNAL_VALIDATE(cond) - #if defined(MBEDTLS_SHA256_PROCESS_ALT) #include "hw_sce_hash_private.h" @@ -46,8 +42,6 @@ int mbedtls_internal_sha256_process_ext (mbedtls_sha256_context * ctx, const unsigned char data[SIZE_MBEDTLS_SHA256_PROCESS_BUFFER_BYTES], uint32_t len) { - SHA256_VALIDATE_RET(ctx != NULL); - SHA256_VALIDATE_RET((const unsigned char *) data != NULL); uint32_t out_data[HW_SCE_SHA256_HASH_STATE_BUFFER_SIZE] = {0}; uint32_t * outbuff_digest_ptr = out_data; uint32_t sce_hash_type[1]; @@ -123,6 +117,18 @@ int mbedtls_internal_sha256_process_ext (mbedtls_sha256_context * ctx, memcpy(&ctx->state[0], out_data, HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE); } + #elif BSP_FEATURE_CRYPTO_HAS_RSIP_E11A + InData_MsgLen[0] = BYTES_TO_WORDS(len); + FSP_PARAMETER_NOT_USED(sce_hash_cmd); + FSP_PARAMETER_NOT_USED(sce_hash_type); + + if (FSP_SUCCESS != + HW_SCE_ShaGenerateMessageDigestSub(&ctx->state[0], (uint32_t *) &data[0], outbuff_digest_ptr, InData_MsgLen[0])) + { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + memcpy(&ctx->state[0], out_data, HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE); #else InData_MsgLen[0] = BYTES_TO_WORDS(len); if (FSP_SUCCESS != diff --git a/ra/fsp/src/rm_psa_crypto/sha512_alt.c b/ra/fsp/src/rm_psa_crypto/sha512_alt.c index ee032c98d..140754c76 100644 --- a/ra/fsp/src/rm_psa_crypto/sha512_alt.c +++ b/ra/fsp/src/rm_psa_crypto/sha512_alt.c @@ -2,19 +2,7 @@ * FIPS-180-2 compliant SHA-384/512 implementation * * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later */ /* * The SHA-512 Secure Hash Standard was published by NIST in 2002. @@ -31,7 +19,7 @@ * By defining the macros ourselves we gain access to those declarations without * requiring -march on the command line. * - * `arm_neon.h` could be included by any header file, so we put these defines + * `arm_neon.h` is included by common.h, so we put these defines * at the top of this file, before any includes. */ #define __ARM_FEATURE_SHA512 1 @@ -60,9 +48,7 @@ #if defined(MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT) || \ defined(MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY) /* *INDENT-OFF* */ -# ifdef __ARM_NEON -# include -# else +# if !defined(MBEDTLS_HAVE_NEON_INTRINSICS) # error "Target does not support NEON instructions" # endif /* @@ -116,21 +102,24 @@ # if defined(__unix__) # if defined(__linux__) /* Our preferred method of detection is getauxval() */ - # include - # endif +# include +# if !defined(HWCAP_SHA512) +/* The same header that declares getauxval() should provide the HWCAP_xxx + * constants to analyze its return value. However, the libc may be too + * old to have the constant that we need. So if it's missing, assume that + * the value is the same one used by the Linux kernel ABI. + */ +# define HWCAP_SHA512 (1 << 21) +# endif +# endif /* Use SIGILL on Unix, and fall back to it on Linux */ - # include - # endif - # endif - #elif defined(_M_ARM64) - # if defined(MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT) || \ - defined(MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY) - # include - # endif - #else - # undef MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY - # undef MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT - #endif +# include +# endif +# endif +#elif !defined(MBEDTLS_PLATFORM_IS_WINDOWS_ON_ARM64) +# undef MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY +# undef MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT +#endif #if defined(MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT) /* @@ -155,7 +144,7 @@ static int mbedtls_a64_crypto_sha512_determine_support(void) NULL, 0); return ret == 0 && value != 0; } - #elif defined(_M_ARM64) +#elif defined(MBEDTLS_PLATFORM_IS_WINDOWS_ON_ARM64) /* * As of March 2022, there don't appear to be any PF_ARM_V8_* flags * available to pass to IsProcessorFeaturePresent() to check for diff --git a/ra/fsp/src/rm_psa_crypto/sha512_alt_process.c b/ra/fsp/src/rm_psa_crypto/sha512_alt_process.c index 1c623b09c..2ffa80c02 100644 --- a/ra/fsp/src/rm_psa_crypto/sha512_alt_process.c +++ b/ra/fsp/src/rm_psa_crypto/sha512_alt_process.c @@ -26,10 +26,6 @@ #if defined(MBEDTLS_SHA512_PROCESS_ALT) #include "hw_sce_hash_private.h" - #define SHA512_VALIDATE_RET(cond) \ - MBEDTLS_INTERNAL_VALIDATE_RET(cond, \ - MBEDTLS_ERR_SHA512_BAD_INPUT_DATA) - /*******************************************************************************************************************//** * @addtogroup RM_PSA_CRYPTO * @{ @@ -46,8 +42,6 @@ int mbedtls_internal_sha512_process_ext (mbedtls_sha512_context * ctx, const unsigned char data[SIZE_MBEDTLS_SHA512_PROCESS_BUFFER_BYTES], uint32_t len) { - SHA512_VALIDATE_RET(ctx != NULL); - SHA512_VALIDATE_RET((const unsigned char *) data != NULL); uint32_t out_data[HW_SCE_SHA512_HASH_STATE_BUFFER_SIZE] = {0}; uint32_t * outbuff_digest_ptr = out_data; uint32_t sce_hash_type[1]; diff --git a/ra/fsp/src/rm_psa_crypto/vendor.c b/ra/fsp/src/rm_psa_crypto/vendor.c index 0cb16d005..c61ff42a9 100644 --- a/ra/fsp/src/rm_psa_crypto/vendor.c +++ b/ra/fsp/src/rm_psa_crypto/vendor.c @@ -10,6 +10,7 @@ #include "asymmetric_vendor.h" #include "aes_vendor.h" #include "mbedtls/error.h" +#include "mbedtls/psa_util.h" uint32_t ecp_load_key_size(bool wrapped_mode_ctx, const mbedtls_ecp_group * grp); @@ -87,16 +88,19 @@ static psa_key_bits_t calculate_key_bits_vendor (const psa_key_slot_t * slot) */ psa_status_t psa_generate_key_vendor (psa_key_slot_t * slot, size_t bits, - const uint8_t * domain_parameters, - size_t domain_parameters_size) + const psa_key_production_parameters_t *params, + size_t params_data_length) { (void) slot; (void) bits; - (void) domain_parameters; - (void) domain_parameters_size; + + /* Only used for RSA */ + (void) params; + (void) params_data_length; + psa_status_t status = PSA_ERROR_NOT_SUPPORTED; - if ((domain_parameters == NULL) && (domain_parameters_size != 0)) + if ((params == NULL) && (params_data_length != 0)) { return PSA_ERROR_INVALID_ARGUMENT; } @@ -124,7 +128,7 @@ psa_status_t psa_generate_key_vendor (psa_key_slot_t * slot, { mbedtls_rsa_context * rsa; int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - int exponent; + int exponent = 65537; // NOLINT(readability-magic-numbers) uint32_t export_der_size_bytes = 0; if (bits == RSA_2048_BITS) @@ -151,10 +155,12 @@ psa_status_t psa_generate_key_vendor (psa_key_slot_t * slot, return PSA_ERROR_NOT_SUPPORTED; } - status = psa_rsa_read_exponent(domain_parameters, domain_parameters_size, &exponent); - if (status != PSA_SUCCESS) - { - return status; + if (params_data_length != 0) { + status = psa_rsa_read_exponent(params->data, params_data_length, + &exponent); + if (status != PSA_SUCCESS) { + return status; + } } rsa = mbedtls_calloc(1, sizeof(*rsa)); @@ -176,7 +182,7 @@ psa_status_t psa_generate_key_vendor (psa_key_slot_t * slot, mbedtls_rsa_free(rsa); mbedtls_free(rsa); - return PSA_ERROR_HARDWARE_FAILURE; + return ret; } /* The key is stored in an export representation (DER format) in the slot. @@ -213,13 +219,14 @@ psa_status_t psa_generate_key_vendor (psa_key_slot_t * slot, { psa_ecc_family_t curve = PSA_KEY_TYPE_ECC_GET_FAMILY(slot->attr.type); uint32_t ecc_bytes = 0; + size_t olen = 0; mbedtls_ecp_group_id grp_id = - mbedtls_ecc_group_of_psa(curve, bits, 1); + mbedtls_ecc_group_from_psa(curve, bits); const mbedtls_ecp_curve_info * curve_info = mbedtls_ecp_curve_info_from_grp_id(grp_id); mbedtls_ecp_keypair * ecp; int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - if (domain_parameters_size != 0) + if (params_data_length != 0) { return PSA_ERROR_NOT_SUPPORTED; } @@ -229,11 +236,6 @@ psa_status_t psa_generate_key_vendor (psa_key_slot_t * slot, return PSA_ERROR_NOT_SUPPORTED; } - if (curve_info->bit_size != bits) - { - return PSA_ERROR_INVALID_ARGUMENT; - } - ecp = mbedtls_calloc(1, sizeof(*ecp)); if (ecp == NULL) { @@ -247,7 +249,7 @@ psa_status_t psa_generate_key_vendor (psa_key_slot_t * slot, mbedtls_ecp_keypair_free(ecp); mbedtls_free(ecp); - return PSA_ERROR_HARDWARE_FAILURE; + return ret; } /* The key is stored in an export representation (DER format) in the slot. */ @@ -261,7 +263,7 @@ psa_status_t psa_generate_key_vendor (psa_key_slot_t * slot, return status; } - status = mbedtls_to_psa_error(mbedtls_ecp_write_key(ecp, slot->key.data, ecc_bytes)); + status = mbedtls_to_psa_error(mbedtls_ecp_write_key_ext(ecp, &olen, slot->key.data, ecc_bytes)); mbedtls_ecp_keypair_free(ecp); mbedtls_free(ecp); diff --git a/ra/fsp/src/rm_tfm_port/config_impl.h b/ra/fsp/src/rm_tfm_port/config_impl.h index 1202f0ce1..e778f0d54 100644 --- a/ra/fsp/src/rm_tfm_port/config_impl.h +++ b/ra/fsp/src/rm_tfm_port/config_impl.h @@ -1,10 +1,12 @@ /* * Copyright (c) 2021-2022, Arm Limited. All rights reserved. + * Copyright (c) 2024, Cypress Semiconductor Corporation (an Infineon company) + * or an affiliate of Cypress Semiconductor Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * */ -/***********{{utilities.donotedit_warning}}***********/ +/*********** WARNING: This is an auto-generated file. Do not edit! ***********/ #ifndef __CONFIG_IMPL_H__ #define __CONFIG_IMPL_H__ @@ -28,16 +30,39 @@ #define CONFIG_TFM_NS_AGENT_TZ_STACK_SIZE 1024 #endif -/* SPM re-uses Trustzone NS agent stack. */ -#define CONFIG_TFM_SPM_THREAD_STACK_SIZE \ - CONFIG_TFM_NS_AGENT_TZ_STACK_SIZE +#if !defined CONFIG_TFM_USE_TRUSTZONE +/* SPM has to have its own stack if Trustzone isn't present. */ +#if defined(TFM_FIH_PROFILE_ON) +#define CONFIG_TFM_SPM_THREAD_STACK_SIZE 1536 +#else +#define CONFIG_TFM_SPM_THREAD_STACK_SIZE 1024 +#endif +#endif #elif CONFIG_TFM_SPM_BACKEND_SFN == 1 +/* + * In isolation level 1 SFN model, all subsequent components work on NS agent + * stack. It is observed that half of the sum of all partition stack sizes is + * enough for working. Define a divisor factor + * CONFIG_TFM_NS_AGENT_TZ_STK_SIZE_SHIFT_FACTOR for reference, and allow + * modification of the factor based on application situation. The stack size + * value is aligned to 8 bytes. + * The minimum value is 0x400 to satisfy the SPM functional requirement. + * Manifest tool will assure this. + */ +#define CONFIG_TFM_TOTAL_STACK_SIZE (0 + PS_STACK_SIZE + ITS_STACK_SIZE + CRYPTO_STACK_SIZE + PLATFORM_SP_STACK_SIZE + ATTEST_STACK_SIZE) +#if (CONFIG_TFM_TOTAL_STACK_SIZE < 2048) +#undef CONFIG_TFM_TOTAL_STACK_SIZE +#define CONFIG_TFM_TOTAL_STACK_SIZE 2048 +#endif #define CONFIG_TFM_NS_AGENT_TZ_STK_SIZE_SHIFT_FACTOR 1 #define CONFIG_TFM_NS_AGENT_TZ_STACK_SIZE \ - (((0x6220 >> CONFIG_TFM_NS_AGENT_TZ_STK_SIZE_SHIFT_FACTOR) + 0x7) & (~0x7)) + (((CONFIG_TFM_TOTAL_STACK_SIZE >> CONFIG_TFM_NS_AGENT_TZ_STK_SIZE_SHIFT_FACTOR) + 0x7) & (~0x7)) #endif /* CONFIG_TFM_SPM_BACKEND_IPC == 1 */ +/* Define whether ARoT partitions are present. Can be used when applying protections. */ +#define CONFIG_TFM_AROT_PRESENT 1 + #endif /* __CONFIG_IMPL_H__ */ diff --git a/ra/fsp/src/rm_tfm_port/ra/boot_hal_bl2.c b/ra/fsp/src/rm_tfm_port/ra/boot_hal_bl2.c index 23261bdf6..eaf3d430d 100644 --- a/ra/fsp/src/rm_tfm_port/ra/boot_hal_bl2.c +++ b/ra/fsp/src/rm_tfm_port/ra/boot_hal_bl2.c @@ -223,3 +223,16 @@ __WEAK int boot_platform_post_load (uint32_t image_id) { return 0; } + +__WEAK bool boot_platform_should_load_image(uint32_t image_id) +{ + return true; +} + +__WEAK int boot_initiate_recovery_mode(uint32_t image_id) +{ + (void)image_id; + + /* We haven't done anything, therefore recovery has failed */ + return 1; +} diff --git a/ra/fsp/src/rm_tfm_port/ra/tfm_hal_isolation.c b/ra/fsp/src/rm_tfm_port/ra/tfm_hal_isolation.c index 5a2d6f3b5..f5439d25c 100644 --- a/ra/fsp/src/rm_tfm_port/ra/tfm_hal_isolation.c +++ b/ra/fsp/src/rm_tfm_port/ra/tfm_hal_isolation.c @@ -166,6 +166,8 @@ enum tfm_hal_status_t tfm_hal_set_up_static_boundaries(uintptr_t *p_spm_boundary } #endif /* CONFIG_TFM_ENABLE_MEMORY_PROTECT */ + *p_spm_boundary = (uintptr_t)PROT_BOUNDARY_VAL; + return TFM_HAL_SUCCESS; } diff --git a/ra/fsp/src/rm_tfm_port/ra/tz_shim_layer.c b/ra/fsp/src/rm_tfm_port/ra/tz_shim_layer.c index 7bfe7d78f..6a43c851f 100644 --- a/ra/fsp/src/rm_tfm_port/ra/tz_shim_layer.c +++ b/ra/fsp/src/rm_tfm_port/ra/tz_shim_layer.c @@ -17,6 +17,7 @@ #include "tfm_ns_client_ext.h" #include "tfm_nspm.h" +#include "security_defs.h" #ifdef TFM_NS_MANAGE_NSID #define NSID_MGR_THREAD_ID_MAX 0xFF @@ -37,7 +38,7 @@ static uint8_t nsid_mgr_thread_id = 1; * Initialize token-nsid map table in tfm nsid manager * Return execution status (1: success, 0: error) */ -__tfm_nspm_secure_gateway_attributes__ +__tz_c_veneer uint32_t TZ_InitContextSystem_S(void) { #ifdef TFM_NS_MANAGE_NSID @@ -63,7 +64,7 @@ uint32_t TZ_InitContextSystem_S(void) * Return token if TFM_NS_MANAGE_NSID is enabled * Return 0 if no memory available or internal error */ -__tfm_nspm_secure_gateway_attributes__ +__tz_c_veneer TZ_MemoryId_t TZ_AllocModuleContext_S(TZ_ModuleId_t module) { #ifdef TFM_NS_MANAGE_NSID @@ -95,7 +96,7 @@ TZ_MemoryId_t TZ_AllocModuleContext_S(TZ_ModuleId_t module) * Param: TZ_MemoryId_t (token if TFM_NS_MANAGE_NSID is enabled) * Return execution status (1: success, 0: error) */ -__tfm_nspm_secure_gateway_attributes__ +__tz_c_veneer uint32_t TZ_FreeModuleContext_S(TZ_MemoryId_t id) { #ifdef TFM_NS_MANAGE_NSID @@ -123,7 +124,7 @@ uint32_t TZ_FreeModuleContext_S(TZ_MemoryId_t id) * Param: TZ_MemoryId_t (token if TFM_NS_MANAGE_NSID is enabled) * Return execution status (1: success, 0: error) */ -__tfm_nspm_secure_gateway_attributes__ +__tz_c_veneer uint32_t TZ_LoadContext_S(TZ_MemoryId_t id) { #ifdef TFM_NS_MANAGE_NSID @@ -154,7 +155,7 @@ uint32_t TZ_LoadContext_S(TZ_MemoryId_t id) * Param: TZ_MemoryId_t (token if TFM_NS_MANAGE_NSID is enabled) * Return execution status (1: success, 0: error) */ -__tfm_nspm_secure_gateway_attributes__ +__tz_c_veneer uint32_t TZ_StoreContext_S(TZ_MemoryId_t id) { #ifdef TFM_NS_MANAGE_NSID diff --git a/ra/fsp/src/rm_touch/rm_touch.c b/ra/fsp/src/rm_touch/rm_touch.c index 758f2df87..43690f399 100644 --- a/ra/fsp/src/rm_touch/rm_touch.c +++ b/ra/fsp/src/rm_touch/rm_touch.c @@ -506,19 +506,9 @@ fsp_err_t RM_TOUCH_Open (touch_ctrl_t * const p_ctrl, touch_cfg_t const * const (uint8_t) (g_touch_button_index + p_instance_ctrl->p_touch_cfg->num_buttons); } - if (0 == p_cfg->on_freq) - { - err = FSP_ERR_INVALID_ARGUMENT; - } - - if (0 == p_cfg->off_freq) - { - err = FSP_ERR_INVALID_ARGUMENT; - } - if (0 != p_cfg->cancel_freq) { - if (p_cfg->cancel_freq < p_cfg->on_freq) + if (p_cfg->cancel_freq <= p_cfg->on_freq) { err = FSP_ERR_INVALID_ARGUMENT; } diff --git a/ra/fsp/src/rm_zmod4xxx/iaq_1st_gen/rm_zmod4410_iaq_1st_gen.c b/ra/fsp/src/rm_zmod4xxx/iaq_1st_gen/rm_zmod4410_iaq_1st_gen.c index f2f2d8500..3a8373e22 100644 --- a/ra/fsp/src/rm_zmod4xxx/iaq_1st_gen/rm_zmod4410_iaq_1st_gen.c +++ b/ra/fsp/src/rm_zmod4xxx/iaq_1st_gen/rm_zmod4410_iaq_1st_gen.c @@ -73,6 +73,9 @@ static fsp_err_t rm_zmod4410_iaq_1st_gen_rel_iaq_data_calculate(rm_zmod4xxx_ctrl static fsp_err_t rm_zmod4410_iaq_1st_gen_pbaq_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, rm_zmod4xxx_pbaq_data_t * const p_zmod4xxx_data); +static fsp_err_t rm_zmod4410_iaq_1st_gen_no2_o3_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data); static fsp_err_t rm_zmod4410_iaq_1st_gen_close(rm_zmod4xxx_ctrl_t * const p_api_ctrl); static fsp_err_t rm_zmod4410_iaq_1st_gen_device_error_check(rm_zmod4xxx_ctrl_t * const p_api_ctrl); @@ -96,6 +99,7 @@ rm_zmod4xxx_api_t const g_zmod4xxx_on_zmod4410_iaq_1st_gen = .raqDataCalculate = rm_zmod4410_iaq_1st_gen_raq_data_calculate, .relIaqDataCalculate = rm_zmod4410_iaq_1st_gen_rel_iaq_data_calculate, .pbaqDataCalculate = rm_zmod4410_iaq_1st_gen_pbaq_data_calculate, + .no2O3DataCalculate = rm_zmod4410_iaq_1st_gen_no2_o3_data_calculate, .temperatureAndHumiditySet = rm_zmod4410_iaq_1st_gen_temperature_and_humidity_set, .deviceErrorCheck = rm_zmod4410_iaq_1st_gen_device_error_check, }; @@ -368,6 +372,22 @@ static fsp_err_t rm_zmod4410_iaq_1st_gen_pbaq_data_calculate (rm_zmod4xxx_ctrl_t return FSP_ERR_UNSUPPORTED; } +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4410_iaq_1st_gen_no2_o3_data_calculate (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_raw_data); + FSP_PARAMETER_NOT_USED(p_zmod4xxx_data); + + return FSP_ERR_UNSUPPORTED; +} + /*******************************************************************************************************************//** * @brief Unsupported API. * diff --git a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/rm_zmod4410_iaq_2nd_gen.c b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/rm_zmod4410_iaq_2nd_gen.c index 85cde7388..dce1985f8 100644 --- a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/rm_zmod4410_iaq_2nd_gen.c +++ b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/rm_zmod4410_iaq_2nd_gen.c @@ -78,6 +78,9 @@ static fsp_err_t rm_zmod4410_iaq_2nd_gen_rel_iaq_data_calculate(rm_zmod4xxx_ctrl static fsp_err_t rm_zmod4410_iaq_2nd_gen_pbaq_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, rm_zmod4xxx_pbaq_data_t * const p_zmod4xxx_data); +static fsp_err_t rm_zmod4410_iaq_2nd_gen_no2_o3_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data); static fsp_err_t rm_zmod4410_iaq_2nd_gen_close(rm_zmod4xxx_ctrl_t * const p_api_ctrl); static fsp_err_t rm_zmod4410_iaq_2nd_gen_device_error_check(rm_zmod4xxx_ctrl_t * const p_api_ctrl); @@ -101,6 +104,7 @@ rm_zmod4xxx_api_t const g_zmod4xxx_on_zmod4410_iaq_2nd_gen = .raqDataCalculate = rm_zmod4410_iaq_2nd_gen_raq_data_calculate, .relIaqDataCalculate = rm_zmod4410_iaq_2nd_gen_rel_iaq_data_calculate, .pbaqDataCalculate = rm_zmod4410_iaq_2nd_gen_pbaq_data_calculate, + .no2O3DataCalculate = rm_zmod4410_iaq_2nd_gen_no2_o3_data_calculate, .temperatureAndHumiditySet = rm_zmod4410_iaq_2nd_gen_temperature_and_humidity_set, .deviceErrorCheck = rm_zmod4410_iaq_2nd_gen_device_error_check, }; @@ -387,6 +391,22 @@ static fsp_err_t rm_zmod4410_iaq_2nd_gen_pbaq_data_calculate (rm_zmod4xxx_ctrl_t return FSP_ERR_UNSUPPORTED; } +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4410_iaq_2nd_gen_no2_o3_data_calculate (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_raw_data); + FSP_PARAMETER_NOT_USED(p_zmod4xxx_data); + + return FSP_ERR_UNSUPPORTED; +} + /*******************************************************************************************************************//** * @brief Unsupported API. * diff --git a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/rm_zmod4410_iaq_2nd_gen_ulp.c b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/rm_zmod4410_iaq_2nd_gen_ulp.c index fbf02dcb9..e24d5f292 100644 --- a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/rm_zmod4410_iaq_2nd_gen_ulp.c +++ b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/rm_zmod4410_iaq_2nd_gen_ulp.c @@ -79,6 +79,9 @@ static fsp_err_t rm_zmod4410_iaq_2nd_gen_ulp_rel_iaq_data_calculate(rm_zmod4xxx_ static fsp_err_t rm_zmod4410_iaq_2nd_gen_ulp_pbaq_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, rm_zmod4xxx_pbaq_data_t * const p_zmod4xxx_data); +static fsp_err_t rm_zmod4410_iaq_2nd_gen_ulp_no2_o3_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data); static fsp_err_t rm_zmod4410_iaq_2nd_gen_ulp_close(rm_zmod4xxx_ctrl_t * const p_api_ctrl); static fsp_err_t rm_zmod4410_iaq_2nd_gen_ulp_device_error_check(rm_zmod4xxx_ctrl_t * const p_api_ctrl); @@ -102,6 +105,7 @@ rm_zmod4xxx_api_t const g_zmod4xxx_on_zmod4410_iaq_2nd_gen_ulp = .raqDataCalculate = rm_zmod4410_iaq_2nd_gen_ulp_raq_data_calculate, .relIaqDataCalculate = rm_zmod4410_iaq_2nd_gen_ulp_rel_iaq_data_calculate, .pbaqDataCalculate = rm_zmod4410_iaq_2nd_gen_ulp_pbaq_data_calculate, + .no2O3DataCalculate = rm_zmod4410_iaq_2nd_gen_ulp_no2_o3_data_calculate, .temperatureAndHumiditySet = rm_zmod4410_iaq_2nd_gen_ulp_temperature_and_humidity_set, .deviceErrorCheck = rm_zmod4410_iaq_2nd_gen_ulp_device_error_check, }; @@ -393,6 +397,22 @@ static fsp_err_t rm_zmod4410_iaq_2nd_gen_ulp_pbaq_data_calculate (rm_zmod4xxx_ct return FSP_ERR_UNSUPPORTED; } +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4410_iaq_2nd_gen_ulp_no2_o3_data_calculate (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_raw_data); + FSP_PARAMETER_NOT_USED(p_zmod4xxx_data); + + return FSP_ERR_UNSUPPORTED; +} + /*******************************************************************************************************************//** * @brief Unsupported API. * diff --git a/ra/fsp/src/rm_zmod4xxx/no2_o3/no2_o3.h b/ra/fsp/src/rm_zmod4xxx/no2_o3/no2_o3.h new file mode 100644 index 000000000..4a26358d5 --- /dev/null +++ b/ra/fsp/src/rm_zmod4xxx/no2_o3/no2_o3.h @@ -0,0 +1,104 @@ +/** + * @addtogroup _api + * @{ + * @file no2_o3.h + * @author Renesas Electronics Corporation + * @version 1.0.1 + * @brief This file contains the data structure definitions and + * the function definitions for the NO2 O3 algorithm. + * @details The library contains an algorithm to calculate ozone and + * nitrogen dioxide concentrations and various air quality index + * values from the ZMOD4510 measurements. + */ + +#ifndef NO2_O3_H_ +#define NO2_O3_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if TEST_RM_ZMOD4XXX // For RA FSP test + #include "../../../../../fsp/src/rm_zmod4xxx/zmod4xxx_types.h" +#else + #include "../zmod4xxx_types.h" +#endif + +/** \addtogroup RetCodes Return codes of the algorithm functions. + * \ingroup _api + * @{ + */ +#define NO2_O3_OK (0) /**< everything okay */ +#define NO2_O3_STABILIZATION (1) /**< sensor in stabilization */ +#define NO2_O3_DAMAGE (-102) /**< sensor damaged */ +/** @}*/ + +/** +* @brief Variables that describe the sensor or the algorithm state. +*/ +typedef struct { + uint32_t sample_counter; /**< Sample counter. Will saturate at 0xFFFFFFFF. */ + float rmoxs_smooth[4]; + float logrmoxs_mean[4]; + float logrmoxs_var[4]; + float o3_1min_ppb; + float o3_1h_ppb; + float o3_8h_ppb; + float no2_1min_ppb; + float no2_1h_ppb; +} no2_o3_handle_t; + +/** +* @brief Variables that receive the algorithm outputs. +*/ +typedef struct { + float rmox[4]; /**< MOx resistance. */ + float temperature; /**< Temperature (degC) used for ambient compensation */ + float O3_conc_ppb; /**< O3_conc_ppb stands for the ozone concentration in part-per-billion */ + float NO2_conc_ppb; /**< NO2_conc_ppb stands for the NO2 concentration in part-per-billion */ + uint16_t + FAST_AQI; /**< FAST_AQI stands for a 1-minute average of the Air Quality Index according to the EPA standard based on ozone */ + uint16_t + EPA_AQI; /**< EPA_AQI stands for the Air Quality Index according to the EPA standard based on ozone. */ +} no2_o3_results_t; + +/** +* @brief Variables that are needed for algorithm + * @param [in] adc_result Value from read_adc_result function + * @param [in] humidity_pct relative ambient humidity (%) + * @param [in] temperature_degc ambient temperature (degC) +*/ +typedef struct { + uint8_t *adc_result; + float humidity_pct; + float temperature_degc; +} no2_o3_inputs_t; + +/** + * @brief Initializes the NO2 O3 algorithm. + * @param [out] handle Pointer to algorithm state variable. + * @return error code. +*/ +int8_t init_no2_o3(no2_o3_handle_t *handle); + +/** + * @brief calculates NO2 O3 results from present sample. + * @param [in] handle Pointer to algorithm state variable. + * @param [in] dev Pointer to the device. + * @param [in] algo_input Structure containing inputs required for algo calculation. + * @param [out] results Pointer for storing the algorithm results. + * @return error code. + */ +int8_t calc_no2_o3(no2_o3_handle_t *handle, const zmod4xxx_dev_t *dev, + const no2_o3_inputs_t *algo_input, + no2_o3_results_t *results); + +#ifdef __cplusplus +} +#endif + +#endif /* NO2_O3_H_ */ +/** @} */ diff --git a/ra/fsp/src/rm_zmod4xxx/no2_o3/rm_zmod4510_no2_o3.c b/ra/fsp/src/rm_zmod4xxx/no2_o3/rm_zmod4510_no2_o3.c new file mode 100644 index 000000000..786cfbef7 --- /dev/null +++ b/ra/fsp/src/rm_zmod4xxx/no2_o3/rm_zmod4510_no2_o3.c @@ -0,0 +1,420 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * Includes , "Project Includes" + *********************************************************************************************************************/ +#if defined(__CCRX__) || defined(__ICCRX__) || defined(__RX__) + #include "r_zmod4xxx_if.h" +#elif defined(__CCRL__) || defined(__ICCRL78__) || defined(__RL78__) + #include "r_zmod4xxx_if.h" +#else + #define RM_ZMOD4510_NO2_O3_GEN_CFG_LIB_ENABLE (1) +#endif + +#if RM_ZMOD4510_NO2_O3_GEN_CFG_LIB_ENABLE + #include "rm_zmod4xxx.h" + #include "../zmod4xxx_types.h" + #include "no2_o3.h" + #include "zmod4510_config_no2_o3.h" + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ + +/* Definitions of NO2 O3 Parameter */ + #define RM_ZMOD4410_NO2_O3_DEFAULT_HUMIDITY (50.0F) + #define RM_ZMOD4410_NO2_O3_DEFAULT_TEMPERATURE (20.0F) + +/********************************************************************************************************************** + * Local Typedef definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Private (static) variables and functions + *********************************************************************************************************************/ + +static fsp_err_t rm_zmod4510_no2_o3_open(rm_zmod4xxx_ctrl_t * const p_api_ctrl, rm_zmod4xxx_cfg_t const * const p_cfg); +static fsp_err_t rm_zmod4510_no2_o3_measurement_start(rm_zmod4xxx_ctrl_t * const p_api_ctrl); +static fsp_err_t rm_zmod4510_no2_o3_measurement_stop(rm_zmod4xxx_ctrl_t * const p_api_ctrl); +static fsp_err_t rm_zmod4510_no2_o3_status_check(rm_zmod4xxx_ctrl_t * const p_api_ctrl); +static fsp_err_t rm_zmod4510_no2_o3_read(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data); +static fsp_err_t rm_zmod4510_no2_o3_temperature_and_humidity_set(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + float temperature, + float humidity); +static fsp_err_t rm_zmod4510_no2_o3_iaq_1st_gen_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_iaq_1st_data_t * const p_zmod4xxx_data); +static fsp_err_t rm_zmod4510_no2_o3_iaq_2nd_gen_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_iaq_2nd_data_t * const p_zmod4xxx_data); +static fsp_err_t rm_zmod4510_no2_o3_odor_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_odor_data_t * const p_zmod4xxx_data); +static fsp_err_t rm_zmod4510_no2_o3_sulfur_odor_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_sulfur_odor_data_t * const p_zmod4xxx_data); +static fsp_err_t rm_zmod4510_no2_o3_oaq_1st_gen_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_oaq_1st_data_t * const p_zmod4xxx_data); +static fsp_err_t rm_zmod4510_no2_o3_oaq_2nd_gen_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_oaq_2nd_data_t * const p_zmod4xxx_data); +static fsp_err_t rm_zmod4510_no2_o3_raq_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_raq_data_t * const p_zmod4xxx_data); +static fsp_err_t rm_zmod4510_no2_o3_rel_iaq_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_rel_iaq_data_t * const p_zmod4xxx_data); +static fsp_err_t rm_zmod4510_no2_o3_pbaq_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_pbaq_data_t * const p_zmod4xxx_data); +static fsp_err_t rm_zmod4510_no2_o3_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data); +static fsp_err_t rm_zmod4510_no2_o3_close(rm_zmod4xxx_ctrl_t * const p_api_ctrl); +static fsp_err_t rm_zmod4510_no2_o3_device_error_check(rm_zmod4xxx_ctrl_t * const p_api_ctrl); + +/********************************************************************************************************************** + * Exported global variables + *********************************************************************************************************************/ +rm_zmod4xxx_api_t const g_zmod4xxx_on_zmod4510_no2_o3 = +{ + .open = rm_zmod4510_no2_o3_open, + .close = rm_zmod4510_no2_o3_close, + .measurementStart = rm_zmod4510_no2_o3_measurement_start, + .measurementStop = rm_zmod4510_no2_o3_measurement_stop, + .statusCheck = rm_zmod4510_no2_o3_status_check, + .read = rm_zmod4510_no2_o3_read, + .iaq1stGenDataCalculate = rm_zmod4510_no2_o3_iaq_1st_gen_data_calculate, + .iaq2ndGenDataCalculate = rm_zmod4510_no2_o3_iaq_2nd_gen_data_calculate, + .odorDataCalculate = rm_zmod4510_no2_o3_odor_data_calculate, + .sulfurOdorDataCalculate = rm_zmod4510_no2_o3_sulfur_odor_data_calculate, + .oaq1stGenDataCalculate = rm_zmod4510_no2_o3_oaq_1st_gen_data_calculate, + .oaq2ndGenDataCalculate = rm_zmod4510_no2_o3_oaq_2nd_gen_data_calculate, + .raqDataCalculate = rm_zmod4510_no2_o3_raq_data_calculate, + .relIaqDataCalculate = rm_zmod4510_no2_o3_rel_iaq_data_calculate, + .pbaqDataCalculate = rm_zmod4510_no2_o3_pbaq_data_calculate, + .no2O3DataCalculate = rm_zmod4510_no2_o3_data_calculate, + .temperatureAndHumiditySet = rm_zmod4510_no2_o3_temperature_and_humidity_set, + .deviceErrorCheck = rm_zmod4510_no2_o3_device_error_check, +}; + +/********************************************************************************************************************** + * Exported global functions + *********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Initialize the NO2 O3 library + * + * @retval FSP_SUCCESS Successfully started. + * @retval FSP_ERR_ASSERTION Null pointer passed as a parameter. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4510_no2_o3_open (rm_zmod4xxx_ctrl_t * const p_api_ctrl, rm_zmod4xxx_cfg_t const * const p_cfg) +{ + rm_zmod4xxx_instance_ctrl_t * p_ctrl = (rm_zmod4xxx_instance_ctrl_t *) p_api_ctrl; + int8_t lib_err = 0; + rm_zmod4xxx_lib_extended_cfg_t * p_lib = p_ctrl->p_zmod4xxx_lib; + no2_o3_handle_t * p_handle = (no2_o3_handle_t *) p_lib->p_handle; + + FSP_PARAMETER_NOT_USED(p_cfg); + + /* Set default temperature and humidity */ + p_lib->temperature = RM_ZMOD4410_NO2_O3_DEFAULT_HUMIDITY; + p_lib->humidity = RM_ZMOD4410_NO2_O3_DEFAULT_TEMPERATURE; + + /* Initialize the library */ + lib_err = init_no2_o3(p_handle); + FSP_ERROR_RETURN(0 == lib_err, FSP_ERR_ASSERTION); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @brief Calculate the NO2 O3 data with the library API. + * + * @retval FSP_SUCCESS Successfully results are read. + * @retval FSP_ERR_ASSERTION Null pointer passed as a parameter. + * @retval FSP_ERR_SENSOR_IN_STABILIZATION Module is stabilizing. + * @retval FSP_ERR_SENSOR_INVALID_DATA Sensor probably damaged. Algorithm results may be incorrect. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4510_no2_o3_data_calculate (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data) +{ + rm_zmod4xxx_instance_ctrl_t * p_ctrl = (rm_zmod4xxx_instance_ctrl_t *) p_api_ctrl; + rm_zmod4xxx_lib_extended_cfg_t * p_lib = p_ctrl->p_zmod4xxx_lib; + no2_o3_handle_t * p_handle = (no2_o3_handle_t *) p_lib->p_handle; + no2_o3_results_t * p_results = (no2_o3_results_t *) p_lib->p_results; + zmod4xxx_dev_t * p_device = (zmod4xxx_dev_t *) p_lib->p_device; + uint16_t i; + int8_t lib_err = 0; + no2_o3_inputs_t algorithm_input; + + /* Calculate NO2 O3 data form ADC data */ + algorithm_input.adc_result = &p_raw_data->adc_data[0]; + algorithm_input.humidity_pct = p_lib->humidity; + algorithm_input.temperature_degc = p_lib->temperature; + lib_err = calc_no2_o3(p_handle, p_device, &algorithm_input, p_results); + FSP_ERROR_RETURN(0 <= lib_err, FSP_ERR_ASSERTION); + + /* Set Data */ + for (i = 0; i < 4; i++) + { + p_zmod4xxx_data->rmox[i] = p_results->rmox[i]; + } + + p_zmod4xxx_data->temperature = p_results->temperature; + p_zmod4xxx_data->ozone_concentration = p_results->O3_conc_ppb; + p_zmod4xxx_data->no2_concentration = p_results->NO2_conc_ppb; + p_zmod4xxx_data->fast_aqi = p_results->FAST_AQI; + p_zmod4xxx_data->epa_aqi = p_results->EPA_AQI; + FSP_ERROR_RETURN(NO2_O3_STABILIZATION != lib_err, FSP_ERR_SENSOR_IN_STABILIZATION); + FSP_ERROR_RETURN(NO2_O3_DAMAGE != lib_err, FSP_ERR_SENSOR_INVALID_DATA); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4510_no2_o3_close (rm_zmod4xxx_ctrl_t * const p_api_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4510_no2_o3_measurement_start (rm_zmod4xxx_ctrl_t * const p_api_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4510_no2_o3_measurement_stop (rm_zmod4xxx_ctrl_t * const p_api_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4510_no2_o3_status_check (rm_zmod4xxx_ctrl_t * const p_api_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4510_no2_o3_read (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_raw_data); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4510_no2_o3_temperature_and_humidity_set (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + float temperature, + float humidity) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(temperature); + FSP_PARAMETER_NOT_USED(humidity); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4510_no2_o3_iaq_1st_gen_data_calculate (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_iaq_1st_data_t * const p_zmod4xxx_data) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_raw_data); + FSP_PARAMETER_NOT_USED(p_zmod4xxx_data); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4510_no2_o3_iaq_2nd_gen_data_calculate (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_iaq_2nd_data_t * const p_zmod4xxx_data) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_raw_data); + FSP_PARAMETER_NOT_USED(p_zmod4xxx_data); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4510_no2_o3_odor_data_calculate (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_odor_data_t * const p_zmod4xxx_data) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_raw_data); + FSP_PARAMETER_NOT_USED(p_zmod4xxx_data); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4510_no2_o3_sulfur_odor_data_calculate (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_sulfur_odor_data_t * const p_zmod4xxx_data) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_raw_data); + FSP_PARAMETER_NOT_USED(p_zmod4xxx_data); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4510_no2_o3_oaq_1st_gen_data_calculate (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_oaq_1st_data_t * const p_zmod4xxx_data) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_raw_data); + FSP_PARAMETER_NOT_USED(p_zmod4xxx_data); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4510_no2_o3_oaq_2nd_gen_data_calculate (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_oaq_2nd_data_t * const p_zmod4xxx_data) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_raw_data); + FSP_PARAMETER_NOT_USED(p_zmod4xxx_data); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4510_no2_o3_raq_data_calculate (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_raq_data_t * const p_zmod4xxx_data) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_raw_data); + FSP_PARAMETER_NOT_USED(p_zmod4xxx_data); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4510_no2_o3_rel_iaq_data_calculate (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_rel_iaq_data_t * const p_zmod4xxx_data) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_raw_data); + FSP_PARAMETER_NOT_USED(p_zmod4xxx_data); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4510_no2_o3_pbaq_data_calculate (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_pbaq_data_t * const p_zmod4xxx_data) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_raw_data); + FSP_PARAMETER_NOT_USED(p_zmod4xxx_data); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4510_no2_o3_device_error_check (rm_zmod4xxx_ctrl_t * const p_api_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +#endif diff --git a/ra/fsp/src/rm_zmod4xxx/no2_o3/zmod4510_config_no2_o3.h b/ra/fsp/src/rm_zmod4xxx/no2_o3/zmod4510_config_no2_o3.h new file mode 100644 index 000000000..4eef52cf2 --- /dev/null +++ b/ra/fsp/src/rm_zmod4xxx/no2_o3/zmod4510_config_no2_o3.h @@ -0,0 +1,101 @@ +/** + * @file zmod4510_config_no2_o3.h + * @brief This is the configuration for ZMOD4510 module - no2_o3 library + * @author Renesas Electronics Corporation + * @version 1.0.1 + */ + +#ifndef _ZMOD4510_CONFIG_NO2_O3_H_ +#define _ZMOD4510_CONFIG_NO2_O3_H_ + +#include + +#if TEST_RM_ZMOD4XXX // For RA FSP test + #include "../../../../../fsp/src/rm_zmod4xxx/zmod4xxx_types.h" +#else + #include "../zmod4xxx_types.h" +#endif + +#define INIT 0 +#define MEASUREMENT 1 + +/**********************************/ +/* < Define product ID > */ +#define ZMOD4510_PID 0x6320 + +/**********************************/ +/* < Define I2C slave address > */ +#define ZMOD4510_I2C_ADDR 0x33 + +/**********************************/ +/* < Define product data length > */ +#define ZMOD4510_PROD_DATA_LEN 10 + +/*************************************/ +/* < Define ADC result data length > */ +#define ZMOD4510_ADC_DATA_LEN (32) + +// time between samples +#define ZMOD4510_NO2_O3_SAMPLE_TIME (6000U) + +// REMOVE Sequencer adresses +#define ZMOD4XXX_H_ADDR 0x40 +#define ZMOD4XXX_D_ADDR 0x50 +#define ZMOD4XXX_M_ADDR 0x60 +#define ZMOD4XXX_S_ADDR 0x68 + +// clang-format off +static uint8_t data_set_4510_init[] = { +// REMOVE heater + 0x00, 0x50, +// REMOVE delay , measurement + 0x00, 0x28, 0xC3, 0xE3, +// REMOVE sequencer + 0x00, 0x00, 0x80, 0x40}; + +static uint8_t data_set_4510_no2_o3[] = { +// REMOVE this implements the ULP_NN_16ext.xml sequence +// REMOVE heater + 0x00, 0x50, 0xFF, 0x06, + 0xFE, 0xA2, 0xFE, 0x3E, +// REMOVE delay + 0x00, 0x10, 0x00, 0x52, + 0x3F, 0x66, 0x00, 0x42, +// REMOVE measurement + 0x23, 0x03, +// REMOVE sequencer + 0x00, 0x00, 0x02, 0x41, + 0x00, 0x41, 0x00, 0x41, + 0x00, 0x49, 0x00, 0x50, + 0x02, 0x42, 0x00, 0x42, + 0x00, 0x42, 0x00, 0x4A, + 0x00, 0x50, 0x02, 0x43, + 0x00, 0x43, 0x00, 0x43, + 0x00, 0x43, 0x80, 0x5B, + }; + +// clang-format on +zmod4xxx_conf g_zmod4510_no2_o3_sensor_type[] = { + [INIT] = { + .start = 0x80, + .h = { .addr = ZMOD4XXX_H_ADDR, .len = 2, .data_buf = &data_set_4510_init[0]}, + .d = { .addr = ZMOD4XXX_D_ADDR, .len = 2, .data_buf = &data_set_4510_init[2]}, + .m = { .addr = ZMOD4XXX_M_ADDR, .len = 2, .data_buf = &data_set_4510_init[4]}, + .s = { .addr = ZMOD4XXX_S_ADDR, .len = 4, .data_buf = &data_set_4510_init[6]}, + .r = { .addr = 0x97, .len = 4}, + }, + + [MEASUREMENT] = { + .start = 0x80, + .h = {.addr = ZMOD4XXX_H_ADDR, .len = 8, .data_buf = &data_set_4510_no2_o3[0]}, + .d = {.addr = ZMOD4XXX_D_ADDR, .len = 8, .data_buf = &data_set_4510_no2_o3[8]}, + .m = {.addr = ZMOD4XXX_M_ADDR, .len = 2, .data_buf = &data_set_4510_no2_o3[16]}, + .s = {.addr = ZMOD4XXX_S_ADDR, .len = 32, .data_buf = &data_set_4510_no2_o3[18]}, + .r = {.addr = 0x97, .len = 32}, + .prod_data_len = ZMOD4510_PROD_DATA_LEN, + }, +}; + +#define RMOX3_OFFSET (15 * 2) + +#endif //_ZMOD4510_CONFIG_NO2_O3_H_ diff --git a/ra/fsp/src/rm_zmod4xxx/oaq_1st_gen/rm_zmod4510_oaq_1st_gen.c b/ra/fsp/src/rm_zmod4xxx/oaq_1st_gen/rm_zmod4510_oaq_1st_gen.c index d0d3c744a..205dd0c8b 100644 --- a/ra/fsp/src/rm_zmod4xxx/oaq_1st_gen/rm_zmod4510_oaq_1st_gen.c +++ b/ra/fsp/src/rm_zmod4xxx/oaq_1st_gen/rm_zmod4510_oaq_1st_gen.c @@ -73,6 +73,9 @@ static fsp_err_t rm_zmod4510_oaq_1st_gen_rel_iaq_data_calculate(rm_zmod4xxx_ctrl static fsp_err_t rm_zmod4510_oaq_1st_gen_pbaq_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, rm_zmod4xxx_pbaq_data_t * const p_zmod4xxx_data); +static fsp_err_t rm_zmod4510_oaq_1st_gen_no2_o3_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data); static fsp_err_t rm_zmod4510_oaq_1st_gen_close(rm_zmod4xxx_ctrl_t * const p_api_ctrl); static fsp_err_t rm_zmod4510_oaq_1st_gen_device_error_check(rm_zmod4xxx_ctrl_t * const p_api_ctrl); static fsp_err_t rm_zmod4510_oaq_1st_gen_calc_rmox(rm_zmod4xxx_instance_ctrl_t * const p_ctrl, @@ -99,6 +102,7 @@ rm_zmod4xxx_api_t const g_zmod4xxx_on_zmod4510_oaq_1st_gen = .raqDataCalculate = rm_zmod4510_oaq_1st_gen_raq_data_calculate, .relIaqDataCalculate = rm_zmod4510_oaq_1st_gen_rel_iaq_data_calculate, .pbaqDataCalculate = rm_zmod4510_oaq_1st_gen_pbaq_data_calculate, + .no2O3DataCalculate = rm_zmod4510_oaq_1st_gen_no2_o3_data_calculate, .temperatureAndHumiditySet = rm_zmod4510_oaq_1st_gen_temperature_and_humidity_set, .deviceErrorCheck = rm_zmod4510_oaq_1st_gen_device_error_check, }; @@ -368,6 +372,22 @@ static fsp_err_t rm_zmod4510_oaq_1st_gen_pbaq_data_calculate (rm_zmod4xxx_ctrl_t return FSP_ERR_UNSUPPORTED; } +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4510_oaq_1st_gen_no2_o3_data_calculate (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_raw_data); + FSP_PARAMETER_NOT_USED(p_zmod4xxx_data); + + return FSP_ERR_UNSUPPORTED; +} + /*******************************************************************************************************************//** * @brief Unsupported API. * diff --git a/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/oaq_2nd_gen.h b/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/oaq_2nd_gen.h index 17ab4aabc..d42924196 100644 --- a/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/oaq_2nd_gen.h +++ b/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/oaq_2nd_gen.h @@ -1,104 +1,30 @@ -/* -* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - /** - * @file oaq_2nd_gen.h - * @author Renesas Electronics Corporation - * @version 4.0.0 - * @brief This file contains the data structure definitions and - * the function definitions for the 2nd generation OAQ algorithm. - * @details The library contains an algorithm to calculate an ozone - * concentration and various air quality index values - * from the ZMOD4510 measurements. - */ + * @file oaq_2nd_gen.h + * @author Renesas Electronics Corporation + * @version 5.0.0 + * @brief Provide names for oaq_2nd_gen backward compatibility. + * @note OAQ 2nd Gen naming is deprecated and will be removed + * in future revisions. + */ #ifndef OAQ_2ND_GEN_H_ - #define OAQ_2ND_GEN_H_ - - #ifdef __cplusplus -extern "C" { - #endif - - #include - #include - -#if TEST_RM_ZMOD4XXX // For RA FSP test - #include "../../../../../fsp/src/rm_zmod4xxx/zmod4xxx_types.h" -#else - #include "../zmod4xxx_types.h" -#endif - -/** \addtogroup RetCodes Return codes of the algorithm functions. - * @{ - */ - #define OAQ_2ND_GEN_OK (0) /**< everything okay */ - #define OAQ_2ND_GEN_STABILIZATION (1) /**< sensor in stabilization */ -/** @}*/ - -/** - * @brief Variables that describe the sensor or the algorithm state. - */ -typedef struct -{ - uint32_t sample_cnt; /**< Sample counter. Will satturate at 0xFFFFFFFF. */ - float smooth_rmox; - float gcda; /**< baseline conductance. */ - float o3_conc_ppb; - float o3_1h_ppb; - float o3_8h_ppb; -} oaq_2nd_gen_handle_t; - -/** - * @brief Variables that receive the algorithm outputs. - */ -typedef struct -{ - float rmox[8]; /**< MOx resistance. */ - float O3_conc_ppb; /**< O3_conc_ppb stands for the ozone concentration in part-per-billion */ - uint16_t - FAST_AQI; /**< FAST_AQI stands for a 1-minute average of the Air Quality Index according to the EPA standard based on ozone */ - uint16_t - EPA_AQI; /**< EPA_AQI stands for the Air Quality Index according to the EPA standard based on ozone. */ -} oaq_2nd_gen_results_t; - -/** - * @brief Variables that are needed for algorithm - * @param [in] adc_result Value from read_adc_result function - * @param [in] humidity_pct relative ambient humidity (%) - * @param [in] temperature_degc ambient temperature (degC) - */ -typedef struct -{ - uint8_t * adc_result; - float humidity_pct; - float temperature_degc; -} oaq_2nd_gen_inputs_t; - -/** - * @brief Initializes the OAQ algorithm. - * @param [out] handle Pointer to algorithm state variable. - * @return error code. - */ -int8_t init_oaq_2nd_gen(oaq_2nd_gen_handle_t * handle); - -/** - * @brief calculates OAQ results from present sample. - * @param [in] handle Pointer to algorithm state variable. - * @param [in] dev Pointer to the device. - * @param [in] algo_input Structure containing inputs required for algo calculation. - * @param [out] results Pointer for storing the algorithm results. - * @return error code. - */ -int8_t calc_oaq_2nd_gen(oaq_2nd_gen_handle_t * handle, - zmod4xxx_dev_t * dev, - const oaq_2nd_gen_inputs_t * algo_input, - oaq_2nd_gen_results_t * results); - - #ifdef __cplusplus -} - #endif - -#endif /* OAQ_2ND_GEN_H_ */ +#define OAQ_2ND_GEN_H_ + +#include "ulp_o3.h" + +// clang-format off +// #warning "The oaq_2nd_gen.h header is provided for backward compatibility only and will be removed in future revisions. Please use names defined in ulp_o3.h" +// clang-format on + +/* below definitions map the legacy OAQ 2nd Gen to ULP O3 names */ +#define OAQ_2ND_GEN_OK ULP_O3_OK +#define OAQ_2ND_GEN_STABILIZATION ULP_O3_STABILIZATION +#define OAQ_2ND_GEN_DAMAGE ULP_O3_DAMAGE +#define oaq_2nd_gen_handle_t ulp_o3_handle_t +#define oaq_2nd_gen_results_t ulp_o3_results_t +#define oaq_2nd_gen_inputs_t ulp_o3_inputs_t +#define init_oaq_2nd_gen init_ulp_o3 +#define calc_oaq_2nd_gen calc_ulp_o3 +#define g_zmod4510_oaq_2nd_gen_sensor_type g_zmod4510_ulp_o3_sensor_type + +#endif /* OAQ_2ND_GEN_H_ */ diff --git a/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/rm_zmod4510_oaq_2nd_gen.c b/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/rm_zmod4510_oaq_2nd_gen.c index ca127f470..e635fca01 100644 --- a/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/rm_zmod4510_oaq_2nd_gen.c +++ b/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/rm_zmod4510_oaq_2nd_gen.c @@ -74,6 +74,9 @@ static fsp_err_t rm_zmod4510_oaq_2nd_gen_rel_iaq_data_calculate(rm_zmod4xxx_ctrl static fsp_err_t rm_zmod4510_oaq_2nd_gen_pbaq_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, rm_zmod4xxx_pbaq_data_t * const p_zmod4xxx_data); +static fsp_err_t rm_zmod4510_oaq_2nd_gen_no2_o3_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data); static fsp_err_t rm_zmod4510_oaq_2nd_gen_close(rm_zmod4xxx_ctrl_t * const p_api_ctrl); static fsp_err_t rm_zmod4510_oaq_2nd_gen_device_error_check(rm_zmod4xxx_ctrl_t * const p_api_ctrl); @@ -97,6 +100,7 @@ rm_zmod4xxx_api_t const g_zmod4xxx_on_zmod4510_oaq_2nd_gen = .raqDataCalculate = rm_zmod4510_oaq_2nd_gen_raq_data_calculate, .relIaqDataCalculate = rm_zmod4510_oaq_2nd_gen_rel_iaq_data_calculate, .pbaqDataCalculate = rm_zmod4510_oaq_2nd_gen_pbaq_data_calculate, + .no2O3DataCalculate = rm_zmod4510_oaq_2nd_gen_no2_o3_data_calculate, .temperatureAndHumiditySet = rm_zmod4510_oaq_2nd_gen_temperature_and_humidity_set, .deviceErrorCheck = rm_zmod4510_oaq_2nd_gen_device_error_check, }; @@ -142,6 +146,7 @@ static fsp_err_t rm_zmod4510_oaq_2nd_gen_open (rm_zmod4xxx_ctrl_t * const p * @retval FSP_SUCCESS Successfully results are read. * @retval FSP_ERR_ASSERTION Null pointer passed as a parameter. * @retval FSP_ERR_SENSOR_IN_STABILIZATION Module is stabilizing. + * @retval FSP_ERR_SENSOR_INVALID_DATA Sensor probably damaged. Algorithm results may be incorrect. **********************************************************************************************************************/ static fsp_err_t rm_zmod4510_oaq_2nd_gen_data_calculate (rm_zmod4xxx_ctrl_t * const p_api_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, @@ -169,10 +174,12 @@ static fsp_err_t rm_zmod4510_oaq_2nd_gen_data_calculate (rm_zmod4xxx_ctrl_t * co p_zmod4xxx_data->rmox[i] = p_results->rmox[i]; } + p_zmod4xxx_data->temperature = p_results->temperature; p_zmod4xxx_data->ozone_concentration = p_results->O3_conc_ppb; p_zmod4xxx_data->fast_aqi = p_results->FAST_AQI; p_zmod4xxx_data->epa_aqi = p_results->EPA_AQI; FSP_ERROR_RETURN(OAQ_2ND_GEN_STABILIZATION != lib_err, FSP_ERR_SENSOR_IN_STABILIZATION); + FSP_ERROR_RETURN(OAQ_2ND_GEN_DAMAGE != lib_err, FSP_ERR_SENSOR_INVALID_DATA); return FSP_SUCCESS; } @@ -383,6 +390,22 @@ static fsp_err_t rm_zmod4510_oaq_2nd_gen_pbaq_data_calculate (rm_zmod4xxx_ctrl_t return FSP_ERR_UNSUPPORTED; } +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4510_oaq_2nd_gen_no2_o3_data_calculate (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_raw_data); + FSP_PARAMETER_NOT_USED(p_zmod4xxx_data); + + return FSP_ERR_UNSUPPORTED; +} + /*******************************************************************************************************************//** * @brief Unsupported API. * diff --git a/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/ulp_o3.h b/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/ulp_o3.h new file mode 100644 index 000000000..19803523c --- /dev/null +++ b/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/ulp_o3.h @@ -0,0 +1,102 @@ +/** + * @file ulp_o3.h + * @author Renesas Electronics Corporation + * @version 5.0.0 + * @brief This file contains the data structure definitions and + * the function definitions for the ULP O3 algorithm. + * @details The library contains an algorithm to calculate an ozone + * concentration and various air quality index values + * from the ZMOD4510 measurements. + */ + +#ifndef ULP_O3_H_ +#define ULP_O3_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if TEST_RM_ZMOD4XXX // For RA FSP test + #include "../../../../../fsp/src/rm_zmod4xxx/zmod4xxx_types.h" +#else + #include "../zmod4xxx_types.h" +#endif + +/** \addtogroup RetCodes Return codes of the algorithm functions. + * @{ + */ +#define ULP_O3_OK (0) /**< everything okay */ +#define ULP_O3_STABILIZATION (1) /**< sensor in stabilization */ +#define ULP_O3_DAMAGE (-102) /**< sensor damaged */ +/** @}*/ + +/** +* @brief Variables that describe the sensor or the algorithm state. +*/ +// clang-format off +typedef struct { + uint32_t sample_cnt; /**< Sample counter. Will satturate at 0xFFFFFFFF. */ + float smooth_rmox; + float gcda; /**< baseline conductance. */ + float o3_conc_ppb; + float o3_1h_ppb; + float o3_8h_ppb; +} ulp_o3_handle_t; +// clang-format on + +/** +* @brief Variables that receive the algorithm outputs. +*/ +// clang-format off +typedef struct { + float rmox[8]; /**< MOx resistance. */ + float temperature; /**< Temperature (degC) used for ambient compensation */ + float O3_conc_ppb; /**< O3_conc_ppb stands for the ozone concentration + in part-per-billion */ + uint16_t FAST_AQI; /**< FAST_AQI stands for a 1-minute average of the + Air Quality Index according to the EPA + standard based on ozone */ + uint16_t EPA_AQI; /**< EPA_AQI stands for the Air Quality Index + according to the EPA standard based on ozone.*/ +} ulp_o3_results_t; +// clang-format on + +/** +* @brief Variables that are needed for algorithm + * @param [in] adc_result Value from read_adc_result function + * @param [in] humidity_pct relative ambient humidity (%) + * @param [in] temperature_degc ambient temperature (degC) +*/ +typedef struct { + uint8_t *adc_result; + float humidity_pct; + float temperature_degc; +} ulp_o3_inputs_t; + +/** + * @brief Initializes the ULP O3 algorithm. + * @param [out] handle Pointer to algorithm state variable. + * @return error code. +*/ +int8_t init_ulp_o3(ulp_o3_handle_t *handle); + +/** + * @brief calculates results from present sample. + * @param [in] handle Pointer to algorithm state variable. + * @param [in] dev Pointer to the device. + * @param [in] algo_input Structure containing inputs required for algo calculation. + * @param [out] results Pointer for storing the algorithm results. + * @return error code. + */ +int8_t calc_ulp_o3(ulp_o3_handle_t *handle, zmod4xxx_dev_t *dev, + const ulp_o3_inputs_t *algo_input, + ulp_o3_results_t *results); + +#ifdef __cplusplus +} +#endif + +#endif /* ULP_O3_H_ */ diff --git a/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/zmod4510_config_oaq2.h b/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/zmod4510_config_oaq2.h index 29e394422..c42a6fe9e 100644 --- a/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/zmod4510_config_oaq2.h +++ b/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/zmod4510_config_oaq2.h @@ -8,104 +8,12 @@ * @file zmod4510_config_oaq2.h * @brief This is the configuration for ZMOD4510 module - oaq_2nd_gen library * @author Renesas Electronics Corporation - * @version 4.0.0 + * @version 5.0.0 */ #ifndef _ZMOD4510_CONFIG_OAQ_2ND_GEN_H_ #define _ZMOD4510_CONFIG_OAQ_2ND_GEN_H_ -#include - -#if TEST_RM_ZMOD4XXX // For RA FSP test - #include "../../../../../fsp/src/rm_zmod4xxx/zmod4xxx_types.h" -#else - #include "../zmod4xxx_types.h" -#endif - -#define INIT 0 -#define MEASUREMENT 1 - -/**********************************/ -/* < Define product ID > */ -#define ZMOD4510_PID 0x6320 - -/**********************************/ -/* < Define I2C slase address > */ -#define ZMOD4510_I2C_ADDR 0x33 - -/**********************************/ -/* < Define product data length > */ -#define ZMOD4510_PROD_DATA_LEN 10 - -/*************************************/ -/* < Define ADC result data length > */ -#define ZMOD4510_ADC_DATA_LEN 18 - -// time between samples -#define ZMOD4510_OAQ2_SAMPLE_TIME (2000U) - -// REMOVE Sequencer adresses -#define ZMOD4XXX_H_ADDR 0x40 -#define ZMOD4XXX_D_ADDR 0x50 -#define ZMOD4XXX_M_ADDR 0x60 -#define ZMOD4XXX_S_ADDR 0x68 - -// clang-format off -static uint8_t data_set_4510_init[] = -{ -// REMOVE heater - 0x00, 0x50, - -// REMOVE delay , measurement - 0x00, 0x28,0xC3, 0xE3, - -// REMOVE sequencer - 0x00, 0x00,0x80, 0x40 -}; - -static uint8_t data_set_4510_oaq_2nd_gen[] = -{ -// REMOVE this implements the ULP_NN_05.xml sequence -// REMOVE heater - 0x00, 0x50, 0xFE, 0x70, - -// REMOVE delay - 0x00, 0x10, - -// REMOVE measurement - 0x23, 0x03, - -// REMOVE sequencer - 0x00, 0x00, 0x06, 0x41, - 0x06, 0x41, 0x06, 0x41, - 0x06, 0x41, 0x06, 0x41, - 0x06, 0x41, 0x06, 0x41, - 0x86, 0x41 -}; - -// clang-format on -zmod4xxx_conf g_zmod4510_oaq_2nd_gen_sensor_type[] = -{ - [INIT] = - { - .start = 0x80, - .h = {.addr = ZMOD4XXX_H_ADDR, .len = 2, .data_buf = &data_set_4510_init[0] }, - .d = {.addr = ZMOD4XXX_D_ADDR, .len = 2, .data_buf = &data_set_4510_init[2] }, - .m = {.addr = ZMOD4XXX_M_ADDR, .len = 2, .data_buf = &data_set_4510_init[4] }, - .s = {.addr = ZMOD4XXX_S_ADDR, .len = 4, .data_buf = &data_set_4510_init[6] }, - .r = {.addr = 0x97, .len = 4}, - }, - - [MEASUREMENT] = - { - .start = 0x80, - .h = {.addr = ZMOD4XXX_H_ADDR, .len = 4, .data_buf = &data_set_4510_oaq_2nd_gen[0]}, - .d = {.addr = ZMOD4XXX_D_ADDR, .len = 2, .data_buf = &data_set_4510_oaq_2nd_gen[4]}, - .m = {.addr = ZMOD4XXX_M_ADDR, .len = 2, .data_buf = &data_set_4510_oaq_2nd_gen[6]}, - .s = {.addr = ZMOD4XXX_S_ADDR, .len = 18, .data_buf = &data_set_4510_oaq_2nd_gen[8]}, - .r = {.addr = 0x97, .len = 18}, - .prod_data_len = ZMOD4510_PROD_DATA_LEN, - }, -}; +#include "zmod4510_config_ulp_o3.h" #endif // _ZMOD4510_CONFIG_OAQ_2ND_GEN_H_ diff --git a/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/zmod4510_config_ulp_o3.h b/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/zmod4510_config_ulp_o3.h new file mode 100644 index 000000000..dd3d974bd --- /dev/null +++ b/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/zmod4510_config_ulp_o3.h @@ -0,0 +1,95 @@ +/** + * @file zmod4510_config_ulp_o3.h + * @brief This is the configuration for ZMOD4510 module - ulp_o3 library + * @author Renesas Electronics Corporation + * @version 5.0.0 + */ + +#ifndef _ZMOD4510_CONFIG_ULP_O3_H_ +#define _ZMOD4510_CONFIG_ULP_O3_H_ + +#include + +#if TEST_RM_ZMOD4XXX // For RA FSP test + #include "../../../../../fsp/src/rm_zmod4xxx/zmod4xxx_types.h" +#else + #include "../zmod4xxx_types.h" +#endif + +#define INIT 0 +#define MEASUREMENT 1 + +/**********************************/ +/* < Define product ID > */ +#define ZMOD4510_PID 0x6320 + +/**********************************/ +/* < Define I2C slase address > */ +#define ZMOD4510_I2C_ADDR 0x33 + +/**********************************/ +/* < Define product data length > */ +#define ZMOD4510_PROD_DATA_LEN 10 + +/*************************************/ +/* < Define ADC result data length > */ +#define ZMOD4510_ADC_DATA_LEN 18 + +// time between samples +#define ZMOD4510_ULP_O3_SAMPLE_TIME (2000U) + +// REMOVE Sequencer adresses +#define ZMOD4XXX_H_ADDR 0x40 +#define ZMOD4XXX_D_ADDR 0x50 +#define ZMOD4XXX_M_ADDR 0x60 +#define ZMOD4XXX_S_ADDR 0x68 + +// clang-format off +static uint8_t data_set_4510_init[] = { +// REMOVE heater + 0x00, 0x50, +// REMOVE delay , measurement + 0x00, 0x28, 0xC3, 0xE3, +// REMOVE sequencer + 0x00, 0x00, 0x80, 0x40}; + +static uint8_t data_set_4510_ulp_o3[] = { +// REMOVE this implements the ULP_NN_05.xml sequence +// REMOVE heater + 0x00, 0x50, 0xFE, 0x70, +// REMOVE delay + 0x00, 0x10, +// REMOVE measurement + 0x23, 0x03, +// REMOVE sequencer + 0x00, 0x00, 0x06, 0x41, + 0x06, 0x41, 0x06, 0x41, + 0x06, 0x41, 0x06, 0x41, + 0x06, 0x41, 0x06, 0x41, + 0x86, 0x41 + }; + +// clang-format on +zmod4xxx_conf g_zmod4510_ulp_o3_sensor_type[] = +{ + [INIT] = { + .start = 0x80, + .h = { .addr = ZMOD4XXX_H_ADDR, .len = 2, .data_buf = &data_set_4510_init[0]}, + .d = { .addr = ZMOD4XXX_D_ADDR, .len = 2, .data_buf = &data_set_4510_init[2]}, + .m = { .addr = ZMOD4XXX_M_ADDR, .len = 2, .data_buf = &data_set_4510_init[4]}, + .s = { .addr = ZMOD4XXX_S_ADDR, .len = 4, .data_buf = &data_set_4510_init[6]}, + .r = { .addr = 0x97, .len = 4}, + }, + + [MEASUREMENT] = { + .start = 0x80, + .h = {.addr = ZMOD4XXX_H_ADDR, .len = 4, .data_buf = &data_set_4510_ulp_o3[0]}, + .d = {.addr = ZMOD4XXX_D_ADDR, .len = 2, .data_buf = &data_set_4510_ulp_o3[4]}, + .m = {.addr = ZMOD4XXX_M_ADDR, .len = 2, .data_buf = &data_set_4510_ulp_o3[6]}, + .s = {.addr = ZMOD4XXX_S_ADDR, .len = 18, .data_buf = &data_set_4510_ulp_o3[8]}, + .r = {.addr = 0x97, .len = 18}, + .prod_data_len = ZMOD4510_PROD_DATA_LEN, + }, +}; + +#endif //_ZMOD4510_CONFIG_ULP_O3_H_ diff --git a/ra/fsp/src/rm_zmod4xxx/odor/rm_zmod4410_odor.c b/ra/fsp/src/rm_zmod4xxx/odor/rm_zmod4410_odor.c index 51c1be09a..e817a67c3 100644 --- a/ra/fsp/src/rm_zmod4xxx/odor/rm_zmod4410_odor.c +++ b/ra/fsp/src/rm_zmod4xxx/odor/rm_zmod4410_odor.c @@ -81,6 +81,9 @@ static fsp_err_t rm_zmod4410_odor_rel_iaq_data_calculate(rm_zmod4xxx_ctrl_t * co static fsp_err_t rm_zmod4410_odor_pbaq_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, rm_zmod4xxx_pbaq_data_t * const p_zmod4xxx_data); +static fsp_err_t rm_zmod4410_odor_no2_o3_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data); static fsp_err_t rm_zmod4410_odor_close(rm_zmod4xxx_ctrl_t * const p_api_ctrl); static fsp_err_t rm_zmod4410_odor_device_error_check(rm_zmod4xxx_ctrl_t * const p_api_ctrl); static fsp_err_t rm_zmod4410_odor_calc_rmox(rm_zmod4xxx_instance_ctrl_t * const p_ctrl, @@ -107,6 +110,7 @@ rm_zmod4xxx_api_t const g_zmod4xxx_on_zmod4410_odor = .raqDataCalculate = rm_zmod4410_odor_raq_data_calculate, .relIaqDataCalculate = rm_zmod4410_odor_rel_iaq_data_calculate, .pbaqDataCalculate = rm_zmod4410_odor_pbaq_data_calculate, + .no2O3DataCalculate = rm_zmod4410_odor_no2_o3_data_calculate, .temperatureAndHumiditySet = rm_zmod4410_odor_temperature_and_humidity_set, .deviceErrorCheck = rm_zmod4410_odor_device_error_check, }; @@ -383,6 +387,22 @@ static fsp_err_t rm_zmod4410_odor_pbaq_data_calculate (rm_zmod4xxx_ctrl_t * cons return FSP_ERR_UNSUPPORTED; } +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4410_odor_no2_o3_data_calculate (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_raw_data); + FSP_PARAMETER_NOT_USED(p_zmod4xxx_data); + + return FSP_ERR_UNSUPPORTED; +} + /*******************************************************************************************************************//** * @brief Unsupported API. * diff --git a/ra/fsp/src/rm_zmod4xxx/pbaq/rm_zmod4410_pbaq.c b/ra/fsp/src/rm_zmod4xxx/pbaq/rm_zmod4410_pbaq.c index 18b219a28..75499f6ca 100644 --- a/ra/fsp/src/rm_zmod4xxx/pbaq/rm_zmod4410_pbaq.c +++ b/ra/fsp/src/rm_zmod4xxx/pbaq/rm_zmod4410_pbaq.c @@ -73,6 +73,9 @@ static fsp_err_t rm_zmod4410_pbaq_rel_iaq_data_calculate(rm_zmod4xxx_ctrl_t * co static fsp_err_t rm_zmod4410_pbaq_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, rm_zmod4xxx_pbaq_data_t * const p_zmod4xxx_data); +static fsp_err_t rm_zmod4410_pbaq_no2_o3_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data); static fsp_err_t rm_zmod4410_pbaq_close(rm_zmod4xxx_ctrl_t * const p_api_ctrl); static fsp_err_t rm_zmod4410_pbaq_device_error_check(rm_zmod4xxx_ctrl_t * const p_api_ctrl); @@ -96,6 +99,7 @@ rm_zmod4xxx_api_t const g_zmod4xxx_on_zmod4410_pbaq = .raqDataCalculate = rm_zmod4410_pbaq_raq_data_calculate, .relIaqDataCalculate = rm_zmod4410_pbaq_rel_iaq_data_calculate, .pbaqDataCalculate = rm_zmod4410_pbaq_data_calculate, + .no2O3DataCalculate = rm_zmod4410_pbaq_no2_o3_data_calculate, .temperatureAndHumiditySet = rm_zmod4410_pbaq_temperature_and_humidity_set, .deviceErrorCheck = rm_zmod4410_pbaq_device_error_check, }; @@ -377,6 +381,22 @@ static fsp_err_t rm_zmod4410_pbaq_rel_iaq_data_calculate (rm_zmod4xxx_ctrl_t * c return FSP_ERR_UNSUPPORTED; } +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4410_pbaq_no2_o3_data_calculate (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_raw_data); + FSP_PARAMETER_NOT_USED(p_zmod4xxx_data); + + return FSP_ERR_UNSUPPORTED; +} + /*******************************************************************************************************************//** * @brief Unsupported API. * diff --git a/ra/fsp/src/rm_zmod4xxx/raq/rm_zmod4450_raq.c b/ra/fsp/src/rm_zmod4xxx/raq/rm_zmod4450_raq.c index 3f9e18f0a..66d3f6a6e 100644 --- a/ra/fsp/src/rm_zmod4xxx/raq/rm_zmod4450_raq.c +++ b/ra/fsp/src/rm_zmod4xxx/raq/rm_zmod4450_raq.c @@ -80,6 +80,9 @@ static fsp_err_t rm_zmod4450_raq_rel_iaq_data_calculate(rm_zmod4xxx_ctrl_t * con static fsp_err_t rm_zmod4450_raq_pbaq_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, rm_zmod4xxx_pbaq_data_t * const p_zmod4xxx_data); +static fsp_err_t rm_zmod4450_raq_no2_o3_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data); static fsp_err_t rm_zmod4450_raq_close(rm_zmod4xxx_ctrl_t * const p_api_ctrl); static fsp_err_t rm_zmod4410_raq_device_error_check(rm_zmod4xxx_ctrl_t * const p_api_ctrl); @@ -107,6 +110,7 @@ rm_zmod4xxx_api_t const g_zmod4xxx_on_zmod4450_raq = .raqDataCalculate = rm_zmod4450_raq_data_calculate, .relIaqDataCalculate = rm_zmod4450_raq_rel_iaq_data_calculate, .pbaqDataCalculate = rm_zmod4450_raq_pbaq_data_calculate, + .no2O3DataCalculate = rm_zmod4450_raq_no2_o3_data_calculate, .temperatureAndHumiditySet = rm_zmod4450_raq_temperature_and_humidity_set, .deviceErrorCheck = rm_zmod4410_raq_device_error_check, }; @@ -382,6 +386,22 @@ static fsp_err_t rm_zmod4450_raq_pbaq_data_calculate (rm_zmod4xxx_ctrl_t * const return FSP_ERR_UNSUPPORTED; } +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4450_raq_no2_o3_data_calculate (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_raw_data); + FSP_PARAMETER_NOT_USED(p_zmod4xxx_data); + + return FSP_ERR_UNSUPPORTED; +} + /*******************************************************************************************************************//** * @brief Unsupported API. * diff --git a/ra/fsp/src/rm_zmod4xxx/rel_iaq/rm_zmod4410_rel_iaq.c b/ra/fsp/src/rm_zmod4xxx/rel_iaq/rm_zmod4410_rel_iaq.c index 57d6967e3..f44acdcc9 100644 --- a/ra/fsp/src/rm_zmod4xxx/rel_iaq/rm_zmod4410_rel_iaq.c +++ b/ra/fsp/src/rm_zmod4xxx/rel_iaq/rm_zmod4410_rel_iaq.c @@ -73,6 +73,9 @@ static fsp_err_t rm_zmod4410_rel_iaq_data_calculate(rm_zmod4xxx_ctrl_t * const static fsp_err_t rm_zmod4410_rel_iaq_pbaq_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, rm_zmod4xxx_pbaq_data_t * const p_zmod4xxx_data); +static fsp_err_t rm_zmod4410_rel_iaq_no2_o3_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data); static fsp_err_t rm_zmod4410_rel_iaq_close(rm_zmod4xxx_ctrl_t * const p_api_ctrl); static fsp_err_t rm_zmod4410_rel_iaq_device_error_check(rm_zmod4xxx_ctrl_t * const p_api_ctrl); @@ -96,6 +99,7 @@ rm_zmod4xxx_api_t const g_zmod4xxx_on_zmod4410_rel_iaq = .raqDataCalculate = rm_zmod4410_rel_iaq_raq_data_calculate, .relIaqDataCalculate = rm_zmod4410_rel_iaq_data_calculate, .pbaqDataCalculate = rm_zmod4410_rel_iaq_pbaq_data_calculate, + .no2O3DataCalculate = rm_zmod4410_rel_iaq_no2_o3_data_calculate, .temperatureAndHumiditySet = rm_zmod4410_rel_iaq_temperature_and_humidity_set, .deviceErrorCheck = rm_zmod4410_rel_iaq_device_error_check, }; @@ -372,6 +376,22 @@ static fsp_err_t rm_zmod4410_rel_iaq_pbaq_data_calculate (rm_zmod4xxx_ctrl_t * c return FSP_ERR_UNSUPPORTED; } +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4410_rel_iaq_no2_o3_data_calculate (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_raw_data); + FSP_PARAMETER_NOT_USED(p_zmod4xxx_data); + + return FSP_ERR_UNSUPPORTED; +} + /*******************************************************************************************************************//** * @brief Unsupported API. * diff --git a/ra/fsp/src/rm_zmod4xxx/rel_iaq_ulp/rm_zmod4410_rel_iaq_ulp.c b/ra/fsp/src/rm_zmod4xxx/rel_iaq_ulp/rm_zmod4410_rel_iaq_ulp.c index 5f5ad887d..584b5b7de 100644 --- a/ra/fsp/src/rm_zmod4xxx/rel_iaq_ulp/rm_zmod4410_rel_iaq_ulp.c +++ b/ra/fsp/src/rm_zmod4xxx/rel_iaq_ulp/rm_zmod4410_rel_iaq_ulp.c @@ -74,6 +74,9 @@ static fsp_err_t rm_zmod4410_rel_iaq_ulp_data_calculate(rm_zmod4xxx_ctrl_t * con static fsp_err_t rm_zmod4410_rel_iaq_ulp_pbaq_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, rm_zmod4xxx_pbaq_data_t * const p_zmod4xxx_data); +static fsp_err_t rm_zmod4410_rel_iaq_ulp_no2_o3_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data); static fsp_err_t rm_zmod4410_rel_iaq_ulp_close(rm_zmod4xxx_ctrl_t * const p_api_ctrl); static fsp_err_t rm_zmod4410_rel_iaq_ulp_device_error_check(rm_zmod4xxx_ctrl_t * const p_api_ctrl); @@ -97,6 +100,7 @@ rm_zmod4xxx_api_t const g_zmod4xxx_on_zmod4410_rel_iaq_ulp = .raqDataCalculate = rm_zmod4410_rel_iaq_ulp_raq_data_calculate, .relIaqDataCalculate = rm_zmod4410_rel_iaq_ulp_data_calculate, .pbaqDataCalculate = rm_zmod4410_rel_iaq_ulp_pbaq_data_calculate, + .no2O3DataCalculate = rm_zmod4410_rel_iaq_ulp_no2_o3_data_calculate, .temperatureAndHumiditySet = rm_zmod4410_rel_iaq_ulp_temperature_and_humidity_set, .deviceErrorCheck = rm_zmod4410_rel_iaq_ulp_device_error_check, }; @@ -374,6 +378,22 @@ static fsp_err_t rm_zmod4410_rel_iaq_ulp_pbaq_data_calculate (rm_zmod4xxx_ctrl_t return FSP_ERR_UNSUPPORTED; } +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4410_rel_iaq_ulp_no2_o3_data_calculate (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_raw_data); + FSP_PARAMETER_NOT_USED(p_zmod4xxx_data); + + return FSP_ERR_UNSUPPORTED; +} + /*******************************************************************************************************************//** * @brief Unsupported API. * diff --git a/ra/fsp/src/rm_zmod4xxx/rm_zmod4xxx.c b/ra/fsp/src/rm_zmod4xxx/rm_zmod4xxx.c index eb68e491b..4477b2b89 100644 --- a/ra/fsp/src/rm_zmod4xxx/rm_zmod4xxx.c +++ b/ra/fsp/src/rm_zmod4xxx/rm_zmod4xxx.c @@ -92,6 +92,7 @@ rm_zmod4xxx_api_t const g_zmod4xxx_on_zmod4xxx = .raqDataCalculate = RM_ZMOD4XXX_RaqDataCalculate, .relIaqDataCalculate = RM_ZMOD4XXX_RelIaqDataCalculate, .pbaqDataCalculate = RM_ZMOD4XXX_PbaqDataCalculate, + .no2O3DataCalculate = RM_ZMOD4XXX_No2O3DataCalculate, .temperatureAndHumiditySet = RM_ZMOD4XXX_TemperatureAndHumiditySet, .deviceErrorCheck = RM_ZMOD4XXX_DeviceErrorCheck, }; @@ -675,6 +676,43 @@ fsp_err_t RM_ZMOD4XXX_PbaqDataCalculate (rm_zmod4xxx_ctrl_t * const p_api_c return FSP_SUCCESS; } +/*******************************************************************************************************************//** + * @brief This function should be called when measurement finishes. To check measurement status either polling or + * busy/interrupt pin can be used. + * Implements @ref rm_zmod4xxx_api_t::no2O3DataCalculate + * + * @retval FSP_SUCCESS Successfully results are read. + * @retval FSP_ERR_ASSERTION Null pointer passed as a parameter or library internal error occured. + * @retval FSP_ERR_NOT_OPEN Module is not opened configured. + * @retval FSP_ERR_SENSOR_IN_STABILIZATION Module is stabilizing. + * @retval FSP_ERR_SENSOR_INVALID_DATA Sensor probably damaged. Algorithm results may be incorrect. + **********************************************************************************************************************/ +fsp_err_t RM_ZMOD4XXX_No2O3DataCalculate (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data) +{ + fsp_err_t err = FSP_SUCCESS; rm_zmod4xxx_instance_ctrl_t * p_ctrl = (rm_zmod4xxx_instance_ctrl_t *) p_api_ctrl; + rm_zmod4xxx_lib_extended_cfg_t * p_lib; + +#if RM_ZMOD4XXX_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_raw_data); + FSP_ASSERT(NULL != p_zmod4xxx_data); + FSP_ERROR_RETURN(RM_ZMOD4XXX_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Set ZMOD4XXX library specific */ + p_lib = p_ctrl->p_zmod4xxx_lib; + + /* Calculate NO2 O3 data */ + err = p_lib->p_api->no2O3DataCalculate(p_ctrl, p_raw_data, p_zmod4xxx_data); + FSP_ERROR_RETURN(FSP_ERR_ASSERTION != err, err); + FSP_ERROR_RETURN(FSP_ERR_SENSOR_IN_STABILIZATION != err, err); + FSP_ERROR_RETURN(FSP_ERR_SENSOR_INVALID_DATA != err, err); + + return err; +} + /*******************************************************************************************************************//** * @brief This function is valid only for OAQ_2nd_Gen and IAQ_2nd_Gen_ULP. This function should be called before DataCalculate. * Humidity and temperature measurements are needed for ambient compensation. diff --git a/ra/fsp/src/rm_zmod4xxx/sulfur_odor/rm_zmod4410_sulfur_odor.c b/ra/fsp/src/rm_zmod4xxx/sulfur_odor/rm_zmod4410_sulfur_odor.c index b35443140..70377a803 100644 --- a/ra/fsp/src/rm_zmod4xxx/sulfur_odor/rm_zmod4410_sulfur_odor.c +++ b/ra/fsp/src/rm_zmod4xxx/sulfur_odor/rm_zmod4410_sulfur_odor.c @@ -74,6 +74,9 @@ static fsp_err_t rm_zmod4410_sulfur_odor_rel_iaq_data_calculate(rm_zmod4xxx_ctrl static fsp_err_t rm_zmod4410_sulfur_odor_pbaq_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, rm_zmod4xxx_pbaq_data_t * const p_zmod4xxx_data); +static fsp_err_t rm_zmod4410_sulfur_odor_no2_o3_data_calculate(rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data); static fsp_err_t rm_zmod4410_sulfur_odor_close(rm_zmod4xxx_ctrl_t * const p_api_ctrl); static fsp_err_t rm_zmod4410_sulfur_odor_device_error_check(rm_zmod4xxx_ctrl_t * const p_api_ctrl); @@ -97,6 +100,7 @@ rm_zmod4xxx_api_t const g_zmod4xxx_on_zmod4410_sulfur_odor = .raqDataCalculate = rm_zmod4410_sulfur_odor_raq_data_calculate, .relIaqDataCalculate = rm_zmod4410_sulfur_odor_rel_iaq_data_calculate, .pbaqDataCalculate = rm_zmod4410_sulfur_odor_pbaq_data_calculate, + .no2O3DataCalculate = rm_zmod4410_sulfur_odor_no2_o3_data_calculate, .temperatureAndHumiditySet = rm_zmod4410_sulfur_odor_temperature_and_humidity_set, .deviceErrorCheck = rm_zmod4410_sulfur_odor_device_error_check, }; @@ -380,6 +384,22 @@ static fsp_err_t rm_zmod4410_sulfur_odor_pbaq_data_calculate (rm_zmod4xxx_ctrl_t return FSP_ERR_UNSUPPORTED; } +/*******************************************************************************************************************//** + * @brief Unsupported API. + * + * @retval FSP_ERR_UNSUPPORTED Operation mode is not supported. + **********************************************************************************************************************/ +static fsp_err_t rm_zmod4410_sulfur_odor_no2_o3_data_calculate (rm_zmod4xxx_ctrl_t * const p_api_ctrl, + rm_zmod4xxx_raw_data_t * const p_raw_data, + rm_zmod4xxx_no2_o3_data_t * const p_zmod4xxx_data) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_raw_data); + FSP_PARAMETER_NOT_USED(p_zmod4xxx_data); + + return FSP_ERR_UNSUPPORTED; +} + /*******************************************************************************************************************//** * @brief Unsupported API. *