From 6e985de6ceb64eb32325cd0b488abe58a01c30b7 Mon Sep 17 00:00:00 2001
From: Vadim Kuznetsov <ra3xdh@gmail.com>
Date: Mon, 30 Dec 2024 20:51:15 +0300
Subject: [PATCH 1/3] Fix crash when try to simulate digital schematic with
 subcircuit

---
 qucs/components/subcircuit.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/qucs/components/subcircuit.cpp b/qucs/components/subcircuit.cpp
index 1bb0e92d8..87bfa72ec 100644
--- a/qucs/components/subcircuit.cpp
+++ b/qucs/components/subcircuit.cpp
@@ -244,7 +244,7 @@ QString Subcircuit::vhdlCode(int) {
   QString s = "  " + Name + ": entity Sub_" + misc::properName(f);
 
   // output all user defined properties
-  if (Props.at(1) != nullptr) {
+  if (Props.count() > 1) {
     s += " generic map (";
     s += Props.at(1)->Value;
     for (qsizetype i = 2; i < Props.size(); i++) {
@@ -274,7 +274,7 @@ QString Subcircuit::verilogCode(int) {
   QString s = "  Sub_" + misc::properName(f);
 
   // output all user defined properties
-  if (Props.at(1) != nullptr) {
+  if (Props.count() > 1) {
     s += " #(";
     s += misc::Verilog_Param(Props.at(1)->Value);
     for (qsizetype i = 2; i < Props.size(); i++)

From 55428164d069f631895e84f8762385759d95f832 Mon Sep 17 00:00:00 2001
From: Vadim Kuznetsov <ra3xdh@gmail.com>
Date: Mon, 30 Dec 2024 21:00:39 +0300
Subject: [PATCH 2/3] Fix writing digital netlists with subcircuits

---
 qucs/schematic_file.cpp | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/qucs/schematic_file.cpp b/qucs/schematic_file.cpp
index e730a8d4e..b088cd710 100644
--- a/qucs/schematic_file.cpp
+++ b/qucs/schematic_file.cpp
@@ -1869,7 +1869,8 @@ void Schematic::createSubNetlistPlain(QTextStream *stream, QPlainTextEdit *ErrTe
 
 
 
-  if (QucsSettings.DefaultSimulator == spicecompat::simQucsator) {
+  if (QucsSettings.DefaultSimulator == spicecompat::simQucsator ||
+      !a_isAnalog) {
 
         if(a_isAnalog) {
             // ..... analog subcircuit ...................................
@@ -2054,7 +2055,8 @@ bool Schematic::createSubNetlist(QTextStream *stream, int& countInit,
 
   // Emit subcircuit components
    createSubNetlistPlain(stream, ErrText, NumPorts);
-   if (QucsSettings.DefaultSimulator != spicecompat::simQucsator) {
+   if (QucsSettings.DefaultSimulator != spicecompat::simQucsator &&
+       a_isAnalog) {
       AbstractSpiceKernel *kern = new AbstractSpiceKernel(this);
       QStringList err_lst;
       if (!kern->checkSchematic(err_lst)) {

From 7ffbcc58243719d58b8948e27a3c70e7fcfadbd0 Mon Sep 17 00:00:00 2001
From: Vadim Kuznetsov <ra3xdh@gmail.com>
Date: Mon, 30 Dec 2024 21:13:41 +0300
Subject: [PATCH 3/3] Fix GHDL simulation for subcircuits

---
 qucs/schematic_file.cpp | 23 ++++++++++++++++-------
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/qucs/schematic_file.cpp b/qucs/schematic_file.cpp
index b088cd710..67163e8c7 100644
--- a/qucs/schematic_file.cpp
+++ b/qucs/schematic_file.cpp
@@ -1957,26 +1957,35 @@ void Schematic::createSubNetlistPlain(QTextStream *stream, QPlainTextEdit *ErrTe
             } else {
               // ..... digital subcircuit ...................................
               (*tstream) << VHDL_LIBRARIES;
-              (*tstream) << "entity Sub_" << Type << " is\n"
-                        << " port ("
-                        << SubcircuitPortNames.join(";\n ") << ");\n";
+              (*tstream) << "entity Sub_" << Type << " is\n";
 
-              for(pi = a_SymbolPaints.first(); pi != 0; pi = a_SymbolPaints.next())
+              QString generic_str;
+              for(pi = a_SymbolPaints.first(); pi != 0; pi = a_SymbolPaints.next()) {
                 if(pi->Name == ".ID ") {
                   ID_Text *pid = (ID_Text*)pi;
                   QList<SubParameter *>::const_iterator it;
 
-                  (*tstream) << " generic (";
+
 
                   for(it = pid->Parameter.constBegin(); it != pid->Parameter.constEnd(); it++) {
                     s = (*it)->Name;
                     QString t = (*it)->Type.isEmpty() ? "real" : (*it)->Type;
-                    (*tstream) << s.replace("=", " : "+t+" := ") << ";\n ";
+                    generic_str += s.replace("=", " : "+t+" := ") + ";\n ";
                   }
 
-                  (*tstream) << ");\n";
+
                   break;
                 }
+              }
+              if (!generic_str.isEmpty()) {
+                (*tstream) << " generic (";
+                (*tstream) << generic_str;
+                (*tstream) << ");\n";
+              }
+
+              (*tstream) << " port ("
+                        << SubcircuitPortNames.join(";\n ") << ");\n";
+
 
               (*tstream) << "end entity;\n"
                           << "use work.all;\n"