diff --git a/bhv/cv32e40x_wrapper.sv b/bhv/cv32e40x_wrapper.sv index 4bedfd33..a3c650e2 100644 --- a/bhv/cv32e40x_wrapper.sv +++ b/bhv/cv32e40x_wrapper.sv @@ -614,7 +614,7 @@ endgenerate .wpt_match_wb_i ( core_i.wb_stage_i.wpt_match_wb_o ), .mpu_status_wb_i ( core_i.wb_stage_i.mpu_status_wb_o ), .align_status_wb_i ( core_i.wb_stage_i.align_status_wb_o ), - .csr_mscratchcsw_in_wb_i ( core_i.cs_registers_i.mscratchcsw_in_wb ), + .csr_mscratchcsw_in_wb_i ( 1'b0 /* Not implemented in cv32e40x */ ), .csr_mscratchcswl_in_wb_i ( core_i.cs_registers_i.mscratchcswl_in_wb ), .csr_mnxti_in_wb_i ( core_i.cs_registers_i.mnxti_in_wb ), @@ -682,9 +682,9 @@ endgenerate .csr_mintthresh_n_i ( core_i.cs_registers_i.mintthresh_n ), .csr_mintthresh_q_i ( core_i.cs_registers_i.mintthresh_rdata ), .csr_mintthresh_we_i ( core_i.cs_registers_i.mintthresh_we ), - .csr_mscratchcsw_n_i ( core_i.cs_registers_i.mscratchcsw_n ), - .csr_mscratchcsw_q_i ( core_i.cs_registers_i.mscratchcsw_rdata ), - .csr_mscratchcsw_we_i ( core_i.cs_registers_i.mscratchcsw_we ), + .csr_mscratchcsw_n_i ( 32'd0 /* Not implemented in cv32e40x */ ), + .csr_mscratchcsw_q_i ( 32'd0 /* Not implemented in cv32e40x */ ), + .csr_mscratchcsw_we_i ( 1'b0 /* Not implemented in cv32e40x */ ), .csr_mscratchcswl_n_i ( core_i.cs_registers_i.mscratchcswl_n ), .csr_mscratchcswl_q_i ( core_i.cs_registers_i.mscratchcswl_rdata ), .csr_mscratchcswl_we_i ( core_i.cs_registers_i.mscratchcswl_we ), diff --git a/rtl/cv32e40x_controller_bypass.sv b/rtl/cv32e40x_controller_bypass.sv index bca531c6..fd04c42d 100644 --- a/rtl/cv32e40x_controller_bypass.sv +++ b/rtl/cv32e40x_controller_bypass.sv @@ -260,7 +260,7 @@ module cv32e40x_controller_bypass import cv32e40x_pkg::*; // 2: or an explicit CSR read is in EX while any implicit write is in WB (conservative stall) // 3: or an explicit CSR read is in EX while an explicit CSR write to the same CSR is in WB. (exact stall) // - // Cases like accesses to mscratchcsw[l] and mnxti which reads multiple CSRs are handled by 1 above. + // Cases like accesses to mscratchcswl and mnxti which reads multiple CSRs are handled by 1 above. if ((csr_hz_i.impl_re_ex && csr_write_in_wb) || (id_ex_pipe_i.csr_en && id_ex_pipe_i.instr_valid && csr_impl_write_in_wb) || csr_expl_hz_ex) begin diff --git a/rtl/cv32e40x_cs_registers.sv b/rtl/cv32e40x_cs_registers.sv index 00318e3b..16e4cf22 100644 --- a/rtl/cv32e40x_cs_registers.sv +++ b/rtl/cv32e40x_cs_registers.sv @@ -216,9 +216,6 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; logic [31:0] mintthresh_q, mintthresh_n, mintthresh_rdata; logic mintthresh_we; - logic [31:0] mscratchcsw_n, mscratchcsw_rdata; - logic mscratchcsw_we; - logic [31:0] mscratchcswl_n, mscratchcswl_rdata; logic mscratchcswl_we; @@ -277,7 +274,6 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; logic [31:0] mhpmcounter_write_increment; // Write increment of mhpmcounter_q // Signal used for RVFI to set rmask, not used internally - logic mscratchcsw_in_wb; logic mscratchcswl_in_wb; logic mnxti_in_wb; @@ -458,29 +454,6 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; end end - // mscratchcsw: Scratch Swap for Multiple Privilege Modes - CSR_MSCRATCHCSW: begin - if (CLIC) begin - // CLIC spec 13.2 - // Depending on mstatus.MPP, we return either mscratch_rdata or rs1 to rd. - // Safe to use mstatus_rdata here (EX timing), as there is a generic stall of the ID stage - // whenever a CSR instruction follows another CSR instruction. Alternative implementation using - // a local forward of mstatus_rdata is identical (SEC). - csr_hz_o.impl_re_ex = 1'b1; // Reads mstatus and mscratch - csr_hz_o.impl_wr_ex = 1'b1; // Writes mscratch - if (mstatus_rdata.mpp != PRIV_LVL_M) begin - // Return mscratch for writing to GPR - csr_rdata_int = mscratch_rdata; - end else begin - // return rs1 for writing to GPR - csr_rdata_int = id_ex_pipe_i.alu_operand_a; - end - end else begin - csr_rdata_int = '0; - illegal_csr_read = 1'b1; - end - end - // mscratchcswl: Scratch Swap for Interrupt Levels CSR_MSCRATCHCSWL: begin if (CLIC) begin @@ -750,10 +723,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; mintthresh_n = csr_next_value(csr_wdata_int, CSR_MINTTHRESH_MASK, MINTTHRESH_RESET_VAL); mintthresh_we = 1'b0; - mscratchcsw_n = mscratch_n; // mscratchcsw operates conditionally on mscratch - mscratchcsw_we = 1'b0; - - mscratchcswl_n = mscratch_n; // mscratchcsw operates conditionally on mscratch + mscratchcswl_n = mscratch_n; // mscratchcswl operates conditionally on mscratch mscratchcswl_we = 1'b0; mie_n = '0; @@ -795,9 +765,6 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; mintthresh_n = '0; mintthresh_we = 1'b0; - mscratchcsw_n = '0; - mscratchcsw_we = 1'b0; - mscratchcswl_n = '0; mscratchcswl_we = 1'b0; @@ -939,17 +906,6 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; end end - CSR_MSCRATCHCSW: begin - if (CLIC) begin - // mscratchcsw operates on mscratch - // Writing only when mstatus.mpp != PRIV_LVL_M - if (mstatus_rdata.mpp != PRIV_LVL_M) begin - mscratchcsw_we = 1'b1; - mscratch_we = 1'b1; - end - end - end - CSR_MSCRATCHCSWL: begin if (CLIC) begin // mscratchcswl operates on mscratch @@ -1521,11 +1477,6 @@ dcsr_we = 1'b1; // if no interrupt is pending. assign mnxti_rdata = mnxti_irq_pending_i ? {mtvt_addr_o, mnxti_irq_id, 2'b00} : 32'h00000000; - // mscratchcsw_rdata breaks the regular convension for CSRs. Read data depends on mstatus.mpp - // mscratch_rdata is returned if mstatus.mpp differs from PRIV_LVL_M, otherwise rs1 is returned. - // This signal is only used by RVFI, and has WB timing (rs1 comes from ex_wb_pipe_i.csr_wdata, flopped version of id_ex_pipe.alu_operand_a) - assign mscratchcsw_rdata = (mstatus_rdata.mpp != PRIV_LVL_M) ? mscratch_rdata : ex_wb_pipe_i.csr_wdata; - // mscratchcswl_rdata breaks the regular convension for CSrs. Read data depend on mcause.pil and mintstatus.mil. // This signal is only used by RVFI, and has WB timing (rs1 comes from ex_wb_pipe_i.csr_wdata, flopped version of id_ex_pipe.alu_operand_a) assign mscratchcswl_rdata = ((mcause_rdata.mpil == '0) != (mintstatus_rdata.mil == 0)) ? mscratch_rdata : ex_wb_pipe_i.csr_wdata; @@ -1948,16 +1899,14 @@ dcsr_we = 1'b1; assign mcountinhibit_rdata = mcountinhibit_q; // Assign values used for setting rmask in RVFI - assign mscratchcsw_in_wb = ex_wb_pipe_i.csr_en && (csr_waddr == CSR_MSCRATCHCSW); assign mscratchcswl_in_wb = ex_wb_pipe_i.csr_en && (csr_waddr == CSR_MSCRATCHCSWL); assign mnxti_in_wb = ex_wb_pipe_i.csr_en && (csr_waddr == CSR_MNXTI); // Some signals are unused on purpose (typically they are used by RVFI code). Use them here for easier LINT waiving. assign unused_signals = mstatush_we | misa_we | mip_we | mvendorid_we | - marchid_we | mimpid_we | mhartid_we | mconfigptr_we | mtval_we | (|mnxti_n) | mscratchcsw_we | mscratchcswl_we | - (|mscratchcsw_rdata) | (|mscratchcswl_rdata) | (|mscratchcsw_n) | (|mscratchcswl_n) | - mscratchcsw_in_wb | mscratchcswl_in_wb | mnxti_in_wb | + marchid_we | mimpid_we | mhartid_we | mconfigptr_we | mtval_we | (|mnxti_n) | mscratchcswl_we | + (|mscratchcswl_rdata) | (|mscratchcswl_n) |mscratchcswl_in_wb | mnxti_in_wb | (|mtval_n) | (|mconfigptr_n) | (|mhartid_n) | (|mimpid_n) | (|marchid_n) | (|mvendorid_n) | (|mip_n) | (|misa_n) | (|mstatush_n); endmodule diff --git a/rtl/cv32e40x_i_decoder.sv b/rtl/cv32e40x_i_decoder.sv index fea1b51b..e0e686ee 100644 --- a/rtl/cv32e40x_i_decoder.sv +++ b/rtl/cv32e40x_i_decoder.sv @@ -379,8 +379,8 @@ module cv32e40x_i_decoder import cv32e40x_pkg::*; endcase if (CLIC) begin - // The mscratchcsw[l] CSRs are only accessible using CSRRW with neither rd nor rs1 set to x0 - if ((instr_rdata_i[31:20] == CSR_MSCRATCHCSW) || (instr_rdata_i[31:20] == CSR_MSCRATCHCSWL)) begin + // The mscratchcswl CSR is only accessible using CSRRW with neither rd nor rs1 set to x0 + if (instr_rdata_i[31:20] == CSR_MSCRATCHCSWL) begin if (instr_rdata_i[14:12] == 3'b001) begin // CSRRW if ((instr_rdata_i[11:7] == 5'b0) || (instr_rdata_i[19:15] == 5'b0)) begin // rd or rs1 is zero, flag instruction as illegal diff --git a/rtl/include/cv32e40x_pkg.sv b/rtl/include/cv32e40x_pkg.sv index 08ae222f..65b61eb0 100644 --- a/rtl/include/cv32e40x_pkg.sv +++ b/rtl/include/cv32e40x_pkg.sv @@ -263,7 +263,6 @@ typedef enum logic[11:0] { CSR_MIP = 12'h344, CSR_MNXTI = 12'h345, CSR_MINTTHRESH = 12'h347, - CSR_MSCRATCHCSW = 12'h348, CSR_MSCRATCHCSWL = 12'h349, CSR_MCLICBASE = 12'h34A, diff --git a/sva/cv32e40x_cs_registers_sva.sv b/sva/cv32e40x_cs_registers_sva.sv index 9b96c428..02e17351 100644 --- a/sva/cv32e40x_cs_registers_sva.sv +++ b/sva/cv32e40x_cs_registers_sva.sv @@ -119,16 +119,6 @@ module cv32e40x_cs_registers_sva a_htrap_interrupt_level: assert property(p_htrap_interrupt_level) else `uvm_error("cs_registers", "Horizontal trap taken caused interrupt level to change"); - // Check that mscratch do not update due to mscratchcsw if the conditions are not right - property p_mscratchcsw_mscratch; - @(posedge clk) disable iff (!rst_n) - ( ex_wb_pipe_i.csr_en && (csr_waddr == CSR_MSCRATCHCSW) && (mstatus_q.mpp == PRIV_LVL_M) - |=> $stable(mscratch_q)); - endproperty; - - a_mscratchcsw_mscratch: assert property(p_mscratchcsw_mscratch) - else `uvm_error("cs_registers", "Mscratch not stable after mscratwchsw with mpp=M"); - // Check that mscratch do not update due to mscratchcswl if the conditions are not right property p_mscratchcswl_mscratch; @(posedge clk) disable iff (!rst_n) diff --git a/yaml/csr.yaml.m4 b/yaml/csr.yaml.m4 index 4bdf0679..04c088de 100644 --- a/yaml/csr.yaml.m4 +++ b/yaml/csr.yaml.m4 @@ -4487,7 +4487,7 @@ ifelse(eval(CLIC != 0), 1, [[[ lsb: 0 ]]]) -ifelse(eval(CLIC != 0), 1, [[[ +ifelse(eval((CLIC != 0) && (UMODE != 0)), 1, [[[ - csr: mscratchcsw description: > Machine scratch swap for privilege mode change