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graphics_processor.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 17:36:04 April 29, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# graphics_processor_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M50DAF484C7G
set_global_assignment -name TOP_LEVEL_ENTITY graphics_processor
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:36:04 APRIL 29, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_location_assignment PIN_N2 -to VGA_B[3]
set_location_assignment PIN_P4 -to VGA_B[2]
set_location_assignment PIN_T1 -to VGA_B[1]
set_location_assignment PIN_R1 -to VGA_G[3]
set_location_assignment PIN_P1 -to VGA_B[0]
set_location_assignment PIN_R2 -to VGA_G[2]
set_location_assignment PIN_T2 -to VGA_G[1]
set_location_assignment PIN_W1 -to VGA_G[0]
set_location_assignment PIN_N3 -to VGA_HS
set_location_assignment PIN_Y1 -to VGA_R[3]
set_location_assignment PIN_Y2 -to VGA_R[2]
set_location_assignment PIN_V1 -to VGA_R[1]
set_location_assignment PIN_AA1 -to VGA_R[0]
set_location_assignment PIN_N1 -to VGA_VS
set_location_assignment PIN_P11 -to MAX10_CLK1_50
set_global_assignment -name ENABLE_OCT_DONE ON
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE WITH ERAM"
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH testbench_su -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME testbench_ru -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id testbench_ru
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1000000 ns" -section_id testbench_ru
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench_ru -section_id testbench_ru
set_location_assignment PIN_A7 -to Keys[1]
set_location_assignment PIN_B8 -to Keys[0]
set_global_assignment -name EDA_TEST_BENCH_NAME testbench_mm -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id testbench_mm
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "100000 ns" -section_id testbench_mm
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench_mm -section_id testbench_mm
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name SYSTEMVERILOG_FILE testbench/testbench_su.sv
set_global_assignment -name SYSTEMVERILOG_FILE graphics_processor.sv
set_global_assignment -name SYSTEMVERILOG_FILE mat_vec_multiply.sv
set_global_assignment -name SYSTEMVERILOG_FILE shader_unit.sv
set_global_assignment -name SYSTEMVERILOG_FILE testbench/testbench_mm.sv
set_global_assignment -name SYSTEMVERILOG_FILE memory/address_translator_vga.sv
set_global_assignment -name SYSTEMVERILOG_FILE memory/address_translator_gpu.sv
set_global_assignment -name SYSTEMVERILOG_FILE testbench/testbench_ru.sv
set_global_assignment -name SDC_FILE lab6.sdc
set_global_assignment -name SYSTEMVERILOG_FILE VGA_controller.sv
set_global_assignment -name SYSTEMVERILOG_FILE registers/reg_32.sv
set_global_assignment -name SYSTEMVERILOG_FILE rasterizer_unit.sv
set_global_assignment -name QIP_FILE fp_units/fp_mul.qip
set_global_assignment -name SIP_FILE fp_units/fp_mul.sip
set_global_assignment -name QIP_FILE fp_units/fp_div.qip
set_global_assignment -name SIP_FILE fp_units/fp_div.sip
set_global_assignment -name QIP_FILE fp_units/fp_to_int.qip
set_global_assignment -name SIP_FILE fp_units/fp_to_int.sip
set_global_assignment -name QIP_FILE fp_units/int_to_fp.qip
set_global_assignment -name SIP_FILE fp_units/int_to_fp.sip
set_global_assignment -name QIP_FILE memory/frame_buffer.qip
set_global_assignment -name QIP_FILE fp_units/fp_add_sub.qip
set_global_assignment -name SIP_FILE fp_units/fp_add_sub.sip
set_global_assignment -name QIP_FILE fp_units/fp_inv.qip
set_global_assignment -name SIP_FILE fp_units/fp_inv.sip
set_global_assignment -name QIP_FILE fp_units/fp_sqrt.qip
set_global_assignment -name SIP_FILE fp_units/fp_sqrt.sip
set_global_assignment -name QIP_FILE fp_units/fp_dot.qip
set_global_assignment -name SIP_FILE fp_units/fp_dot.sip
set_global_assignment -name QIP_FILE fp_units/fp_sin.qip
set_global_assignment -name SIP_FILE fp_units/fp_sin.sip
set_global_assignment -name QIP_FILE fp_units/fp_cos.qip
set_global_assignment -name SIP_FILE fp_units/fp_cos.sip
set_global_assignment -name QIP_FILE memory/vertices.qip
set_global_assignment -name QIP_FILE test.qip
set_global_assignment -name QIP_FILE tws.qip
set_global_assignment -name QIP_FILE memory/z_buffer.qip
set_global_assignment -name EDA_TEST_BENCH_NAME testbench_su -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id testbench_su
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "100000 ns" -section_id testbench_su
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench_su -section_id testbench_su
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/testbench_ru.sv -section_id testbench_ru
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/testbench_mm.sv -section_id testbench_mm
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/testbench_su.sv -section_id testbench_su
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top