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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entityfuellstandsmessungisport(
a_i : instd_logic;
b_i : instd_logic;
c_i : instd_logic;
led_o : outstd_logic_vector(2downto0)
);
endentity;
architecturertl_unbedingtoffuellstandsmessungisbegin
led_o(0) <= (a_i andnot(b_i and c_i)) or (a_i and b_i and c_i);
led_o(1) <= (a_i and b_i) or (a_i and b_i and c_i);
led_o(2) <= ((not a_i) and c_i) or ((not a_i) and b_i) or ((not b_i) and c_i);
endrtl_unbedingt;
architecturertl_bedingtoffuellstandsmessungissignal in_vec : std_logic_vector(2downto0);
begin
in_vec <= (c_i, b_i, a_i);
led_o <="000"when in_vec ="000"else"001"when in_vec ="001"else"011"when in_vec ="011"else"011"when in_vec ="111"else"100";
endrtl_bedingt;
architecturertl_selectoffuellstandsmessungissignal in_vec : std_logic_vector(2downto0);
begin
in_vec <= (c_i, b_i, a_i);
with in_vec select
led_o <="000"when"000",
"001"when"001",
"011"when"011",
"011"when"111",
"100"whenothers;
endrtl_select;
architecturertl_seqoffuellstandsmessungisbeginfuellstandsmessung: process(a_i, b_i, c_i)
beginif ((a_i ='1'and b_i ='0'and c_i ='0')
or (a_i ='1'and b_i ='1'and c_i ='1')) then
led_o <="001";
elsif ((a_i ='1'and b_i ='1')
or (a_i ='1'and b_i ='1'and c_i ='1')) then
led_o <="011";
elsif((a_i ='0'and c_i ='1')
or (a_i ='0'and b_i ='1')
or (b_i ='0'and c_i ='1')) then
led_o <="100";
endif;
endprocess;
endrtl_seq;
configuration fuellstand_conf of fuellstandsmessung isfor rtl_unbedingt
endfor;
end fuellstand_conf;
Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITYfuellstandsmessung_tbISENDfuellstandsmessung_tb;
ARCHITECTUREbehaviorOFfuellstandsmessung_tbISCOMPONENTfuellstandsmessungPORT(
a_i : instd_logic;
b_i : instd_logic;
c_i : instd_logic;
led_o : outstd_logic_vector(2downto0)
);
END COMPONENT;
signal a, b, c : std_logic;
signal y : std_logic_vector;
BEGIN
uut: fuellstandsmessung
PORT MAP(
a_i => a,
b_i => b,
c_i => c,
led_o => y
);
tb : PROCESS
BEGIN
wait for 500 us;
a <= '0';
b <= '0';
c <= '0';
wait for 10 us;
a <= '1';
wait for 1 ms;
b <= '1';
wait for 1 ms;
c <= '1';
wait for 1 ms;
a <= '0';
b <= '0';
wait for 1 ms;
a <= '1';
b <= '0';
c <= '1';
wait for 100 us;
assert false report "Simulation ended" severity FAILURE;
END PROCESS;
END behavior;