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OV7670_RegDefs.h
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/**************************************************************
* Init_OV7670.h
* Header for OV7670 initialization
* Thanks to ComputerNerd for great code and comments
**************************************************************/
#ifndef OV7670_REGDEFS
#define OV7670_REGDEFS
struct regval_entry {
uint8_t reg_num;
uint8_t value;
};
#ifdef __cplusplus
extern "C" {
#endif
/* Register definitions */
#define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
#define REG_BLUE 0x01 /* blue gain */
#define REG_RED 0x02 /* red gain */
#define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
#define REG_COM1 0x04 /* Control 1 */
#define COM1_CCIR656 0x40 /* CCIR656 enable */
#define REG_BAVE 0x05 /* U/B Average level */
#define REG_GbAVE 0x06 /* Y/Gb Average level */
#define REG_AECHH 0x07 /* AEC MS 5 bits */
#define REG_RAVE 0x08 /* V/R Average level */
#define REG_COM2 0x09 /* Control 2 */
#define COM2_SSLEEP 0x10 /* Soft sleep mode */
#define REG_PID 0x0a /* Product ID MSB */
#define REG_VER 0x0b /* Product ID LSB */
#define REG_COM3 0x0c /* Control 3 */
#define COM3_SWAP 0x40 /* Byte swap */
#define COM3_SCALEEN 0x08 /* Enable scaling */
#define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
#define REG_COM4 0x0d /* Control 4 */
#define REG_COM5 0x0e /* All "reserved" */
#define REG_COM6 0x0f /* Control 6 */
#define REG_AECH 0x10 /* More bits of AEC value */
#define REG_CLKRC 0x11 /* Clocl control */
#define CLK_EXT 0x40 /* Use external clock directly */
#define CLK_SCALE 0x3f /* Mask for internal clock scale */
#define REG_COM7 0x12 /* Control 7 */
#define COM7_RESET 0x80 /* Register reset */
#define COM7_FMT_MASK 0x38
#define COM7_FMT_VGA 0x00
#define COM7_FMT_CIF 0x20 /* CIF format */
#define COM7_FMT_QVGA 0x10 /* QVGA format */
#define COM7_FMT_QCIF 0x08 /* QCIF format */
#define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
#define COM7_YUV 0x00 /* YUV */
#define COM7_BAYER 0x01 /* Bayer format */
#define COM7_PBAYER 0x05 /* "Processed bayer" */
#define REG_COM8 0x13 /* Control 8 */
#define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
#define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
#define COM8_BFILT 0x20 /* Band filter enable */
#define COM8_AGC 0x04 /* Auto gain enable */
#define COM8_AWB 0x02 /* White balance enable */
#define COM8_AEC 0x01 /* Auto exposure enable */
#define REG_COM9 0x14 /* Control 9- gain ceiling */
#define REG_COM10 0x15 /* Control 10 */
#define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
#define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
#define COM10_HREF_REV 0x08 /* Reverse HREF */
#define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
#define COM10_VS_NEG 0x02 /* VSYNC negative */
#define COM10_HS_NEG 0x01 /* HSYNC negative */
#define REG_HSTART 0x17 /* Horiz start high bits */
#define REG_HSTOP 0x18 /* Horiz stop high bits */
#define REG_VSTART 0x19 /* Vert start high bits */
#define REG_VSTOP 0x1a /* Vert stop high bits */
#define REG_PSHFT 0x1b /* Pixel delay after HREF */
#define REG_MIDH 0x1c /* Manuf. ID high */
#define REG_MIDL 0x1d /* Manuf. ID low */
#define REG_MVFP 0x1e /* Mirror / vflip */
#define MVFP_MIRROR 0x20 /* Mirror image */
#define MVFP_FLIP 0x10 /* Vertical flip */
#define REG_AEW 0x24 /* AGC upper limit */
#define REG_AEB 0x25 /* AGC lower limit */
#define REG_VPT 0x26 /* AGC/AEC fast mode op region */
#define REG_HSYST 0x30 /* HSYNC rising edge delay */
#define REG_HSYEN 0x31 /* HSYNC falling edge delay */
#define REG_HREF 0x32 /* HREF pieces */
#define REG_TSLB 0x3a /* lots of stuff */
#define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */
#define REG_COM11 0x3b /* Control 11 */
#define COM11_NIGHT 0x80 /* NIght mode enable */
#define COM11_NMFR 0x60 /* Two bit NM frame rate */
#define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
#define COM11_50HZ 0x08 /* Manual 50Hz select */
#define COM11_EXP 0x02
#define REG_COM12 0x3c /* Control 12 */
#define COM12_HREF 0x80 /* HREF always */
#define REG_COM13 0x3d /* Control 13 */
#define COM13_GAMMA 0x80 /* Gamma enable */
#define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
#define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
#define REG_COM14 0x3e /* Control 14 */
#define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
#define REG_EDGE 0x3f /* Edge enhancement factor */
#define REG_COM15 0x40 /* Control 15 */
#define COM15_R10F0 0x00 /* Data range 10 to F0 */
#define COM15_R01FE 0x80 /* 01 to FE */
#define COM15_R00FF 0xc0 /* 00 to FF */
#define COM15_RGB565 0x10 /* RGB565 output */
#define COM15_RGB555 0x30 /* RGB555 output */
#define REG_COM16 0x41 /* Control 16 */
#define COM16_AWBGAIN 0x08 /* AWB gain enable */
#define REG_COM17 0x42 /* Control 17 */
#define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
#define COM17_CBAR 0x08 /* DSP Color bar */
/*
* This matrix defines how the colors are generated, must be
* tweaked to adjust hue and saturation.
*
* Order: v-red, v-green, v-blue, u-red, u-green, u-blue
* They are nine-bit signed quantities, with the sign bit
* stored in 0x58. Sign for v-red is bit 0, and up from there.
*/
#define REG_CMATRIX_BASE 0x4f
#define CMATRIX_LEN 6
#define REG_CMATRIX_SIGN 0x58
#define REG_BRIGHT 0x55 /* Brightness */
#define REG_CONTRAS 0x56 /* Contrast control */
#define REG_GFIX 0x69 /* Fix gain control */
#define REG_REG76 0x76 /* OV's name */
#define R76_BLKPCOR 0x80 /* Black pixel correction enable */
#define R76_WHTPCOR 0x40 /* White pixel correction enable */
#define REG_RGB444 0x8c /* RGB 444 control */
#define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
#define R444_RGBX 0x01 /* Empty nibble at end */
#define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
#define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
#define REG_BD50MAX 0xa5 /* 50hz banding step limit */
#define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
#define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
#define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
#define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
#define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
#define REG_BD60MAX 0xab /* 60hz banding step limit */
#define COM7_FMT_CIF 0x20 /* CIF format */
#define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
#define COM7_YUV 0x00 /* YUV */
#define COM7_BAYER 0x01 /* Bayer format */
#define COM7_PBAYER 0x05 /* "Processed bayer" */
#define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
#define COM11_50HZ 0x08 /* Manual 50Hz select */
#define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
#define COM15_R01FE 0x80 /* 01 to FE */
#define MTX1 0x4f /* Matrix Coefficient 1 */
#define MTX2 0x50 /* Matrix Coefficient 2 */
#define MTX3 0x51 /* Matrix Coefficient 3 */
#define MTX4 0x52 /* Matrix Coefficient 4 */
#define MTX5 0x53 /* Matrix Coefficient 5 */
#define MTX6 0x54 /* Matrix Coefficient 6 */
#define MTXS 0x58 /* Matrix Coefficient Sign */
#define AWBC7 0x59 /* AWB Control 7 */
#define AWBC8 0x5a /* AWB Control 8 */
#define AWBC9 0x5b /* AWB Control 9 */
#define AWBC10 0x5c /* AWB Control 10 */
#define AWBC11 0x5d /* AWB Control 11 */
#define AWBC12 0x5e /* AWB Control 12 */
#define REG_GFI 0x69 /* Fix gain control */
#define GGAIN 0x6a /* G Channel AWB Gain */
#define DBLV 0x6b
#define AWBCTR3 0x6c /* AWB Control 3 */
#define AWBCTR2 0x6d /* AWB Control 2 */
#define AWBCTR1 0x6e /* AWB Control 1 */
#define AWBCTR0 0x6f /* AWB Control 0 */
// CSI Register bit definitions from KurtE
#ifndef CSI_CSICR1_SWAP16_EN // in process of adding to IMXRT.H
#define CSI_CSICR1_SWAP16_EN ((uint32_t)(1<<31))
#define CSI_CSICR1_EXT_VSYNC ((uint32_t)(1<<30))
#define CSI_CSICR1_EOF_INT_EN ((uint32_t)(1<<29))
#define CSI_CSICR1_PrP_IF_EN ((uint32_t)(1<<28))
#define CSI_CSICR1_CCIR_MODE ((uint32_t)(1<<27))
#define CSI_CSICR1_COF_INT_EN ((uint32_t)(1<<26))
#define CSI_CSICR1_SF_OR_INTEN ((uint32_t)(1<<25))
#define CSI_CSICR1_RF_OR_INTEN ((uint32_t)(1<<24))
#define CSI_CSICR1_SFF_DMA_DONE_INTEN ((uint32_t)(1<<22))
#define CSI_CSICR1_STATFF_INTEN ((uint32_t)(1<<21))
#define CSI_CSICR1_FB2_DMA_DONE_INTEN ((uint32_t)(1<<20))
#define CSI_CSICR1_FB1_DMA_DONE_INTEN ((uint32_t)(1<<19))
#define CSI_CSICR1_RXFF_INTEN ((uint32_t)(1<<18))
#define CSI_CSICR1_SOF_POL ((uint32_t)(1<<17))
#define CSI_CSICR1_SOF_INTEN ((uint32_t)(1<<16))
#define CSI_CSICR1_HSYNC_POL ((uint32_t)(1<<11))
#define CSI_CSICR1_CCIR_EN ((uint32_t)(1<<10))
#define CSI_CSICR1_FCC ((uint32_t)(1<<8))
#define CSI_CSICR1_PACK_DIR ((uint32_t)(1<<7))
#define CSI_CSICR1_CLR_STATFIFO ((uint32_t)(1<<6))
#define CSI_CSICR1_CLR_RXFIFO ((uint32_t)(1<<5))
#define CSI_CSICR1_GCLK_MODE ((uint32_t)(1<<4))
#define CSI_CSICR1_INV_DATA ((uint32_t)(1<<3))
#define CSI_CSICR1_INV_PCLK ((uint32_t)(1<<2))
#define CSI_CSICR1_REDGE ((uint32_t)(1<<1))
#define CSI_CSICR1_PIXEL_BIT ((uint32_t)(1<<0))
#define CSI_CSICR2_DMA_BURST_TYPE_RFF(n) ((uint32_t)(((n) & 0x3)<<30))
#define CSI_CSICR2_DMA_BURST_TYPE_SFF(n) ((uint32_t)(((n) & 0x3)<<28))
#define CSI_CSICR2_DRM ((uint32_t)(1<<26))
#define CSI_CSICR2_AFS(n) ((uint32_t)(((n) & 0x3)<<24))
#define CSI_CSICR2_SCE ((uint32_t)(1<<23))
#define CSI_CSICR2_BTS(n) ((uint32_t)(((n) & 0x3)<<19))
#define CSI_CSICR2_LVRM(n) ((uint32_t)(((n) & 0x7)<<16))
#define CSI_CSICR2_VSC(n) ((uint32_t)(((n) & 0xff)<<8))
#define CSI_CSICR2_HSC(n) ((uint32_t)(((n) & 0xff)<<0))
#define CSI_CSICR3_FRMCNT(n) ((uint32_t)(((n) & 0xffff)<<16))
#define CSI_CSICR3_FRMCNT_RST ((uint32_t)(1<<15))
#define CSI_CSICR3_DMA_REFLASH_RFF ((uint32_t)(1<<14))
#define CSI_CSICR3_DMA_REFLASH_SFF ((uint32_t)(1<<13))
#define CSI_CSICR3_DMA_REQ_EN_RFF ((uint32_t)(1<<12))
#define CSI_CSICR3_DMA_REQ_EN_SFF ((uint32_t)(1<<11))
#define CSI_CSICR3_STATFF_LEVEL(n) ((uint32_t)(((n) & 0x7)<<8))
#define CSI_CSICR3_HRESP_ERR_EN ((uint32_t)(1<<7))
#define CSI_CSICR3_RxFF_LEVEL(n) ((uint32_t)(((n) & 0x7)<<4))
#define CSI_CSICR3_TWO_8BIT_SENSOR ((uint32_t)(1<<3))
#define CSI_CSICR3_ZERO_PACK_EN ((uint32_t)(1<<2))
#define CSI_CSICR3_ECC_INT_EN ((uint32_t)(1<<1))
#define CSI_CSICR3_ECC_AUTO_EN ((uint32_t)(1<<0))
#define CSI_CSISR_BASEADDR_CHHANGE_ERROR ((uint32_t)(1<<28))
#define CSI_CSISR_DMA_FIELD0_DONE ((uint32_t)(1<<27))
#define CSI_CSISR_DMA_FIELD1_DONE ((uint32_t)(1<<26))
#define CSI_CSISR_SF_OR_INT ((uint32_t)(1<<25))
#define CSI_CSISR_RF_OR_INT ((uint32_t)(1<<24))
#define CSI_CSISR_DMA_TSF_DONE_SFF ((uint32_t)(1<<22))
#define CSI_CSISR_STATFF_INT ((uint32_t)(1<<21))
#define CSI_CSISR_DMA_TSF_DONE_FB2 ((uint32_t)(1<<20))
#define CSI_CSISR_DMA_TSF_DONE_FB1 ((uint32_t)(1<<19))
#define CSI_CSISR_RxFF_INT ((uint32_t)(1<<18))
#define CSI_CSISR_EOF_INT ((uint32_t)(1<<17))
#define CSI_CSISR_SOF_INT ((uint32_t)(1<<16))
#define CSI_CSISR_F2_INT ((uint32_t)(1<<15))
#define CSI_CSISR_F1_INT ((uint32_t)(1<<14))
#define CSI_CSISR_COF_INT ((uint32_t)(1<<13))
#define CSI_CSISR_HRESP_ERR_INT ((uint32_t)(1<<7))
#define CSI_CSISR_ECC_INT ((uint32_t)(1<<1))
#define CSI_CSISR_DRDY ((uint32_t)(1<<0))
#define CSI_CSICR18_CSI_ENABLE ((uint32_t)(1<<31))
#define CSI_CSICR18_MASK_OPTION(n) ((uint32_t)(((n) & 0x3)<<18))
#define CSI_CSICR18_AHB_HPROT(n) ((uint32_t)(((n) & 0xf)<<12))
#define CSI_CSICR18_RGB888A_FORMAT_SEL ((uint32_t)(1<<10))
#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE ((uint32_t)(1<<9))
#define CSI_CSICR18_LAST_DMA_REQ_SEL ((uint32_t)(1<<8))
#define CSI_CSICR18_DMA_FIELD1_DONE_IE ((uint32_t)(1<<7))
#define CSI_CSICR18_FIELD0_DONE_IE ((uint32_t)(1<<6))
#define CSI_CSICR18_BASEADDR_SWITCH_SEL ((uint32_t)(1<<5))
#define CSI_CSICR18_BASEADDR_SWITCH_EN ((uint32_t)(1<<4))
#define CSI_CSICR18_PARALLEL24_EN ((uint32_t)(1<<3))
#define CSI_CSICR18_DEINTERLACE_EN ((uint32_t)(1<<2))
#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(n) ((uint32_t)(((n) & 0xf)<<12))
#endif
#ifdef __cplusplus
}
#endif
#endif // OV7670.h