diff --git a/dts/bindings/sys/cpus,cluster.yaml b/dts/bindings/sys/cpus,cluster.yaml
new file mode 100644
index 00000000000000..032507eba651c3
--- /dev/null
+++ b/dts/bindings/sys/cpus,cluster.yaml
@@ -0,0 +1,83 @@
+# Copyright 2023 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+include:
+  - name: base.yaml
+    property-allowlist:
+      - "#address-cells"
+      - "#size-cells"
+      - compatible
+      - status
+
+compatible: cpus,cluster
+
+description: |
+  A CPU cluster is a node which describes one or more CPUs on an SoC.
+
+  For detailed semantics, please refer to the System Devicetree
+  Specification, chapter 2.
+
+properties:
+  "#address-cells":
+    const: 1
+  "#size-cells":
+    const: 0
+  "#ranges-address-cells":
+    type: int
+    required: true
+    description: |
+      The number of cells required to represent the base address
+      of a region of hardware resources which have been mapped into
+      this cluster's address space by an entry in the address-map
+      property.
+  "#ranges-size-cells":
+    type: int
+    required: true
+    description: |
+      The number of cells required to represent the size of an
+      address range in an address-map entry.
+  address-map:
+    type: compound
+    required: true
+    decription: |
+      Provides a mapping for the hardware resources visible to this
+      CPU cluster to the address space of the CPUs in the cluster.
+
+child-binding:
+  include:
+    - name: base.yaml
+      property-allowlist:
+        - compatible
+
+  description: |
+    The child nodes of a CPU cluster node represent the CPUs in the
+    cluster. These follow the binding for CPUs defined in the
+    Devicetree Specification, section 3.8.
+
+    Implementation note:
+
+    There's a small sysDT spec issue here. Some required CPU node
+    properties from the DT spec aren't present in sysdt spec examples
+    for CPU nodes in a CPU cluster.
+
+    For example, DT spec section 3.8 says that 'clock-frequency' is a
+    required CPU property, and the system DT spec currently says we
+    follow 3.8 for these nodes, but the examples in the system DT spec
+    don't provide 'clock-frequency' properties.
+
+    For now, we side with the examples and are permissive by requiring
+    minimal properties here.
+
+  properties:
+    device_type:
+      required: true
+      type: string
+      const: "cpu"
+      description: |
+        Use of this standard property is deprecated in most cases, but
+        is still accepted for CPU nodes.
+
+    reg:
+      required: true
+      type: array
+      description: A unique CPU or thread identifier
diff --git a/dts/bindings/sys/indirect-bus.yaml b/dts/bindings/sys/indirect-bus.yaml
new file mode 100644
index 00000000000000..636f1bf975eb63
--- /dev/null
+++ b/dts/bindings/sys/indirect-bus.yaml
@@ -0,0 +1,26 @@
+# Copyright 2023 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+include: base.yaml
+
+compatible: indirect-bus
+
+description: |
+  A node in a system devicetree which acts as a resource container. It
+  is similar to the "simple-bus" compatible value defined in the
+  Devicetree Specification.
+
+  Hardware resources that are children of an indirect-bus node do not
+  automatically map into the parent node's address space. The devices
+  on this bus must be explicitly mapped into each CPU cluster's address
+  space. (See the "cpus,cluster" binding for more information on CPU
+  clusters.)
+
+  For detailed semantics, please refer to the System Devicetree
+  Specification, chapter 2.
+
+properties:
+  "#address-cells":
+    required: true
+  "#size-cells":
+    required: true
diff --git a/dts/bindings/sys/openamp,domain-v1.yaml b/dts/bindings/sys/openamp,domain-v1.yaml
new file mode 100644
index 00000000000000..43c1187f9d3cae
--- /dev/null
+++ b/dts/bindings/sys/openamp,domain-v1.yaml
@@ -0,0 +1,100 @@
+# Copyright 2023 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+compatible: openamp,domain-v1
+
+description: |
+  An execution domain is a node which describes a software or firmware
+  image running on a CPU cluster. For more information on CPU
+  clusters, see the binding for the "cpus,cluster" compatible.
+
+  For detailed semantics, please refer to the System Devicetree
+  Specification, chapter 3.
+
+properties:
+  cpus:
+    type: compound
+    required: true
+    description: |
+      Describes the physical CPUs that this execution domain runs
+      on, along with the domain's execution level on those CPUs.
+
+  "#access-flags-cells":
+    type: int
+    default: 0
+    description: |
+      Number of cells used to represent the access flags for each
+      device in the access property. The default value is specified
+      by the System Devicetree Specification.
+
+  access:
+    type: compound
+    description: |
+      SPecifies devices which are accessible by this domain.
+
+  "#memory-flags-cells":
+    type: int
+    default: 0
+    description: |
+      Number of cells used to represent the flags for each memory
+      range in the memory property. The default value is specified
+      by the System Devicetree Specification.
+
+  memory:
+    type: compound
+    description: |
+      Memory assigned to the domain.
+
+  "#sram-flags-cells":
+    type: int
+    default: 0
+    description: |
+      Number of cells used to represent the flags for each SRAM
+      range in the sram property. The default value is specified
+      by the System Devicetree Specification.
+
+  sram:
+    type: compound
+    description: |
+      MMIO SRAM assigned to the domain.
+
+  id:
+    type: int
+    description: |
+      A unique numeric identifier which may be given to the domain.
+
+  os,type:
+    type: string
+    description: |
+      A string in the format OS_TYPE[,TYPE_ID[,TYPE_ID_VERSION]]
+      which identifies the operating system of the domain.
+
+  "#access-implicit-default-cells":
+    type: int
+    description: |
+      Number of cells in the access-implicit-default property.
+
+  access-implicit-default:
+    type: array
+    description: |
+      Default value for the access flags for the execution domain.
+
+  "#memory-implicit-default-cells":
+    type: int
+    description: |
+      Number of cells in the memory-implicit-default property.
+
+  memory-implicit-default:
+    type: array
+    description: |
+      Default value for the memory flags for the execution domain.
+
+  "#sram-implicit-default-cells":
+    type: int
+    description: |
+      Number of cells in the sram-implicit-default property.
+
+  sram-implicit-default:
+    type: array
+    description: |
+      Default value for the sram flags for the execution domain.