diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 428dc83e2fd3d4..60174fc9da8f82 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -2456,6 +2456,7 @@ void DAGTypeLegalizer::SoftPromoteHalfResult(SDNode *N, unsigned ResNo) {
   case ISD::FLOG10:
   case ISD::FNEARBYINT:
   case ISD::FNEG:
+  case ISD::FREEZE:
   case ISD::FRINT:
   case ISD::FROUND:
   case ISD::FSIN:
diff --git a/llvm/test/CodeGen/X86/freeze.ll b/llvm/test/CodeGen/X86/freeze.ll
index 9ae9661a148c80..07f9faabf68c09 100644
--- a/llvm/test/CodeGen/X86/freeze.ll
+++ b/llvm/test/CodeGen/X86/freeze.ll
@@ -33,6 +33,26 @@ define float @freeze_float() {
   ret float %t1
 }
 
+define half @freeze_half() {
+; X86ASM-LABEL: freeze_half:
+; X86ASM:       # %bb.0:
+; X86ASM-NEXT:    pushq %rax
+; X86ASM-NEXT:    .cfi_def_cfa_offset 16
+; X86ASM-NEXT:    xorl %edi, %edi
+; X86ASM-NEXT:    callq __gnu_h2f_ieee
+; X86ASM-NEXT:    callq __gnu_f2h_ieee
+; X86ASM-NEXT:    movzwl %ax, %edi
+; X86ASM-NEXT:    callq __gnu_h2f_ieee
+; X86ASM-NEXT:    addss %xmm0, %xmm0
+; X86ASM-NEXT:    callq __gnu_f2h_ieee
+; X86ASM-NEXT:    popq %rcx
+; X86ASM-NEXT:    .cfi_def_cfa_offset 8
+; X86ASM-NEXT:    retq
+  %y1 = freeze half undef
+  %t1 = fadd half %y1, %y1
+  ret half %t1
+}
+
 define <2 x i32> @freeze_ivec() {
 ; X86ASM-LABEL: freeze_ivec:
 ; X86ASM:       # %bb.0: