forked from open-power/skiboot
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathspira.c
1918 lines (1619 loc) · 51.1 KB
/
spira.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
/* Copyright 2013-2019 IBM Corp. */
#include <inttypes.h>
#include <device.h>
#include <cpu.h>
#include <vpd.h>
#include <interrupts.h>
#include <ccan/str/str.h>
#include <chip.h>
#include <opal-dump.h>
#include <fsp-attn.h>
#include <fsp-leds.h>
#include <skiboot.h>
#include <vas.h>
#include "hdata.h"
#include "hostservices.h"
#include "naca.h"
#include "spira.h"
/* Processor Initialization structure, contains
* the initial NIA and MSR values for the entry
* point
*
* Note: It appears to be ignoring the entry point
* and always going to 0x180
*/
static int cpu_type;
extern struct proc_init_data proc_init_data;
__section(".procin.data") struct proc_init_data proc_init_data = {
.hdr = HDIF_SIMPLE_HDR("PROCIN", 1, struct proc_init_data),
.regs_ptr = HDIF_IDATA_PTR(offsetof(struct proc_init_data, regs), 0x10),
.regs = {
.nia = CPU_TO_BE64(0x180),
.msr = CPU_TO_BE64(MSR_SF | MSR_HV),
},
};
extern struct cpu_ctl_init_data cpu_ctl_init_data;
extern struct sp_addr_table cpu_ctl_spat_area;
extern struct sp_attn_area cpu_ctl_sp_attn_area1;
extern struct sp_attn_area cpu_ctl_sp_attn_area2;
extern struct hsr_data_area cpu_ctl_hsr_area;
/*
* cpuctrl.data begins at CPU_CTL_OFF - cpu_ctl_init_data is located there.
* + sizeof(struct cpu_ctl_init_data) - cpu_ctl_spat_area
* + sizeof(struct sp_addr_table) - cpu_ctl_sp_attn_area1
* + sizeof(struct sp_attn_area) - cpu_ctl_sp_attn_area2
* + sizeof(struct sp_attn_area) - cpu_ctl_hsr_area
*
* Can't use CPU_TO_BE64 directly on the labels as a constant initialiser.
*
* CPU_CTL_INIT_DATA_OFF is offset from 0, the others are addressed from the
* relocated address (+SKIBOOT_BASE)
*/
#define CPU_CTL_INIT_DATA_OFF (CPU_CTL_OFF)
#define CPU_CTL_SPAT_AREA_OFF (CPU_CTL_INIT_DATA_OFF + sizeof(struct cpu_ctl_init_data) + SKIBOOT_BASE)
#define CPU_CTL_SP_ATTN_AREA1_OFF (ALIGN_UP((CPU_CTL_SPAT_AREA_OFF + sizeof(struct sp_addr_table)), ATTN_AREA_SZ))
#define CPU_CTL_SP_ATTN_AREA2_OFF (CPU_CTL_SP_ATTN_AREA1_OFF + sizeof(struct sp_attn_area))
#define CPU_CTL_HSR_AREA_OFF (CPU_CTL_SP_ATTN_AREA2_OFF + sizeof(struct sp_attn_area))
__section(".cpuctrl.data") struct hsr_data_area cpu_ctl_hsr_area;
__section(".cpuctrl.data") struct sp_attn_area cpu_ctl_sp_attn_area2;
__section(".cpuctrl.data") struct sp_attn_area cpu_ctl_sp_attn_area1;
__section(".cpuctrl.data") struct sp_addr_table cpu_ctl_spat_area;
__section(".cpuctrl.data") struct cpu_ctl_init_data cpu_ctl_init_data = {
.hdr = HDIF_SIMPLE_HDR(CPU_CTL_HDIF_SIG, 2, struct cpu_ctl_init_data),
.cpu_ctl = HDIF_IDATA_PTR(offsetof(struct cpu_ctl_init_data, cpu_ctl_lt),
sizeof(struct cpu_ctl_legacy_table)),
.cpu_ctl_lt = {
.spat = {
.addr = CPU_TO_BE64(CPU_CTL_SPAT_AREA_OFF),
.size = CPU_TO_BE64(sizeof(struct sp_addr_table)),
},
.sp_attn_area1 = {
.addr = CPU_TO_BE64(CPU_CTL_SP_ATTN_AREA1_OFF),
.size = CPU_TO_BE64(sizeof(struct sp_attn_area)),
},
.sp_attn_area2 = {
.addr = CPU_TO_BE64(CPU_CTL_SP_ATTN_AREA2_OFF),
.size = CPU_TO_BE64(sizeof(struct sp_attn_area)),
},
.hsr_area = {
.addr = CPU_TO_BE64(CPU_CTL_HSR_AREA_OFF),
.size = CPU_TO_BE64(sizeof(struct hsr_data_area)),
},
},
};
/* Populate MDST table
*
* Note that we only pass sapphire console buffer here so that we can
* capture early failure logs. Later dump component (fsp_dump_mdst_init)
* creates new table with all the memory sections we are interested and
* sends updated table to FSP via MBOX.
*
* To help the FSP distinguishing between TCE tokens and actual physical
* addresses, we set the top bit to 1 on physical addresses
*/
extern struct mdst_table init_mdst_table[];
__section(".mdst.data") struct mdst_table init_mdst_table[2] = {
{
.addr = CPU_TO_BE64(INMEM_CON_START | HRMOR_BIT),
.data_region = DUMP_REGION_CONSOLE,
.dump_type = DUMP_TYPE_SYSDUMP,
.size = CPU_TO_BE32(INMEM_CON_LEN),
},
{
.addr = CPU_TO_BE64(HBRT_CON_START | HRMOR_BIT),
.data_region = DUMP_REGION_HBRT_LOG,
.dump_type = DUMP_TYPE_SYSDUMP,
.size = CPU_TO_BE32(HBRT_CON_LEN),
},
};
/* SP Interface Root Array, aka SPIRA */
__section(".spira.data") struct spira spira = {
.hdr = HDIF_SIMPLE_HDR("SPIRA ", SPIRA_VERSION, struct spira),
.ntuples_ptr = HDIF_IDATA_PTR(offsetof(struct spira, ntuples),
sizeof(struct spira_ntuples)),
.ntuples = {
.array_hdr = {
.offset = CPU_TO_BE32(HDIF_ARRAY_OFFSET),
.ecnt = CPU_TO_BE32(SPIRA_NTUPLES_COUNT),
.esize
= CPU_TO_BE32(sizeof(struct spira_ntuple)),
.eactsz = CPU_TO_BE32(0x18),
},
/* We only populate some n-tuples */
.proc_init = {
.addr = CPU_TO_BE64(PROCIN_OFF),
.alloc_cnt = CPU_TO_BE16(1),
.act_cnt = CPU_TO_BE16(1),
.alloc_len
= CPU_TO_BE32(sizeof(struct proc_init_data)),
},
.heap = {
.addr = CPU_TO_BE64(SPIRA_HEAP_BASE),
.alloc_cnt = CPU_TO_BE16(1),
.alloc_len = CPU_TO_BE32(SPIRA_HEAP_SIZE),
},
.mdump_src = {
.addr = CPU_TO_BE64(MDST_TABLE_OFF),
.alloc_cnt = CPU_TO_BE16(ARRAY_SIZE(init_mdst_table)),
.act_cnt = CPU_TO_BE16(ARRAY_SIZE(init_mdst_table)),
.alloc_len =
CPU_TO_BE32(sizeof(init_mdst_table)),
},
.cpu_ctrl = {
.addr = CPU_TO_BE64(CPU_CTL_INIT_DATA_OFF),
.alloc_cnt = CPU_TO_BE16(1),
.act_cnt = CPU_TO_BE16(1),
.alloc_len = CPU_TO_BE32(sizeof(cpu_ctl_init_data)),
},
},
};
/* The Hypervisor SPIRA-H Structure */
__section(".spirah.data") struct spirah spirah = {
.hdr = HDIF_SIMPLE_HDR(SPIRAH_HDIF_SIG, SPIRAH_VERSION, struct spirah),
.ntuples_ptr = HDIF_IDATA_PTR(offsetof(struct spirah, ntuples),
sizeof(struct spirah_ntuples)),
.ntuples = {
.array_hdr = {
.offset = CPU_TO_BE32(HDIF_ARRAY_OFFSET),
.ecnt = CPU_TO_BE32(SPIRAH_NTUPLES_COUNT),
.esize
= CPU_TO_BE32(sizeof(struct spira_ntuple)),
.eactsz = CPU_TO_BE32(0x18),
},
/* Host Data Areas */
.hs_data_area = {
.addr = CPU_TO_BE64(SPIRA_HEAP_BASE),
.alloc_cnt = CPU_TO_BE16(1),
.alloc_len = CPU_TO_BE32(SPIRA_HEAP_SIZE),
},
/* We only populate some n-tuples */
.proc_init = {
.addr = CPU_TO_BE64(PROCIN_OFF),
.alloc_cnt = CPU_TO_BE16(1),
.act_cnt = CPU_TO_BE16(1),
.alloc_len
= CPU_TO_BE32(sizeof(struct proc_init_data)),
},
.cpu_ctrl = {
.addr = CPU_TO_BE64(CPU_CTL_INIT_DATA_OFF),
.alloc_cnt = CPU_TO_BE16(1),
.act_cnt = CPU_TO_BE16(1),
.alloc_len =
CPU_TO_BE32(sizeof(cpu_ctl_init_data)),
},
.mdump_src = {
.addr = CPU_TO_BE64(MDST_TABLE_OFF),
.alloc_cnt = CPU_TO_BE16(MDST_TABLE_SIZE / sizeof(struct mdst_table)),
.act_cnt = CPU_TO_BE16(ARRAY_SIZE(init_mdst_table)),
.alloc_len = CPU_TO_BE32(sizeof(struct mdst_table)),
.act_len = CPU_TO_BE32(sizeof(struct mdst_table)),
},
.mdump_dst = {
.addr = CPU_TO_BE64(MDDT_TABLE_OFF),
.alloc_cnt = CPU_TO_BE16(MDDT_TABLE_SIZE / sizeof(struct mddt_table)),
.act_cnt = CPU_TO_BE16(0),
.alloc_len = CPU_TO_BE32(sizeof(struct mddt_table)),
.act_len = CPU_TO_BE32(sizeof(struct mddt_table)),
},
.mdump_res = {
.addr = CPU_TO_BE64(MDRT_TABLE_BASE),
.alloc_cnt = CPU_TO_BE16(MDRT_TABLE_SIZE / sizeof(struct mdrt_table)),
/*
* XXX: Ideally hostboot should use allocated count and
* length. But looks like hostboot uses actual count
* and length to get MDRT table size. And post dump
* hostboot will update act_cnt. Hence update both
* alloc_cnt and act_cnt.
*/
.act_cnt = CPU_TO_BE16(MDRT_TABLE_SIZE / sizeof(struct mdrt_table)),
.alloc_len = CPU_TO_BE32(sizeof(struct mdrt_table)),
.act_len = CPU_TO_BE32(sizeof(struct mdrt_table)),
},
.proc_dump_area = {
.addr = CPU_TO_BE64(PROC_DUMP_AREA_OFF),
.alloc_cnt = CPU_TO_BE16(1),
.act_cnt = CPU_TO_BE16(1),
.alloc_len = CPU_TO_BE32(sizeof(struct proc_dump_area)),
.act_len = CPU_TO_BE32(sizeof(struct proc_dump_area)),
},
},
};
/* The service processor SPIRA-S structure */
struct spiras *skiboot_constant_addr spiras;
/* Overridden for testing. */
#ifndef spira_check_ptr
bool spira_check_ptr(const void *ptr, const char *file, unsigned int line)
{
if (!ptr)
return false;
if (((unsigned long)ptr) >= SPIRA_HEAP_BASE &&
((unsigned long)ptr) < (SPIRA_HEAP_BASE + SPIRA_HEAP_SIZE))
return true;
prerror("SPIRA: Bad pointer %p at %s line %d\n", ptr, file, line);
return false;
}
#endif
struct HDIF_common_hdr *__get_hdif(struct spira_ntuple *n, const char id[],
const char *file, int line)
{
struct HDIF_common_hdr *h = ntuple_addr(n);
u16 act_cnt, alloc_cnt;
u32 act_len, alloc_len;
if (!spira_check_ptr(h, file, line))
return NULL;
act_cnt = be16_to_cpu(n->act_cnt);
alloc_cnt = be16_to_cpu(n->alloc_cnt);
if (act_cnt > alloc_cnt) {
prerror("SPIRA: bad ntuple, act_cnt > alloc_cnt (%u > %u)\n",
act_cnt, alloc_cnt);
return NULL;
}
act_len = be32_to_cpu(n->act_len);
alloc_len = be32_to_cpu(n->alloc_len);
if (act_len > alloc_len) {
prerror("SPIRA: bad ntuple, act_len > alloc_len (%u > %u)\n",
act_len, alloc_len);
return NULL;
}
if (!HDIF_check(h, id)) {
prerror("SPIRA: bad tuple %p: expected %s at %s line %d\n",
h, id, file, line);
return NULL;
}
return h;
}
uint32_t get_xscom_id(const struct sppcrd_chip_info *cinfo)
{
if (proc_gen <= proc_gen_p9)
return be32_to_cpu(cinfo->xscom_id);
/* On P10 use Processor fabric topology id for chip id */
return (uint32_t)(cinfo->fab_topology_id);
}
static struct dt_node *add_xscom_node(uint64_t base,
const struct sppcrd_chip_info *cinfo)
{
struct dt_node *node;
uint64_t addr, size;
uint64_t freq;
uint32_t hw_id = get_xscom_id(cinfo);
uint32_t proc_chip_id = be32_to_cpu(cinfo->proc_chip_id);
switch (proc_gen) {
case proc_gen_p8:
/* On P8 all the chip SCOMs share single region */
addr = base | ((uint64_t)hw_id << PPC_BITLSHIFT(28));
break;
case proc_gen_p9:
/* On P9 we need to put the chip ID in the natural powerbus
* position.
*/
addr = base | (((uint64_t)hw_id) << 42);
break;
case proc_gen_p10:
default:
/* Use Primary topology table index for xscom address */
addr = base | (((uint64_t)cinfo->topology_id_table[cinfo->primary_topology_loc]) << 44);
break;
};
size = (u64)1 << PPC_BITLSHIFT(28);
prlog(PR_INFO, "XSCOM: Found HW ID 0x%x (PCID 0x%x) @ 0x%llx\n",
hw_id, proc_chip_id, (long long)addr);
node = dt_new_addr(dt_root, "xscom", addr);
assert(node);
dt_add_property_cells(node, "ibm,chip-id", hw_id);
dt_add_property_cells(node, "ibm,proc-chip-id", proc_chip_id);
dt_add_property_cells(node, "#address-cells", 1);
dt_add_property_cells(node, "#size-cells", 1);
dt_add_property(node, "scom-controller", NULL, 0);
switch(proc_gen) {
case proc_gen_p8:
dt_add_property_strings(node, "compatible",
"ibm,xscom", "ibm,power8-xscom");
break;
case proc_gen_p9:
dt_add_property_strings(node, "compatible",
"ibm,xscom", "ibm,power9-xscom");
break;
case proc_gen_p10:
dt_add_property_strings(node, "compatible",
"ibm,xscom", "ibm,power10-xscom");
break;
default:
dt_add_property_strings(node, "compatible", "ibm,xscom");
}
dt_add_property_u64s(node, "reg", addr, size);
/*
* The bus-frequency of the xscom node is actually the PIB/PCB
* frequency. It is derived from the nest-clock via a 4:1 divider
*/
freq = dt_prop_get_u64_def(dt_root, "nest-frequency", 0);
freq /= 4;
if (freq)
dt_add_property_u64(node, "bus-frequency", freq);
return node;
}
/*
* Given a xscom@ node this will return a pointer into the SPPCRD
* structure corresponding to that node
*/
#define GET_HDIF_HDR -1
static const void *xscom_to_pcrd(struct dt_node *xscom, int idata_index)
{
struct spira_ntuple *t = &spira.ntuples.proc_chip;
const struct HDIF_common_hdr *hdif;
const void *idata;
unsigned int size;
uint32_t i;
void *base;
i = dt_prop_get_u32_def(xscom, DT_PRIVATE "sppcrd-index", 0xffffffff);
if (i == 0xffffffff)
return NULL;
base = get_hdif(t, "SPPCRD");
assert(base);
assert(i < be16_to_cpu(t->act_cnt));
hdif = base + i * be32_to_cpu(t->alloc_len);
assert(hdif);
if (idata_index == GET_HDIF_HDR)
return hdif;
idata = HDIF_get_idata(hdif, idata_index, &size);
if (!idata || !size)
return NULL;
return idata;
}
struct dt_node *find_xscom_for_chip(uint32_t chip_id)
{
struct dt_node *node;
uint32_t id;
dt_for_each_compatible(dt_root, node, "ibm,xscom") {
id = dt_get_chip_id(node);
if (id == chip_id)
return node;
}
return NULL;
}
static void add_psihb_node(struct dt_node *np)
{
u32 psi_scom, psi_slen;
const char *psi_comp;
/*
* We add a few things under XSCOM that aren't added
* by any other HDAT path
*/
/* PSI host bridge */
switch(proc_gen) {
case proc_gen_p8:
psi_scom = 0x2010900;
psi_slen = 0x20;
psi_comp = "ibm,power8-psihb-x";
break;
case proc_gen_p9:
psi_scom = 0x5012900;
psi_slen = 0x100;
psi_comp = "ibm,power9-psihb-x";
break;
case proc_gen_p10:
psi_scom = 0x3011d00;
psi_slen = 0x100;
psi_comp = "ibm,power10-psihb-x";
break;
default:
psi_comp = NULL;
}
if (psi_comp) {
struct dt_node *psi_np;
psi_np = dt_new_addr(np, "psihb", psi_scom);
if (!psi_np)
return;
dt_add_property_cells(psi_np, "reg", psi_scom, psi_slen);
dt_add_property_strings(psi_np, "compatible", psi_comp,
"ibm,psihb-x");
}
}
static void add_xive_node(struct dt_node *np)
{
struct dt_node *xive;
const char *comp;
u32 scom, slen;
switch (proc_gen) {
case proc_gen_p9:
scom = 0x5013000;
slen = 0x300;
comp = "ibm,power9-xive-x";
break;
case proc_gen_p10:
scom = 0x2010800;
slen = 0x400;
comp = "ibm,power10-xive-x";
break;
default:
return;
}
xive = dt_new_addr(np, "xive", scom);
dt_add_property_cells(xive, "reg", scom, slen);
dt_add_property_string(xive, "compatible", comp);
/* HACK: required for simics */
dt_add_property(xive, "force-assign-bars", NULL, 0);
}
static void add_vas_node(struct dt_node *np, int idx)
{
struct dt_node *vas;
const char *comp;
uint64_t base_addr;
if (proc_gen == proc_gen_p9) {
base_addr = P9_VAS_SCOM_BASE_ADDR;
comp = "ibm,power9-vas-x";
} else {
base_addr = VAS_SCOM_BASE_ADDR;
comp = "ibm,power10-vas-x";
}
vas = dt_new_addr(np, "vas", base_addr);
dt_add_property_cells(vas, "reg", base_addr, 0x300);
dt_add_property_string(vas, "compatible", comp);
dt_add_property_cells(vas, "ibm,vas-id", idx);
}
static void add_ecid_data(const struct HDIF_common_hdr *hdr,
struct dt_node *xscom)
{
char wafer_id[11];
uint8_t tmp;
int i;
uint32_t size = 0;
struct sppcrd_ecid *ecid;
const struct HDIF_array_hdr *ec_hdr;
ec_hdr = HDIF_get_idata(hdr, SPPCRD_IDATA_EC_LEVEL, &size);
if (!ec_hdr || !size)
return;
ecid = (void *)ec_hdr + be32_to_cpu(ec_hdr->offset);
dt_add_property_u64s(xscom, "ecid", be64_to_cpu(ecid->low),
be64_to_cpu(ecid->high));
/*
* bits 4:63 of ECID data contains wafter ID data (ten 6 bit fields
* each containing a code).
*/
for (i = 0; i < 10; i++) {
tmp = (u8)((be64_to_cpu(ecid->low) >> (i * 6)) & 0x3f);
if (tmp <= 9)
wafer_id[9 - i] = tmp + '0';
else if (tmp >= 0xA && tmp <= 0x23)
wafer_id[9 - i] = tmp + '0' + 7;
else if (tmp == 0x3D)
wafer_id[9 - i] = '-';
else if (tmp == 0x3E)
wafer_id[9 - i] = '.';
else if (tmp == 0x3F)
wafer_id[9 - i] = ' ';
else /* Unknown code */
wafer_id[9 - i] = tmp + '0';
}
wafer_id[10] = '\0';
dt_add_property_nstr(xscom, "wafer-id", wafer_id, 10);
dt_add_property_cells(xscom, "wafer-location",
(u32)((be64_to_cpu(ecid->high) >> 56) & 0xff),
(u32)((be64_to_cpu(ecid->high) >> 48) & 0xff));
}
static void add_xscom_add_pcia_assoc(struct dt_node *np, uint32_t pcid)
{
const struct HDIF_common_hdr *hdr;
u32 size;
/*
* The SPPCRD doesn't contain all the affinity data, we have
* to dig it out of a core. I assume this is so that node
* affinity can be different for groups of cores within the
* chip, but for now we are going to ignore that
*/
hdr = get_hdif(&spira.ntuples.pcia, SPPCIA_HDIF_SIG);
if (!hdr)
return;
for_each_pcia(hdr) {
const struct sppcia_core_unique *id;
id = HDIF_get_idata(hdr, SPPCIA_IDATA_CORE_UNIQUE, &size);
if (!id || size < sizeof(*id))
continue;
if (be32_to_cpu(id->proc_chip_id) != pcid)
continue;
dt_add_property_cells(np, "ibm,ccm-node-id",
be32_to_cpu(id->ccm_node_id));
dt_add_property_cells(np, "ibm,hw-card-id",
be32_to_cpu(id->hw_card_id));
dt_add_property_cells(np, "ibm,hw-module-id",
be32_to_cpu(id->hw_module_id));
if (!dt_find_property(np, "ibm,dbob-id"))
dt_add_property_cells(np, "ibm,dbob-id",
be32_to_cpu(id->drawer_book_octant_blade_id));
if (proc_gen < proc_gen_p9) {
dt_add_property_cells(np, "ibm,mem-interleave-scope",
be32_to_cpu(id->memory_interleaving_scope));
}
return;
}
}
static bool add_xscom_sppcrd(uint64_t xscom_base)
{
const struct HDIF_common_hdr *hdif;
unsigned int i, vpd_sz;
const void *vpd;
struct dt_node *np, *vpd_node;
for_each_ntuple_idx(&spira.ntuples.proc_chip, hdif, i,
SPPCRD_HDIF_SIG) {
const struct sppcrd_chip_info *cinfo;
const struct spira_fru_id *fru_id = NULL;
unsigned int csize;
u32 ve, version;
cinfo = HDIF_get_idata(hdif, SPPCRD_IDATA_CHIP_INFO, &csize);
if (!CHECK_SPPTR(cinfo)) {
prerror("XSCOM: Bad ChipID data %d\n", i);
continue;
}
ve = be32_to_cpu(cinfo->verif_exist_flags) & CHIP_VERIFY_MASK;
ve >>= CHIP_VERIFY_SHIFT;
if (ve == CHIP_VERIFY_NOT_INSTALLED ||
ve == CHIP_VERIFY_UNUSABLE)
continue;
/* Create the XSCOM node */
np = add_xscom_node(xscom_base, cinfo);
if (!np)
continue;
dt_add_property_cells(np, DT_PRIVATE "sppcrd-index", i);
version = be16_to_cpu(hdif->version);
/* Version 0A has additional OCC related stuff */
if (version >= 0x000a) {
if (!dt_find_property(np, "ibm,dbob-id"))
dt_add_property_cells(np, "ibm,dbob-id",
be32_to_cpu(cinfo->dbob_id));
dt_add_property_cells(np, "ibm,occ-functional-state",
be32_to_cpu(cinfo->occ_state));
}
/* Add chip VPD */
vpd_node = dt_add_vpd_node(hdif, SPPCRD_IDATA_FRU_ID,
SPPCRD_IDATA_KW_VPD);
if (vpd_node)
dt_add_property_cells(vpd_node, "ibm,chip-id",
get_xscom_id(cinfo));
fru_id = HDIF_get_idata(hdif, SPPCRD_IDATA_FRU_ID, NULL);
if (fru_id)
slca_vpd_add_loc_code(np, be16_to_cpu(fru_id->slca_index));
/* Add module VPD on version A and later */
if (version >= 0x000a) {
vpd = HDIF_get_idata(hdif, SPPCRD_IDATA_MODULE_VPD,
&vpd_sz);
if (CHECK_SPPTR(vpd)) {
dt_add_property(np, "ibm,module-vpd", vpd,
vpd_sz);
vpd_data_parse(np, vpd, vpd_sz);
if (vpd_node)
dt_add_proc_vendor(vpd_node, vpd, vpd_sz);
}
}
/*
* Extract additional associativity information from
* the core data. Pick one core on that chip
*/
add_xscom_add_pcia_assoc(np, be32_to_cpu(cinfo->proc_chip_id));
/* Add PSI Host bridge */
add_psihb_node(np);
if (proc_gen >= proc_gen_p9) {
add_xive_node(np);
parse_i2c_devs(hdif, SPPCRD_IDATA_HOST_I2C, np);
add_vas_node(np, i);
add_ecid_data(hdif, np);
if (be32_to_cpu(cinfo->verif_exist_flags) & CHIP_VERIFY_MASTER_PROC)
dt_add_property(np, "primary", NULL, 0);
}
/*
* Add sw checkstop scom address (ibm,sw-checkstop-fir)
*
* The latest HDAT versions have sw checkstop scom address
* info. But not sure from which version onwards (at least
* HDAT spec do not mention that explicitly). Hence use the
* sppcrd struct size returned by HDIF_get_idata to figure out
* whether it contains sw checkstop scom address info. Also
* check if sw_xstop_fir_scom address is non-zero.
*/
if ((csize >= (offsetof(struct sppcrd_chip_info,
sw_xstop_fir_bitpos) + 1)) &&
cinfo->sw_xstop_fir_scom) {
uint8_t fir_bit = cinfo->sw_xstop_fir_bitpos;
if (!dt_find_property(dt_root, "ibm,sw-checkstop-fir"))
dt_add_property_cells(dt_root,
"ibm,sw-checkstop-fir",
be32_to_cpu(cinfo->sw_xstop_fir_scom),
fir_bit);
}
if (proc_gen >= proc_gen_p10) {
uint8_t primary_loc = cinfo->primary_topology_loc;
if (primary_loc >= CHIP_MAX_TOPOLOGY_ENTRIES) {
prerror("XSCOM: Invalid primary topology index %d\n",
primary_loc);
continue;
}
dt_add_property_cells(np, "ibm,primary-topology-index",
cinfo->topology_id_table[primary_loc]);
}
}
return i > 0;
}
static void add_xscom(void)
{
const void *ms_vpd;
const struct msvpd_pmover_bsr_synchro *pmbs;
unsigned int size;
uint64_t xscom_base;
ms_vpd = get_hdif(&spira.ntuples.ms_vpd, MSVPD_HDIF_SIG);
if (!ms_vpd) {
prerror("XSCOM: Can't find MS VPD\n");
return;
}
pmbs = HDIF_get_idata(ms_vpd, MSVPD_IDATA_PMOVER_SYNCHRO, &size);
if (!CHECK_SPPTR(pmbs) || size < sizeof(*pmbs)) {
prerror("XSCOM: absent or bad PMBS size %u @ %p\n", size, pmbs);
return;
}
if (!(be32_to_cpu(pmbs->flags) & MSVPD_PMS_FLAG_XSCOMBASE_VALID)) {
prerror("XSCOM: No XSCOM base in PMBS, using default\n");
return;
}
xscom_base = be64_to_cpu(pmbs->xscom_addr);
/* Get rid of the top bits */
xscom_base = cleanup_addr(xscom_base);
/* First, try the new proc_chip ntuples for chip data */
if (add_xscom_sppcrd(xscom_base))
return;
}
static void add_chiptod_node(unsigned int chip_id, int flags)
{
struct dt_node *node, *xscom_node;
const char *compat_str;
uint32_t addr, len;
if ((flags & CHIPTOD_ID_FLAGS_STATUS_MASK) !=
CHIPTOD_ID_FLAGS_STATUS_OK)
return;
xscom_node = find_xscom_for_chip(chip_id);
if (!xscom_node) {
prerror("CHIPTOD: No xscom for chiptod %d?\n", chip_id);
return;
}
addr = 0x40000;
len = 0x34;
switch(proc_gen) {
case proc_gen_p8:
compat_str = "ibm,power8-chiptod";
break;
case proc_gen_p9:
compat_str = "ibm,power9-chiptod";
break;
case proc_gen_p10:
compat_str = "ibm,power10-chiptod";
break;
default:
return;
}
prlog(PR_DEBUG, "CHIPTOD: Found on chip 0x%x %s\n", chip_id,
(flags & CHIPTOD_ID_FLAGS_PRIMARY) ? "[primary]" :
((flags & CHIPTOD_ID_FLAGS_SECONDARY) ? "[secondary]" : ""));
node = dt_new_addr(xscom_node, "chiptod", addr);
if (!node)
return;
dt_add_property_cells(node, "reg", addr, len);
dt_add_property_strings(node, "compatible", "ibm,power-chiptod",
compat_str);
if (flags & CHIPTOD_ID_FLAGS_PRIMARY)
dt_add_property(node, "primary", NULL, 0);
if (flags & CHIPTOD_ID_FLAGS_SECONDARY)
dt_add_property(node, "secondary", NULL, 0);
}
static bool add_chiptod_old(void)
{
const void *hdif;
unsigned int i;
bool found = false;
/*
* Locate chiptod ID structures in SPIRA
*/
if (!get_hdif(&spira.ntuples.chip_tod, "TOD "))
return found;
for_each_ntuple_idx(&spira.ntuples.chip_tod, hdif, i, "TOD ") {
const struct chiptod_chipid *id;
id = HDIF_get_idata(hdif, CHIPTOD_IDATA_CHIPID, NULL);
if (!CHECK_SPPTR(id)) {
prerror("CHIPTOD: Bad ChipID data %d\n", i);
continue;
}
add_chiptod_node(pcid_to_chip_id(be32_to_cpu(id->chip_id)),
be32_to_cpu(id->flags));
found = true;
}
return found;
}
static bool add_chiptod_new(void)
{
const void *hdif;
unsigned int i;
bool found = false;
/*
* Locate Proc Chip ID structures in SPIRA
*/
if (!get_hdif(&spira.ntuples.proc_chip, SPPCRD_HDIF_SIG))
return found;
for_each_ntuple_idx(&spira.ntuples.proc_chip, hdif, i,
SPPCRD_HDIF_SIG) {
const struct sppcrd_chip_info *cinfo;
const struct sppcrd_chip_tod *tinfo;
unsigned int size;
u32 ve, flags;
cinfo = HDIF_get_idata(hdif, SPPCRD_IDATA_CHIP_INFO, NULL);
if (!CHECK_SPPTR(cinfo)) {
prerror("CHIPTOD: Bad ChipID data %d\n", i);
continue;
}
ve = be32_to_cpu(cinfo->verif_exist_flags) & CHIP_VERIFY_MASK;
ve >>= CHIP_VERIFY_SHIFT;
if (ve == CHIP_VERIFY_NOT_INSTALLED ||
ve == CHIP_VERIFY_UNUSABLE)
continue;
tinfo = HDIF_get_idata(hdif, SPPCRD_IDATA_CHIP_TOD, &size);
if (!CHECK_SPPTR(tinfo)) {
prerror("CHIPTOD: Bad TOD data %d\n", i);
continue;
}
flags = be32_to_cpu(tinfo->flags);
/* The FSP may strip the chiptod info from HDAT; if we find
* a zero-ed out entry, assume that the chiptod is
* present, but we don't have any primary/secondary info. In
* this case, pick chip zero as the master.
*/
if (!size) {
flags = CHIPTOD_ID_FLAGS_STATUS_OK;
if (be32_to_cpu(cinfo->xscom_id) == 0x0)
flags |= CHIPTOD_ID_FLAGS_PRIMARY;
}
add_chiptod_node(get_xscom_id(cinfo), flags);
found = true;
}
return found;
}
static void add_nx_node(u32 gcid)
{
struct dt_node *nx;
u32 addr;
u32 size;
struct dt_node *xscom;
xscom = find_xscom_for_chip(gcid);
if (xscom == NULL) {
prerror("NX%d: did not found xscom node.\n", gcid);
return;
}
/*
* The NX register space is relatively self contained on P7+ but
* a bit more messy on P8. However it's all contained within the
* PB chiplet port 1 so we'll stick to that in the "reg" property
* and let the NX "driver" deal with the details.
*/
addr = 0x2010000;
size = 0x0004000;
nx = dt_new_addr(xscom, "nx", addr);
if (!nx)
return;
switch (proc_gen) {
case proc_gen_p8:
dt_add_property_strings(nx, "compatible", "ibm,power-nx",
"ibm,power8-nx");
break;
case proc_gen_p9:
case proc_gen_p10:
/* POWER9 NX is not software compatible with P8 NX */
dt_add_property_strings(nx, "compatible", "ibm,power9-nx");
break;
default:
return;
}
dt_add_property_cells(nx, "reg", addr, size);
}
static void add_nx(void)
{
unsigned int i;
void *hdif;
for_each_ntuple_idx(&spira.ntuples.proc_chip, hdif, i,
SPPCRD_HDIF_SIG) {
const struct sppcrd_chip_info *cinfo;
u32 ve;
cinfo = HDIF_get_idata(hdif, SPPCRD_IDATA_CHIP_INFO, NULL);
if (!CHECK_SPPTR(cinfo)) {
prerror("NX: Bad ChipID data %d\n", i);
continue;
}
ve = be32_to_cpu(cinfo->verif_exist_flags) & CHIP_VERIFY_MASK;
ve >>= CHIP_VERIFY_SHIFT;
if (ve == CHIP_VERIFY_NOT_INSTALLED ||
ve == CHIP_VERIFY_UNUSABLE)
continue;
if (cinfo->nx_state)
add_nx_node(get_xscom_id(cinfo));
}
}
static void add_nmmu(void)
{
struct dt_node *xscom, *nmmu;
u32 scom1, scom2;
u32 chip_id;
/* Nest MMU only exists on POWER9 or later */
if (proc_gen < proc_gen_p9)
return;
if (proc_gen == proc_gen_p10) {
scom1 = 0x2010c40;
scom2 = 0x3010c40;
} else
scom1 = 0x5012c40;
dt_for_each_compatible(dt_root, xscom, "ibm,xscom") {
nmmu = dt_new_addr(xscom, "nmmu", scom1);
dt_add_property_strings(nmmu, "compatible", "ibm,power9-nest-mmu");
dt_add_property_cells(nmmu, "reg", scom1, 0x20);
/*
* P10 has a second nMMU, a.k.a "south" nMMU.
* It exists only on P1 and P3
*/
if (proc_gen == proc_gen_p10) {
chip_id = __dt_get_chip_id(xscom);
if (chip_id != 2 && chip_id != 6)
continue;
nmmu = dt_new_addr(xscom, "nmmu", scom2);
dt_add_property_strings(nmmu, "compatible", "ibm,power9-nest-mmu");
dt_add_property_cells(nmmu, "reg", scom2, 0x20);
}