diff --git a/README.md b/README.md
index 11917382..f56ddbd0 100644
--- a/README.md
+++ b/README.md
@@ -10,6 +10,8 @@ longer workloads.
 * toplev now supports --sample-args to pass different arguments to the sample perf.
 The arguments need to be specified with + instead of - (--sample-args "+b")
 * toplev now automatically includes cycles with sampling
+* toplev now checks for event errata and automatically disables affected nodes, unless --ignore-errata is specified.
+* ucevents now supports Broadwell Xeon-D
 * jevents has now limited support for Uncore events
 * toplev updated to Ahmad Yasin's TopDown/TMAM 3.02:
 	- Tuned Memory_Bound vs Core_Bound threshold
diff --git a/jevents/rdpmc.c b/jevents/rdpmc.c
index 9bfbb25a..bba09115 100644
--- a/jevents/rdpmc.c
+++ b/jevents/rdpmc.c
@@ -123,13 +123,16 @@ unsigned long long rdpmc_read(struct rdpmc_ctx *ctx)
 	unsigned seq;
 	u64 offset; 
 	typeof (ctx->buf) buf = ctx->buf;
+	unsigned index;
 
 	do {
 		seq = buf->lock;
 		rmb();
-		/* XXX fallback */
-		val = __builtin_ia32_rdpmc(buf->index - 1);
+		index = buf->index;
 		offset = buf->offset;
+		if (index == 0) /* rdpmc not allowed */
+			return offset;
+		val = __builtin_ia32_rdpmc(index - 1);
 		rmb();
 	} while (buf->lock != seq);
 	return val + offset;
diff --git a/ocperf.py b/ocperf.py
index 5160c5c8..265dfa22 100755
--- a/ocperf.py
+++ b/ocperf.py
@@ -116,8 +116,8 @@ def checked_writemsr(self, msr, val, print_only = False):
     ("cp", "in_tx_cp=1", 0, ""))
 
 qualval_map = (
-    (r"c(mask=)?([0-9]+)", "cmask=%d", 24),
-    (r"(sa|sample-after)=([0-9x]+)", "period=%d", 0))
+    (r"c(mask=)?(0x[0-9a-f]+|[0-9]+)", "cmask=%d", 24),
+    (r"(sa|sample-after)=([0-9]+)", "period=%d", 0))
 
 # newe gets modified
 def convert_extra(extra, val, newe):
@@ -131,8 +131,8 @@ def convert_extra(extra, val, newe):
             m = re.match(j[0], extra)
             if m:
                 if j[2]:
-                    val |= int(m.group(2)) << j[2]
-                newe.append(j[1] % (int(m.group(2))))
+                    val |= int(m.group(2), 0) << j[2]
+                newe.append(j[1] % (int(m.group(2), 0)))
                 extra = extra[len(m.group(0)):]
                 found = True
                 break
@@ -253,6 +253,10 @@ def __init__(self, name, row):
         e.msr = None
         e.overflow = 0
         e.counter = "1" # dummy for toplev
+	if 'Errata' in row:
+	    e.errata = row['Errata']
+	else:
+	    e.errata = None
 
     #  {
     # "Unit": "CBO",
@@ -412,9 +416,14 @@ def read_table(self, r, m):
             if 'other' in m and m['other'] in row:
                 other = gethex('other') << 16
             else:
-                other = gethex('edge') << 18
+                other = 0
+            if 'edge' in m:
+                other |= gethex('edge') << 18
+            if 'any' in m:
                 other |= (gethex('any') | anyf) << 21
+            if 'cmask' in m:
                 other |= getdec('cmask') << 24
+            if 'invert' in m:
                 other |= gethex('invert') << 23
             val = code | (umask << 8) | other
             val &= EVMASK
@@ -427,6 +436,11 @@ def read_table(self, r, m):
             counter = get('counter')
             e.pname = "r%x" % (val,)
             e.newextra = ""
+            if other & ((1<<16)|(1<<17)):
+                if other & (1<<16):
+                    e.extra += "u"
+                if other & (1<<17):
+                    e.extra += "k"
             if ('msr_index' in m and m['msr_index'] in row
                     and get('msr_index') and get('msr_value')):
                 msrnum = gethex('msr_index')
@@ -454,9 +468,11 @@ def read_table(self, r, m):
                     d += " (Uses PEBS)"
                 else:
                     d = d.replace("(Precise Event)","") + " (Supports PEBS)"
+	    e.errata = None
             try:
                 if get('errata') != "null":
                     d += " Errata: " + get('errata')
+		    e.errata = get('errata')
             except KeyError:
                 pass
             e.desc = d
@@ -545,14 +561,15 @@ def __init__(self, name):
             'overflow': u'SampleAfterValue',
             'errata': u'Errata',
             'sav': u'SampleAfterValue',
+            'other': u'Other',
         }
         super(EmapNativeJSON, self).__init__()
         if name.find("JKT") >= 0:
             self.latego = True
         try:
             data = json.load(open(name, 'rb'))
-        except ValueError:
-            print >>sys.stderr, "Cannot open", name
+        except ValueError as e:
+            print >>sys.stderr, "Cannot open", name + ":", e.message
             return
         if u'PublicDescription' not in data[0]:
             mapping['desc'] = u'BriefDescription'
diff --git a/power_metrics.py b/power_metrics.py
index 33aba00e..ccf1af4a 100644
--- a/power_metrics.py
+++ b/power_metrics.py
@@ -52,10 +52,7 @@ class Setup:
     def __init__(self, r):
         r.metric(EnergyCores())
         r.metric(EnergyPackage())
-        perf = os.getenv("PERF")
-        if not perf:
-            perf = "perf"
-        if os.system(perf + " stat -e power/energy-ram/ >/dev/null 2>/dev/null true") == 0:
+        if os.path.exists("/sys/devices/power/events/energy-ram"):
             r.metric(EnergyRAM())
-        if os.system(perf + " stat -e power/energy-gpu/ >/dev/null 2>/dev/null true") == 0:
+        if os.path.exists("/sys/devices/power/events/energy-gpu"):
             r.metric(EnergyGPU())
diff --git a/tl-tester b/tl-tester
index 4da91879..894acfa6 100755
--- a/tl-tester
+++ b/tl-tester
@@ -62,6 +62,9 @@ EVENTMAP=${cpus[$DCPU]} FORCECPU=$DCPU $WRAP ./toplev.py --no-desc --stats -d $A
 grep :k log
 grep /k log
 EVENTMAP=${cpus[$DCPU]} FORCECPU=simple $WRAP ./toplev.py --no-desc -l1 $LOAD
+# check errata handling
+EVENTMAP=GenuineIntel-6-56 FORCECPU=bdw $WRAP ./toplev.py --no-desc --all $LOAD | tee log
+grep BDE70 log
 
 # test L1 uses a single group
 onegroup() {
diff --git a/toplev.py b/toplev.py
index 07d948cc..372b6110 100755
--- a/toplev.py
+++ b/toplev.py
@@ -118,6 +118,8 @@
 
 smt_mode = False
 
+errata_events = dict()
+
 perf = os.getenv("PERF")
 if not perf:
     perf = "perf"
@@ -305,6 +307,7 @@ def exe_dir():
 p.add_argument('--nodes', help='Include or exclude nodes (with + to add, ^ to remove, comma separated list, wildcards allowed)')
 p.add_argument('--quiet', help='Avoid unnecessary status output', action='store_true')
 p.add_argument('--bottleneck', help='Show critical bottleneck', action='store_true')
+p.add_argument('--ignore-errata', help='Do not disable events with errata', action='store_true')
 args, rest = p.parse_known_args()
 
 rest = [x for x in rest if x != "--"]
@@ -417,11 +420,13 @@ def wait(self):
 fixed_to_name = dict(zip(fixed_counters.values(), fixed_counters.keys()))
 
 def separator(x):
-    if x.startswith("cpu") or x.startswith("power") or x.startswith("uncore"):
+    if x.startswith("cpu"):
         return ""
     return ":"
 
 def add_filter_event(e):
+    if "/" in e and not e.startswith("cpu"):
+        return e
     s = separator(e)
     if not e.endswith(s + ring_filter):
         return e + s + ring_filter
@@ -435,6 +440,7 @@ def add_filter(s):
 notfound_cache = set()
 
 def raw_event(i, name="", period=False):
+    orig_i = i
     if i.count(".") > 0:
         if i in fixed_counters:
             return fixed_counters[i]
@@ -453,7 +459,7 @@ def raw_event(i, name="", period=False):
             print "Event", oi, "maps to multiple units. Ignored."
             return "dummy" # FIXME
         emap.update_event(e.output(noname=True), e)
-        # next two things should be moved somewhere else
+	# next three things should be moved somewhere else
         if i.startswith("uncore"):
             outgroup_events.add(i)
         if e.counter != cpu.standard_counters and not e.counter.startswith("Fixed"):
@@ -462,6 +468,8 @@ def raw_event(i, name="", period=False):
             # CPUs
             limited_counters[i] = int(e.counter.split(",")[0])
             limited_set.add(i)
+	if e.errata:
+	    errata_events[orig_i] = e.errata
     return i
 
 # generate list of converted raw events from events string
@@ -474,9 +482,13 @@ def mark_fixed(s):
         return "%s[F]" % s
     return s
 
-def pwrap(s, linelen=60, indent=""):
+def pwrap(s, linelen=70, indent=""):
     print indent + ("\n" + indent).join(textwrap.wrap(s, linelen, break_long_words=False))
 
+def pwrap_not_quiet(s, linelen=70, indent=""):
+    if not args.quiet:
+	pwrap(s, linelen, indent)
+
 def has(obj, name):
     return name in obj.__class__.__dict__
 
@@ -717,6 +729,12 @@ def do_execute(runner, events, out, rest, res, rev, valstats, env):
             l = inf.readline()
             if not l:
                 break
+            l = l.strip()
+
+            # some perf versions break CSV output lines incorrectly for power events
+            if l.endswith("Joules"):
+                l2 = inf.readline()
+                l = l + l2.strip()
         except exceptions.IOError:
              # handle pty EIO
              break
@@ -736,7 +754,7 @@ def do_execute(runner, events, out, rest, res, rev, valstats, env):
                         valstats = defaultdict(list)
                     prev_interval = interval
 
-	n = l.strip().split(";")
+	n = l.split(";")
 
         # filter out the empty unit field added by 3.14
         n = filter(lambda x: x != "" and x != "Joules", n)
@@ -921,6 +939,7 @@ class BadEvent:
     def __init__(self, name):
         self.event = name
 
+# XXX check for errata
 def sample_event(e):
     ev = emap.getevent(e.replace("_PS", ""))
     if not ev:
@@ -1042,6 +1061,19 @@ def _find_final(bn, level):
 def find_final(bn):
     return _find_final(bn, 0)
 
+pmu_does_not_exist = set()
+
+def missing_pmu(e):
+    m = re.match(r"([a-z0-9_]+)/", e)
+    if m:
+        pmu = m.group(1)
+        if pmu in pmu_does_not_exist:
+            return True
+        if not os.path.isdir("/sys/devices/%s" % pmu):
+            pmu_does_not_exist.add(pmu)
+            return True
+    return False
+
 class Runner:
     """Schedule measurements of event groups. Map events to groups."""
 
@@ -1139,6 +1171,9 @@ def add(self, objl, evnum, evlev, force=False):
     def collect(self):
         bad_nodes = set()
         bad_events = set()
+        unsup_nodes = set()
+	errata_nodes = set()
+	errata_names = set()
 	min_kernel = []
         for obj in self.olist:
             obj.evlevels = []
@@ -1146,23 +1181,41 @@ def collect(self):
             obj.evlist = [x[0] for x in obj.evlevels]
             obj.evnum = raw_events(obj.evlist)
             obj.nc = needed_counters(obj.evnum)
+
+	    # work arounds for lots of different problems
 	    unsup = [x for x in obj.evlist if unsup_event(x, unsup_events, min_kernel)]
             if any(unsup):
                 bad_nodes.add(obj)
                 bad_events |= set(unsup)
-        if len(bad_nodes) > 0 and not args.quiet:
+            unsup = [x for x in obj.evlist if missing_pmu(x)]
+            if any(unsup):
+                unsup_nodes.add(obj)
+	    errata = [errata_events[x] for x in obj.evlist if x in errata_events]
+	    if any(errata):
+		errata_nodes.add(obj)
+		errata_names |= set(errata)
+	if bad_nodes:
             if args.force_events:
-                pwrap("warning: Using --force-events. Nodes: " +
-		   " ".join([x.name for x in bad_nodes]) + " may be unreliable")
+		pwrap_not_quiet("warning: Using --force-events. Nodes: " +
+			" ".join([x.name for x in bad_nodes]) + " may be unreliable")
             else:
-	        pwrap("warning: removing " +
+		if not args.quiet:
+		    pwrap("warning: removing " +
 		       " ".join([x.name for x in bad_nodes]) +
 		       " due to unsupported events in kernel: " +
 		       " ".join(sorted(bad_events)), 80, "")
-	        if min_kernel:
-		    print "Fixed in kernel %d.%d" % (sorted(min_kernel, key=kv_to_key, reverse=True)[0])
-	        print "Use --force-events to override (may result in wrong measurements)"
+		    if min_kernel:
+			print "Fixed in kernel %d.%d" % (sorted(min_kernel, key=kv_to_key, reverse=True)[0])
+		    print "Use --force-events to override (may result in wrong measurements)"
                 self.olist = [x for x in self.olist if x not in bad_nodes]
+	if unsup_nodes:
+	    pwrap_not_quiet("Nodes " + " ".join(x.name for x in unsup_nodes) + " has unsupported PMUs")
+            self.olist = [x for x in self.olist if x not in unsup_nodes]
+	if errata_nodes and not args.ignore_errata:
+	    pwrap_not_quiet("Nodes " + " ".join(x.name for x in errata_nodes) + " have errata " +
+			" ".join(errata_names) + " and were disabled. " +
+			"Override with --ignore-errata")
+	    self.olist = [x for x in self.olist if x in errata_nodes]
 
     # fit events into available counters
     # simple first fit algorithm
diff --git a/ucevent/RUN-ALL b/ucevent/RUN-ALL
index a111e40a..5fcef91f 100755
--- a/ucevent/RUN-ALL
+++ b/ucevent/RUN-ALL
@@ -1,5 +1,11 @@
 #!/bin/sh
 
+CPULIST="${CPULIST:-jkt ivt hsx bdxde}"
+
+for cpu in $CPULIST ; do
+
+export FORCECPU=$cpu
+
 for i in CHECK-* SANITY-ALL MOCK-ALL ; do 
 	echo $i 
 	./$i
@@ -7,3 +13,6 @@ for i in CHECK-* SANITY-ALL MOCK-ALL ; do
 done
 
 ./uctester | tee res-tester
+
+
+done
diff --git a/ucevent/bdxde_aux.py b/ucevent/bdxde_aux.py
new file mode 120000
index 00000000..7533e4a7
--- /dev/null
+++ b/ucevent/bdxde_aux.py
@@ -0,0 +1 @@
+jkt_aux.py
\ No newline at end of file
diff --git a/ucevent/bdxde_extra.py b/ucevent/bdxde_extra.py
new file mode 100644
index 00000000..c440484e
--- /dev/null
+++ b/ucevent/bdxde_extra.py
@@ -0,0 +1,3 @@
+# empty for now
+
+extra_derived = {}
diff --git a/ucevent/bdxde_uc.py b/ucevent/bdxde_uc.py
new file mode 100644
index 00000000..f8e5bcd4
--- /dev/null
+++ b/ucevent/bdxde_uc.py
@@ -0,0 +1,9617 @@
+# BDXDE bdxde_uc_events.v1.00p bdxde_uc_derived.v1.00p 
+
+# aliases
+aliases = {
+     "PCUFilter": "PCU_MSR_PMON_BOX_FILTER",
+     "HA_AddrMatch0": "HAn_PCI_PMON_BOX_ADDRMATCH0",
+     "IRPFilter": "IRP_PCI_PMON_BOX_FILTER",
+     "HA_AddrMatch1": "HAn_PCI_PMON_BOX_ADDRMATCH1",
+     "HA_OpcodeMatch": "HAn_PCI_PMON_BOX_OPCODEMATCH",
+     "CBoFilter0": "Cn_MSR_PMON_BOX_FILTER",
+     "UBoxFilter": "U_MSR_PMON_BOX_FILTER",
+     "CBoFilter1": "Cn_MSR_PMON_BOX_FILTER1",
+}
+
+events = {
+     
+# UBOX:
+     "UBOX.EVENT_MSG": {
+          "Box": "UBOX",
+          "Category": "UBOX EVENT_MSG Events",
+          "Counters": "0-1",
+          "Defn": "Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+          "Desc": "VLW Received",
+          "EvSel": 66,
+          "ExtSel": "",
+     },
+     "UBOX.EVENT_MSG.DOORBELL_RCVD": {
+          "Box": "UBOX",
+          "Category": "UBOX EVENT_MSG Events",
+          "Counters": "0-1",
+          "Defn": "Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+          "Desc": "VLW Received",
+          "EvSel": 66,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "UBOX.PHOLD_CYCLES": {
+          "Box": "UBOX",
+          "Category": "UBOX PHOLD Events",
+          "Counters": "0-1",
+          "Defn": "PHOLD cycles.  Filter from source CoreID.",
+          "Desc": "Cycles PHOLD Assert to Ack",
+          "EvSel": 69,
+          "ExtSel": "",
+     },
+     "UBOX.PHOLD_CYCLES.ASSERT_TO_ACK": {
+          "Box": "UBOX",
+          "Category": "UBOX PHOLD Events",
+          "Counters": "0-1",
+          "Defn": "PHOLD cycles.  Filter from source CoreID.",
+          "Desc": "Cycles PHOLD Assert to Ack",
+          "EvSel": 69,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "UBOX.RACU_REQUESTS": {
+          "Box": "UBOX",
+          "Category": "UBOX RACU Events",
+          "Counters": "0-1",
+          "Defn": "Number outstanding register requests within message channel tracker",
+          "Desc": "RACU Request",
+          "EvSel": 70,
+          "ExtSel": "",
+     },
+     
+# R2PCIe:
+     "R2PCIe.CLOCKTICKS": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe UCLK Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of uclks in the R2PCIe uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
+          "Desc": "Number of uclks in domain",
+          "EvSel": 1,
+          "ExtSel": "",
+     },
+     "R2PCIe.IIO_CREDIT": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe IIO Credit Events",
+          "Counters": "0-1",
+          "EvSel": 45,
+          "ExtSel": "",
+          "MaxIncCyc": 4,
+     },
+     "R2PCIe.IIO_CREDIT.ISOCH_QPI0": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe IIO Credit Events",
+          "Counters": "0-1",
+          "EvSel": 45,
+          "ExtSel": "",
+          "MaxIncCyc": 4,
+          "Umask": "bxxxxx1xx",
+     },
+     "R2PCIe.IIO_CREDIT.ISOCH_QPI1": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe IIO Credit Events",
+          "Counters": "0-1",
+          "EvSel": 45,
+          "ExtSel": "",
+          "MaxIncCyc": 4,
+          "Umask": "bxxxx1xxx",
+     },
+     "R2PCIe.IIO_CREDIT.PRQ_QPI0": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe IIO Credit Events",
+          "Counters": "0-1",
+          "EvSel": 45,
+          "ExtSel": "",
+          "MaxIncCyc": 4,
+          "Umask": "bxxxxxxx1",
+     },
+     "R2PCIe.IIO_CREDIT.PRQ_QPI1": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe IIO Credit Events",
+          "Counters": "0-1",
+          "EvSel": 45,
+          "ExtSel": "",
+          "MaxIncCyc": 4,
+          "Umask": "bxxxxxx1x",
+     },
+     "R2PCIe.RING_AD_USED": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 AD Ring in Use",
+          "EvSel": 7,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+     },
+     "R2PCIe.RING_AD_USED.CCW_ODD": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 AD Ring in Use",
+          "EvSel": 7,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxx1xxx",
+     },
+     "R2PCIe.RING_AD_USED.ALL": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 AD Ring in Use",
+          "EvSel": 7,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "b00001111",
+     },
+     "R2PCIe.RING_AD_USED.CW_ODD": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 AD Ring in Use",
+          "EvSel": 7,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxxxx1x",
+     },
+     "R2PCIe.RING_AD_USED.CCW_EVEN": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 AD Ring in Use",
+          "EvSel": 7,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxxx1xx",
+     },
+     "R2PCIe.RING_AD_USED.CW": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 AD Ring in Use",
+          "EvSel": 7,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "b00000011",
+     },
+     "R2PCIe.RING_AD_USED.CW_EVEN": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 AD Ring in Use",
+          "EvSel": 7,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxxxxx1",
+     },
+     "R2PCIe.RING_AD_USED.CCW": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 AD Ring in Use",
+          "EvSel": 7,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "b00001100",
+     },
+     "R2PCIe.RING_AK_BOUNCES": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when a request destined for the AK ingress bounced.",
+          "Desc": "AK Ingress Bounced",
+          "EvSel": 18,
+          "ExtSel": "",
+     },
+     "R2PCIe.RING_AK_BOUNCES.DN": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when a request destined for the AK ingress bounced.",
+          "Desc": "AK Ingress Bounced",
+          "EvSel": 18,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "R2PCIe.RING_AK_BOUNCES.UP": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when a request destined for the AK ingress bounced.",
+          "Desc": "AK Ingress Bounced",
+          "EvSel": 18,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "R2PCIe.RING_AK_USED": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 AK Ring in Use",
+          "EvSel": 8,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+     },
+     "R2PCIe.RING_AK_USED.CW_ODD": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 AK Ring in Use",
+          "EvSel": 8,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxxxx1x",
+     },
+     "R2PCIe.RING_AK_USED.CCW_EVEN": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 AK Ring in Use",
+          "EvSel": 8,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxxx1xx",
+     },
+     "R2PCIe.RING_AK_USED.CCW_ODD": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 AK Ring in Use",
+          "EvSel": 8,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxx1xxx",
+     },
+     "R2PCIe.RING_AK_USED.ALL": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 AK Ring in Use",
+          "EvSel": 8,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "b00001111",
+     },
+     "R2PCIe.RING_AK_USED.CW_EVEN": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 AK Ring in Use",
+          "EvSel": 8,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxxxxx1",
+     },
+     "R2PCIe.RING_AK_USED.CCW": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 AK Ring in Use",
+          "EvSel": 8,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "b00001100",
+     },
+     "R2PCIe.RING_AK_USED.CW": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 AK Ring in Use",
+          "EvSel": 8,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "b00000011",
+     },
+     "R2PCIe.RING_BL_USED": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 BL Ring in Use",
+          "EvSel": 9,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+     },
+     "R2PCIe.RING_BL_USED.CCW_EVEN": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 BL Ring in Use",
+          "EvSel": 9,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxxx1xx",
+     },
+     "R2PCIe.RING_BL_USED.CW_ODD": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 BL Ring in Use",
+          "EvSel": 9,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxxxx1x",
+     },
+     "R2PCIe.RING_BL_USED.ALL": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 BL Ring in Use",
+          "EvSel": 9,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "b00001111",
+     },
+     "R2PCIe.RING_BL_USED.CCW_ODD": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 BL Ring in Use",
+          "EvSel": 9,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxx1xxx",
+     },
+     "R2PCIe.RING_BL_USED.CCW": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 BL Ring in Use",
+          "EvSel": 9,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "b00001100",
+     },
+     "R2PCIe.RING_BL_USED.CW_EVEN": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 BL Ring in Use",
+          "EvSel": 9,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxxxxx1",
+     },
+     "R2PCIe.RING_BL_USED.CW": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "R2 BL Ring in Use",
+          "EvSel": 9,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "b00000011",
+     },
+     "R2PCIe.RING_IV_USED": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+          "Desc": "R2 IV Ring in Use",
+          "EvSel": 10,
+          "ExtSel": "",
+          "Notes": "IV messages are split into two parts.  In any cycle, a ring stop can see up to one (half-)packet moving in the CW direction and one (half-)packet moving in the CCW direction.",
+     },
+     "R2PCIe.RING_IV_USED.CCW": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+          "Desc": "R2 IV Ring in Use",
+          "EvSel": 10,
+          "ExtSel": "",
+          "Notes": "IV messages are split into two parts.  In any cycle, a ring stop can see up to one (half-)packet moving in the CW direction and one (half-)packet moving in the CCW direction.",
+          "Umask": "b00001100",
+     },
+     "R2PCIe.RING_IV_USED.ANY": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+          "Desc": "R2 IV Ring in Use",
+          "EvSel": 10,
+          "ExtSel": "",
+          "Notes": "IV messages are split into two parts.  In any cycle, a ring stop can see up to one (half-)packet moving in the CW direction and one (half-)packet moving in the CCW direction.",
+          "Umask": "b00001111",
+     },
+     "R2PCIe.RING_IV_USED.CW": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+          "Desc": "R2 IV Ring in Use",
+          "EvSel": 10,
+          "ExtSel": "",
+          "Notes": "IV messages are split into two parts.  In any cycle, a ring stop can see up to one (half-)packet moving in the CW direction and one (half-)packet moving in the CCW direction.",
+          "Umask": "b00000011",
+     },
+     "R2PCIe.RxR_CYCLES_NE": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe INGRESS Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
+          "Desc": "Ingress Cycles Not Empty",
+          "EvSel": 16,
+          "ExtSel": "",
+     },
+     "R2PCIe.RxR_CYCLES_NE.NCB": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe INGRESS Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
+          "Desc": "Ingress Cycles Not Empty",
+          "EvSel": 16,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "R2PCIe.RxR_CYCLES_NE.NCS": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe INGRESS Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
+          "Desc": "Ingress Cycles Not Empty",
+          "EvSel": 16,
+          "ExtSel": "",
+          "Umask": "bxx1xxxxx",
+     },
+     "R2PCIe.RxR_INSERTS": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe INGRESS Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of allocations into the R2PCIe Ingress.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
+          "Desc": "Ingress Allocations",
+          "EvSel": 17,
+          "ExtSel": "",
+     },
+     "R2PCIe.RxR_INSERTS.NCS": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe INGRESS Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of allocations into the R2PCIe Ingress.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
+          "Desc": "Ingress Allocations",
+          "EvSel": 17,
+          "ExtSel": "",
+          "Umask": "bxx1xxxxx",
+     },
+     "R2PCIe.RxR_INSERTS.NCB": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe INGRESS Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of allocations into the R2PCIe Ingress.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
+          "Desc": "Ingress Allocations",
+          "EvSel": 17,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "R2PCIe.RxR_OCCUPANCY": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe INGRESS Events",
+          "Counters": 0,
+          "Defn": "Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.",
+          "Desc": "Ingress Occupancy Accumulator",
+          "EvSel": 19,
+          "ExtSel": "",
+          "MaxIncCyc": 24,
+          "SubCtr": 1,
+     },
+     "R2PCIe.RxR_OCCUPANCY.DRS": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe INGRESS Events",
+          "Counters": 0,
+          "Defn": "Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.",
+          "Desc": "Ingress Occupancy Accumulator",
+          "EvSel": 19,
+          "ExtSel": "",
+          "MaxIncCyc": 24,
+          "SubCtr": 1,
+          "Umask": "b00001000",
+     },
+     "R2PCIe.SBO0_CREDITS_ACQUIRED": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe SBO Credit Events",
+          "Counters": "0-1",
+          "Defn": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
+          "Desc": "SBo0 Credits Acquired",
+          "EvSel": 40,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+     },
+     "R2PCIe.SBO0_CREDITS_ACQUIRED.AD": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe SBO Credit Events",
+          "Counters": "0-1",
+          "Defn": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
+          "Desc": "SBo0 Credits Acquired",
+          "EvSel": 40,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Umask": "bxxxxxxx1",
+     },
+     "R2PCIe.SBO0_CREDITS_ACQUIRED.BL": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe SBO Credit Events",
+          "Counters": "0-1",
+          "Defn": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
+          "Desc": "SBo0 Credits Acquired",
+          "EvSel": 40,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Umask": "bxxxxxx1x",
+     },
+     "R2PCIe.STALL_NO_SBO_CREDIT": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe SBO Credit Events",
+          "Counters": "0-1",
+          "Defn": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+          "Desc": "Stall on No Sbo Credits",
+          "EvSel": 44,
+          "ExtSel": "",
+          "MaxIncCyc": 4,
+     },
+     "R2PCIe.STALL_NO_SBO_CREDIT.SBO0_AD": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe SBO Credit Events",
+          "Counters": "0-1",
+          "Defn": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+          "Desc": "Stall on No Sbo Credits",
+          "EvSel": 44,
+          "ExtSel": "",
+          "MaxIncCyc": 4,
+          "Umask": "bxxxxxxx1",
+     },
+     "R2PCIe.STALL_NO_SBO_CREDIT.SBO0_BL": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe SBO Credit Events",
+          "Counters": "0-1",
+          "Defn": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+          "Desc": "Stall on No Sbo Credits",
+          "EvSel": 44,
+          "ExtSel": "",
+          "MaxIncCyc": 4,
+          "Umask": "bxxxxx1xx",
+     },
+     "R2PCIe.STALL_NO_SBO_CREDIT.SBO1_AD": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe SBO Credit Events",
+          "Counters": "0-1",
+          "Defn": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+          "Desc": "Stall on No Sbo Credits",
+          "EvSel": 44,
+          "ExtSel": "",
+          "MaxIncCyc": 4,
+          "Umask": "bxxxxxx1x",
+     },
+     "R2PCIe.STALL_NO_SBO_CREDIT.SBO1_BL": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe SBO Credit Events",
+          "Counters": "0-1",
+          "Defn": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+          "Desc": "Stall on No Sbo Credits",
+          "EvSel": 44,
+          "ExtSel": "",
+          "MaxIncCyc": 4,
+          "Umask": "bxxxx1xxx",
+     },
+     "R2PCIe.TxR_CYCLES_FULL": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe EGRESS Events",
+          "Counters": 0,
+          "Defn": "Counts the number of cycles when the R2PCIe Egress buffer is full.",
+          "Desc": "Egress Cycles Full",
+          "EvSel": 37,
+          "ExtSel": "",
+     },
+     "R2PCIe.TxR_CYCLES_FULL.AK": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe EGRESS Events",
+          "Counters": 0,
+          "Defn": "Counts the number of cycles when the R2PCIe Egress buffer is full.",
+          "Desc": "Egress Cycles Full",
+          "EvSel": 37,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "R2PCIe.TxR_CYCLES_FULL.BL": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe EGRESS Events",
+          "Counters": 0,
+          "Defn": "Counts the number of cycles when the R2PCIe Egress buffer is full.",
+          "Desc": "Egress Cycles Full",
+          "EvSel": 37,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "R2PCIe.TxR_CYCLES_FULL.AD": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe EGRESS Events",
+          "Counters": 0,
+          "Defn": "Counts the number of cycles when the R2PCIe Egress buffer is full.",
+          "Desc": "Egress Cycles Full",
+          "EvSel": 37,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "R2PCIe.TxR_CYCLES_NE": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe EGRESS Events",
+          "Counters": 0,
+          "Defn": "Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+          "Desc": "Egress Cycles Not Empty",
+          "EvSel": 35,
+          "ExtSel": "",
+     },
+     "R2PCIe.TxR_CYCLES_NE.AD": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe EGRESS Events",
+          "Counters": 0,
+          "Defn": "Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+          "Desc": "Egress Cycles Not Empty",
+          "EvSel": 35,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "R2PCIe.TxR_CYCLES_NE.AK": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe EGRESS Events",
+          "Counters": 0,
+          "Defn": "Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+          "Desc": "Egress Cycles Not Empty",
+          "EvSel": 35,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "R2PCIe.TxR_CYCLES_NE.BL": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe EGRESS Events",
+          "Counters": 0,
+          "Defn": "Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+          "Desc": "Egress Cycles Not Empty",
+          "EvSel": 35,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "R2PCIe.TxR_NACK_CW": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe EGRESS Events",
+          "Counters": "0-1",
+          "Desc": "Egress CCW NACK",
+          "EvSel": 38,
+          "ExtSel": "",
+     },
+     "R2PCIe.TxR_NACK_CW.UP_BL": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe EGRESS Events",
+          "Counters": "0-1",
+          "Desc": "Egress CCW NACK",
+          "EvSel": 38,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "R2PCIe.TxR_NACK_CW.DN_AD": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe EGRESS Events",
+          "Counters": "0-1",
+          "Desc": "Egress CCW NACK",
+          "EvSel": 38,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "R2PCIe.TxR_NACK_CW.UP_AK": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe EGRESS Events",
+          "Counters": "0-1",
+          "Desc": "Egress CCW NACK",
+          "EvSel": 38,
+          "ExtSel": "",
+          "Umask": "bxx1xxxxx",
+     },
+     "R2PCIe.TxR_NACK_CW.UP_AD": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe EGRESS Events",
+          "Counters": "0-1",
+          "Desc": "Egress CCW NACK",
+          "EvSel": 38,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "R2PCIe.TxR_NACK_CW.DN_AK": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe EGRESS Events",
+          "Counters": "0-1",
+          "Desc": "Egress CCW NACK",
+          "EvSel": 38,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "R2PCIe.TxR_NACK_CW.DN_BL": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe EGRESS Events",
+          "Counters": "0-1",
+          "Desc": "Egress CCW NACK",
+          "EvSel": 38,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     
+# CBO:
+     "CBO.BOUNCE_CONTROL": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Desc": "Bounce Control",
+          "EvSel": 10,
+          "ExtSel": "",
+     },
+     "CBO.CLOCKTICKS": {
+          "Box": "CBO",
+          "Category": "CBO UCLK Events",
+          "Counters": "0-3",
+          "Desc": "Uncore Clocks",
+          "EvSel": 0,
+          "ExtSel": "",
+     },
+     "CBO.COUNTER0_OCCUPANCY": {
+          "Box": "CBO",
+          "Category": "CBO OCCUPANCY Events",
+          "Counters": "0-3",
+          "Defn": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0.   The filtering available is found in the control register - threshold, invert and edge detect.   E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
+          "Desc": "Counter 0 Occupancy",
+          "EvSel": 31,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "SubCtr": 1,
+     },
+     "CBO.FAST_ASSERTED": {
+          "Box": "CBO",
+          "Category": "CBO EGRESS Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of cycles either the local distress or incoming distress signals are asserted.  Incoming distress includes both up and dn.",
+          "Desc": "FaST wire asserted",
+          "EvSel": 9,
+          "ExtSel": "",
+     },
+     "CBO.LLC_LOOKUP": {
+          "Box": "CBO",
+          "Category": "CBO CACHE Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.",
+          "Desc": "Cache Lookups",
+          "EvSel": 52,
+          "ExtSel": "",
+          "Notes": "Bit 0 of the umask must always be set for this event.  This allows us to match a given state (or states).  The state is programmed in Cn_MSR_PMON_BOX_FILTER.state.   The state field is a bit mask, so you can select (and monitor) multiple states at a time.  0 = I (miss), 1 = S, 2 = E, 3 = M, 4 = F.  For example, if you wanted to monitor F and S hits, you could set 10010b in the 5-bit state field.   To monitor any lookup, set the field to 0x1F.",
+     },
+     "CBO.LLC_LOOKUP.ANY": {
+          "Box": "CBO",
+          "Category": "CBO CACHE Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.",
+          "Desc": "Cache Lookups",
+          "EvSel": 52,
+          "ExtSel": "",
+          "Notes": "Bit 0 of the umask must always be set for this event.  This allows us to match a given state (or states).  The state is programmed in Cn_MSR_PMON_BOX_FILTER.state.   The state field is a bit mask, so you can select (and monitor) multiple states at a time.  0 = I (miss), 1 = S, 2 = E, 3 = M, 4 = F.  For example, if you wanted to monitor F and S hits, you could set 10010b in the 5-bit state field.   To monitor any lookup, set the field to 0x1F.",
+          "Umask": "b00010001",
+     },
+     "CBO.LLC_LOOKUP.NID": {
+          "Box": "CBO",
+          "Category": "CBO CACHE Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.",
+          "Desc": "Cache Lookups",
+          "EvSel": 52,
+          "ExtSel": "",
+          "Notes": "Bit 0 of the umask must always be set for this event.  This allows us to match a given state (or states).  The state is programmed in Cn_MSR_PMON_BOX_FILTER.state.   The state field is a bit mask, so you can select (and monitor) multiple states at a time.  0 = I (miss), 1 = S, 2 = E, 3 = M, 4 = F.  For example, if you wanted to monitor F and S hits, you could set 10010b in the 5-bit state field.   To monitor any lookup, set the field to 0x1F.",
+          "Umask": "b01000001",
+     },
+     "CBO.LLC_LOOKUP.READ": {
+          "Box": "CBO",
+          "Category": "CBO CACHE Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.",
+          "Desc": "Cache Lookups",
+          "EvSel": 52,
+          "ExtSel": "",
+          "Notes": "Bit 0 of the umask must always be set for this event.  This allows us to match a given state (or states).  The state is programmed in Cn_MSR_PMON_BOX_FILTER.state.   The state field is a bit mask, so you can select (and monitor) multiple states at a time.  0 = I (miss), 1 = S, 2 = E, 3 = M, 4 = F.  For example, if you wanted to monitor F and S hits, you could set 10010b in the 5-bit state field.   To monitor any lookup, set the field to 0x1F.",
+          "Umask": "b00100001",
+     },
+     "CBO.LLC_LOOKUP.DATA_READ": {
+          "Box": "CBO",
+          "Category": "CBO CACHE Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.",
+          "Desc": "Cache Lookups",
+          "EvSel": 52,
+          "ExtSel": "",
+          "Notes": "Bit 0 of the umask must always be set for this event.  This allows us to match a given state (or states).  The state is programmed in Cn_MSR_PMON_BOX_FILTER.state.   The state field is a bit mask, so you can select (and monitor) multiple states at a time.  0 = I (miss), 1 = S, 2 = E, 3 = M, 4 = F.  For example, if you wanted to monitor F and S hits, you could set 10010b in the 5-bit state field.   To monitor any lookup, set the field to 0x1F.",
+          "Umask": "b00000011",
+     },
+     "CBO.LLC_LOOKUP.WRITE": {
+          "Box": "CBO",
+          "Category": "CBO CACHE Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.",
+          "Desc": "Cache Lookups",
+          "EvSel": 52,
+          "ExtSel": "",
+          "Notes": "Bit 0 of the umask must always be set for this event.  This allows us to match a given state (or states).  The state is programmed in Cn_MSR_PMON_BOX_FILTER.state.   The state field is a bit mask, so you can select (and monitor) multiple states at a time.  0 = I (miss), 1 = S, 2 = E, 3 = M, 4 = F.  For example, if you wanted to monitor F and S hits, you could set 10010b in the 5-bit state field.   To monitor any lookup, set the field to 0x1F.",
+          "Umask": "b00000101",
+     },
+     "CBO.LLC_LOOKUP.REMOTE_SNOOP": {
+          "Box": "CBO",
+          "Category": "CBO CACHE Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.",
+          "Desc": "Cache Lookups",
+          "EvSel": 52,
+          "ExtSel": "",
+          "Notes": "Bit 0 of the umask must always be set for this event.  This allows us to match a given state (or states).  The state is programmed in Cn_MSR_PMON_BOX_FILTER.state.   The state field is a bit mask, so you can select (and monitor) multiple states at a time.  0 = I (miss), 1 = S, 2 = E, 3 = M, 4 = F.  For example, if you wanted to monitor F and S hits, you could set 10010b in the 5-bit state field.   To monitor any lookup, set the field to 0x1F.",
+          "Umask": "b00001001",
+     },
+     "CBO.LLC_VICTIMS": {
+          "Box": "CBO",
+          "Category": "CBO CACHE Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+          "Desc": "Lines Victimized",
+          "EvSel": 55,
+          "ExtSel": "",
+     },
+     "CBO.LLC_VICTIMS.NID": {
+          "Box": "CBO",
+          "Category": "CBO CACHE Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+          "Desc": "Lines Victimized",
+          "EvSel": 55,
+          "ExtSel": "",
+          "Umask": "bx1xxxxxx",
+     },
+     "CBO.LLC_VICTIMS.I_STATE": {
+          "Box": "CBO",
+          "Category": "CBO CACHE Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+          "Desc": "Lines Victimized",
+          "EvSel": 55,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "CBO.LLC_VICTIMS.M_STATE": {
+          "Box": "CBO",
+          "Category": "CBO CACHE Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+          "Desc": "Lines Victimized",
+          "EvSel": 55,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "CBO.LLC_VICTIMS.MISS": {
+          "Box": "CBO",
+          "Category": "CBO CACHE Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+          "Desc": "Lines Victimized",
+          "EvSel": 55,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "CBO.LLC_VICTIMS.F_STATE": {
+          "Box": "CBO",
+          "Category": "CBO CACHE Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+          "Desc": "Lines Victimized",
+          "EvSel": 55,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "CBO.LLC_VICTIMS.E_STATE": {
+          "Box": "CBO",
+          "Category": "CBO CACHE Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+          "Desc": "Lines Victimized",
+          "EvSel": 55,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "CBO.MISC": {
+          "Box": "CBO",
+          "Category": "CBO MISC Events",
+          "Counters": "0-3",
+          "Defn": "Miscellaneous events in the Cbo.",
+          "Desc": "Cbo Misc",
+          "EvSel": 57,
+          "ExtSel": "",
+     },
+     "CBO.MISC.WC_ALIASING": {
+          "Box": "CBO",
+          "Category": "CBO MISC Events",
+          "Counters": "0-3",
+          "Defn": "Miscellaneous events in the Cbo.",
+          "Desc": "Cbo Misc",
+          "EvSel": 57,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "CBO.MISC.RSPI_WAS_FSE": {
+          "Box": "CBO",
+          "Category": "CBO MISC Events",
+          "Counters": "0-3",
+          "Defn": "Miscellaneous events in the Cbo.",
+          "Desc": "Cbo Misc",
+          "EvSel": 57,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "CBO.MISC.RFO_HIT_S": {
+          "Box": "CBO",
+          "Category": "CBO MISC Events",
+          "Counters": "0-3",
+          "Defn": "Miscellaneous events in the Cbo.",
+          "Desc": "Cbo Misc",
+          "EvSel": 57,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "CBO.MISC.STARTED": {
+          "Box": "CBO",
+          "Category": "CBO MISC Events",
+          "Counters": "0-3",
+          "Defn": "Miscellaneous events in the Cbo.",
+          "Desc": "Cbo Misc",
+          "EvSel": 57,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "CBO.MISC.CVZERO_PREFETCH_MISS": {
+          "Box": "CBO",
+          "Category": "CBO MISC Events",
+          "Counters": "0-3",
+          "Defn": "Miscellaneous events in the Cbo.",
+          "Desc": "Cbo Misc",
+          "EvSel": 57,
+          "ExtSel": "",
+          "Umask": "bxx1xxxxx",
+     },
+     "CBO.MISC.CVZERO_PREFETCH_VICTIM": {
+          "Box": "CBO",
+          "Category": "CBO MISC Events",
+          "Counters": "0-3",
+          "Defn": "Miscellaneous events in the Cbo.",
+          "Desc": "Cbo Misc",
+          "EvSel": 57,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "CBO.RING_AD_USED": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "AD Ring In Use",
+          "EvSel": 27,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+     },
+     "CBO.RING_AD_USED.DOWN_ODD": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "AD Ring In Use",
+          "EvSel": 27,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+          "Umask": "bxxxx1xxx",
+     },
+     "CBO.RING_AD_USED.UP_ODD": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "AD Ring In Use",
+          "EvSel": 27,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+          "Umask": "bxxxxxx1x",
+     },
+     "CBO.RING_AD_USED.ALL": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "AD Ring In Use",
+          "EvSel": 27,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+          "Umask": "b00001111",
+     },
+     "CBO.RING_AD_USED.CCW": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "AD Ring In Use",
+          "EvSel": 27,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+          "Umask": "b00001100",
+     },
+     "CBO.RING_AD_USED.DOWN_EVEN": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "AD Ring In Use",
+          "EvSel": 27,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+          "Umask": "bxxxxx1xx",
+     },
+     "CBO.RING_AD_USED.CW": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "AD Ring In Use",
+          "EvSel": 27,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+          "Umask": "b00000011",
+     },
+     "CBO.RING_AD_USED.UP_EVEN": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "AD Ring In Use",
+          "EvSel": 27,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+          "Umask": "bxxxxxxx1",
+     },
+     "CBO.RING_AK_USED": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "AK Ring In Use",
+          "EvSel": 28,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+     },
+     "CBO.RING_AK_USED.CCW": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "AK Ring In Use",
+          "EvSel": 28,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+          "Umask": "b00001100",
+     },
+     "CBO.RING_AK_USED.UP_EVEN": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "AK Ring In Use",
+          "EvSel": 28,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+          "Umask": "bxxxxxxx1",
+     },
+     "CBO.RING_AK_USED.CW": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "AK Ring In Use",
+          "EvSel": 28,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+          "Umask": "b00000011",
+     },
+     "CBO.RING_AK_USED.DOWN_EVEN": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "AK Ring In Use",
+          "EvSel": 28,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+          "Umask": "bxxxxx1xx",
+     },
+     "CBO.RING_AK_USED.UP_ODD": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "AK Ring In Use",
+          "EvSel": 28,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+          "Umask": "bxxxxxx1x",
+     },
+     "CBO.RING_AK_USED.ALL": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "AK Ring In Use",
+          "EvSel": 28,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+          "Umask": "b00001111",
+     },
+     "CBO.RING_AK_USED.DOWN_ODD": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "AK Ring In Use",
+          "EvSel": 28,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+          "Umask": "bxxxx1xxx",
+     },
+     "CBO.RING_BL_USED": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "BL Ring in Use",
+          "EvSel": 29,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+     },
+     "CBO.RING_BL_USED.UP_ODD": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "BL Ring in Use",
+          "EvSel": 29,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+          "Umask": "bxxxxxx1x",
+     },
+     "CBO.RING_BL_USED.ALL": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "BL Ring in Use",
+          "EvSel": 29,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+          "Umask": "b00001111",
+     },
+     "CBO.RING_BL_USED.DOWN_ODD": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "BL Ring in Use",
+          "EvSel": 29,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+          "Umask": "bxxxx1xxx",
+     },
+     "CBO.RING_BL_USED.CW": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "BL Ring in Use",
+          "EvSel": 29,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+          "Umask": "b00000011",
+     },
+     "CBO.RING_BL_USED.UP_EVEN": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "BL Ring in Use",
+          "EvSel": 29,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+          "Umask": "bxxxxxxx1",
+     },
+     "CBO.RING_BL_USED.DOWN_EVEN": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "BL Ring in Use",
+          "EvSel": 29,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+          "Umask": "bxxxxx1xx",
+     },
+     "CBO.RING_BL_USED.CCW": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+          "Desc": "BL Ring in Use",
+          "EvSel": 29,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the UP direction and one packet moving in the DN direction.",
+          "Umask": "b00001100",
+     },
+     "CBO.RING_BOUNCES": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Desc": "Number of LLC responses that bounced on the Ring.",
+          "EvSel": 5,
+          "ExtSel": "",
+     },
+     "CBO.RING_BOUNCES.IV": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Desc": "Number of LLC responses that bounced on the Ring.",
+          "EvSel": 5,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "CBO.RING_BOUNCES.BL": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Desc": "Number of LLC responses that bounced on the Ring.",
+          "EvSel": 5,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "CBO.RING_BOUNCES.AK": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Desc": "Number of LLC responses that bounced on the Ring.",
+          "EvSel": 5,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "CBO.RING_BOUNCES.AD": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Desc": "Number of LLC responses that bounced on the Ring.",
+          "EvSel": 5,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "CBO.RING_IV_USED": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in BDX  Therefore, if one wants to monitor the \"Even\" ring, they should select both UP_EVEN and DN_EVEN.  To monitor the \"Odd\" ring, they should select both UP_ODD and DN_ODD.",
+          "Desc": "BL Ring in Use",
+          "EvSel": 30,
+          "ExtSel": "",
+          "Notes": "IV messages are split into two parts.  In any cycle, a ring stop can see up to one (half-)packet moving in the UP direction and one (half-)packet moving in the DN direction.",
+     },
+     "CBO.RING_IV_USED.DOWN": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in BDX  Therefore, if one wants to monitor the \"Even\" ring, they should select both UP_EVEN and DN_EVEN.  To monitor the \"Odd\" ring, they should select both UP_ODD and DN_ODD.",
+          "Desc": "BL Ring in Use",
+          "EvSel": 30,
+          "ExtSel": "",
+          "Notes": "IV messages are split into two parts.  In any cycle, a ring stop can see up to one (half-)packet moving in the UP direction and one (half-)packet moving in the DN direction.",
+          "Umask": "b11001100",
+     },
+     "CBO.RING_IV_USED.UP": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in BDX  Therefore, if one wants to monitor the \"Even\" ring, they should select both UP_EVEN and DN_EVEN.  To monitor the \"Odd\" ring, they should select both UP_ODD and DN_ODD.",
+          "Desc": "BL Ring in Use",
+          "EvSel": 30,
+          "ExtSel": "",
+          "Notes": "IV messages are split into two parts.  In any cycle, a ring stop can see up to one (half-)packet moving in the UP direction and one (half-)packet moving in the DN direction.",
+          "Umask": "b00000011",
+     },
+     "CBO.RING_IV_USED.ANY": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in BDX  Therefore, if one wants to monitor the \"Even\" ring, they should select both UP_EVEN and DN_EVEN.  To monitor the \"Odd\" ring, they should select both UP_ODD and DN_ODD.",
+          "Desc": "BL Ring in Use",
+          "EvSel": 30,
+          "ExtSel": "",
+          "Notes": "IV messages are split into two parts.  In any cycle, a ring stop can see up to one (half-)packet moving in the UP direction and one (half-)packet moving in the DN direction.",
+          "Umask": "b00001111",
+     },
+     "CBO.RING_IV_USED.DN": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in BDX  Therefore, if one wants to monitor the \"Even\" ring, they should select both UP_EVEN and DN_EVEN.  To monitor the \"Odd\" ring, they should select both UP_ODD and DN_ODD.",
+          "Desc": "BL Ring in Use",
+          "EvSel": 30,
+          "ExtSel": "",
+          "Notes": "IV messages are split into two parts.  In any cycle, a ring stop can see up to one (half-)packet moving in the UP direction and one (half-)packet moving in the DN direction.",
+          "Umask": "b00001100",
+     },
+     "CBO.RING_SRC_THRTL": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Counters": "0-3",
+          "Desc": "Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic.",
+          "EvSel": 7,
+          "ExtSel": "",
+     },
+     "CBO.RxR_EXT_STARVED": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS Events",
+          "Counters": "0-3",
+          "Defn": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.",
+          "Desc": "Ingress Arbiter Blocking Cycles",
+          "EvSel": 18,
+          "ExtSel": "",
+     },
+     "CBO.RxR_EXT_STARVED.IPQ": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS Events",
+          "Counters": "0-3",
+          "Defn": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.",
+          "Desc": "Ingress Arbiter Blocking Cycles",
+          "EvSel": 18,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "CBO.RxR_EXT_STARVED.ISMQ_BIDS": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS Events",
+          "Counters": "0-3",
+          "Defn": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.",
+          "Desc": "Ingress Arbiter Blocking Cycles",
+          "EvSel": 18,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "CBO.RxR_EXT_STARVED.IRQ": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS Events",
+          "Counters": "0-3",
+          "Defn": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.",
+          "Desc": "Ingress Arbiter Blocking Cycles",
+          "EvSel": 18,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "CBO.RxR_EXT_STARVED.PRQ": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS Events",
+          "Counters": "0-3",
+          "Defn": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.",
+          "Desc": "Ingress Arbiter Blocking Cycles",
+          "EvSel": 18,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "CBO.RxR_INSERTS": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS Events",
+          "Counters": "0-3",
+          "Defn": "Counts number of allocations per cycle into the specified Ingress queue.",
+          "Desc": "Ingress Allocations",
+          "EvSel": 19,
+          "ExtSel": "",
+          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
+     },
+     "CBO.RxR_INSERTS.PRQ_REJ": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS Events",
+          "Counters": "0-3",
+          "Defn": "Counts number of allocations per cycle into the specified Ingress queue.",
+          "Desc": "Ingress Allocations",
+          "EvSel": 19,
+          "ExtSel": "",
+          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
+          "Umask": "bxx1xxxxx",
+     },
+     "CBO.RxR_INSERTS.IPQ": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS Events",
+          "Counters": "0-3",
+          "Defn": "Counts number of allocations per cycle into the specified Ingress queue.",
+          "Desc": "Ingress Allocations",
+          "EvSel": 19,
+          "ExtSel": "",
+          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
+          "Umask": "bxxxxx1xx",
+     },
+     "CBO.RxR_INSERTS.PRQ": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS Events",
+          "Counters": "0-3",
+          "Defn": "Counts number of allocations per cycle into the specified Ingress queue.",
+          "Desc": "Ingress Allocations",
+          "EvSel": 19,
+          "ExtSel": "",
+          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
+          "Umask": "bxxx1xxxx",
+     },
+     "CBO.RxR_INSERTS.IRQ": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS Events",
+          "Counters": "0-3",
+          "Defn": "Counts number of allocations per cycle into the specified Ingress queue.",
+          "Desc": "Ingress Allocations",
+          "EvSel": 19,
+          "ExtSel": "",
+          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
+          "Umask": "bxxxxxxx1",
+     },
+     "CBO.RxR_INSERTS.IRQ_REJ": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS Events",
+          "Counters": "0-3",
+          "Defn": "Counts number of allocations per cycle into the specified Ingress queue.",
+          "Desc": "Ingress Allocations",
+          "EvSel": 19,
+          "ExtSel": "",
+          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
+          "Umask": "bxxxxxx1x",
+     },
+     "CBO.RxR_IPQ_RETRY": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Defn": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.",
+          "Desc": "Probe Queue Retries",
+          "EvSel": 49,
+          "ExtSel": "",
+     },
+     "CBO.RxR_IPQ_RETRY.QPI_CREDITS": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Defn": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.",
+          "Desc": "Probe Queue Retries",
+          "EvSel": 49,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "CBO.RxR_IPQ_RETRY.ADDR_CONFLICT": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Defn": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.",
+          "Desc": "Probe Queue Retries",
+          "EvSel": 49,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "CBO.RxR_IPQ_RETRY.FULL": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Defn": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.",
+          "Desc": "Probe Queue Retries",
+          "EvSel": 49,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "CBO.RxR_IPQ_RETRY.ANY": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Defn": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.",
+          "Desc": "Probe Queue Retries",
+          "EvSel": 49,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "CBO.RxR_IPQ_RETRY2": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Defn": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.",
+          "Desc": "Probe Queue Retries",
+          "EvSel": 40,
+          "ExtSel": "",
+     },
+     "CBO.RxR_IPQ_RETRY2.TARGET": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Defn": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.",
+          "Desc": "Probe Queue Retries",
+          "EvSel": 40,
+          "ExtSel": "",
+          "Umask": "bx1xxxxxx",
+     },
+     "CBO.RxR_IPQ_RETRY2.AD_SBO": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Defn": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.",
+          "Desc": "Probe Queue Retries",
+          "EvSel": 40,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "CBO.RxR_IRQ_RETRY": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Desc": "Ingress Request Queue Rejects",
+          "EvSel": 50,
+          "ExtSel": "",
+     },
+     "CBO.RxR_IRQ_RETRY.FULL": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Desc": "Ingress Request Queue Rejects",
+          "EvSel": 50,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "CBO.RxR_IRQ_RETRY.IIO_CREDITS": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Desc": "Ingress Request Queue Rejects",
+          "EvSel": 50,
+          "ExtSel": "",
+          "Umask": "bxx1xxxxx",
+     },
+     "CBO.RxR_IRQ_RETRY.ADDR_CONFLICT": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Desc": "Ingress Request Queue Rejects",
+          "EvSel": 50,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "CBO.RxR_IRQ_RETRY.QPI_CREDITS": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Desc": "Ingress Request Queue Rejects",
+          "EvSel": 50,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "CBO.RxR_IRQ_RETRY.RTID": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Desc": "Ingress Request Queue Rejects",
+          "EvSel": 50,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "CBO.RxR_IRQ_RETRY.ANY": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Desc": "Ingress Request Queue Rejects",
+          "EvSel": 50,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "CBO.RxR_IRQ_RETRY.NID": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Desc": "Ingress Request Queue Rejects",
+          "EvSel": 50,
+          "ExtSel": "",
+          "Umask": "bx1xxxxxx",
+     },
+     "CBO.RxR_IRQ_RETRY2": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Desc": "Ingress Request Queue Rejects",
+          "EvSel": 41,
+          "ExtSel": "",
+     },
+     "CBO.RxR_IRQ_RETRY2.AD_SBO": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Desc": "Ingress Request Queue Rejects",
+          "EvSel": 41,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "CBO.RxR_IRQ_RETRY2.BL_SBO": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Desc": "Ingress Request Queue Rejects",
+          "EvSel": 41,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "CBO.RxR_IRQ_RETRY2.TARGET": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Desc": "Ingress Request Queue Rejects",
+          "EvSel": 41,
+          "ExtSel": "",
+          "Umask": "bx1xxxxxx",
+     },
+     "CBO.RxR_ISMQ_RETRY": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+          "Desc": "ISMQ Retries",
+          "EvSel": 51,
+          "ExtSel": "",
+     },
+     "CBO.RxR_ISMQ_RETRY.FULL": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+          "Desc": "ISMQ Retries",
+          "EvSel": 51,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "CBO.RxR_ISMQ_RETRY.IIO_CREDITS": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+          "Desc": "ISMQ Retries",
+          "EvSel": 51,
+          "ExtSel": "",
+          "Umask": "bxx1xxxxx",
+     },
+     "CBO.RxR_ISMQ_RETRY.RTID": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+          "Desc": "ISMQ Retries",
+          "EvSel": 51,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "CBO.RxR_ISMQ_RETRY.QPI_CREDITS": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+          "Desc": "ISMQ Retries",
+          "EvSel": 51,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "CBO.RxR_ISMQ_RETRY.NID": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+          "Desc": "ISMQ Retries",
+          "EvSel": 51,
+          "ExtSel": "",
+          "Umask": "bx1xxxxxx",
+     },
+     "CBO.RxR_ISMQ_RETRY.ANY": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+          "Desc": "ISMQ Retries",
+          "EvSel": 51,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "CBO.RxR_ISMQ_RETRY.WB_CREDITS": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+          "Desc": "ISMQ Retries",
+          "EvSel": 51,
+          "ExtSel": "",
+          "Umask": "b1xxxxxxx",
+     },
+     "CBO.RxR_ISMQ_RETRY2": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Desc": "ISMQ Request Queue Rejects",
+          "EvSel": 42,
+          "ExtSel": "",
+     },
+     "CBO.RxR_ISMQ_RETRY2.TARGET": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Desc": "ISMQ Request Queue Rejects",
+          "EvSel": 42,
+          "ExtSel": "",
+          "Umask": "bx1xxxxxx",
+     },
+     "CBO.RxR_ISMQ_RETRY2.AD_SBO": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Desc": "ISMQ Request Queue Rejects",
+          "EvSel": 42,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "CBO.RxR_ISMQ_RETRY2.BL_SBO": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS_RETRY Events",
+          "Counters": "0-3",
+          "Desc": "ISMQ Request Queue Rejects",
+          "EvSel": 42,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "CBO.RxR_OCCUPANCY": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS Events",
+          "Counters": 0,
+          "Defn": "Counts number of entries in the specified Ingress queue in each cycle.",
+          "Desc": "Ingress Occupancy",
+          "EvSel": 17,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
+          "SubCtr": 1,
+     },
+     "CBO.RxR_OCCUPANCY.IRQ_REJ": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS Events",
+          "Counters": 0,
+          "Defn": "Counts number of entries in the specified Ingress queue in each cycle.",
+          "Desc": "Ingress Occupancy",
+          "EvSel": 17,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
+          "SubCtr": 1,
+          "Umask": "b00000010",
+     },
+     "CBO.RxR_OCCUPANCY.IRQ": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS Events",
+          "Counters": 0,
+          "Defn": "Counts number of entries in the specified Ingress queue in each cycle.",
+          "Desc": "Ingress Occupancy",
+          "EvSel": 17,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
+          "SubCtr": 1,
+          "Umask": "b00000001",
+     },
+     "CBO.RxR_OCCUPANCY.IPQ": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS Events",
+          "Counters": 0,
+          "Defn": "Counts number of entries in the specified Ingress queue in each cycle.",
+          "Desc": "Ingress Occupancy",
+          "EvSel": 17,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
+          "SubCtr": 1,
+          "Umask": "b00000100",
+     },
+     "CBO.RxR_OCCUPANCY.PRQ_REJ": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS Events",
+          "Counters": 0,
+          "Defn": "Counts number of entries in the specified Ingress queue in each cycle.",
+          "Desc": "Ingress Occupancy",
+          "EvSel": 17,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
+          "SubCtr": 1,
+          "Umask": "b00100000",
+     },
+     "CBO.SBO_CREDITS_ACQUIRED": {
+          "Box": "CBO",
+          "Category": "CBO SBO Credit Events",
+          "Counters": "0-3",
+          "Defn": "Number of Sbo credits acquired in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
+          "Desc": "SBo Credits Acquired",
+          "EvSel": 61,
+          "ExtSel": "",
+     },
+     "CBO.SBO_CREDITS_ACQUIRED.AD": {
+          "Box": "CBO",
+          "Category": "CBO SBO Credit Events",
+          "Counters": "0-3",
+          "Defn": "Number of Sbo credits acquired in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
+          "Desc": "SBo Credits Acquired",
+          "EvSel": 61,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "CBO.SBO_CREDITS_ACQUIRED.BL": {
+          "Box": "CBO",
+          "Category": "CBO SBO Credit Events",
+          "Counters": "0-3",
+          "Defn": "Number of Sbo credits acquired in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
+          "Desc": "SBo Credits Acquired",
+          "EvSel": 61,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "CBO.SBO_CREDIT_OCCUPANCY": {
+          "Box": "CBO",
+          "Category": "CBO SBO Credit Events",
+          "Counters": 0,
+          "Defn": "Number of Sbo credits in use in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
+          "Desc": "SBo Credits Occupancy",
+          "EvSel": 62,
+          "ExtSel": "",
+          "MaxIncCyc": 7,
+          "Notes": "Each Cbo has 3 AD and 2 BL credits into its assigned Sbo.",
+          "SubCtr": 1,
+     },
+     "CBO.SBO_CREDIT_OCCUPANCY.BL": {
+          "Box": "CBO",
+          "Category": "CBO SBO Credit Events",
+          "Counters": 0,
+          "Defn": "Number of Sbo credits in use in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
+          "Desc": "SBo Credits Occupancy",
+          "EvSel": 62,
+          "ExtSel": "",
+          "MaxIncCyc": 7,
+          "Notes": "Each Cbo has 3 AD and 2 BL credits into its assigned Sbo.",
+          "SubCtr": 1,
+          "Umask": "bxxxxxx1x",
+     },
+     "CBO.SBO_CREDIT_OCCUPANCY.AD": {
+          "Box": "CBO",
+          "Category": "CBO SBO Credit Events",
+          "Counters": 0,
+          "Defn": "Number of Sbo credits in use in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
+          "Desc": "SBo Credits Occupancy",
+          "EvSel": 62,
+          "ExtSel": "",
+          "MaxIncCyc": 7,
+          "Notes": "Each Cbo has 3 AD and 2 BL credits into its assigned Sbo.",
+          "SubCtr": 1,
+          "Umask": "bxxxxxxx1",
+     },
+     "CBO.TOR_INSERTS": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+          "Desc": "TOR Inserts",
+          "EvSel": 53,
+          "ExtSel": "",
+     },
+     "CBO.TOR_INSERTS.OPCODE": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+          "Desc": "TOR Inserts",
+          "EvSel": 53,
+          "ExtSel": "",
+          "Umask": "b00000001",
+     },
+     "CBO.TOR_INSERTS.ALL": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+          "Desc": "TOR Inserts",
+          "EvSel": 53,
+          "ExtSel": "",
+          "Umask": "b00001000",
+     },
+     "CBO.TOR_INSERTS.WB": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+          "Desc": "TOR Inserts",
+          "EvSel": 53,
+          "ExtSel": "",
+          "Umask": "b00010000",
+     },
+     "CBO.TOR_INSERTS.NID_EVICTION": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+          "Desc": "TOR Inserts",
+          "EvSel": 53,
+          "ExtSel": "",
+          "Umask": "b01000100",
+     },
+     "CBO.TOR_INSERTS.REMOTE_OPCODE": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+          "Desc": "TOR Inserts",
+          "EvSel": 53,
+          "ExtSel": "",
+          "Umask": "b10000001",
+     },
+     "CBO.TOR_INSERTS.NID_MISS_ALL": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+          "Desc": "TOR Inserts",
+          "EvSel": 53,
+          "ExtSel": "",
+          "Umask": "b01001010",
+     },
+     "CBO.TOR_INSERTS.EVICTION": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+          "Desc": "TOR Inserts",
+          "EvSel": 53,
+          "ExtSel": "",
+          "Umask": "b00000100",
+     },
+     "CBO.TOR_INSERTS.MISS_REMOTE_OPCODE": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+          "Desc": "TOR Inserts",
+          "EvSel": 53,
+          "ExtSel": "",
+          "Umask": "b10000011",
+     },
+     "CBO.TOR_INSERTS.LOCAL": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+          "Desc": "TOR Inserts",
+          "EvSel": 53,
+          "ExtSel": "",
+          "Umask": "b00101000",
+     },
+     "CBO.TOR_INSERTS.LOCAL_OPCODE": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+          "Desc": "TOR Inserts",
+          "EvSel": 53,
+          "ExtSel": "",
+          "Umask": "b00100001",
+     },
+     "CBO.TOR_INSERTS.MISS_LOCAL_OPCODE": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+          "Desc": "TOR Inserts",
+          "EvSel": 53,
+          "ExtSel": "",
+          "Umask": "b00100011",
+     },
+     "CBO.TOR_INSERTS.REMOTE": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+          "Desc": "TOR Inserts",
+          "EvSel": 53,
+          "ExtSel": "",
+          "Umask": "b10001000",
+     },
+     "CBO.TOR_INSERTS.MISS_LOCAL": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+          "Desc": "TOR Inserts",
+          "EvSel": 53,
+          "ExtSel": "",
+          "Umask": "b00101010",
+     },
+     "CBO.TOR_INSERTS.NID_OPCODE": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+          "Desc": "TOR Inserts",
+          "EvSel": 53,
+          "ExtSel": "",
+          "Umask": "b01000001",
+     },
+     "CBO.TOR_INSERTS.MISS_OPCODE": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+          "Desc": "TOR Inserts",
+          "EvSel": 53,
+          "ExtSel": "",
+          "Umask": "b00000011",
+     },
+     "CBO.TOR_INSERTS.NID_MISS_OPCODE": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+          "Desc": "TOR Inserts",
+          "EvSel": 53,
+          "ExtSel": "",
+          "Umask": "b01000011",
+     },
+     "CBO.TOR_INSERTS.MISS_REMOTE": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+          "Desc": "TOR Inserts",
+          "EvSel": 53,
+          "ExtSel": "",
+          "Umask": "b10001010",
+     },
+     "CBO.TOR_INSERTS.NID_ALL": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+          "Desc": "TOR Inserts",
+          "EvSel": 53,
+          "ExtSel": "",
+          "Umask": "b01001000",
+     },
+     "CBO.TOR_INSERTS.NID_WB": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+          "Desc": "TOR Inserts",
+          "EvSel": 53,
+          "ExtSel": "",
+          "Umask": "b01010000",
+     },
+     "CBO.TOR_OCCUPANCY": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": 0,
+          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+          "Desc": "TOR Occupancy",
+          "EvSel": 54,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "SubCtr": 1,
+     },
+     "CBO.TOR_OCCUPANCY.MISS_LOCAL_OPCODE": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": 0,
+          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+          "Desc": "TOR Occupancy",
+          "EvSel": 54,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "SubCtr": 1,
+          "Umask": "b00100011",
+     },
+     "CBO.TOR_OCCUPANCY.LOCAL_OPCODE": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": 0,
+          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+          "Desc": "TOR Occupancy",
+          "EvSel": 54,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "SubCtr": 1,
+          "Umask": "b00100001",
+     },
+     "CBO.TOR_OCCUPANCY.MISS_LOCAL": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": 0,
+          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+          "Desc": "TOR Occupancy",
+          "EvSel": 54,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "SubCtr": 1,
+          "Umask": "b00101010",
+     },
+     "CBO.TOR_OCCUPANCY.REMOTE": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": 0,
+          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+          "Desc": "TOR Occupancy",
+          "EvSel": 54,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "SubCtr": 1,
+          "Umask": "b10001000",
+     },
+     "CBO.TOR_OCCUPANCY.NID_OPCODE": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": 0,
+          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+          "Desc": "TOR Occupancy",
+          "EvSel": 54,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "SubCtr": 1,
+          "Umask": "b01000001",
+     },
+     "CBO.TOR_OCCUPANCY.NID_MISS_OPCODE": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": 0,
+          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+          "Desc": "TOR Occupancy",
+          "EvSel": 54,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "SubCtr": 1,
+          "Umask": "b01000011",
+     },
+     "CBO.TOR_OCCUPANCY.MISS_OPCODE": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": 0,
+          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+          "Desc": "TOR Occupancy",
+          "EvSel": 54,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "SubCtr": 1,
+          "Umask": "b00000011",
+     },
+     "CBO.TOR_OCCUPANCY.NID_WB": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": 0,
+          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+          "Desc": "TOR Occupancy",
+          "EvSel": 54,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "SubCtr": 1,
+          "Umask": "b01010000",
+     },
+     "CBO.TOR_OCCUPANCY.MISS_REMOTE": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": 0,
+          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+          "Desc": "TOR Occupancy",
+          "EvSel": 54,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "SubCtr": 1,
+          "Umask": "b10001010",
+     },
+     "CBO.TOR_OCCUPANCY.NID_ALL": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": 0,
+          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+          "Desc": "TOR Occupancy",
+          "EvSel": 54,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "SubCtr": 1,
+          "Umask": "b01001000",
+     },
+     "CBO.TOR_OCCUPANCY.OPCODE": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": 0,
+          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+          "Desc": "TOR Occupancy",
+          "EvSel": 54,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "SubCtr": 1,
+          "Umask": "b00000001",
+     },
+     "CBO.TOR_OCCUPANCY.NID_EVICTION": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": 0,
+          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+          "Desc": "TOR Occupancy",
+          "EvSel": 54,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "SubCtr": 1,
+          "Umask": "b01000100",
+     },
+     "CBO.TOR_OCCUPANCY.WB": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": 0,
+          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+          "Desc": "TOR Occupancy",
+          "EvSel": 54,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "SubCtr": 1,
+          "Umask": "b00010000",
+     },
+     "CBO.TOR_OCCUPANCY.REMOTE_OPCODE": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": 0,
+          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+          "Desc": "TOR Occupancy",
+          "EvSel": 54,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "SubCtr": 1,
+          "Umask": "b10000001",
+     },
+     "CBO.TOR_OCCUPANCY.MISS_ALL": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": 0,
+          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+          "Desc": "TOR Occupancy",
+          "EvSel": 54,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "SubCtr": 1,
+          "Umask": "b00001010",
+     },
+     "CBO.TOR_OCCUPANCY.ALL": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": 0,
+          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+          "Desc": "TOR Occupancy",
+          "EvSel": 54,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "SubCtr": 1,
+          "Umask": "b00001000",
+     },
+     "CBO.TOR_OCCUPANCY.NID_MISS_ALL": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": 0,
+          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+          "Desc": "TOR Occupancy",
+          "EvSel": 54,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "SubCtr": 1,
+          "Umask": "b01001010",
+     },
+     "CBO.TOR_OCCUPANCY.MISS_REMOTE_OPCODE": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": 0,
+          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+          "Desc": "TOR Occupancy",
+          "EvSel": 54,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "SubCtr": 1,
+          "Umask": "b10000011",
+     },
+     "CBO.TOR_OCCUPANCY.LOCAL": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": 0,
+          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+          "Desc": "TOR Occupancy",
+          "EvSel": 54,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "SubCtr": 1,
+          "Umask": "b00101000",
+     },
+     "CBO.TOR_OCCUPANCY.EVICTION": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Counters": 0,
+          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select \"MISS_OPC_MATCH\" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+          "Desc": "TOR Occupancy",
+          "EvSel": 54,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "SubCtr": 1,
+          "Umask": "b00000100",
+     },
+     "CBO.TxR_ADS_USED": {
+          "Box": "CBO",
+          "Category": "CBO EGRESS Events",
+          "Counters": "0-3",
+          "EvSel": 4,
+          "ExtSel": "",
+     },
+     "CBO.TxR_ADS_USED.AD": {
+          "Box": "CBO",
+          "Category": "CBO EGRESS Events",
+          "Counters": "0-3",
+          "EvSel": 4,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "CBO.TxR_ADS_USED.AK": {
+          "Box": "CBO",
+          "Category": "CBO EGRESS Events",
+          "Counters": "0-3",
+          "EvSel": 4,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "CBO.TxR_ADS_USED.BL": {
+          "Box": "CBO",
+          "Category": "CBO EGRESS Events",
+          "Counters": "0-3",
+          "EvSel": 4,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "CBO.TxR_INSERTS": {
+          "Box": "CBO",
+          "Category": "CBO EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.",
+          "Desc": "Egress Allocations",
+          "EvSel": 2,
+          "ExtSel": "",
+     },
+     "CBO.TxR_INSERTS.AD_CORE": {
+          "Box": "CBO",
+          "Category": "CBO EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.",
+          "Desc": "Egress Allocations",
+          "EvSel": 2,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "CBO.TxR_INSERTS.IV_CACHE": {
+          "Box": "CBO",
+          "Category": "CBO EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.",
+          "Desc": "Egress Allocations",
+          "EvSel": 2,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "CBO.TxR_INSERTS.BL_CACHE": {
+          "Box": "CBO",
+          "Category": "CBO EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.",
+          "Desc": "Egress Allocations",
+          "EvSel": 2,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "CBO.TxR_INSERTS.BL_CORE": {
+          "Box": "CBO",
+          "Category": "CBO EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.",
+          "Desc": "Egress Allocations",
+          "EvSel": 2,
+          "ExtSel": "",
+          "Umask": "bx1xxxxxx",
+     },
+     "CBO.TxR_INSERTS.AK_CACHE": {
+          "Box": "CBO",
+          "Category": "CBO EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.",
+          "Desc": "Egress Allocations",
+          "EvSel": 2,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "CBO.TxR_INSERTS.AK_CORE": {
+          "Box": "CBO",
+          "Category": "CBO EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.",
+          "Desc": "Egress Allocations",
+          "EvSel": 2,
+          "ExtSel": "",
+          "Umask": "bxx1xxxxx",
+     },
+     "CBO.TxR_INSERTS.AD_CACHE": {
+          "Box": "CBO",
+          "Category": "CBO EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.",
+          "Desc": "Egress Allocations",
+          "EvSel": 2,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     
+# HA:
+     "HA.ADDR_OPC_MATCH": {
+          "Box": "HA",
+          "Category": "HA ADDR_OPCODE_MATCH Events",
+          "Counters": "0-3",
+          "Desc": "QPI Address/Opcode Match",
+          "EvSel": 32,
+          "ExtSel": "",
+     },
+     "HA.ADDR_OPC_MATCH.AD": {
+          "Box": "HA",
+          "Category": "HA ADDR_OPCODE_MATCH Events",
+          "Counters": "0-3",
+          "Desc": "QPI Address/Opcode Match",
+          "EvSel": 32,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "HA.ADDR_OPC_MATCH.FILT": {
+          "Box": "HA",
+          "Category": "HA ADDR_OPCODE_MATCH Events",
+          "Counters": "0-3",
+          "Desc": "QPI Address/Opcode Match",
+          "EvSel": 32,
+          "ExtSel": "",
+          "Umask": "b00000011",
+     },
+     "HA.ADDR_OPC_MATCH.AK": {
+          "Box": "HA",
+          "Category": "HA ADDR_OPCODE_MATCH Events",
+          "Counters": "0-3",
+          "Desc": "QPI Address/Opcode Match",
+          "EvSel": 32,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "HA.ADDR_OPC_MATCH.BL": {
+          "Box": "HA",
+          "Category": "HA ADDR_OPCODE_MATCH Events",
+          "Counters": "0-3",
+          "Desc": "QPI Address/Opcode Match",
+          "EvSel": 32,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "HA.ADDR_OPC_MATCH.ADDR": {
+          "Box": "HA",
+          "Category": "HA ADDR_OPCODE_MATCH Events",
+          "Counters": "0-3",
+          "Desc": "QPI Address/Opcode Match",
+          "EvSel": 32,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.ADDR_OPC_MATCH.OPC": {
+          "Box": "HA",
+          "Category": "HA ADDR_OPCODE_MATCH Events",
+          "Counters": "0-3",
+          "Desc": "QPI Address/Opcode Match",
+          "EvSel": 32,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.BT_CYCLES_NE": {
+          "Box": "HA",
+          "Category": "HA BT (Backup Tracker) Events",
+          "Counters": "0-3",
+          "Defn": "Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT.",
+          "Desc": "BT Cycles Not Empty",
+          "EvSel": 66,
+          "ExtSel": "",
+          "Notes": "Will not count case HT is empty and a Bypass happens.",
+     },
+     "HA.BT_OCCUPANCY": {
+          "Box": "HA",
+          "Category": "HA BT (Backup Tracker) Events",
+          "Counters": "0-3",
+          "Defn": "Accumulates the occupancy of the HA BT pool in every cycle.  This can be used with the \"not empty\" stat to calculate average queue occupancy or the \"allocations\" stat in order to calculate average queue latency.  HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+          "Desc": "BT Occupancy",
+          "EvSel": 67,
+          "ExtSel": "",
+          "MaxIncCyc": 512,
+     },
+     "HA.BYPASS_IMC": {
+          "Box": "HA",
+          "Category": "HA BYPASS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.",
+          "Desc": "HA to iMC Bypass",
+          "EvSel": 20,
+          "ExtSel": "",
+          "Notes": "Only read transactions use iMC bypass",
+     },
+     "HA.BYPASS_IMC.TAKEN": {
+          "Box": "HA",
+          "Category": "HA BYPASS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.",
+          "Desc": "HA to iMC Bypass",
+          "EvSel": 20,
+          "ExtSel": "",
+          "Notes": "Only read transactions use iMC bypass",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.BYPASS_IMC.NOT_TAKEN": {
+          "Box": "HA",
+          "Category": "HA BYPASS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.",
+          "Desc": "HA to iMC Bypass",
+          "EvSel": 20,
+          "ExtSel": "",
+          "Notes": "Only read transactions use iMC bypass",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.CLOCKTICKS": {
+          "Box": "HA",
+          "Category": "HA UCLK Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of uclks in the HA.  This will be slightly different than the count in the Ubox because of enable/freeze delays.  The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.",
+          "Desc": "uclks",
+          "EvSel": 0,
+          "ExtSel": "",
+     },
+     "HA.CONFLICT_CYCLES": {
+          "Box": "HA",
+          "Category": "HA CONFLICTS Events",
+          "Counters": 1,
+          "Defn": "Counters the number of cycles there was a conflict in the HA because threads in two different sockets were requesting the same address at the same time",
+          "Desc": "Conflict Checks",
+          "EvSel": 11,
+          "Filter": "N",
+          "ExtSel": "",
+     },
+     "HA.DIRECT2CORE_COUNT": {
+          "Box": "HA",
+          "Category": "HA DIRECT2CORE Events",
+          "Counters": "0-3",
+          "Defn": "Number of Direct2Core messages sent",
+          "Desc": "Direct2Core Messages Sent",
+          "EvSel": 17,
+          "ExtSel": "",
+          "Notes": "Will not be implemented since OUTBOUND_TX_BL:0x1 will count DRS to CORE which is effectively the same thing as D2C count",
+     },
+     "HA.DIRECT2CORE_CYCLES_DISABLED": {
+          "Box": "HA",
+          "Category": "HA DIRECT2CORE Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles in which Direct2Core was disabled",
+          "Desc": "Cycles when Direct2Core was Disabled",
+          "EvSel": 18,
+          "ExtSel": "",
+     },
+     "HA.DIRECT2CORE_TXN_OVERRIDE": {
+          "Box": "HA",
+          "Category": "HA DIRECT2CORE Events",
+          "Counters": "0-3",
+          "Defn": "Number of Reads where Direct2Core overridden",
+          "Desc": "Number of Reads that had Direct2Core Overridden",
+          "EvSel": 19,
+          "ExtSel": "",
+     },
+     "HA.DIRECTORY_LAT_OPT": {
+          "Box": "HA",
+          "Category": "HA DIRECTORY Events",
+          "Counters": "0-3",
+          "Defn": "Directory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory retuned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc).",
+          "Desc": "Directory Lat Opt Return",
+          "EvSel": 65,
+          "ExtSel": "",
+     },
+     "HA.DIRECTORY_LOOKUP": {
+          "Box": "HA",
+          "Category": "HA DIRECTORY Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.",
+          "Desc": "Directory Lookups",
+          "EvSel": 12,
+          "ExtSel": "",
+          "Notes": "Only valid for parts that implement the Directory",
+     },
+     "HA.DIRECTORY_LOOKUP.NO_SNP": {
+          "Box": "HA",
+          "Category": "HA DIRECTORY Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.",
+          "Desc": "Directory Lookups",
+          "EvSel": 12,
+          "ExtSel": "",
+          "Notes": "Only valid for parts that implement the Directory",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.DIRECTORY_LOOKUP.SNP": {
+          "Box": "HA",
+          "Category": "HA DIRECTORY Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.",
+          "Desc": "Directory Lookups",
+          "EvSel": 12,
+          "ExtSel": "",
+          "Notes": "Only valid for parts that implement the Directory",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.DIRECTORY_UPDATE": {
+          "Box": "HA",
+          "Category": "HA DIRECTORY Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.",
+          "Desc": "Directory Updates",
+          "EvSel": 13,
+          "ExtSel": "",
+          "Notes": "Only valid for parts that implement the Directory",
+     },
+     "HA.DIRECTORY_UPDATE.SET": {
+          "Box": "HA",
+          "Category": "HA DIRECTORY Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.",
+          "Desc": "Directory Updates",
+          "EvSel": 13,
+          "ExtSel": "",
+          "Notes": "Only valid for parts that implement the Directory",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.DIRECTORY_UPDATE.CLEAR": {
+          "Box": "HA",
+          "Category": "HA DIRECTORY Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.",
+          "Desc": "Directory Updates",
+          "EvSel": 13,
+          "ExtSel": "",
+          "Notes": "Only valid for parts that implement the Directory",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.DIRECTORY_UPDATE.ANY": {
+          "Box": "HA",
+          "Category": "HA DIRECTORY Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.",
+          "Desc": "Directory Updates",
+          "EvSel": 13,
+          "ExtSel": "",
+          "Notes": "Only valid for parts that implement the Directory",
+          "Umask": "bxxxxxx11",
+     },
+     "HA.HITME_HIT": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of Hits in HitMe Cache",
+          "EvSel": 113,
+          "ExtSel": "",
+     },
+     "HA.HITME_HIT.RSPFWDI_LOCAL": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of Hits in HitMe Cache",
+          "EvSel": 113,
+          "ExtSel": "",
+          "Umask": "bxx1xxxxx",
+     },
+     "HA.HITME_HIT.ALL": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of Hits in HitMe Cache",
+          "EvSel": 113,
+          "ExtSel": "",
+          "Umask": "b11111111",
+     },
+     "HA.HITME_HIT.READ_OR_INVITOE": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of Hits in HitMe Cache",
+          "EvSel": 113,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.HITME_HIT.ACKCNFLTWBI": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of Hits in HitMe Cache",
+          "EvSel": 113,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "HA.HITME_HIT.WBMTOI": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of Hits in HitMe Cache",
+          "EvSel": 113,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.HITME_HIT.HOM": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of Hits in HitMe Cache",
+          "EvSel": 113,
+          "ExtSel": "",
+          "Umask": "b00001111",
+     },
+     "HA.HITME_HIT.INVALS": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of Hits in HitMe Cache",
+          "EvSel": 113,
+          "ExtSel": "",
+          "Umask": "b00100110",
+     },
+     "HA.HITME_HIT.RSPFWDI_REMOTE": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of Hits in HitMe Cache",
+          "EvSel": 113,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "HA.HITME_HIT.RSP": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of Hits in HitMe Cache",
+          "EvSel": 113,
+          "ExtSel": "",
+          "Umask": "b1xxxxxxx",
+     },
+     "HA.HITME_HIT.ALLOCS": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of Hits in HitMe Cache",
+          "EvSel": 113,
+          "ExtSel": "",
+          "Umask": "b01110000",
+     },
+     "HA.HITME_HIT.EVICTS": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of Hits in HitMe Cache",
+          "EvSel": 113,
+          "ExtSel": "",
+          "Umask": "b01000010",
+     },
+     "HA.HITME_HIT.RSPFWDS": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of Hits in HitMe Cache",
+          "EvSel": 113,
+          "ExtSel": "",
+          "Umask": "bx1xxxxxx",
+     },
+     "HA.HITME_HIT.WBMTOE_OR_S": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of Hits in HitMe Cache",
+          "EvSel": 113,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "HA.HITME_HIT_PV_BITS_SET": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Accumulates Number of PV bits set on HitMe Cache Hits",
+          "EvSel": 114,
+          "ExtSel": "",
+     },
+     "HA.HITME_HIT_PV_BITS_SET.WBMTOI": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Accumulates Number of PV bits set on HitMe Cache Hits",
+          "EvSel": 114,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.HITME_HIT_PV_BITS_SET.HOM": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Accumulates Number of PV bits set on HitMe Cache Hits",
+          "EvSel": 114,
+          "ExtSel": "",
+          "Umask": "b00001111",
+     },
+     "HA.HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Accumulates Number of PV bits set on HitMe Cache Hits",
+          "EvSel": 114,
+          "ExtSel": "",
+          "Umask": "bxx1xxxxx",
+     },
+     "HA.HITME_HIT_PV_BITS_SET.ALL": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Accumulates Number of PV bits set on HitMe Cache Hits",
+          "EvSel": 114,
+          "ExtSel": "",
+          "Umask": "b11111111",
+     },
+     "HA.HITME_HIT_PV_BITS_SET.READ_OR_INVITOE": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Accumulates Number of PV bits set on HitMe Cache Hits",
+          "EvSel": 114,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.HITME_HIT_PV_BITS_SET.ACKCNFLTWBI": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Accumulates Number of PV bits set on HitMe Cache Hits",
+          "EvSel": 114,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "HA.HITME_HIT_PV_BITS_SET.RSP": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Accumulates Number of PV bits set on HitMe Cache Hits",
+          "EvSel": 114,
+          "ExtSel": "",
+          "Umask": "b1xxxxxxx",
+     },
+     "HA.HITME_HIT_PV_BITS_SET.WBMTOE_OR_S": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Accumulates Number of PV bits set on HitMe Cache Hits",
+          "EvSel": 114,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "HA.HITME_HIT_PV_BITS_SET.RSPFWDS": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Accumulates Number of PV bits set on HitMe Cache Hits",
+          "EvSel": 114,
+          "ExtSel": "",
+          "Umask": "bx1xxxxxx",
+     },
+     "HA.HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Accumulates Number of PV bits set on HitMe Cache Hits",
+          "EvSel": 114,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "HA.HITME_LOOKUP": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of times HitMe Cache is accessed",
+          "EvSel": 112,
+          "ExtSel": "",
+     },
+     "HA.HITME_LOOKUP.RSPFWDI_LOCAL": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of times HitMe Cache is accessed",
+          "EvSel": 112,
+          "ExtSel": "",
+          "Umask": "bxx1xxxxx",
+     },
+     "HA.HITME_LOOKUP.ALL": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of times HitMe Cache is accessed",
+          "EvSel": 112,
+          "ExtSel": "",
+          "Umask": "b11111111",
+     },
+     "HA.HITME_LOOKUP.READ_OR_INVITOE": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of times HitMe Cache is accessed",
+          "EvSel": 112,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.HITME_LOOKUP.ACKCNFLTWBI": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of times HitMe Cache is accessed",
+          "EvSel": 112,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "HA.HITME_LOOKUP.WBMTOI": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of times HitMe Cache is accessed",
+          "EvSel": 112,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.HITME_LOOKUP.HOM": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of times HitMe Cache is accessed",
+          "EvSel": 112,
+          "ExtSel": "",
+          "Umask": "b00001111",
+     },
+     "HA.HITME_LOOKUP.INVALS": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of times HitMe Cache is accessed",
+          "EvSel": 112,
+          "ExtSel": "",
+          "Umask": "b00100110",
+     },
+     "HA.HITME_LOOKUP.RSPFWDI_REMOTE": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of times HitMe Cache is accessed",
+          "EvSel": 112,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "HA.HITME_LOOKUP.RSP": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of times HitMe Cache is accessed",
+          "EvSel": 112,
+          "ExtSel": "",
+          "Umask": "b1xxxxxxx",
+     },
+     "HA.HITME_LOOKUP.RSPFWDS": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of times HitMe Cache is accessed",
+          "EvSel": 112,
+          "ExtSel": "",
+          "Umask": "bx1xxxxxx",
+     },
+     "HA.HITME_LOOKUP.ALLOCS": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of times HitMe Cache is accessed",
+          "EvSel": 112,
+          "ExtSel": "",
+          "Umask": "b01110000",
+     },
+     "HA.HITME_LOOKUP.WBMTOE_OR_S": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Counters": "0-3",
+          "Desc": "Counts Number of times HitMe Cache is accessed",
+          "EvSel": 112,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "HA.IGR_NO_CREDIT_CYCLES": {
+          "Box": "HA",
+          "Category": "HA QPI_IGR_CREDITS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+          "Desc": "Cycles without QPI Ingress Credits",
+          "EvSel": 34,
+          "ExtSel": "",
+     },
+     "HA.IGR_NO_CREDIT_CYCLES.AD_QPI0": {
+          "Box": "HA",
+          "Category": "HA QPI_IGR_CREDITS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+          "Desc": "Cycles without QPI Ingress Credits",
+          "EvSel": 34,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.IGR_NO_CREDIT_CYCLES.BL_QPI0": {
+          "Box": "HA",
+          "Category": "HA QPI_IGR_CREDITS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+          "Desc": "Cycles without QPI Ingress Credits",
+          "EvSel": 34,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "HA.IGR_NO_CREDIT_CYCLES.BL_QPI2": {
+          "Box": "HA",
+          "Category": "HA QPI_IGR_CREDITS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+          "Desc": "Cycles without QPI Ingress Credits",
+          "EvSel": 34,
+          "ExtSel": "",
+          "Umask": "bxx1xxxxx",
+     },
+     "HA.IGR_NO_CREDIT_CYCLES.BL_QPI1": {
+          "Box": "HA",
+          "Category": "HA QPI_IGR_CREDITS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+          "Desc": "Cycles without QPI Ingress Credits",
+          "EvSel": 34,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "HA.IGR_NO_CREDIT_CYCLES.AD_QPI2": {
+          "Box": "HA",
+          "Category": "HA QPI_IGR_CREDITS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+          "Desc": "Cycles without QPI Ingress Credits",
+          "EvSel": 34,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "HA.IGR_NO_CREDIT_CYCLES.AD_QPI1": {
+          "Box": "HA",
+          "Category": "HA QPI_IGR_CREDITS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+          "Desc": "Cycles without QPI Ingress Credits",
+          "EvSel": 34,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.IMC_READS": {
+          "Box": "HA",
+          "Category": "HA IMC_READS Events",
+          "Counters": "0-3",
+          "Defn": "Count of the number of reads issued to any of the memory controller channels.  This can be filtered by the priority of the reads.",
+          "Desc": "HA to iMC Normal Priority Reads Issued",
+          "EvSel": 23,
+          "ExtSel": "",
+          "MaxIncCyc": 4,
+          "Notes": "Does not count reads using the bypass path. That is counted separately in HA_IMC.BYPASS",
+     },
+     "HA.IMC_READS.NORMAL": {
+          "Box": "HA",
+          "Category": "HA IMC_READS Events",
+          "Counters": "0-3",
+          "Defn": "Count of the number of reads issued to any of the memory controller channels.  This can be filtered by the priority of the reads.",
+          "Desc": "HA to iMC Normal Priority Reads Issued",
+          "EvSel": 23,
+          "ExtSel": "",
+          "MaxIncCyc": 4,
+          "Notes": "Does not count reads using the bypass path. That is counted separately in HA_IMC.BYPASS",
+          "Umask": "b00000001",
+     },
+     "HA.IMC_RETRY": {
+          "Box": "HA",
+          "Category": "HA IMC_MISC Events",
+          "Counters": "0-3",
+          "Desc": "Retry Events",
+          "EvSel": 30,
+          "ExtSel": "",
+     },
+     "HA.IMC_WRITES": {
+          "Box": "HA",
+          "Category": "HA IMC_WRITES Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+          "Desc": "HA to iMC Full Line Writes Issued",
+          "EvSel": 26,
+          "ExtSel": "",
+     },
+     "HA.IMC_WRITES.FULL_ISOCH": {
+          "Box": "HA",
+          "Category": "HA IMC_WRITES Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+          "Desc": "HA to iMC Full Line Writes Issued",
+          "EvSel": 26,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "HA.IMC_WRITES.PARTIAL_ISOCH": {
+          "Box": "HA",
+          "Category": "HA IMC_WRITES Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+          "Desc": "HA to iMC Full Line Writes Issued",
+          "EvSel": 26,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "HA.IMC_WRITES.ALL": {
+          "Box": "HA",
+          "Category": "HA IMC_WRITES Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+          "Desc": "HA to iMC Full Line Writes Issued",
+          "EvSel": 26,
+          "ExtSel": "",
+          "Umask": "b00001111",
+     },
+     "HA.IMC_WRITES.PARTIAL": {
+          "Box": "HA",
+          "Category": "HA IMC_WRITES Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+          "Desc": "HA to iMC Full Line Writes Issued",
+          "EvSel": 26,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.IMC_WRITES.FULL": {
+          "Box": "HA",
+          "Category": "HA IMC_WRITES Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+          "Desc": "HA to iMC Full Line Writes Issued",
+          "EvSel": 26,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.OSB": {
+          "Box": "HA",
+          "Category": "HA OSB (Opportunistic Snoop Broadcast) Events",
+          "Counters": "0-3",
+          "Defn": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+          "Desc": "OSB Snoop Broadcast",
+          "EvSel": 83,
+          "ExtSel": "",
+     },
+     "HA.OSB.REMOTE_USEFUL": {
+          "Box": "HA",
+          "Category": "HA OSB (Opportunistic Snoop Broadcast) Events",
+          "Counters": "0-3",
+          "Defn": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+          "Desc": "OSB Snoop Broadcast",
+          "EvSel": 83,
+          "ExtSel": "",
+          "Umask": "bx1xxxxxx",
+     },
+     "HA.OSB.READS_LOCAL_USEFUL": {
+          "Box": "HA",
+          "Category": "HA OSB (Opportunistic Snoop Broadcast) Events",
+          "Counters": "0-3",
+          "Defn": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+          "Desc": "OSB Snoop Broadcast",
+          "EvSel": 83,
+          "ExtSel": "",
+          "Umask": "bxx1xxxxx",
+     },
+     "HA.OSB.CANCELLED": {
+          "Box": "HA",
+          "Category": "HA OSB (Opportunistic Snoop Broadcast) Events",
+          "Counters": "0-3",
+          "Defn": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+          "Desc": "OSB Snoop Broadcast",
+          "EvSel": 83,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "HA.OSB.INVITOE_LOCAL": {
+          "Box": "HA",
+          "Category": "HA OSB (Opportunistic Snoop Broadcast) Events",
+          "Counters": "0-3",
+          "Defn": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+          "Desc": "OSB Snoop Broadcast",
+          "EvSel": 83,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "HA.OSB.READS_LOCAL": {
+          "Box": "HA",
+          "Category": "HA OSB (Opportunistic Snoop Broadcast) Events",
+          "Counters": "0-3",
+          "Defn": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+          "Desc": "OSB Snoop Broadcast",
+          "EvSel": 83,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.OSB.REMOTE": {
+          "Box": "HA",
+          "Category": "HA OSB (Opportunistic Snoop Broadcast) Events",
+          "Counters": "0-3",
+          "Defn": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+          "Desc": "OSB Snoop Broadcast",
+          "EvSel": 83,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "HA.OSB_EDR": {
+          "Box": "HA",
+          "Category": "HA OSB (Opportunistic Snoop Broadcast) Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+          "Desc": "OSB Early Data Return",
+          "EvSel": 84,
+          "ExtSel": "",
+     },
+     "HA.OSB_EDR.READS_LOCAL_S": {
+          "Box": "HA",
+          "Category": "HA OSB (Opportunistic Snoop Broadcast) Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+          "Desc": "OSB Early Data Return",
+          "EvSel": 84,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "HA.OSB_EDR.READS_REMOTE_S": {
+          "Box": "HA",
+          "Category": "HA OSB (Opportunistic Snoop Broadcast) Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+          "Desc": "OSB Early Data Return",
+          "EvSel": 84,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "HA.OSB_EDR.READS_LOCAL_I": {
+          "Box": "HA",
+          "Category": "HA OSB (Opportunistic Snoop Broadcast) Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+          "Desc": "OSB Early Data Return",
+          "EvSel": 84,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.OSB_EDR.READS_REMOTE_I": {
+          "Box": "HA",
+          "Category": "HA OSB (Opportunistic Snoop Broadcast) Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+          "Desc": "OSB Early Data Return",
+          "EvSel": 84,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "HA.OSB_EDR.ALL": {
+          "Box": "HA",
+          "Category": "HA OSB (Opportunistic Snoop Broadcast) Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+          "Desc": "OSB Early Data Return",
+          "EvSel": 84,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.REQUESTS": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
+          "Desc": "Read and Write Requests",
+          "EvSel": 1,
+          "ExtSel": "",
+     },
+     "HA.REQUESTS.READS_REMOTE": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
+          "Desc": "Read and Write Requests",
+          "EvSel": 1,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.REQUESTS.WRITES_LOCAL": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
+          "Desc": "Read and Write Requests",
+          "EvSel": 1,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "HA.REQUESTS.READS": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
+          "Desc": "Read and Write Requests",
+          "EvSel": 1,
+          "ExtSel": "",
+          "Umask": "b00000011",
+     },
+     "HA.REQUESTS.INVITOE_REMOTE": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
+          "Desc": "Read and Write Requests",
+          "EvSel": 1,
+          "ExtSel": "",
+          "Umask": "bxx1xxxxx",
+     },
+     "HA.REQUESTS.WRITES_REMOTE": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
+          "Desc": "Read and Write Requests",
+          "EvSel": 1,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "HA.REQUESTS.WRITES": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
+          "Desc": "Read and Write Requests",
+          "EvSel": 1,
+          "ExtSel": "",
+          "Umask": "b00001100",
+     },
+     "HA.REQUESTS.INVITOE_LOCAL": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
+          "Desc": "Read and Write Requests",
+          "EvSel": 1,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "HA.REQUESTS.READS_LOCAL": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
+          "Desc": "Read and Write Requests",
+          "EvSel": 1,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.RING_AD_USED": {
+          "Box": "HA",
+          "Category": "HA RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "HA AD Ring in Use",
+          "EvSel": 62,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+     },
+     "HA.RING_AD_USED.CCW": {
+          "Box": "HA",
+          "Category": "HA RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "HA AD Ring in Use",
+          "EvSel": 62,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "b00001100",
+     },
+     "HA.RING_AD_USED.CW_EVEN": {
+          "Box": "HA",
+          "Category": "HA RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "HA AD Ring in Use",
+          "EvSel": 62,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.RING_AD_USED.CW": {
+          "Box": "HA",
+          "Category": "HA RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "HA AD Ring in Use",
+          "EvSel": 62,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "b00000011",
+     },
+     "HA.RING_AD_USED.CCW_EVEN": {
+          "Box": "HA",
+          "Category": "HA RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "HA AD Ring in Use",
+          "EvSel": 62,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxxx1xx",
+     },
+     "HA.RING_AD_USED.CW_ODD": {
+          "Box": "HA",
+          "Category": "HA RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "HA AD Ring in Use",
+          "EvSel": 62,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.RING_AD_USED.CCW_ODD": {
+          "Box": "HA",
+          "Category": "HA RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "HA AD Ring in Use",
+          "EvSel": 62,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxx1xxx",
+     },
+     "HA.RING_AK_USED": {
+          "Box": "HA",
+          "Category": "HA RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "HA AK Ring in Use",
+          "EvSel": 63,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+     },
+     "HA.RING_AK_USED.CW_ODD": {
+          "Box": "HA",
+          "Category": "HA RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "HA AK Ring in Use",
+          "EvSel": 63,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.RING_AK_USED.CCW_EVEN": {
+          "Box": "HA",
+          "Category": "HA RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "HA AK Ring in Use",
+          "EvSel": 63,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxxx1xx",
+     },
+     "HA.RING_AK_USED.CCW_ODD": {
+          "Box": "HA",
+          "Category": "HA RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "HA AK Ring in Use",
+          "EvSel": 63,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxx1xxx",
+     },
+     "HA.RING_AK_USED.ALL": {
+          "Box": "HA",
+          "Category": "HA RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "HA AK Ring in Use",
+          "EvSel": 63,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "b00001111",
+     },
+     "HA.RING_AK_USED.CW_EVEN": {
+          "Box": "HA",
+          "Category": "HA RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "HA AK Ring in Use",
+          "EvSel": 63,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.RING_AK_USED.CCW": {
+          "Box": "HA",
+          "Category": "HA RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "HA AK Ring in Use",
+          "EvSel": 63,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "b00001100",
+     },
+     "HA.RING_AK_USED.CW": {
+          "Box": "HA",
+          "Category": "HA RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "HA AK Ring in Use",
+          "EvSel": 63,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "b00000011",
+     },
+     "HA.RING_BL_USED": {
+          "Box": "HA",
+          "Category": "HA RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "HA BL Ring in Use",
+          "EvSel": 64,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+     },
+     "HA.RING_BL_USED.CW_EVEN": {
+          "Box": "HA",
+          "Category": "HA RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "HA BL Ring in Use",
+          "EvSel": 64,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.RING_BL_USED.CCW": {
+          "Box": "HA",
+          "Category": "HA RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "HA BL Ring in Use",
+          "EvSel": 64,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "b00001100",
+     },
+     "HA.RING_BL_USED.CW": {
+          "Box": "HA",
+          "Category": "HA RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "HA BL Ring in Use",
+          "EvSel": 64,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "b00000011",
+     },
+     "HA.RING_BL_USED.CW_ODD": {
+          "Box": "HA",
+          "Category": "HA RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "HA BL Ring in Use",
+          "EvSel": 64,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.RING_BL_USED.CCW_EVEN": {
+          "Box": "HA",
+          "Category": "HA RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "HA BL Ring in Use",
+          "EvSel": 64,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxxx1xx",
+     },
+     "HA.RING_BL_USED.CCW_ODD": {
+          "Box": "HA",
+          "Category": "HA RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "HA BL Ring in Use",
+          "EvSel": 64,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "bxxxx1xxx",
+     },
+     "HA.RING_BL_USED.ALL": {
+          "Box": "HA",
+          "Category": "HA RING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+          "Desc": "HA BL Ring in Use",
+          "EvSel": 64,
+          "ExtSel": "",
+          "Notes": "In any cycle, a ring stop can see up to one packet moving in the CW direction and one packet moving in the CCW direction.",
+          "Umask": "b00001111",
+     },
+     "HA.RPQ_CYCLES_NO_REG_CREDITS": {
+          "Box": "HA",
+          "Category": "HA RPQ_CREDITS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when there are no \"regular\" credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and \"special\" requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+          "Desc": "iMC RPQ Credits Empty - Regular",
+          "EvSel": 21,
+          "ExtSel": "",
+          "MaxIncCyc": 4,
+     },
+     "HA.RPQ_CYCLES_NO_REG_CREDITS.CHN3": {
+          "Box": "HA",
+          "Category": "HA RPQ_CREDITS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when there are no \"regular\" credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and \"special\" requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+          "Desc": "iMC RPQ Credits Empty - Regular",
+          "EvSel": 21,
+          "ExtSel": "",
+          "MaxIncCyc": 4,
+          "Umask": "b00001000",
+     },
+     "HA.RPQ_CYCLES_NO_REG_CREDITS.CHN0": {
+          "Box": "HA",
+          "Category": "HA RPQ_CREDITS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when there are no \"regular\" credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and \"special\" requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+          "Desc": "iMC RPQ Credits Empty - Regular",
+          "EvSel": 21,
+          "ExtSel": "",
+          "MaxIncCyc": 4,
+          "Umask": "b00000001",
+     },
+     "HA.RPQ_CYCLES_NO_REG_CREDITS.CHN2": {
+          "Box": "HA",
+          "Category": "HA RPQ_CREDITS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when there are no \"regular\" credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and \"special\" requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+          "Desc": "iMC RPQ Credits Empty - Regular",
+          "EvSel": 21,
+          "ExtSel": "",
+          "MaxIncCyc": 4,
+          "Umask": "b00000100",
+     },
+     "HA.RPQ_CYCLES_NO_REG_CREDITS.CHN1": {
+          "Box": "HA",
+          "Category": "HA RPQ_CREDITS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when there are no \"regular\" credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and \"special\" requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+          "Desc": "iMC RPQ Credits Empty - Regular",
+          "EvSel": 21,
+          "ExtSel": "",
+          "MaxIncCyc": 4,
+          "Umask": "b00000010",
+     },
+     "HA.SBO0_CREDITS_ACQUIRED": {
+          "Box": "HA",
+          "Category": "HA SBO Credit Events",
+          "Counters": "0-3",
+          "Defn": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
+          "Desc": "SBo0 Credits Acquired",
+          "EvSel": 104,
+          "ExtSel": "",
+     },
+     "HA.SBO0_CREDITS_ACQUIRED.BL": {
+          "Box": "HA",
+          "Category": "HA SBO Credit Events",
+          "Counters": "0-3",
+          "Defn": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
+          "Desc": "SBo0 Credits Acquired",
+          "EvSel": 104,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.SBO0_CREDITS_ACQUIRED.AD": {
+          "Box": "HA",
+          "Category": "HA SBO Credit Events",
+          "Counters": "0-3",
+          "Defn": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
+          "Desc": "SBo0 Credits Acquired",
+          "EvSel": 104,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.SBO0_CREDIT_OCCUPANCY": {
+          "Box": "HA",
+          "Category": "HA SBO Credit Events",
+          "Counters": "0-3",
+          "Defn": "Number of Sbo 0 credits in use in a given cycle, per ring.",
+          "Desc": "SBo0 Credits Occupancy",
+          "EvSel": 106,
+          "ExtSel": "",
+     },
+     "HA.SBO0_CREDIT_OCCUPANCY.BL": {
+          "Box": "HA",
+          "Category": "HA SBO Credit Events",
+          "Counters": "0-3",
+          "Defn": "Number of Sbo 0 credits in use in a given cycle, per ring.",
+          "Desc": "SBo0 Credits Occupancy",
+          "EvSel": 106,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.SBO0_CREDIT_OCCUPANCY.AD": {
+          "Box": "HA",
+          "Category": "HA SBO Credit Events",
+          "Counters": "0-3",
+          "Defn": "Number of Sbo 0 credits in use in a given cycle, per ring.",
+          "Desc": "SBo0 Credits Occupancy",
+          "EvSel": 106,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.SBO1_CREDITS_ACQUIRED": {
+          "Box": "HA",
+          "Category": "HA SBO Credit Events",
+          "Counters": "0-3",
+          "Defn": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
+          "Desc": "SBo1 Credits Acquired",
+          "EvSel": 105,
+          "ExtSel": "",
+     },
+     "HA.SBO1_CREDITS_ACQUIRED.BL": {
+          "Box": "HA",
+          "Category": "HA SBO Credit Events",
+          "Counters": "0-3",
+          "Defn": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
+          "Desc": "SBo1 Credits Acquired",
+          "EvSel": 105,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.SBO1_CREDITS_ACQUIRED.AD": {
+          "Box": "HA",
+          "Category": "HA SBO Credit Events",
+          "Counters": "0-3",
+          "Defn": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
+          "Desc": "SBo1 Credits Acquired",
+          "EvSel": 105,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.SBO1_CREDIT_OCCUPANCY": {
+          "Box": "HA",
+          "Category": "HA SBO Credit Events",
+          "Counters": "0-3",
+          "Defn": "Number of Sbo 1 credits in use in a given cycle, per ring.",
+          "Desc": "SBo1 Credits Occupancy",
+          "EvSel": 107,
+          "ExtSel": "",
+     },
+     "HA.SBO1_CREDIT_OCCUPANCY.BL": {
+          "Box": "HA",
+          "Category": "HA SBO Credit Events",
+          "Counters": "0-3",
+          "Defn": "Number of Sbo 1 credits in use in a given cycle, per ring.",
+          "Desc": "SBo1 Credits Occupancy",
+          "EvSel": 107,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.SBO1_CREDIT_OCCUPANCY.AD": {
+          "Box": "HA",
+          "Category": "HA SBO Credit Events",
+          "Counters": "0-3",
+          "Defn": "Number of Sbo 1 credits in use in a given cycle, per ring.",
+          "Desc": "SBo1 Credits Occupancy",
+          "EvSel": 107,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.SNOOPS_RSP_AFTER_DATA": {
+          "Box": "HA",
+          "Category": "HA SNOOPS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of reads when the snoop was on the critical path to the data return.",
+          "Desc": "Data beat the Snoop Responses",
+          "EvSel": 10,
+          "ExtSel": "",
+          "MaxIncCyc": 127,
+     },
+     "HA.SNOOPS_RSP_AFTER_DATA.LOCAL": {
+          "Box": "HA",
+          "Category": "HA SNOOPS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of reads when the snoop was on the critical path to the data return.",
+          "Desc": "Data beat the Snoop Responses",
+          "EvSel": 10,
+          "ExtSel": "",
+          "MaxIncCyc": 127,
+          "Umask": "b00000001",
+     },
+     "HA.SNOOPS_RSP_AFTER_DATA.REMOTE": {
+          "Box": "HA",
+          "Category": "HA SNOOPS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of reads when the snoop was on the critical path to the data return.",
+          "Desc": "Data beat the Snoop Responses",
+          "EvSel": 10,
+          "ExtSel": "",
+          "MaxIncCyc": 127,
+          "Umask": "b00000010",
+     },
+     "HA.SNOOP_CYCLES_NE": {
+          "Box": "HA",
+          "Category": "HA SNOOPS Events",
+          "Counters": "0-3",
+          "Defn": "Counts cycles when one or more snoops are outstanding.",
+          "Desc": "Cycles with Snoops Outstanding",
+          "EvSel": 8,
+          "ExtSel": "",
+     },
+     "HA.SNOOP_CYCLES_NE.LOCAL": {
+          "Box": "HA",
+          "Category": "HA SNOOPS Events",
+          "Counters": "0-3",
+          "Defn": "Counts cycles when one or more snoops are outstanding.",
+          "Desc": "Cycles with Snoops Outstanding",
+          "EvSel": 8,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.SNOOP_CYCLES_NE.REMOTE": {
+          "Box": "HA",
+          "Category": "HA SNOOPS Events",
+          "Counters": "0-3",
+          "Defn": "Counts cycles when one or more snoops are outstanding.",
+          "Desc": "Cycles with Snoops Outstanding",
+          "EvSel": 8,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.SNOOP_CYCLES_NE.ALL": {
+          "Box": "HA",
+          "Category": "HA SNOOPS Events",
+          "Counters": "0-3",
+          "Defn": "Counts cycles when one or more snoops are outstanding.",
+          "Desc": "Cycles with Snoops Outstanding",
+          "EvSel": 8,
+          "ExtSel": "",
+          "Umask": "b00000011",
+     },
+     "HA.SNOOP_OCCUPANCY": {
+          "Box": "HA",
+          "Category": "HA SNOOPS Events",
+          "Counters": "0-3",
+          "Defn": "Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle.    This can be used in conjection with the \"not empty\" stat to calculate average queue occupancy or the \"allocations\" stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.",
+          "Desc": "Tracker Snoops Outstanding Accumulator",
+          "EvSel": 9,
+          "ExtSel": "",
+          "MaxIncCyc": 127,
+          "SubCtr": 1,
+     },
+     "HA.SNOOP_OCCUPANCY.REMOTE": {
+          "Box": "HA",
+          "Category": "HA SNOOPS Events",
+          "Counters": "0-3",
+          "Defn": "Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle.    This can be used in conjection with the \"not empty\" stat to calculate average queue occupancy or the \"allocations\" stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.",
+          "Desc": "Tracker Snoops Outstanding Accumulator",
+          "EvSel": 9,
+          "ExtSel": "",
+          "MaxIncCyc": 127,
+          "SubCtr": 1,
+          "Umask": "b00000010",
+     },
+     "HA.SNOOP_OCCUPANCY.LOCAL": {
+          "Box": "HA",
+          "Category": "HA SNOOPS Events",
+          "Counters": "0-3",
+          "Defn": "Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle.    This can be used in conjection with the \"not empty\" stat to calculate average queue occupancy or the \"allocations\" stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.",
+          "Desc": "Tracker Snoops Outstanding Accumulator",
+          "EvSel": 9,
+          "ExtSel": "",
+          "MaxIncCyc": 127,
+          "SubCtr": 1,
+          "Umask": "b00000001",
+     },
+     "HA.SNOOP_RESP": {
+          "Box": "HA",
+          "Category": "HA SNP_RESP Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.",
+          "Desc": "Snoop Responses Received",
+          "EvSel": 33,
+          "ExtSel": "",
+     },
+     "HA.SNOOP_RESP.RSPS": {
+          "Box": "HA",
+          "Category": "HA SNP_RESP Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.",
+          "Desc": "Snoop Responses Received",
+          "EvSel": 33,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.SNOOP_RESP.RSPIFWD": {
+          "Box": "HA",
+          "Category": "HA SNP_RESP Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.",
+          "Desc": "Snoop Responses Received",
+          "EvSel": 33,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "HA.SNOOP_RESP.RSPCNFLCT": {
+          "Box": "HA",
+          "Category": "HA SNP_RESP Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.",
+          "Desc": "Snoop Responses Received",
+          "EvSel": 33,
+          "ExtSel": "",
+          "Umask": "bx1xxxxxx",
+     },
+     "HA.SNOOP_RESP.RSPSFWD": {
+          "Box": "HA",
+          "Category": "HA SNP_RESP Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.",
+          "Desc": "Snoop Responses Received",
+          "EvSel": 33,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "HA.SNOOP_RESP.RSP_WB": {
+          "Box": "HA",
+          "Category": "HA SNP_RESP Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.",
+          "Desc": "Snoop Responses Received",
+          "EvSel": 33,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "HA.SNOOP_RESP.RSP_FWD_WB": {
+          "Box": "HA",
+          "Category": "HA SNP_RESP Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.",
+          "Desc": "Snoop Responses Received",
+          "EvSel": 33,
+          "ExtSel": "",
+          "Umask": "bxx1xxxxx",
+     },
+     "HA.SNOOP_RESP.RSPI": {
+          "Box": "HA",
+          "Category": "HA SNP_RESP Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.",
+          "Desc": "Snoop Responses Received",
+          "EvSel": 33,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.SNP_RESP_RECV_LOCAL": {
+          "Box": "HA",
+          "Category": "HA SNP_RESP Events",
+          "Counters": "0-3",
+          "Defn": "Number of snoop responses received for a Local  request",
+          "Desc": "Snoop Responses Received Local",
+          "EvSel": 96,
+          "ExtSel": "",
+     },
+     "HA.SNP_RESP_RECV_LOCAL.RSPxWB": {
+          "Box": "HA",
+          "Category": "HA SNP_RESP Events",
+          "Counters": "0-3",
+          "Defn": "Number of snoop responses received for a Local  request",
+          "Desc": "Snoop Responses Received Local",
+          "EvSel": 96,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "HA.SNP_RESP_RECV_LOCAL.RSPS": {
+          "Box": "HA",
+          "Category": "HA SNP_RESP Events",
+          "Counters": "0-3",
+          "Defn": "Number of snoop responses received for a Local  request",
+          "Desc": "Snoop Responses Received Local",
+          "EvSel": 96,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.SNP_RESP_RECV_LOCAL.OTHER": {
+          "Box": "HA",
+          "Category": "HA SNP_RESP Events",
+          "Counters": "0-3",
+          "Defn": "Number of snoop responses received for a Local  request",
+          "Desc": "Snoop Responses Received Local",
+          "EvSel": 96,
+          "ExtSel": "",
+          "Umask": "b1xxxxxxx",
+     },
+     "HA.SNP_RESP_RECV_LOCAL.RSPI": {
+          "Box": "HA",
+          "Category": "HA SNP_RESP Events",
+          "Counters": "0-3",
+          "Defn": "Number of snoop responses received for a Local  request",
+          "Desc": "Snoop Responses Received Local",
+          "EvSel": 96,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.SNP_RESP_RECV_LOCAL.RSPSFWD": {
+          "Box": "HA",
+          "Category": "HA SNP_RESP Events",
+          "Counters": "0-3",
+          "Defn": "Number of snoop responses received for a Local  request",
+          "Desc": "Snoop Responses Received Local",
+          "EvSel": 96,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "HA.SNP_RESP_RECV_LOCAL.RSPCNFLCT": {
+          "Box": "HA",
+          "Category": "HA SNP_RESP Events",
+          "Counters": "0-3",
+          "Defn": "Number of snoop responses received for a Local  request",
+          "Desc": "Snoop Responses Received Local",
+          "EvSel": 96,
+          "ExtSel": "",
+          "Umask": "bx1xxxxxx",
+     },
+     "HA.SNP_RESP_RECV_LOCAL.RSPxFWDxWB": {
+          "Box": "HA",
+          "Category": "HA SNP_RESP Events",
+          "Counters": "0-3",
+          "Defn": "Number of snoop responses received for a Local  request",
+          "Desc": "Snoop Responses Received Local",
+          "EvSel": 96,
+          "ExtSel": "",
+          "Umask": "bxx1xxxxx",
+     },
+     "HA.SNP_RESP_RECV_LOCAL.RSPIFWD": {
+          "Box": "HA",
+          "Category": "HA SNP_RESP Events",
+          "Counters": "0-3",
+          "Defn": "Number of snoop responses received for a Local  request",
+          "Desc": "Snoop Responses Received Local",
+          "EvSel": 96,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "HA.STALL_NO_SBO_CREDIT": {
+          "Box": "HA",
+          "Category": "HA SBO Credit Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+          "Desc": "Stall on No Sbo Credits",
+          "EvSel": 108,
+          "ExtSel": "",
+     },
+     "HA.STALL_NO_SBO_CREDIT.SBO1_BL": {
+          "Box": "HA",
+          "Category": "HA SBO Credit Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+          "Desc": "Stall on No Sbo Credits",
+          "EvSel": 108,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "HA.STALL_NO_SBO_CREDIT.SBO0_AD": {
+          "Box": "HA",
+          "Category": "HA SBO Credit Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+          "Desc": "Stall on No Sbo Credits",
+          "EvSel": 108,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.STALL_NO_SBO_CREDIT.SBO1_AD": {
+          "Box": "HA",
+          "Category": "HA SBO Credit Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+          "Desc": "Stall on No Sbo Credits",
+          "EvSel": 108,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.STALL_NO_SBO_CREDIT.SBO0_BL": {
+          "Box": "HA",
+          "Category": "HA SBO Credit Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+          "Desc": "Stall on No Sbo Credits",
+          "EvSel": 108,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "HA.TAD_REQUESTS_G0": {
+          "Box": "HA",
+          "Category": "HA TAD Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for \"Monroe\" systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+          "Desc": "HA Requests to a TAD Region - Group 0",
+          "EvSel": 27,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+     },
+     "HA.TAD_REQUESTS_G0.REGION6": {
+          "Box": "HA",
+          "Category": "HA TAD Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for \"Monroe\" systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+          "Desc": "HA Requests to a TAD Region - Group 0",
+          "EvSel": 27,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Umask": "b01000000",
+     },
+     "HA.TAD_REQUESTS_G0.REGION1": {
+          "Box": "HA",
+          "Category": "HA TAD Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for \"Monroe\" systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+          "Desc": "HA Requests to a TAD Region - Group 0",
+          "EvSel": 27,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Umask": "b00000010",
+     },
+     "HA.TAD_REQUESTS_G0.REGION4": {
+          "Box": "HA",
+          "Category": "HA TAD Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for \"Monroe\" systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+          "Desc": "HA Requests to a TAD Region - Group 0",
+          "EvSel": 27,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Umask": "b00010000",
+     },
+     "HA.TAD_REQUESTS_G0.REGION7": {
+          "Box": "HA",
+          "Category": "HA TAD Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for \"Monroe\" systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+          "Desc": "HA Requests to a TAD Region - Group 0",
+          "EvSel": 27,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Umask": "b10000000",
+     },
+     "HA.TAD_REQUESTS_G0.REGION0": {
+          "Box": "HA",
+          "Category": "HA TAD Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for \"Monroe\" systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+          "Desc": "HA Requests to a TAD Region - Group 0",
+          "EvSel": 27,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Umask": "b00000001",
+     },
+     "HA.TAD_REQUESTS_G0.REGION3": {
+          "Box": "HA",
+          "Category": "HA TAD Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for \"Monroe\" systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+          "Desc": "HA Requests to a TAD Region - Group 0",
+          "EvSel": 27,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Umask": "b00001000",
+     },
+     "HA.TAD_REQUESTS_G0.REGION2": {
+          "Box": "HA",
+          "Category": "HA TAD Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for \"Monroe\" systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+          "Desc": "HA Requests to a TAD Region - Group 0",
+          "EvSel": 27,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Umask": "b00000100",
+     },
+     "HA.TAD_REQUESTS_G0.REGION5": {
+          "Box": "HA",
+          "Category": "HA TAD Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for \"Monroe\" systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+          "Desc": "HA Requests to a TAD Region - Group 0",
+          "EvSel": 27,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Umask": "b00100000",
+     },
+     "HA.TAD_REQUESTS_G1": {
+          "Box": "HA",
+          "Category": "HA TAD Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for \"Monroe\" systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+          "Desc": "HA Requests to a TAD Region - Group 1",
+          "EvSel": 28,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+     },
+     "HA.TAD_REQUESTS_G1.REGION9": {
+          "Box": "HA",
+          "Category": "HA TAD Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for \"Monroe\" systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+          "Desc": "HA Requests to a TAD Region - Group 1",
+          "EvSel": 28,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Umask": "b00000010",
+     },
+     "HA.TAD_REQUESTS_G1.REGION11": {
+          "Box": "HA",
+          "Category": "HA TAD Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for \"Monroe\" systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+          "Desc": "HA Requests to a TAD Region - Group 1",
+          "EvSel": 28,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Umask": "b00001000",
+     },
+     "HA.TAD_REQUESTS_G1.REGION10": {
+          "Box": "HA",
+          "Category": "HA TAD Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for \"Monroe\" systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+          "Desc": "HA Requests to a TAD Region - Group 1",
+          "EvSel": 28,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Umask": "b00000100",
+     },
+     "HA.TAD_REQUESTS_G1.REGION8": {
+          "Box": "HA",
+          "Category": "HA TAD Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for \"Monroe\" systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+          "Desc": "HA Requests to a TAD Region - Group 1",
+          "EvSel": 28,
+          "ExtSel": "",
+          "MaxIncCyc": 2,
+          "Umask": "b00000001",
+     },
+     "HA.TRACKER_CYCLES_FULL": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the local HA tracker pool is completely used.  This can be used with edge detect to identify the number of situations when the pool became fully utilized.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, the system could be starved for RTIDs but not fill up the HA trackers.  HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+          "Desc": "Tracker Cycles Full",
+          "EvSel": 2,
+          "ExtSel": "",
+     },
+     "HA.TRACKER_CYCLES_FULL.ALL": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the local HA tracker pool is completely used.  This can be used with edge detect to identify the number of situations when the pool became fully utilized.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, the system could be starved for RTIDs but not fill up the HA trackers.  HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+          "Desc": "Tracker Cycles Full",
+          "EvSel": 2,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.TRACKER_CYCLES_FULL.GP": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the local HA tracker pool is completely used.  This can be used with edge detect to identify the number of situations when the pool became fully utilized.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, the system could be starved for RTIDs but not fill up the HA trackers.  HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+          "Desc": "Tracker Cycles Full",
+          "EvSel": 2,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.TRACKER_CYCLES_NE": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+          "Desc": "Tracker Cycles Not Empty",
+          "EvSel": 3,
+          "ExtSel": "",
+     },
+     "HA.TRACKER_CYCLES_NE.REMOTE": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+          "Desc": "Tracker Cycles Not Empty",
+          "EvSel": 3,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.TRACKER_CYCLES_NE.LOCAL": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+          "Desc": "Tracker Cycles Not Empty",
+          "EvSel": 3,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.TRACKER_CYCLES_NE.ALL": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+          "Desc": "Tracker Cycles Not Empty",
+          "EvSel": 3,
+          "ExtSel": "",
+          "Umask": "b00000011",
+     },
+     "HA.TRACKER_OCCUPANCY": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the \"not empty\" stat to calculate average queue occupancy or the \"allocations\" stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+          "Desc": "Tracker Occupancy Accumultor",
+          "EvSel": 4,
+          "ExtSel": "",
+          "MaxIncCyc": 128,
+          "SubCtr": 1,
+     },
+     "HA.TRACKER_OCCUPANCY.READS_LOCAL": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the \"not empty\" stat to calculate average queue occupancy or the \"allocations\" stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+          "Desc": "Tracker Occupancy Accumultor",
+          "EvSel": 4,
+          "ExtSel": "",
+          "MaxIncCyc": 128,
+          "SubCtr": 1,
+          "Umask": "bxxxxx1xx",
+     },
+     "HA.TRACKER_OCCUPANCY.INVITOE_LOCAL": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the \"not empty\" stat to calculate average queue occupancy or the \"allocations\" stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+          "Desc": "Tracker Occupancy Accumultor",
+          "EvSel": 4,
+          "ExtSel": "",
+          "MaxIncCyc": 128,
+          "SubCtr": 1,
+          "Umask": "bx1xxxxxx",
+     },
+     "HA.TRACKER_OCCUPANCY.READS_REMOTE": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the \"not empty\" stat to calculate average queue occupancy or the \"allocations\" stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+          "Desc": "Tracker Occupancy Accumultor",
+          "EvSel": 4,
+          "ExtSel": "",
+          "MaxIncCyc": 128,
+          "SubCtr": 1,
+          "Umask": "bxxxx1xxx",
+     },
+     "HA.TRACKER_OCCUPANCY.WRITES_REMOTE": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the \"not empty\" stat to calculate average queue occupancy or the \"allocations\" stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+          "Desc": "Tracker Occupancy Accumultor",
+          "EvSel": 4,
+          "ExtSel": "",
+          "MaxIncCyc": 128,
+          "SubCtr": 1,
+          "Umask": "bxx1xxxxx",
+     },
+     "HA.TRACKER_OCCUPANCY.INVITOE_REMOTE": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the \"not empty\" stat to calculate average queue occupancy or the \"allocations\" stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+          "Desc": "Tracker Occupancy Accumultor",
+          "EvSel": 4,
+          "ExtSel": "",
+          "MaxIncCyc": 128,
+          "SubCtr": 1,
+          "Umask": "b1xxxxxxx",
+     },
+     "HA.TRACKER_OCCUPANCY.WRITES_LOCAL": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the \"not empty\" stat to calculate average queue occupancy or the \"allocations\" stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+          "Desc": "Tracker Occupancy Accumultor",
+          "EvSel": 4,
+          "ExtSel": "",
+          "MaxIncCyc": 128,
+          "SubCtr": 1,
+          "Umask": "bxxx1xxxx",
+     },
+     "HA.TRACKER_PENDING_OCCUPANCY": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress.  This can be used to calculate the queuing latency for two things.  (1) If the system is waiting for snoops, this will increase.  (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.",
+          "Desc": "Data Pending Occupancy Accumultor",
+          "EvSel": 5,
+          "ExtSel": "",
+          "MaxIncCyc": 127,
+          "SubCtr": 1,
+     },
+     "HA.TRACKER_PENDING_OCCUPANCY.REMOTE": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress.  This can be used to calculate the queuing latency for two things.  (1) If the system is waiting for snoops, this will increase.  (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.",
+          "Desc": "Data Pending Occupancy Accumultor",
+          "EvSel": 5,
+          "ExtSel": "",
+          "MaxIncCyc": 127,
+          "SubCtr": 1,
+          "Umask": "b00000010",
+     },
+     "HA.TRACKER_PENDING_OCCUPANCY.LOCAL": {
+          "Box": "HA",
+          "Category": "HA TRACKER Events",
+          "Counters": "0-3",
+          "Defn": "Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress.  This can be used to calculate the queuing latency for two things.  (1) If the system is waiting for snoops, this will increase.  (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.",
+          "Desc": "Data Pending Occupancy Accumultor",
+          "EvSel": 5,
+          "ExtSel": "",
+          "MaxIncCyc": 127,
+          "SubCtr": 1,
+          "Umask": "b00000001",
+     },
+     "HA.TxR_AD_CYCLES_FULL": {
+          "Box": "HA",
+          "Category": "HA EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "AD Egress Full",
+          "Desc": "AD Egress Full",
+          "EvSel": 42,
+          "ExtSel": "",
+     },
+     "HA.TxR_AD_CYCLES_FULL.ALL": {
+          "Box": "HA",
+          "Category": "HA EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "AD Egress Full",
+          "Desc": "AD Egress Full",
+          "EvSel": 42,
+          "ExtSel": "",
+          "Umask": "bxxxxxx11",
+     },
+     "HA.TxR_AD_CYCLES_FULL.SCHED1": {
+          "Box": "HA",
+          "Category": "HA EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "AD Egress Full",
+          "Desc": "AD Egress Full",
+          "EvSel": 42,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.TxR_AD_CYCLES_FULL.SCHED0": {
+          "Box": "HA",
+          "Category": "HA EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "AD Egress Full",
+          "Desc": "AD Egress Full",
+          "EvSel": 42,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.TxR_AK": {
+          "Box": "HA",
+          "Category": "HA OUTBOUND_TX Events",
+          "Counters": "0-3",
+          "Desc": "Outbound Ring Transactions on AK",
+          "EvSel": 14,
+          "ExtSel": "",
+     },
+     "HA.TxR_AK_CYCLES_FULL": {
+          "Box": "HA",
+          "Category": "HA EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "AK Egress Full",
+          "Desc": "AK Egress Full",
+          "EvSel": 50,
+          "ExtSel": "",
+     },
+     "HA.TxR_AK_CYCLES_FULL.SCHED0": {
+          "Box": "HA",
+          "Category": "HA EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "AK Egress Full",
+          "Desc": "AK Egress Full",
+          "EvSel": 50,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.TxR_AK_CYCLES_FULL.SCHED1": {
+          "Box": "HA",
+          "Category": "HA EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "AK Egress Full",
+          "Desc": "AK Egress Full",
+          "EvSel": 50,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.TxR_AK_CYCLES_FULL.ALL": {
+          "Box": "HA",
+          "Category": "HA EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "AK Egress Full",
+          "Desc": "AK Egress Full",
+          "EvSel": 50,
+          "ExtSel": "",
+          "Umask": "bxxxxxx11",
+     },
+     "HA.TxR_BL": {
+          "Box": "HA",
+          "Category": "HA OUTBOUND_TX Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.",
+          "Desc": "Outbound DRS Ring Transactions to Cache",
+          "EvSel": 16,
+          "ExtSel": "",
+     },
+     "HA.TxR_BL.DRS_CORE": {
+          "Box": "HA",
+          "Category": "HA OUTBOUND_TX Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.",
+          "Desc": "Outbound DRS Ring Transactions to Cache",
+          "EvSel": 16,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.TxR_BL.DRS_CACHE": {
+          "Box": "HA",
+          "Category": "HA OUTBOUND_TX Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.",
+          "Desc": "Outbound DRS Ring Transactions to Cache",
+          "EvSel": 16,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.TxR_BL.DRS_QPI": {
+          "Box": "HA",
+          "Category": "HA OUTBOUND_TX Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.",
+          "Desc": "Outbound DRS Ring Transactions to Cache",
+          "EvSel": 16,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "HA.TxR_BL_CYCLES_FULL": {
+          "Box": "HA",
+          "Category": "HA EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "BL Egress Full",
+          "Desc": "BL Egress Full",
+          "EvSel": 54,
+          "ExtSel": "",
+     },
+     "HA.TxR_BL_CYCLES_FULL.SCHED1": {
+          "Box": "HA",
+          "Category": "HA EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "BL Egress Full",
+          "Desc": "BL Egress Full",
+          "EvSel": 54,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.TxR_BL_CYCLES_FULL.ALL": {
+          "Box": "HA",
+          "Category": "HA EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "BL Egress Full",
+          "Desc": "BL Egress Full",
+          "EvSel": 54,
+          "ExtSel": "",
+          "Umask": "bxxxxxx11",
+     },
+     "HA.TxR_BL_CYCLES_FULL.SCHED0": {
+          "Box": "HA",
+          "Category": "HA EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "BL Egress Full",
+          "Desc": "BL Egress Full",
+          "EvSel": 54,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.TxR_BL_OCCUPANCY": {
+          "Box": "HA",
+          "Category": "HA BL_EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "BL Egress Occupancy",
+          "Desc": "BL Egress Occupancy",
+          "EvSel": 52,
+          "ExtSel": "",
+          "MaxIncCyc": 20,
+          "SubCtr": 1,
+     },
+     "HA.TxR_STARVED": {
+          "Box": "HA",
+          "Category": "HA EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
+          "Desc": "Injection Starvation",
+          "EvSel": 109,
+          "ExtSel": "",
+     },
+     "HA.TxR_STARVED.BL": {
+          "Box": "HA",
+          "Category": "HA EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
+          "Desc": "Injection Starvation",
+          "EvSel": 109,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "HA.TxR_STARVED.AK": {
+          "Box": "HA",
+          "Category": "HA EGRESS Events",
+          "Counters": "0-3",
+          "Defn": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
+          "Desc": "Injection Starvation",
+          "EvSel": 109,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "HA.WPQ_CYCLES_NO_REG_CREDITS": {
+          "Box": "HA",
+          "Category": "HA WPQ_CREDITS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when there are no \"regular\" credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and \"special\" requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+          "Desc": "HA iMC CHN0 WPQ Credits Empty - Regular",
+          "EvSel": 24,
+          "ExtSel": "",
+          "MaxIncCyc": 4,
+     },
+     "HA.WPQ_CYCLES_NO_REG_CREDITS.CHN3": {
+          "Box": "HA",
+          "Category": "HA WPQ_CREDITS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when there are no \"regular\" credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and \"special\" requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+          "Desc": "HA iMC CHN0 WPQ Credits Empty - Regular",
+          "EvSel": 24,
+          "ExtSel": "",
+          "MaxIncCyc": 4,
+          "Umask": "b00001000",
+     },
+     "HA.WPQ_CYCLES_NO_REG_CREDITS.CHN0": {
+          "Box": "HA",
+          "Category": "HA WPQ_CREDITS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when there are no \"regular\" credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and \"special\" requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+          "Desc": "HA iMC CHN0 WPQ Credits Empty - Regular",
+          "EvSel": 24,
+          "ExtSel": "",
+          "MaxIncCyc": 4,
+          "Umask": "b00000001",
+     },
+     "HA.WPQ_CYCLES_NO_REG_CREDITS.CHN2": {
+          "Box": "HA",
+          "Category": "HA WPQ_CREDITS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when there are no \"regular\" credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and \"special\" requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+          "Desc": "HA iMC CHN0 WPQ Credits Empty - Regular",
+          "EvSel": 24,
+          "ExtSel": "",
+          "MaxIncCyc": 4,
+          "Umask": "b00000100",
+     },
+     "HA.WPQ_CYCLES_NO_REG_CREDITS.CHN1": {
+          "Box": "HA",
+          "Category": "HA WPQ_CREDITS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when there are no \"regular\" credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and \"special\" requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+          "Desc": "HA iMC CHN0 WPQ Credits Empty - Regular",
+          "EvSel": 24,
+          "ExtSel": "",
+          "MaxIncCyc": 4,
+          "Umask": "b00000010",
+     },
+     
+# iMC:
+     "iMC.ACT_COUNT": {
+          "Box": "iMC",
+          "Category": "iMC ACT Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+          "Desc": "DRAM Activate Count",
+          "EvSel": 1,
+          "ExtSel": "",
+     },
+     "iMC.ACT_COUNT.BYP": {
+          "Box": "iMC",
+          "Category": "iMC ACT Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+          "Desc": "DRAM Activate Count",
+          "EvSel": 1,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "iMC.ACT_COUNT.WR": {
+          "Box": "iMC",
+          "Category": "iMC ACT Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+          "Desc": "DRAM Activate Count",
+          "EvSel": 1,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "iMC.ACT_COUNT.RD": {
+          "Box": "iMC",
+          "Category": "iMC ACT Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+          "Desc": "DRAM Activate Count",
+          "EvSel": 1,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "iMC.BYP_CMDS": {
+          "Box": "iMC",
+          "Category": "iMC BYPASS Command Events",
+          "Counters": "0-3",
+          "EvSel": 161,
+          "ExtSel": "",
+     },
+     "iMC.BYP_CMDS.CAS": {
+          "Box": "iMC",
+          "Category": "iMC BYPASS Command Events",
+          "Counters": "0-3",
+          "EvSel": 161,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "iMC.BYP_CMDS.PRE": {
+          "Box": "iMC",
+          "Category": "iMC BYPASS Command Events",
+          "Counters": "0-3",
+          "EvSel": 161,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "iMC.BYP_CMDS.ACT": {
+          "Box": "iMC",
+          "Category": "iMC BYPASS Command Events",
+          "Counters": "0-3",
+          "EvSel": 161,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "iMC.CAS_COUNT": {
+          "Box": "iMC",
+          "Category": "iMC PRE Events",
+          "Counters": "0-3",
+          "Defn": "DRAM RD_CAS and WR_CAS Commands",
+          "Desc": "DRAM RD_CAS and WR_CAS Commands.",
+          "EvSel": 4,
+          "ExtSel": "",
+     },
+     "iMC.CAS_COUNT.RD_UNDERFILL": {
+          "Box": "iMC",
+          "Category": "iMC PRE Events",
+          "Counters": "0-3",
+          "Defn": "DRAM RD_CAS and WR_CAS Commands",
+          "Desc": "DRAM RD_CAS and WR_CAS Commands.",
+          "EvSel": 4,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "iMC.CAS_COUNT.RD_RMM": {
+          "Box": "iMC",
+          "Category": "iMC PRE Events",
+          "Counters": "0-3",
+          "Defn": "DRAM RD_CAS and WR_CAS Commands",
+          "Desc": "DRAM RD_CAS and WR_CAS Commands.",
+          "EvSel": 4,
+          "ExtSel": "",
+          "Umask": "bxx1xxxxx",
+     },
+     "iMC.CAS_COUNT.RD_REG": {
+          "Box": "iMC",
+          "Category": "iMC PRE Events",
+          "Counters": "0-3",
+          "Defn": "DRAM RD_CAS and WR_CAS Commands",
+          "Desc": "DRAM RD_CAS and WR_CAS Commands.",
+          "EvSel": 4,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "iMC.CAS_COUNT.RD_WMM": {
+          "Box": "iMC",
+          "Category": "iMC PRE Events",
+          "Counters": "0-3",
+          "Defn": "DRAM RD_CAS and WR_CAS Commands",
+          "Desc": "DRAM RD_CAS and WR_CAS Commands.",
+          "EvSel": 4,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "iMC.CAS_COUNT.WR_RMM": {
+          "Box": "iMC",
+          "Category": "iMC PRE Events",
+          "Counters": "0-3",
+          "Defn": "DRAM RD_CAS and WR_CAS Commands",
+          "Desc": "DRAM RD_CAS and WR_CAS Commands.",
+          "EvSel": 4,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "iMC.CAS_COUNT.RD": {
+          "Box": "iMC",
+          "Category": "iMC PRE Events",
+          "Counters": "0-3",
+          "Defn": "DRAM RD_CAS and WR_CAS Commands",
+          "Desc": "DRAM RD_CAS and WR_CAS Commands.",
+          "EvSel": 4,
+          "ExtSel": "",
+          "Umask": "b00000011",
+     },
+     "iMC.CAS_COUNT.WR": {
+          "Box": "iMC",
+          "Category": "iMC PRE Events",
+          "Counters": "0-3",
+          "Defn": "DRAM RD_CAS and WR_CAS Commands",
+          "Desc": "DRAM RD_CAS and WR_CAS Commands.",
+          "EvSel": 4,
+          "ExtSel": "",
+          "Umask": "b00001100",
+     },
+     "iMC.CAS_COUNT.ALL": {
+          "Box": "iMC",
+          "Category": "iMC PRE Events",
+          "Counters": "0-3",
+          "Defn": "DRAM RD_CAS and WR_CAS Commands",
+          "Desc": "DRAM RD_CAS and WR_CAS Commands.",
+          "EvSel": 4,
+          "ExtSel": "",
+          "Umask": "b00001111",
+     },
+     "iMC.CAS_COUNT.WR_WMM": {
+          "Box": "iMC",
+          "Category": "iMC PRE Events",
+          "Counters": "0-3",
+          "Defn": "DRAM RD_CAS and WR_CAS Commands",
+          "Desc": "DRAM RD_CAS and WR_CAS Commands.",
+          "EvSel": 4,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "iMC.DCLOCKTICKS": {
+          "Box": "iMC",
+          "Category": "iMC DCLK Events",
+          "Counters": "0-3",
+          "Desc": "DRAM Clockticks",
+          "EvSel": 0,
+          "ExtSel": "",
+     },
+     "iMC.DRAM_PRE_ALL": {
+          "Box": "iMC",
+          "Category": "iMC DRAM_PRE_ALL Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times that the precharge all command was sent.",
+          "Desc": "DRAM Precharge All Commands",
+          "EvSel": 6,
+          "ExtSel": "",
+     },
+     "iMC.DRAM_REFRESH": {
+          "Box": "iMC",
+          "Category": "iMC DRAM_REFRESH Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of refreshes issued.",
+          "Desc": "Number of DRAM Refreshes Issued",
+          "EvSel": 5,
+          "ExtSel": "",
+     },
+     "iMC.DRAM_REFRESH.PANIC": {
+          "Box": "iMC",
+          "Category": "iMC DRAM_REFRESH Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of refreshes issued.",
+          "Desc": "Number of DRAM Refreshes Issued",
+          "EvSel": 5,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "iMC.DRAM_REFRESH.HIGH": {
+          "Box": "iMC",
+          "Category": "iMC DRAM_REFRESH Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of refreshes issued.",
+          "Desc": "Number of DRAM Refreshes Issued",
+          "EvSel": 5,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "iMC.ECC_CORRECTABLE_ERRORS": {
+          "Box": "iMC",
+          "Category": "iMC ECC Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of ECC errors detected and corrected by the iMC on this channel.  This counter is only useful with ECC DRAM devices.  This count will increment one time for each correction regardless of the number of bits corrected.  The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode.",
+          "Desc": "ECC Correctable Errors",
+          "EvSel": 9,
+          "ExtSel": "",
+     },
+     "iMC.MAJOR_MODES": {
+          "Box": "iMC",
+          "Category": "iMC MAJOR_MODES Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.",
+          "Desc": "Cycles in a Major Mode",
+          "EvSel": 7,
+          "ExtSel": "",
+     },
+     "iMC.MAJOR_MODES.WRITE": {
+          "Box": "iMC",
+          "Category": "iMC MAJOR_MODES Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.",
+          "Desc": "Cycles in a Major Mode",
+          "EvSel": 7,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "iMC.MAJOR_MODES.PARTIAL": {
+          "Box": "iMC",
+          "Category": "iMC MAJOR_MODES Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.",
+          "Desc": "Cycles in a Major Mode",
+          "EvSel": 7,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "iMC.MAJOR_MODES.ISOCH": {
+          "Box": "iMC",
+          "Category": "iMC MAJOR_MODES Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.",
+          "Desc": "Cycles in a Major Mode",
+          "EvSel": 7,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "iMC.MAJOR_MODES.READ": {
+          "Box": "iMC",
+          "Category": "iMC MAJOR_MODES Events",
+          "Counters": "0-3",
+          "Defn": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.",
+          "Desc": "Cycles in a Major Mode",
+          "EvSel": 7,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "iMC.POWER_CHANNEL_DLLOFF": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.",
+          "Desc": "Channel DLLOFF Cycles",
+          "EvSel": 132,
+          "ExtSel": "",
+          "Notes": "IBT = Input Buffer Termination = Off",
+     },
+     "iMC.POWER_CHANNEL_PPD": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles when all the ranks in the channel are in PPD mode.  If IBT=off is enabled, then this can be used to count those cycles.  If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.",
+          "Desc": "Channel PPD Cycles",
+          "EvSel": 133,
+          "ExtSel": "",
+          "MaxIncCyc": 4,
+          "Notes": "IBT = Input Buffer Termination = On.   ALL Ranks must be populated in order to measure",
+     },
+     "iMC.POWER_CKE_CYCLES": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+          "Desc": "CKE_ON_CYCLES by Rank",
+          "EvSel": 131,
+          "ExtSel": "",
+          "MaxIncCyc": 16,
+     },
+     "iMC.POWER_CKE_CYCLES.RANK0": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+          "Desc": "CKE_ON_CYCLES by Rank",
+          "EvSel": 131,
+          "ExtSel": "",
+          "MaxIncCyc": 16,
+          "Umask": "b00000001",
+     },
+     "iMC.POWER_CKE_CYCLES.RANK2": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+          "Desc": "CKE_ON_CYCLES by Rank",
+          "EvSel": 131,
+          "ExtSel": "",
+          "MaxIncCyc": 16,
+          "Umask": "b00000100",
+     },
+     "iMC.POWER_CKE_CYCLES.RANK6": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+          "Desc": "CKE_ON_CYCLES by Rank",
+          "EvSel": 131,
+          "ExtSel": "",
+          "MaxIncCyc": 16,
+          "Umask": "b01000000",
+     },
+     "iMC.POWER_CKE_CYCLES.RANK5": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+          "Desc": "CKE_ON_CYCLES by Rank",
+          "EvSel": 131,
+          "ExtSel": "",
+          "MaxIncCyc": 16,
+          "Umask": "b00100000",
+     },
+     "iMC.POWER_CKE_CYCLES.RANK7": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+          "Desc": "CKE_ON_CYCLES by Rank",
+          "EvSel": 131,
+          "ExtSel": "",
+          "MaxIncCyc": 16,
+          "Umask": "b10000000",
+     },
+     "iMC.POWER_CKE_CYCLES.RANK1": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+          "Desc": "CKE_ON_CYCLES by Rank",
+          "EvSel": 131,
+          "ExtSel": "",
+          "MaxIncCyc": 16,
+          "Umask": "b00000010",
+     },
+     "iMC.POWER_CKE_CYCLES.RANK3": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+          "Desc": "CKE_ON_CYCLES by Rank",
+          "EvSel": 131,
+          "ExtSel": "",
+          "MaxIncCyc": 16,
+          "Umask": "b00001000",
+     },
+     "iMC.POWER_CKE_CYCLES.RANK4": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+          "Desc": "CKE_ON_CYCLES by Rank",
+          "EvSel": 131,
+          "ExtSel": "",
+          "MaxIncCyc": 16,
+          "Umask": "b00010000",
+     },
+     "iMC.POWER_CRITICAL_THROTTLE_CYCLES": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the iMC is in critical thermal throttling.  When this happens, all traffic is blocked.  This should be rare unless something bad is going on in the platform.  There is no filtering by rank for this event.",
+          "Desc": "Critical Throttle Cycles",
+          "EvSel": 134,
+          "ExtSel": "",
+     },
+     "iMC.POWER_PCU_THROTTLING": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Counters": "0-3",
+          "EvSel": 66,
+          "ExtSel": "",
+     },
+     "iMC.POWER_SELF_REFRESH": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock.  This happens in some package C-states.  For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing.  One use of this is for Monroe technology.  Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
+          "Desc": "Clock-Enabled Self-Refresh",
+          "EvSel": 67,
+          "ExtSel": "",
+     },
+     "iMC.POWER_THROTTLE_CYCLES": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+          "Desc": "Throttle Cycles for Rank 0",
+          "EvSel": 65,
+          "ExtSel": "",
+     },
+     "iMC.POWER_THROTTLE_CYCLES.RANK2": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+          "Desc": "Throttle Cycles for Rank 0",
+          "EvSel": 65,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "iMC.POWER_THROTTLE_CYCLES.RANK6": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+          "Desc": "Throttle Cycles for Rank 0",
+          "EvSel": 65,
+          "ExtSel": "",
+          "Umask": "bx1xxxxxx",
+     },
+     "iMC.POWER_THROTTLE_CYCLES.RANK5": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+          "Desc": "Throttle Cycles for Rank 0",
+          "EvSel": 65,
+          "ExtSel": "",
+          "Umask": "bxx1xxxxx",
+     },
+     "iMC.POWER_THROTTLE_CYCLES.RANK7": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+          "Desc": "Throttle Cycles for Rank 0",
+          "EvSel": 65,
+          "ExtSel": "",
+          "Umask": "b1xxxxxxx",
+     },
+     "iMC.POWER_THROTTLE_CYCLES.RANK0": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+          "Desc": "Throttle Cycles for Rank 0",
+          "EvSel": 65,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "iMC.POWER_THROTTLE_CYCLES.RANK4": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+          "Desc": "Throttle Cycles for Rank 0",
+          "EvSel": 65,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "iMC.POWER_THROTTLE_CYCLES.RANK1": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+          "Desc": "Throttle Cycles for Rank 0",
+          "EvSel": 65,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "iMC.POWER_THROTTLE_CYCLES.RANK3": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+          "Desc": "Throttle Cycles for Rank 0",
+          "EvSel": 65,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "iMC.PREEMPTION": {
+          "Box": "iMC",
+          "Category": "iMC PREEMPTION Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.",
+          "Desc": "Read Preemption Count",
+          "EvSel": 8,
+          "ExtSel": "",
+     },
+     "iMC.PREEMPTION.RD_PREEMPT_WR": {
+          "Box": "iMC",
+          "Category": "iMC PREEMPTION Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.",
+          "Desc": "Read Preemption Count",
+          "EvSel": 8,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "iMC.PREEMPTION.RD_PREEMPT_RD": {
+          "Box": "iMC",
+          "Category": "iMC PREEMPTION Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.",
+          "Desc": "Read Preemption Count",
+          "EvSel": 8,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "iMC.PRE_COUNT": {
+          "Box": "iMC",
+          "Category": "iMC PRE Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of DRAM Precharge commands sent on this channel.",
+          "Desc": "DRAM Precharge commands.",
+          "EvSel": 2,
+          "ExtSel": "",
+     },
+     "iMC.PRE_COUNT.PAGE_MISS": {
+          "Box": "iMC",
+          "Category": "iMC PRE Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of DRAM Precharge commands sent on this channel.",
+          "Desc": "DRAM Precharge commands.",
+          "EvSel": 2,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "iMC.PRE_COUNT.BYP": {
+          "Box": "iMC",
+          "Category": "iMC PRE Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of DRAM Precharge commands sent on this channel.",
+          "Desc": "DRAM Precharge commands.",
+          "EvSel": 2,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "iMC.PRE_COUNT.WR": {
+          "Box": "iMC",
+          "Category": "iMC PRE Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of DRAM Precharge commands sent on this channel.",
+          "Desc": "DRAM Precharge commands.",
+          "EvSel": 2,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "iMC.PRE_COUNT.PAGE_CLOSE": {
+          "Box": "iMC",
+          "Category": "iMC PRE Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of DRAM Precharge commands sent on this channel.",
+          "Desc": "DRAM Precharge commands.",
+          "EvSel": 2,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "iMC.PRE_COUNT.RD": {
+          "Box": "iMC",
+          "Category": "iMC PRE Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of DRAM Precharge commands sent on this channel.",
+          "Desc": "DRAM Precharge commands.",
+          "EvSel": 2,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "iMC.RD_CAS_PRIO": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "EvSel": 160,
+          "ExtSel": "",
+     },
+     "iMC.RD_CAS_PRIO.LOW": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "EvSel": 160,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "iMC.RD_CAS_PRIO.PANIC": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "EvSel": 160,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "iMC.RD_CAS_PRIO.HIGH": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "EvSel": 160,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "iMC.RD_CAS_PRIO.MED": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "EvSel": 160,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "iMC.RD_CAS_RANK0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 0",
+          "EvSel": 176,
+          "ExtSel": "",
+     },
+     "iMC.RD_CAS_RANK0.BANK5": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 0",
+          "EvSel": 176,
+          "ExtSel": "",
+          "Umask": "b00000101",
+     },
+     "iMC.RD_CAS_RANK0.BANK15": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 0",
+          "EvSel": 176,
+          "ExtSel": "",
+          "Umask": "b00001111",
+     },
+     "iMC.RD_CAS_RANK0.BANK9": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 0",
+          "EvSel": 176,
+          "ExtSel": "",
+          "Umask": "b00001001",
+     },
+     "iMC.RD_CAS_RANK0.BANK1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 0",
+          "EvSel": 176,
+          "ExtSel": "",
+          "Umask": "b00000001",
+     },
+     "iMC.RD_CAS_RANK0.BANKG2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 0",
+          "EvSel": 176,
+          "ExtSel": "",
+          "Umask": "b00010011",
+     },
+     "iMC.RD_CAS_RANK0.BANK13": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 0",
+          "EvSel": 176,
+          "ExtSel": "",
+          "Umask": "b00001101",
+     },
+     "iMC.RD_CAS_RANK0.BANK8": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 0",
+          "EvSel": 176,
+          "ExtSel": "",
+          "Umask": "b00001000",
+     },
+     "iMC.RD_CAS_RANK0.BANK7": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 0",
+          "EvSel": 176,
+          "ExtSel": "",
+          "Umask": "b00000111",
+     },
+     "iMC.RD_CAS_RANK0.BANK4": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 0",
+          "EvSel": 176,
+          "ExtSel": "",
+          "Umask": "b00000100",
+     },
+     "iMC.RD_CAS_RANK0.BANKG3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 0",
+          "EvSel": 176,
+          "ExtSel": "",
+          "Umask": "b00010100",
+     },
+     "iMC.RD_CAS_RANK0.BANK2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 0",
+          "EvSel": 176,
+          "ExtSel": "",
+          "Umask": "b00000010",
+     },
+     "iMC.RD_CAS_RANK0.BANKG0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 0",
+          "EvSel": 176,
+          "ExtSel": "",
+          "Umask": "b00010001",
+     },
+     "iMC.RD_CAS_RANK0.ALLBANKS": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 0",
+          "EvSel": 176,
+          "ExtSel": "",
+          "Umask": "b00010000",
+     },
+     "iMC.RD_CAS_RANK0.BANK11": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 0",
+          "EvSel": 176,
+          "ExtSel": "",
+          "Umask": "b00001011",
+     },
+     "iMC.RD_CAS_RANK0.BANK0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 0",
+          "EvSel": 176,
+          "ExtSel": "",
+          "Umask": "b00000000",
+     },
+     "iMC.RD_CAS_RANK0.BANK6": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 0",
+          "EvSel": 176,
+          "ExtSel": "",
+          "Umask": "b00000110",
+     },
+     "iMC.RD_CAS_RANK0.BANKG1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 0",
+          "EvSel": 176,
+          "ExtSel": "",
+          "Umask": "b00010010",
+     },
+     "iMC.RD_CAS_RANK0.BANK10": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 0",
+          "EvSel": 176,
+          "ExtSel": "",
+          "Umask": "b00001010",
+     },
+     "iMC.RD_CAS_RANK0.BANK3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 0",
+          "EvSel": 176,
+          "ExtSel": "",
+          "Umask": "b00000011",
+     },
+     "iMC.RD_CAS_RANK0.BANK12": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 0",
+          "EvSel": 176,
+          "ExtSel": "",
+          "Umask": "b00001100",
+     },
+     "iMC.RD_CAS_RANK0.BANK14": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 0",
+          "EvSel": 176,
+          "ExtSel": "",
+          "Umask": "b00001110",
+     },
+     "iMC.RD_CAS_RANK1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 1",
+          "EvSel": 177,
+          "ExtSel": "",
+     },
+     "iMC.RD_CAS_RANK1.BANK9": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 1",
+          "EvSel": 177,
+          "ExtSel": "",
+          "Umask": "b00001001",
+     },
+     "iMC.RD_CAS_RANK1.BANK15": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 1",
+          "EvSel": 177,
+          "ExtSel": "",
+          "Umask": "b00001111",
+     },
+     "iMC.RD_CAS_RANK1.BANK5": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 1",
+          "EvSel": 177,
+          "ExtSel": "",
+          "Umask": "b00000101",
+     },
+     "iMC.RD_CAS_RANK1.BANKG2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 1",
+          "EvSel": 177,
+          "ExtSel": "",
+          "Umask": "b00010011",
+     },
+     "iMC.RD_CAS_RANK1.BANK1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 1",
+          "EvSel": 177,
+          "ExtSel": "",
+          "Umask": "b00000001",
+     },
+     "iMC.RD_CAS_RANK1.BANK13": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 1",
+          "EvSel": 177,
+          "ExtSel": "",
+          "Umask": "b00001101",
+     },
+     "iMC.RD_CAS_RANK1.BANK4": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 1",
+          "EvSel": 177,
+          "ExtSel": "",
+          "Umask": "b00000100",
+     },
+     "iMC.RD_CAS_RANK1.BANK8": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 1",
+          "EvSel": 177,
+          "ExtSel": "",
+          "Umask": "b00001000",
+     },
+     "iMC.RD_CAS_RANK1.BANK7": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 1",
+          "EvSel": 177,
+          "ExtSel": "",
+          "Umask": "b00000111",
+     },
+     "iMC.RD_CAS_RANK1.BANKG3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 1",
+          "EvSel": 177,
+          "ExtSel": "",
+          "Umask": "b00010100",
+     },
+     "iMC.RD_CAS_RANK1.BANKG0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 1",
+          "EvSel": 177,
+          "ExtSel": "",
+          "Umask": "b00010001",
+     },
+     "iMC.RD_CAS_RANK1.BANK2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 1",
+          "EvSel": 177,
+          "ExtSel": "",
+          "Umask": "b00000010",
+     },
+     "iMC.RD_CAS_RANK1.BANK11": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 1",
+          "EvSel": 177,
+          "ExtSel": "",
+          "Umask": "b00001011",
+     },
+     "iMC.RD_CAS_RANK1.BANK0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 1",
+          "EvSel": 177,
+          "ExtSel": "",
+          "Umask": "b00000000",
+     },
+     "iMC.RD_CAS_RANK1.ALLBANKS": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 1",
+          "EvSel": 177,
+          "ExtSel": "",
+          "Umask": "b00010000",
+     },
+     "iMC.RD_CAS_RANK1.BANKG1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 1",
+          "EvSel": 177,
+          "ExtSel": "",
+          "Umask": "b00010010",
+     },
+     "iMC.RD_CAS_RANK1.BANK10": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 1",
+          "EvSel": 177,
+          "ExtSel": "",
+          "Umask": "b00001010",
+     },
+     "iMC.RD_CAS_RANK1.BANK6": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 1",
+          "EvSel": 177,
+          "ExtSel": "",
+          "Umask": "b00000110",
+     },
+     "iMC.RD_CAS_RANK1.BANK3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 1",
+          "EvSel": 177,
+          "ExtSel": "",
+          "Umask": "b00000011",
+     },
+     "iMC.RD_CAS_RANK1.BANK14": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 1",
+          "EvSel": 177,
+          "ExtSel": "",
+          "Umask": "b00001110",
+     },
+     "iMC.RD_CAS_RANK1.BANK12": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 1",
+          "EvSel": 177,
+          "ExtSel": "",
+          "Umask": "b00001100",
+     },
+     "iMC.RD_CAS_RANK2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 2",
+          "EvSel": 178,
+          "ExtSel": "",
+     },
+     "iMC.RD_CAS_RANK2.BANK0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 2",
+          "EvSel": 178,
+          "ExtSel": "",
+          "Umask": "b00000000",
+     },
+     "iMC.RD_CAS_RANK4": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 4",
+          "EvSel": 180,
+          "ExtSel": "",
+     },
+     "iMC.RD_CAS_RANK4.BANK1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 4",
+          "EvSel": 180,
+          "ExtSel": "",
+          "Umask": "b00000001",
+     },
+     "iMC.RD_CAS_RANK4.BANKG2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 4",
+          "EvSel": 180,
+          "ExtSel": "",
+          "Umask": "b00010011",
+     },
+     "iMC.RD_CAS_RANK4.BANK5": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 4",
+          "EvSel": 180,
+          "ExtSel": "",
+          "Umask": "b00000101",
+     },
+     "iMC.RD_CAS_RANK4.BANK15": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 4",
+          "EvSel": 180,
+          "ExtSel": "",
+          "Umask": "b00001111",
+     },
+     "iMC.RD_CAS_RANK4.BANK9": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 4",
+          "EvSel": 180,
+          "ExtSel": "",
+          "Umask": "b00001001",
+     },
+     "iMC.RD_CAS_RANK4.BANK7": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 4",
+          "EvSel": 180,
+          "ExtSel": "",
+          "Umask": "b00000111",
+     },
+     "iMC.RD_CAS_RANK4.BANK4": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 4",
+          "EvSel": 180,
+          "ExtSel": "",
+          "Umask": "b00000100",
+     },
+     "iMC.RD_CAS_RANK4.BANK8": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 4",
+          "EvSel": 180,
+          "ExtSel": "",
+          "Umask": "b00001000",
+     },
+     "iMC.RD_CAS_RANK4.BANK13": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 4",
+          "EvSel": 180,
+          "ExtSel": "",
+          "Umask": "b00001101",
+     },
+     "iMC.RD_CAS_RANK4.BANKG3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 4",
+          "EvSel": 180,
+          "ExtSel": "",
+          "Umask": "b00010100",
+     },
+     "iMC.RD_CAS_RANK4.BANKG0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 4",
+          "EvSel": 180,
+          "ExtSel": "",
+          "Umask": "b00010001",
+     },
+     "iMC.RD_CAS_RANK4.BANK2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 4",
+          "EvSel": 180,
+          "ExtSel": "",
+          "Umask": "b00000010",
+     },
+     "iMC.RD_CAS_RANK4.BANK6": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 4",
+          "EvSel": 180,
+          "ExtSel": "",
+          "Umask": "b00000110",
+     },
+     "iMC.RD_CAS_RANK4.BANKG1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 4",
+          "EvSel": 180,
+          "ExtSel": "",
+          "Umask": "b00010010",
+     },
+     "iMC.RD_CAS_RANK4.BANK10": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 4",
+          "EvSel": 180,
+          "ExtSel": "",
+          "Umask": "b00001010",
+     },
+     "iMC.RD_CAS_RANK4.ALLBANKS": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 4",
+          "EvSel": 180,
+          "ExtSel": "",
+          "Umask": "b00010000",
+     },
+     "iMC.RD_CAS_RANK4.BANK11": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 4",
+          "EvSel": 180,
+          "ExtSel": "",
+          "Umask": "b00001011",
+     },
+     "iMC.RD_CAS_RANK4.BANK0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 4",
+          "EvSel": 180,
+          "ExtSel": "",
+          "Umask": "b00000000",
+     },
+     "iMC.RD_CAS_RANK4.BANK3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 4",
+          "EvSel": 180,
+          "ExtSel": "",
+          "Umask": "b00000011",
+     },
+     "iMC.RD_CAS_RANK4.BANK12": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 4",
+          "EvSel": 180,
+          "ExtSel": "",
+          "Umask": "b00001100",
+     },
+     "iMC.RD_CAS_RANK4.BANK14": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 4",
+          "EvSel": 180,
+          "ExtSel": "",
+          "Umask": "b00001110",
+     },
+     "iMC.RD_CAS_RANK5": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 5",
+          "EvSel": 181,
+          "ExtSel": "",
+     },
+     "iMC.RD_CAS_RANK5.BANK13": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 5",
+          "EvSel": 181,
+          "ExtSel": "",
+          "Umask": "b00001101",
+     },
+     "iMC.RD_CAS_RANK5.BANK8": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 5",
+          "EvSel": 181,
+          "ExtSel": "",
+          "Umask": "b00001000",
+     },
+     "iMC.RD_CAS_RANK5.BANK7": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 5",
+          "EvSel": 181,
+          "ExtSel": "",
+          "Umask": "b00000111",
+     },
+     "iMC.RD_CAS_RANK5.BANK4": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 5",
+          "EvSel": 181,
+          "ExtSel": "",
+          "Umask": "b00000100",
+     },
+     "iMC.RD_CAS_RANK5.BANK15": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 5",
+          "EvSel": 181,
+          "ExtSel": "",
+          "Umask": "b00001111",
+     },
+     "iMC.RD_CAS_RANK5.BANK9": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 5",
+          "EvSel": 181,
+          "ExtSel": "",
+          "Umask": "b00001001",
+     },
+     "iMC.RD_CAS_RANK5.BANK5": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 5",
+          "EvSel": 181,
+          "ExtSel": "",
+          "Umask": "b00000101",
+     },
+     "iMC.RD_CAS_RANK5.BANKG2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 5",
+          "EvSel": 181,
+          "ExtSel": "",
+          "Umask": "b00010011",
+     },
+     "iMC.RD_CAS_RANK5.BANK1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 5",
+          "EvSel": 181,
+          "ExtSel": "",
+          "Umask": "b00000001",
+     },
+     "iMC.RD_CAS_RANK5.BANKG0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 5",
+          "EvSel": 181,
+          "ExtSel": "",
+          "Umask": "b00010001",
+     },
+     "iMC.RD_CAS_RANK5.BANK2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 5",
+          "EvSel": 181,
+          "ExtSel": "",
+          "Umask": "b00000010",
+     },
+     "iMC.RD_CAS_RANK5.BANKG3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 5",
+          "EvSel": 181,
+          "ExtSel": "",
+          "Umask": "b00010100",
+     },
+     "iMC.RD_CAS_RANK5.BANK11": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 5",
+          "EvSel": 181,
+          "ExtSel": "",
+          "Umask": "b00001011",
+     },
+     "iMC.RD_CAS_RANK5.BANK0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 5",
+          "EvSel": 181,
+          "ExtSel": "",
+          "Umask": "b00000000",
+     },
+     "iMC.RD_CAS_RANK5.ALLBANKS": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 5",
+          "EvSel": 181,
+          "ExtSel": "",
+          "Umask": "b00010000",
+     },
+     "iMC.RD_CAS_RANK5.BANK10": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 5",
+          "EvSel": 181,
+          "ExtSel": "",
+          "Umask": "b00001010",
+     },
+     "iMC.RD_CAS_RANK5.BANKG1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 5",
+          "EvSel": 181,
+          "ExtSel": "",
+          "Umask": "b00010010",
+     },
+     "iMC.RD_CAS_RANK5.BANK6": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 5",
+          "EvSel": 181,
+          "ExtSel": "",
+          "Umask": "b00000110",
+     },
+     "iMC.RD_CAS_RANK5.BANK14": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 5",
+          "EvSel": 181,
+          "ExtSel": "",
+          "Umask": "b00001110",
+     },
+     "iMC.RD_CAS_RANK5.BANK12": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 5",
+          "EvSel": 181,
+          "ExtSel": "",
+          "Umask": "b00001100",
+     },
+     "iMC.RD_CAS_RANK5.BANK3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 5",
+          "EvSel": 181,
+          "ExtSel": "",
+          "Umask": "b00000011",
+     },
+     "iMC.RD_CAS_RANK6": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 6",
+          "EvSel": 182,
+          "ExtSel": "",
+     },
+     "iMC.RD_CAS_RANK6.BANKG3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 6",
+          "EvSel": 182,
+          "ExtSel": "",
+          "Umask": "b00010100",
+     },
+     "iMC.RD_CAS_RANK6.BANKG0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 6",
+          "EvSel": 182,
+          "ExtSel": "",
+          "Umask": "b00010001",
+     },
+     "iMC.RD_CAS_RANK6.BANK2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 6",
+          "EvSel": 182,
+          "ExtSel": "",
+          "Umask": "b00000010",
+     },
+     "iMC.RD_CAS_RANK6.BANKG2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 6",
+          "EvSel": 182,
+          "ExtSel": "",
+          "Umask": "b00010011",
+     },
+     "iMC.RD_CAS_RANK6.BANK1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 6",
+          "EvSel": 182,
+          "ExtSel": "",
+          "Umask": "b00000001",
+     },
+     "iMC.RD_CAS_RANK6.BANK9": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 6",
+          "EvSel": 182,
+          "ExtSel": "",
+          "Umask": "b00001001",
+     },
+     "iMC.RD_CAS_RANK6.BANK15": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 6",
+          "EvSel": 182,
+          "ExtSel": "",
+          "Umask": "b00001111",
+     },
+     "iMC.RD_CAS_RANK6.BANK5": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 6",
+          "EvSel": 182,
+          "ExtSel": "",
+          "Umask": "b00000101",
+     },
+     "iMC.RD_CAS_RANK6.BANK7": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 6",
+          "EvSel": 182,
+          "ExtSel": "",
+          "Umask": "b00000111",
+     },
+     "iMC.RD_CAS_RANK6.BANK4": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 6",
+          "EvSel": 182,
+          "ExtSel": "",
+          "Umask": "b00000100",
+     },
+     "iMC.RD_CAS_RANK6.BANK8": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 6",
+          "EvSel": 182,
+          "ExtSel": "",
+          "Umask": "b00001000",
+     },
+     "iMC.RD_CAS_RANK6.BANK13": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 6",
+          "EvSel": 182,
+          "ExtSel": "",
+          "Umask": "b00001101",
+     },
+     "iMC.RD_CAS_RANK6.BANK3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 6",
+          "EvSel": 182,
+          "ExtSel": "",
+          "Umask": "b00000011",
+     },
+     "iMC.RD_CAS_RANK6.BANK14": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 6",
+          "EvSel": 182,
+          "ExtSel": "",
+          "Umask": "b00001110",
+     },
+     "iMC.RD_CAS_RANK6.BANK12": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 6",
+          "EvSel": 182,
+          "ExtSel": "",
+          "Umask": "b00001100",
+     },
+     "iMC.RD_CAS_RANK6.BANKG1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 6",
+          "EvSel": 182,
+          "ExtSel": "",
+          "Umask": "b00010010",
+     },
+     "iMC.RD_CAS_RANK6.BANK10": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 6",
+          "EvSel": 182,
+          "ExtSel": "",
+          "Umask": "b00001010",
+     },
+     "iMC.RD_CAS_RANK6.BANK6": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 6",
+          "EvSel": 182,
+          "ExtSel": "",
+          "Umask": "b00000110",
+     },
+     "iMC.RD_CAS_RANK6.BANK11": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 6",
+          "EvSel": 182,
+          "ExtSel": "",
+          "Umask": "b00001011",
+     },
+     "iMC.RD_CAS_RANK6.BANK0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 6",
+          "EvSel": 182,
+          "ExtSel": "",
+          "Umask": "b00000000",
+     },
+     "iMC.RD_CAS_RANK6.ALLBANKS": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 6",
+          "EvSel": 182,
+          "ExtSel": "",
+          "Umask": "b00010000",
+     },
+     "iMC.RD_CAS_RANK7": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 7",
+          "EvSel": 183,
+          "ExtSel": "",
+     },
+     "iMC.RD_CAS_RANK7.BANKG0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 7",
+          "EvSel": 183,
+          "ExtSel": "",
+          "Umask": "b00010001",
+     },
+     "iMC.RD_CAS_RANK7.BANK2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 7",
+          "EvSel": 183,
+          "ExtSel": "",
+          "Umask": "b00000010",
+     },
+     "iMC.RD_CAS_RANK7.BANKG3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 7",
+          "EvSel": 183,
+          "ExtSel": "",
+          "Umask": "b00010100",
+     },
+     "iMC.RD_CAS_RANK7.BANK4": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 7",
+          "EvSel": 183,
+          "ExtSel": "",
+          "Umask": "b00000100",
+     },
+     "iMC.RD_CAS_RANK7.BANK8": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 7",
+          "EvSel": 183,
+          "ExtSel": "",
+          "Umask": "b00001000",
+     },
+     "iMC.RD_CAS_RANK7.BANK7": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 7",
+          "EvSel": 183,
+          "ExtSel": "",
+          "Umask": "b00000111",
+     },
+     "iMC.RD_CAS_RANK7.BANK13": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 7",
+          "EvSel": 183,
+          "ExtSel": "",
+          "Umask": "b00001101",
+     },
+     "iMC.RD_CAS_RANK7.BANK1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 7",
+          "EvSel": 183,
+          "ExtSel": "",
+          "Umask": "b00000001",
+     },
+     "iMC.RD_CAS_RANK7.BANKG2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 7",
+          "EvSel": 183,
+          "ExtSel": "",
+          "Umask": "b00010011",
+     },
+     "iMC.RD_CAS_RANK7.BANK5": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 7",
+          "EvSel": 183,
+          "ExtSel": "",
+          "Umask": "b00000101",
+     },
+     "iMC.RD_CAS_RANK7.BANK9": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 7",
+          "EvSel": 183,
+          "ExtSel": "",
+          "Umask": "b00001001",
+     },
+     "iMC.RD_CAS_RANK7.BANK15": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 7",
+          "EvSel": 183,
+          "ExtSel": "",
+          "Umask": "b00001111",
+     },
+     "iMC.RD_CAS_RANK7.BANK12": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 7",
+          "EvSel": 183,
+          "ExtSel": "",
+          "Umask": "b00001100",
+     },
+     "iMC.RD_CAS_RANK7.BANK14": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 7",
+          "EvSel": 183,
+          "ExtSel": "",
+          "Umask": "b00001110",
+     },
+     "iMC.RD_CAS_RANK7.BANK3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 7",
+          "EvSel": 183,
+          "ExtSel": "",
+          "Umask": "b00000011",
+     },
+     "iMC.RD_CAS_RANK7.BANK6": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 7",
+          "EvSel": 183,
+          "ExtSel": "",
+          "Umask": "b00000110",
+     },
+     "iMC.RD_CAS_RANK7.BANK10": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 7",
+          "EvSel": 183,
+          "ExtSel": "",
+          "Umask": "b00001010",
+     },
+     "iMC.RD_CAS_RANK7.BANKG1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 7",
+          "EvSel": 183,
+          "ExtSel": "",
+          "Umask": "b00010010",
+     },
+     "iMC.RD_CAS_RANK7.ALLBANKS": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 7",
+          "EvSel": 183,
+          "ExtSel": "",
+          "Umask": "b00010000",
+     },
+     "iMC.RD_CAS_RANK7.BANK0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 7",
+          "EvSel": 183,
+          "ExtSel": "",
+          "Umask": "b00000000",
+     },
+     "iMC.RD_CAS_RANK7.BANK11": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "RD_CAS Access to Rank 7",
+          "EvSel": 183,
+          "ExtSel": "",
+          "Umask": "b00001011",
+     },
+     "iMC.RPQ_CYCLES_NE": {
+          "Box": "iMC",
+          "Category": "iMC RPQ Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the Read Pending Queue is not empty.  This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
+          "Desc": "Read Pending Queue Not Empty",
+          "EvSel": 17,
+          "ExtSel": "",
+     },
+     "iMC.RPQ_INSERTS": {
+          "Box": "iMC",
+          "Category": "iMC RPQ Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests.",
+          "Desc": "Read Pending Queue Allocations",
+          "EvSel": 16,
+          "ExtSel": "",
+     },
+     "iMC.VMSE_MXB_WR_OCCUPANCY": {
+          "Box": "iMC",
+          "Category": "iMC VMSE Events",
+          "Counters": "0-3",
+          "Desc": "VMSE MXB write buffer occupancy",
+          "EvSel": 145,
+          "ExtSel": "",
+          "MaxIncCyc": 32,
+          "SubCtr": 1,
+     },
+     "iMC.VMSE_WR_PUSH": {
+          "Box": "iMC",
+          "Category": "iMC VMSE Events",
+          "Counters": "0-3",
+          "Desc": "VMSE WR PUSH issued",
+          "EvSel": 144,
+          "ExtSel": "",
+     },
+     "iMC.VMSE_WR_PUSH.WMM": {
+          "Box": "iMC",
+          "Category": "iMC VMSE Events",
+          "Counters": "0-3",
+          "Desc": "VMSE WR PUSH issued",
+          "EvSel": 144,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "iMC.VMSE_WR_PUSH.RMM": {
+          "Box": "iMC",
+          "Category": "iMC VMSE Events",
+          "Counters": "0-3",
+          "Desc": "VMSE WR PUSH issued",
+          "EvSel": 144,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "iMC.WMM_TO_RMM": {
+          "Box": "iMC",
+          "Category": "iMC MAJOR_MODES Events",
+          "Counters": "0-3",
+          "Desc": "Transition from WMM to RMM because of low threshold",
+          "EvSel": 192,
+          "ExtSel": "",
+     },
+     "iMC.WMM_TO_RMM.LOW_THRESH": {
+          "Box": "iMC",
+          "Category": "iMC MAJOR_MODES Events",
+          "Counters": "0-3",
+          "Desc": "Transition from WMM to RMM because of low threshold",
+          "EvSel": 192,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "iMC.WMM_TO_RMM.VMSE_RETRY": {
+          "Box": "iMC",
+          "Category": "iMC MAJOR_MODES Events",
+          "Counters": "0-3",
+          "Desc": "Transition from WMM to RMM because of low threshold",
+          "EvSel": 192,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "iMC.WMM_TO_RMM.STARVE": {
+          "Box": "iMC",
+          "Category": "iMC MAJOR_MODES Events",
+          "Counters": "0-3",
+          "Desc": "Transition from WMM to RMM because of low threshold",
+          "EvSel": 192,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "iMC.WPQ_CYCLES_FULL": {
+          "Box": "iMC",
+          "Category": "iMC WPQ Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
+          "Desc": "Write Pending Queue Full Cycles",
+          "EvSel": 34,
+          "ExtSel": "",
+     },
+     "iMC.WPQ_CYCLES_NE": {
+          "Box": "iMC",
+          "Category": "iMC WPQ Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have \"posted\" to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
+          "Desc": "Write Pending Queue Not Empty",
+          "EvSel": 33,
+          "ExtSel": "",
+     },
+     "iMC.WPQ_READ_HIT": {
+          "Box": "iMC",
+          "Category": "iMC WPQ Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+          "Desc": "Write Pending Queue CAM Match",
+          "EvSel": 35,
+          "ExtSel": "",
+     },
+     "iMC.WPQ_WRITE_HIT": {
+          "Box": "iMC",
+          "Category": "iMC WPQ Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+          "Desc": "Write Pending Queue CAM Match",
+          "EvSel": 36,
+          "ExtSel": "",
+     },
+     "iMC.WRONG_MM": {
+          "Box": "iMC",
+          "Category": "iMC MAJOR_MODES Events",
+          "Counters": "0-3",
+          "Desc": "Not getting the requested Major Mode",
+          "EvSel": 193,
+          "ExtSel": "",
+     },
+     "iMC.WR_CAS_RANK0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 0",
+          "EvSel": 184,
+          "ExtSel": "",
+     },
+     "iMC.WR_CAS_RANK0.BANK3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 0",
+          "EvSel": 184,
+          "ExtSel": "",
+          "Umask": "b00000011",
+     },
+     "iMC.WR_CAS_RANK0.BANK12": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 0",
+          "EvSel": 184,
+          "ExtSel": "",
+          "Umask": "b00001100",
+     },
+     "iMC.WR_CAS_RANK0.BANK14": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 0",
+          "EvSel": 184,
+          "ExtSel": "",
+          "Umask": "b00001110",
+     },
+     "iMC.WR_CAS_RANK0.BANK6": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 0",
+          "EvSel": 184,
+          "ExtSel": "",
+          "Umask": "b00000110",
+     },
+     "iMC.WR_CAS_RANK0.BANK10": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 0",
+          "EvSel": 184,
+          "ExtSel": "",
+          "Umask": "b00001010",
+     },
+     "iMC.WR_CAS_RANK0.BANKG1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 0",
+          "EvSel": 184,
+          "ExtSel": "",
+          "Umask": "b00010010",
+     },
+     "iMC.WR_CAS_RANK0.ALLBANKS": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 0",
+          "EvSel": 184,
+          "ExtSel": "",
+          "Umask": "b00010000",
+     },
+     "iMC.WR_CAS_RANK0.BANK11": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 0",
+          "EvSel": 184,
+          "ExtSel": "",
+          "Umask": "b00001011",
+     },
+     "iMC.WR_CAS_RANK0.BANK0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 0",
+          "EvSel": 184,
+          "ExtSel": "",
+          "Umask": "b00000000",
+     },
+     "iMC.WR_CAS_RANK0.BANKG3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 0",
+          "EvSel": 184,
+          "ExtSel": "",
+          "Umask": "b00010100",
+     },
+     "iMC.WR_CAS_RANK0.BANK2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 0",
+          "EvSel": 184,
+          "ExtSel": "",
+          "Umask": "b00000010",
+     },
+     "iMC.WR_CAS_RANK0.BANKG0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 0",
+          "EvSel": 184,
+          "ExtSel": "",
+          "Umask": "b00010001",
+     },
+     "iMC.WR_CAS_RANK0.BANK1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 0",
+          "EvSel": 184,
+          "ExtSel": "",
+          "Umask": "b00000001",
+     },
+     "iMC.WR_CAS_RANK0.BANKG2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 0",
+          "EvSel": 184,
+          "ExtSel": "",
+          "Umask": "b00010011",
+     },
+     "iMC.WR_CAS_RANK0.BANK5": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 0",
+          "EvSel": 184,
+          "ExtSel": "",
+          "Umask": "b00000101",
+     },
+     "iMC.WR_CAS_RANK0.BANK15": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 0",
+          "EvSel": 184,
+          "ExtSel": "",
+          "Umask": "b00001111",
+     },
+     "iMC.WR_CAS_RANK0.BANK9": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 0",
+          "EvSel": 184,
+          "ExtSel": "",
+          "Umask": "b00001001",
+     },
+     "iMC.WR_CAS_RANK0.BANK8": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 0",
+          "EvSel": 184,
+          "ExtSel": "",
+          "Umask": "b00001000",
+     },
+     "iMC.WR_CAS_RANK0.BANK4": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 0",
+          "EvSel": 184,
+          "ExtSel": "",
+          "Umask": "b00000100",
+     },
+     "iMC.WR_CAS_RANK0.BANK7": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 0",
+          "EvSel": 184,
+          "ExtSel": "",
+          "Umask": "b00000111",
+     },
+     "iMC.WR_CAS_RANK0.BANK13": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 0",
+          "EvSel": 184,
+          "ExtSel": "",
+          "Umask": "b00001101",
+     },
+     "iMC.WR_CAS_RANK1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 1",
+          "EvSel": 185,
+          "ExtSel": "",
+     },
+     "iMC.WR_CAS_RANK1.BANK1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 1",
+          "EvSel": 185,
+          "ExtSel": "",
+          "Umask": "b00000001",
+     },
+     "iMC.WR_CAS_RANK1.BANKG2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 1",
+          "EvSel": 185,
+          "ExtSel": "",
+          "Umask": "b00010011",
+     },
+     "iMC.WR_CAS_RANK1.BANK5": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 1",
+          "EvSel": 185,
+          "ExtSel": "",
+          "Umask": "b00000101",
+     },
+     "iMC.WR_CAS_RANK1.BANK15": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 1",
+          "EvSel": 185,
+          "ExtSel": "",
+          "Umask": "b00001111",
+     },
+     "iMC.WR_CAS_RANK1.BANK9": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 1",
+          "EvSel": 185,
+          "ExtSel": "",
+          "Umask": "b00001001",
+     },
+     "iMC.WR_CAS_RANK1.BANK4": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 1",
+          "EvSel": 185,
+          "ExtSel": "",
+          "Umask": "b00000100",
+     },
+     "iMC.WR_CAS_RANK1.BANK8": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 1",
+          "EvSel": 185,
+          "ExtSel": "",
+          "Umask": "b00001000",
+     },
+     "iMC.WR_CAS_RANK1.BANK7": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 1",
+          "EvSel": 185,
+          "ExtSel": "",
+          "Umask": "b00000111",
+     },
+     "iMC.WR_CAS_RANK1.BANK13": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 1",
+          "EvSel": 185,
+          "ExtSel": "",
+          "Umask": "b00001101",
+     },
+     "iMC.WR_CAS_RANK1.BANKG3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 1",
+          "EvSel": 185,
+          "ExtSel": "",
+          "Umask": "b00010100",
+     },
+     "iMC.WR_CAS_RANK1.BANK2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 1",
+          "EvSel": 185,
+          "ExtSel": "",
+          "Umask": "b00000010",
+     },
+     "iMC.WR_CAS_RANK1.BANKG0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 1",
+          "EvSel": 185,
+          "ExtSel": "",
+          "Umask": "b00010001",
+     },
+     "iMC.WR_CAS_RANK1.BANK6": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 1",
+          "EvSel": 185,
+          "ExtSel": "",
+          "Umask": "b00000110",
+     },
+     "iMC.WR_CAS_RANK1.BANK10": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 1",
+          "EvSel": 185,
+          "ExtSel": "",
+          "Umask": "b00001010",
+     },
+     "iMC.WR_CAS_RANK1.BANKG1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 1",
+          "EvSel": 185,
+          "ExtSel": "",
+          "Umask": "b00010010",
+     },
+     "iMC.WR_CAS_RANK1.ALLBANKS": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 1",
+          "EvSel": 185,
+          "ExtSel": "",
+          "Umask": "b00010000",
+     },
+     "iMC.WR_CAS_RANK1.BANK0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 1",
+          "EvSel": 185,
+          "ExtSel": "",
+          "Umask": "b00000000",
+     },
+     "iMC.WR_CAS_RANK1.BANK11": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 1",
+          "EvSel": 185,
+          "ExtSel": "",
+          "Umask": "b00001011",
+     },
+     "iMC.WR_CAS_RANK1.BANK3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 1",
+          "EvSel": 185,
+          "ExtSel": "",
+          "Umask": "b00000011",
+     },
+     "iMC.WR_CAS_RANK1.BANK12": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 1",
+          "EvSel": 185,
+          "ExtSel": "",
+          "Umask": "b00001100",
+     },
+     "iMC.WR_CAS_RANK1.BANK14": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 1",
+          "EvSel": 185,
+          "ExtSel": "",
+          "Umask": "b00001110",
+     },
+     "iMC.WR_CAS_RANK2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 2",
+          "EvSel": 186,
+          "ExtSel": "",
+     },
+     "iMC.WR_CAS_RANK3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 3",
+          "EvSel": 187,
+          "ExtSel": "",
+     },
+     "iMC.WR_CAS_RANK4": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 4",
+          "EvSel": 188,
+          "ExtSel": "",
+     },
+     "iMC.WR_CAS_RANK4.BANK1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 4",
+          "EvSel": 188,
+          "ExtSel": "",
+          "Umask": "b00000001",
+     },
+     "iMC.WR_CAS_RANK4.BANKG2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 4",
+          "EvSel": 188,
+          "ExtSel": "",
+          "Umask": "b00010011",
+     },
+     "iMC.WR_CAS_RANK4.BANK5": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 4",
+          "EvSel": 188,
+          "ExtSel": "",
+          "Umask": "b00000101",
+     },
+     "iMC.WR_CAS_RANK4.BANK15": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 4",
+          "EvSel": 188,
+          "ExtSel": "",
+          "Umask": "b00001111",
+     },
+     "iMC.WR_CAS_RANK4.BANK9": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 4",
+          "EvSel": 188,
+          "ExtSel": "",
+          "Umask": "b00001001",
+     },
+     "iMC.WR_CAS_RANK4.BANK4": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 4",
+          "EvSel": 188,
+          "ExtSel": "",
+          "Umask": "b00000100",
+     },
+     "iMC.WR_CAS_RANK4.BANK7": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 4",
+          "EvSel": 188,
+          "ExtSel": "",
+          "Umask": "b00000111",
+     },
+     "iMC.WR_CAS_RANK4.BANK8": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 4",
+          "EvSel": 188,
+          "ExtSel": "",
+          "Umask": "b00001000",
+     },
+     "iMC.WR_CAS_RANK4.BANK13": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 4",
+          "EvSel": 188,
+          "ExtSel": "",
+          "Umask": "b00001101",
+     },
+     "iMC.WR_CAS_RANK4.BANKG3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 4",
+          "EvSel": 188,
+          "ExtSel": "",
+          "Umask": "b00010100",
+     },
+     "iMC.WR_CAS_RANK4.BANK2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 4",
+          "EvSel": 188,
+          "ExtSel": "",
+          "Umask": "b00000010",
+     },
+     "iMC.WR_CAS_RANK4.BANKG0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 4",
+          "EvSel": 188,
+          "ExtSel": "",
+          "Umask": "b00010001",
+     },
+     "iMC.WR_CAS_RANK4.BANK6": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 4",
+          "EvSel": 188,
+          "ExtSel": "",
+          "Umask": "b00000110",
+     },
+     "iMC.WR_CAS_RANK4.BANKG1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 4",
+          "EvSel": 188,
+          "ExtSel": "",
+          "Umask": "b00010010",
+     },
+     "iMC.WR_CAS_RANK4.BANK10": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 4",
+          "EvSel": 188,
+          "ExtSel": "",
+          "Umask": "b00001010",
+     },
+     "iMC.WR_CAS_RANK4.ALLBANKS": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 4",
+          "EvSel": 188,
+          "ExtSel": "",
+          "Umask": "b00010000",
+     },
+     "iMC.WR_CAS_RANK4.BANK11": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 4",
+          "EvSel": 188,
+          "ExtSel": "",
+          "Umask": "b00001011",
+     },
+     "iMC.WR_CAS_RANK4.BANK0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 4",
+          "EvSel": 188,
+          "ExtSel": "",
+          "Umask": "b00000000",
+     },
+     "iMC.WR_CAS_RANK4.BANK3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 4",
+          "EvSel": 188,
+          "ExtSel": "",
+          "Umask": "b00000011",
+     },
+     "iMC.WR_CAS_RANK4.BANK12": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 4",
+          "EvSel": 188,
+          "ExtSel": "",
+          "Umask": "b00001100",
+     },
+     "iMC.WR_CAS_RANK4.BANK14": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 4",
+          "EvSel": 188,
+          "ExtSel": "",
+          "Umask": "b00001110",
+     },
+     "iMC.WR_CAS_RANK5": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 5",
+          "EvSel": 189,
+          "ExtSel": "",
+     },
+     "iMC.WR_CAS_RANK5.BANK10": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 5",
+          "EvSel": 189,
+          "ExtSel": "",
+          "Umask": "b00001010",
+     },
+     "iMC.WR_CAS_RANK5.BANKG1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 5",
+          "EvSel": 189,
+          "ExtSel": "",
+          "Umask": "b00010010",
+     },
+     "iMC.WR_CAS_RANK5.BANK6": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 5",
+          "EvSel": 189,
+          "ExtSel": "",
+          "Umask": "b00000110",
+     },
+     "iMC.WR_CAS_RANK5.BANK11": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 5",
+          "EvSel": 189,
+          "ExtSel": "",
+          "Umask": "b00001011",
+     },
+     "iMC.WR_CAS_RANK5.BANK0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 5",
+          "EvSel": 189,
+          "ExtSel": "",
+          "Umask": "b00000000",
+     },
+     "iMC.WR_CAS_RANK5.ALLBANKS": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 5",
+          "EvSel": 189,
+          "ExtSel": "",
+          "Umask": "b00010000",
+     },
+     "iMC.WR_CAS_RANK5.BANK14": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 5",
+          "EvSel": 189,
+          "ExtSel": "",
+          "Umask": "b00001110",
+     },
+     "iMC.WR_CAS_RANK5.BANK12": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 5",
+          "EvSel": 189,
+          "ExtSel": "",
+          "Umask": "b00001100",
+     },
+     "iMC.WR_CAS_RANK5.BANK3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 5",
+          "EvSel": 189,
+          "ExtSel": "",
+          "Umask": "b00000011",
+     },
+     "iMC.WR_CAS_RANK5.BANK8": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 5",
+          "EvSel": 189,
+          "ExtSel": "",
+          "Umask": "b00001000",
+     },
+     "iMC.WR_CAS_RANK5.BANK4": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 5",
+          "EvSel": 189,
+          "ExtSel": "",
+          "Umask": "b00000100",
+     },
+     "iMC.WR_CAS_RANK5.BANK7": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 5",
+          "EvSel": 189,
+          "ExtSel": "",
+          "Umask": "b00000111",
+     },
+     "iMC.WR_CAS_RANK5.BANK13": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 5",
+          "EvSel": 189,
+          "ExtSel": "",
+          "Umask": "b00001101",
+     },
+     "iMC.WR_CAS_RANK5.BANKG2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 5",
+          "EvSel": 189,
+          "ExtSel": "",
+          "Umask": "b00010011",
+     },
+     "iMC.WR_CAS_RANK5.BANK1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 5",
+          "EvSel": 189,
+          "ExtSel": "",
+          "Umask": "b00000001",
+     },
+     "iMC.WR_CAS_RANK5.BANK15": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 5",
+          "EvSel": 189,
+          "ExtSel": "",
+          "Umask": "b00001111",
+     },
+     "iMC.WR_CAS_RANK5.BANK9": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 5",
+          "EvSel": 189,
+          "ExtSel": "",
+          "Umask": "b00001001",
+     },
+     "iMC.WR_CAS_RANK5.BANK5": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 5",
+          "EvSel": 189,
+          "ExtSel": "",
+          "Umask": "b00000101",
+     },
+     "iMC.WR_CAS_RANK5.BANKG0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 5",
+          "EvSel": 189,
+          "ExtSel": "",
+          "Umask": "b00010001",
+     },
+     "iMC.WR_CAS_RANK5.BANK2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 5",
+          "EvSel": 189,
+          "ExtSel": "",
+          "Umask": "b00000010",
+     },
+     "iMC.WR_CAS_RANK5.BANKG3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 5",
+          "EvSel": 189,
+          "ExtSel": "",
+          "Umask": "b00010100",
+     },
+     "iMC.WR_CAS_RANK6": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 6",
+          "EvSel": 190,
+          "ExtSel": "",
+     },
+     "iMC.WR_CAS_RANK6.ALLBANKS": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 6",
+          "EvSel": 190,
+          "ExtSel": "",
+          "Umask": "b00010000",
+     },
+     "iMC.WR_CAS_RANK6.BANK11": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 6",
+          "EvSel": 190,
+          "ExtSel": "",
+          "Umask": "b00001011",
+     },
+     "iMC.WR_CAS_RANK6.BANK0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 6",
+          "EvSel": 190,
+          "ExtSel": "",
+          "Umask": "b00000000",
+     },
+     "iMC.WR_CAS_RANK6.BANK6": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 6",
+          "EvSel": 190,
+          "ExtSel": "",
+          "Umask": "b00000110",
+     },
+     "iMC.WR_CAS_RANK6.BANK10": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 6",
+          "EvSel": 190,
+          "ExtSel": "",
+          "Umask": "b00001010",
+     },
+     "iMC.WR_CAS_RANK6.BANKG1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 6",
+          "EvSel": 190,
+          "ExtSel": "",
+          "Umask": "b00010010",
+     },
+     "iMC.WR_CAS_RANK6.BANK12": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 6",
+          "EvSel": 190,
+          "ExtSel": "",
+          "Umask": "b00001100",
+     },
+     "iMC.WR_CAS_RANK6.BANK14": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 6",
+          "EvSel": 190,
+          "ExtSel": "",
+          "Umask": "b00001110",
+     },
+     "iMC.WR_CAS_RANK6.BANK3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 6",
+          "EvSel": 190,
+          "ExtSel": "",
+          "Umask": "b00000011",
+     },
+     "iMC.WR_CAS_RANK6.BANK13": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 6",
+          "EvSel": 190,
+          "ExtSel": "",
+          "Umask": "b00001101",
+     },
+     "iMC.WR_CAS_RANK6.BANK8": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 6",
+          "EvSel": 190,
+          "ExtSel": "",
+          "Umask": "b00001000",
+     },
+     "iMC.WR_CAS_RANK6.BANK4": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 6",
+          "EvSel": 190,
+          "ExtSel": "",
+          "Umask": "b00000100",
+     },
+     "iMC.WR_CAS_RANK6.BANK7": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 6",
+          "EvSel": 190,
+          "ExtSel": "",
+          "Umask": "b00000111",
+     },
+     "iMC.WR_CAS_RANK6.BANK5": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 6",
+          "EvSel": 190,
+          "ExtSel": "",
+          "Umask": "b00000101",
+     },
+     "iMC.WR_CAS_RANK6.BANK9": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 6",
+          "EvSel": 190,
+          "ExtSel": "",
+          "Umask": "b00001001",
+     },
+     "iMC.WR_CAS_RANK6.BANK15": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 6",
+          "EvSel": 190,
+          "ExtSel": "",
+          "Umask": "b00001111",
+     },
+     "iMC.WR_CAS_RANK6.BANK1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 6",
+          "EvSel": 190,
+          "ExtSel": "",
+          "Umask": "b00000001",
+     },
+     "iMC.WR_CAS_RANK6.BANKG2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 6",
+          "EvSel": 190,
+          "ExtSel": "",
+          "Umask": "b00010011",
+     },
+     "iMC.WR_CAS_RANK6.BANK2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 6",
+          "EvSel": 190,
+          "ExtSel": "",
+          "Umask": "b00000010",
+     },
+     "iMC.WR_CAS_RANK6.BANKG0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 6",
+          "EvSel": 190,
+          "ExtSel": "",
+          "Umask": "b00010001",
+     },
+     "iMC.WR_CAS_RANK6.BANKG3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 6",
+          "EvSel": 190,
+          "ExtSel": "",
+          "Umask": "b00010100",
+     },
+     "iMC.WR_CAS_RANK7": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 7",
+          "EvSel": 191,
+          "ExtSel": "",
+     },
+     "iMC.WR_CAS_RANK7.BANKG3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 7",
+          "EvSel": 191,
+          "ExtSel": "",
+          "Umask": "b00010100",
+     },
+     "iMC.WR_CAS_RANK7.BANKG0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 7",
+          "EvSel": 191,
+          "ExtSel": "",
+          "Umask": "b00010001",
+     },
+     "iMC.WR_CAS_RANK7.BANK2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 7",
+          "EvSel": 191,
+          "ExtSel": "",
+          "Umask": "b00000010",
+     },
+     "iMC.WR_CAS_RANK7.BANK5": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 7",
+          "EvSel": 191,
+          "ExtSel": "",
+          "Umask": "b00000101",
+     },
+     "iMC.WR_CAS_RANK7.BANK15": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 7",
+          "EvSel": 191,
+          "ExtSel": "",
+          "Umask": "b00001111",
+     },
+     "iMC.WR_CAS_RANK7.BANK9": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 7",
+          "EvSel": 191,
+          "ExtSel": "",
+          "Umask": "b00001001",
+     },
+     "iMC.WR_CAS_RANK7.BANK1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 7",
+          "EvSel": 191,
+          "ExtSel": "",
+          "Umask": "b00000001",
+     },
+     "iMC.WR_CAS_RANK7.BANKG2": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 7",
+          "EvSel": 191,
+          "ExtSel": "",
+          "Umask": "b00010011",
+     },
+     "iMC.WR_CAS_RANK7.BANK13": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 7",
+          "EvSel": 191,
+          "ExtSel": "",
+          "Umask": "b00001101",
+     },
+     "iMC.WR_CAS_RANK7.BANK8": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 7",
+          "EvSel": 191,
+          "ExtSel": "",
+          "Umask": "b00001000",
+     },
+     "iMC.WR_CAS_RANK7.BANK4": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 7",
+          "EvSel": 191,
+          "ExtSel": "",
+          "Umask": "b00000100",
+     },
+     "iMC.WR_CAS_RANK7.BANK7": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 7",
+          "EvSel": 191,
+          "ExtSel": "",
+          "Umask": "b00000111",
+     },
+     "iMC.WR_CAS_RANK7.BANK3": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 7",
+          "EvSel": 191,
+          "ExtSel": "",
+          "Umask": "b00000011",
+     },
+     "iMC.WR_CAS_RANK7.BANK12": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 7",
+          "EvSel": 191,
+          "ExtSel": "",
+          "Umask": "b00001100",
+     },
+     "iMC.WR_CAS_RANK7.BANK14": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 7",
+          "EvSel": 191,
+          "ExtSel": "",
+          "Umask": "b00001110",
+     },
+     "iMC.WR_CAS_RANK7.ALLBANKS": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 7",
+          "EvSel": 191,
+          "ExtSel": "",
+          "Umask": "b00010000",
+     },
+     "iMC.WR_CAS_RANK7.BANK11": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 7",
+          "EvSel": 191,
+          "ExtSel": "",
+          "Umask": "b00001011",
+     },
+     "iMC.WR_CAS_RANK7.BANK0": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 7",
+          "EvSel": 191,
+          "ExtSel": "",
+          "Umask": "b00000000",
+     },
+     "iMC.WR_CAS_RANK7.BANK6": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 7",
+          "EvSel": 191,
+          "ExtSel": "",
+          "Umask": "b00000110",
+     },
+     "iMC.WR_CAS_RANK7.BANKG1": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 7",
+          "EvSel": 191,
+          "ExtSel": "",
+          "Umask": "b00010010",
+     },
+     "iMC.WR_CAS_RANK7.BANK10": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Counters": "0-3",
+          "Desc": "WR_CAS Access to Rank 7",
+          "EvSel": 191,
+          "ExtSel": "",
+          "Umask": "b00001010",
+     },
+     
+# IRP:
+     "IRP.CACHE_TOTAL_OCCUPANCY": {
+          "Box": "IRP",
+          "Category": "IRP WRITE_CACHE Events",
+          "Counters": "0-1",
+          "Defn": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.",
+          "Desc": "Total Write Cache Occupancy",
+          "EvSel": 18,
+          "ExtSel": "",
+          "MaxIncCyc": 128,
+          "SubCtr": 1,
+     },
+     "IRP.CACHE_TOTAL_OCCUPANCY.ANY": {
+          "Box": "IRP",
+          "Category": "IRP WRITE_CACHE Events",
+          "Counters": "0-1",
+          "Defn": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.",
+          "Desc": "Total Write Cache Occupancy",
+          "EvSel": 18,
+          "ExtSel": "",
+          "MaxIncCyc": 128,
+          "SubCtr": 1,
+          "Umask": "b00000001",
+     },
+     "IRP.CACHE_TOTAL_OCCUPANCY.SOURCE": {
+          "Box": "IRP",
+          "Category": "IRP WRITE_CACHE Events",
+          "Counters": "0-1",
+          "Defn": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.",
+          "Desc": "Total Write Cache Occupancy",
+          "EvSel": 18,
+          "ExtSel": "",
+          "MaxIncCyc": 128,
+          "SubCtr": 1,
+          "Umask": "b00000010",
+     },
+     "IRP.CLOCKTICKS": {
+          "Box": "IRP",
+          "Category": "IRP IO_CLKS Events",
+          "Counters": "0-1",
+          "Defn": "Number of clocks in the IRP.",
+          "Desc": "Clocks in the IRP",
+          "EvSel": 0,
+          "ExtSel": "",
+     },
+     "IRP.COHERENT_OPS": {
+          "Box": "IRP",
+          "Category": "IRP Coherency Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of coherency related operations servied by the IRP",
+          "Desc": "Coherent Ops",
+          "EvSel": 19,
+          "ExtSel": "",
+     },
+     "IRP.COHERENT_OPS.PCIRDCUR": {
+          "Box": "IRP",
+          "Category": "IRP Coherency Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of coherency related operations servied by the IRP",
+          "Desc": "Coherent Ops",
+          "EvSel": 19,
+          "ExtSel": "",
+          "Umask": "bxxxxxxx1",
+     },
+     "IRP.COHERENT_OPS.CRD": {
+          "Box": "IRP",
+          "Category": "IRP Coherency Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of coherency related operations servied by the IRP",
+          "Desc": "Coherent Ops",
+          "EvSel": 19,
+          "ExtSel": "",
+          "Umask": "bxxxxxx1x",
+     },
+     "IRP.COHERENT_OPS.DRD": {
+          "Box": "IRP",
+          "Category": "IRP Coherency Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of coherency related operations servied by the IRP",
+          "Desc": "Coherent Ops",
+          "EvSel": 19,
+          "ExtSel": "",
+          "Umask": "bxxxxx1xx",
+     },
+     "IRP.COHERENT_OPS.PCITOM": {
+          "Box": "IRP",
+          "Category": "IRP Coherency Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of coherency related operations servied by the IRP",
+          "Desc": "Coherent Ops",
+          "EvSel": 19,
+          "ExtSel": "",
+          "Umask": "bxxx1xxxx",
+     },
+     "IRP.COHERENT_OPS.PCIDCAHINT": {
+          "Box": "IRP",
+          "Category": "IRP Coherency Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of coherency related operations servied by the IRP",
+          "Desc": "Coherent Ops",
+          "EvSel": 19,
+          "ExtSel": "",
+          "Umask": "bxx1xxxxx",
+     },
+     "IRP.COHERENT_OPS.CLFLUSH": {
+          "Box": "IRP",
+          "Category": "IRP Coherency Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of coherency related operations servied by the IRP",
+          "Desc": "Coherent Ops",
+          "EvSel": 19,
+          "ExtSel": "",
+          "Umask": "b1xxxxxxx",
+     },
+     "IRP.COHERENT_OPS.WBMTOI": {
+          "Box": "IRP",
+          "Category": "IRP Coherency Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of coherency related operations servied by the IRP",
+          "Desc": "Coherent Ops",
+          "EvSel": 19,
+          "ExtSel": "",
+          "Umask": "bx1xxxxxx",
+     },
+     "IRP.COHERENT_OPS.RFO": {
+          "Box": "IRP",
+          "Category": "IRP Coherency Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of coherency related operations servied by the IRP",
+          "Desc": "Coherent Ops",
+          "EvSel": 19,
+          "ExtSel": "",
+          "Umask": "bxxxx1xxx",
+     },
+     "IRP.MISC0": {
+          "Box": "IRP",
+          "Category": "IRP MISC Events",
+          "Counters": "0-1",
+          "Desc": "Misc Events - Set 0",
+          "EvSel": 20,
+          "ExtSel": "",
+     },
+     "IRP.MISC0.2ND_ATOMIC_INSERT": {
+          "Box": "IRP",
+          "Category": "IRP MISC Events",
+          "Counters": "0-1",
+          "Desc": "Misc Events - Set 0",
+          "EvSel": 20,
+          "ExtSel": "",
+          "Umask": "bx001xx00",
+     },
+     "IRP.MISC0.2ND_RD_INSERT": {
+          "Box": "IRP",
+          "Category": "IRP MISC Events",
+          "Counters": "0-1",
+          "Desc": "Misc Events - Set 0",
+          "EvSel": 20,
+          "ExtSel": "",
+          "Umask": "bx00xx100",
+     },
+     "IRP.MISC0.FAST_REJ": {
+          "Box": "IRP",
+          "Category": "IRP MISC Events",
+          "Counters": "0-1",
+          "Desc": "Misc Events - Set 0",
+          "EvSel": 20,
+          "ExtSel": "",
+          "Umask": "b0000001x",
+     },
+     "IRP.MISC0.FAST_XFER": {
+          "Box": "IRP",
+          "Category": "IRP MISC Events",
+          "Counters": "0-1",
+          "Desc": "Misc Events - Set 0",
+          "EvSel": 20,
+          "ExtSel": "",
+          "Umask": "bxx100000",
+     },
+     "IRP.MISC0.PF_TIMEOUT": {
+          "Box": "IRP",
+          "Category": "IRP MISC Events",
+          "Counters": "0-1",
+          "Desc": "Misc Events - Set 0",
+          "EvSel": 20,
+          "ExtSel": "",
+          "Umask": "b1xx00000",
+     },
+     "IRP.MISC0.FAST_REQ": {
+          "Box": "IRP",
+          "Category": "IRP MISC Events",
+          "Counters": "0-1",
+          "Desc": "Misc Events - Set 0",
+          "EvSel": 20,
+          "ExtSel": "",
+          "Umask": "b000000x1",
+     },
+     "IRP.MISC0.2ND_WR_INSERT": {
+          "Box": "IRP",
+          "Category": "IRP MISC Events",
+          "Counters": "0-1",
+          "Desc": "Misc Events - Set 0",
+          "EvSel": 20,
+          "ExtSel": "",
+          "Umask": "bx00x1x00",
+     },
+     "IRP.MISC0.PF_ACK_HINT": {
+          "Box": "IRP",
+          "Category": "IRP MISC Events",
+          "Counters": "0-1",
+          "Desc": "Misc Events - Set 0",
+          "EvSel": 20,
+          "ExtSel": "",
+          "Umask": "bx1x00000",
+     },
+     "IRP.MISC1": {
+          "Box": "IRP",
+          "Category": "IRP MISC Events",
+          "Counters": "0-1",
+          "Desc": "Misc Events - Set 1",
+          "EvSel": 21,
+          "ExtSel": "",
+     },
+     "IRP.MISC1.SLOW_S": {
+          "Box": "IRP",
+          "Category": "IRP MISC Events",
+          "Counters": "0-1",
+          "Desc": "Misc Events - Set 1",
+          "EvSel": 21,
+          "ExtSel": "",
+          "Umask": "b000xxx1x",
+     },
+     "IRP.MISC1.SLOW_M": {
+          "Box": "IRP",
+          "Category": "IRP MISC Events",
+          "Counters": "0-1",
+          "Desc": "Misc Events - Set 1",
+          "EvSel": 21,
+          "ExtSel": "",
+          "Umask": "b000x1xxx",
+     },
+     "IRP.MISC1.SLOW_I": {
+          "Box": "IRP",
+          "Category": "IRP MISC Events",
+          "Counters": "0-1",
+          "Desc": "Misc Events - Set 1",
+          "EvSel": 21,
+          "ExtSel": "",
+          "Umask": "b000xxxx1",
+     },
+     "IRP.MISC1.SEC_RCVD_INVLD": {
+          "Box": "IRP",
+          "Category": "IRP MISC Events",
+          "Counters": "0-1",
+          "Desc": "Misc Events - Set 1",
+          "EvSel": 21,
+          "ExtSel": "",
+          "Umask": "bxx1x0000",
+     },
+     "IRP.MISC1.SLOW_E": {
+          "Box": "IRP",
+          "Category": "IRP MISC Events",
+          "Counters": "0-1",
+          "Desc": "Misc Events - Set 1",
+          "EvSel": 21,
+          "ExtSel": "",
+          "Umask": "b000xx1xx",
+     },
+     "IRP.MISC1.LOST_FWD": {
+          "Box": "IRP",
+          "Category": "IRP MISC Events",
+          "Counters": "0-1",
+          "Desc": "Misc Events - Set 1",
+          "EvSel": 21,
+          "ExtSel": "",
+          "Umask": "b0001xxxx",
+     },
+     "IRP.MISC1.SEC_RCVD_VLD": {
+          "Box": "IRP",
+          "Category": "IRP MISC Events",
+          "Counters": "0-1",
+          "Desc": "Misc Events - Set 1",
+          "EvSel": 21,
+          "ExtSel": "",
+          "Umask": "bx1xx0000",
+     },
+     "IRP.MISC1.DATA_THROTTLE": {
+          "Box": "IRP",
+          "Category": "IRP MISC Events",
+          "Counters": "0-1",
+          "Desc": "Misc Events - Set 1",
+          "EvSel": 21,
+          "ExtSel": "",
+          "Umask": "b1xxx0000",
+     },
+     "IRP.RxR_AK_INSERTS": {
+          "Box": "IRP",
+          "Category": "IRP AK_INGRESS Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of allocations into the AK Ingress.  This queue is where the IRP receives responses from R2PCIe (the ring).",
+          "Desc": "AK Ingress Occupancy",
+          "EvSel": 10,
+          "ExtSel": "",
+     },
+     "IRP.RxR_BL_DRS_CYCLES_FULL": {
+          "Box": "IRP",
+          "Category": "IRP BL_INGRESS_DRS Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+          "EvSel": 4,
+          "ExtSel": "",
+     },
+     "IRP.RxR_BL_DRS_INSERTS": {
+          "Box": "IRP",
+          "Category": "IRP BL_INGRESS_DRS Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+          "Desc": "BL Ingress Occupancy - DRS",
+          "EvSel": 1,
+          "ExtSel": "",
+     },
+     "IRP.RxR_BL_DRS_OCCUPANCY": {
+          "Box": "IRP",
+          "Category": "IRP BL_INGRESS_DRS Events",
+          "Counters": "0-1",
+          "Defn": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+          "EvSel": 7,
+          "ExtSel": "",
+          "MaxIncCyc": 24,
+          "SubCtr": 1,
+     },
+     "IRP.RxR_BL_NCB_CYCLES_FULL": {
+          "Box": "IRP",
+          "Category": "IRP BL_INGRESS_NCB Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+          "EvSel": 5,
+          "ExtSel": "",
+     },
+     "IRP.RxR_BL_NCB_INSERTS": {
+          "Box": "IRP",
+          "Category": "IRP BL_INGRESS_NCB Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+          "Desc": "BL Ingress Occupancy - NCB",
+          "EvSel": 2,
+          "ExtSel": "",
+     },
+     "IRP.RxR_BL_NCB_OCCUPANCY": {
+          "Box": "IRP",
+          "Category": "IRP BL_INGRESS_NCB Events",
+          "Counters": "0-1",
+          "Defn": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+          "EvSel": 8,
+          "ExtSel": "",
+          "MaxIncCyc": 24,
+          "SubCtr": 1,
+     },
+     "IRP.RxR_BL_NCS_CYCLES_FULL": {
+          "Box": "IRP",
+          "Category": "IRP BL_INGRESS_NCS Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+          "EvSel": 6,
+          "ExtSel": "",
+     },
+     "IRP.RxR_BL_NCS_INSERTS": {
+          "Box": "IRP",
+          "Category": "IRP BL_INGRESS_NCS Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+          "Desc": "BL Ingress Occupancy - NCS",
+          "EvSel": 3,
+          "ExtSel": "",
+     },
+     "IRP.RxR_BL_NCS_OCCUPANCY": {
+          "Box": "IRP",
+          "Category": "IRP BL_INGRESS_NCS Events",
+          "Counters": "0-1",
+          "Defn": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+          "EvSel": 9,
+          "ExtSel": "",
+          "MaxIncCyc": 24,
+          "SubCtr": 1,
+     },
+     "IRP.SNOOP_RESP": {
+          "Box": "IRP",
+          "Category": "IRP TRANSACTIONS Events",
+          "Counters": "0-1",
+          "Desc": "Snoop Responses",
+          "EvSel": 23,
+          "ExtSel": "",
+          "Notes": "The first 4 subevent bits are the Responses to the Code/Data/Invalid Snoops represented by the last 3 subevent bits.  At least 1 of the bottom 4 bits must be combined with 1 of the top 3 bits to obtain counts.  Unsure which combinations are possible.",
+     },
+     "IRP.SNOOP_RESP.SNPINV": {
+          "Box": "IRP",
+          "Category": "IRP TRANSACTIONS Events",
+          "Counters": "0-1",
+          "Desc": "Snoop Responses",
+          "EvSel": 23,
+          "ExtSel": "",
+          "Notes": "The first 4 subevent bits are the Responses to the Code/Data/Invalid Snoops represented by the last 3 subevent bits.  At least 1 of the bottom 4 bits must be combined with 1 of the top 3 bits to obtain counts.  Unsure which combinations are possible.",
+          "Umask": "bx1xxxxxx",
+     },
+     "IRP.SNOOP_RESP.HIT_I": {
+          "Box": "IRP",
+          "Category": "IRP TRANSACTIONS Events",
+          "Counters": "0-1",
+          "Desc": "Snoop Responses",
+          "EvSel": 23,
+          "ExtSel": "",
+          "Notes": "The first 4 subevent bits are the Responses to the Code/Data/Invalid Snoops represented by the last 3 subevent bits.  At least 1 of the bottom 4 bits must be combined with 1 of the top 3 bits to obtain counts.  Unsure which combinations are possible.",
+          "Umask": "bxxxxxx1x",
+     },
+     "IRP.SNOOP_RESP.SNPDATA": {
+          "Box": "IRP",
+          "Category": "IRP TRANSACTIONS Events",
+          "Counters": "0-1",
+          "Desc": "Snoop Responses",
+          "EvSel": 23,
+          "ExtSel": "",
+          "Notes": "The first 4 subevent bits are the Responses to the Code/Data/Invalid Snoops represented by the last 3 subevent bits.  At least 1 of the bottom 4 bits must be combined with 1 of the top 3 bits to obtain counts.  Unsure which combinations are possible.",
+          "Umask": "bxx1xxxxx",
+     },
+     "IRP.SNOOP_RESP.HIT_ES": {
+          "Box": "IRP",
+          "Category": "IRP TRANSACTIONS Events",
+          "Counters": "0-1",
+          "Desc": "Snoop Responses",
+          "EvSel": 23,
+          "ExtSel": "",
+          "Notes": "The first 4 subevent bits are the Responses to the Code/Data/Invalid Snoops represented by the last 3 subevent bits.  At least 1 of the bottom 4 bits must be combined with 1 of the top 3 bits to obtain counts.  Unsure which combinations are possible.",
+          "Umask": "bxxxxx1xx",
+     },
+     "IRP.SNOOP_RESP.SNPCODE": {
+          "Box": "IRP",
+          "Category": "IRP TRANSACTIONS Events",
+          "Counters": "0-1",
+          "Desc": "Snoop Responses",
+          "EvSel": 23,
+          "ExtSel": "",
+          "Notes": "The first 4 subevent bits are the Responses to the Code/Data/Invalid Snoops represented by the last 3 subevent bits.  At least 1 of the bottom 4 bits must be combined with 1 of the top 3 bits to obtain counts.  Unsure which combinations are possible.",
+          "Umask": "bxxx1xxxx",
+     },
+     "IRP.SNOOP_RESP.MISS": {
+          "Box": "IRP",
+          "Category": "IRP TRANSACTIONS Events",
+          "Counters": "0-1",
+          "Desc": "Snoop Responses",
+          "EvSel": 23,
+          "ExtSel": "",
+          "Notes": "The first 4 subevent bits are the Responses to the Code/Data/Invalid Snoops represented by the last 3 subevent bits.  At least 1 of the bottom 4 bits must be combined with 1 of the top 3 bits to obtain counts.  Unsure which combinations are possible.",
+          "Umask": "bxxxxxxx1",
+     },
+     "IRP.SNOOP_RESP.HIT_M": {
+          "Box": "IRP",
+          "Category": "IRP TRANSACTIONS Events",
+          "Counters": "0-1",
+          "Desc": "Snoop Responses",
+          "EvSel": 23,
+          "ExtSel": "",
+          "Notes": "The first 4 subevent bits are the Responses to the Code/Data/Invalid Snoops represented by the last 3 subevent bits.  At least 1 of the bottom 4 bits must be combined with 1 of the top 3 bits to obtain counts.  Unsure which combinations are possible.",
+          "Umask": "bxxxx1xxx",
+     },
+     "IRP.TRANSACTIONS": {
+          "Box": "IRP",
+          "Category": "IRP TRANSACTIONS Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of \"Inbound\" transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.",
+          "Desc": "Inbound Transaction Count",
+          "EvSel": 22,
+          "ExtSel": "",
+          "Notes": "Bit 7 is a filter that can be applied to the other subevents.  Meaningless by itself.",
+     },
+     "IRP.TRANSACTIONS.WRITES": {
+          "Box": "IRP",
+          "Category": "IRP TRANSACTIONS Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of \"Inbound\" transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.",
+          "Desc": "Inbound Transaction Count",
+          "EvSel": 22,
+          "ExtSel": "",
+          "Notes": "Bit 7 is a filter that can be applied to the other subevents.  Meaningless by itself.",
+          "Umask": "bxxxxxx1x",
+     },
+     "IRP.TRANSACTIONS.WR_PREF": {
+          "Box": "IRP",
+          "Category": "IRP TRANSACTIONS Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of \"Inbound\" transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.",
+          "Desc": "Inbound Transaction Count",
+          "EvSel": 22,
+          "ExtSel": "",
+          "Notes": "Bit 7 is a filter that can be applied to the other subevents.  Meaningless by itself.",
+          "Umask": "bxxxx1xxx",
+     },
+     "IRP.TRANSACTIONS.RD_PREF": {
+          "Box": "IRP",
+          "Category": "IRP TRANSACTIONS Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of \"Inbound\" transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.",
+          "Desc": "Inbound Transaction Count",
+          "EvSel": 22,
+          "ExtSel": "",
+          "Notes": "Bit 7 is a filter that can be applied to the other subevents.  Meaningless by itself.",
+          "Umask": "bxxxxx1xx",
+     },
+     "IRP.TRANSACTIONS.ATOMIC": {
+          "Box": "IRP",
+          "Category": "IRP TRANSACTIONS Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of \"Inbound\" transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.",
+          "Desc": "Inbound Transaction Count",
+          "EvSel": 22,
+          "ExtSel": "",
+          "Notes": "Bit 7 is a filter that can be applied to the other subevents.  Meaningless by itself.",
+          "Umask": "bxxx1xxxx",
+     },
+     "IRP.TRANSACTIONS.OTHER": {
+          "Box": "IRP",
+          "Category": "IRP TRANSACTIONS Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of \"Inbound\" transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.",
+          "Desc": "Inbound Transaction Count",
+          "EvSel": 22,
+          "ExtSel": "",
+          "Notes": "Bit 7 is a filter that can be applied to the other subevents.  Meaningless by itself.",
+          "Umask": "bxx1xxxxx",
+     },
+     "IRP.TRANSACTIONS.ORDERINGQ": {
+          "Box": "IRP",
+          "Category": "IRP TRANSACTIONS Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of \"Inbound\" transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.",
+          "Desc": "Inbound Transaction Count",
+          "EvSel": 22,
+          "ExtSel": "",
+          "Notes": "Bit 7 is a filter that can be applied to the other subevents.  Meaningless by itself.",
+          "Umask": "bx1xxxxxx",
+     },
+     "IRP.TRANSACTIONS.READS": {
+          "Box": "IRP",
+          "Category": "IRP TRANSACTIONS Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of \"Inbound\" transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.",
+          "Desc": "Inbound Transaction Count",
+          "EvSel": 22,
+          "ExtSel": "",
+          "Notes": "Bit 7 is a filter that can be applied to the other subevents.  Meaningless by itself.",
+          "Umask": "bxxxxxxx1",
+     },
+     "IRP.TxR_AD_STALL_CREDIT_CYCLES": {
+          "Box": "IRP",
+          "Category": "IRP STALL_CYCLES Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.",
+          "Desc": "No AD Egress Credit Stalls",
+          "EvSel": 24,
+          "ExtSel": "",
+     },
+     "IRP.TxR_BL_STALL_CREDIT_CYCLES": {
+          "Box": "IRP",
+          "Category": "IRP STALL_CYCLES Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
+          "Desc": "No BL Egress Credit Stalls",
+          "EvSel": 25,
+          "ExtSel": "",
+     },
+     "IRP.TxR_DATA_INSERTS_NCB": {
+          "Box": "IRP",
+          "Category": "IRP OUTBOUND_REQUESTS Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of requests issued to the switch (towards the devices).",
+          "Desc": "Outbound Read Requests",
+          "EvSel": 14,
+          "ExtSel": "",
+     },
+     "IRP.TxR_DATA_INSERTS_NCS": {
+          "Box": "IRP",
+          "Category": "IRP OUTBOUND_REQUESTS Events",
+          "Counters": "0-1",
+          "Defn": "Counts the number of requests issued to the switch (towards the devices).",
+          "Desc": "Outbound Read Requests",
+          "EvSel": 15,
+          "ExtSel": "",
+     },
+     "IRP.TxR_REQUEST_OCCUPANCY": {
+          "Box": "IRP",
+          "Category": "IRP OUTBOUND_REQUESTS Events",
+          "Counters": "0-1",
+          "Defn": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices).  This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.",
+          "Desc": "Outbound Request Queue Occupancy",
+          "EvSel": 13,
+          "ExtSel": "",
+          "SubCtr": 1,
+     },
+     
+# PCU:
+     "PCU.CLOCKTICKS": {
+          "Box": "PCU",
+          "Category": "PCU PCLK Events",
+          "Counters": "0-3",
+          "Defn": "The PCU runs off a fixed 1 GHz clock.  This event counts the number of pclk cycles measured while the counter was enabled.  The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
+          "Desc": "pclk Cycles",
+          "EvSel": 0,
+          "ExtSel": "",
+     },
+     "PCU.CORE0_TRANSITION_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+          "Desc": "Core C State Transition Cycles",
+          "EvSel": 96,
+          "ExtSel": "",
+          "Notes": "This only tracks the hardware portion in the RCFSM (CFCFSM).  This portion is just doing the core C state transition.  It does not include any necessary frequency/voltage transitions.",
+     },
+     "PCU.CORE10_TRANSITION_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+          "Desc": "Core C State Transition Cycles",
+          "EvSel": 106,
+          "ExtSel": "",
+     },
+     "PCU.CORE11_TRANSITION_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+          "Desc": "Core C State Transition Cycles",
+          "EvSel": 107,
+          "ExtSel": "",
+     },
+     "PCU.CORE12_TRANSITION_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+          "Desc": "Core C State Transition Cycles",
+          "EvSel": 108,
+          "ExtSel": "",
+     },
+     "PCU.CORE13_TRANSITION_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+          "Desc": "Core C State Transition Cycles",
+          "EvSel": 109,
+          "ExtSel": "",
+     },
+     "PCU.CORE14_TRANSITION_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+          "Desc": "Core C State Transition Cycles",
+          "EvSel": 110,
+          "ExtSel": "",
+     },
+     "PCU.CORE15_TRANSITION_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+          "Desc": "Core C State Transition Cycles",
+          "EvSel": 111,
+          "ExtSel": "",
+     },
+     "PCU.CORE16_TRANSITION_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+          "Desc": "Core C State Transition Cycles",
+          "EvSel": 112,
+          "ExtSel": "",
+     },
+     "PCU.CORE17_TRANSITION_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+          "Desc": "Core C State Transition Cycles",
+          "EvSel": 113,
+          "ExtSel": "",
+     },
+     "PCU.CORE1_TRANSITION_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+          "Desc": "Core C State Transition Cycles",
+          "EvSel": 97,
+          "ExtSel": "",
+     },
+     "PCU.CORE2_TRANSITION_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+          "Desc": "Core C State Transition Cycles",
+          "EvSel": 98,
+          "ExtSel": "",
+     },
+     "PCU.CORE3_TRANSITION_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+          "Desc": "Core C State Transition Cycles",
+          "EvSel": 99,
+          "ExtSel": "",
+     },
+     "PCU.CORE4_TRANSITION_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+          "Desc": "Core C State Transition Cycles",
+          "EvSel": 100,
+          "ExtSel": "",
+     },
+     "PCU.CORE5_TRANSITION_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+          "Desc": "Core C State Transition Cycles",
+          "EvSel": 101,
+          "ExtSel": "",
+     },
+     "PCU.CORE6_TRANSITION_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+          "Desc": "Core C State Transition Cycles",
+          "EvSel": 102,
+          "ExtSel": "",
+     },
+     "PCU.CORE7_TRANSITION_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+          "Desc": "Core C State Transition Cycles",
+          "EvSel": 103,
+          "ExtSel": "",
+     },
+     "PCU.CORE8_TRANSITION_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+          "Desc": "Core C State Transition Cycles",
+          "EvSel": 104,
+          "ExtSel": "",
+          "Notes": "This only tracks the hardware portion in the RCFSM (CFCFSM).  This portion is just doing the core C state transition.  It does not include any necessary frequency/voltage transitions.",
+     },
+     "PCU.CORE9_TRANSITION_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+          "Desc": "Core C State Transition Cycles",
+          "EvSel": 105,
+          "ExtSel": "",
+     },
+     "PCU.DEMOTIONS_CORE0": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when a configurable cores had a C-state demotion",
+          "Desc": "Core C State Demotions",
+          "EvSel": 48,
+          "ExtSel": "",
+     },
+     "PCU.DEMOTIONS_CORE1": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when a configurable cores had a C-state demotion",
+          "Desc": "Core C State Demotions",
+          "EvSel": 49,
+          "ExtSel": "",
+     },
+     "PCU.DEMOTIONS_CORE10": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when a configurable cores had a C-state demotion",
+          "Desc": "Core C State Demotions",
+          "EvSel": 58,
+          "ExtSel": "",
+     },
+     "PCU.DEMOTIONS_CORE11": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when a configurable cores had a C-state demotion",
+          "Desc": "Core C State Demotions",
+          "EvSel": 59,
+          "ExtSel": "",
+     },
+     "PCU.DEMOTIONS_CORE12": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when a configurable cores had a C-state demotion",
+          "Desc": "Core C State Demotions",
+          "EvSel": 60,
+          "ExtSel": "",
+     },
+     "PCU.DEMOTIONS_CORE13": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when a configurable cores had a C-state demotion",
+          "Desc": "Core C State Demotions",
+          "EvSel": 61,
+          "ExtSel": "",
+     },
+     "PCU.DEMOTIONS_CORE14": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when a configurable cores had a C-state demotion",
+          "Desc": "Core C State Demotions",
+          "EvSel": 62,
+          "ExtSel": "",
+     },
+     "PCU.DEMOTIONS_CORE15": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when a configurable cores had a C-state demotion",
+          "Desc": "Core C State Demotions",
+          "EvSel": 63,
+          "ExtSel": "",
+     },
+     "PCU.DEMOTIONS_CORE16": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when a configurable cores had a C-state demotion",
+          "Desc": "Core C State Demotions",
+          "EvSel": 64,
+          "ExtSel": "",
+     },
+     "PCU.DEMOTIONS_CORE17": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when a configurable cores had a C-state demotion",
+          "Desc": "Core C State Demotions",
+          "EvSel": 65,
+          "ExtSel": "",
+     },
+     "PCU.DEMOTIONS_CORE2": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when a configurable cores had a C-state demotion",
+          "Desc": "Core C State Demotions",
+          "EvSel": 50,
+          "ExtSel": "",
+     },
+     "PCU.DEMOTIONS_CORE3": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when a configurable cores had a C-state demotion",
+          "Desc": "Core C State Demotions",
+          "EvSel": 51,
+          "ExtSel": "",
+     },
+     "PCU.DEMOTIONS_CORE4": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when a configurable cores had a C-state demotion",
+          "Desc": "Core C State Demotions",
+          "EvSel": 52,
+          "ExtSel": "",
+     },
+     "PCU.DEMOTIONS_CORE5": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when a configurable cores had a C-state demotion",
+          "Desc": "Core C State Demotions",
+          "EvSel": 53,
+          "ExtSel": "",
+     },
+     "PCU.DEMOTIONS_CORE6": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when a configurable cores had a C-state demotion",
+          "Desc": "Core C State Demotions",
+          "EvSel": 54,
+          "ExtSel": "",
+     },
+     "PCU.DEMOTIONS_CORE7": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when a configurable cores had a C-state demotion",
+          "Desc": "Core C State Demotions",
+          "EvSel": 55,
+          "ExtSel": "",
+     },
+     "PCU.DEMOTIONS_CORE8": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when a configurable cores had a C-state demotion",
+          "Desc": "Core C State Demotions",
+          "EvSel": 56,
+          "ExtSel": "",
+     },
+     "PCU.DEMOTIONS_CORE9": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of times when a configurable cores had a C-state demotion",
+          "Desc": "Core C State Demotions",
+          "EvSel": 57,
+          "ExtSel": "",
+     },
+     "PCU.FREQ_MAX_LIMIT_THERMAL_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU FREQ_MAX_LIMIT Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when thermal conditions are the upper limit on frequency.  This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature.  This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.",
+          "Desc": "Thermal Strongest Upper Limit Cycles",
+          "EvSel": 4,
+          "ExtSel": "",
+     },
+     "PCU.FREQ_MAX_OS_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU FREQ_MAX_LIMIT Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the OS is the upper limit on frequency.",
+          "Desc": "OS Strongest Upper Limit Cycles",
+          "EvSel": 6,
+          "ExtSel": "",
+          "Notes": "Essentially, this event says the OS is getting the frequency it requested.",
+     },
+     "PCU.FREQ_MAX_POWER_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU FREQ_MAX_LIMIT Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when power is the upper limit on frequency.",
+          "Desc": "Power Strongest Upper Limit Cycles",
+          "EvSel": 5,
+          "ExtSel": "",
+     },
+     "PCU.FREQ_MIN_IO_P_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU FREQ_MIN_LIMIT Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower.  This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW.  This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
+          "Desc": "IO P Limit Strongest Lower Limit Cycles",
+          "EvSel": 115,
+          "ExtSel": "",
+     },
+     "PCU.FREQ_TRANS_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU FREQ_TRANS Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the system is changing frequency.  This can not be filtered by thread ID.  One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
+          "Desc": "Cycles spent changing Frequency",
+          "EvSel": 116,
+          "ExtSel": "",
+     },
+     "PCU.MEMORY_PHASE_SHEDDING_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU MEMORY_PHASE_SHEDDING Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that the PCU has triggered memory phase shedding.  This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
+          "Desc": "Memory Phase Shedding Cycles",
+          "EvSel": 47,
+          "ExtSel": "",
+          "Notes": "Package C1",
+     },
+     "PCU.PKG_RESIDENCY_C0_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU PKG_C_STATE_RESIDENCY Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the package was in C0.  This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert).  Residency events do not include transition times.",
+          "Desc": "Package C State Residency - C0",
+          "EvSel": 42,
+          "ExtSel": "",
+     },
+     "PCU.PKG_RESIDENCY_C1E_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU PKG_C_STATE_RESIDENCY Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the package was in C1E.  This event can be used in conjunction with edge detect to count C1E entrances (or exits using invert).  Residency events do not include transition times.",
+          "Desc": "Package C State Residency - C1E",
+          "EvSel": 78,
+          "ExtSel": "",
+     },
+     "PCU.PKG_RESIDENCY_C2E_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU PKG_C_STATE_RESIDENCY Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the package was in C2E.  This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert).  Residency events do not include transition times.",
+          "Desc": "Package C State Residency - C2E",
+          "EvSel": 43,
+          "ExtSel": "",
+     },
+     "PCU.PKG_RESIDENCY_C3_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU PKG_C_STATE_RESIDENCY Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the package was in C3.  This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert).  Residency events do not include transition times.",
+          "Desc": "Package C State Residency - C3",
+          "EvSel": 44,
+          "ExtSel": "",
+     },
+     "PCU.PKG_RESIDENCY_C6_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU PKG_C_STATE_RESIDENCY Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the package was in C6.  This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert).  Residency events do not include transition times.",
+          "Desc": "Package C State Residency - C6",
+          "EvSel": 45,
+          "ExtSel": "",
+     },
+     "PCU.PKG_RESIDENCY_C7_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU PKG_C_STATE_RESIDENCY Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles when the package was in C7.  This event can be used in conjunction with edge detect to count C7 entrances (or exits using invert).  Residency events do not include transition times.",
+          "Desc": "Package C7 State Residency",
+          "EvSel": 46,
+          "ExtSel": "",
+     },
+     "PCU.POWER_STATE_OCCUPANCY": {
+          "Box": "PCU",
+          "Category": "PCU POWER_STATE_OCC Events",
+          "Counters": "0-3",
+          "Defn": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
+          "Desc": "Number of cores in C-State",
+          "EvSel": 128,
+          "ExtSel": "",
+          "MaxIncCyc": 8,
+          "SubCtr": 1,
+     },
+     "PCU.POWER_STATE_OCCUPANCY.CORES_C3": {
+          "Box": "PCU",
+          "Category": "PCU POWER_STATE_OCC Events",
+          "Counters": "0-3",
+          "Defn": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
+          "Desc": "Number of cores in C-State",
+          "EvSel": 128,
+          "ExtSel": "",
+          "MaxIncCyc": 8,
+          "SubCtr": 1,
+          "Umask": "b10000000",
+     },
+     "PCU.POWER_STATE_OCCUPANCY.CORES_C6": {
+          "Box": "PCU",
+          "Category": "PCU POWER_STATE_OCC Events",
+          "Counters": "0-3",
+          "Defn": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
+          "Desc": "Number of cores in C-State",
+          "EvSel": 128,
+          "ExtSel": "",
+          "MaxIncCyc": 8,
+          "SubCtr": 1,
+          "Umask": "b11000000",
+     },
+     "PCU.POWER_STATE_OCCUPANCY.CORES_C0": {
+          "Box": "PCU",
+          "Category": "PCU POWER_STATE_OCC Events",
+          "Counters": "0-3",
+          "Defn": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
+          "Desc": "Number of cores in C-State",
+          "EvSel": 128,
+          "ExtSel": "",
+          "MaxIncCyc": 8,
+          "SubCtr": 1,
+          "Umask": "b01000000",
+     },
+     "PCU.PROCHOT_EXTERNAL_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU PROCHOT Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that we are in external PROCHOT mode.  This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
+          "Desc": "External Prochot",
+          "EvSel": 10,
+          "ExtSel": "",
+     },
+     "PCU.PROCHOT_INTERNAL_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU PROCHOT Events",
+          "Counters": "0-3",
+          "Defn": "Counts the number of cycles that we are in Interal PROCHOT mode.  This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
+          "Desc": "Internal Prochot",
+          "EvSel": 9,
+          "ExtSel": "",
+     },
+     "PCU.TOTAL_TRANSITION_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU CORE_C_STATE_TRANSITION Events",
+          "Counters": "0-3",
+          "Defn": "Number of cycles spent performing core C state transitions across all cores.",
+          "Desc": "Total Core C State Transition Cycles",
+          "EvSel": 114,
+          "ExtSel": "",
+     },
+     "PCU.UFS_TRANSITIONS_RING_GV": {
+          "Box": "PCU",
+          "Category": "PCU UFS Events",
+          "Counters": "0-3",
+          "Defn": "Ring GV with same final and initial frequency",
+          "EvSel": 121,
+          "ExtSel": "",
+     },
+     "PCU.VR_HOT_CYCLES": {
+          "Box": "PCU",
+          "Category": "PCU VR_HOT Events",
+          "Counters": "0-3",
+          "Desc": "VR Hot",
+          "EvSel": 66,
+          "ExtSel": "",
+     },
+}
+derived = {
+     
+# R2PCIe:
+     "R2PCIe.CYC_USED_DN": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Defn": "Cycles Used in the Down direction, Even polarity",
+          "Desc": "Cycles Used Down and Even",
+          "Equation": "RING_BL_USED.CCW / SAMPLE_INTERVAL",
+     },
+     "R2PCIe.CYC_USED_UP": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Defn": "Cycles Used in the Up direction, Even polarity",
+          "Desc": "Cycles Used Up and Even",
+          "Equation": "RING_BL_USED.CW / SAMPLE_INTERVAL",
+     },
+     "R2PCIe.RING_THRU_DN_BYTES": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Defn": "Ring throughput in the Down direction, Even polarity in Bytes",
+          "Desc": "Ring Throughput Down and Even",
+          "Equation": "RING_BL_USED.CCW* 32",
+     },
+     "R2PCIe.RING_THRU_UP_BYTES": {
+          "Box": "R2PCIe",
+          "Category": "R2PCIe RING Events",
+          "Defn": "Ring throughput in the Up direction, Even polarity in Bytes",
+          "Desc": "Ring Throughput Up and Even",
+          "Equation": "RING_BL_USED.CW * 32",
+     },
+     
+# CBO:
+     "CBO.AVG_INGRESS_DEPTH": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS Events",
+          "Defn": "Average Depth of the Ingress Queue through the sample interval",
+          "Desc": "Average Ingress Depth",
+          "Equation": "RxR_OCCUPANCY.IRQ  / SAMPLE_INTERVAL",
+     },
+     "CBO.AVG_INGRESS_LATENCY": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS Events",
+          "Defn": "Average Latency of Requests through the Ingress Queue in Uncore Clocks",
+          "Desc": "Average Ingress Latency",
+          "Equation": "RxR_OCCUPANCY.IRQ / RxR_INSERTS.IRQ",
+     },
+     "CBO.AVG_INGRESS_LATENCY_WHEN_NE": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS Events",
+          "Defn": "Average Latency of Requests through the Ingress Queue in Uncore Clocks when Ingress Queue has at least one entry",
+          "Desc": "Average Latency in Non-Empty Ingress",
+          "Equation": "RxR_OCCUPANCY.IRQ / COUNTER0_OCCUPANCY{edge_det,thresh=0x1}",
+     },
+     "CBO.AVG_TOR_DRDS_MISS_WHEN_NE": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Defn": "Average Number of Data Read Entries that Miss the LLC when the TOR is not empty.",
+          "Desc": "Average Data Read Misses in Non-Empty TOR",
+          "Equation": "(TOR_OCCUPANCY.MISS_OPCODE / COUNTER0_OCCUPANCY{edge_det,thresh=0x1})) with:Cn_MSR_PMON_BOX_FILTER1.opc=0x182",
+          "Filter": "CBoFilter1[28:20]",
+     },
+     "CBO.AVG_TOR_DRDS_WHEN_NE": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Defn": "Average Number of Data Read Entries when the TOR is not empty.",
+          "Desc": "Average Data Reads in Non-Empty TOR",
+          "Equation": "(TOR_OCCUPANCY.OPCODE / COUNTER0_OCCUPANCY{edge_det,thresh=0x1}) with:Cn_MSR_PMON_BOX_FILTER1.opc=0x182",
+          "Filter": "CBoFilter1[28:20]",
+     },
+     "CBO.AVG_TOR_DRD_HIT_LATENCY": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Defn": "Average Latency of Data Reads through the TOR that hit the LLC",
+          "Desc": "Data Read Hit Latency through TOR",
+          "Equation": "((TOR_OCCUPANCY.OPCODE  - TOR_OCCUPANCY.MISS_OPCODE) / (TOR_INSERTS.OPCODE - TOR_INSERTS.MISS_OPCODE)) with:Cn_MSR_PMON_BOX_FILTER.opc=0x182",
+          "Filter": "CBoFilter1[28:20]",
+     },
+     "CBO.AVG_TOR_DRD_LATENCY": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Defn": "Average Latency of Data Read Entries making their way through the TOR",
+          "Desc": "Data Read Latency through TOR",
+          "Equation": "(TOR_OCCUPANCY.OPCODE / TOR_INSERTS.OPCODE) with:Cn_MSR_PMON_BOX_FILTER1.opc=0x182",
+          "Filter": "CBoFilter1[28:20]",
+     },
+     "CBO.AVG_TOR_DRD_LOC_MISS_LATENCY": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Defn": "Average Latency of Data Reads through the TOR that miss the LLC and were satsified by Local Memory",
+          "Desc": "Data Read Local Miss Latency through TOR",
+          "Equation": "(TOR_OCCUPANCY.MISS_OPCODE / TOR_INSERTS.MISS_OPCODE) with:Cn_MSR_PMON_BOX_FILTER1.{opc,nid}={0x182,my_node}",
+          "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]",
+     },
+     "CBO.AVG_TOR_DRD_MISS_LATENCY": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Defn": "Average Latency of Data Reads through the TOR that miss the LLC",
+          "Desc": "Data Read Miss Latency through TOR",
+          "Equation": "(TOR_OCCUPANCY.MISS_OPCODE / TOR_INSERTS.MISS_OPCODE) with:Cn_MSR_PMON_BOX_FILTER1.opc=0x182",
+          "Filter": "CBoFilter1[28:20]",
+     },
+     "CBO.AVG_TOR_DRD_REM_MISS_LATENCY": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Defn": "Average Latency of Data Reads through the TOR that miss the LLC and were satsified by a Remote cache or Remote Memory",
+          "Desc": "Data Read Remote Miss Latency through TOR",
+          "Equation": "(TOR_OCCUPANCY.MISS_OPCODE / TOR_INSERTS.MISS_OPCODE) with:Cn_MSR_PMON_BOX_FILTER.{opc,nid}={0x182,other_nodes}",
+          "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]",
+     },
+     "CBO.CYC_INGRESS_BLOCKED": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS Events",
+          "Defn": "Cycles the Ingress Request Queue arbiter was Blocked",
+          "Desc": "Cycles Ingress Blocked",
+          "Equation": "RxR_EXT_STARVED.IRQ  / SAMPLE_INTERVAL",
+     },
+     "CBO.CYC_USED_DN": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Defn": "Cycles Used in the Down direction, Even polarity",
+          "Desc": "Cycles Used Down and Even",
+          "Equation": "RING_BL_USED.CCW / SAMPLE_INTERVAL",
+     },
+     "CBO.CYC_USED_UP": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Defn": "Cycles Used in the Up direction, Even polarity",
+          "Desc": "Cycles Used Up and Even",
+          "Equation": "RING_BL_USED.CW / SAMPLE_INTERVAL",
+     },
+     "CBO.FAST_STR_LLC_MISS": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Defn": "Number of ItoM (fast string) operations that miss the LLC",
+          "Desc": "Fast String misses",
+          "Equation": "TOR_INSERTS.MISS_OPCODE with:Cn_MSR_PMON_BOX_FILTER1.opc=0x1C8 + TOR_INSERTS.MISS_OPCODE with:{Cn_MSR_PMON_BOX_FILTER0.tid=0x3E, Cn_MSR_PMON_BOX_FILTER1.opc=0x1C8}",
+          "Filter": "CBoFilter1[28:20]",
+     },
+     "CBO.FAST_STR_LLC_REQ": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Defn": "Number of ItoM (fast string) operations that reference the LLC",
+          "Desc": "Fast String operations",
+          "Equation": "TOR_INSERTS.OPCODE with:Cn_MSR_PMON_BOX_FILTER1.opc=0x1C8 + TOR_INSERTS.OPCODE with:{Cn_MSR_PMON_BOX_FILTER0.tid=0x3E, Cn_MSR_PMON_BOX_FILTER1.opc=0x1C8}",
+          "Filter": "CBoFilter1[28:20]",
+     },
+     "CBO.INGRESS_REJ_V_INS": {
+          "Box": "CBO",
+          "Category": "CBO INGRESS Events",
+          "Defn": "Ratio of Ingress Request Entries that were rejected vs. inserted",
+          "Desc": "Ingress Rejects vs. Inserts",
+          "Equation": "RxR_INSERTS.IRQ_REJ  / RxR_INSERTS.IRQ",
+     },
+     "CBO.IO_READ_BW": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Defn": "IO Read Bandwidth in MB - Disk or Network Reads",
+          "Desc": "IO Read Bandwidth",
+          "Equation": "(TOR_INSERTS.OPCODE with:{Cn_MSR_PMON_BOX_FILTER0.tid=0x3E, Cn_MSR_PMON_BOX_FILTER1.opc=0x1C8} + TOR_INSERTS.OPCODE with:Cn_MSR_PMON_BOX_FILTER.opc=0x1E6) * 64 / 1000000",
+          "Filter": "CBoFilter0[5:0], CBoFilter1[28:20]",
+     },
+     "CBO.IO_WRITE_BW": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Defn": "IO Write Bandwidth in MB - Disk or Network Writes",
+          "Desc": "IO Write Bandwidth",
+          "Equation": "(TOR_INSERTS.OPCODE with:Cn_MSR_PMON_BOX_FILTER1.opc=0x19E + TOR_INSERTS.OPCODE with:Cn_MSR_PMON_BOX_FILTER.opc=0x1E4) * 64 / 1000000",
+          "Filter": "CBoFilter1[28:20]",
+     },
+     "CBO.LLC_DRD_MISS_PCT": {
+          "Box": "CBO",
+          "Category": "CBO CACHE Events",
+          "Defn": "LLC Data Read miss ratio",
+          "Desc": "LLC DRD Miss Ratio",
+          "Equation": "LLC_LOOKUP.DATA_READ with:Cn_MSR_PMON_BOX_FILTER0.state=0x1 / LLC_LOOKUP.DATA_READ with:Cn_MSR_PMON_BOX_FILTER.state=0x3F",
+          "Filter": "CBoFilter0[23:17]",
+     },
+     "CBO.LLC_MPI": {
+          "Box": "CBO",
+          "Category": "CBO CACHE Events",
+          "Defn": "LLC Misses Per Instruction (code, read, RFO and prefetches)",
+          "Desc": "LLC MPI",
+          "Equation": "LLC_LOOKUP.ANY (Cn_MSR_PMON_BOX_FILTER0.state=0x1) / INST_RETIRED.ALL (on Core)",
+          "Filter": "CBoFilter0[23:17]",
+     },
+     "CBO.LLC_RFO_MISS_PCT": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Defn": "LLC RFO Miss Ratio",
+          "Desc": "LLC RFO Miss Ratio",
+          "Equation": "(TOR_INSERTS.MISS_OPCODE / TOR_INSERTS.OPCODE) with:Cn_MSR_PMON_BOX_FILTER1.opc=0x180 - (TOR_INSERTS.MISS_OPCODE / TOR_INSERTS.OPCODE) with:{Cn_MSR_PMON_BOX_FILTER0.tid=0x3E,Cn_MSR_PMON_BOX_FILTER1.opc=0x180}",
+          "Filter": "CBoFilter1[28:20]",
+     },
+     "CBO.MEM_WB_BYTES": {
+          "Box": "CBO",
+          "Category": "CBO CACHE Events",
+          "Defn": "Data written back to memory in Number of Bytes",
+          "Desc": "Memory Writebacks",
+          "Equation": "LLC_VICTIMS.M_STATE * 64",
+     },
+     "CBO.MMIO_PARTIAL_READS_CPU": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Defn": "Number of Partial MMIO Reads initiated by a Core",
+          "Desc": "MMIO Partial Reads - CPU",
+          "Equation": "TOR_INSERTS.OPCODE with:{Cn_MSR_PMON_BOX_FILTER0.nc=1, Cn_MSR_PMON_BOX_FILTER1.opc=0x187}",
+          "Filter": "CBoFilter1[28:20], CBoFilter1[30]",
+     },
+     "CBO.MMIO_WRITES_CPU": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Defn": "Number of MMIO Writes initiated by a Core",
+          "Desc": "MMIO Writes - CPU",
+          "Equation": "TOR_INSERTS.OPCODE with:{Cn_MSR_PMON_BOX_FILTER0.nc=1, Cn_MSR_PMON_BOX_FILTER1.opc=0x18F}",
+          "Filter": "CBoFilter1[28:20], CBoFilter1[30]",
+     },
+     "CBO.PARTIAL_PCI_WRITES": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Defn": "Number of partial PCI writes",
+          "Desc": "Partial PCI Writes",
+          "Equation": "TOR_INSERTS.OPCODE with:{Cn_MSR_PMON_BOX_FILTER0.tid=0x3E,Cn_MSR_PMON_BOX_FILTER1.opc=0x180}",
+          "Filter": "CBoFilter0[5:0], CBoFilter1[28:20]",
+     },
+     "CBO.PCI_READS": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Defn": "Number of PCI reads (full and partial)",
+          "Desc": "PCI Reads",
+          "Equation": "TOR_INSERTS.OPCODE with:Cn_MSR_PMON_BOX_FILTER1.opc=0x19E",
+          "Filter": "CBoFilter1[28:20]",
+     },
+     "CBO.PCI_WRITES": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Defn": "Number of PCI writes",
+          "Desc": "PCI Writes",
+          "Equation": "TOR_INSERTS.OPCODE with:{Cn_MSR_PMON_BOX_FILTER0.tid=0x3E,Cn_MSR_PMON_BOX_FILTER1.opc=0x1C8}",
+          "Filter": "CBoFilter0[5:0], CBoFilter1[28:20]",
+     },
+     "CBO.RING_THRU_DN_BYTES": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Defn": "Ring throughput in the Down direction, Even polarity in Bytes",
+          "Desc": "Ring Throughput Down and Even",
+          "Equation": "RING_BL_USED.CCW* 32",
+     },
+     "CBO.RING_THRU_UP_BYTES": {
+          "Box": "CBO",
+          "Category": "CBO RING Events",
+          "Defn": "Ring throughput in the Up direction, Even polarity in Bytes",
+          "Desc": "Ring Throughput Up and Even",
+          "Equation": "RING_BL_USED.CW * 32",
+     },
+     "CBO.STREAMED_FULL_STORES": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Defn": "Number of Streamed Store (of Full Cache Line) Transactions",
+          "Desc": "Streaming Stores (Full Line)",
+          "Equation": "TOR_INSERTS.OPCODE with:Cn_MSR_PMON_BOX_FILTER1.opc=0x18C",
+          "Filter": "CBoFilter1[28:20]",
+     },
+     "CBO.STREAMED_PART_STORES": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Defn": "Number of Streamed Store (of Partial Cache Line) Transactions",
+          "Desc": "Streaming Stores (Partial Line)",
+          "Equation": "TOR_INSERTS.OPCODE with:Cn_MSR_PMON_BOX_FILTER1.opc=0x18D",
+          "Filter": "CBoFilter1[28:20]",
+     },
+     "CBO.UC_READS": {
+          "Box": "CBO",
+          "Category": "CBO TOR Events",
+          "Defn": "Uncachable Read Transactions",
+          "Desc": "Uncacheable Reads",
+          "Equation": "TOR_INSERTS.MISS_OPCODE with:Cn_MSR_PMON_BOX_FILTER1.opc=0x187",
+          "Filter": "CBoFilter1[28:20]",
+     },
+     
+# HA:
+     "HA.HITME_INSERTS": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Equation": "HITME_LOOKUP.ALLOCS - HITME_HIT.ALLOCS",
+     },
+     "HA.HITME_INVAL": {
+          "Box": "HA",
+          "Category": "HA HitME Events",
+          "Equation": "HITME_HIT.INVALS",
+     },
+     "HA.PCT_CYCLES_BL_FULL": {
+          "Box": "HA",
+          "Category": "HA EGRESS Events",
+          "Defn": "Percentage of time the BL Egress Queue is full",
+          "Desc": "Percent BL Egress Full",
+          "Equation": "TxR_BL_CYCLES_FULL.ALL / SAMPLE_INTERVAL",
+     },
+     "HA.PCT_CYCLES_D2C_DISABLED": {
+          "Box": "HA",
+          "Category": "HA DIRECT2CORE Events",
+          "Defn": "Percentage of time that Direct2Core was disabled.",
+          "Desc": "Percent D2C Disabled",
+          "Equation": "DIRECT2CORE_CYCLES_DISABLED / SAMPLE_INTERVAL",
+     },
+     "HA.PCT_RD_REQUESTS": {
+          "Box": "HA",
+          "Category": "HA REQUESTS Events",
+          "Defn": "Percentage of HA traffic that is from Read Requests",
+          "Desc": "Percent Read Requests",
+          "Equation": "REQUESTS.READS / (REQUESTS.READS + REQUESTS.WRITES)",
+     },
+     "HA.PCT_WR_REQUESTS": {
+          "Box": "HA",
+          "Category": "HA REQUESTS Events",
+          "Defn": "Percentage of HA traffic that is from Write Requests",
+          "Desc": "Percent Write Requests",
+          "Equation": "REQUESTS.WRITES / (REQUESTS.READS + REQUESTS.WRITES)",
+     },
+     
+# iMC:
+     "iMC.MEM_BW_READS": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Defn": "Memory bandwidth consumed by reads.  Expressed in bytes.",
+          "Desc": "Read Memory Bandwidth",
+          "Equation": "(CAS_COUNT.RD * 64)",
+     },
+     "iMC.MEM_BW_TOTAL": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Defn": "Total memory bandwidth.  Expressed in bytes.",
+          "Desc": "Total Memory Bandwidth",
+          "Equation": "MEM_BW_READS + MEM_BW_WRITES",
+     },
+     "iMC.MEM_BW_WRITES": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Defn": "Memory bandwidth consumed by writes  Expressed in bytes.",
+          "Desc": "Write Memory Bandwidth",
+          "Equation": "(CAS_COUNT.WR * 64)",
+     },
+     "iMC.PCT_CYCLES_CRITICAL_THROTTLE": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Defn": "The percentage of cycles all DRAM ranks in critical thermal throttling",
+          "Desc": "Percent Cycles Critical Throttle",
+          "Equation": "POWER_CRITICAL_THROTTLE_CYCLES / MC_Chy_PCI_PMON_CTR_FIXED",
+     },
+     "iMC.PCT_CYCLES_DLLOFF": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Defn": "The percentage of cycles all DRAM ranks in CKE slow (DLOFF) mode",
+          "Desc": "Percent Cycles DLOFF",
+          "Equation": "POWER_CHANNEL_DLLOFF / MC_Chy_PCI_PMON_CTR_FIXED",
+     },
+     "iMC.PCT_CYCLES_DRAM_RANKx_IN_CKE": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Defn": "The percentage of cycles DRAM rank (x) spent in CKE ON mode.",
+          "Desc": "Percent Cycles DRAM Rank x in CKE",
+          "Equation": "POWER_CKE_CYCLES.RANKx / MC_Chy_PCI_PMON_CTR_FIXED",
+     },
+     "iMC.PCT_CYCLES_DRAM_RANKx_IN_THR": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Defn": "The percentage of cycles DRAM rank (x) spent in thermal throttling.",
+          "Desc": "Percent Cycles DRAM Rank x in CKE",
+          "Equation": "POWER_THROTTLE_CYCLES.RANKx / MC_Chy_PCI_PMON_CTR_FIXED",
+     },
+     "iMC.PCT_CYCLES_PPD": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Defn": "The percentage of cycles all DRAM ranks in PPD mode",
+          "Desc": "Percent Cycles PPD",
+          "Equation": "POWER_CHANNEL_PPD / MC_Chy_PCI_PMON_CTR_FIXED",
+     },
+     "iMC.PCT_CYCLES_SELF_REFRESH": {
+          "Box": "iMC",
+          "Category": "iMC POWER Events",
+          "Defn": "The percentage of cycles Memory is in self refresh power mode",
+          "Desc": "Percent Cycles Self Refresh",
+          "Equation": "POWER_SELF_REFRESH / MC_Chy_PCI_PMON_CTR_FIXED",
+     },
+     "iMC.PCT_REQUESTS_PAGE_EMPTY": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Defn": "Percentage of memory requests that resulted in Page Empty",
+          "Desc": "Percent Requests Page Empty",
+          "Equation": "(ACT_COUNT - PRE_COUNT.PAGE_MISS)/ (CAS_COUNT.RD + CAS_COUNT.WR)",
+     },
+     "iMC.PCT_REQUESTS_PAGE_HIT": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Defn": "Percentage of memory requests that resulted in Page Hits",
+          "Desc": "Percent Requests Page Hit",
+          "Equation": "1 - (PCT_REQUESTS_PAGE_EMPTY + PCT_REQUESTS_PAGE_MISS)",
+     },
+     "iMC.PCT_REQUESTS_PAGE_MISS": {
+          "Box": "iMC",
+          "Category": "iMC CAS Events",
+          "Defn": "Percentage of memory requests that resulted in Page Misses",
+          "Desc": "Percent Requests Page Miss",
+          "Equation": "PRE_COUNT.PAGE_MISS / (CAS_COUNT.RD + CAS_COUNT.WR)",
+     },
+     
+# PCU:
+     "PCU.PCT_CYC_FREQ_OS_LTD": {
+          "Box": "PCU",
+          "Category": "PCU FREQ_MAX_LIMIT Events",
+          "Defn": "Percentage of Cycles the Max Frequency is limited by the OS",
+          "Desc": "Percent Frequency OS Limited",
+          "Equation": "FREQ_MAX_OS_CYCLES / CLOCKTICKS",
+     },
+     "PCU.PCT_CYC_FREQ_POWER_LTD": {
+          "Box": "PCU",
+          "Category": "PCU FREQ_MAX_LIMIT Events",
+          "Defn": "Percentage of Cycles the Max Frequency is limited by power",
+          "Desc": "Percent Frequency Power Limited",
+          "Equation": "FREQ_MAX_POWER_CYCLES / CLOCKTICKS",
+     },
+     "PCU.PCT_CYC_FREQ_THERMAL_LTD": {
+          "Box": "PCU",
+          "Category": "PCU FREQ_MAX_LIMIT Events",
+          "Defn": "Percentage of Cycles the Max Frequency is limited by thermal issues",
+          "Desc": "Percent Frequency Thermal Limited",
+          "Equation": "FREQ_MAX_LIMIT_THERMAL_CYCLES / CLOCKTICKS",
+     },
+}
+categories = (
+     "CBO CACHE Events",
+     "CBO EGRESS Events",
+     "CBO INGRESS Events",
+     "CBO INGRESS_RETRY Events",
+     "CBO MISC Events",
+     "CBO OCCUPANCY Events",
+     "CBO RING Events",
+     "CBO SBO Credit Events",
+     "CBO TOR Events",
+     "CBO UCLK Events",
+     "HA ADDR_OPCODE_MATCH Events",
+     "HA BL_EGRESS Events",
+     "HA BT (Backup Tracker) Events",
+     "HA BYPASS Events",
+     "HA CONFLICTS Events",
+     "HA DIRECT2CORE Events",
+     "HA DIRECTORY Events",
+     "HA EGRESS Events",
+     "HA HitME Events",
+     "HA IMC_MISC Events",
+     "HA IMC_READS Events",
+     "HA IMC_WRITES Events",
+     "HA OSB (Opportunistic Snoop Broadcast) Events",
+     "HA OUTBOUND_TX Events",
+     "HA QPI_IGR_CREDITS Events",
+     "HA REQUESTS Events",
+     "HA RING Events",
+     "HA RPQ_CREDITS Events",
+     "HA SBO Credit Events",
+     "HA SNOOPS Events",
+     "HA SNP_RESP Events",
+     "HA TAD Events",
+     "HA TRACKER Events",
+     "HA UCLK Events",
+     "HA WPQ_CREDITS Events",
+     "IRP AK_INGRESS Events",
+     "IRP BL_INGRESS_DRS Events",
+     "IRP BL_INGRESS_NCB Events",
+     "IRP BL_INGRESS_NCS Events",
+     "IRP Coherency Events",
+     "IRP IO_CLKS Events",
+     "IRP MISC Events",
+     "IRP OUTBOUND_REQUESTS Events",
+     "IRP STALL_CYCLES Events",
+     "IRP TRANSACTIONS Events",
+     "IRP WRITE_CACHE Events",
+     "PCU CORE_C_STATE_TRANSITION Events",
+     "PCU FREQ_MAX_LIMIT Events",
+     "PCU FREQ_MIN_LIMIT Events",
+     "PCU FREQ_TRANS Events",
+     "PCU MEMORY_PHASE_SHEDDING Events",
+     "PCU PCLK Events",
+     "PCU PKG_C_STATE_RESIDENCY Events",
+     "PCU POWER_STATE_OCC Events",
+     "PCU PROCHOT Events",
+     "PCU UFS Events",
+     "PCU VR_HOT Events",
+     "R2PCIe EGRESS Events",
+     "R2PCIe IIO Credit Events",
+     "R2PCIe INGRESS Events",
+     "R2PCIe RING Events",
+     "R2PCIe SBO Credit Events",
+     "R2PCIe UCLK Events",
+     "UBOX EVENT_MSG Events",
+     "UBOX PHOLD Events",
+     "UBOX RACU Events",
+     "iMC ACT Events",
+     "iMC BYPASS Command Events",
+     "iMC CAS Events",
+     "iMC DCLK Events",
+     "iMC DRAM_PRE_ALL Events",
+     "iMC DRAM_REFRESH Events",
+     "iMC ECC Events",
+     "iMC MAJOR_MODES Events",
+     "iMC POWER Events",
+     "iMC PRE Events",
+     "iMC PREEMPTION Events",
+     "iMC RPQ Events",
+     "iMC VMSE Events",
+     "iMC WPQ Events",
+);
diff --git a/ucevent/ucevent.py b/ucevent/ucevent.py
index 95180600..ea023305 100755
--- a/ucevent/ucevent.py
+++ b/ucevent/ucevent.py
@@ -44,6 +44,7 @@
     45: "jkt",
     62: "ivt",
     63: "hsx",
+    86: "bdxde",
 }
 
 args = None
@@ -85,7 +86,9 @@ def max_node(self):
         return max(self.socket)
 
     def socket_to_cpu(self, s):
-        return self.socket[s]
+        if s in self.socket:
+            return self.socket[s]
+        sys.exit("Invalid socket %d" % s)
         
 cpu = CPU()
 cputype = os.getenv("FORCECPU")
@@ -226,6 +229,8 @@ def cmp_cat(a, b):
     return cmp(a.lower(), b.lower())
 
 def get_pager():
+    if args.no_pager:
+	return sys.stdout, None
     f = sys.stdout
     if f.isatty():
         try:
@@ -248,9 +253,6 @@ def print_events(cat, desc, equation):
         ehdr = EventsHeader(c, f)
         ecount += print_list(f, events, c, desc, equation, ehdr)
         dcount += print_list(f, derived, c, desc, equation, ehdr)
-    if not cat:
-        assert ecount == len(events)
-        assert dcount == len(derived)
     if proc:
         f.close()
         proc.wait()
@@ -1053,6 +1055,8 @@ def parse_all():
                    type=argparse.FileType('w'))
     p.add_argument('--resolve', action='store_true',
                    help='Only print resolved event names. Do not run perf.')
+    p.add_argument("--no-pager", action='store_true',
+		   help='Do not use a pager')
     p.add_argument('--debug', help=argparse.SUPPRESS)
     args = p.parse_args()