ultrapif.ldf

<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="ultrapif" device="LCMXO2-2000HC-4TG100C" default_implementation="impl1">
    <Options/>
    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="lse" default_strategy="Strategy1">
        <Options def_top="pif_rom" top="top"/>
        <Source name="top.vhd" type="VHDL" type_short="VHDL">
            <Options top_module="top"/>
        </Source>
        <Source name="ResetGen.vhd" type="VHDL" type_short="VHDL">
            <Options/>
        </Source>
        <Source name="pif_ram.ipx" type="IPX_Module" type_short="IPX">
            <Options/>
        </Source>
        <Source name="pif_rom.ipx" type="IPX_Module" type_short="IPX">
            <Options/>
        </Source>
        <Source name="efb_core.ipx" type="IPX_Module" type_short="IPX">
            <Options/>
        </Source>
        <Source name="bram8_to_32.vhd" type="VHDL" type_short="VHDL">
            <Options/>
        </Source>
        <Source name="dma_mem.ipx" type="IPX_Module" type_short="IPX">
            <Options/>
        </Source>
        <Source name="SerialInterface.vhd" type="VHDL" type_short="VHDL">
            <Options/>
        </Source>
        <Source name="CicInterface.vhd" type="VHDL" type_short="VHDL">
            <Options/>
        </Source>
        <Source name="prio_arbiter_single_slave.vhd" type="VHDL" type_short="VHDL">
            <Options/>
        </Source>
        <Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
            <Options/>
        </Source>
        <Source name="ultrapif.lpf" type="Logic Preference" type_short="LPF">
            <Options/>
        </Source>
    </Implementation>
    <Strategy name="Strategy1" file="pif_test1.sty"/>
</BaliProject>