pif_ram.lpc

[Device]
Family=machxo2
PartType=LCMXO2-2000HC
PartName=LCMXO2-2000HC-4TG100C
SpeedGrade=4
Package=TQFP100
OperatingCondition=COM
Status=S

[IP]
VendorName=Lattice Semiconductor Corporation
CoreType=LPM
CoreStatus=Demo
CoreName=RAM_DP_TRUE
CoreRevision=7.5
ModuleName=pif_ram
SourceFormat=VHDL
ParameterFileVersion=1.0
Date=07/13/2017
Time=19:18:45

[Parameters]
Verilog=0
VHDL=1
EDIF=1
Destination=Synplicity
Expression=BusA(0 to 7)
Order=Big Endian [MSB:LSB]
IO=0
RAddress=2048
RData=8
WAddress=2048
WData=8
ROutputEn=0
RClockEn=0
WOutputEn=0
WClockEn=0
enByte=0
ByteSize=9
Optimization=Speed
Reset=Sync
Reset1=Sync
Init=0
MemFile=
MemFormat=bin
EnECC=0
Pipeline=0
WriteA=Normal
WriteB=Normal
init_data=0

[FilesGenerated]
=mem

[Command]
cmd_line= -w -n pif_ram -lang vhdl -synth lse -bus_exp 7 -bb -arch xo2c00 -type ramdp -device LCMXO2-2000HC -aaddr_width 11 -widtha 8 -baddr_width 11 -widthb 8 -anum_words 2048 -bnum_words 2048 -cascade -1 -mem_init0 -writemodeA NORMAL -writemodeB NORMAL