From 677dc960bd3c82a2b9945cd13d3f8de9fda205ce Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Wed, 2 Aug 2023 17:26:47 +0100 Subject: [PATCH 1/2] Fix various spelling mistakes and typos as found using codespell There are a bunch of spelling mistakes in the json and csv data as well as a variable spelling mistake in scripts/create_perf_json.py. Fix these. Signed-off-by: Colin Ian King --- ADL/events/alderlake_goldencove_core.json | 4 ++-- Atom_TMA.csv | 6 +++--- BDW-DE/events/broadwellde_uncore.json | 20 ++++++++++---------- BDX/events/broadwellx_uncore.json | 20 ++++++++++---------- E-core_TMA_Metrics.csv | 6 +++--- HSW/events/haswell_core.json | 4 ++-- HSX/events/haswellx_core.json | 4 ++-- HSX/events/haswellx_uncore.json | 20 ++++++++++---------- IVT/events/ivytown_uncore.json | 20 ++++++++++---------- JKT/events/Jaketown_uncore.json | 20 ++++++++++---------- NHM-EP/events/NehalemEP_core.json | 6 +++--- NHM-EX/events/NehalemEX_core.json | 6 +++--- README.md | 2 +- WSM-EP-DP/events/WestmereEP-DP_core.json | 6 +++--- WSM-EP-SP/events/WestmereEP-SP_core.json | 6 +++--- WSM-EX/events/WestmereEX_core.json | 6 +++--- scripts/create_perf_json.py | 8 ++++---- 17 files changed, 82 insertions(+), 82 deletions(-) diff --git a/ADL/events/alderlake_goldencove_core.json b/ADL/events/alderlake_goldencove_core.json index cbb937d6..f8c37acc 100644 --- a/ADL/events/alderlake_goldencove_core.json +++ b/ADL/events/alderlake_goldencove_core.json @@ -3132,7 +3132,7 @@ "UMask": "0x08", "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", - "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of specualtive operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction.", + "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of speculative operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction.", "Counter": "0", "PEBScounters": "0", "SampleAfterValue": "10000003", @@ -7016,4 +7016,4 @@ "Speculative": "1" } ] -} \ No newline at end of file +} diff --git a/Atom_TMA.csv b/Atom_TMA.csv index 17aa77f1..2ffb745e 100644 --- a/Atom_TMA.csv +++ b/Atom_TMA.csv @@ -32,7 +32,7 @@ BE_aux,,,Reorder_Buffer,,TOPDOWN_BE_BOUND.REORDER_BUFFER / SLOTS,,,Slots,Counts BE_aux,,,Store_Buffer,,TOPDOWN_BE_BOUND.STORE_BUFFER / SLOTS,,,Slots,Counts the number of issue slots that were not consumed by the backend due to store buffers stalls.,,>0.10 BE_aux,,,Alloc_Restriction,,TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / SLOTS,,,Slots,Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions.,,>0.10 BE_aux,,,Serialization,,TOPDOWN_BE_BOUND.SERIALIZATION / SLOTS,,,Slots,"Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).",,>0.10 -RET,Retiring,,,,TOPDOWN_RETIRING.ALL / SLOTS,UOPS_RETIRED.ANY / SLOTS ,,Slots,Counts the numer of issue slots that result in retirement slots. ,,>0.75 +RET,Retiring,,,,TOPDOWN_RETIRING.ALL / SLOTS,UOPS_RETIRED.ANY / SLOTS ,,Slots,Counts the number of issue slots that result in retirement slots. ,,>0.75 RET,,Base,,,( TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS ) / SLOTS,,,Slots,Counts the number of uops that are not from the microsequencer. ,,>0.60 RET,,,FPDIV_uops,,UOPS_RETIRED.FPDIV / SLOTS,UOPS_RETIRED.FPDIV / SLOTS,,Slots,Counts the number of floating point divide operations per uop.,,>0.20 RET,,,Other_Ret,,( TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS - UOPS_RETIRED.FPDIV ) / SLOTS,,,Slots,Counts the number of uops retired excluding ms and fp div uops.,,>0.30 @@ -47,8 +47,8 @@ Info.Core,UPI,,,,UOPS_RETIRED.ALL / INST_RETIRED.ANY,UOPS_RETIRED.ANY / INST_RET Info.L1_Bound,Store_Fwd_Blocks,,,,100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS,100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS,,,Percentage of total non-speculative loads with a store forward or unknown store address block,, Info.L1_Bound,Address_Alias_Blocks,,,,100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS,100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS,,,Percentage of total non-speculative loads with a address aliasing block,, Info.L1_Bound,Load_Splits,,,,100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS,100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS,,,Percentage of total non-speculative loads that are splits,, -Info.Inst_Mix,IpBranch,,,,INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES,INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES,,,Instructions per Branch (lower number means higher occurance rate), , -Info.Inst_Mix,IpCall,,,,INST_RETIRED.ANY / BR_INST_RETIRED.CALL,INST_RETIRED.ANY / BR_INST_RETIRED.CALL,,,Instruction per (near) call (lower number means higher occurance rate), , +Info.Inst_Mix,IpBranch,,,,INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES,INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES,,,Instructions per Branch (lower number means higher occurrence rate), , +Info.Inst_Mix,IpCall,,,,INST_RETIRED.ANY / BR_INST_RETIRED.CALL,INST_RETIRED.ANY / BR_INST_RETIRED.CALL,,,Instruction per (near) call (lower number means higher occurrence rate), , Info.Inst_Mix,IpLoad,,,,INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS,INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS,,,Instructions per Load, , Info.Inst_Mix,IpStore,,,,INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES,INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES,,,Instructions per Store, , Info.Inst_Mix,IpMispredict,,,,INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES,INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES,,,Instructions per retired Branch Misprediction, , diff --git a/BDW-DE/events/broadwellde_uncore.json b/BDW-DE/events/broadwellde_uncore.json index 9bd9c074..3f342301 100644 --- a/BDW-DE/events/broadwellde_uncore.json +++ b/BDW-DE/events/broadwellde_uncore.json @@ -5421,7 +5421,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", "BriefDescription": "UNC_I_RxR_BL_DRS_CYCLES_FULL", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5434,7 +5434,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_DRS_INSERTS", "BriefDescription": "BL Ingress Occupancy - DRS", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5447,7 +5447,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", "BriefDescription": "UNC_I_RxR_BL_DRS_OCCUPANCY", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5460,7 +5460,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", "BriefDescription": "UNC_I_RxR_BL_NCB_CYCLES_FULL", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5473,7 +5473,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCB_INSERTS", "BriefDescription": "BL Ingress Occupancy - NCB", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5486,7 +5486,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", "BriefDescription": "UNC_I_RxR_BL_NCB_OCCUPANCY", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5499,7 +5499,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", "BriefDescription": "UNC_I_RxR_BL_NCS_CYCLES_FULL", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5512,7 +5512,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCS_INSERTS", "BriefDescription": "BL Ingress Occupancy - NCS", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5525,7 +5525,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", "BriefDescription": "UNC_I_RxR_BL_NCS_OCCUPANCY", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -11708,4 +11708,4 @@ "ExtSel": "0" } ] -} \ No newline at end of file +} diff --git a/BDX/events/broadwellx_uncore.json b/BDX/events/broadwellx_uncore.json index 2a1b9e6e..d484c619 100644 --- a/BDX/events/broadwellx_uncore.json +++ b/BDX/events/broadwellx_uncore.json @@ -4654,7 +4654,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", "BriefDescription": "UNC_I_RxR_BL_DRS_CYCLES_FULL", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4667,7 +4667,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_DRS_INSERTS", "BriefDescription": "BL Ingress Occupancy - DRS", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4680,7 +4680,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", "BriefDescription": "UNC_I_RxR_BL_DRS_OCCUPANCY", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4693,7 +4693,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", "BriefDescription": "UNC_I_RxR_BL_NCB_CYCLES_FULL", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4706,7 +4706,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCB_INSERTS", "BriefDescription": "BL Ingress Occupancy - NCB", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4719,7 +4719,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", "BriefDescription": "UNC_I_RxR_BL_NCB_OCCUPANCY", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4732,7 +4732,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", "BriefDescription": "UNC_I_RxR_BL_NCS_CYCLES_FULL", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4745,7 +4745,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCS_INSERTS", "BriefDescription": "BL Ingress Occupancy - NCS", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4758,7 +4758,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", "BriefDescription": "UNC_I_RxR_BL_NCS_OCCUPANCY", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -16700,4 +16700,4 @@ "ExtSel": "0" } ] -} \ No newline at end of file +} diff --git a/E-core_TMA_Metrics.csv b/E-core_TMA_Metrics.csv index 3dc3b115..1bd0637f 100644 --- a/E-core_TMA_Metrics.csv +++ b/E-core_TMA_Metrics.csv @@ -46,7 +46,7 @@ BE_aux,,,Register,,TOPDOWN_BE_BOUND.REGISTER / SLOTS,,Slots,Counts the number of BE_aux,,,Reorder_Buffer,,TOPDOWN_BE_BOUND.REORDER_BUFFER / SLOTS,,Slots,Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls).,,>0.10 BE_aux,,,Alloc_Restriction,,TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / SLOTS,,Slots,Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions.,,>0.10 BE_aux,,,Serialization,,TOPDOWN_BE_BOUND.SERIALIZATION / SLOTS,,Slots,"Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).",,>0.10 -RET,Retiring,,,,TOPDOWN_RETIRING.ALL / SLOTS,,Slots,Counts the numer of issue slots that result in retirement slots. ,,>0.75 +RET,Retiring,,,,TOPDOWN_RETIRING.ALL / SLOTS,,Slots,Counts the number of issue slots that result in retirement slots. ,,>0.75 RET,,Base,,,( TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS ) / SLOTS,,Slots,Counts the number of uops that are not from the microsequencer. ,,>0.60 RET,,,FPDIV_uops,,UOPS_RETIRED.FPDIV / SLOTS,,Slots,Counts the number of floating point divide operations per uop.,,>0.20 RET,,,Other_Ret,,( TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS - UOPS_RETIRED.FPDIV ) / SLOTS,,Slots,Counts the number of uops retired excluding ms and fp div uops.,,>0.30 @@ -61,8 +61,8 @@ Info.Core,UPI,,,,UOPS_RETIRED.ALL / INST_RETIRED.ANY,,,Uops Per Instruction, , Info.L1_Bound,Store_Fwd_Blocks,,,,100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS,,,Percentage of total non-speculative loads with a store forward or unknown store address block,, Info.L1_Bound,Address_Alias_Blocks,,,,100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS,,,Percentage of total non-speculative loads with a address aliasing block,, Info.L1_Bound,Load_Splits,,,,100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS,,,Percentage of total non-speculative loads that are splits,, -Info.Inst_Mix,IpBranch,,,,INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES,,,Instructions per Branch (lower number means higher occurance rate), , -Info.Inst_Mix,IpCall,,,,INST_RETIRED.ANY / BR_INST_RETIRED.CALL,,,Instruction per (near) call (lower number means higher occurance rate), , +Info.Inst_Mix,IpBranch,,,,INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES,,,Instructions per Branch (lower number means higher occurrence rate), , +Info.Inst_Mix,IpCall,,,,INST_RETIRED.ANY / BR_INST_RETIRED.CALL,,,Instruction per (near) call (lower number means higher occurrence rate), , Info.Inst_Mix,IpLoad,,,,INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS,,,Instructions per Load, , Info.Inst_Mix,IpStore,,,,INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES,,,Instructions per Store, , Info.Inst_Mix,IpMispredict,,,,INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES,,,Instructions per retired Branch Misprediction, , diff --git a/HSW/events/haswell_core.json b/HSW/events/haswell_core.json index 5865b17e..cbe053ce 100644 --- a/HSW/events/haswell_core.json +++ b/HSW/events/haswell_core.json @@ -5831,7 +5831,7 @@ "UMask": "0x02", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", - "PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.", + "PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data in-flight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -8656,4 +8656,4 @@ "Deprecated": "0" } ] -} \ No newline at end of file +} diff --git a/HSX/events/haswellx_core.json b/HSX/events/haswellx_core.json index 6de610bf..c71d4e1a 100644 --- a/HSX/events/haswellx_core.json +++ b/HSX/events/haswellx_core.json @@ -6084,7 +6084,7 @@ "UMask": "0x02", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", - "PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.", + "PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data in-flight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -9272,4 +9272,4 @@ "Deprecated": "0" } ] -} \ No newline at end of file +} diff --git a/HSX/events/haswellx_uncore.json b/HSX/events/haswellx_uncore.json index a17ecf6b..270c3adb 100644 --- a/HSX/events/haswellx_uncore.json +++ b/HSX/events/haswellx_uncore.json @@ -5739,7 +5739,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", "BriefDescription": "UNC_I_RxR_BL_DRS_CYCLES_FULL", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5753,7 +5753,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_DRS_INSERTS", "BriefDescription": "BL Ingress Occupancy - DRS", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5767,7 +5767,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", "BriefDescription": "UNC_I_RxR_BL_DRS_OCCUPANCY", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5781,7 +5781,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", "BriefDescription": "UNC_I_RxR_BL_NCB_CYCLES_FULL", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5795,7 +5795,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCB_INSERTS", "BriefDescription": "BL Ingress Occupancy - NCB", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5809,7 +5809,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", "BriefDescription": "UNC_I_RxR_BL_NCB_OCCUPANCY", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5823,7 +5823,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", "BriefDescription": "UNC_I_RxR_BL_NCS_CYCLES_FULL", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5837,7 +5837,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCS_INSERTS", "BriefDescription": "BL Ingress Occupancy - NCS", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5851,7 +5851,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", "BriefDescription": "UNC_I_RxR_BL_NCS_OCCUPANCY", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -17900,4 +17900,4 @@ "EVENT_STATUS": "0" } ] -} \ No newline at end of file +} diff --git a/IVT/events/ivytown_uncore.json b/IVT/events/ivytown_uncore.json index d4a64d62..39906acc 100644 --- a/IVT/events/ivytown_uncore.json +++ b/IVT/events/ivytown_uncore.json @@ -6841,7 +6841,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", "BriefDescription": "", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x0", "Filter": "null", @@ -6853,7 +6853,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_DRS_INSERTS", "BriefDescription": "BL Ingress Occupancy - DRS", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x0", "Filter": "null", @@ -6865,7 +6865,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", "BriefDescription": "", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x0", "Filter": "null", @@ -6877,7 +6877,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", "BriefDescription": "", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x0", "Filter": "null", @@ -6889,7 +6889,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCB_INSERTS", "BriefDescription": "BL Ingress Occupancy - NCB", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x0", "Filter": "null", @@ -6901,7 +6901,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", "BriefDescription": "", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x0", "Filter": "null", @@ -6913,7 +6913,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", "BriefDescription": "", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x0", "Filter": "null", @@ -6925,7 +6925,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCS_INSERTS", "BriefDescription": "BL Ingress Occupancy - NCS", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x0", "Filter": "null", @@ -6937,7 +6937,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", "BriefDescription": "", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0x0", "Filter": "null", @@ -12896,4 +12896,4 @@ "ExtSel": "0" } ] -} \ No newline at end of file +} diff --git a/JKT/events/Jaketown_uncore.json b/JKT/events/Jaketown_uncore.json index 84320008..35f16ff8 100644 --- a/JKT/events/Jaketown_uncore.json +++ b/JKT/events/Jaketown_uncore.json @@ -6241,7 +6241,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", "BriefDescription": "tbd", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0", "Filter": "null", @@ -6253,7 +6253,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_DRS_INSERTS", "BriefDescription": "BL Ingress Occupancy - DRS", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0", "Filter": "null", @@ -6265,7 +6265,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", "BriefDescription": "tbd", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0", "Filter": "null", @@ -6277,7 +6277,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", "BriefDescription": "tbd", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0", "Filter": "null", @@ -6289,7 +6289,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCB_INSERTS", "BriefDescription": "BL Ingress Occupancy - NCB", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0", "Filter": "null", @@ -6301,7 +6301,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", "BriefDescription": "tbd", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0", "Filter": "null", @@ -6313,7 +6313,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", "BriefDescription": "tbd", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0", "Filter": "null", @@ -6325,7 +6325,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCS_INSERTS", "BriefDescription": "BL Ingress Occupancy - NCS", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0", "Filter": "null", @@ -6337,7 +6337,7 @@ "UMask": "0x0", "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", "BriefDescription": "tbd", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requests as well as outbound MMIO writes.", "Counter": "0,1", "MSRValue": "0", "Filter": "null", @@ -6488,4 +6488,4 @@ "ExtSel": "0" } ] -} \ No newline at end of file +} diff --git a/NHM-EP/events/NehalemEP_core.json b/NHM-EP/events/NehalemEP_core.json index e1dc0935..bc2b3d65 100644 --- a/NHM-EP/events/NehalemEP_core.json +++ b/NHM-EP/events/NehalemEP_core.json @@ -861,8 +861,8 @@ "EventCode": "0xF7", "UMask": "0x4", "EventName": "FP_ASSIST.INPUT", - "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)", - "PublicDescription": "X87 Floating poiint assists for invalid input value (Precise Event)", + "BriefDescription": "X87 Floating point assists for invalid input value (Precise Event)", + "PublicDescription": "X87 Floating point assists for invalid input value (Precise Event)", "Counter": "0,1,2,3", "SampleAfterValue": "20000", "MSRIndex": "0", @@ -9494,4 +9494,4 @@ "Offcore": "1" } ] -} \ No newline at end of file +} diff --git a/NHM-EX/events/NehalemEX_core.json b/NHM-EX/events/NehalemEX_core.json index 34c262e8..2803200a 100644 --- a/NHM-EX/events/NehalemEX_core.json +++ b/NHM-EX/events/NehalemEX_core.json @@ -861,8 +861,8 @@ "EventCode": "0xF7", "UMask": "0x4", "EventName": "FP_ASSIST.INPUT", - "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)", - "PublicDescription": "X87 Floating poiint assists for invalid input value (Precise Event)", + "BriefDescription": "X87 Floating point assists for invalid input value (Precise Event)", + "PublicDescription": "X87 Floating point assists for invalid input value (Precise Event)", "Counter": "0,1,2,3", "SampleAfterValue": "20000", "MSRIndex": "0", @@ -9409,4 +9409,4 @@ "Offcore": "1" } ] -} \ No newline at end of file +} diff --git a/README.md b/README.md index 94d298cf..17f22370 100644 --- a/README.md +++ b/README.md @@ -211,7 +211,7 @@ workload or tool preference. ### MSRIndex Additional MSRs may be required for programming certain events. This field gives the address of such MSRS. Potential values are: -* 0x3F6: MSR_PEBS_LD_LAT - used to configure the Load Latency Perforamnce Monitoring Facility +* 0x3F6: MSR_PEBS_LD_LAT - used to configure the Load Latency Performance Monitoring Facility * 0x1A6/0x1A7: MSR_OFFCORE_RSP_X - used to configure the offcore response events ### MSRValue diff --git a/WSM-EP-DP/events/WestmereEP-DP_core.json b/WSM-EP-DP/events/WestmereEP-DP_core.json index 5d01fd91..2a7e08c6 100644 --- a/WSM-EP-DP/events/WestmereEP-DP_core.json +++ b/WSM-EP-DP/events/WestmereEP-DP_core.json @@ -997,8 +997,8 @@ "EventCode": "0xF7", "UMask": "0x4", "EventName": "FP_ASSIST.INPUT", - "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)", - "PublicDescription": "X87 Floating poiint assists for invalid input value (Precise Event)", + "BriefDescription": "X87 Floating point assists for invalid input value (Precise Event)", + "PublicDescription": "X87 Floating point assists for invalid input value (Precise Event)", "Counter": "0,1,2,3", "SampleAfterValue": "20000", "MSRIndex": "0", @@ -9222,4 +9222,4 @@ "Offcore": "1" } ] -} \ No newline at end of file +} diff --git a/WSM-EP-SP/events/WestmereEP-SP_core.json b/WSM-EP-SP/events/WestmereEP-SP_core.json index 9740b301..0cbbc62a 100644 --- a/WSM-EP-SP/events/WestmereEP-SP_core.json +++ b/WSM-EP-SP/events/WestmereEP-SP_core.json @@ -963,8 +963,8 @@ "EventCode": "0xF7", "UMask": "0x4", "EventName": "FP_ASSIST.INPUT", - "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)", - "PublicDescription": "X87 Floating poiint assists for invalid input value (Precise Event)", + "BriefDescription": "X87 Floating point assists for invalid input value (Precise Event)", + "PublicDescription": "X87 Floating point assists for invalid input value (Precise Event)", "Counter": "0,1,2,3", "SampleAfterValue": "20000", "MSRIndex": "0", @@ -9800,4 +9800,4 @@ "Offcore": "1" } ] -} \ No newline at end of file +} diff --git a/WSM-EX/events/WestmereEX_core.json b/WSM-EX/events/WestmereEX_core.json index 8d86e6e7..f645824b 100644 --- a/WSM-EX/events/WestmereEX_core.json +++ b/WSM-EX/events/WestmereEX_core.json @@ -997,8 +997,8 @@ "EventCode": "0xF7", "UMask": "0x4", "EventName": "FP_ASSIST.INPUT", - "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)", - "PublicDescription": "X87 Floating poiint assists for invalid input value (Precise Event)", + "BriefDescription": "X87 Floating point assists for invalid input value (Precise Event)", + "PublicDescription": "X87 Floating point assists for invalid input value (Precise Event)", "Counter": "0,1,2,3", "SampleAfterValue": "20000", "MSRIndex": "0", @@ -9851,4 +9851,4 @@ "Offcore": "1" } ] -} \ No newline at end of file +} diff --git a/scripts/create_perf_json.py b/scripts/create_perf_json.py index 9afb07b0..787254b6 100644 --- a/scripts/create_perf_json.py +++ b/scripts/create_perf_json.py @@ -487,7 +487,7 @@ def __init__(self, shortname: str, longname: str, version: str, @param shortname: typically 3 letter name like SKL. @param longname: the model name like Skylake. @param version: the version number associated with the event json. - @param models: a set of model indentifier strings like "GenuineIntel-6-2E". + @param models: a set of model identifier strings like "GenuineIntel-6-2E". @param files: a mapping from a type of file to the file's path. """ self.shortname = shortname @@ -519,16 +519,16 @@ def mapfile_line(self) -> str: if len(min(self.models)) - len(prefix) > 1: start_bracket = '(' end_bracket = ')' - seperator = '|' + separator = '|' else: start_bracket = '[' end_bracket = ']' - seperator = '' + separator = '' ret = prefix + start_bracket first = True for x in self.models: if not first: - ret += seperator + ret += separator ret += x[len(prefix):] first = False ret += end_bracket From 37fcb3c3374216096557d71c5eac3d4adc90b65d Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Thu, 28 Sep 2023 13:44:23 +0100 Subject: [PATCH 2/2] Fix even spelling mistakes found using the spell tool More spelling mistakes found using the spell tool on json data. Fix these. Signed-off-by: Colin Ian King --- BDW-DE/events/broadwellde_uncore.json | 44 +++++++++--------- BDX/events/broadwellx_uncore.json | 44 +++++++++--------- CLX/events/cascadelakex_core.json | 6 +-- .../cascadelakex_uncore_experimental.json | 16 +++---- HSX/events/haswellx_uncore.json | 46 +++++++++---------- ICL/events/icelake_core.json | 6 +-- ICX/events/icelakex_core.json | 6 +-- ICX/events/icelakex_uncore.json | 4 +- ICX/events/icelakex_uncore_experimental.json | 6 +-- IVB/events/ivybridge_core.json | 26 +++++------ IVT/events/ivytown_core.json | 6 +-- IVT/events/ivytown_uncore.json | 44 +++++++++--------- JKT/events/Jaketown_core.json | 8 ++-- JKT/events/Jaketown_uncore.json | 28 +++++------ KNL/events/KnightsLanding_core.json | 6 +-- KNM/events/KnightsLanding_core.json | 6 +-- NHM-EP/events/NehalemEP_core.json | 8 ++-- NHM-EX/events/NehalemEX_core.json | 8 ++-- RKL/events/rocketlake_core.json | 6 +-- SKL/events/skylake_core.json | 4 +- SKX/events/skylakex_core.json | 6 +-- SKX/events/skylakex_uncore.json | 4 +- SKX/events/skylakex_uncore_experimental.json | 16 +++---- SNB/events/sandybridge_core.json | 8 ++-- SNR/events/snowridgex_uncore.json | 4 +- .../snowridgex_uncore_experimental.json | 6 +-- .../sapphirerapids_uncore_experimental.json | 10 ++-- TGL/events/tigerlake_core.json | 6 +-- WSM-EP-DP/events/WestmereEP-DP_core.json | 4 +- WSM-EP-SP/events/WestmereEP-SP_core.json | 8 ++-- WSM-EX/events/WestmereEX_core.json | 8 ++-- 31 files changed, 204 insertions(+), 204 deletions(-) diff --git a/BDW-DE/events/broadwellde_uncore.json b/BDW-DE/events/broadwellde_uncore.json index 3f342301..9a945d02 100644 --- a/BDW-DE/events/broadwellde_uncore.json +++ b/BDW-DE/events/broadwellde_uncore.json @@ -832,7 +832,7 @@ "UMask": "0x2", "EventName": "UNC_C_RxR_EXT_STARVED.IPQ", "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ", - "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally startved and therefore we are blocking the IRQ.", + "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally starved and therefore we are blocking the IRQ.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -2262,7 +2262,7 @@ "UMask": "0x1", "EventName": "UNC_H_BYPASS_IMC.TAKEN", "BriefDescription": "HA to iMC Bypass; Taken", - "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass.", + "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -2275,7 +2275,7 @@ "UMask": "0x2", "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN", "BriefDescription": "HA to iMC Bypass; Not Taken", - "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass.", + "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -3653,7 +3653,7 @@ "UMask": "0x1", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0", "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -3666,7 +3666,7 @@ "UMask": "0x2", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1", "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -3679,7 +3679,7 @@ "UMask": "0x4", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2", "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -3692,7 +3692,7 @@ "UMask": "0x8", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3", "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -4381,7 +4381,7 @@ "UMask": "0x1", "EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL", "BriefDescription": "Tracker Cycles Not Empty; Local Requests", - "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from the local socket.", + "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occupancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from the local socket.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -4394,7 +4394,7 @@ "UMask": "0x2", "EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE", "BriefDescription": "Tracker Cycles Not Empty; Remote Requests", - "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from remote sockets.", + "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occupancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from remote sockets.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -4407,7 +4407,7 @@ "UMask": "0x3", "EventName": "UNC_H_TRACKER_CYCLES_NE.ALL", "BriefDescription": "Tracker Cycles Not Empty; All Requests", - "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Requests coming from both local and remote sockets.", + "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occupancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Requests coming from both local and remote sockets.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -4953,7 +4953,7 @@ "UMask": "0x1", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0", "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -4966,7 +4966,7 @@ "UMask": "0x2", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1", "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -4979,7 +4979,7 @@ "UMask": "0x4", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2", "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -4992,7 +4992,7 @@ "UMask": "0x8", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3", "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -5096,7 +5096,7 @@ "UMask": "0x1", "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", "BriefDescription": "Coherent Ops; PCIRdCur", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5109,7 +5109,7 @@ "UMask": "0x2", "EventName": "UNC_I_COHERENT_OPS.CRD", "BriefDescription": "Coherent Ops; CRd", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5122,7 +5122,7 @@ "UMask": "0x4", "EventName": "UNC_I_COHERENT_OPS.DRD", "BriefDescription": "Coherent Ops; DRd", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5135,7 +5135,7 @@ "UMask": "0x8", "EventName": "UNC_I_COHERENT_OPS.RFO", "BriefDescription": "Coherent Ops; RFO", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5148,7 +5148,7 @@ "UMask": "0x10", "EventName": "UNC_I_COHERENT_OPS.PCITOM", "BriefDescription": "Coherent Ops; PCIItoM", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5161,7 +5161,7 @@ "UMask": "0x20", "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", "BriefDescription": "Coherent Ops; PCIDCAHin5t", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5174,7 +5174,7 @@ "UMask": "0x40", "EventName": "UNC_I_COHERENT_OPS.WBMTOI", "BriefDescription": "Coherent Ops; WbMtoI", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5187,7 +5187,7 @@ "UMask": "0x80", "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", "BriefDescription": "Coherent Ops; CLFlush", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", diff --git a/BDX/events/broadwellx_uncore.json b/BDX/events/broadwellx_uncore.json index d484c619..d189fe7d 100644 --- a/BDX/events/broadwellx_uncore.json +++ b/BDX/events/broadwellx_uncore.json @@ -702,7 +702,7 @@ "UMask": "0x2", "EventName": "UNC_C_RxR_EXT_STARVED.IPQ", "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ", - "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally startved and therefore we are blocking the IRQ.", + "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally starved and therefore we are blocking the IRQ.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -1976,7 +1976,7 @@ "UMask": "0x1", "EventName": "UNC_H_BYPASS_IMC.TAKEN", "BriefDescription": "HA to iMC Bypass; Taken", - "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass.", + "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -1989,7 +1989,7 @@ "UMask": "0x2", "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN", "BriefDescription": "HA to iMC Bypass; Not Taken", - "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass.", + "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -3237,7 +3237,7 @@ "UMask": "0x1", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0", "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -3250,7 +3250,7 @@ "UMask": "0x2", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1", "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -3263,7 +3263,7 @@ "UMask": "0x4", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2", "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -3276,7 +3276,7 @@ "UMask": "0x8", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3", "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -3913,7 +3913,7 @@ "UMask": "0x1", "EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL", "BriefDescription": "Tracker Cycles Not Empty; Local Requests", - "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from the local socket.", + "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occupancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from the local socket.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -3926,7 +3926,7 @@ "UMask": "0x2", "EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE", "BriefDescription": "Tracker Cycles Not Empty; Remote Requests", - "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from remote sockets.", + "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occupancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from remote sockets.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -3939,7 +3939,7 @@ "UMask": "0x3", "EventName": "UNC_H_TRACKER_CYCLES_NE.ALL", "BriefDescription": "Tracker Cycles Not Empty; All Requests", - "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Requests coming from both local and remote sockets.", + "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occupancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Requests coming from both local and remote sockets.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -4238,7 +4238,7 @@ "UMask": "0x1", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0", "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -4251,7 +4251,7 @@ "UMask": "0x2", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1", "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -4264,7 +4264,7 @@ "UMask": "0x4", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2", "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -4277,7 +4277,7 @@ "UMask": "0x8", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3", "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -4329,7 +4329,7 @@ "UMask": "0x1", "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", "BriefDescription": "Coherent Ops; PCIRdCur", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4342,7 +4342,7 @@ "UMask": "0x2", "EventName": "UNC_I_COHERENT_OPS.CRD", "BriefDescription": "Coherent Ops; CRd", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4355,7 +4355,7 @@ "UMask": "0x4", "EventName": "UNC_I_COHERENT_OPS.DRD", "BriefDescription": "Coherent Ops; DRd", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4368,7 +4368,7 @@ "UMask": "0x8", "EventName": "UNC_I_COHERENT_OPS.RFO", "BriefDescription": "Coherent Ops; RFO", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4381,7 +4381,7 @@ "UMask": "0x10", "EventName": "UNC_I_COHERENT_OPS.PCITOM", "BriefDescription": "Coherent Ops; PCIItoM", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4394,7 +4394,7 @@ "UMask": "0x20", "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", "BriefDescription": "Coherent Ops; PCIDCAHin5t", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4407,7 +4407,7 @@ "UMask": "0x40", "EventName": "UNC_I_COHERENT_OPS.WBMTOI", "BriefDescription": "Coherent Ops; WbMtoI", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4420,7 +4420,7 @@ "UMask": "0x80", "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", "BriefDescription": "Coherent Ops; CLFlush", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", diff --git a/CLX/events/cascadelakex_core.json b/CLX/events/cascadelakex_core.json index 8e89839c..06c918e8 100644 --- a/CLX/events/cascadelakex_core.json +++ b/CLX/events/cascadelakex_core.json @@ -1020,7 +1020,7 @@ "UMask": "0x20", "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", - "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture). This includes high current AVX 512-bit instructions.", + "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture). This includes high current AVX 512-bit instructions.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "200003", @@ -3060,7 +3060,7 @@ "UMask": "0x10", "EventName": "ITLB_MISSES.WALK_PENDING", "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.", - "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.", + "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake microarchitecture.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -56240,4 +56240,4 @@ "Deprecated": "0" } ] -} \ No newline at end of file +} diff --git a/CLX/events/cascadelakex_uncore_experimental.json b/CLX/events/cascadelakex_uncore_experimental.json index dad2551e..5e66940e 100644 --- a/CLX/events/cascadelakex_uncore_experimental.json +++ b/CLX/events/cascadelakex_uncore_experimental.json @@ -4408,7 +4408,7 @@ "UMaskExt": "0x00", "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", "BriefDescription": "Coherent Ops; PCIRdCur", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4426,7 +4426,7 @@ "UMaskExt": "0x00", "EventName": "UNC_I_COHERENT_OPS.CRD", "BriefDescription": "Coherent Ops; CRd", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4444,7 +4444,7 @@ "UMaskExt": "0x00", "EventName": "UNC_I_COHERENT_OPS.DRD", "BriefDescription": "Coherent Ops; DRd", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4462,7 +4462,7 @@ "UMaskExt": "0x00", "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", "BriefDescription": "Coherent Ops; PCIDCAHin5t", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4480,7 +4480,7 @@ "UMaskExt": "0x00", "EventName": "UNC_I_COHERENT_OPS.WBMTOI", "BriefDescription": "Coherent Ops; WbMtoI", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4498,7 +4498,7 @@ "UMaskExt": "0x00", "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", "BriefDescription": "Coherent Ops; CLFlush", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5182,7 +5182,7 @@ "UMaskExt": "0x00", "EventName": "UNC_I_TRANSACTIONS.WRITES", "BriefDescription": "Inbound Transaction Count; Writes", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -56438,4 +56438,4 @@ "FILTER_VALUE": "0" } ] -} \ No newline at end of file +} diff --git a/HSX/events/haswellx_uncore.json b/HSX/events/haswellx_uncore.json index 270c3adb..bab62199 100644 --- a/HSX/events/haswellx_uncore.json +++ b/HSX/events/haswellx_uncore.json @@ -895,7 +895,7 @@ "UMask": "0x2", "EventName": "UNC_C_RxR_EXT_STARVED.IPQ", "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ", - "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally startved and therefore we are blocking the IRQ.", + "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally starved and therefore we are blocking the IRQ.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -2421,7 +2421,7 @@ "UMask": "0x1", "EventName": "UNC_H_BYPASS_IMC.TAKEN", "BriefDescription": "HA to iMC Bypass; Taken", - "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass.", + "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -2435,7 +2435,7 @@ "UMask": "0x2", "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN", "BriefDescription": "HA to iMC Bypass; Not Taken", - "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass.", + "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -3891,7 +3891,7 @@ "UMask": "0x1", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0", "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -3905,7 +3905,7 @@ "UMask": "0x2", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1", "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -3919,7 +3919,7 @@ "UMask": "0x4", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2", "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -3933,7 +3933,7 @@ "UMask": "0x8", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3", "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -5249,7 +5249,7 @@ "UMask": "0x1", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0", "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -5263,7 +5263,7 @@ "UMask": "0x2", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1", "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -5277,7 +5277,7 @@ "UMask": "0x4", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2", "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -5291,7 +5291,7 @@ "UMask": "0x8", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3", "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -5403,7 +5403,7 @@ "UMask": "0x1", "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", "BriefDescription": "Coherent Ops; PCIRdCur", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5417,7 +5417,7 @@ "UMask": "0x2", "EventName": "UNC_I_COHERENT_OPS.CRD", "BriefDescription": "Coherent Ops; CRd", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5431,7 +5431,7 @@ "UMask": "0x4", "EventName": "UNC_I_COHERENT_OPS.DRD", "BriefDescription": "Coherent Ops; DRd", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5445,7 +5445,7 @@ "UMask": "0x8", "EventName": "UNC_I_COHERENT_OPS.RFO", "BriefDescription": "Coherent Ops; RFO", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5459,7 +5459,7 @@ "UMask": "0x10", "EventName": "UNC_I_COHERENT_OPS.PCITOM", "BriefDescription": "Coherent Ops; PCIItoM", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5473,7 +5473,7 @@ "UMask": "0x20", "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", "BriefDescription": "Coherent Ops; PCIDCAHin5t", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5487,7 +5487,7 @@ "UMask": "0x40", "EventName": "UNC_I_COHERENT_OPS.WBMTOI", "BriefDescription": "Coherent Ops; WbMtoI", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5501,7 +5501,7 @@ "UMask": "0x80", "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", "BriefDescription": "Coherent Ops; CLFlush", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5977,7 +5977,7 @@ "UMask": "0x2", "EventName": "UNC_I_TRANSACTIONS.WRITES", "BriefDescription": "Inbound Transaction Count; Writes", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -17793,7 +17793,7 @@ "UMask": "0x1", "EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL", "BriefDescription": "Tracker Cycles Not Empty; Local Requests", - "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from the local socket.", + "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occupancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from the local socket.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -17807,7 +17807,7 @@ "UMask": "0x2", "EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE", "BriefDescription": "Tracker Cycles Not Empty; Remote Requests", - "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from remote sockets.", + "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occupancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from remote sockets.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -17821,7 +17821,7 @@ "UMask": "0x3", "EventName": "UNC_H_TRACKER_CYCLES_NE.ALL", "BriefDescription": "Tracker Cycles Not Empty; All Requests", - "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Requests coming from both local and remote sockets.", + "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occupancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Requests coming from both local and remote sockets.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", diff --git a/ICL/events/icelake_core.json b/ICL/events/icelake_core.json index 344dc22f..a3a93631 100644 --- a/ICL/events/icelake_core.json +++ b/ICL/events/icelake_core.json @@ -972,7 +972,7 @@ "UMask": "0x20", "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", - "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.", + "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture). This includes high current AVX 512-bit instructions.", "Counter": "0,1,2,3", "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", @@ -1812,7 +1812,7 @@ "UMask": "0x01", "EventName": "RS_EVENTS.EMPTY_CYCLES", "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", - "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)", + "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", @@ -8144,4 +8144,4 @@ "Speculative": "1" } ] -} \ No newline at end of file +} diff --git a/ICX/events/icelakex_core.json b/ICX/events/icelakex_core.json index 5aff65a1..59ab9dde 100644 --- a/ICX/events/icelakex_core.json +++ b/ICX/events/icelakex_core.json @@ -924,7 +924,7 @@ "UMask": "0x20", "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", - "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.", + "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture). This includes high current AVX 512-bit instructions.", "Counter": "0,1,2,3", "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", @@ -1692,7 +1692,7 @@ "UMask": "0x01", "EventName": "RS_EVENTS.EMPTY_CYCLES", "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", - "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)", + "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", @@ -8648,4 +8648,4 @@ "Speculative": "0" } ] -} \ No newline at end of file +} diff --git a/ICX/events/icelakex_uncore.json b/ICX/events/icelakex_uncore.json index 1966f4f6..7d644ccc 100644 --- a/ICX/events/icelakex_uncore.json +++ b/ICX/events/icelakex_uncore.json @@ -1612,7 +1612,7 @@ "UMaskExt": "0x00", "EventName": "UNC_I_COHERENT_OPS.WBMTOI", "BriefDescription": "Coherent Ops : WbMtoI", - "PublicDescription": "Coherent Ops : WbMtoI : Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Coherent Ops : WbMtoI : Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5081,4 +5081,4 @@ "CounterType": "PGMABLE" } ] -} \ No newline at end of file +} diff --git a/ICX/events/icelakex_uncore_experimental.json b/ICX/events/icelakex_uncore_experimental.json index 797b4863..63f19f13 100644 --- a/ICX/events/icelakex_uncore_experimental.json +++ b/ICX/events/icelakex_uncore_experimental.json @@ -10409,7 +10409,7 @@ "UMaskExt": "0x00", "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", "BriefDescription": "Coherent Ops : CLFlush", - "PublicDescription": "Coherent Ops : CLFlush : Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Coherent Ops : CLFlush : Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -10998,7 +10998,7 @@ "UMaskExt": "0x00", "EventName": "UNC_I_TRANSACTIONS.WRITES", "BriefDescription": "Inbound Transaction Count : Writes", - "PublicDescription": "Inbound Transaction Count : Writes : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", + "PublicDescription": "Inbound Transaction Count : Writes : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -70726,4 +70726,4 @@ "CounterType": "PGMABLE" } ] -} \ No newline at end of file +} diff --git a/IVB/events/ivybridge_core.json b/IVB/events/ivybridge_core.json index 667c1aa3..5389e6cc 100644 --- a/IVB/events/ivybridge_core.json +++ b/IVB/events/ivybridge_core.json @@ -1250,7 +1250,7 @@ "EventCode": "0x48", "UMask": "0x01", "EventName": "L1D_PEND_MISS.PENDING", - "BriefDescription": "L1D miss oustandings duration in cycles", + "BriefDescription": "L1D miss outstandings duration in cycles", "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", "Counter": "2", "CounterHTOff": "2", @@ -1313,8 +1313,8 @@ "EventCode": "0x48", "UMask": "0x02", "EventName": "L1D_PEND_MISS.FB_FULL", - "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability", - "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability", + "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -2048,7 +2048,7 @@ "EventCode": "0x79", "UMask": "0x10", "EventName": "IDQ.MS_DSB_UOPS", - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", @@ -2069,8 +2069,8 @@ "EventCode": "0x79", "UMask": "0x10", "EventName": "IDQ.MS_DSB_CYCLES", - "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -2090,8 +2090,8 @@ "EventCode": "0x79", "UMask": "0x10", "EventName": "IDQ.MS_DSB_OCCUR", - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", - "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy", + "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -2153,7 +2153,7 @@ "EventCode": "0x79", "UMask": "0x20", "EventName": "IDQ.MS_MITE_UOPS", - "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", @@ -2216,7 +2216,7 @@ "EventCode": "0x79", "UMask": "0x30", "EventName": "IDQ.MS_UOPS", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", @@ -2237,8 +2237,8 @@ "EventCode": "0x79", "UMask": "0x30", "EventName": "IDQ.MS_CYCLES", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -6686,4 +6686,4 @@ "Offcore": "1" } ] -} \ No newline at end of file +} diff --git a/IVT/events/ivytown_core.json b/IVT/events/ivytown_core.json index 87355bf1..1add6d6a 100644 --- a/IVT/events/ivytown_core.json +++ b/IVT/events/ivytown_core.json @@ -1355,8 +1355,8 @@ "EventCode": "0x48", "UMask": "0x02", "EventName": "L1D_PEND_MISS.FB_FULL", - "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability", - "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability", + "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -7484,4 +7484,4 @@ "Offcore": "1" } ] -} \ No newline at end of file +} diff --git a/IVT/events/ivytown_uncore.json b/IVT/events/ivytown_uncore.json index 39906acc..a0012b33 100644 --- a/IVT/events/ivytown_uncore.json +++ b/IVT/events/ivytown_uncore.json @@ -649,7 +649,7 @@ "UMask": "0x2", "EventName": "UNC_C_RxR_EXT_STARVED.IPQ", "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ", - "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally startved and therefore we are blocking the IRQ.", + "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally starved and therefore we are blocking the IRQ.", "Counter": "0,1", "MSRValue": "0x0", "Filter": "null", @@ -2041,7 +2041,7 @@ "UMask": "0x2", "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN", "BriefDescription": "HA to iMC Bypass; Not Taken", - "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass.", + "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass.", "Counter": "0,1,2,3", "MSRValue": "0x0", "Filter": "null", @@ -2053,7 +2053,7 @@ "UMask": "0x1", "EventName": "UNC_H_BYPASS_IMC.TAKEN", "BriefDescription": "HA to iMC Bypass; Taken", - "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass.", + "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass.", "Counter": "0,1,2,3", "MSRValue": "0x0", "Filter": "null", @@ -3037,7 +3037,7 @@ "UMask": "0x1", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0", "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.", "Counter": "0,1,2,3", "MSRValue": "0x0", "Filter": "null", @@ -3049,7 +3049,7 @@ "UMask": "0x2", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1", "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.", "Counter": "0,1,2,3", "MSRValue": "0x0", "Filter": "null", @@ -3061,7 +3061,7 @@ "UMask": "0x4", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2", "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.", "Counter": "0,1,2,3", "MSRValue": "0x0", "Filter": "null", @@ -3073,7 +3073,7 @@ "UMask": "0x8", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3", "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.", "Counter": "0,1,2,3", "MSRValue": "0x0", "Filter": "null", @@ -3457,7 +3457,7 @@ "UMask": "0x0", "EventName": "UNC_H_TRACKER_CYCLES_NE", "BriefDescription": "Tracker Cycles Not Empty", - "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.", + "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occupancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.", "Counter": "0,1,2,3", "MSRValue": "0x0", "Filter": "null", @@ -3925,7 +3925,7 @@ "UMask": "0x1", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0", "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.", "Counter": "0,1,2,3", "MSRValue": "0x0", "Filter": "null", @@ -3937,7 +3937,7 @@ "UMask": "0x2", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1", "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.", "Counter": "0,1,2,3", "MSRValue": "0x0", "Filter": "null", @@ -3949,7 +3949,7 @@ "UMask": "0x4", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2", "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.", "Counter": "0,1,2,3", "MSRValue": "0x0", "Filter": "null", @@ -3961,7 +3961,7 @@ "UMask": "0x8", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3", "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3", - "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.", + "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.", "Counter": "0,1,2,3", "MSRValue": "0x0", "Filter": "null", @@ -6673,7 +6673,7 @@ "UMask": "0x1", "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.ANY", "BriefDescription": "Write Ack Pending Occupancy; Any Source", - "PublicDescription": "Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time.", + "PublicDescription": "Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occupancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time.", "Counter": "0,1", "MSRValue": "0x0", "Filter": "null", @@ -6685,7 +6685,7 @@ "UMask": "0x2", "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.SOURCE", "BriefDescription": "Write Ack Pending Occupancy; Select Source", - "PublicDescription": "Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements.; Tracks all requests from any source port.", + "PublicDescription": "Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occupancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements.; Tracks all requests from any source port.", "Counter": "0,1", "MSRValue": "0x0", "Filter": "null", @@ -7009,7 +7009,7 @@ "UMask": "0x2", "EventName": "UNC_I_TRANSACTIONS.WRITES", "BriefDescription": "Inbound Transaction Count; Writes", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", "Counter": "0,1", "MSRValue": "0x0", "Filter": "null", @@ -7069,7 +7069,7 @@ "UMask": "0x0", "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", "BriefDescription": "Outbound Request Queue Occupancy", - "PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.", + "PublicDescription": "Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", "Counter": "0,1", "MSRValue": "0x0", "Filter": "null", @@ -10777,7 +10777,7 @@ "UMask": "0xCC", "EventName": "UNC_R2_RING_IV_USED.CCW", "BriefDescription": "R2 IV Ring in Use; Counterclockwise", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Therefore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity", "Counter": "0,1,2,3", "MSRValue": "0x0", "Filter": "null", @@ -10789,7 +10789,7 @@ "UMask": "0x33", "EventName": "UNC_R2_RING_IV_USED.CW", "BriefDescription": "R2 IV Ring in Use; Clockwise", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Clockwise polarity", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Therefore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Clockwise polarity", "Counter": "0,1,2,3", "MSRValue": "0x0", "Filter": "null", @@ -11017,7 +11017,7 @@ "UMask": "0xFF", "EventName": "UNC_R2_RING_IV_USED.ANY", "BriefDescription": "R2 IV Ring in Use; Any", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Therefore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity", "Counter": "0,1,2,3", "MSRValue": "0", "Filter": "null", @@ -11845,7 +11845,7 @@ "UMask": "0xCC", "EventName": "UNC_R3_RING_IV_USED.CCW", "BriefDescription": "R2 IV Ring in Use; Counterclockwise", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Therefore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity", "Counter": "0,1,2", "MSRValue": "0x0", "Filter": "null", @@ -11857,7 +11857,7 @@ "UMask": "0x33", "EventName": "UNC_R3_RING_IV_USED.CW", "BriefDescription": "R2 IV Ring in Use; Clockwise", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Clockwise polarity", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Therefore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Clockwise polarity", "Counter": "0,1,2", "MSRValue": "0x0", "Filter": "null", @@ -12601,7 +12601,7 @@ "UMask": "0xFF", "EventName": "UNC_R3_RING_IV_USED.ANY", "BriefDescription": "R2 IV Ring in Use; Any", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Therefore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity", "Counter": "0,1,2", "MSRValue": "0", "Filter": "null", diff --git a/JKT/events/Jaketown_core.json b/JKT/events/Jaketown_core.json index b4b4acd3..bbb64304 100644 --- a/JKT/events/Jaketown_core.json +++ b/JKT/events/Jaketown_core.json @@ -600,7 +600,7 @@ "UMask": "0x02", "EventName": "ICACHE.MISSES", "BriefDescription": "Instruction cache, streaming buffer and victim cache misses.", - "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.", + "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes uncacheable accesses.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "200003", @@ -1062,7 +1062,7 @@ "UMask": "0x40", "EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", "BriefDescription": "Cycles with at least one slow LEA uop being allocated.", - "PublicDescription": "This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.", + "PublicDescription": "This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index registers, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -1230,7 +1230,7 @@ "UMask": "0x01", "EventName": "UOPS_ISSUED.ANY", "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS).", - "PublicDescription": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.", + "PublicDescription": "This event counts the number of Uops issued by the front-end of the pipeline to the back-end.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -7442,4 +7442,4 @@ "Offcore": "1" } ] -} \ No newline at end of file +} diff --git a/JKT/events/Jaketown_uncore.json b/JKT/events/Jaketown_uncore.json index 35f16ff8..40a7257b 100644 --- a/JKT/events/Jaketown_uncore.json +++ b/JKT/events/Jaketown_uncore.json @@ -3193,7 +3193,7 @@ "UMask": "0xf", "EventName": "UNC_R3_RING_IV_USED.ANY", "BriefDescription": "R3 IV Ring in Use; Any", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Therefore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.", "Counter": "0,1,2", "MSRValue": "0", "Filter": "null", @@ -3949,7 +3949,7 @@ "UMask": "0xf", "EventName": "UNC_R2_RING_IV_USED.ANY", "BriefDescription": "R2 IV Ring in Use; Any", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Therefore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.", "Counter": "0,1,2,3", "MSRValue": "0", "Filter": "null", @@ -4129,7 +4129,7 @@ "UMask": "0x2", "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN", "BriefDescription": "HA to iMC Bypass; Not Taken", - "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.", + "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.", "Counter": "0,1,2,3", "MSRValue": "0", "Filter": "null", @@ -4141,7 +4141,7 @@ "UMask": "0x1", "EventName": "UNC_H_BYPASS_IMC.TAKEN", "BriefDescription": "HA to iMC Bypass; Taken", - "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.", + "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.", "Counter": "0,1,2,3", "MSRValue": "0", "Filter": "null", @@ -4573,7 +4573,7 @@ "UMask": "0x1", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0", "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0", - "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.", + "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.", "Counter": "0,1,2,3", "MSRValue": "0", "Filter": "null", @@ -4585,7 +4585,7 @@ "UMask": "0x2", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1", "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1", - "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.", + "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.", "Counter": "0,1,2,3", "MSRValue": "0", "Filter": "null", @@ -4597,7 +4597,7 @@ "UMask": "0x4", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2", "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2", - "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.", + "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.", "Counter": "0,1,2,3", "MSRValue": "0", "Filter": "null", @@ -4609,7 +4609,7 @@ "UMask": "0x8", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3", "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3", - "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.", + "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.", "Counter": "0,1,2,3", "MSRValue": "0", "Filter": "null", @@ -5329,7 +5329,7 @@ "UMask": "0x1", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0", "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0", - "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.", + "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.", "Counter": "0,1,2,3", "MSRValue": "0", "Filter": "null", @@ -5341,7 +5341,7 @@ "UMask": "0x2", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1", "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1", - "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.", + "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.", "Counter": "0,1,2,3", "MSRValue": "0", "Filter": "null", @@ -5353,7 +5353,7 @@ "UMask": "0x4", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2", "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2", - "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.", + "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.", "Counter": "0,1,2,3", "MSRValue": "0", "Filter": "null", @@ -5365,7 +5365,7 @@ "UMask": "0x8", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3", "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3", - "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.", + "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes. This count only tracks the regular credits Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.", "Counter": "0,1,2,3", "MSRValue": "0", "Filter": "null", @@ -6073,7 +6073,7 @@ "UMask": "0x1", "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.ANY", "BriefDescription": "Write Ack Pending Occupancy; Any Source", - "PublicDescription": "Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements.", + "PublicDescription": "Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occupancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements.", "Counter": "0,1", "MSRValue": "0", "Filter": "null", @@ -6085,7 +6085,7 @@ "UMask": "0x2", "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.SOURCE", "BriefDescription": "Write Ack Pending Occupancy; Select Source", - "PublicDescription": "Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements.", + "PublicDescription": "Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occupancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements.", "Counter": "0,1", "MSRValue": "0", "Filter": "null", diff --git a/KNL/events/KnightsLanding_core.json b/KNL/events/KnightsLanding_core.json index d16ac7da..ee4bee25 100644 --- a/KNL/events/KnightsLanding_core.json +++ b/KNL/events/KnightsLanding_core.json @@ -751,8 +751,8 @@ "EventCode": "0x30", "UMask": "0x00", "EventName": "L2_REQUESTS_REJECT.ALL", - "BriefDescription": "Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) excluding SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times", - "PublicDescription": "Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) excluding SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times", + "BriefDescription": "Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) excluding SW prefetches filling only to L2 cache and L1 evictions (automatically excludes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times", + "PublicDescription": "Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) excluding SW prefetches filling only to L2 cache and L1 evictions (automatically excludes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times", "Counter": "0,1", "PEBScounters": "0", "SampleAfterValue": "200003", @@ -7488,4 +7488,4 @@ "Offcore": "1" } ] -} \ No newline at end of file +} diff --git a/KNM/events/KnightsLanding_core.json b/KNM/events/KnightsLanding_core.json index d16ac7da..ee4bee25 100644 --- a/KNM/events/KnightsLanding_core.json +++ b/KNM/events/KnightsLanding_core.json @@ -751,8 +751,8 @@ "EventCode": "0x30", "UMask": "0x00", "EventName": "L2_REQUESTS_REJECT.ALL", - "BriefDescription": "Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) excluding SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times", - "PublicDescription": "Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) excluding SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times", + "BriefDescription": "Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) excluding SW prefetches filling only to L2 cache and L1 evictions (automatically excludes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times", + "PublicDescription": "Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) excluding SW prefetches filling only to L2 cache and L1 evictions (automatically excludes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times", "Counter": "0,1", "PEBScounters": "0", "SampleAfterValue": "200003", @@ -7488,4 +7488,4 @@ "Offcore": "1" } ] -} \ No newline at end of file +} diff --git a/NHM-EP/events/NehalemEP_core.json b/NHM-EP/events/NehalemEP_core.json index bc2b3d65..e870b8ab 100644 --- a/NHM-EP/events/NehalemEP_core.json +++ b/NHM-EP/events/NehalemEP_core.json @@ -113,8 +113,8 @@ "EventCode": "0xE8", "UMask": "0x1", "EventName": "BPU_CLEARS.EARLY", - "BriefDescription": "Early Branch Prediciton Unit clears", - "PublicDescription": "Early Branch Prediciton Unit clears", + "BriefDescription": "Early Branch Prediction Unit clears", + "PublicDescription": "Early Branch Prediction Unit clears", "Counter": "0,1,2,3", "SampleAfterValue": "2000000", "MSRIndex": "0", @@ -2119,8 +2119,8 @@ "EventCode": "0xF1", "UMask": "0x7", "EventName": "L2_LINES_IN.ANY", - "BriefDescription": "L2 lines alloacated", - "PublicDescription": "L2 lines alloacated", + "BriefDescription": "L2 lines allocated", + "PublicDescription": "L2 lines allocated", "Counter": "0,1,2,3", "SampleAfterValue": "100000", "MSRIndex": "0", diff --git a/NHM-EX/events/NehalemEX_core.json b/NHM-EX/events/NehalemEX_core.json index 2803200a..31b89356 100644 --- a/NHM-EX/events/NehalemEX_core.json +++ b/NHM-EX/events/NehalemEX_core.json @@ -113,8 +113,8 @@ "EventCode": "0xE8", "UMask": "0x1", "EventName": "BPU_CLEARS.EARLY", - "BriefDescription": "Early Branch Prediciton Unit clears", - "PublicDescription": "Early Branch Prediciton Unit clears", + "BriefDescription": "Early Branch Prediction Unit clears", + "PublicDescription": "Early Branch Prediction Unit clears", "Counter": "0,1,2,3", "SampleAfterValue": "2000000", "MSRIndex": "0", @@ -2119,8 +2119,8 @@ "EventCode": "0xF1", "UMask": "0x7", "EventName": "L2_LINES_IN.ANY", - "BriefDescription": "L2 lines alloacated", - "PublicDescription": "L2 lines alloacated", + "BriefDescription": "L2 lines allocated", + "PublicDescription": "L2 lines allocated", "Counter": "0,1,2,3", "SampleAfterValue": "100000", "MSRIndex": "0", diff --git a/RKL/events/rocketlake_core.json b/RKL/events/rocketlake_core.json index e2f30288..2cd69eb4 100644 --- a/RKL/events/rocketlake_core.json +++ b/RKL/events/rocketlake_core.json @@ -972,7 +972,7 @@ "UMask": "0x20", "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", - "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.", + "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture). This includes high current AVX 512-bit instructions.", "Counter": "0,1,2,3", "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", @@ -1812,7 +1812,7 @@ "UMask": "0x01", "EventName": "RS_EVENTS.EMPTY_CYCLES", "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", - "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)", + "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", @@ -8144,4 +8144,4 @@ "Speculative": "1" } ] -} \ No newline at end of file +} diff --git a/SKL/events/skylake_core.json b/SKL/events/skylake_core.json index fed87fcb..c81a30ca 100644 --- a/SKL/events/skylake_core.json +++ b/SKL/events/skylake_core.json @@ -2864,7 +2864,7 @@ "UMask": "0x10", "EventName": "ITLB_MISSES.WALK_PENDING", "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.", - "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.", + "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake microarchitecture.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -12957,4 +12957,4 @@ "Deprecated": "0" } ] -} \ No newline at end of file +} diff --git a/SKX/events/skylakex_core.json b/SKX/events/skylakex_core.json index 83885546..719d295b 100644 --- a/SKX/events/skylakex_core.json +++ b/SKX/events/skylakex_core.json @@ -1044,7 +1044,7 @@ "UMask": "0x20", "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", - "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture). This includes high current AVX 512-bit instructions.", + "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture). This includes high current AVX 512-bit instructions.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "200003", @@ -3084,7 +3084,7 @@ "UMask": "0x10", "EventName": "ITLB_MISSES.WALK_PENDING", "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.", - "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.", + "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake microarchitecture.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", @@ -11240,4 +11240,4 @@ "Deprecated": "0" } ] -} \ No newline at end of file +} diff --git a/SKX/events/skylakex_uncore.json b/SKX/events/skylakex_uncore.json index ae462918..615dc1c4 100644 --- a/SKX/events/skylakex_uncore.json +++ b/SKX/events/skylakex_uncore.json @@ -502,7 +502,7 @@ "UMaskExt": "0x00", "EventName": "UNC_IIO_CLOCKTICKS", "BriefDescription": "Clockticks of the IIO Traffic Controller", - "PublicDescription": "Counts clockticks of the 1GHz trafiic controller clock in the IIO unit.", + "PublicDescription": "Counts clockticks of the 1GHz traffic controller clock in the IIO unit.", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -4832,4 +4832,4 @@ "FILTER_VALUE": "0" } ] -} \ No newline at end of file +} diff --git a/SKX/events/skylakex_uncore_experimental.json b/SKX/events/skylakex_uncore_experimental.json index 30f13e8a..aea1655a 100644 --- a/SKX/events/skylakex_uncore_experimental.json +++ b/SKX/events/skylakex_uncore_experimental.json @@ -4408,7 +4408,7 @@ "UMaskExt": "0x00", "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", "BriefDescription": "Coherent Ops; PCIRdCur", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4426,7 +4426,7 @@ "UMaskExt": "0x00", "EventName": "UNC_I_COHERENT_OPS.CRD", "BriefDescription": "Coherent Ops; CRd", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4444,7 +4444,7 @@ "UMaskExt": "0x00", "EventName": "UNC_I_COHERENT_OPS.DRD", "BriefDescription": "Coherent Ops; DRd", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4462,7 +4462,7 @@ "UMaskExt": "0x00", "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", "BriefDescription": "Coherent Ops; PCIDCAHin5t", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4480,7 +4480,7 @@ "UMaskExt": "0x00", "EventName": "UNC_I_COHERENT_OPS.WBMTOI", "BriefDescription": "Coherent Ops; WbMtoI", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -4498,7 +4498,7 @@ "UMaskExt": "0x00", "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", "BriefDescription": "Coherent Ops; CLFlush", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -5182,7 +5182,7 @@ "UMaskExt": "0x00", "EventName": "UNC_I_TRANSACTIONS.WRITES", "BriefDescription": "Inbound Transaction Count; Writes", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -54728,4 +54728,4 @@ "FILTER_VALUE": "0" } ] -} \ No newline at end of file +} diff --git a/SNB/events/sandybridge_core.json b/SNB/events/sandybridge_core.json index eaa2eb85..0d1f5eaf 100644 --- a/SNB/events/sandybridge_core.json +++ b/SNB/events/sandybridge_core.json @@ -432,7 +432,7 @@ "UMask": "0x01", "EventName": "UOPS_ISSUED.ANY", "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS).", - "PublicDescription": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.", + "PublicDescription": "This event counts the number of Uops issued by the front-end of the pipeline to the back-end.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -1713,7 +1713,7 @@ "UMask": "0x40", "EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", "BriefDescription": "Cycles with at least one slow LEA uop being allocated.", - "PublicDescription": "This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.", + "PublicDescription": "This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index registers, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", @@ -2511,7 +2511,7 @@ "UMask": "0x02", "EventName": "ICACHE.MISSES", "BriefDescription": "Instruction cache, streaming buffer and victim cache misses.", - "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.", + "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes uncacheable accesses.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "SampleAfterValue": "200003", @@ -8555,4 +8555,4 @@ "Offcore": "1" } ] -} \ No newline at end of file +} diff --git a/SNR/events/snowridgex_uncore.json b/SNR/events/snowridgex_uncore.json index 7aa2a2ae..40fbef24 100644 --- a/SNR/events/snowridgex_uncore.json +++ b/SNR/events/snowridgex_uncore.json @@ -1365,7 +1365,7 @@ "UMaskExt": "0x00", "EventName": "UNC_I_COHERENT_OPS.WBMTOI", "BriefDescription": "Coherent Ops : WbMtoI", - "PublicDescription": "Coherent Ops : WbMtoI : Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Coherent Ops : WbMtoI : Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -3941,4 +3941,4 @@ "CounterType": "PGMABLE" } ] -} \ No newline at end of file +} diff --git a/SNR/events/snowridgex_uncore_experimental.json b/SNR/events/snowridgex_uncore_experimental.json index b868fbf7..b396f5ee 100644 --- a/SNR/events/snowridgex_uncore_experimental.json +++ b/SNR/events/snowridgex_uncore_experimental.json @@ -8205,7 +8205,7 @@ "UMaskExt": "0x00", "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", "BriefDescription": "Coherent Ops : CLFlush", - "PublicDescription": "Coherent Ops : CLFlush : Counts the number of coherency related operations servied by the IRP", + "PublicDescription": "Coherent Ops : CLFlush : Counts the number of coherency related operations serviced by the IRP", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -8794,7 +8794,7 @@ "UMaskExt": "0x00", "EventName": "UNC_I_TRANSACTIONS.WRITES", "BriefDescription": "Inbound Transaction Count : Writes", - "PublicDescription": "Inbound Transaction Count : Writes : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", + "PublicDescription": "Inbound Transaction Count : Writes : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", "Counter": "0,1", "MSRValue": "0x00", "ELLC": "0", @@ -44031,4 +44031,4 @@ "CounterType": "PGMABLE" } ] -} \ No newline at end of file +} diff --git a/SPR/events/sapphirerapids_uncore_experimental.json b/SPR/events/sapphirerapids_uncore_experimental.json index 5351180f..aeb23420 100644 --- a/SPR/events/sapphirerapids_uncore_experimental.json +++ b/SPR/events/sapphirerapids_uncore_experimental.json @@ -13049,8 +13049,8 @@ "FCMask": "0x00", "UMaskExt": "0x00000000", "EventName": "UNC_MDF_CRS_TxR_INSERTS.AD_BNC", - "BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (AD Bouncable)", - "PublicDescription": "AD Bouncable : Number of allocations into the CRS Egress", + "BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (AD Bounceable)", + "PublicDescription": "AD Bounceable : Number of allocations into the CRS Egress", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -13087,8 +13087,8 @@ "FCMask": "0x00", "UMaskExt": "0x00000000", "EventName": "UNC_MDF_CRS_TxR_INSERTS.BL_BNC", - "BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (BL Bouncable)", - "PublicDescription": "BL Bouncable : Number of allocations into the CRS Egress", + "BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (BL Bounceable)", + "PublicDescription": "BL Bounceable : Number of allocations into the CRS Egress", "Counter": "0,1,2,3", "MSRValue": "0x00", "ELLC": "0", @@ -38236,4 +38236,4 @@ "CounterType": "PGMABLE" } ] -} \ No newline at end of file +} diff --git a/TGL/events/tigerlake_core.json b/TGL/events/tigerlake_core.json index 710a2bf6..846b752f 100644 --- a/TGL/events/tigerlake_core.json +++ b/TGL/events/tigerlake_core.json @@ -924,7 +924,7 @@ "UMask": "0x20", "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", - "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.", + "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture). This includes high current AVX 512-bit instructions.", "Counter": "0,1,2,3", "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", @@ -1644,7 +1644,7 @@ "UMask": "0x01", "EventName": "RS_EVENTS.EMPTY_CYCLES", "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", - "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)", + "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", @@ -6248,4 +6248,4 @@ "Speculative": "1" } ] -} \ No newline at end of file +} diff --git a/WSM-EP-DP/events/WestmereEP-DP_core.json b/WSM-EP-DP/events/WestmereEP-DP_core.json index 2a7e08c6..586a7dc2 100644 --- a/WSM-EP-DP/events/WestmereEP-DP_core.json +++ b/WSM-EP-DP/events/WestmereEP-DP_core.json @@ -113,8 +113,8 @@ "EventCode": "0xE8", "UMask": "0x1", "EventName": "BPU_CLEARS.EARLY", - "BriefDescription": "Early Branch Prediciton Unit clears", - "PublicDescription": "Early Branch Prediciton Unit clears", + "BriefDescription": "Early Branch Prediction Unit clears", + "PublicDescription": "Early Branch Prediction Unit clears", "Counter": "0,1,2,3", "SampleAfterValue": "2000000", "MSRIndex": "0", diff --git a/WSM-EP-SP/events/WestmereEP-SP_core.json b/WSM-EP-SP/events/WestmereEP-SP_core.json index 0cbbc62a..9f67e5a4 100644 --- a/WSM-EP-SP/events/WestmereEP-SP_core.json +++ b/WSM-EP-SP/events/WestmereEP-SP_core.json @@ -113,8 +113,8 @@ "EventCode": "0xE8", "UMask": "0x1", "EventName": "BPU_CLEARS.EARLY", - "BriefDescription": "Early Branch Prediciton Unit clears", - "PublicDescription": "Early Branch Prediciton Unit clears", + "BriefDescription": "Early Branch Prediction Unit clears", + "PublicDescription": "Early Branch Prediction Unit clears", "Counter": "0,1,2,3", "SampleAfterValue": "2000000", "MSRIndex": "0", @@ -1983,8 +1983,8 @@ "EventCode": "0xF1", "UMask": "0x7", "EventName": "L2_LINES_IN.ANY", - "BriefDescription": "L2 lines alloacated", - "PublicDescription": "L2 lines alloacated", + "BriefDescription": "L2 lines allocated", + "PublicDescription": "L2 lines allocated", "Counter": "0,1,2,3", "SampleAfterValue": "100000", "MSRIndex": "0", diff --git a/WSM-EX/events/WestmereEX_core.json b/WSM-EX/events/WestmereEX_core.json index f645824b..4e71e3ba 100644 --- a/WSM-EX/events/WestmereEX_core.json +++ b/WSM-EX/events/WestmereEX_core.json @@ -113,8 +113,8 @@ "EventCode": "0xE8", "UMask": "0x1", "EventName": "BPU_CLEARS.EARLY", - "BriefDescription": "Early Branch Prediciton Unit clears", - "PublicDescription": "Early Branch Prediciton Unit clears", + "BriefDescription": "Early Branch Prediction Unit clears", + "PublicDescription": "Early Branch Prediction Unit clears", "Counter": "0,1,2,3", "SampleAfterValue": "2000000", "MSRIndex": "0", @@ -2034,8 +2034,8 @@ "EventCode": "0xF1", "UMask": "0x7", "EventName": "L2_LINES_IN.ANY", - "BriefDescription": "L2 lines alloacated", - "PublicDescription": "L2 lines alloacated", + "BriefDescription": "L2 lines allocated", + "PublicDescription": "L2 lines allocated", "Counter": "0,1,2,3", "SampleAfterValue": "100000", "MSRIndex": "0",