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index_files/figure-html/.-sizing-techsweep_sg13_plots_triode-cell-7-output-1.png create mode 100644 index_files/figure-html/.-sizing-techsweep_sg13_plots_triode-cell-8-output-1.png create mode 100644 index_files/mediabag/xschem/measurement_amplifier.pdf create mode 100644 xschem/measurement_amplifier.svg diff --git a/.nojekyll b/.nojekyll index d786a0aa..ded2c74c 100644 --- a/.nojekyll +++ b/.nojekyll @@ -1 +1 @@ -72ba064e \ No newline at end of file +8bc59979 \ No newline at end of file diff --git a/_tex/index.tex b/_tex/index.tex index 652327ff..4c1f96fd 100644 --- a/_tex/index.tex +++ b/_tex/index.tex @@ -281,7 +281,7 @@ \section{Introduction}\label{sec-intro} Tools and PDK are integrated in the \textbf{IIC-OSIC-TOOLS} Docker image, which will be used during the coursework. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-important-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-important-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-important-color}{\faExclamation}\hspace{0.5em}{Important}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-important-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-important-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-important-color}{\faExclamation}\hspace{0.5em}{Important}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] All course material (source code of this document, Jupyter notebooks for calculations, Xschem circuits, etc.) is made publicly available on @@ -424,7 +424,7 @@ \subsection{Integrated IC Design Environment \href{https://github.com/iic-jku/IIC-OSIC-TOOLS}{IIC-OSIC-TOOLS GitHub page}. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-warning-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-warning-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-warning-color}{\faExclamationTriangle}\hspace{0.5em}{Preparation}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-warning-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-warning-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-warning-color}{\faExclamationTriangle}\hspace{0.5em}{Preparation}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Please make sure to receive information about your personal VM access ahead of the course start. @@ -435,7 +435,7 @@ \subsection{Integrated IC Design Environment JKU students the IIC will host a VM on our compute cluster and provide personal login credentials. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-warning-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-warning-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-warning-color}{\faExclamationTriangle}\hspace{0.5em}{Linux}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-warning-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-warning-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-warning-color}{\faExclamationTriangle}\hspace{0.5em}{Linux}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] In this course, we assume that students have a basic knowledge of Linux and how to operate it using the terminal. If you are not yet familiar @@ -523,7 +523,7 @@ \subsubsection{Updating the Repository}\label{updating-the-repository} \texttt{git\ merge\ origin/main} \end{itemize} -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-warning-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-warning-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-warning-color}{\faExclamationTriangle}\hspace{0.5em}{Git Merge Conflicts}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-warning-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-warning-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-warning-color}{\faExclamationTriangle}\hspace{0.5em}{Git Merge Conflicts}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] It is possible that \texttt{git\ merge} does not complete successfully. Either you are able to resolve the merge conflict manually, or it may be @@ -573,7 +573,7 @@ \subsection{The Metal-Oxide-Semiconductor Field-Effect-Transistor source, and then the bulk terminal is not shown to declutter the schematics. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-note-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-note-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{MOSFET Background}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-note-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-note-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{MOSFET Background}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Strictly speaking is the drain-source current of a MOSFET controlled by the voltage between gate and bulk and the voltage between drain and @@ -686,7 +686,7 @@ \subsection{The Metal-Oxide-Semiconductor Field-Effect-Transistor For lower frequencies and bulk MOSFETs we will not consider these resistors, and just deal with the capacitive behavior. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-note-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-note-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{MOSFET Bulk Terminal}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-note-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-note-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{MOSFET Bulk Terminal}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] In many situations we will connect the bulk and source terminals of a MOSFET together, which results in a simplified large-signal model. As an @@ -720,7 +720,7 @@ \subsection{The Metal-Oxide-Semiconductor Field-Effect-Transistor first simple dc sweeps of various voltages and currents will be done. But before that, please look at the import note below! -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-important-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-important-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-important-color}{\faExclamation}\hspace{0.5em}{Mathematical Notation}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-important-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-important-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-important-color}{\faExclamation}\hspace{0.5em}{Mathematical Notation}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Throughout this material, we will largely stick to the following notation standardized by IEEE: @@ -766,7 +766,7 @@ \subsubsection{Large-Signal MOSFET \end{figure}% -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-note-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-note-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{MOSFET Simulation Model}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-note-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-note-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{MOSFET Simulation Model}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] For modelling the MOSFET behavior in a circuit simulator like ngspice different models are available. Some of these models have been widely @@ -794,7 +794,7 @@ \subsubsection{Large-Signal MOSFET \end{tcolorbox} -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-tip-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-tip-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: MOSFET Investigation}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-tip-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-tip-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: MOSFET Investigation}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Please try to execute the following steps and answer these questions: @@ -972,7 +972,7 @@ \subsubsection{Small-Signal MOSFET \(\gamma =1\) for triode operation; \(g_\mathrm{d0}\) is equal to \(g_\mathrm{m}\) in saturation and \(g_\mathrm{ds}\) in triode). -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-note-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-note-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{MOSFET Triode and Saturation Region}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-note-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-note-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{MOSFET Triode and Saturation Region}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Sometimes we will refer to different operating modes of the MOSFET like ``saturation'' or ``triode.'' Generally speaking, when the drain-source @@ -1042,7 +1042,7 @@ \subsubsection{Small-Signal MOSFET \href{https://iic-jku.github.io/analog-circuit-design/index.qmd.html}{Article Notebook}} -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-tip-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-tip-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: MOSFET Model Transformation}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-tip-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-tip-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: MOSFET Model Transformation}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Can you show, with which circuit manipulations you can transform the pi-model of Figure~\ref{fig-mosfet-small-signal-model-basic} into the @@ -1070,7 +1070,7 @@ \subsubsection{Small-Signal MOSFET speed of a MOSFET; in other words, how much input capacitance \(C_\mathrm{gg}\) is incurred when creating a certain \(g_\mathrm{m}\). -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-tip-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-tip-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: MOSFET Transit Frequency}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-tip-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-tip-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: MOSFET Transit Frequency}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] As a home exercise, try to derive Equation~\ref{eq-mosfet-transit-frequency} starting from @@ -1084,7 +1084,7 @@ \subsubsection{Small-Signal MOSFET Figure~\ref{fig-mosfet-small-signal-model} can be investigated and estimated using circuit simulation. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-tip-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-tip-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: MOSFET Small-Signal Parameters}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-tip-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-tip-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: MOSFET Small-Signal Parameters}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Please try to execute the following steps and answer the following questions: @@ -1134,7 +1134,7 @@ \subsubsection{Small-Signal MOSFET \end{tcolorbox} -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-note-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-note-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Note \ref*{nte-maxwell-cap-matrix}: Maxwell Capacitance Matrix}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-note-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-note-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Note \ref*{nte-maxwell-cap-matrix}: Maxwell Capacitance Matrix}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] \quartocalloutnte{nte-maxwell-cap-matrix} @@ -1203,7 +1203,7 @@ \section{Transistor Sizing Using gm/ID the overdrive voltage, which are interesting from a theoretical viewpoint, but bear little practical use. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-note-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-note-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{MOSFET Square-Law Model}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-note-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-note-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{MOSFET Square-Law Model}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] One of the many simplifications of the square-law model is that the mobility of the charge carriers is assumed constant (it is not). @@ -1251,7 +1251,7 @@ \subsection{MOSFET Characterization Figure~\ref{fig-techsweep-nmos-tb}, and the TB for the LV PMOS is shown in Figure~\ref{fig-techsweep-pmos-tb}. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-note-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-note-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Note on Characterization Testbench}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-note-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-note-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Note on Characterization Testbench}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] The testbenches are relatively straightforward, with one exception: The drain current noise is sensed via the drain voltage source \texttt{vd} @@ -1327,7 +1327,7 @@ \subsection{NMOS Characterization in lowest power consumption. Thus, a high \(g_\mathrm{m}/I_\mathrm{D}\) ratio is good. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-note-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-note-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Power Consumption}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-note-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-note-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Power Consumption}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Designing for minimum power consumption is pretty much always mandated. For battery-operated equipment it is a paramount requirement, but also @@ -1364,7 +1364,7 @@ \subsection{NMOS Characterization in }\end{equation} with \(V_\mathrm{th}\) the threshold voltage and \(V_\mathrm{od}\) the so-called ``overdrive voltage.'' -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-note-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-note-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Why 300K?}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-note-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-note-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Why 300K?}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Why are we so often using a temperature of \(300\,\text{K}\) for a typical condition? As this corresponds to roughly @@ -1464,7 +1464,7 @@ \subsection{NMOS Characterization in \href{https://en.wikipedia.org/wiki/Johnson–Nyquist_noise}{quantum effects} start to kick in. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-note-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-note-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Noise Notation}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-note-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-note-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Noise Notation}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] We usually leave the \(\Delta f\) away for a shorter notation, so we write \(\overline{V_\mathrm{n}^2}\) when we actually mean @@ -1526,7 +1526,7 @@ \subsection{NMOS Characterization in so here we have a trade-off between flicker-noise performance and MOSFET speed, and this can have dramatic consequences for high-speed circuits. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-note-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-note-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{MOSFET Flicker Noise}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-note-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-note-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{MOSFET Flicker Noise}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] The physical origin of flicker noise is the crystal interface between silicon (Si) and the silicon dioxide (SiO\textsubscript{2}). Since these @@ -1554,7 +1554,7 @@ \subsection{PMOS Characterization in In the following, we have the same plots as discussed in Section~\ref{sec-techsweep-nmos}, but now for the PMOS. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-note-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-note-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{PMOS Sign Convention}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-note-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-note-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{PMOS Sign Convention}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] In all PMOS plots we plot positive values for voltages and currents, to have compatible plots to the NMOS. Of course, in a PMOS, voltages and @@ -1589,7 +1589,7 @@ \subsection{PMOS Characterization in for the PMOS. We can not use these values for our circuit sizing, so we will use the respective NMOS plots also for the PMOS. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-important-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-important-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-important-color}{\faExclamation}\hspace{0.5em}{Beware of Modelling Issues}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-important-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-important-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-important-color}{\faExclamation}\hspace{0.5em}{Beware of Modelling Issues}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] This example shows how important it is to benchmark the device models when starting to use a new technology. Modelling artifacts like the one @@ -1649,6 +1649,69 @@ \subsection{PMOS Characterization in \href{https://iic-jku.github.io/analog-circuit-design/index.qmd.html}{Article Notebook}} +\subsection{NMOS and PMOS Characterization in +Triode}\label{nmos-and-pmos-characterization-in-triode} + +Besides using the MOSFET as a transconductor in saturation we often use +the MOSFET as a switch in triode mode (to either switch voltages or +currents). In this triode/switch mode of operation we are mainly +interested in two parameters: + +\begin{itemize} +\tightlist +\item + The resistance of the switch/MOSFET when it is turned on + (\(R_\mathrm{on} = 1 / g_\mathrm{ds}\)). +\item + The shunt capacitance of the switch when it is turned off + (\(C_\mathrm{off}\) is defined by the coupling capacitances between + drain and source). +\end{itemize} + +In the operation of the NMOS as a switch the gate is usually pulled to +\(V_\mathrm{DD}\) and the bulk is permanently connected to +\(V_\mathrm{SS}\) to achieve the lowest \(R_\mathrm{on}\) (to turn the +switch off the gate is pulled towards \(V_\mathrm{SS}\)). Likewise, to +turn on a PMOS, the gate is usually pulled to \(V_\mathrm{SS}\) and the +bulk is connected to \(V_\mathrm{DD}\). In this situation the +drain/source potential is somewhere between \(V_\mathrm{DD}\) and +\(V_\mathrm{SS}\), so the MOSFET will experience a +\(V_\mathrm{SB}\neq 0\), leading to a quite noticeable bulk effect. Once +the drain/source potential is sufficiently high for NMOS (low PMOS) the +switch resistance will drastically degrade. + +In order to get a feeling for the behavior of the MOSFET as a switch the +following characterization plots show \(R_\mathrm{on}\) and +\(C_\mathrm{off}\) for the NMOS and the PMOS, respectively. Both plots +are for \(L = L_\mathrm{min} = 0.13\mu m\), as for switches usually +minimum length devices are used. Only for special applications (e.g., +the leakage current in off-mode is a concern) MOSFETs with increased +\(L\) are used. + +\includegraphics{index_files/figure-latex/.-sizing-techsweep_sg13_plots_triode-cell-4-output-1.png} + +\textsubscript{Source: +\href{https://iic-jku.github.io/analog-circuit-design/index.qmd.html}{Article +Notebook}} + +As can be seen in the previous plot, an NMOS can be used to switch at +potentials close to \(V_\mathrm{SS}\), while a PMOS can be used to +switch at potentials close to \(V_\mathrm{DD}\). To construct a switch +which can work for all voltage levels between \(V_\mathrm{DD}\) and +\(V_\mathrm{SS}\) an NMOS is put in parallel to a PMOS, resulting in the +well-known \textbf{transmission gate}. + +\includegraphics{index_files/figure-latex/.-sizing-techsweep_sg13_plots_triode-cell-7-output-1.png} + +\textsubscript{Source: +\href{https://iic-jku.github.io/analog-circuit-design/index.qmd.html}{Article +Notebook}} + +As the switch on-resistance gets lower when increasing \(W\), the +off-capacitance gets larger. Thus, a good performance indicator for +comparing switches in a given technology is the +\(R_\mathrm{on} C_\mathrm{off}\) product. + \section{First Circuit: MOSFET Diode}\label{sec-mosfet-diode} The first (simple) circuit we will investigate is a MOSFET, where the @@ -1689,7 +1752,7 @@ \section{First Circuit: MOSFET Diode}\label{sec-mosfet-diode} This voltage can be used as a biasing voltage for other circuit parts, for example. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-note-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-note-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Feedback in the MOSFET Diode}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-note-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-note-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Feedback in the MOSFET Diode}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] It is important to realize that this configuration essentially employs a feedback loop for operation. The voltage at the drain of the MOSFET is @@ -1705,7 +1768,7 @@ \subsection{MOSFET Diode Sizing}\label{mosfet-diode-sizing} use the \(g_\mathrm{m}/I_\mathrm{D}\) methodology introduced in Section~\ref{sec-gmid-method}. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-tip-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-tip-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: MOSFET Diode Sizing}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-tip-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-tip-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: MOSFET Diode Sizing}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Please build a MOSFET diode circuit in Xschem where you use an LV NMOS, set \(I_\mathrm{bias} = 20\,\mu\text{A}\), \(L = 0.13\,\mu\text{m}\), @@ -1731,7 +1794,7 @@ \subsection{MOSFET Diode Sizing}\label{mosfet-diode-sizing} Before continuing, please finish the previous exercise. Once you are done, compare with the below provided solution. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-tip-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-tip-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Solution: MOSFET Diode Sizing}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-tip-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-tip-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Solution: MOSFET Diode Sizing}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] \begin{enumerate} \def\labelenumi{\arabic{enumi}.} @@ -1838,7 +1901,7 @@ \subsection{MOSFET Diode Small-Signal \href{https://iic-jku.github.io/analog-circuit-design/index.qmd.html}{Article Notebook}} -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-note-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-note-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Ground Node Selection}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-note-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-note-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Ground Node Selection}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] For small-signal analysis we would not need to declare one node as the ground potential. However, when doing so, and selecting the ground node @@ -1863,7 +1926,7 @@ \subsection{MOSFET Diode Small-Signal \(Z_\mathrm{diode} = 1 / g_\mathrm{m}\), which is an important result and should be memorized. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-important-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-important-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-important-color}{\faExclamation}\hspace{0.5em}{The Admittance is Your Friend}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-important-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-important-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-important-color}{\faExclamation}\hspace{0.5em}{The Admittance is Your Friend}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] In circuit analysis it is often algebraically easier to work with admittance instead of impedance, so please remember that Ohm's law for a @@ -1961,7 +2024,7 @@ \subsection{MOSFET Diode Stability \(H_\mathrm{ol}(s)\) by using Middlebrook's method and confirm our analysis above. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-tip-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-tip-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: MOSFET Diode Loop Analysis}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-tip-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-tip-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: MOSFET Diode Loop Analysis}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Please build a simulation testbench in Xschem to simulate the open-loop transfer function of the MOSFET diode. Confirm the dc gain and pole @@ -2052,7 +2115,7 @@ \subsection{MOSFET Diode Noise interested in the rms value (the total noise) we need to integrate this equation, using the following identity: -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-note-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-note-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Useful Integral for Noise Calculations}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-note-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-note-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Useful Integral for Noise Calculations}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] \begin{equation}\phantomsection\label{eq-integral-identity}{ \int_0^\infty {\frac{a}{b^2 + c^2 f^2} df} = \frac{\pi}{2} \frac{a}{b \cdot c} @@ -2082,14 +2145,14 @@ \subsection{MOSFET Diode Noise of ca. \(1.1\,\mathrm{V_{pp}}\), resulting in a dynamic range in this case of \(20 \log (1.58 \cdot 10^{-3} / 0.39) \approx -48\,\text{dB}\). -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-important-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-important-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-important-color}{\faExclamation}\hspace{0.5em}{Large Bandwidth and Noise}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-important-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-important-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-important-color}{\faExclamation}\hspace{0.5em}{Large Bandwidth and Noise}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Large BW circuits can integrate noise over a wide bandwidth resulting in considerable rms noise. \end{tcolorbox} -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-tip-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-tip-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: MOSFET Diode Noise}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-tip-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-tip-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: MOSFET Diode Noise}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Please build a simulation testbench in Xschem to simulate the noise performance of the MOSFET diode, and confirm the rms noise value that we @@ -2208,7 +2271,7 @@ \subsection{Sense Amplifier for 50Ohm \href{https://iic-jku.github.io/analog-circuit-design/index.qmd.html}{Article Notebook}} -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-tip-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-tip-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: PMOS-Based Measurement Amplifier}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-tip-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-tip-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: PMOS-Based Measurement Amplifier}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Please think about why exactly we want this measurement amplifier be based on a PMOS instead of an NMOS. @@ -2233,7 +2296,7 @@ \subsection{Sense Amplifier for 50Ohm notebook (the red input capacitor shows the \(C_\mathrm{gg}\) of the MOSFET). -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-tip-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-tip-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: Measurement Amplifier Simulation}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-tip-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-tip-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: Measurement Amplifier Simulation}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Please go through the \href{./sizing/sizing_measurement_amplifier.ipynb}{sizing notebook} of @@ -2265,7 +2328,21 @@ \subsection{Sense Amplifier for 50Ohm \end{itemize} If you get stuck, \href{./xschem/measurement_amplifier.sch}{here} is the -solution to this exercise. +solution to this exercise, and it is also shown in +Figure~\ref{fig-meas-amp-tb}. + +\begin{figure}[H] + +\centering{ + +\includegraphics{index_files/mediabag/xschem/measurement_amplifier.pdf} + +} + +\caption{\label{fig-meas-amp-tb}Simulation schematic of the +common-source measurement amplifier.} + +\end{figure}% \end{tcolorbox} @@ -2340,7 +2417,7 @@ \section{Current Mirror}\label{sec-current-mirror} simple current mirror is required this structure is used for its simplicity. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-tip-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-tip-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: Current Mirror}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-tip-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-tip-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: Current Mirror}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Please construct a current mirror based on the MOSFET-diode which we sized in Section~\ref{sec-mosfet-diode}. The input current @@ -2540,7 +2617,7 @@ \section{A Basic 5-Transistor OTA}\label{sec-basic-ota} \href{https://iic-jku.github.io/analog-circuit-design/index.qmd.html}{Article Notebook}} -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-warning-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-warning-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-warning-color}{\faExclamationTriangle}\hspace{0.5em}{Refresh MOSFET Basic Circuits}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-warning-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-warning-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-warning-color}{\faExclamationTriangle}\hspace{0.5em}{Refresh MOSFET Basic Circuits}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] While we repeat the basics of elementary MOSFET amplifier stages (like common-source stage, common-gate stage, and current mirror) in this @@ -2773,7 +2850,7 @@ \subsubsection{OTA Small-Signal Transfer The resulting small-signal equivalent circuit is shown in Figure~\ref{fig-basic-ota-small-signal}. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-warning-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-warning-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-warning-color}{\faExclamationTriangle}\hspace{0.5em}{Refresh MOSFET Small-Signal Model}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-warning-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-warning-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-warning-color}{\faExclamationTriangle}\hspace{0.5em}{Refresh MOSFET Small-Signal Model}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Please review the MOSFET small-signal equivalent model in Figure~\ref{fig-mosfet-small-signal-model} at this point. For the PMOS @@ -2918,7 +2995,7 @@ \subsubsection{OTA Noise}\label{ota-noise} \overline{V_\mathrm{gs34}^2} = \frac{1}{g_\mathrm{m34}^2} \left( \overline{I_\mathrm{n1}^2} + \overline{I_\mathrm{n3}^2} \right). \] -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-important-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-important-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-important-color}{\faExclamation}\hspace{0.5em}{Noise Addition}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-important-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-important-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-important-color}{\faExclamation}\hspace{0.5em}{Noise Addition}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Remember that \textbf{uncorrelated} noise quantities need to be power-summed (i.e., \(I^2 = I_1^2 + I_2^2\))! @@ -2966,7 +3043,7 @@ \subsubsection{OTA Noise}\label{ota-noise} \href{https://iic-jku.github.io/analog-circuit-design/index.qmd.html}{Article Notebook}} -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-note-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-note-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Output Impedance of the Voltage Buffer}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-note-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-note-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Output Impedance of the Voltage Buffer}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] First we short the input terminal to ground and then we connect a current source \(I_\mathrm{out}\) at the output terminal, see @@ -3025,7 +3102,7 @@ \subsubsection{OTA Noise}\label{ota-noise} pair, plus a (smaller) contribution of the current mirror load \(M_{3,4}\). Intuitively, this result makes sense. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-tip-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-tip-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: Derivation of 5T-OTA Performance}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-tip-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-tip-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: Derivation of 5T-OTA Performance}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Please take your time and carefully go through the explanations and derivations for the 5-transistor-OTA in @@ -3059,7 +3136,7 @@ \subsection{5T-OTA Sizing}\label{sec-basic-ota-sizing} V_\mathrm{ds,sat} = \frac{2}{g_\mathrm{m}/I_\mathrm{D}} }\end{equation} -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-tip-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-tip-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: 5T-OTA Sizing}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-tip-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-tip-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: 5T-OTA Sizing}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Please size the 5T-OTA according to the previous \(g_\mathrm{m}/I_\mathrm{D}\) and \(L\) suggestions. Please calculate @@ -3073,7 +3150,7 @@ \subsection{5T-OTA Sizing}\label{sec-basic-ota-sizing} notebook, as we can easily look up the exact data from the pre-computed tables: -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-tip-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-tip-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Solution: 5T-OTA Sizing}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-tip-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-tip-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Solution: 5T-OTA Sizing}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] \section*{Sizing for Basic 5T-OTA}\label{sizing-for-basic-5t-ota} @@ -3354,7 +3431,7 @@ \subsection{5T-OTA Simulation}\label{sec-basic-ota-simulation} Please read Section~\ref{sec-designers-etiquette} before you start into your design work. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-tip-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-tip-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: 5T-OTA Design and Testbench}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-tip-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-tip-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: 5T-OTA Design and Testbench}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Please design the circuit of the 5T-OTA. Put the OTA circuit in a separate schematic, create a symbol for it, and use this symbol in a @@ -3444,7 +3521,7 @@ \subsection{5T-OTA Simulation versus result of a full run of this \href{./xschem/ota-5t.svg}{OTA design} is presented here: -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-note-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-note-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Note \ref*{nte-basic-ota-cace-result}: CACE Summary for 5T-OTA}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-note-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-note-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Note \ref*{nte-basic-ota-cace-result}: CACE Summary for 5T-OTA}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] \quartocalloutnte{nte-basic-ota-cace-result} @@ -3859,7 +3936,7 @@ \subsection{Cascode Output Impedance}\label{cascode-output-impedance} g_\mathrm{out} = \frac{g_\mathrm{ds}\cdot g_\mathrm{ds}'}{g_\mathrm{ds}' + g_\mathrm{m}+ g_\mathrm{ds}} \approx g_\mathrm{ds}' \frac{g_\mathrm{ds}}{g_\mathrm{m}}. }\end{equation} -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-important-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-important-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-important-color}{\faExclamation}\hspace{0.5em}{Benefit of Cascode (Output)}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-important-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-important-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-important-color}{\faExclamation}\hspace{0.5em}{Benefit of Cascode (Output)}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] The output impedance of the lower MOSFET (\(g_\mathrm{ds}'\)) is \textbf{reduced} by the self-gain of the cascode transistor! This is a @@ -3920,7 +3997,7 @@ \subsection{Cascode Input Impedance}\label{cascode-input-impedance} which means that the input impedance looking into a cascode is approximately \(1/g_\mathrm{m}\). -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-important-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-important-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-important-color}{\faExclamation}\hspace{0.5em}{Benefit of Cascode (Input)}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-important-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-important-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-important-color}{\faExclamation}\hspace{0.5em}{Benefit of Cascode (Input)}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] This has the practical benefit that a capacitance connected at this node results in a high-frequency pole, which is often not critical in terms @@ -3969,7 +4046,7 @@ \section{Improved OTA}\label{sec-improved-ota} \(V_\mathrm{DS}\) of \(M_{1,2}\) stays constant with a changing common-mode input voltage. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-important-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-important-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-important-color}{\faExclamation}\hspace{0.5em}{Cascode Bias Voltage Generation}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-important-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-important-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-important-color}{\faExclamation}\hspace{0.5em}{Cascode Bias Voltage Generation}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] It is critically import for a stable performance across PVT that the bias voltages for the cascode gates are created in a manner that tracks @@ -3985,7 +4062,7 @@ \section{Improved OTA}\label{sec-improved-ota} \(M_{5,6}\) (and \(M_{3,4}\)) to be equal, so the current mirror ratio is independent of \(g_\mathrm{ds}\). -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-tip-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-tip-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: Cascode Current Mirror vs.~High-Swing Cascode Current Mirror}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-tip-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-tip-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: Cascode Current Mirror vs.~High-Swing Cascode Current Mirror}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Try to verify the above statement of equal drain-source voltages by deriving both, an equation for \(V_\mathrm{DS5}\) assuming a high-swing @@ -4043,7 +4120,7 @@ \subsection{Sizing the Improved OTA}\label{sec-improved-ota-sizing} we stack now double as many MOSFET at the same supply voltage). Please look at Section~\ref{sec-gmid-method} to confirm this choice. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-note-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-note-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Improved OTA Sizing}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-note-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-note-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Improved OTA Sizing}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] \section*{Sizing for Basic (Improved) OTA}\label{sizing-for-basic-improved-ota} @@ -4386,7 +4463,7 @@ \section*{Sizing for Basic (Improved) we can squeeze it into the available supply voltage range, and see that this is possible with our above choice selection of parameters. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-tip-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-tip-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: Improved OTA Sizing}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-tip-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-tip-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: Improved OTA Sizing}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Please take a detailed look at the above sizing notebook and play with the numbers and calculations. Do you find a better trade-off for the @@ -4507,7 +4584,7 @@ \subsubsection{Discussion of the OTA \end{figure}% -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-note-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-note-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Parallel Connection}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-note-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-note-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Parallel Connection}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Note that a parallel connection of devices is effectively possible using the multiplier notation of Xschem. @@ -4548,7 +4625,7 @@ \subsection{Simulation of Improved \end{figure}% -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-tip-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-tip-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: Improved OTA Initial Simulation}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-tip-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-tip-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-tip-color}{\faLightbulb}\hspace{0.5em}{Exercise: Improved OTA Initial Simulation}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] Please use the above testbenches to simulate the improved OTA: @@ -4582,7 +4659,7 @@ \subsection{Corner Simulation of Improved like PVT and input signal variations. The results of the CACE run are shown below in Note~\ref{nte-improved-ota-cace-result}. -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-note-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-note-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Note \ref*{nte-improved-ota-cace-result}: CACE Summary for Improved OTA}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-note-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-note-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-note-color}{\faInfo}\hspace{0.5em}{Note \ref*{nte-improved-ota-cace-result}: CACE Summary for Improved OTA}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] \quartocalloutnte{nte-improved-ota-cace-result} @@ -4905,7 +4982,7 @@ \section{Summary \& Conclusion}\label{summary-conclusion} OTA structures. In summary, you are on a good way to become a good analog or mixed-signal circuit designer! -\begin{tcolorbox}[enhanced jigsaw, arc=.35mm, colbacktitle=quarto-callout-important-color!10!white, leftrule=.75mm, bottomtitle=1mm, opacityback=0, breakable, toprule=.15mm, coltitle=black, bottomrule=.15mm, colframe=quarto-callout-important-color-frame, opacitybacktitle=0.6, colback=white, title=\textcolor{quarto-callout-important-color}{\faExclamation}\hspace{0.5em}{Feedback}, toptitle=1mm, titlerule=0mm, rightrule=.15mm, left=2mm] +\begin{tcolorbox}[enhanced jigsaw, opacityback=0, colbacktitle=quarto-callout-important-color!10!white, colback=white, bottomtitle=1mm, toptitle=1mm, colframe=quarto-callout-important-color-frame, toprule=.15mm, coltitle=black, arc=.35mm, titlerule=0mm, title=\textcolor{quarto-callout-important-color}{\faExclamation}\hspace{0.5em}{Feedback}, rightrule=.15mm, breakable, left=2mm, bottomrule=.15mm, opacitybacktitle=0.6, leftrule=.75mm] We hope you have enjoyed these lecture notes! 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+++ b/index.html @@ -228,6 +228,7 @@

Table of contents

  • 3.1 MOSFET Characterization Testbench
  • 3.2 NMOS Characterization in Saturation
  • 3.3 PMOS Characterization in Saturation
    • +
  • 3.4 NMOS and PMOS Characterization in Triode
  • 4 First Circuit: MOSFET Diode
      @@ -1194,6 +1195,40 @@

      +
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      3.4 NMOS and PMOS Characterization in Triode

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      Besides using the MOSFET as a transconductor in saturation we often use the MOSFET as a switch in triode mode (to either switch voltages or currents). In this triode/switch mode of operation we are mainly interested in two parameters:

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      • The resistance of the switch/MOSFET when it is turned on (\(R_\mathrm{on} = 1 / g_\mathrm{ds}\)).
        • +
      • The shunt capacitance of the switch when it is turned off (\(C_\mathrm{off}\) is defined by the coupling capacitances between drain and source).
        • +
      +

      In the operation of the NMOS as a switch the gate is usually pulled to \(V_\mathrm{DD}\) and the bulk is permanently connected to \(V_\mathrm{SS}\) to achieve the lowest \(R_\mathrm{on}\) (to turn the switch off the gate is pulled towards \(V_\mathrm{SS}\)). Likewise, to turn on a PMOS, the gate is usually pulled to \(V_\mathrm{SS}\) and the bulk is connected to \(V_\mathrm{DD}\). In this situation the drain/source potential is somewhere between \(V_\mathrm{DD}\) and \(V_\mathrm{SS}\), so the MOSFET will experience a \(V_\mathrm{SB}\neq 0\), leading to a quite noticeable bulk effect. Once the drain/source potential is sufficiently high for NMOS (low PMOS) the switch resistance will drastically degrade.

      +

      In order to get a feeling for the behavior of the MOSFET as a switch the following characterization plots show \(R_\mathrm{on}\) and \(C_\mathrm{off}\) for the NMOS and the PMOS, respectively. Both plots are for \(L = L_\mathrm{min} = 0.13\mu m\), as for switches usually minimum length devices are used. Only for special applications (e.g., the leakage current in off-mode is a concern) MOSFETs with increased \(L\) are used.

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      As can be seen in the previous plot, an NMOS can be used to switch at potentials close to \(V_\mathrm{SS}\), while a PMOS can be used to switch at potentials close to \(V_\mathrm{DD}\). To construct a switch which can work for all voltage levels between \(V_\mathrm{DD}\) and \(V_\mathrm{SS}\) an NMOS is put in parallel to a PMOS, resulting in the well-known transmission gate.

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      As the switch on-resistance gets lower when increasing \(W\), the off-capacitance gets larger. Thus, a good performance indicator for comparing switches in a given technology is the \(R_\mathrm{on} C_\mathrm{off}\) product.

      +

      4 First Circuit: MOSFET Diode

      @@ -1203,7 +1238,7 @@

      4 First Circuit:
      - +
      Figure 11: A MOSFET connected as a diode. @@ -1279,7 +1314,7 @@

      - +
      Figure 12: Testbench for MOSFET diode transient settling. @@ -1297,7 +1332,7 @@

      - +
      Figure 13: The MOSFET diode small-signal model. @@ -1351,7 +1386,7 @@

      - +
      Figure 14: The MOSFET diode small-signal circuit for open-loop analysis. @@ -1390,7 +1425,7 @@

      - +
      Figure 15: Testbench for MOSFET diode stability analysis. @@ -1410,7 +1445,7 @@

      - +
      Figure 16: The MOSFET diode small-signal model with drain noise source. @@ -1482,7 +1517,7 @@

      - +
      Figure 17: Testbench for MOSFET diode noise analysis. @@ -1506,7 +1541,7 @@

      5 Common-Source A
      - +
      Figure 18: A MOSFET common-source amplifier with resistive load. @@ -1528,7 +1563,7 @@

      - +
      Figure 19: A MOSFET common-source amplifier with 50 Ohm load. @@ -1570,7 +1605,17 @@

      \(W\) of the PMOS until the gain is correct. What is the \(W\) that you had to set, and how much is \(I_\mathrm{D}\) now?
    • What is the bandwidth (i.e., the -3dB corner frequency) of the output, when the voltage source has a source resistance of 1k\(\Omega\)?

    -

    If you get stuck, here is the solution to this exercise.

    +

    If you get stuck, here is the solution to this exercise, and it is also shown in Figure 20.

    +
    +
    +
    + +
    +
    +Figure 20: Simulation schematic of the common-source measurement amplifier. +
    +
    +

    By now we have designed a measurement amplifier based on a common-source stage. One problem with this stage is the relatively large input capacitance of approx. 0.3pF, which loads the input. Another issue even more severe is that the fact that the bias point in the circuit is set by the dc voltage level at the input. In general, we want a setup where the bias points of the circuit are largely independent of the dc input voltages. This is why in integrated circuit design we often design differential circuits where the input and output signals are given by the differential voltages, and are largely independent from the common-mode voltages. This is usually an advantage.

    @@ -1578,16 +1623,16 @@

    6 Current Mirror

    -

    In this section we will look into a fundamental building block which is often used in integrated circuit design, the current mirror. A diagram is shown in Figure 20 with one MOSFET diode converting the incoming bias current into a voltage, and two output MOSFETs working as current sources, which are biased from the diode. By properly selecting all \(W\) and \(L\) the input current can be scaled, and multiple copies can be created at once. Shown in the figure are two output currents, but any number of parallel branches can be realized.

    +

    In this section we will look into a fundamental building block which is often used in integrated circuit design, the current mirror. A diagram is shown in Figure 21 with one MOSFET diode converting the incoming bias current into a voltage, and two output MOSFETs working as current sources, which are biased from the diode. By properly selecting all \(W\) and \(L\) the input current can be scaled, and multiple copies can be created at once. Shown in the figure are two output currents, but any number of parallel branches can be realized.

    - +
    -Figure 20: A current mirror with two output branches. +Figure 21: A current mirror with two output branches.
    @@ -1599,7 +1644,7 @@

    6 Current Mirror< I_\mathrm{out2} = I_\mathrm{bias} \frac{W_3}{L_3} \frac{L_1}{W_1}. \]

    For good matching in layout care has to be taken that the MOSFET widths and lengths are constructed out of unit elements of identical size, where an appropriate amount of these single units are then arranged in series or parallel configuration to arrive at the target \(W\) and \(L\).

    -

    As we know from earlier investigations of the MOSFET performance in Section 3 the drain current of a MOSFET is a function of \(V_\mathrm{GS}\) and \(V_\mathrm{DS}\). As long as the MOSFET stays in saturation (i.e., \(V_\mathrm{DS}> V_\mathrm{ds,dsat}\)) the drain current is just a mild function of \(V_\mathrm{DS}\) (essentially the effect of \(g_\mathrm{ds}\), which is the output conductance of the MOSFET). A fundamental flaw of the basic current mirror shown in Figure 20 is the mismatch of the \(V_\mathrm{DS}\) of the MOSFET. The input-side diode has \(V_\mathrm{GS}= V_\mathrm{DS}\), whereas the output current sources have a \(V_\mathrm{DS}\) depending on the connected circuitry. Improved current mirrors exist (basically fixing this flaw), still, when just a simple current mirror is required this structure is used for its simplicity.

    +

    As we know from earlier investigations of the MOSFET performance in Section 3 the drain current of a MOSFET is a function of \(V_\mathrm{GS}\) and \(V_\mathrm{DS}\). As long as the MOSFET stays in saturation (i.e., \(V_\mathrm{DS}> V_\mathrm{ds,dsat}\)) the drain current is just a mild function of \(V_\mathrm{DS}\) (essentially the effect of \(g_\mathrm{ds}\), which is the output conductance of the MOSFET). A fundamental flaw of the basic current mirror shown in Figure 21 is the mismatch of the \(V_\mathrm{DS}\) of the MOSFET. The input-side diode has \(V_\mathrm{GS}= V_\mathrm{DS}\), whereas the output current sources have a \(V_\mathrm{DS}\) depending on the connected circuitry. Improved current mirrors exist (basically fixing this flaw), still, when just a simple current mirror is required this structure is used for its simplicity.

    @@ -1619,16 +1664,16 @@

    6 Current Mirror<

    7 Differential Pair

    -

    Like the current mirror in Section 6 the differential pair is an ubiquitous building block often used in integrated circuit design. The fundamental structure is given in Figure 21.

    +

    Like the current mirror in Section 6 the differential pair is an ubiquitous building block often used in integrated circuit design. The fundamental structure is given in Figure 22.

    - +
    -Figure 21: A differential pair. +Figure 22: A differential pair.
    @@ -1657,16 +1702,16 @@

    \(g_\mathrm{tail}\) is realized by a current source and ideally should be \(g_\mathrm{tail} = 0\). If this is the case, then the output currents are not a function of the common-mode input voltage, and (\(I_\mathrm{tail}\) is set by the tail current source) \[ I_\mathrm{out,p} = I_\mathrm{out,n} = \frac{I_\mathrm{tail}}{2}. \]

    -

    However, if we assume a realistic tail current source then \(g_\mathrm{tail} > 0\). For analysis we can simply look at a half circuit since everything is symmetric. In order to simplify the analysis a bit we remove all capacitors from the MOSFET small-signal model and set \(g_\mathrm{ds}= g_\mathrm{mb}= 0\). We arrive then at the small-signal equivalent circuit shown in Figure 22 (note that we set \(v_\mathrm{in,p} = v_\mathrm{in,n} = v_\mathrm{in}\) and \(i_\mathrm{out,p} = i_\mathrm{out,n} = i_\mathrm{out}\) under symmetry considerations).

    +

    However, if we assume a realistic tail current source then \(g_\mathrm{tail} > 0\). For analysis we can simply look at a half circuit since everything is symmetric. In order to simplify the analysis a bit we remove all capacitors from the MOSFET small-signal model and set \(g_\mathrm{ds}= g_\mathrm{mb}= 0\). We arrive then at the small-signal equivalent circuit shown in Figure 23 (note that we set \(v_\mathrm{in,p} = v_\mathrm{in,n} = v_\mathrm{in}\) and \(i_\mathrm{out,p} = i_\mathrm{out,n} = i_\mathrm{out}\) under symmetry considerations).

    - +
    -Figure 22: Small-signal model of the differential pair half-circuit in common-mode operation. +Figure 23: Small-signal model of the differential pair half-circuit in common-mode operation.
    @@ -1687,16 +1732,16 @@

    8 A Basic 5-Transistor OTA

    -

    Suited with the knowledge of basic transistor operation (Section 2 and Section 3) and the working knowledge of the current mirror (Section 4 and Section 6) as well as the differential pair (Section 7) we can now start to design our first real circuit. A fundamental (simple) circuit that is often used for basic tasks is the 5-transistor operational transconductance amplifier (OTA). A circuit diagram of this 5T-OTA is shown in Figure 23.

    +

    Suited with the knowledge of basic transistor operation (Section 2 and Section 3) and the working knowledge of the current mirror (Section 4 and Section 6) as well as the differential pair (Section 7) we can now start to design our first real circuit. A fundamental (simple) circuit that is often used for basic tasks is the 5-transistor operational transconductance amplifier (OTA). A circuit diagram of this 5T-OTA is shown in Figure 24.

    - +
    -Figure 23: The 5-transistor OTA. +Figure 24: The 5-transistor OTA.
    @@ -1721,22 +1766,22 @@

    8 A Basic 5-Trans

    As this is an OTA the output is a current; if the load impedance is high (i.e., purely capacitive, which is often the case in integrated circuits when driving MOSFET inputs) then the voltage gain of the OTA can be high (of course, in this simple OTA it is limited). With a high-impedance loading this OTA can provide a voltage output, and this is actually how OTAs are mostly operated.

    8.1 Voltage Buffer with OTA

    -

    In order to design an OTA we need an application, and from this we need to derive the circuit specifications. We want to use this OTA to realize a voltage buffer which lightly loads a voltage source and can drive a large capacitive load. Such a configuration is often used to, e.g., buffer a reference voltage that is needed (and thus loaded) by another circuit. The block diagram of this configuration is shown in Figure 24.

    +

    In order to design an OTA we need an application, and from this we need to derive the circuit specifications. We want to use this OTA to realize a voltage buffer which lightly loads a voltage source and can drive a large capacitive load. Such a configuration is often used to, e.g., buffer a reference voltage that is needed (and thus loaded) by another circuit. The block diagram of this configuration is shown in Figure 25.

    - +
    -Figure 24: A voltage buffer (based on OTA) driving a capacitive load. +Figure 25: A voltage buffer (based on OTA) driving a capacitive load.
    -

    If the voltage gain of the OTA in Figure 24 is high, then \(V_\mathrm{out} \approx V_\mathrm{in}\). We now want to design an OTA for this application for the following specification values (see Table 2). These values are rather typical of what could be expected for such a buffer design.

    +

    If the voltage gain of the OTA in Figure 25 is high, then \(V_\mathrm{out} \approx V_\mathrm{in}\). We now want to design an OTA for this application for the following specification values (see Table 2). These values are rather typical of what could be expected for such a buffer design.

    @@ -1827,7 +1872,7 @@

    \(0.7\,\text{V}\), we see that the \(V_\mathrm{DS5}\) of \(M_5\) is calculated as \(V_\mathrm{DS5} = V_\mathrm{in} - V_\mathrm{GS1} = 0.7 - 0.6 = 0.1\,\text{V}\), so this leaves little margin, but likely \(V_\mathrm{GS1}\) will be smaller, so it should work out.

  • For the output voltage, when the output voltage is on the high side, it leaves \(|V_\mathrm{DS4}| = V_\mathrm{DD}- V_\mathrm{out} = 1.45 - 0.9 = 0.55\,\text{V}\), which is enough margin.
    • -

    In summary, we think that we can make an NMOS-input OTA like the one in Figure 23 work for the required supply and input- and output voltages. If this would not work out, we need to look for further options, like a PMOS-input OTA, or a NMOS/PMOS-input OTA.

    +

    In summary, we think that we can make an NMOS-input OTA like the one in Figure 24 work for the required supply and input- and output voltages. If this would not work out, we need to look for further options, like a PMOS-input OTA, or a NMOS/PMOS-input OTA.

    Another large-signal specification item that we can quickly check is the settling time. Under slewing conditions, the complete bias current in the OTA is steered towards the output (try to understand why this is the case), so when the output capacitor is fully discharged, and we assume just a linear ramp due to constant-current charging of the output capacitor, the settling time is \[ T_\mathrm{slew} \approx \frac{C_\mathrm{load} V_\mathrm{out}}{I_\mathrm{tail}} = \frac{50 \cdot 10^{-15} \cdot 1.3}{10 \cdot 10^{-6}} = 6.5\,\text{ns} \] so this leaves plenty of margin for additional slow-signal settling due to the limited bandwidth, as well as reducing the supply current.

    @@ -1843,7 +1888,7 @@

    Table 2, the dc gain we have to calculate from the voltage accuracy specification. For a voltage follower in the configuration shown in Figure 24 the voltage gain is given by \[ +

    The specification for GBW is given in Table 2, the dc gain we have to calculate from the voltage accuracy specification. For a voltage follower in the configuration shown in Figure 25 the voltage gain is given by \[ \frac{V_\mathrm{out}}{V_\mathrm{in}} = \frac{A_0}{1 + A_0}. \tag{13}\]

    So in order to reach an output voltage accuracy of at least 3% we need a dc gain of \(A_0 > 30.2\,\text{dB}\). To allow for process and temperature variation we need to add a bit of extra gain as margin.

    @@ -1856,7 +1901,7 @@

    \(g_\mathrm{m}\gg g_\mathrm{ds}\), so we set \(g_\mathrm{ds1} = g_\mathrm{ds3} = 0\).
  • The drain capacitance of \(M_2\) and \(M_4\), as well as the gate capacitance of \(M_2\) we can add to the load capacitance \(C_\mathrm{load}\). Note that \(C_\mathrm{gs2}\) can be added because of the feedback connection between the inverting input and the output. However, this is not shown in the small-signal equivalent circuits below, because we are interested in the open-loop transfer function.
    • -

    The resulting small-signal equivalent circuit is shown in Figure 25.

    +

    The resulting small-signal equivalent circuit is shown in Figure 26.

    @@ -1875,31 +1920,31 @@

    - +
    -Figure 25: 5-transistor OTA small-signal model. +Figure 26: 5-transistor OTA small-signal model.

    -

    We can further simplify the output side by recognizing that the impedance looking from the output down we have \(g_\mathrm{ds2}\) in series with \(g_\mathrm{ds5} + g_\mathrm{m12}\) (since we treat \(M_1\) as a common-gate stage when looking from the output, and since it is loaded by a low impedance of \(g_\mathrm{m34}^{-1}\) we can approximate the impedance looking into the source of \(M_1\) with \(g_\mathrm{m12}^{-1}\)). With the approximation that \(g_\mathrm{m}\gg g_\mathrm{ds}\) the parallel connection of \(g_\mathrm{m12}\) and \(g_\mathrm{ds5}\) is dominated by \(g_\mathrm{m12}\) and series connection by \(g_\mathrm{ds2}\). Therefore, we can move \(g_\mathrm{ds2} + g_\mathrm{ds4}\) in parallel to \(C_\mathrm{load}\). Further, assuming a differential drive with a virtual ground at the tailpoint we can remove \(g_\mathrm{ds5}\). The current source \(g_\mathrm{m34} v_\mathrm{gs34}\) is replace with the equivalent conductance \(g_\mathrm{m34}\). This results in the further simplified equivalent circuit shown in Figure 26.

    +

    We can further simplify the output side by recognizing that the impedance looking from the output down we have \(g_\mathrm{ds2}\) in series with \(g_\mathrm{ds5} + g_\mathrm{m12}\) (since we treat \(M_1\) as a common-gate stage when looking from the output, and since it is loaded by a low impedance of \(g_\mathrm{m34}^{-1}\) we can approximate the impedance looking into the source of \(M_1\) with \(g_\mathrm{m12}^{-1}\)). With the approximation that \(g_\mathrm{m}\gg g_\mathrm{ds}\) the parallel connection of \(g_\mathrm{m12}\) and \(g_\mathrm{ds5}\) is dominated by \(g_\mathrm{m12}\) and series connection by \(g_\mathrm{ds2}\). Therefore, we can move \(g_\mathrm{ds2} + g_\mathrm{ds4}\) in parallel to \(C_\mathrm{load}\). Further, assuming a differential drive with a virtual ground at the tailpoint we can remove \(g_\mathrm{ds5}\). The current source \(g_\mathrm{m34} v_\mathrm{gs34}\) is replace with the equivalent conductance \(g_\mathrm{m34}\). This results in the further simplified equivalent circuit shown in Figure 27.

    - +
    -Figure 26: 5-transistor OTA small-signal model with further simplifications. +Figure 27: 5-transistor OTA small-signal model with further simplifications.
    -

    In the simplified circuit model in Figure 26 we can see that we have two poles in the circuit, one at the gate note of \(M_{3,4}\), and one at the output. Realizing that \(v_\mathrm{in,p} = v_\mathrm{in}/2\) and \(v_\mathrm{in,n} = - v_\mathrm{in}/2\) we can formulate KCL at the output node to \[ +

    In the simplified circuit model in Figure 27 we can see that we have two poles in the circuit, one at the gate note of \(M_{3,4}\), and one at the output. Realizing that \(v_\mathrm{in,p} = v_\mathrm{in}/2\) and \(v_\mathrm{in,n} = - v_\mathrm{in}/2\) we can formulate KCL at the output node to \[ -g_\mathrm{m34} V_\mathrm{gs34} - \left( -g_\mathrm{m12} \frac{V_\mathrm{in}}{2} \right) - V_\mathrm{out} (g_\mathrm{ds2} + g_\mathrm{ds4} + s C_\mathrm{load}) = 0. \tag{14}\] We further realize that \[ V_\mathrm{gs34} = -g_\mathrm{m12} \frac{V_\mathrm{in}}{2} \frac{1}{g_\mathrm{m34} + s C_\mathrm{gs34}}. @@ -1924,16 +1969,16 @@

    8.3.2 OTA Noise

    -

    For the noise analysis we ignore the pole-zero doublet due to \(C_\mathrm{gs34}\) (we assume minor impact due to this) and just consider the dominant pole. For the noise analysis at the output we set the input signal to zero, and thus we arrive at the simplified small-signal circuit shown in Figure 27.

    +

    For the noise analysis we ignore the pole-zero doublet due to \(C_\mathrm{gs34}\) (we assume minor impact due to this) and just consider the dominant pole. For the noise analysis at the output we set the input signal to zero, and thus we arrive at the simplified small-signal circuit shown in Figure 28.

    - +
    -Figure 27: 5-transistor OTA small-signal model for noise calculation. +Figure 28: 5-transistor OTA small-signal model for noise calculation.
    @@ -1961,16 +2006,16 @@

    As a next step, let us rewrite the OTA transfer function \(A(s)\) (see Equation 16) by getting rid of the pole-zero doublet as a simplifying assumption to get \[ A'(s) = \frac{g_\mathrm{m12}}{g_\mathrm{ds2} + g_\mathrm{ds4} + s C_\mathrm{load}}. \tag{19}\]

    -

    Inspecting Equation 19 we can interpret the OTA transfer function as a transconductor \(g_\mathrm{m12}\) driving a load of \(Y_\mathrm{load} = g_\mathrm{ds2} + g_\mathrm{ds4} + s C_\mathrm{load}\). We can thus redraw Figure 24 in the following way, injecting the previously calculated noise current into the output node. The result is shown in Figure 29.

    +

    Inspecting Equation 19 we can interpret the OTA transfer function as a transconductor \(g_\mathrm{m12}\) driving a load of \(Y_\mathrm{load} = g_\mathrm{ds2} + g_\mathrm{ds4} + s C_\mathrm{load}\). We can thus redraw Figure 25 in the following way, injecting the previously calculated noise current into the output node. The result is shown in Figure 30.

    - +
    -Figure 28: Output impedance calculation of a voltage buffer. +Figure 29: Output impedance calculation of a voltage buffer.
    @@ -1986,7 +2031,7 @@

    -

    First we short the input terminal to ground and then we connect a current source \(I_\mathrm{out}\) at the output terminal, see Figure 28. Since we can neglect the gate leakage current into the inverting input terminal of the OTA, KCL at the output node is simply: \[ +

    First we short the input terminal to ground and then we connect a current source \(I_\mathrm{out}\) at the output terminal, see Figure 29. Since we can neglect the gate leakage current into the inverting input terminal of the OTA, KCL at the output node is simply: \[ I_\mathrm{out} + g_\mathrm{m12}\left(-V_\mathrm{out}\right) = 0 \] Thus, the output impedance is easily calculated. \[ Z_\mathrm{out} = \frac{V_\mathrm{out}}{I_\mathrm{out}} = \frac{V_\mathrm{out}}{g_\mathrm{m12}V_\mathrm{out}} = \frac{1}{g_\mathrm{m12}} @@ -1998,10 +2043,10 @@

    - +
    -Figure 29: A voltage buffer redrawn for noise analysis. +Figure 30: A voltage buffer redrawn for noise analysis.

    @@ -2294,7 +2339,7 @@

    -

    Please design the circuit of the 5T-OTA. Put the OTA circuit in a separate schematic, create a symbol for it, and use this symbol in a testbench you create in Xschem for this 5T-OTA used as a voltage buffer as shown in Figure 24. Use typical conditions for the simulation, and check how well the specification in Table 2 is met, and how well the derivations in Section 8.2 and Section 8.3 fit to the simulation results.

    +

    Please design the circuit of the 5T-OTA. Put the OTA circuit in a separate schematic, create a symbol for it, and use this symbol in a testbench you create in Xschem for this 5T-OTA used as a voltage buffer as shown in Figure 25. Use typical conditions for the simulation, and check how well the specification in Table 2 is met, and how well the derivations in Section 8.2 and Section 8.3 fit to the simulation results.

    If you get stuck, you can find the testbench and 5T-OTA schematic here (for the small-signal analysis) and here (for the large-signal settling simulation).

    @@ -2415,7 +2460,7 @@

    Plots

    gain_vs_temp

    -

    gain_vs_temp

    +

    gain_vs_temp

    gain_vs_temp
    @@ -2424,7 +2469,7 @@

    gain_vs_t

    gain_vs_vin

    -

    gain_vs_vin

    +

    gain_vs_vin

    gain_vs_vin
    @@ -2433,7 +2478,7 @@

    gain_vs_vi

    gain_vs_vdd

    -

    gain_vs_vdd

    +

    gain_vs_vdd

    gain_vs_vdd
    @@ -2442,7 +2487,7 @@

    gain_vs_vd

    gain_vs_corner

    -

    gain_vs_corner

    +

    gain_vs_corner

    gain_vs_corner
    @@ -2451,7 +2496,7 @@

    gain_vs

    bw_vs_temp

    -

    bw_vs_temp

    +

    bw_vs_temp

    bw_vs_temp
    @@ -2460,7 +2505,7 @@

    bw_vs_temp<

    bw_vs_vin

    -

    bw_vs_vin

    +

    bw_vs_vin

    bw_vs_vin
    @@ -2469,7 +2514,7 @@

    bw_vs_vinbw_vs_vdd

    -

    bw_vs_vdd

    +

    bw_vs_vdd

    bw_vs_vdd
    @@ -2478,7 +2523,7 @@

    bw_vs_vddbw_vs_corner

    -

    bw_vs_corner

    +

    bw_vs_corner

    bw_vs_corner
    @@ -2487,7 +2532,7 @@

    bw_vs_cor

    noise_vs_temp

    -

    noise_vs_temp

    +

    noise_vs_temp

    noise_vs_temp
    @@ -2496,7 +2541,7 @@

    noise_vs

    noise_vs_vin

    -

    noise_vs_vin

    +

    noise_vs_vin

    noise_vs_vin
    @@ -2505,7 +2550,7 @@

    noise_vs_

    noise_vs_vdd

    -

    noise_vs_vdd

    +

    noise_vs_vdd

    noise_vs_vdd
    @@ -2514,7 +2559,7 @@

    noise_vs_

    noise_vs_corner

    -

    noise_vs_corner

    +

    noise_vs_corner

    noise_vs_corner
    @@ -2523,7 +2568,7 @@

    noise_

    settling_vs_temp

    -

    settling_vs_temp

    +

    settling_vs_temp

    settling_vs_temp
    @@ -2532,7 +2577,7 @@

    settl

    settling_vs_vin

    -

    settling_vs_vin

    +

    settling_vs_vin

    settling_vs_vin
    @@ -2541,7 +2586,7 @@

    settli

    settling_vs_vdd

    -

    settling_vs_vdd

    +

    settling_vs_vdd

    settling_vs_vdd
    @@ -2550,7 +2595,7 @@

    settli

    settling_vs_corner

    -

    settling_vs_corner

    +

    settling_vs_corner

    settling_vs_corner
    @@ -2566,33 +2611,33 @@

    9 Cascode Stage

    -

    As we have seen in Section 8 the performance of the OTA is generally quite acceptable (see Table 2), but we might want to aim for better output voltage accuracy. As our analysis has shown the output voltage tolerance is limited by the open-loop dc gain \(A_0\) of the OTA (see Equation 13), which in turn is limited by the output conductance of \(M_2\) and \(M_4\) in Figure 23, which is also confirmed by the analytical result in Equation 17.

    +

    As we have seen in Section 8 the performance of the OTA is generally quite acceptable (see Table 2), but we might want to aim for better output voltage accuracy. As our analysis has shown the output voltage tolerance is limited by the open-loop dc gain \(A_0\) of the OTA (see Equation 13), which in turn is limited by the output conductance of \(M_2\) and \(M_4\) in Figure 24, which is also confirmed by the analytical result in Equation 17.

    During the sizing procedure we have seen that the achievable \(g_\mathrm{m}/ g_\mathrm{ds}\) ratio of a single MOSFET is limited, even if we increase \(L\). We are thus searching for a better option, and here (local) feedback in form of a cascode comes to help.

    -

    For analysis of a cascode, we use the following single-transistor stage shown in Figure 30.

    +

    For analysis of a cascode, we use the following single-transistor stage shown in Figure 31.

    - +
    -Figure 30: A MOSFET cascode circuit. +Figure 31: A MOSFET cascode circuit.
    -

    In order to derive the operation of the cascode analytically, we draw the small-signal equivalent circuit in Figure 31. We assume that \(V_\mathrm{B}\) is a low-ohmic bias voltage, thus we replace it by ac ground. We further set \(g_\mathrm{mb}= 0\).

    +

    In order to derive the operation of the cascode analytically, we draw the small-signal equivalent circuit in Figure 32. We assume that \(V_\mathrm{B}\) is a low-ohmic bias voltage, thus we replace it by ac ground. We further set \(g_\mathrm{mb}= 0\).

    - +
    -Figure 31: The MOSFET cascode small-signal model. +Figure 32: The MOSFET cascode small-signal model.
    @@ -2604,10 +2649,10 @@

    9 Cascode Stage
    - +
    -Figure 32: The simplified MOSFET cascode small-signal model. +Figure 33: The simplified MOSFET cascode small-signal model.

    @@ -2615,16 +2660,16 @@

    9 Cascode Stage

    9.1 Cascode Output Impedance

    -

    As a first step, we want to calculate the output impedance at the drain of the MOSFET (i.e., looking into the drain). For this, we replace \(G_\mathrm{D}\) with a current source. The resulting small-signal equivalent circuit is shown in Figure 33.

    +

    As a first step, we want to calculate the output impedance at the drain of the MOSFET (i.e., looking into the drain). For this, we replace \(G_\mathrm{D}\) with a current source. The resulting small-signal equivalent circuit is shown in Figure 34.

    - +
    -Figure 33: The simplified MOSFET cascode small-signal model for calculation of the output impedance. +Figure 34: The simplified MOSFET cascode small-signal model for calculation of the output impedance.
    @@ -2658,16 +2703,16 @@

    9.2 Cascode Input Impedance

    -

    To calculate the input impedance of a cascode (i.e., looking into the source) we replace \(G_\mathrm{S}\) with a current source. The resulting small-signal equivalent circuit is shown in Figure 34.

    +

    To calculate the input impedance of a cascode (i.e., looking into the source) we replace \(G_\mathrm{S}\) with a current source. The resulting small-signal equivalent circuit is shown in Figure 35.

    - +
    -Figure 34: The simplified MOSFET cascode small-signal model for calculation of the input impedance. +Figure 35: The simplified MOSFET cascode small-signal model for calculation of the input impedance.
    @@ -2698,16 +2743,16 @@

    10 Improved OTA

    -

    With the new learned know-how of the cascode stage we can set out to improve our original basic 5T-OTA design. Essentially this means to add cascodes to \(M_2\) and \(M_4\) in Figure 23. For symmetry reasons we will add cascodes to both sides, and the resulting schematic is shown in Figure 35.

    +

    With the new learned know-how of the cascode stage we can set out to improve our original basic 5T-OTA design. Essentially this means to add cascodes to \(M_2\) and \(M_4\) in Figure 24. For symmetry reasons we will add cascodes to both sides, and the resulting schematic is shown in Figure 36.

    - +
    -Figure 35: The improved OTA based on the 5T-OTA design. +Figure 36: The improved OTA based on the 5T-OTA design.
    @@ -2738,7 +2783,7 @@

    10 Improved OTA<

    -

    Try to verify the above statement of equal drain-source voltages by deriving both, an equation for \(V_\mathrm{DS5}\) assuming a high-swing cascode current mirror (Figure 35) and \(V_\mathrm{DS5}\) in case of a simple cascode current mirror, where the reference branch \((M_\mathrm{6/6C})\) is comprised of two mosfet diodes.

    +

    Try to verify the above statement of equal drain-source voltages by deriving both, an equation for \(V_\mathrm{DS5}\) assuming a high-swing cascode current mirror (Figure 36) and \(V_\mathrm{DS5}\) in case of a simple cascode current mirror, where the reference branch \((M_\mathrm{6/6C})\) is comprised of two mosfet diodes.

    Further, by properly selecting the bias voltages of the cascode a low-voltage operation is achieved as \(V_\mathrm{DS}\) can be minimized, allowing even triode operation of the current-mirror MOSFETs (as, noted above, a large \(g_\mathrm{ds}\) is not a big issue).

    @@ -3063,14 +3108,14 @@

    Sizing for Basic (Improved) OTA

    10.2 Designing the Improved OTA

    Based on the collected experience in this lecture and the result of the sizing procedure in Section 10.1 you should be able to design this OTA. If you want, please go ahead and try an implementation and check its performance with CACE.

    -

    As an alternative there is a prepared OTA design shown in Figure 36 which we will discuss in detail next.

    +

    As an alternative there is a prepared OTA design shown in Figure 37 which we will discuss in detail next.

    - +
    -Figure 36: Improved OTA design in Xschem. +Figure 37: Improved OTA design in Xschem.
    @@ -3078,7 +3123,7 @@

    10.2.1 Discussion of the OTA Design

    We will now do an analysis of the circuit design of the OTA including all the complications which make this design practical.

      -
    1. For easier navigation, the device identifier are consistent with the circuit sketch in Figure 35.
      2. +
    2. For easier navigation, the device identifier are consistent with the circuit sketch in Figure 36.
    3. Some MOSFET dimensions are rounded to make a better fit in IC layout. Please also look carefully at \(W\), \(L\), and \(\mathrm{ng}\). The parameter \(\mathrm{ng}\) sets how the total \(W\) of a MOSFET should be split into individual MOSFET fingers with \(W_\mathrm{f} = W / \mathrm{ng}\). This is done to arrive at a suitably sized MOSFET physical implementation. As we will not deal with IC layout in this lecture we will leave it at that.
    4. In order to allow good matching in the IC layout, MOSFETs (and other components) have to be constructed from equal pieces. To that end, \(W/L\) scaling is done using unit elements (see finger width \(W_\mathrm{f}\)). Sometimes, besides \(W\) the length \(L\) has to be scaled, and this leads to the oddly-looking series stacking of some MOSFET (easily recognizable by the connected gates). In order to increase circuit readability, a subcircuit could be constructed hiding this series stacking of MOSFET, but it is sometimes easier to avoid subcircuits. There is a fine line in this trade, sometime a depth of 4 is the decision point between subcircuit use/no-use.
    5. As you can (hopefully) see the circuit is carefully drawn to ease readability. Important nets are named, text comments state certain properties like nominal voltage levels, bias currents, etc. Current sensing elements are added to directly see the dc currents in the circuit simulation.
      6. @@ -3087,14 +3132,14 @@

      \(M_{\mathrm{pd,}x}\) are added to allow a proper shutdown of the circuit with a digital enable input. It is generally a good idea to clamp floating nodes in off-mode so that no issues during power-down (like increased leakage currents) or delayed startup or shutdown are occurring. It is further a good design principle to buffer all incoming digital signals with inverters connected to the local supply. This lowers the risk of unwanted noise coupling or excessive slew rates on the incoming digital signals.
    6. Sensitive bias nodes are buffered with decoupling capacitors. We are using MOSFET as nonlinear capacitors, which is not an issue in this application, but we value the increased capacitive density. Please note how the MOSFET are connected (to \(V_\mathrm{DD}\)? or to \(V_\mathrm{SS}\)?).

    -

    The resistor used in this circuit are subcircuits to allow series connection of unit resistor elements. The schematic of one element is shown in Figure 37. It is using an effective method to create a series string of connected resistors using wire bundles. Try to understand the circuit, consult the Xschem manual, and look at the resulting SPICE netlist to confirm your finding.

    +

    The resistor used in this circuit are subcircuits to allow series connection of unit resistor elements. The schematic of one element is shown in Figure 38. It is using an effective method to create a series string of connected resistors using wire bundles. Try to understand the circuit, consult the Xschem manual, and look at the resulting SPICE netlist to confirm your finding.

    - +
    -Figure 37: Series resistor implementation used in the improved OTA design. +Figure 38: Series resistor implementation used in the improved OTA design.
    @@ -3115,24 +3160,24 @@

    10.3 Simulation of Improved OTA

    -

    Now that the circuit design of the improved OTA is done, we an use the same simulation test bench as for the basic OTA. The testbench is shown in Figure 38 and Figure 39.

    +

    Now that the circuit design of the improved OTA is done, we an use the same simulation test bench as for the basic OTA. The testbench is shown in Figure 39 and Figure 40.

    - +
    -Figure 38: Simulation testbench of the improved OTA design (small-signal). +Figure 39: Simulation testbench of the improved OTA design (small-signal).
    - +
    -Figure 39: Simulation testbench of the improved OTA design (large-signal). +Figure 40: Simulation testbench of the improved OTA design (large-signal).
    @@ -3258,7 +3303,7 @@

    Plots

    gain_vs_temp

    -

    gain_vs_temp

    +

    gain_vs_temp

    gain_vs_temp
    @@ -3267,7 +3312,7 @@

    gain_vs

    gain_vs_vin

    -

    gain_vs_vin

    +

    gain_vs_vin

    gain_vs_vin
    @@ -3276,7 +3321,7 @@

    gain_vs_

    gain_vs_vdd

    -

    gain_vs_vdd

    +

    gain_vs_vdd

    gain_vs_vdd
    @@ -3285,7 +3330,7 @@

    gain_vs_

    gain_vs_corner

    -

    gain_vs_corner

    +

    gain_vs_corner

    gain_vs_corner
    @@ -3294,7 +3339,7 @@

    gain_

    bw_vs_temp

    -

    bw_vs_temp

    +

    bw_vs_temp

    bw_vs_temp
    @@ -3303,7 +3348,7 @@

    bw_vs_tem

    bw_vs_vin

    -

    bw_vs_vin

    +

    bw_vs_vin

    bw_vs_vin
    @@ -3312,7 +3357,7 @@

    bw_vs_vin<

    bw_vs_vdd

    -

    bw_vs_vdd

    +

    bw_vs_vdd

    bw_vs_vdd
    @@ -3321,7 +3366,7 @@

    bw_vs_vdd<

    bw_vs_corner

    -

    bw_vs_corner

    +

    bw_vs_corner

    bw_vs_corner
    @@ -3330,7 +3375,7 @@

    bw_vs_c

    noise_vs_temp

    -

    noise_vs_temp

    +

    noise_vs_temp

    noise_vs_temp
    @@ -3339,7 +3384,7 @@

    noise_

    noise_vs_vin

    -

    noise_vs_vin

    +

    noise_vs_vin

    noise_vs_vin
    @@ -3348,7 +3393,7 @@

    noise_v

    noise_vs_vdd

    -

    noise_vs_vdd

    +

    noise_vs_vdd

    noise_vs_vdd
    @@ -3357,7 +3402,7 @@

    noise_v

    noise_vs_corner

    -

    noise_vs_corner

    +

    noise_vs_corner

    noise_vs_corner
    @@ -3366,7 +3411,7 @@

    nois

    settling_vs_temp

    -

    settling_vs_temp

    +

    settling_vs_temp

    settling_vs_temp
    @@ -3375,7 +3420,7 @@

    set

    settling_vs_vin

    -

    settling_vs_vin

    +

    settling_vs_vin

    settling_vs_vin
    @@ -3384,7 +3429,7 @@

    sett

    settling_vs_vdd

    -

    settling_vs_vdd

    +

    settling_vs_vdd

    settling_vs_vdd
    @@ -3393,7 +3438,7 @@

    sett

    settling_vs_corner

    -

    settling_vs_corner

    +

    settling_vs_corner

    settling_vs_corner
    @@ -3492,16 +3537,16 @@

    14 Summary &

    15 Appendix: Middlebrook’s Method

    -

    When we want to do a closed-loop gain analysis (for stability or other investigations), we have the need to break the loop at one point, apply a stimulus, and monitor the response on the other end. By doing this we want to keep the loading on both ends similar to the original case. To achieve this, we break the loop at one point by inserting (1) an ac voltage source, and (2) attach an ac current source, as shown in Figure 40 and Figure 41. The derivation of this approach is presented in (Middlebrook 1975), and has the big advantage that loading is not changed, and the bias points are also correct.

    +

    When we want to do a closed-loop gain analysis (for stability or other investigations), we have the need to break the loop at one point, apply a stimulus, and monitor the response on the other end. By doing this we want to keep the loading on both ends similar to the original case. To achieve this, we break the loop at one point by inserting (1) an ac voltage source, and (2) attach an ac current source, as shown in Figure 41 and Figure 42. The derivation of this approach is presented in (Middlebrook 1975), and has the big advantage that loading is not changed, and the bias points are also correct.

    - +
    -Figure 40: Middlebrook voltage loop gain simulation. +Figure 41: Middlebrook voltage loop gain simulation.
    @@ -3512,10 +3557,10 @@

    15 Appendix: Mid
    - +
    -Figure 41: Middlebrook current loop gain simulation. +Figure 42: Middlebrook current loop gain simulation.
    @@ -3532,16 +3577,16 @@

    15 Appendix: Mid

    16 Appendix: Miller’s Theorem

    -

    Using Miller’s theorem we can find the equivalent circuit of an impedance connected between two nodes, and we know the transfer function between these nodes. The given situation is shown in Figure 42, and the equivalent circuit is shown in Figure 43.

    +

    Using Miller’s theorem we can find the equivalent circuit of an impedance connected between two nodes, and we know the transfer function between these nodes. The given situation is shown in Figure 43, and the equivalent circuit is shown in Figure 44.

    - +
    -Figure 42: An impedance connected between two nodes A and B. +Figure 43: An impedance connected between two nodes A and B.
    @@ -3552,10 +3597,10 @@

    16 Appendix: Mil
    - +
    -Figure 43: An equivalent circuit using Miller’s theorem. +Figure 44: An equivalent circuit using Miller’s theorem.
    @@ -3577,10 +3622,10 @@

    17 Appendix: 5T-
    - +
    -Figure 44: 5-transistor OTA small-signal model for output impedance calculations. +Figure 45: 5-transistor OTA small-signal model for output impedance calculations.
    @@ -4365,7 +4410,7 @@

    -