diff --git a/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v b/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v
index 1b32be20d..6362479d3 100644
--- a/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -211,4 +210,3 @@ module caravan_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
index a6bd94dfb..3a5ff65c2 100644
--- a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -193,4 +192,3 @@ module gpio_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
index e7af16e4a..53a8c2264 100644
--- a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*	
 	StriVe housekeeping SPI testbench.
 */
@@ -428,4 +427,3 @@ module hkspi_tb;
 	);
 		
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
index 4aa244a3b..a2ef3bc42 100644
--- a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -200,4 +199,3 @@ module mem_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
index 6ddfca37d..12f98afcd 100644
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 `timescale 1 ns / 1 ps
 
@@ -173,4 +172,3 @@ module mprj_ctrl_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
index dea8dba05..5aa45b66a 100644
--- a/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*	
  *	StriVe housekeeping pass-thru mode SPI testbench.
  */
@@ -347,4 +346,3 @@ module pass_thru_tb;
 	);
 		
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
index 25798ec24..85b292818 100644
--- a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -156,4 +155,3 @@ module perf_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
index 5c037b06a..180579125 100644
--- a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 `timescale 1 ns / 1 ps
 
@@ -155,4 +154,3 @@ module pll_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v b/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v
index d8683b993..ad925d688 100644
--- a/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -202,4 +201,3 @@ module qspi_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v b/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
index 0adee87b9..d380ee3fa 100644
--- a/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -187,4 +186,3 @@ module storage_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
index a39e689f5..c1ba5d4c5 100644
--- a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 `timescale 1 ns / 1 ps
 
@@ -217,4 +216,3 @@ module sysctrl_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
index 3865bf333..0e3365c44 100644
--- a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -198,4 +197,3 @@ module timer_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
index a53e216d1..94ce8a566 100644
--- a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -226,4 +225,3 @@ module timer2_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
index d8bbd35ec..dad0a9f85 100644
--- a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -147,4 +146,3 @@ module uart_tb;
 	);
 		
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/spiflash.v b/verilog/dv/caravel/spiflash.v
index 6aa29baac..7af4ec19a 100644
--- a/verilog/dv/caravel/spiflash.v
+++ b/verilog/dv/caravel/spiflash.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017 Clifford Wolf
  *
diff --git a/verilog/dv/caravel/tbuart.v b/verilog/dv/caravel/tbuart.v
index bac9480e1..b0e87a27d 100644
--- a/verilog/dv/caravel/tbuart.v
+++ b/verilog/dv/caravel/tbuart.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017 Clifford Wolf
  *
diff --git a/verilog/dv/dummy_slave.v b/verilog/dv/dummy_slave.v
index be068fc5b..876e8f855 100644
--- a/verilog/dv/dummy_slave.v
+++ b/verilog/dv/dummy_slave.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 module dummy_slave(
     input wb_clk_i,
     input wb_rst_i,
diff --git a/verilog/dv/wb_utests/chip_io/chip_io_tb.v b/verilog/dv/wb_utests/chip_io/chip_io_tb.v
index 4a004cdaf..01fdeacb6 100644
--- a/verilog/dv/wb_utests/chip_io/chip_io_tb.v
+++ b/verilog/dv/wb_utests/chip_io/chip_io_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 `timescale 1 ns / 1 ps
 
diff --git a/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v b/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
index ea6c7726f..5821c6fee 100644
--- a/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
+++ b/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v b/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v
index 4f6fd387d..35324a8f0 100644
--- a/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v
+++ b/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/la_wb/la_wb_tb.v b/verilog/dv/wb_utests/la_wb/la_wb_tb.v
index a1c10abf0..9e3087ea7 100644
--- a/verilog/dv/wb_utests/la_wb/la_wb_tb.v
+++ b/verilog/dv/wb_utests/la_wb/la_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 `timescale 1 ns / 1 ps
 
 `include "la_wb.v"
diff --git a/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v b/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
index cfc82aacf..9fcec4a58 100644
--- a/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
+++ b/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/mgmt_protect/mgmt_protect_tb.v b/verilog/dv/wb_utests/mgmt_protect/mgmt_protect_tb.v
index b90afa8c7..9a4ac5d79 100644
--- a/verilog/dv/wb_utests/mgmt_protect/mgmt_protect_tb.v
+++ b/verilog/dv/wb_utests/mgmt_protect/mgmt_protect_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
index fd9e5a240..242464516 100644
--- a/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
+++ b/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v b/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
index 99cb0081c..86cc9b4cf 100644
--- a/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
+++ b/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v b/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v
index c474fd062..cac66be0b 100644
--- a/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v
+++ b/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v b/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v
index c9aa7682b..2377de5cf 100644
--- a/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v
+++ b/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 // `define DBG
 
 `define STORAGE_BASE_ADR  32'h0100_0000
diff --git a/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
index 77140c753..c9fb757c4 100644
--- a/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
+++ b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 `timescale 1 ns / 1 ps
 
diff --git a/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v b/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v
index da481512a..9ee7878e4 100644
--- a/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v
+++ b/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/gl/__user_project_wrapper.v b/verilog/gl/__user_project_wrapper.v
index eed6cd759..f7a753a0f 100644
--- a/verilog/gl/__user_project_wrapper.v
+++ b/verilog/gl/__user_project_wrapper.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*
  *-------------------------------------------------------------
  *
diff --git a/verilog/gl/gpio_control_block.v b/verilog/gl/gpio_control_block.v
index 2488ba236..c550e25a6 100644
--- a/verilog/gl/gpio_control_block.v
+++ b/verilog/gl/gpio_control_block.v
@@ -1,4 +1,3 @@
-`default_nettype wire
 module gpio_control_block (mgmt_gpio_in,
     mgmt_gpio_oeb,
     mgmt_gpio_out,
diff --git a/verilog/gl/storage.v b/verilog/gl/storage.v
index f212dc2ad..6e71a98b5 100644
--- a/verilog/gl/storage.v
+++ b/verilog/gl/storage.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
 
 module storage(mgmt_clk, mgmt_ena_ro, VPWR, VGND, mgmt_addr, mgmt_addr_ro, mgmt_ena, mgmt_rdata, mgmt_rdata_ro, mgmt_wdata, mgmt_wen, mgmt_wen_mask);
diff --git a/verilog/rtl/DFFRAM.v b/verilog/rtl/DFFRAM.v
index b80677f2b..494cac9a2 100644
--- a/verilog/rtl/DFFRAM.v
+++ b/verilog/rtl/DFFRAM.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 `ifndef USE_CUSTOM_DFFRAM
 
 module DFFRAM(
diff --git a/verilog/rtl/DFFRAMBB.v b/verilog/rtl/DFFRAMBB.v
index 22ab55eb1..00f977a9a 100644
--- a/verilog/rtl/DFFRAMBB.v
+++ b/verilog/rtl/DFFRAMBB.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*
     Building blocks for DFF based RAM compiler for SKY130A 
     BYTE        :   8 memory cells used as a building block for WORD module
diff --git a/verilog/rtl/__user_analog_project_wrapper.v b/verilog/rtl/__user_analog_project_wrapper.v
index 5fd2096e5..621c7e1c5 100644
--- a/verilog/rtl/__user_analog_project_wrapper.v
+++ b/verilog/rtl/__user_analog_project_wrapper.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*
  *-------------------------------------------------------------
  *
diff --git a/verilog/rtl/__user_project_wrapper.v b/verilog/rtl/__user_project_wrapper.v
index a6d8911b2..684c16e76 100644
--- a/verilog/rtl/__user_project_wrapper.v
+++ b/verilog/rtl/__user_project_wrapper.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*
  *-------------------------------------------------------------
  *
diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v
index da9d245ed..4e5b3be65 100644
--- a/verilog/rtl/caravan.v
+++ b/verilog/rtl/caravan.v
@@ -1,4 +1,3 @@
-// `default_nettype none
 // SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
@@ -864,4 +863,3 @@ module caravan (
 	);
 
 endmodule
-// `default_nettype wire
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 1cbc60534..8edba2b8d 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -1,4 +1,3 @@
-// `default_nettype none
 // SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
@@ -801,4 +800,3 @@ module caravel (
 	);
 
 endmodule
-// `default_nettype wire
diff --git a/verilog/rtl/caravel_clocking.v b/verilog/rtl/caravel_clocking.v
index cc0af252b..18db9e28b 100644
--- a/verilog/rtl/caravel_clocking.v
+++ b/verilog/rtl/caravel_clocking.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 // This routine synchronizes the 
 
 module caravel_clocking(
@@ -108,4 +107,3 @@ module caravel_clocking(
     assign resetb_sync = ~(reset_delay[0] | ext_reset);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index 39529c507..82b1be62a 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-// `default_nettype none
 module chip_io(
 	// Package Pins
 	inout  vddio,		// Common padframe/ESD supply
@@ -362,4 +361,3 @@ module chip_io(
 	);
 
 endmodule
-// `default_nettype wire
diff --git a/verilog/rtl/chip_io_alt.v b/verilog/rtl/chip_io_alt.v
index 799403dfe..b47bda6f2 100644
--- a/verilog/rtl/chip_io_alt.v
+++ b/verilog/rtl/chip_io_alt.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-// `default_nettype none
 
 /* Alternative padframe that removes the GPIO from the top row,	*/
 /* replacing them with un-overlaid power pads which have a	*/
@@ -446,4 +445,3 @@ module chip_io_alt #(
 	);
 
 endmodule
-// `default_nettype wire
diff --git a/verilog/rtl/clock_div.v b/verilog/rtl/clock_div.v
index 49ff44bf6..8bf21c798 100644
--- a/verilog/rtl/clock_div.v
+++ b/verilog/rtl/clock_div.v
@@ -14,7 +14,6 @@
 // SPDX-License-Identifier: Apache-2.0
 
 /* Integer-N clock divider */
-`default_nettype none
  
 module clock_div #(
     parameter SIZE = 3		// Number of bits for the divider value
@@ -210,4 +209,3 @@ module even #(
     end
  
 endmodule //even
-`default_nettype wire
diff --git a/verilog/rtl/convert_gpio_sigs.v b/verilog/rtl/convert_gpio_sigs.v
index e9e835102..2c9735e19 100644
--- a/verilog/rtl/convert_gpio_sigs.v
+++ b/verilog/rtl/convert_gpio_sigs.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /* Convert the standard set of GPIO signals: input, output, output_enb,
  * pullup, and pulldown into the set needed by the s8 GPIO pads:
  * input, output, output_enb, input_enb, mode.  Note that dm[2] on
@@ -48,4 +47,3 @@ module convert_gpio_sigs (
     assign gpio_mode0_pad = gpio_outenb;
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/counter_timer_high.v b/verilog/rtl/counter_timer_high.v
index e91d7ecef..80fc33b72 100755
--- a/verilog/rtl/counter_timer_high.v
+++ b/verilog/rtl/counter_timer_high.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /* Simple 32-bit counter-timer for Caravel. */
 
 /* Counter acts as high 32 bits of a 64-bit counter
@@ -287,4 +286,3 @@ always @(posedge clkin or negedge resetn) begin
 end
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/counter_timer_low.v b/verilog/rtl/counter_timer_low.v
index 8d75adf8f..3e2d9343e 100755
--- a/verilog/rtl/counter_timer_low.v
+++ b/verilog/rtl/counter_timer_low.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /* Simple 32-bit counter-timer for Caravel. */
 
 /* Counter acts as low 32 bits of a 64-bit counter
@@ -319,4 +318,3 @@ always @(posedge clkin or negedge resetn) begin
 end
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v
index 7fefe52db..a59f3643f 100644
--- a/verilog/rtl/defines.v
+++ b/verilog/rtl/defines.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 `ifndef __GLOBAL_DEFINE_H
 // Global parameters
diff --git a/verilog/rtl/digital_pll.v b/verilog/rtl/digital_pll.v
index b8dd69e9a..9e5092ac5 100644
--- a/verilog/rtl/digital_pll.v
+++ b/verilog/rtl/digital_pll.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 // Digital PLL (ring oscillator + controller)
 // Technically this is a frequency locked loop, not a phase locked loop.
 
@@ -68,4 +67,3 @@ module digital_pll(
     );
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/digital_pll_controller.v b/verilog/rtl/digital_pll_controller.v
index ae13d9d10..68e8c4352 100644
--- a/verilog/rtl/digital_pll_controller.v
+++ b/verilog/rtl/digital_pll_controller.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 // (True) digital PLL
 //
 // Output goes to a trimmable ring oscillator (see documentation).
@@ -133,4 +132,3 @@ module digital_pll_controller(reset, clock, osc, div, trim);
     end
 
 endmodule	// digital_pll_controller
-`default_nettype wire
diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v
index 4f22b2ba1..665ee69ac 100644
--- a/verilog/rtl/gpio_control_block.v
+++ b/verilog/rtl/gpio_control_block.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /* 
  *---------------------------------------------------------------------
  * See gpio_control_block for description.  This module is like
@@ -261,4 +260,3 @@ module gpio_control_block #(
     );
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/gpio_wb.v b/verilog/rtl/gpio_wb.v
index 74f260863..ffab49a33 100644
--- a/verilog/rtl/gpio_wb.v
+++ b/verilog/rtl/gpio_wb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 module gpio_wb # (
     parameter BASE_ADR  = 32'h 2100_0000,
     parameter GPIO_DATA = 8'h 00,
@@ -148,4 +147,3 @@ module gpio #(
     end
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/housekeeping_spi.v b/verilog/rtl/housekeeping_spi.v
index 37c27c86a..1540806be 100644
--- a/verilog/rtl/housekeeping_spi.v
+++ b/verilog/rtl/housekeeping_spi.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 //-------------------------------------
 // SPI controller for Caravel (PicoSoC)
 //-------------------------------------
@@ -491,4 +490,3 @@ module housekeeping_spi_slave(reset, SCK, SDI, CSB, SDO,
     end			// always @ SCK
 
 endmodule // housekeeping_spi_slave
-`default_nettype wire
diff --git a/verilog/rtl/la_wb.v b/verilog/rtl/la_wb.v
index fbbc77cf0..eaa058f9d 100644
--- a/verilog/rtl/la_wb.v
+++ b/verilog/rtl/la_wb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 module la_wb # (
     parameter BASE_ADR  = 32'h 2200_0000,
     parameter LA_DATA_0 = 8'h00,
@@ -302,4 +301,3 @@ module la #(
     end
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/mem_wb.v b/verilog/rtl/mem_wb.v
index 44826d727..61d851249 100644
--- a/verilog/rtl/mem_wb.v
+++ b/verilog/rtl/mem_wb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 module mem_wb (
 `ifdef USE_POWER_PINS
     input VPWR,
@@ -137,4 +136,3 @@ module soc_mem
 `endif
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index 79db58c79..814b0809b 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 module mgmt_core (
 `ifdef USE_POWER_PINS
 	inout VPWR,	   
@@ -331,4 +330,3 @@ module mgmt_core (
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/mgmt_protect.v b/verilog/rtl/mgmt_protect.v
index 37b242868..cfc401b7a 100644
--- a/verilog/rtl/mgmt_protect.v
+++ b/verilog/rtl/mgmt_protect.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*----------------------------------------------------------------------*/
 /* Buffers protecting the management region from the user region.	*/
 /* This mainly consists of tristate buffers that are enabled by a	*/
@@ -417,4 +416,3 @@ module mgmt_protect (
                 .X(user2_vdd_powergood)
 	);
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/mgmt_protect_hv.v b/verilog/rtl/mgmt_protect_hv.v
index bedba4931..f6cff356b 100644
--- a/verilog/rtl/mgmt_protect_hv.v
+++ b/verilog/rtl/mgmt_protect_hv.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*----------------------------------------------------------------------*/
 /* mgmt_protect_hv:							*/
 /*									*/
@@ -103,4 +102,3 @@ module mgmt_protect_hv (
     );
 endmodule
 
-`default_nettype wire
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index 5a9ad8eeb..8f4056258 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2015 Clifford Wolf
  *  PicoSoC - A simple example SoC using PicoRV32
@@ -887,4 +886,3 @@ module mgmt_soc_regs (
     assign rdata1 = regs[raddr1[4:0]];
     assign rdata2 = regs[raddr2[4:0]];
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/mprj_ctrl.v b/verilog/rtl/mprj_ctrl.v
index 22118663e..03f762647 100644
--- a/verilog/rtl/mprj_ctrl.v
+++ b/verilog/rtl/mprj_ctrl.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 module mprj_ctrl_wb #(
     parameter BASE_ADR  = 32'h 2300_0000,
     parameter XFER      = 8'h 00,
@@ -424,4 +423,3 @@ module mprj_ctrl #(
     end
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/mprj_io.v b/verilog/rtl/mprj_io.v
index 3a94da0ea..f7958bd84 100644
--- a/verilog/rtl/mprj_io.v
+++ b/verilog/rtl/mprj_io.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-// `default_nettype none
 
 /* Define the array of GPIO pads.  Note that the analog project support
  * version of caravel (caravan) defines fewer GPIO and replaces them
@@ -135,4 +134,3 @@ module mprj_io #(
     );
 
 endmodule
-// `default_nettype wire
diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v
index f89ba9084..306e8ba95 100644
--- a/verilog/rtl/pads.v
+++ b/verilog/rtl/pads.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-// `default_nettype none
 `ifndef TOP_ROUTING 
 	`define USER1_ABUTMENT_PINS \
 	.AMUXBUS_A(analog_a),\
@@ -169,4 +168,3 @@
 		.TIE_HI_ESD(), \
 		.TIE_LO_ESD(loop_``X) )
 
-// `default_nettype wire
diff --git a/verilog/rtl/picorv32.v b/verilog/rtl/picorv32.v
index 13162736c..1249ad53b 100644
--- a/verilog/rtl/picorv32.v
+++ b/verilog/rtl/picorv32.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2015 Clifford Wolf
  *  PicoRV32 -- A Small RISC-V (RV32I) Processor Core
@@ -3045,4 +3044,3 @@ module picorv32_wb #(
 		end
 	end
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/ring_osc2x13.v b/verilog/rtl/ring_osc2x13.v
index f20110e9d..218707073 100644
--- a/verilog/rtl/ring_osc2x13.v
+++ b/verilog/rtl/ring_osc2x13.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 // Tunable ring oscillator---synthesizable (physical) version.
 //
 // NOTE:  This netlist cannot be simulated correctly due to lack
@@ -247,4 +246,3 @@ module ring_osc2x13(reset, trim, clockp);
 `endif // !FUNCTIONAL
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v
index c5197800d..d5d6b55f4 100644
--- a/verilog/rtl/simple_por.v
+++ b/verilog/rtl/simple_por.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 `timescale 1 ns / 1 ps
 
 module simple_por(
@@ -89,4 +88,3 @@ module simple_por(
     // replaced by a proper inverter
     assign por_l = ~porb_l;
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/simple_spi_master.v b/verilog/rtl/simple_spi_master.v
index e1320fd01..bda80a682 100755
--- a/verilog/rtl/simple_spi_master.v
+++ b/verilog/rtl/simple_spi_master.v
@@ -1,4 +1,3 @@
-`default_nettype none
 // SPDX-FileCopyrightText: 2019 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
@@ -397,4 +396,3 @@ module simple_spi_master (
     end // always
  
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/simpleuart.v b/verilog/rtl/simpleuart.v
index 7fd32e40d..24ba06e8f 100644
--- a/verilog/rtl/simpleuart.v
+++ b/verilog/rtl/simpleuart.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2015 Clifford Wolf
  *  PicoSoC - A simple example SoC using PicoRV32
@@ -219,4 +218,3 @@ module simpleuart (
         end
     end
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/spimemio.v b/verilog/rtl/spimemio.v
index 0d3684cbd..ea602cbd7 100644
--- a/verilog/rtl/spimemio.v
+++ b/verilog/rtl/spimemio.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2015 Clifford Wolf
  *  PicoSoC - A simple example SoC using PicoRV32
@@ -743,4 +742,3 @@ module spimemio_xfer (
     end
 endmodule
 
-`default_nettype wire
diff --git a/verilog/rtl/sram_1rw1r_32_256_8_sky130.v b/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
index f62207972..5a23804ee 100644
--- a/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
+++ b/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 // OpenRAM SRAM model
 // Words: 256
 // Word size: 32
@@ -130,4 +129,3 @@ reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
   end
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/storage.v b/verilog/rtl/storage.v
index 01dac0dce..8c6c5d46d 100644
--- a/verilog/rtl/storage.v
+++ b/verilog/rtl/storage.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
  
 module storage (
     // MGMT_AREA R/W Interface 
@@ -62,4 +61,3 @@ module storage (
     );  
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/storage_bridge_wb.v b/verilog/rtl/storage_bridge_wb.v
index 0f2432152..edd48c5af 100644
--- a/verilog/rtl/storage_bridge_wb.v
+++ b/verilog/rtl/storage_bridge_wb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 module storage_bridge_wb (
     // MGMT_AREA R/W WB Interface
     input wb_clk_i,
@@ -109,4 +108,3 @@ module storage_bridge_wb (
     assign wb_ro_dat_o = mgmt_rdata_ro;
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/sysctrl.v b/verilog/rtl/sysctrl.v
index 8929092ce..71af2ab59 100644
--- a/verilog/rtl/sysctrl.v
+++ b/verilog/rtl/sysctrl.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 module sysctrl_wb #(
     parameter BASE_ADR     = 32'h2F00_0000,
     parameter PWRGOOD	   = 8'h00,
@@ -166,4 +165,3 @@ module sysctrl #(
     end
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/user_id_programming.v b/verilog/rtl/user_id_programming.v
index fc53765e7..98c5b9428 100644
--- a/verilog/rtl/user_id_programming.v
+++ b/verilog/rtl/user_id_programming.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 // This module represents an unprogrammed mask revision
 // block that is configured with via programming on the
 // chip top level.  This value is passed to the block as
@@ -53,4 +52,3 @@ module user_id_programming #(
     endgenerate
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/wb_intercon.v b/verilog/rtl/wb_intercon.v
index e84d1a006..4262271cb 100644
--- a/verilog/rtl/wb_intercon.v
+++ b/verilog/rtl/wb_intercon.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 module wb_intercon #(
     parameter DW = 32,          // Data Width
     parameter AW = 32,          // Address Width
@@ -71,4 +70,3 @@ module wb_intercon #(
     end
  
 endmodule
-`default_nettype wire
diff --git a/verilog/stubs/sky130_fd_io__top_xres4v2.v b/verilog/stubs/sky130_fd_io__top_xres4v2.v
index 3fa6736a3..693e6cd55 100644
--- a/verilog/stubs/sky130_fd_io__top_xres4v2.v
+++ b/verilog/stubs/sky130_fd_io__top_xres4v2.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  * SPDX-FileCopyrightText: 2020 The SkyWater PDK Authors
  *