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Spi documentation confusing about CS and master (IDFGH-1268) #3563

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lestofante opened this issue May 29, 2019 · 1 comment
Open

Spi documentation confusing about CS and master (IDFGH-1268) #3563

lestofante opened this issue May 29, 2019 · 1 comment

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@lestofante
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The docs say:

"SPI1, HSPI and VSPI all have three chip select lines, allowing them to drive up to three SPI devices each as a master."

why is there such limitation? shouldn't we be able to control as many CS we want with normal GPIO? From the Datasheet does not appear to have any limitation in this regards
@github-actions github-actions bot changed the title Spi documentation confusing about CS and master Spi documentation confusing about CS and master (IDFGH-1268) May 29, 2019
@negativekelvin
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#3527

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@lestofante @negativekelvin