From 07dcfebdab10cb867d601d361bea083b5d4bfec7 Mon Sep 17 00:00:00 2001 From: Cao Sen Miao Date: Thu, 12 Oct 2023 11:57:04 +0800 Subject: [PATCH] fix(ota): Fixed OTA fail on octal flash with 32MB memory --- .../include/bootloader_flash_override.h | 2 +- .../include/bootloader_flash_priv.h | 2 ++ .../bootloader_flash/src/bootloader_flash.c | 20 ++++++++++++++++++- .../src/bootloader_flash_config_esp32s3.c | 2 +- components/spi_flash/Kconfig | 7 ++++++- 5 files changed, 29 insertions(+), 4 deletions(-) diff --git a/components/bootloader_support/bootloader_flash/include/bootloader_flash_override.h b/components/bootloader_support/bootloader_flash/include/bootloader_flash_override.h index abf7f1fe65..df68b018d2 100644 --- a/components/bootloader_support/bootloader_flash/include/bootloader_flash_override.h +++ b/components/bootloader_support/bootloader_flash/include/bootloader_flash_override.h @@ -109,7 +109,7 @@ extern const bootloader_qio_info_t __attribute__((weak)) bootloader_flash_qe_sup */ esp_err_t __attribute__((weak)) bootloader_flash_unlock(void); -#if CONFIG_SPI_FLASH_32BIT_ADDR_ENABLE +#if CONFIG_SPI_FLASH_QUAD_32BIT_ADDR_ENABLE || CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE /** * @brief Enable 32bits address flash(larger than 16MB) can map to cache. * diff --git a/components/bootloader_support/bootloader_flash/include/bootloader_flash_priv.h b/components/bootloader_support/bootloader_flash/include/bootloader_flash_priv.h index 0a3eef29b3..d8060476ae 100644 --- a/components/bootloader_support/bootloader_flash/include/bootloader_flash_priv.h +++ b/components/bootloader_support/bootloader_flash/include/bootloader_flash_priv.h @@ -56,6 +56,8 @@ extern "C" { #define CMD_FASTRD_QUAD_4B 0x6C #define CMD_FASTRD_DIO_4B 0xBC #define CMD_FASTRD_DUAL_4B 0x3C +#define CMD_FASTRD_4B 0x0C +#define CMD_SLOWRD_4B 0x13 /* Provide a Flash API for bootloader_support code, diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash.c index c75f0d0eeb..5fbd0cc11c 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash.c @@ -426,7 +426,7 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size) return spi_to_esp_err(rc); } -#if CONFIG_SPI_FLASH_32BIT_ADDR_ENABLE +#if CONFIG_SPI_FLASH_QUAD_32BIT_ADDR_ENABLE || CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE void bootloader_flash_32bits_address_map_enable(esp_rom_spiflash_read_mode_t flash_mode) { esp_rom_opiflash_spi0rd_t cache_rd = {}; @@ -455,12 +455,30 @@ void bootloader_flash_32bits_address_map_enable(esp_rom_spiflash_read_mode_t fla cache_rd.cmd = CMD_FASTRD_QIO_4B; cache_rd.cmd_bit_len = 8; break; + case ESP_ROM_SPIFLASH_FASTRD_MODE: + cache_rd.addr_bit_len = 32; + cache_rd.dummy_bit_len = 8; + cache_rd.cmd = CMD_FASTRD_4B; + cache_rd.cmd_bit_len = 8; + break; + case ESP_ROM_SPIFLASH_SLOWRD_MODE: + cache_rd.addr_bit_len = 32; + cache_rd.dummy_bit_len = 0; + cache_rd.cmd = CMD_SLOWRD_4B; + cache_rd.cmd_bit_len = 8; + break; default: assert(false); break; } cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); esp_rom_opiflash_cache_mode_config(flash_mode, &cache_rd); + if (cache_rd.dummy_bit_len == 0) { + // Patch for ROM function `esp_rom_opiflash_cache_mode_config`, because when dummy is 0, + // `SPI_MEM_USR_DUMMY` should be 0. `esp_rom_opiflash_cache_mode_config` doesn't handle this + // properly. + REG_CLR_BIT(SPI_MEM_USER_REG(0), SPI_MEM_USR_DUMMY); + } cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); } #endif diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c index 1b0caa3020..b1f58765df 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c @@ -288,7 +288,7 @@ esp_err_t bootloader_init_spi_flash(void) bootloader_enable_qio_mode(); } #endif -#if CONFIG_SPI_FLASH_32BIT_ADDR_ENABLE +#if CONFIG_SPI_FLASH_QUAD_32BIT_ADDR_ENABLE || CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE bootloader_flash_32bits_address_map_enable(bootloader_flash_get_spi_mode()); #endif print_flash_info(&bootloader_image_hdr); diff --git a/components/spi_flash/Kconfig b/components/spi_flash/Kconfig index f866d21516..66ccb358df 100644 --- a/components/spi_flash/Kconfig +++ b/components/spi_flash/Kconfig @@ -329,7 +329,7 @@ menu "SPI Flash driver" help This is a helper config for 32bits address flash. Invisible for users. - config SPI_FLASH_32BIT_ADDR_ENABLE + config SPI_FLASH_QUAD_32BIT_ADDR_ENABLE bool "Enable 32-bit-address (over 16MB) SPI Flash access" depends on SPI_FLASH_32BIT_ADDRESS && !ESPTOOLPY_OCT_FLASH && IDF_TARGET_ESP32S3 && IDF_EXPERIMENTAL_FEATURES default n @@ -339,4 +339,9 @@ menu "SPI Flash driver" 2. This option is experimental, which means it can't use on all flash chips stable, for more information, please contact Espressif Business support. + config SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE + bool + default y if ESPTOOLPY_OCT_FLASH && SPI_FLASH_32BIT_ADDRESS + default n + endmenu -- 2.25.1