From 98070179b593c6f8a6f27046a3957e30bde32709 Mon Sep 17 00:00:00 2001 From: morris Date: Tue, 18 Jun 2024 23:05:14 +0800 Subject: [PATCH] fix(huk): switch case fall through unexpected --- components/hal/esp32p4/include/hal/huk_ll.h | 44 +++++++++++-------- .../hal/esp32p4/include/hal/lp_i2s_ll.h | 6 +-- 2 files changed, 28 insertions(+), 22 deletions(-) diff --git a/components/hal/esp32p4/include/hal/huk_ll.h b/components/hal/esp32p4/include/hal/huk_ll.h index 6fa5b98f2aa8..6b5a50a64fd8 100644 --- a/components/hal/esp32p4/include/hal/huk_ll.h +++ b/components/hal/esp32p4/include/hal/huk_ll.h @@ -58,30 +58,36 @@ static inline void huk_ll_continue(void) /* @bried Enable or Disable the HUK interrupts */ static inline void huk_ll_configure_interrupt(const esp_huk_interrupt_type_t intr, const bool en) { - switch(intr) { - case ESP_HUK_INT_PREP_DONE: - REG_SET_FIELD(HUK_INT_ENA_REG, HUK_PREP_DONE_INT_ENA, en); - case ESP_HUK_INT_PROC_DONE: - REG_SET_FIELD(HUK_INT_ENA_REG, HUK_PROC_DONE_INT_ENA, en); - case ESP_HUK_INT_POST_DONE: - REG_SET_FIELD(HUK_INT_ENA_REG, HUK_POST_DONE_INT_ENA, en); - default: - return; + switch (intr) { + case ESP_HUK_INT_PREP_DONE: + REG_SET_FIELD(HUK_INT_ENA_REG, HUK_PREP_DONE_INT_ENA, en); + break; + case ESP_HUK_INT_PROC_DONE: + REG_SET_FIELD(HUK_INT_ENA_REG, HUK_PROC_DONE_INT_ENA, en); + break; + case ESP_HUK_INT_POST_DONE: + REG_SET_FIELD(HUK_INT_ENA_REG, HUK_POST_DONE_INT_ENA, en); + break; + default: + return; } } /* @bried Clear the HUK interrupts */ static inline void huk_ll_clear_int(const esp_huk_interrupt_type_t intr) { - switch(intr) { - case ESP_HUK_INT_PREP_DONE: - REG_SET_FIELD(HUK_INT_CLR_REG, HUK_PREP_DONE_INT_CLR, 1); - case ESP_HUK_INT_PROC_DONE: - REG_SET_FIELD(HUK_INT_CLR_REG, HUK_PROC_DONE_INT_CLR, 1); - case ESP_HUK_INT_POST_DONE: - REG_SET_FIELD(HUK_INT_CLR_REG, HUK_POST_DONE_INT_CLR, 1); - default: - return; + switch (intr) { + case ESP_HUK_INT_PREP_DONE: + REG_SET_FIELD(HUK_INT_CLR_REG, HUK_PREP_DONE_INT_CLR, 1); + break; + case ESP_HUK_INT_PROC_DONE: + REG_SET_FIELD(HUK_INT_CLR_REG, HUK_PROC_DONE_INT_CLR, 1); + break; + case ESP_HUK_INT_POST_DONE: + REG_SET_FIELD(HUK_INT_CLR_REG, HUK_POST_DONE_INT_CLR, 1); + break; + default: + return; } } @@ -108,7 +114,7 @@ static inline esp_huk_gen_status_t huk_ll_get_gen_status(void) */ static inline uint32_t huk_ll_get_date_info(void) { - // Only the least siginificant 28 bits have desired information + // Only the least significant 28 bits have desired information return (uint32_t)(0x0FFFFFFF & REG_READ(HUK_DATE_REG)); } diff --git a/components/hal/esp32p4/include/hal/lp_i2s_ll.h b/components/hal/esp32p4/include/hal/lp_i2s_ll.h index 17f3aba185f5..c25e3c57dfdf 100644 --- a/components/hal/esp32p4/include/hal/lp_i2s_ll.h +++ b/components/hal/esp32p4/include/hal/lp_i2s_ll.h @@ -23,7 +23,7 @@ extern "C" { #endif -#define I2S_LL_GET_HW(num) (((num) == 0)? (&LP_I2S) : NULL) +#define LP_I2S_LL_GET_HW(num) (((num) == 0)? (&LP_I2S) : NULL) #define LP_I2S_LL_EVENT_RX_DONE_INT (1<<0) #define LP_I2S_LL_EVENT_RX_HUNG_INT_INT (1<<1) @@ -146,7 +146,7 @@ static inline void lp_i2s_ll_clk_source_div_num(int id, uint32_t val) * @param a div a * @param b div b */ -static inline void i2s_ll_tx_set_raw_clk_div(int id, uint32_t a, uint32_t b) +static inline void lp_i2s_ll_tx_set_raw_clk_div(int id, uint32_t a, uint32_t b) { if (b <= a / 2) { LPPERI.lp_i2s_rxclk_div_xyz.lp_i2s_rx_clkm_div_yn1 = 0; @@ -297,7 +297,7 @@ static inline void lp_i2s_ll_rx_enable_pdm(lp_i2s_dev_t *hw) /** * @brief Configure LP I2S rx channel bits and bits mode */ -static inline void i2s_ll_rx_set_sample_bit(lp_i2s_dev_t *hw, int chan_bits, int bits_mode) +static inline void lp_i2s_ll_rx_set_sample_bit(lp_i2s_dev_t *hw, int chan_bits, int bits_mode) { hw->rx_conf1.rx_tdm_chan_bits = chan_bits - 1; hw->rx_conf1.rx_bits_mod = bits_mode - 1;