diff --git a/components/driver/rmt.c b/components/driver/rmt.c index 41be13331c3..e63fc2b178b 100644 --- a/components/driver/rmt.c +++ b/components/driver/rmt.c @@ -1025,10 +1025,10 @@ esp_err_t rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, int intr } #if CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH - if (intr_alloc_flags & ESP_INTR_FLAG_IRAM ) { - ESP_LOGE(TAG, "ringbuf ISR functions in flash, but used in IRAM interrupt"); - return ESP_ERR_INVALID_ARG; - } + if (intr_alloc_flags & ESP_INTR_FLAG_IRAM ) { + ESP_LOGE(TAG, "ringbuf ISR functions in flash, but used in IRAM interrupt"); + return ESP_ERR_INVALID_ARG; + } #endif #if !CONFIG_SPIRAM_USE_MALLOC @@ -1217,9 +1217,9 @@ esp_err_t rmt_translator_init(rmt_channel_t channel, sample_to_rmt_t fn) p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)malloc(block_size); #else if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) { - p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)malloc(block_size); - } else { p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)heap_caps_calloc(1, block_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); + } else { + p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)malloc(block_size); } #endif if (p_rmt_obj[channel]->tx_buf == NULL) { diff --git a/components/hal/esp32/include/hal/rmt_ll.h b/components/hal/esp32/include/hal/rmt_ll.h index dfd8199d5ba..32adb02b47a 100644 --- a/components/hal/esp32/include/hal/rmt_ll.h +++ b/components/hal/esp32/include/hal/rmt_ll.h @@ -28,63 +28,75 @@ extern "C" { // Note: TX and RX channel number are all index from zero in the LL driver // i.e. tx_channel belongs to [0,7], and rx_channel belongs to [0,7] +__attribute__((always_inline)) static inline void rmt_ll_enable_drive_clock(rmt_dev_t *dev, bool enable) { dev->conf_ch[0].conf0.clk_en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, bool enable) { dev->conf_ch[0].conf0.mem_pd = enable; // Only conf0 register of channel0 has `mem_pd` } +__attribute__((always_inline)) static inline bool rmt_ll_is_mem_power_down(rmt_dev_t *dev) { return dev->conf_ch[0].conf0.mem_pd; // Only conf0 register of channel0 has `mem_pd` } +__attribute__((always_inline)) static inline void rmt_ll_enable_mem_access(rmt_dev_t *dev, bool enable) { dev->apb_conf.fifo_mask = enable; } +__attribute__((always_inline)) static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src, uint8_t div_num, uint8_t div_a, uint8_t div_b) { dev->conf_ch[channel].conf1.ref_always_on = src; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf1.ref_always_on; } +__attribute__((always_inline)) static inline void rmt_ll_tx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { dev->conf_ch[channel].conf1.ref_cnt_rst = 1; } +__attribute__((always_inline)) static inline void rmt_ll_rx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { dev->conf_ch[channel].conf1.ref_cnt_rst = 1; } +__attribute__((always_inline)) static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel) { dev->conf_ch[channel].conf1.mem_rd_rst = 1; dev->conf_ch[channel].conf1.mem_rd_rst = 0; } +__attribute__((always_inline)) static inline void rmt_ll_rx_reset_pointer(rmt_dev_t *dev, uint32_t channel) { dev->conf_ch[channel].conf1.mem_wr_rst = 1; dev->conf_ch[channel].conf1.mem_wr_rst = 0; } +__attribute__((always_inline)) static inline void rmt_ll_tx_start(rmt_dev_t *dev, uint32_t channel) { dev->conf_ch[channel].conf1.tx_start = 1; } +__attribute__((always_inline)) static inline void rmt_ll_tx_stop(rmt_dev_t *dev, uint32_t channel) { RMTMEM.chan[channel].data32[0].val = 0; @@ -93,138 +105,165 @@ static inline void rmt_ll_tx_stop(rmt_dev_t *dev, uint32_t channel) dev->conf_ch[channel].conf1.mem_rd_rst = 0; } +__attribute__((always_inline)) static inline void rmt_ll_rx_enable(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->conf_ch[channel].conf1.rx_en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num) { dev->conf_ch[channel].conf0.mem_size = block_num; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num) { dev->conf_ch[channel].conf0.mem_size = block_num; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf0.mem_size; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf0.mem_size; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) { HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div); } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) { HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt); return div == 0 ? 256 : div; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt); return div == 0 ? 256 : div; } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->apb_conf.mem_tx_wrap_en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres) { HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres, thres); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel) { return HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres); } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_mem_owner(rmt_dev_t *dev, uint32_t channel, uint8_t owner) { dev->conf_ch[channel].conf1.mem_owner = owner; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_mem_owner(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf1.mem_owner; } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_loop(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->conf_ch[channel].conf1.tx_conti_mode = enable; } +__attribute__((always_inline)) static inline bool rmt_ll_is_tx_loop_enabled(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf1.tx_conti_mode; } +__attribute__((always_inline)) static inline void rmt_ll_tx_reset_loop(rmt_dev_t *dev, uint32_t channel) { // RMT on esp32 doesn't support loop count, adding this only for HAL API consistency } +__attribute__((always_inline)) static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->conf_ch[channel].conf1.rx_filter_en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres) { HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf1, rx_filter_thres, thres); } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_idle(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->conf_ch[channel].conf1.idle_out_en = enable; } +__attribute__((always_inline)) static inline bool rmt_ll_is_tx_idle_enabled(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf1.idle_out_en; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) { dev->conf_ch[channel].conf1.idle_out_lv = level; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf1.idle_out_lv; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_channel_status(rmt_dev_t *dev, uint32_t channel) { return dev->status_ch[channel]; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_channel_status(rmt_dev_t *dev, uint32_t channel) { return dev->status_ch[channel]; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit) { dev->tx_lim_ch[channel].limit = limit; } +__attribute__((always_inline)) static inline void rmt_ll_enable_interrupt(rmt_dev_t *dev, uint32_t mask, bool enable) { if (enable) { @@ -234,61 +273,72 @@ static inline void rmt_ll_enable_interrupt(rmt_dev_t *dev, uint32_t mask, bool e } } +__attribute__((always_inline)) static inline void rmt_ll_enable_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->int_ena.val &= ~(1 << (channel * 3)); dev->int_ena.val |= (enable << (channel * 3)); } +__attribute__((always_inline)) static inline void rmt_ll_enable_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->int_ena.val &= ~(1 << (channel * 3 + 1)); dev->int_ena.val |= (enable << (channel * 3 + 1)); } +__attribute__((always_inline)) static inline void rmt_ll_enable_tx_err_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->int_ena.val &= ~(1 << (channel * 3 + 2)); dev->int_ena.val |= (enable << (channel * 3 + 2)); } +__attribute__((always_inline)) static inline void rmt_ll_enable_rx_err_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->int_ena.val &= ~(1 << (channel * 3 + 2)); dev->int_ena.val |= (enable << (channel * 3 + 2)); } +__attribute__((always_inline)) static inline void rmt_ll_enable_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->int_ena.val &= ~(1 << (channel + 24)); dev->int_ena.val |= (enable << (channel + 24)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel * 3)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel * 3 + 1)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_tx_err_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel * 3 + 2)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_rx_err_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel * 3 + 2)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel + 24)); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev) { uint32_t status = dev->int_st.val; @@ -296,6 +346,7 @@ static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev) ((status & 0x1000) >> 8) | ((status & 0x8000) >> 10) | ((status & 0x40000) >> 12) | ((status & 0x200000) >> 14); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev) { uint32_t status = dev->int_st.val; @@ -303,6 +354,7 @@ static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev) ((status & 0x2000) >> 9) | ((status & 0x10000) >> 11) | ((status & 0x80000) >> 13) | ((status & 0x400000) >> 15); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_err_interrupt_status(rmt_dev_t *dev) { uint32_t status = dev->int_st.val; @@ -310,6 +362,7 @@ static inline uint32_t rmt_ll_get_tx_err_interrupt_status(rmt_dev_t *dev) ((status & 0x4000) >> 10) | ((status & 0x20000) >> 12) | ((status & 0x100000) >> 14) | ((status & 0x800000) >> 16); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_err_interrupt_status(rmt_dev_t *dev) { uint32_t status = dev->int_st.val; @@ -317,29 +370,34 @@ static inline uint32_t rmt_ll_get_rx_err_interrupt_status(rmt_dev_t *dev) ((status & 0x4000) >> 10) | ((status & 0x20000) >> 12) | ((status & 0x100000) >> 14) | ((status & 0x800000) >> 16); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev) { uint32_t status = dev->int_st.val; return (status & 0xFF000000) >> 24; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks) { HAL_FORCE_MODIFY_U32_REG_FIELD(dev->carrier_duty_ch[channel], high, high_ticks); HAL_FORCE_MODIFY_U32_REG_FIELD(dev->carrier_duty_ch[channel], low, low_ticks); } +__attribute__((always_inline)) static inline void rmt_ll_tx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks) { *high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->carrier_duty_ch[channel], high); *low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->carrier_duty_ch[channel], low); } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->conf_ch[channel].conf0.carrier_en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) { dev->conf_ch[channel].conf0.carrier_out_lv = level; @@ -347,6 +405,7 @@ static inline void rmt_ll_tx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, //Writes items to the specified TX channel memory with the given offset and length. //the caller should ensure that (length + off) <= (memory block * SOC_RMT_MEM_WORDS_PER_CHANNEL) +__attribute__((always_inline)) static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const void *data, size_t length_in_words, size_t off) { volatile uint32_t *to = (volatile uint32_t *)&mem->chan[channel].data32[off]; diff --git a/components/hal/esp32c3/include/hal/rmt_ll.h b/components/hal/esp32c3/include/hal/rmt_ll.h index 662e63f784e..4201a142291 100644 --- a/components/hal/esp32c3/include/hal/rmt_ll.h +++ b/components/hal/esp32c3/include/hal/rmt_ll.h @@ -25,18 +25,21 @@ extern "C" { // Note: TX and RX channel number are all index from zero in the LL driver // i.e. tx_channel belongs to [0,2], and rx_channel belongs to [0,2] +__attribute__((always_inline)) static inline void rmt_ll_enable_drive_clock(rmt_dev_t *dev, bool enable) { dev->sys_conf.clk_en = enable; // register clock gating dev->sys_conf.mem_clk_force_on = enable; // memory clock gating } +__attribute__((always_inline)) static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, bool enable) { dev->sys_conf.mem_force_pu = !enable; dev->sys_conf.mem_force_pd = enable; } +__attribute__((always_inline)) static inline bool rmt_ll_is_mem_power_down(rmt_dev_t *dev) { // the RTC domain can also power down RMT memory @@ -45,11 +48,13 @@ static inline bool rmt_ll_is_mem_power_down(rmt_dev_t *dev) return (dev->sys_conf.mem_force_pd) || !(dev->sys_conf.mem_force_pu); } +__attribute__((always_inline)) static inline void rmt_ll_enable_mem_access(rmt_dev_t *dev, bool enable) { dev->sys_conf.fifo_mask = enable; } +__attribute__((always_inline)) static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src, uint8_t div_num, uint8_t div_a, uint8_t div_b) { // Formula: rmt_sclk = module_clock_src / (1 + div_num + div_a / div_b) @@ -61,26 +66,31 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, dev->sys_conf.sclk_active = 1; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel) { return dev->sys_conf.sclk_sel; } +__attribute__((always_inline)) static inline void rmt_ll_tx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { dev->ref_cnt_rst.val |= (1 << channel); } +__attribute__((always_inline)) static inline void rmt_ll_tx_reset_channels_clock_div(rmt_dev_t *dev, uint32_t channel_mask) { dev->ref_cnt_rst.val |= channel_mask; } +__attribute__((always_inline)) static inline void rmt_ll_rx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { dev->ref_cnt_rst.val |= (1 << (channel + 2)); } +__attribute__((always_inline)) static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel) { dev->tx_conf[channel].mem_rd_rst = 1; @@ -89,6 +99,7 @@ static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel) dev->tx_conf[channel].mem_rst = 0; } +__attribute__((always_inline)) static inline void rmt_ll_rx_reset_pointer(rmt_dev_t *dev, uint32_t channel) { dev->rx_conf[channel].conf1.mem_wr_rst = 1; @@ -97,185 +108,221 @@ static inline void rmt_ll_rx_reset_pointer(rmt_dev_t *dev, uint32_t channel) dev->rx_conf[channel].conf1.mem_rst = 0; } +__attribute__((always_inline)) static inline void rmt_ll_tx_start(rmt_dev_t *dev, uint32_t channel) { dev->tx_conf[channel].conf_update = 1; dev->tx_conf[channel].tx_start = 1; } +__attribute__((always_inline)) static inline void rmt_ll_tx_stop(rmt_dev_t *dev, uint32_t channel) { dev->tx_conf[channel].tx_stop = 1; dev->tx_conf[channel].conf_update = 1; } +__attribute__((always_inline)) static inline void rmt_ll_rx_enable(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->rx_conf[channel].conf1.rx_en = enable; dev->rx_conf[channel].conf1.conf_update = 1; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num) { dev->tx_conf[channel].mem_size = block_num; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num) { dev->rx_conf[channel].conf0.mem_size = block_num; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) { return dev->tx_conf[channel].mem_size; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) { return dev->rx_conf[channel].conf0.mem_size; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) { HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_conf[channel], div_cnt, div); } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) { HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_conf[channel].conf0, div_cnt, div); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { return HAL_FORCE_READ_U32_REG_FIELD(dev->tx_conf[channel], div_cnt); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { return HAL_FORCE_READ_U32_REG_FIELD(dev->rx_conf[channel].conf0, div_cnt); } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->tx_conf[channel].mem_tx_wrap_en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres) { dev->rx_conf[channel].conf0.idle_thres = thres; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel) { return dev->rx_conf[channel].conf0.idle_thres; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_mem_owner(rmt_dev_t *dev, uint32_t channel, uint8_t owner) { dev->rx_conf[channel].conf1.mem_owner = owner; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_mem_owner(rmt_dev_t *dev, uint32_t channel) { return dev->rx_conf[channel].conf1.mem_owner; } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_loop(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->tx_conf[channel].tx_conti_mode = enable; } +__attribute__((always_inline)) static inline bool rmt_ll_is_tx_loop_enabled(rmt_dev_t *dev, uint32_t channel) { return dev->tx_conf[channel].tx_conti_mode; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_loop_count(rmt_dev_t *dev, uint32_t channel, uint32_t count) { dev->tx_lim[channel].tx_loop_num = count; } +__attribute__((always_inline)) static inline void rmt_ll_tx_reset_loop(rmt_dev_t *dev, uint32_t channel) { dev->tx_lim[channel].loop_count_reset = 1; dev->tx_lim[channel].loop_count_reset = 0; } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_loop_count(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->tx_lim[channel].tx_loop_cnt_en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_sync(rmt_dev_t *dev, bool enable) { dev->tx_sim.en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_tx_add_to_sync_group(rmt_dev_t *dev, uint32_t channel) { dev->tx_sim.val |= 1 << channel; } +__attribute__((always_inline)) static inline void rmt_ll_tx_remove_from_sync_group(rmt_dev_t *dev, uint32_t channel) { dev->tx_sim.val &= ~(1 << channel); } +__attribute__((always_inline)) static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->rx_conf[channel].conf1.rx_filter_en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres) { HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_conf[channel].conf1, rx_filter_thres, thres); } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_idle(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->tx_conf[channel].idle_out_en = enable; } +__attribute__((always_inline)) static inline bool rmt_ll_is_tx_idle_enabled(rmt_dev_t *dev, uint32_t channel) { return dev->tx_conf[channel].idle_out_en; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) { dev->tx_conf[channel].idle_out_lv = level; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel) { return dev->tx_conf[channel].idle_out_lv; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_channel_status(rmt_dev_t *dev, uint32_t channel) { return dev->rx_status[channel].val; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_channel_status(rmt_dev_t *dev, uint32_t channel) { return dev->tx_status[channel].val; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit) { dev->tx_lim[channel].limit = limit; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit) { dev->rx_lim[channel].rx_lim = limit; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_limit(rmt_dev_t *dev, uint32_t channel) { return dev->rx_lim[channel].rx_lim; } +__attribute__((always_inline)) static inline void rmt_ll_enable_interrupt(rmt_dev_t *dev, uint32_t mask, bool enable) { if (enable) { @@ -285,6 +332,7 @@ static inline void rmt_ll_enable_interrupt(rmt_dev_t *dev, uint32_t mask, bool e } } +__attribute__((always_inline)) static inline void rmt_ll_enable_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { if (enable) { @@ -294,6 +342,7 @@ static inline void rmt_ll_enable_tx_end_interrupt(rmt_dev_t *dev, uint32_t chann } } +__attribute__((always_inline)) static inline void rmt_ll_enable_tx_err_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { if (enable) { @@ -303,6 +352,7 @@ static inline void rmt_ll_enable_tx_err_interrupt(rmt_dev_t *dev, uint32_t chann } } +__attribute__((always_inline)) static inline void rmt_ll_enable_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { if (enable) { @@ -312,6 +362,7 @@ static inline void rmt_ll_enable_rx_end_interrupt(rmt_dev_t *dev, uint32_t chann } } +__attribute__((always_inline)) static inline void rmt_ll_enable_rx_err_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { if (enable) { @@ -321,6 +372,7 @@ static inline void rmt_ll_enable_rx_err_interrupt(rmt_dev_t *dev, uint32_t chann } } +__attribute__((always_inline)) static inline void rmt_ll_enable_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { if (enable) { @@ -330,6 +382,7 @@ static inline void rmt_ll_enable_tx_thres_interrupt(rmt_dev_t *dev, uint32_t cha } } +__attribute__((always_inline)) static inline void rmt_ll_enable_tx_loop_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { if (enable) { @@ -339,6 +392,7 @@ static inline void rmt_ll_enable_tx_loop_interrupt(rmt_dev_t *dev, uint32_t chan } } +__attribute__((always_inline)) static inline void rmt_ll_enable_rx_thres_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { if (enable) { @@ -348,76 +402,91 @@ static inline void rmt_ll_enable_rx_thres_interrupt(rmt_dev_t *dev, uint32_t cha } } +__attribute__((always_inline)) static inline void rmt_ll_clear_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel + 2)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_tx_err_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel + 4)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_rx_err_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel + 6)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel + 8)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_tx_loop_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel + 12)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_rx_thres_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel + 10)); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev) { return dev->int_st.val & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 2) & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_err_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 4) & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_err_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 6) & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 8) & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_thres_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 10) & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_loop_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 12) & 0x03; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks) { // In case the compiler optimise a 32bit instruction (e.g. s32i) into two 16bit instruction (e.g. s16i, which is not allowed to access a register) @@ -428,6 +497,7 @@ static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t dev->tx_carrier[channel].val = reg.val; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks) { typeof(dev->rx_carrier[0]) reg; @@ -436,33 +506,39 @@ static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t dev->rx_carrier[channel].val = reg.val; } +__attribute__((always_inline)) static inline void rmt_ll_tx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks) { *high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->tx_carrier[channel], high); *low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->tx_carrier[channel], low); } +__attribute__((always_inline)) static inline void rmt_ll_rx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks) { *high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->rx_carrier[channel], high_thres); *low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->rx_carrier[channel], low_thres); } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->tx_conf[channel].carrier_en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_rx_enable_carrier_demodulation(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->rx_conf[channel].conf0.carrier_en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) { dev->tx_conf[channel].carrier_out_lv = level; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) { dev->rx_conf[channel].conf0.carrier_out_lv = level; @@ -470,6 +546,7 @@ static inline void rmt_ll_rx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, // set true, enable carrier in all RMT state (idle, reading, sending) // set false, enable carrier only in sending state (i.e. there're effective data in RAM to be sent) +__attribute__((always_inline)) static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->tx_conf[channel].carrier_eff_en = !enable; @@ -477,6 +554,7 @@ static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t chan //Writes items to the specified TX channel memory with the given offset and length. //the caller should ensure that (length + off) <= (memory block * SOC_RMT_MEM_WORDS_PER_CHANNEL) +__attribute__((always_inline)) static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const void *data, size_t length_in_words, size_t off) { volatile uint32_t *to = (volatile uint32_t *)&mem->chan[channel].data32[off]; @@ -486,6 +564,7 @@ static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const v } } +__attribute__((always_inline)) static inline void rmt_ll_rx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->rx_conf[channel].conf1.mem_rx_wrap_en = enable; diff --git a/components/hal/esp32h2/include/hal/rmt_ll.h b/components/hal/esp32h2/include/hal/rmt_ll.h index 0403741429f..e6d4f139480 100644 --- a/components/hal/esp32h2/include/hal/rmt_ll.h +++ b/components/hal/esp32h2/include/hal/rmt_ll.h @@ -24,18 +24,21 @@ extern "C" { // Note: TX and RX channel number are all index from zero in the LL driver // i.e. tx_channel belongs to [0,2], and rx_channel belongs to [0,2] +__attribute__((always_inline)) static inline void rmt_ll_enable_drive_clock(rmt_dev_t *dev, bool enable) { dev->sys_conf.clk_en = enable; // register clock gating dev->sys_conf.mem_clk_force_on = enable; // memory clock gating } +__attribute__((always_inline)) static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, bool enable) { dev->sys_conf.mem_force_pu = !enable; dev->sys_conf.mem_force_pd = enable; } +__attribute__((always_inline)) static inline bool rmt_ll_is_mem_power_down(rmt_dev_t *dev) { // the RTC domain can also power down RMT memory @@ -44,11 +47,13 @@ static inline bool rmt_ll_is_mem_power_down(rmt_dev_t *dev) return (dev->sys_conf.mem_force_pd) || !(dev->sys_conf.mem_force_pu); } +__attribute__((always_inline)) static inline void rmt_ll_enable_mem_access(rmt_dev_t *dev, bool enable) { dev->sys_conf.fifo_mask = enable; } +__attribute__((always_inline)) static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src, uint8_t div_num, uint8_t div_a, uint8_t div_b) { // Formula: rmt_sclk = module_clock_src / (1 + div_num + div_a / div_b) @@ -60,26 +65,31 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, dev->sys_conf.sclk_active = 1; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel) { return dev->sys_conf.sclk_sel; } +__attribute__((always_inline)) static inline void rmt_ll_tx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { dev->ref_cnt_rst.val |= (1 << channel); } +__attribute__((always_inline)) static inline void rmt_ll_tx_reset_channels_clock_div(rmt_dev_t *dev, uint32_t channel_mask) { dev->ref_cnt_rst.val |= channel_mask; } +__attribute__((always_inline)) static inline void rmt_ll_rx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { dev->ref_cnt_rst.val |= (1 << (channel + 2)); } +__attribute__((always_inline)) static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel) { dev->tx_conf[channel].mem_rd_rst = 1; @@ -88,6 +98,7 @@ static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel) dev->tx_conf[channel].mem_rst = 0; } +__attribute__((always_inline)) static inline void rmt_ll_rx_reset_pointer(rmt_dev_t *dev, uint32_t channel) { dev->rx_conf[channel].conf1.mem_wr_rst = 1; @@ -96,185 +107,221 @@ static inline void rmt_ll_rx_reset_pointer(rmt_dev_t *dev, uint32_t channel) dev->rx_conf[channel].conf1.mem_rst = 0; } +__attribute__((always_inline)) static inline void rmt_ll_tx_start(rmt_dev_t *dev, uint32_t channel) { dev->tx_conf[channel].conf_update = 1; dev->tx_conf[channel].tx_start = 1; } +__attribute__((always_inline)) static inline void rmt_ll_tx_stop(rmt_dev_t *dev, uint32_t channel) { dev->tx_conf[channel].tx_stop = 1; dev->tx_conf[channel].conf_update = 1; } +__attribute__((always_inline)) static inline void rmt_ll_rx_enable(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->rx_conf[channel].conf1.rx_en = enable; dev->rx_conf[channel].conf1.conf_update = 1; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num) { dev->tx_conf[channel].mem_size = block_num; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num) { dev->rx_conf[channel].conf0.mem_size = block_num; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) { return dev->tx_conf[channel].mem_size; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) { return dev->rx_conf[channel].conf0.mem_size; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) { HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_conf[channel], div_cnt, div); } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) { HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_conf[channel].conf0, div_cnt, div); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { return HAL_FORCE_READ_U32_REG_FIELD(dev->tx_conf[channel], div_cnt); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { return HAL_FORCE_READ_U32_REG_FIELD(dev->rx_conf[channel].conf0, div_cnt); } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->tx_conf[channel].mem_tx_wrap_en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres) { dev->rx_conf[channel].conf0.idle_thres = thres; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel) { return dev->rx_conf[channel].conf0.idle_thres; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_mem_owner(rmt_dev_t *dev, uint32_t channel, uint8_t owner) { dev->rx_conf[channel].conf1.mem_owner = owner; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_mem_owner(rmt_dev_t *dev, uint32_t channel) { return dev->rx_conf[channel].conf1.mem_owner; } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_loop(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->tx_conf[channel].tx_conti_mode = enable; } +__attribute__((always_inline)) static inline bool rmt_ll_is_tx_loop_enabled(rmt_dev_t *dev, uint32_t channel) { return dev->tx_conf[channel].tx_conti_mode; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_loop_count(rmt_dev_t *dev, uint32_t channel, uint32_t count) { dev->tx_lim[channel].tx_loop_num = count; } +__attribute__((always_inline)) static inline void rmt_ll_tx_reset_loop(rmt_dev_t *dev, uint32_t channel) { dev->tx_lim[channel].loop_count_reset = 1; dev->tx_lim[channel].loop_count_reset = 0; } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_loop_count(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->tx_lim[channel].tx_loop_cnt_en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_sync(rmt_dev_t *dev, bool enable) { dev->tx_sim.en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_tx_add_to_sync_group(rmt_dev_t *dev, uint32_t channel) { dev->tx_sim.val |= 1 << channel; } +__attribute__((always_inline)) static inline void rmt_ll_tx_remove_from_sync_group(rmt_dev_t *dev, uint32_t channel) { dev->tx_sim.val &= ~(1 << channel); } +__attribute__((always_inline)) static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->rx_conf[channel].conf1.rx_filter_en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres) { HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_conf[channel].conf1, rx_filter_thres, thres); } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_idle(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->tx_conf[channel].idle_out_en = enable; } +__attribute__((always_inline)) static inline bool rmt_ll_is_tx_idle_enabled(rmt_dev_t *dev, uint32_t channel) { return dev->tx_conf[channel].idle_out_en; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) { dev->tx_conf[channel].idle_out_lv = level; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel) { return dev->tx_conf[channel].idle_out_lv; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_channel_status(rmt_dev_t *dev, uint32_t channel) { return dev->rx_status[channel].val; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_channel_status(rmt_dev_t *dev, uint32_t channel) { return dev->tx_status[channel].val; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit) { dev->tx_lim[channel].limit = limit; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit) { dev->rx_lim[channel].rx_lim = limit; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_limit(rmt_dev_t *dev, uint32_t channel) { return dev->rx_lim[channel].rx_lim; } +__attribute__((always_inline)) static inline void rmt_ll_enable_interrupt(rmt_dev_t *dev, uint32_t mask, bool enable) { if (enable) { @@ -284,6 +331,7 @@ static inline void rmt_ll_enable_interrupt(rmt_dev_t *dev, uint32_t mask, bool e } } +__attribute__((always_inline)) static inline void rmt_ll_enable_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { if (enable) { @@ -293,6 +341,7 @@ static inline void rmt_ll_enable_tx_end_interrupt(rmt_dev_t *dev, uint32_t chann } } +__attribute__((always_inline)) static inline void rmt_ll_enable_tx_err_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { if (enable) { @@ -302,6 +351,7 @@ static inline void rmt_ll_enable_tx_err_interrupt(rmt_dev_t *dev, uint32_t chann } } +__attribute__((always_inline)) static inline void rmt_ll_enable_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { if (enable) { @@ -311,6 +361,7 @@ static inline void rmt_ll_enable_rx_end_interrupt(rmt_dev_t *dev, uint32_t chann } } +__attribute__((always_inline)) static inline void rmt_ll_enable_rx_err_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { if (enable) { @@ -320,6 +371,7 @@ static inline void rmt_ll_enable_rx_err_interrupt(rmt_dev_t *dev, uint32_t chann } } +__attribute__((always_inline)) static inline void rmt_ll_enable_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { if (enable) { @@ -329,6 +381,7 @@ static inline void rmt_ll_enable_tx_thres_interrupt(rmt_dev_t *dev, uint32_t cha } } +__attribute__((always_inline)) static inline void rmt_ll_enable_tx_loop_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { if (enable) { @@ -338,6 +391,7 @@ static inline void rmt_ll_enable_tx_loop_interrupt(rmt_dev_t *dev, uint32_t chan } } +__attribute__((always_inline)) static inline void rmt_ll_enable_rx_thres_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { if (enable) { @@ -347,76 +401,91 @@ static inline void rmt_ll_enable_rx_thres_interrupt(rmt_dev_t *dev, uint32_t cha } } +__attribute__((always_inline)) static inline void rmt_ll_clear_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel + 2)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_tx_err_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel + 4)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_rx_err_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel + 6)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel + 8)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_tx_loop_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel + 12)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_rx_thres_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel + 10)); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev) { return dev->int_st.val & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 2) & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_err_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 4) & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_err_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 6) & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 8) & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_thres_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 10) & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_loop_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 12) & 0x03; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks) { // In case the compiler optimise a 32bit instruction (e.g. s32i) into two 16bit instruction (e.g. s16i, which is not allowed to access a register) @@ -427,6 +496,7 @@ static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t dev->tx_carrier[channel].val = reg.val; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks) { typeof(dev->rx_carrier[0]) reg; @@ -435,33 +505,39 @@ static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t dev->rx_carrier[channel].val = reg.val; } +__attribute__((always_inline)) static inline void rmt_ll_tx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks) { *high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->tx_carrier[channel], high); *low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->tx_carrier[channel], low); } +__attribute__((always_inline)) static inline void rmt_ll_rx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks) { *high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->rx_carrier[channel], high_thres); *low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->rx_carrier[channel], low_thres); } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->tx_conf[channel].carrier_en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_rx_enable_carrier_demodulation(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->rx_conf[channel].conf0.carrier_en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) { dev->tx_conf[channel].carrier_out_lv = level; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) { dev->rx_conf[channel].conf0.carrier_out_lv = level; @@ -469,6 +545,7 @@ static inline void rmt_ll_rx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, // set true, enable carrier in all RMT state (idle, reading, sending) // set false, enable carrier only in sending state (i.e. there're effective data in RAM to be sent) +__attribute__((always_inline)) static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->tx_conf[channel].carrier_eff_en = !enable; @@ -476,6 +553,7 @@ static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t chan //Writes items to the specified TX channel memory with the given offset and length. //the caller should ensure that (length + off) <= (memory block * SOC_RMT_MEM_WORDS_PER_CHANNEL) +__attribute__((always_inline)) static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const void *data, size_t length_in_words, size_t off) { volatile uint32_t *to = (volatile uint32_t *)&mem->chan[channel].data32[off]; @@ -485,6 +563,7 @@ static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const v } } +__attribute__((always_inline)) static inline void rmt_ll_rx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->rx_conf[channel].conf1.mem_rx_wrap_en = enable; diff --git a/components/hal/esp32s2/include/hal/rmt_ll.h b/components/hal/esp32s2/include/hal/rmt_ll.h index f7452a364e3..60e09ce0ecd 100644 --- a/components/hal/esp32s2/include/hal/rmt_ll.h +++ b/components/hal/esp32s2/include/hal/rmt_ll.h @@ -23,18 +23,21 @@ extern "C" { // Note: TX and RX channel number are all index from zero in the LL driver // i.e. tx_channel belongs to [0,3], and rx_channel belongs to [0,3] +__attribute__((always_inline)) static inline void rmt_ll_enable_drive_clock(rmt_dev_t *dev, bool enable) { dev->apb_conf.clk_en = enable; // register clock gating dev->apb_conf.mem_clk_force_on = enable; // memory clock gating } +__attribute__((always_inline)) static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, bool enable) { dev->apb_conf.mem_force_pu = !enable; dev->apb_conf.mem_force_pd = enable; } +__attribute__((always_inline)) static inline bool rmt_ll_is_mem_power_down(rmt_dev_t *dev) { // the RTC domain can also power down RMT memory @@ -43,216 +46,258 @@ static inline bool rmt_ll_is_mem_power_down(rmt_dev_t *dev) return (dev->apb_conf.mem_force_pd) || !(dev->apb_conf.mem_force_pu); } +__attribute__((always_inline)) static inline void rmt_ll_enable_mem_access(rmt_dev_t *dev, bool enable) { dev->apb_conf.apb_fifo_mask = enable; } +__attribute__((always_inline)) static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src, uint8_t div_num, uint8_t div_a, uint8_t div_b) { dev->conf_ch[channel].conf1.ref_always_on = src; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf1.ref_always_on; } +__attribute__((always_inline)) static inline void rmt_ll_tx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { dev->ref_cnt_rst.val |= (1 << channel); } +__attribute__((always_inline)) static inline void rmt_ll_tx_reset_channels_clock_div(rmt_dev_t *dev, uint32_t channel_mask) { dev->ref_cnt_rst.val |= channel_mask; } +__attribute__((always_inline)) static inline void rmt_ll_rx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { dev->ref_cnt_rst.val |= (1 << channel); } +__attribute__((always_inline)) static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel) { dev->conf_ch[channel].conf1.mem_rd_rst = 1; dev->conf_ch[channel].conf1.mem_rd_rst = 0; } +__attribute__((always_inline)) static inline void rmt_ll_rx_reset_pointer(rmt_dev_t *dev, uint32_t channel) { dev->conf_ch[channel].conf1.mem_wr_rst = 1; dev->conf_ch[channel].conf1.mem_wr_rst = 0; } +__attribute__((always_inline)) static inline void rmt_ll_tx_start(rmt_dev_t *dev, uint32_t channel) { dev->conf_ch[channel].conf1.tx_start = 1; } +__attribute__((always_inline)) static inline void rmt_ll_tx_stop(rmt_dev_t *dev, uint32_t channel) { dev->conf_ch[channel].conf1.tx_stop = 1; } +__attribute__((always_inline)) static inline void rmt_ll_rx_enable(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->conf_ch[channel].conf1.rx_en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num) { dev->conf_ch[channel].conf0.mem_size = block_num; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num) { dev->conf_ch[channel].conf0.mem_size = block_num; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf0.mem_size; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf0.mem_size; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) { HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div); } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) { HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt); return div == 0 ? 256 : div; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt); return div == 0 ? 256 : div; } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->apb_conf.mem_tx_wrap_en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres) { HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres, thres); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel) { return HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres); } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_mem_owner(rmt_dev_t *dev, uint32_t channel, uint8_t owner) { dev->conf_ch[channel].conf1.mem_owner = owner; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_mem_owner(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf1.mem_owner; } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_loop(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->conf_ch[channel].conf1.tx_conti_mode = enable; } +__attribute__((always_inline)) static inline bool rmt_ll_is_tx_loop_enabled(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf1.tx_conti_mode; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_loop_count(rmt_dev_t *dev, uint32_t channel, uint32_t count) { dev->tx_lim_ch[channel].tx_loop_num = count; } +__attribute__((always_inline)) static inline void rmt_ll_tx_reset_loop(rmt_dev_t *dev, uint32_t channel) { dev->tx_lim_ch[channel].loop_count_reset = 1; dev->tx_lim_ch[channel].loop_count_reset = 0; } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_loop_count(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->tx_lim_ch[channel].tx_loop_cnt_en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_sync(rmt_dev_t *dev, bool enable) { dev->tx_sim.en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_tx_add_to_sync_group(rmt_dev_t *dev, uint32_t channel) { dev->tx_sim.val |= 1 << channel; } +__attribute__((always_inline)) static inline void rmt_ll_tx_remove_from_sync_group(rmt_dev_t *dev, uint32_t channel) { dev->tx_sim.val &= ~(1 << channel); } +__attribute__((always_inline)) static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->conf_ch[channel].conf1.rx_filter_en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres) { HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf1, rx_filter_thres, thres); } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_idle(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->conf_ch[channel].conf1.idle_out_en = enable; } +__attribute__((always_inline)) static inline bool rmt_ll_is_tx_idle_enabled(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf1.idle_out_en; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) { dev->conf_ch[channel].conf1.idle_out_lv = level; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf1.idle_out_lv; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_channel_status(rmt_dev_t *dev, uint32_t channel) { return dev->status_ch[channel].val; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_channel_status(rmt_dev_t *dev, uint32_t channel) { return dev->status_ch[channel].val; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit) { dev->tx_lim_ch[channel].tx_lim = limit; } +__attribute__((always_inline)) static inline void rmt_ll_enable_interrupt(rmt_dev_t *dev, uint32_t mask, bool enable) { if (enable) { @@ -262,108 +307,127 @@ static inline void rmt_ll_enable_interrupt(rmt_dev_t *dev, uint32_t mask, bool e } } +__attribute__((always_inline)) static inline void rmt_ll_enable_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->int_ena.val &= ~(1 << (channel * 3)); dev->int_ena.val |= (enable << (channel * 3)); } +__attribute__((always_inline)) static inline void rmt_ll_enable_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->int_ena.val &= ~(1 << (channel * 3 + 1)); dev->int_ena.val |= (enable << (channel * 3 + 1)); } +__attribute__((always_inline)) static inline void rmt_ll_enable_tx_err_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->int_ena.val &= ~(1 << (channel * 3 + 2)); dev->int_ena.val |= (enable << (channel * 3 + 2)); } +__attribute__((always_inline)) static inline void rmt_ll_enable_rx_err_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->int_ena.val &= ~(1 << (channel * 3 + 2)); dev->int_ena.val |= (enable << (channel * 3 + 2)); } +__attribute__((always_inline)) static inline void rmt_ll_enable_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->int_ena.val &= ~(1 << (channel + 12)); dev->int_ena.val |= (enable << (channel + 12)); } +__attribute__((always_inline)) static inline void rmt_ll_enable_tx_loop_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->int_ena.val &= ~(1 << (channel + 16)); dev->int_ena.val |= (enable << (channel + 16)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel * 3)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel * 3 + 1)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_tx_err_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel * 3 + 2)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_rx_err_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel * 3 + 2)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel + 12)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_tx_loop_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel + 16)); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev) { uint32_t status = dev->int_st.val; return ((status & 0x01) >> 0) | ((status & 0x08) >> 2) | ((status & 0x40) >> 4) | ((status & 0x200) >> 6); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev) { uint32_t status = dev->int_st.val; return ((status & 0x02) >> 1) | ((status & 0x10) >> 3) | ((status & 0x80) >> 5) | ((status & 0x400) >> 7); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_err_interrupt_status(rmt_dev_t *dev) { uint32_t status = dev->int_st.val; return ((status & 0x04) >> 2) | ((status & 0x20) >> 4) | ((status & 0x100) >> 6) | ((status & 0x800) >> 8); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_err_interrupt_status(rmt_dev_t *dev) { uint32_t status = dev->int_st.val; return ((status & 0x04) >> 2) | ((status & 0x20) >> 4) | ((status & 0x100) >> 6) | ((status & 0x800) >> 8); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev) { uint32_t status = dev->int_st.val; return (status & 0xF000) >> 12; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_loop_interrupt_status(rmt_dev_t *dev) { uint32_t status = dev->int_st.val; return (status & 0xF0000) >> 16; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks) { // In case the compiler optimise a 32bit instruction (e.g. s32i) into two 16bit instruction (e.g. s16i, which is not allowed to access a register) @@ -374,6 +438,7 @@ static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t dev->carrier_duty_ch[channel].val = reg.val; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks) { typeof(dev->ch_rx_carrier_rm[0]) reg; @@ -382,33 +447,39 @@ static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t dev->ch_rx_carrier_rm[channel].val = reg.val; } +__attribute__((always_inline)) static inline void rmt_ll_tx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks) { *high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->carrier_duty_ch[channel], high); *low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->carrier_duty_ch[channel], low); } +__attribute__((always_inline)) static inline void rmt_ll_rx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks) { *high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->ch_rx_carrier_rm[channel], carrier_high_thres_ch); *low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->ch_rx_carrier_rm[channel], carrier_low_thres_ch); } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->conf_ch[channel].conf0.carrier_en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_rx_enable_carrier_demodulation(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->conf_ch[channel].conf0.carrier_en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) { dev->conf_ch[channel].conf0.carrier_out_lv = level; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) { dev->conf_ch[channel].conf0.carrier_out_lv = level; @@ -416,6 +487,7 @@ static inline void rmt_ll_rx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, // set true, enable carrier in all RMT state (idle, reading, sending) // set false, enable carrier only in sending state (i.e. there're effective data in RAM to be sent) +__attribute__((always_inline)) static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->conf_ch[channel].conf0.carrier_eff_en = !enable; @@ -423,6 +495,7 @@ static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t chan //Writes items to the specified TX channel memory with the given offset and length. //the caller should ensure that (length + off) <= (memory block * SOC_RMT_MEM_WORDS_PER_CHANNEL) +__attribute__((always_inline)) static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const void *data, size_t length_in_words, size_t off) { volatile uint32_t *to = (volatile uint32_t *)&mem->chan[channel].data32[off]; diff --git a/components/hal/esp32s3/include/hal/rmt_ll.h b/components/hal/esp32s3/include/hal/rmt_ll.h index 2e6ddd563a1..02cb83bb0ac 100644 --- a/components/hal/esp32s3/include/hal/rmt_ll.h +++ b/components/hal/esp32s3/include/hal/rmt_ll.h @@ -22,18 +22,21 @@ extern "C" { // Note: TX and RX channel number are all index from zero in the LL driver // i.e. tx_channel belongs to [0,3], and rx_channel belongs to [0,3] +__attribute__((always_inline)) static inline void rmt_ll_enable_drive_clock(rmt_dev_t *dev, bool enable) { dev->sys_conf.clk_en = enable; // register clock gating dev->sys_conf.mem_clk_force_on = enable; // memory clock gating } +__attribute__((always_inline)) static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, bool enable) { dev->sys_conf.mem_force_pu = !enable; dev->sys_conf.mem_force_pd = enable; } +__attribute__((always_inline)) static inline bool rmt_ll_is_mem_power_down(rmt_dev_t *dev) { // the RTC domain can also power down RMT memory @@ -42,11 +45,13 @@ static inline bool rmt_ll_is_mem_power_down(rmt_dev_t *dev) return (dev->sys_conf.mem_force_pd) || !(dev->sys_conf.mem_force_pu); } +__attribute__((always_inline)) static inline void rmt_ll_enable_mem_access(rmt_dev_t *dev, bool enable) { dev->sys_conf.apb_fifo_mask = enable; } +__attribute__((always_inline)) static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src, uint8_t div_num, uint8_t div_a, uint8_t div_b) { // Formula: rmt_sclk = module_clock_src / (1 + div_num + div_a / div_b) @@ -58,26 +63,31 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, dev->sys_conf.sclk_active = 1; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel) { return dev->sys_conf.sclk_sel; } +__attribute__((always_inline)) static inline void rmt_ll_tx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { dev->ref_cnt_rst.val |= (1 << channel); } +__attribute__((always_inline)) static inline void rmt_ll_tx_reset_channels_clock_div(rmt_dev_t *dev, uint32_t channel_mask) { dev->ref_cnt_rst.val |= channel_mask; } +__attribute__((always_inline)) static inline void rmt_ll_rx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { dev->ref_cnt_rst.val |= (1 << (channel + 4)); } +__attribute__((always_inline)) static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel) { dev->chnconf0[channel].mem_rd_rst_n = 1; @@ -86,6 +96,7 @@ static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel) dev->chnconf0[channel].apb_mem_rst_n = 0; } +__attribute__((always_inline)) static inline void rmt_ll_rx_reset_pointer(rmt_dev_t *dev, uint32_t channel) { dev->chmconf[channel].conf1.mem_wr_rst_m = 1; @@ -94,190 +105,227 @@ static inline void rmt_ll_rx_reset_pointer(rmt_dev_t *dev, uint32_t channel) dev->chmconf[channel].conf1.apb_mem_rst_m = 0; } +__attribute__((always_inline)) static inline void rmt_ll_tx_start(rmt_dev_t *dev, uint32_t channel) { dev->chnconf0[channel].conf_update_n = 1; dev->chnconf0[channel].tx_start_n = 1; } +__attribute__((always_inline)) static inline void rmt_ll_tx_stop(rmt_dev_t *dev, uint32_t channel) { dev->chnconf0[channel].tx_stop_n = 1; dev->chnconf0[channel].conf_update_n = 1; } +__attribute__((always_inline)) static inline void rmt_ll_rx_enable(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->chmconf[channel].conf1.rx_en_m = enable; dev->chmconf[channel].conf1.conf_update_m = 1; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num) { dev->chnconf0[channel].mem_size_n = block_num; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num) { dev->chmconf[channel].conf0.mem_size_m = block_num; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) { return dev->chnconf0[channel].mem_size_n; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) { return dev->chmconf[channel].conf0.mem_size_m; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) { HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chnconf0[channel], div_cnt_n, div); } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) { HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chmconf[channel].conf0, div_cnt_m, div); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { return HAL_FORCE_READ_U32_REG_FIELD(dev->chnconf0[channel], div_cnt_n); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { return HAL_FORCE_READ_U32_REG_FIELD(dev->chmconf[channel].conf0, div_cnt_m); } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->chnconf0[channel].mem_tx_wrap_en_n = enable; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres) { dev->chmconf[channel].conf0.idle_thres_m = thres; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel) { return dev->chmconf[channel].conf0.idle_thres_m; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_mem_owner(rmt_dev_t *dev, uint32_t channel, uint8_t owner) { dev->chmconf[channel].conf1.mem_owner_m = owner; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_mem_owner(rmt_dev_t *dev, uint32_t channel) { return dev->chmconf[channel].conf1.mem_owner_m; } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_loop(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->chnconf0[channel].tx_conti_mode_n = enable; } +__attribute__((always_inline)) static inline bool rmt_ll_is_tx_loop_enabled(rmt_dev_t *dev, uint32_t channel) { return dev->chnconf0[channel].tx_conti_mode_n; } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_loop_autostop(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->chn_tx_lim[channel].loop_stop_en_chn = enable; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_loop_count(rmt_dev_t *dev, uint32_t channel, uint32_t count) { dev->chn_tx_lim[channel].tx_loop_num_chn = count; } +__attribute__((always_inline)) static inline void rmt_ll_tx_reset_loop(rmt_dev_t *dev, uint32_t channel) { dev->chn_tx_lim[channel].loop_count_reset_chn = 1; dev->chn_tx_lim[channel].loop_count_reset_chn = 0; } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_loop_count(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->chn_tx_lim[channel].tx_loop_cnt_en_chn = enable; } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_sync(rmt_dev_t *dev, bool enable) { dev->tx_sim.tx_sim_en = enable; } +__attribute__((always_inline)) static inline void rmt_ll_tx_add_to_sync_group(rmt_dev_t *dev, uint32_t channel) { dev->tx_sim.val |= 1 << channel; } +__attribute__((always_inline)) static inline void rmt_ll_tx_remove_from_sync_group(rmt_dev_t *dev, uint32_t channel) { dev->tx_sim.val &= ~(1 << channel); } +__attribute__((always_inline)) static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->chmconf[channel].conf1.rx_filter_en_m = enable; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres) { HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chmconf[channel].conf1, rx_filter_thres_m, thres); } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_idle(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->chnconf0[channel].idle_out_en_n = enable; } +__attribute__((always_inline)) static inline bool rmt_ll_is_tx_idle_enabled(rmt_dev_t *dev, uint32_t channel) { return dev->chnconf0[channel].idle_out_en_n; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) { dev->chnconf0[channel].idle_out_lv_n = level; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel) { return dev->chnconf0[channel].idle_out_lv_n; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_channel_status(rmt_dev_t *dev, uint32_t channel) { return dev->chmstatus[channel].val; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_channel_status(rmt_dev_t *dev, uint32_t channel) { return dev->chnstatus[channel].val; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit) { dev->chn_tx_lim[channel].tx_lim_chn = limit; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit) { dev->chm_rx_lim[channel].chm_rx_lim_reg = limit; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_limit(rmt_dev_t *dev, uint32_t channel) { return dev->chm_rx_lim[channel].chm_rx_lim_reg; } +__attribute__((always_inline)) static inline void rmt_ll_enable_interrupt(rmt_dev_t *dev, uint32_t mask, bool enable) { if (enable) { @@ -287,6 +335,7 @@ static inline void rmt_ll_enable_interrupt(rmt_dev_t *dev, uint32_t mask, bool e } } +__attribute__((always_inline)) static inline void rmt_ll_enable_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { if (enable) { @@ -296,6 +345,7 @@ static inline void rmt_ll_enable_tx_end_interrupt(rmt_dev_t *dev, uint32_t chann } } +__attribute__((always_inline)) static inline void rmt_ll_enable_tx_err_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { if (enable) { @@ -305,6 +355,7 @@ static inline void rmt_ll_enable_tx_err_interrupt(rmt_dev_t *dev, uint32_t chann } } +__attribute__((always_inline)) static inline void rmt_ll_enable_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { if (enable) { @@ -314,6 +365,7 @@ static inline void rmt_ll_enable_rx_end_interrupt(rmt_dev_t *dev, uint32_t chann } } +__attribute__((always_inline)) static inline void rmt_ll_enable_rx_err_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { if (enable) { @@ -323,6 +375,7 @@ static inline void rmt_ll_enable_rx_err_interrupt(rmt_dev_t *dev, uint32_t chann } } +__attribute__((always_inline)) static inline void rmt_ll_enable_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { if (enable) { @@ -332,6 +385,7 @@ static inline void rmt_ll_enable_tx_thres_interrupt(rmt_dev_t *dev, uint32_t cha } } +__attribute__((always_inline)) static inline void rmt_ll_enable_tx_loop_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { if (enable) { @@ -341,6 +395,7 @@ static inline void rmt_ll_enable_tx_loop_interrupt(rmt_dev_t *dev, uint32_t chan } } +__attribute__((always_inline)) static inline void rmt_ll_enable_rx_thres_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { if (enable) { @@ -350,76 +405,91 @@ static inline void rmt_ll_enable_rx_thres_interrupt(rmt_dev_t *dev, uint32_t cha } } +__attribute__((always_inline)) static inline void rmt_ll_clear_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel + 16)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_tx_err_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel + 4)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_rx_err_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel + 20)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel + 8)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_tx_loop_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel + 12)); } +__attribute__((always_inline)) static inline void rmt_ll_clear_rx_thres_interrupt(rmt_dev_t *dev, uint32_t channel) { dev->int_clr.val = (1 << (channel + 24)); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev) { return dev->int_st.val & 0x0F; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 16) & 0x0F; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_err_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 4) & 0x0F; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_err_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 20) & 0x0F; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 8) & 0x0F; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_thres_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 24) & 0x0F; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_loop_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 12) & 0x0F; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks) { // In case the compiler optimise a 32bit instruction (e.g. s32i) into two 16bit instruction (e.g. s16i, which is not allowed to access a register) @@ -430,6 +500,7 @@ static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t dev->chncarrier_duty[channel].val = reg.val; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks) { rmt_chm_rx_carrier_rm_reg_t reg; @@ -438,33 +509,39 @@ static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t dev->chm_rx_carrier_rm[channel].val = reg.val; } +__attribute__((always_inline)) static inline void rmt_ll_tx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks ) { *high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->chncarrier_duty[channel], carrier_high_chn); *low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->chncarrier_duty[channel], carrier_low_chn); } +__attribute__((always_inline)) static inline void rmt_ll_rx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks) { *high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->chm_rx_carrier_rm[channel], carrier_high_thres_chm); *low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->chm_rx_carrier_rm[channel], carrier_low_thres_chm); } +__attribute__((always_inline)) static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->chnconf0[channel].carrier_en_n = enable; } +__attribute__((always_inline)) static inline void rmt_ll_rx_enable_carrier_demodulation(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->chmconf[channel].conf0.carrier_en_m = enable; } +__attribute__((always_inline)) static inline void rmt_ll_tx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) { dev->chnconf0[channel].carrier_out_lv_n = level; } +__attribute__((always_inline)) static inline void rmt_ll_rx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) { dev->chmconf[channel].conf0.carrier_out_lv_m = level; @@ -472,6 +549,7 @@ static inline void rmt_ll_rx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, // set true, enable carrier in all RMT state (idle, reading, sending) // set false, enable carrier only in sending state (i.e. there're effective data in RAM to be sent) +__attribute__((always_inline)) static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->chnconf0[channel].carrier_eff_en_n = !enable; @@ -479,6 +557,7 @@ static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t chan //Writes items to the specified TX channel memory with the given offset and length. //the caller should ensure that (length + off) <= (memory block * SOC_RMT_MEM_WORDS_PER_CHANNEL) +__attribute__((always_inline)) static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const void *data, size_t length_in_words, size_t off) { volatile uint32_t *to = (volatile uint32_t *)&mem->chan[channel].data32[off]; @@ -488,6 +567,7 @@ static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const v } } +__attribute__((always_inline)) static inline void rmt_ll_rx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->chmconf[channel].conf1.mem_rx_wrap_en_m = enable;