From 90eada69939c70c2d6273f1b2a2b474ee2f2969b Mon Sep 17 00:00:00 2001 From: TD-er Date: Fri, 10 Nov 2023 22:43:04 +0100 Subject: [PATCH] fix(spi): Correct REG_SPI_BASE(i) macro for all targets The existing formula can never match these registers. Closes https://github.com/espressif/esp-idf/pull/12559 Closes https://github.com/espressif/esp-idf/pull/12562 --- components/soc/esp32c2/include/soc/soc.h | 1 + components/soc/esp32c2/include/soc/spi_reg.h | 3 +-- .../soc/esp32c2/ld/esp32c2.peripherals.ld | 1 - components/soc/esp32c3/include/soc/soc.h | 1 + components/soc/esp32c3/include/soc/spi_reg.h | 20 ++++++------------ .../soc/esp32c3/ld/esp32c3.peripherals.ld | 2 -- components/soc/esp32c6/include/soc/soc.h | 4 ++-- components/soc/esp32h2/include/soc/soc.h | 2 +- components/soc/esp32p4/include/soc/soc.h | 4 ++-- components/soc/esp32s2/include/soc/reg_base.h | 1 - components/soc/esp32s2/include/soc/soc.h | 17 ++++++++------- .../soc/esp32s2/include/soc/spi_mem_reg.h | 21 ++++++------------- components/soc/esp32s2/include/soc/spi_reg.h | 21 ++++++------------- components/soc/esp32s3/include/soc/soc.h | 17 ++++++++------- .../soc/esp32s3/ld/esp32s3.peripherals.ld | 1 - tools/ci/check_copyright_ignore.txt | 3 --- 16 files changed, 44 insertions(+), 75 deletions(-) diff --git a/components/soc/esp32c2/include/soc/soc.h b/components/soc/esp32c2/include/soc/soc.h index cf01bd2b5b26..5186fdb044bd 100644 --- a/components/soc/esp32c2/include/soc/soc.h +++ b/components/soc/esp32c2/include/soc/soc.h @@ -30,6 +30,7 @@ #define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) +#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) //Registers Operation {{ diff --git a/components/soc/esp32c2/include/soc/spi_reg.h b/components/soc/esp32c2/include/soc/spi_reg.h index 24fa77c80ebc..eaa92535e1ec 100644 --- a/components/soc/esp32c2/include/soc/spi_reg.h +++ b/components/soc/esp32c2/include/soc/spi_reg.h @@ -6,12 +6,11 @@ #ifndef _SOC_SPI_REG_H_ #define _SOC_SPI_REG_H_ +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc/soc.h" -#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (i - 2) * 0x1000) #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) /* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */ diff --git a/components/soc/esp32c2/ld/esp32c2.peripherals.ld b/components/soc/esp32c2/ld/esp32c2.peripherals.ld index 9444bc72eeda..a7133c0f505c 100644 --- a/components/soc/esp32c2/ld/esp32c2.peripherals.ld +++ b/components/soc/esp32c2/ld/esp32c2.peripherals.ld @@ -16,7 +16,6 @@ PROVIDE ( LEDC = 0x60019000 ); PROVIDE ( TIMERG0 = 0x6001F000 ); PROVIDE ( SYSTIMER = 0x60023000 ); PROVIDE ( GPSPI2 = 0x60024000 ); -PROVIDE ( GPSPI3 = 0x60025000 ); PROVIDE ( SYSCON = 0x60026000 ); PROVIDE ( APB_SARADC = 0x60040000 ); PROVIDE ( GDMA = 0x6003F000 ); diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index 03f5809be597..0f686cac4afb 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -23,6 +23,7 @@ #define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1E000) #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) +#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) //Registers Operation {{ diff --git a/components/soc/esp32c3/include/soc/spi_reg.h b/components/soc/esp32c3/include/soc/spi_reg.h index a08cb24f3cda..361f58ba5c55 100644 --- a/components/soc/esp32c3/include/soc/spi_reg.h +++ b/components/soc/esp32c3/include/soc/spi_reg.h @@ -1,24 +1,16 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_SPI_REG_H_ #define _SOC_SPI_REG_H_ +#include "soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) /* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */ diff --git a/components/soc/esp32c3/ld/esp32c3.peripherals.ld b/components/soc/esp32c3/ld/esp32c3.peripherals.ld index 84de00a603ab..191e7120c056 100644 --- a/components/soc/esp32c3/ld/esp32c3.peripherals.ld +++ b/components/soc/esp32c3/ld/esp32c3.peripherals.ld @@ -26,10 +26,8 @@ PROVIDE ( TIMERG0 = 0x6001F000 ); PROVIDE ( TIMERG1 = 0x60020000 ); PROVIDE ( SYSTIMER = 0x60023000 ); PROVIDE ( GPSPI2 = 0x60024000 ); -PROVIDE ( GPSPI3 = 0x60025000 ); PROVIDE ( SYSCON = 0x60026000 ); PROVIDE ( TWAI = 0x6002B000 ); -PROVIDE ( GPSPI4 = 0x60037000 ); PROVIDE ( APB_SARADC = 0x60040000 ); PROVIDE ( USB_SERIAL_JTAG = 0x60043000 ); PROVIDE ( GDMA = 0x6003F000 ); diff --git a/components/soc/esp32c6/include/soc/soc.h b/components/soc/esp32c6/include/soc/soc.h index 97fe076c6f3d..2641a8feaf7a 100644 --- a/components/soc/esp32c6/include/soc/soc.h +++ b/components/soc/esp32c6/include/soc/soc.h @@ -23,10 +23,10 @@ #define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C6 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1 -#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE) // only one GPSPI on C6 +#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI on C6 #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C6 #define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE) // only one MCPWM on C6 -#define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x2000) // TWAI0 and TWAI1 +#define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x2000) // TWAI0 and TWAI1 //Registers Operation {{ #define ETS_UNCACHED_ADDR(addr) (addr) diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h index 20a5f057c38d..017ae691a26c 100644 --- a/components/soc/esp32h2/include/soc/soc.h +++ b/components/soc/esp32h2/include/soc/soc.h @@ -23,8 +23,8 @@ #define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1E000) #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) +#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI #define REG_I2C_BASE(i) (DR_REG_I2C_EXT0_BASE + (i) * 0x1000) -#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (i - 2) * 0x1000) //Registers Operation {{ #define ETS_UNCACHED_ADDR(addr) (addr) diff --git a/components/soc/esp32p4/include/soc/soc.h b/components/soc/esp32p4/include/soc/soc.h index 7bbcd0618b25..392ff3f75d9e 100644 --- a/components/soc/esp32p4/include/soc/soc.h +++ b/components/soc/esp32p4/include/soc/soc.h @@ -22,10 +22,10 @@ #define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1000) // only one I2S on C6 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 #define REG_SPI_MEM_BASE(i) (DR_REG_FLASH_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1 -#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (i) * 0x1000) // GPSPI2 and GPSPI3 +#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3 #define REG_I2C_BASE(i) (DR_REG_I2C0_BASE + (i) * 0x1000) #define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE + (i) * 0x1000) -#define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x1000) // TWAI0 and TWAI1 +#define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x1000) // TWAI0 and TWAI1 //Registers Operation {{ #define ETS_UNCACHED_ADDR(addr) (addr) diff --git a/components/soc/esp32s2/include/soc/reg_base.h b/components/soc/esp32s2/include/soc/reg_base.h index dbc2d2a5ccfe..0a809c6ebf70 100644 --- a/components/soc/esp32s2/include/soc/reg_base.h +++ b/components/soc/esp32s2/include/soc/reg_base.h @@ -56,7 +56,6 @@ #define DR_REG_SYSCON_BASE 0x3f426000 #define DR_REG_APB_CTRL_BASE 0x3f426000 /* Old name for SYSCON, to be removed */ #define DR_REG_I2C1_EXT_BASE 0x3f427000 -#define DR_REG_SPI4_BASE 0x3f437000 #define DR_REG_USB_WRAP_BASE 0x3f439000 #define DR_REG_APB_SARADC_BASE 0x3f440000 #define DR_REG_USB_BASE 0x60080000 diff --git a/components/soc/esp32s2/include/soc/soc.h b/components/soc/esp32s2/include/soc/soc.h index 37bf49554bf8..6d59f4163260 100644 --- a/components/soc/esp32s2/include/soc/soc.h +++ b/components/soc/esp32s2/include/soc/soc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -18,14 +18,15 @@ #define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space -#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) -#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 ) -#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 ) -#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE) -#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) +#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) +#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 ) +#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 ) +#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) +#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE) +#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) -#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) +#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3 +#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) //Convenient way to replace the register ops when ulp riscv projects //consume this file diff --git a/components/soc/esp32s2/include/soc/spi_mem_reg.h b/components/soc/esp32s2/include/soc/spi_mem_reg.h index fd3bf04a4197..b08abdc1fbb8 100644 --- a/components/soc/esp32s2/include/soc/spi_mem_reg.h +++ b/components/soc/esp32s2/include/soc/spi_mem_reg.h @@ -1,25 +1,16 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_SPI_MEM_REG_H_ #define _SOC_SPI_MEM_REG_H_ +#include "soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" -#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) #define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x000) /* SPI_MEM_FLASH_READ : R/W ;bitpos:[31] ;default: 1'b0 ; */ diff --git a/components/soc/esp32s2/include/soc/spi_reg.h b/components/soc/esp32s2/include/soc/spi_reg.h index 0f0f732baa51..1097f31a15e2 100644 --- a/components/soc/esp32s2/include/soc/spi_reg.h +++ b/components/soc/esp32s2/include/soc/spi_reg.h @@ -1,25 +1,16 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_SPI_REG_H_ #define _SOC_SPI_REG_H_ +#include "soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" -#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (((i)>3) ? (((i-2)* 0x1000) + 0x10000) : ((i - 2)* 0x1000 ))) #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x000) /* SPI_USR : R/W ;bitpos:[24] ;default: 1'b0 ; */ diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index 37c0cb2502da..b8eb7a877bec 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -27,14 +27,15 @@ #define DR_REG_EXT_MEM_ENC 0x600CC000 -#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) -#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) -#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) -#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000) -#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) +#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) +#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) +#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) +#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) +#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000) +#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) -#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) +#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3 +#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) //Convenient way to replace the register ops when ulp riscv projects //consume this file diff --git a/components/soc/esp32s3/ld/esp32s3.peripherals.ld b/components/soc/esp32s3/ld/esp32s3.peripherals.ld index f75bc70beda1..0b6d8881a23a 100644 --- a/components/soc/esp32s3/ld/esp32s3.peripherals.ld +++ b/components/soc/esp32s3/ld/esp32s3.peripherals.ld @@ -38,7 +38,6 @@ PROVIDE ( SYSCON = 0x60026000 ); PROVIDE ( I2C1 = 0x60027000 ); PROVIDE ( SDMMC = 0x60028000 ); PROVIDE ( TWAI = 0x6002B000 ); -PROVIDE ( GPSPI4 = 0x60037000 ); PROVIDE ( GDMA = 0x6003F000 ); PROVIDE ( UART2 = 0x6002E000 ); PROVIDE ( DMA = 0x6003F000 ); diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index 9091bf4dcdc5..77229a7ff6e2 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -674,7 +674,6 @@ components/soc/esp32c3/include/soc/sensitive_struct.h components/soc/esp32c3/include/soc/soc_pins.h components/soc/esp32c3/include/soc/spi_mem_reg.h components/soc/esp32c3/include/soc/spi_pins.h -components/soc/esp32c3/include/soc/spi_reg.h components/soc/esp32c3/include/soc/systimer_reg.h components/soc/esp32c3/include/soc/systimer_struct.h components/soc/esp32c3/include/soc/uart_pins.h @@ -711,9 +710,7 @@ components/soc/esp32s2/include/soc/rtc_io_reg.h components/soc/esp32s2/include/soc/sens_reg.h components/soc/esp32s2/include/soc/sensitive_reg.h components/soc/esp32s2/include/soc/soc_ulp.h -components/soc/esp32s2/include/soc/spi_mem_reg.h components/soc/esp32s2/include/soc/spi_pins.h -components/soc/esp32s2/include/soc/spi_reg.h components/soc/esp32s2/include/soc/systimer_reg.h components/soc/esp32s2/include/soc/systimer_struct.h components/soc/esp32s2/include/soc/touch_sensor_channel.h