From cf5bdf5e9f122c2a6236c6bf5f0c80c048e5eaf9 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Thu, 24 Oct 2024 14:11:05 +0800 Subject: [PATCH 1/2] fix(esp_hw_support): enable all supported slow clock at pmu_init --- components/esp_hw_support/port/esp32c6/pmu_param.c | 11 ++--------- components/esp_hw_support/port/esp32h2/pmu_param.c | 11 ++--------- 2 files changed, 4 insertions(+), 18 deletions(-) diff --git a/components/esp_hw_support/port/esp32c6/pmu_param.c b/components/esp_hw_support/port/esp32c6/pmu_param.c index 23acfc344727..6b24a4c4d907 100644 --- a/components/esp_hw_support/port/esp32c6/pmu_param.c +++ b/components/esp_hw_support/port/esp32c6/pmu_param.c @@ -336,21 +336,14 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm /** LP system default parameter */ - -#if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL -# define PMU_SLOW_CLK_USE_EXT_XTAL (1) -#else -# define PMU_SLOW_CLK_USE_EXT_XTAL (0) -#endif - #define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \ .dig_power = { \ .mem_dslp = 0, \ .peri_pd_en = 0, \ }, \ .clk_power = { \ - .xpd_xtal32k = PMU_SLOW_CLK_USE_EXT_XTAL, \ - .xpd_rc32k = 0, \ + .xpd_xtal32k = 1, \ + .xpd_rc32k = 1, \ .xpd_fosc = 1, \ .pd_osc = 0 \ } \ diff --git a/components/esp_hw_support/port/esp32h2/pmu_param.c b/components/esp_hw_support/port/esp32h2/pmu_param.c index 56f679a91451..f9de2ca5aebe 100644 --- a/components/esp_hw_support/port/esp32h2/pmu_param.c +++ b/components/esp_hw_support/port/esp32h2/pmu_param.c @@ -335,21 +335,14 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm /** LP system default parameter */ - -#if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL -# define PMU_SLOW_CLK_USE_EXT_XTAL (1) -#else -# define PMU_SLOW_CLK_USE_EXT_XTAL (0) -#endif - #define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \ .dig_power = { \ .mem_dslp = 0, \ .peri_pd_en = 0, \ }, \ .clk_power = { \ - .xpd_xtal32k = PMU_SLOW_CLK_USE_EXT_XTAL, \ - .xpd_rc32k = 0, \ + .xpd_xtal32k = 1, \ + .xpd_rc32k = 1, \ .xpd_fosc = 1, \ .pd_osc = 0 \ } \ From 280f6cb4e9e547d02fcf38ae08ba56b40884b431 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Thu, 24 Oct 2024 14:38:13 +0800 Subject: [PATCH 2/2] fix(esp_hw_support): disable unused clock sources after rtc clock switching complete --- components/esp_system/port/soc/esp32c5/clk.c | 6 ++++++ components/esp_system/port/soc/esp32c6/clk.c | 9 +++++++++ components/esp_system/port/soc/esp32c61/clk.c | 6 ++++++ components/esp_system/port/soc/esp32h2/clk.c | 9 +++++++++ components/esp_system/port/soc/esp32p4/clk.c | 9 +++++++++ 5 files changed, 39 insertions(+) diff --git a/components/esp_system/port/soc/esp32c5/clk.c b/components/esp_system/port/soc/esp32c5/clk.c index 236410e1aa41..6e62a960edde 100644 --- a/components/esp_system/port/soc/esp32c5/clk.c +++ b/components/esp_system/port/soc/esp32c5/clk.c @@ -164,6 +164,12 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src) } rtc_clk_slow_src_set(rtc_slow_clk_src); + // Disable unused clock sources after clock source switching is complete. + // Regardless of the clock source selection, the internal 136K clock source will always keep on. + if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K && rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { + rtc_clk_32k_enable(false); + } + if (SLOW_CLK_CAL_CYCLES > 0) { /* TODO: 32k XTAL oscillator has some frequency drift at startup. * Improve calibration routine to wait until the frequency is stable. diff --git a/components/esp_system/port/soc/esp32c6/clk.c b/components/esp_system/port/soc/esp32c6/clk.c index 23a8ddab32f9..36e023cd561d 100644 --- a/components/esp_system/port/soc/esp32c6/clk.c +++ b/components/esp_system/port/soc/esp32c6/clk.c @@ -185,6 +185,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src) } rtc_clk_slow_src_set(rtc_slow_clk_src); + // Disable unused clock sources after clock source switching is complete. + // Regardless of the clock source selection, the internal 136K clock source will always keep on. + if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K && rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { + rtc_clk_32k_enable(false); + } + if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) { + rtc_clk_rc32k_enable(false); + } + if (SLOW_CLK_CAL_CYCLES > 0) { /* TODO: 32k XTAL oscillator has some frequency drift at startup. * Improve calibration routine to wait until the frequency is stable. diff --git a/components/esp_system/port/soc/esp32c61/clk.c b/components/esp_system/port/soc/esp32c61/clk.c index 035cc1c87f3b..7e865037ab64 100644 --- a/components/esp_system/port/soc/esp32c61/clk.c +++ b/components/esp_system/port/soc/esp32c61/clk.c @@ -148,6 +148,12 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src) } rtc_clk_slow_src_set(rtc_slow_clk_src); + // Disable unused clock sources after clock source switching is complete. + // Regardless of the clock source selection, the internal 136K clock source will always keep on. + if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K && rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { + rtc_clk_32k_enable(false); + } + if (SLOW_CLK_CAL_CYCLES > 0) { /* TODO: 32k XTAL oscillator has some frequency drift at startup. * Improve calibration routine to wait until the frequency is stable. diff --git a/components/esp_system/port/soc/esp32h2/clk.c b/components/esp_system/port/soc/esp32h2/clk.c index 02aa13411a0f..026fd5c19ea1 100644 --- a/components/esp_system/port/soc/esp32h2/clk.c +++ b/components/esp_system/port/soc/esp32h2/clk.c @@ -184,6 +184,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src) } rtc_clk_slow_src_set(rtc_slow_clk_src); + // Disable unused clock sources after clock source switching is complete. + // Regardless of the clock source selection, the internal 136K clock source will always keep on. + if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K && rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { + rtc_clk_32k_enable(false); + } + if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) { + rtc_clk_rc32k_enable(false); + } + if (SLOW_CLK_CAL_CYCLES > 0) { /* TODO: 32k XTAL oscillator has some frequency drift at startup. * Improve calibration routine to wait until the frequency is stable. diff --git a/components/esp_system/port/soc/esp32p4/clk.c b/components/esp_system/port/soc/esp32p4/clk.c index fabbfe22ed06..bb9a6e0aa51b 100644 --- a/components/esp_system/port/soc/esp32p4/clk.c +++ b/components/esp_system/port/soc/esp32p4/clk.c @@ -189,6 +189,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src) } rtc_clk_slow_src_set(rtc_slow_clk_src); + // Disable unused clock sources after clock source switching is complete. + // Regardless of the clock source selection, the internal 136K clock source will always keep on. + if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K) { + rtc_clk_32k_enable(false); + } + if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) { + rtc_clk_rc32k_enable(false); + } + if (SLOW_CLK_CAL_CYCLES > 0) { /* TODO: 32k XTAL oscillator has some frequency drift at startup. * Improve calibration routine to wait until the frequency is stable.