From ebb27d6317bc2b598e921afdae80c7e921c44d3f Mon Sep 17 00:00:00 2001 From: Nate Clark Date: Wed, 5 Jun 2024 02:51:52 -0400 Subject: [PATCH] [ethernet] Adds documentation for setting PHY register values (#3886) --- components/ethernet.rst | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/components/ethernet.rst b/components/ethernet.rst index 9b582763ee..f5779836ba 100644 --- a/components/ethernet.rst +++ b/components/ethernet.rst @@ -72,6 +72,12 @@ RMII configuration variables: - ``GPIO17_OUT`` - Internal clock - **phy_addr** (*Optional*, int): The PHY addr type of the Ethernet controller. Defaults to 0. +- **phy_registers** (*Optional*, mapping): Arbitrary PHY register values to set after Ethernet initialization. + + - **address** (**Required**, hex): The register address as a hex number (e.g. ``0x10`` for address 16) + - **value** (**Required**, hex): The value of the register to set as a hex number (e.g. ``0x1FFA``) + - **page_id** (*Optional*, hex): (RTL8201 only) Register page number to select before writing (e.g. ``0x07`` for page 7) + - **power_pin** (*Optional*, :ref:`Pin Schema `): The pin controlling the power/reset status of the Ethernet controller. Leave unspecified for no power pin (default). @@ -230,6 +236,11 @@ Configuration examples mdio_pin: GPIO17 clk_mode: GPIO0_IN phy_addr: 0 + phy_registers: + - address: 0x10 + value: 0x1FFA + page_id: 0x07 + .. note::