- Circuit: 9-bit signed adders (no overflow)
- Selection criteria: pareto optimal sub-set wrt. pwr and ep parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| add9se_07Y | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| add9se_00E | 0.098 | 0.78 | 12.50 | 0.87 | 2.0 | [Verilog] [C] |
| add9se_028 | 0.45 | 1.56 | 28.91 | 5.32 | 18 | [Verilog] [C] |
| add9se_087 | 0.23 | 0.78 | 37.50 | 2.71 | 4.5 | [Verilog] [C] |
| add9se_0DG | 3.12 | 6.25 | 50.00 | 36.60 | 512 | [Verilog] [C] |
| add9se_05G | 0.94 | 3.12 | 76.56 | 9.87 | 40 | [Verilog] [C] |
| add9se_063 | 0.68 | 1.37 | 87.50 | 7.97 | 18 | [Verilog] [C] |
| add9se_0DV | 14.37 | 49.61 | 99.53 | 69.54 | 8574 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020