- Circuit: 8-bit signed adders (with overflow)
- Selection criteria: pareto optimal sub-set wrt. pwr and ep parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| add8s_83C | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| add8s_83N | 0.16 | 1.56 | 12.50 | 1.29 | 0.5 | [Verilog] [C] |
| add8s_6YG | 5.78 | 12.50 | 46.35 | 39.10 | 119 | [Verilog] [C] |
| add8s_7YK | 30.39 | 100.00 | 54.43 | 150.85 | 3013 | [Verilog] [C] |
| add8s_6S5 | 1.56 | 4.69 | 71.48 | 9.74 | 6.5 | [Verilog] [C] |
| add8s_70Z | 44.77 | 100.00 | 85.42 | 146.36 | 5003 | [Verilog] [C] |
| add8s_6HF | 44.45 | 100.00 | 99.48 | 99.98 | 4551 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020