- Circuit: 12-bit signed adders (no overflow)
- Selection criteria: pareto optimal sub-set wrt. pwr and wce parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| add12se_58Y | 0.012 | 0.024 | 50.00 | 0.21 | 0.5 | [Verilog] [C] |
| add12se_570 | 0.022 | 0.049 | 68.75 | 0.33 | 1.2 | [Verilog] [C] |
| add12se_59E | 0.049 | 0.098 | 87.50 | 0.77 | 5.5 | [Verilog] [C] |
| add12se_54H | 0.10 | 0.22 | 93.75 | 1.57 | 22 | [Verilog] [C] |
| add12se_57E | 0.20 | 0.46 | 96.97 | 3.25 | 90 | [Verilog] [C] |
| add12se_585 | 0.32 | 1.15 | 97.66 | 4.19 | 260 | [Verilog] [C] |
| add12se_5CX | 0.81 | 2.10 | 99.22 | 12.63 | 1513 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020