diff --git a/hdl/rtl/EF_GPIO8.pp.v b/hdl/rtl/EF_GPIO8.pp.v
deleted file mode 100644
index 9be798c..0000000
--- a/hdl/rtl/EF_GPIO8.pp.v
+++ /dev/null
@@ -1,344 +0,0 @@
-/*
-	Copyright 2023 Efabless Corp.
-
-	Author: Mohamed Shalan (mshalan@aucegypt.edu)
-
-	Licensed under the Apache License, Version 2.0 (the "License");
-	you may not use this file except in compliance with the License.
-	You may obtain a copy of the License at
-
-	    http://www.apache.org/licenses/LICENSE-2.0
-
-	Unless required by applicable law or agreed to in writing, software
-	distributed under the License is distributed on an "AS IS" BASIS,
-	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-	See the License for the specific language governing permissions and
-	limitations under the License.
-
-*/
-
-`timescale			    1ns/1ps
-`default_nettype		none
-
-/*
-    Brute-force Synchronizer
-*/
-module aucohl_sync #(parameter NUM_STAGES = 2) (
-    input clk,
-    input in,
-    output out
-);
-
-    reg [NUM_STAGES-1:0] sync;
-
-    always @(posedge clk)
-        sync <= {sync[NUM_STAGES-2:0], in};
-
-    assign out = sync[NUM_STAGES-1];
-
-endmodule
-
-/*
-    A positive edge detector
-*/
-module aucohl_ped (
-    input clk,
-    input in,
-    output out
-);
-    reg last_in; always @(posedge clk) last_in <= in; assign out = in & ~last_in;
-endmodule
-
-/*
-    A negative edge detector
-*/
-module aucohl_ned (
-    input clk,
-    input in,
-    output out
-);
-    reg last_in; always @(posedge clk) last_in <= in; assign out = ~in & last_in;
-endmodule
-
-/*
-    A tick generator
-*/
-module aucohl_ticker #(parameter W=8) (
-    input   wire            clk, 
-    input   wire            rst_n,
-    input   wire            en,
-    input   wire [W-1:0]    clk_div,
-    output  wire            tick
-);
-
-    reg [W-1:0] counter;
-    wire        counter_is_zero = (counter == 'b0);
-    wire        tick_w;
-    reg         tick_reg;
-
-    always @(posedge clk, negedge rst_n)
-        if(~rst_n)
-            counter <=  'b0;
-        else if(en) 
-            if(counter_is_zero)
-                counter <=  clk_div;
-            else
-                counter <=  counter - 'b1; 
-
-    assign tick_w = (clk_div == 'b1)  ?   1'b1 : counter_is_zero;
-
-    always @(posedge clk or negedge rst_n)
-        if(!rst_n)
-            tick_reg <= 1'b0;
-        else if(en)
-            tick_reg <= tick_w;
-        else
-            tick_reg <= 0;
-
-    assign tick = tick_reg;
-
-endmodule
-
-/*
-    A glitch filter
-*/
-module aucohl_glitch_filter #(parameter N = 8, CLKDIV = 1) (
-    input   wire    clk,
-    input   wire    rst_n,
-    input   wire    in,
-    output  reg     out
-);
-
-    reg [N-1:0] shifter;
-    wire        tick;
-
-    aucohl_ticker ticker (
-        .clk(clk),
-        .rst_n(rst_n),
-        .clk_div(CLKDIV),
-        .tick(tick)
-    );
-
-    always @(posedge clk, negedge rst_n)
-        if(!rst_n)
-            shifter = 'b0;
-        else if(tick)
-            shifter <= {shifter[N-2:0], in};
-
-    wire all_ones   = & shifter;
-    wire all_zeros  = ~| shifter;
-
-    always @(posedge clk, negedge rst_n)
-        if(!rst_n)
-            out <= 1'b0;
-        else
-            if(all_ones) 
-                out <= 1'b1;
-            else if(all_zeros) 
-                out <= 1'b0;
-endmodule
-
-/*
-    A FIFO
-*/
-module aucohl_fifo #(parameter DW=8, AW=4)(
-    input     wire            clk,
-    input     wire            rst_n,
-    input     wire            rd,
-    input     wire            wr,
-    input     wire [DW-1:0]   wdata,
-    output    wire            empty,
-    output    wire            full,
-    output    wire [DW-1:0]   rdata,
-    output    wire [AW-1:0]   level    
-);
-
-    localparam  DEPTH = 2**AW;
-
-    //Internal Signal declarations
-    reg [DW-1:0]  array_reg [DEPTH-1:0];
-    reg [AW-1:0]  w_ptr_reg;
-    reg [AW-1:0]  w_ptr_next;
-    reg [AW-1:0]  w_ptr_succ;
-    reg [AW-1:0]  r_ptr_reg;
-    reg [AW-1:0]  r_ptr_next;
-    reg [AW-1:0]  r_ptr_succ;
-
-    // Level
-    reg [AW-1:0] level_reg;
-    reg [AW-1:0] level_next;      
-    reg full_reg;
-    reg empty_reg;
-    reg full_next;
-    reg empty_next;
-
-    wire w_en;
-
-    always @ (posedge clk)
-        if(w_en) begin
-            array_reg[w_ptr_reg] <= wdata;
-        end
-
-    assign rdata = array_reg[r_ptr_reg];   
-    assign w_en = wr & ~full_reg;           
-
-    //State Machine
-    always @ (posedge clk, negedge rst_n) begin 
-    if(!rst_n)
-        begin
-            w_ptr_reg <= 'b0;
-            r_ptr_reg <= 'b0;
-            full_reg  <= 1'b0;
-            empty_reg <= 1'b1;
-            level_reg <= 4'd0;
-        end
-    else
-        begin
-            w_ptr_reg <= w_ptr_next;
-            r_ptr_reg <= r_ptr_next;
-            full_reg  <= full_next;
-            empty_reg <= empty_next;
-            level_reg <= level_next;
-        end
-    end
-
-    //Next State Logic
-    always @* begin
-        w_ptr_succ = w_ptr_reg + 1;
-        r_ptr_succ = r_ptr_reg + 1;
-
-        w_ptr_next = w_ptr_reg;
-        r_ptr_next = r_ptr_reg;
-        full_next = full_reg;
-        empty_next = empty_reg;
-        level_next = level_reg;
-
-        case({w_en,rd})
-            //2'b00: nop
-            2'b01: 
-                if(~empty_reg) begin
-                    r_ptr_next = r_ptr_succ;
-                    full_next = 1'b0;
-                    level_next = level_reg - 1;
-                    if (r_ptr_succ == w_ptr_reg)
-                        empty_next = 1'b1;
-                end
-            
-            2'b10: 
-                if(~full_reg) begin
-                    w_ptr_next = w_ptr_succ;
-                    empty_next = 1'b0;
-                    level_next = level_reg + 1;
-                    if (w_ptr_succ == r_ptr_reg)
-                        full_next = 1'b1;
-                end
-            
-            2'b11: begin
-                w_ptr_next = w_ptr_succ;
-                r_ptr_next = r_ptr_succ;
-            end
-        endcase
-    end
-
-    //Set Full and Empty
-    assign full = full_reg;
-    assign empty = empty_reg;
-    assign level = level_reg;
-  
-endmodule
-
-
-module EF_GPIO8 (
-    input  wire         clk,
-    input  wire         rst_n,
-    input  wire [7:0]   io_in,
-    output wire [7:0]   bus_in,
-    output wire [7:0]   io_out,
-    input  wire [7:0]   bus_out,
-    output wire [7:0]   io_oe,
-    input  wire [7:0]   bus_oe,
-
-    output wire pin0_hi,
-    output wire pin1_hi,
-    output wire pin2_hi,
-    output wire pin3_hi,
-    output wire pin4_hi,
-    output wire pin5_hi,
-    output wire pin6_hi,
-    output wire pin7_hi,
-    
-    output wire pin0_lo,
-    output wire pin1_lo,
-    output wire pin2_lo,
-    output wire pin3_lo,
-    output wire pin4_lo,
-    output wire pin5_lo,
-    output wire pin6_lo,
-    output wire pin7_lo,
-
-    output wire pin0_pe,
-    output wire pin1_pe,
-    output wire pin2_pe,
-    output wire pin3_pe,
-    output wire pin4_pe,
-    output wire pin5_pe,
-    output wire pin6_pe,
-    output wire pin7_pe,
-
-    output wire pin0_ne,
-    output wire pin1_ne,
-    output wire pin2_ne,
-    output wire pin3_ne,
-    output wire pin4_ne,
-    output wire pin5_ne,
-    output wire pin6_ne,
-    output wire pin7_ne
-    
-);
-    wire [7:0] sync_io_in;
-
-    aucohl_sync synchronizer[7:0] (.clk(clk), .in(io_in), .out(sync_io_in));
-    
-    assign bus_in = sync_io_in;
-    assign io_out = bus_out;
-    assign io_oe  = bus_oe;
-
-    assign pin0_hi = (sync_io_in[0] == 1'b1);
-    assign pin1_hi = (sync_io_in[1] == 1'b1);
-    assign pin2_hi = (sync_io_in[2] == 1'b1);
-    assign pin3_hi = (sync_io_in[3] == 1'b1);
-    assign pin4_hi = (sync_io_in[4] == 1'b1);
-    assign pin5_hi = (sync_io_in[5] == 1'b1);
-    assign pin6_hi = (sync_io_in[6] == 1'b1);
-    assign pin7_hi = (sync_io_in[7] == 1'b1);
-    
-    assign pin0_lo = (sync_io_in[0] == 1'b0);
-    assign pin1_lo = (sync_io_in[1] == 1'b0);
-    assign pin2_lo = (sync_io_in[2] == 1'b0);
-    assign pin3_lo = (sync_io_in[3] == 1'b0);
-    assign pin4_lo = (sync_io_in[4] == 1'b0);
-    assign pin5_lo = (sync_io_in[5] == 1'b0);
-    assign pin6_lo = (sync_io_in[6] == 1'b0);
-    assign pin7_lo = (sync_io_in[7] == 1'b0);
-
-    aucohl_ped ped_0 (.clk(clk), .in(sync_io_in[0]), .out(pin0_pe));
-    aucohl_ped ped_1 (.clk(clk), .in(sync_io_in[1]), .out(pin1_pe));
-    aucohl_ped ped_2 (.clk(clk), .in(sync_io_in[2]), .out(pin2_pe));
-    aucohl_ped ped_3 (.clk(clk), .in(sync_io_in[3]), .out(pin3_pe));
-    aucohl_ped ped_4 (.clk(clk), .in(sync_io_in[4]), .out(pin4_pe));
-    aucohl_ped ped_5 (.clk(clk), .in(sync_io_in[5]), .out(pin5_pe));
-    aucohl_ped ped_6 (.clk(clk), .in(sync_io_in[6]), .out(pin6_pe));
-    aucohl_ped ped_7 (.clk(clk), .in(sync_io_in[7]), .out(pin7_pe));
-
-    aucohl_ned ned_0 (.clk(clk), .in(sync_io_in[0]), .out(pin0_ne));
-    aucohl_ned ned_1 (.clk(clk), .in(sync_io_in[1]), .out(pin1_ne));
-    aucohl_ned ned_2 (.clk(clk), .in(sync_io_in[2]), .out(pin2_ne));
-    aucohl_ned ned_3 (.clk(clk), .in(sync_io_in[3]), .out(pin3_ne));
-    aucohl_ned ned_4 (.clk(clk), .in(sync_io_in[4]), .out(pin4_ne));
-    aucohl_ned ned_5 (.clk(clk), .in(sync_io_in[5]), .out(pin5_ne));
-    aucohl_ned ned_6 (.clk(clk), .in(sync_io_in[6]), .out(pin6_ne));
-    aucohl_ned ned_7 (.clk(clk), .in(sync_io_in[7]), .out(pin7_ne));
-
-    
-
-endmodule
diff --git a/hdl/rtl/bus_wrappers/EF_GPIO8_AHBL.pp.v b/hdl/rtl/bus_wrappers/EF_GPIO8_AHBL.pp.v
index 250fa14..10ed449 100644
--- a/hdl/rtl/bus_wrappers/EF_GPIO8_AHBL.pp.v
+++ b/hdl/rtl/bus_wrappers/EF_GPIO8_AHBL.pp.v
@@ -1,7 +1,7 @@
 /*
-	Copyright 2023 Efabless Corp.
+	Copyright 2024 Efabless Corp.
 
-	Author: Mohamed Shalan (mshalan@aucegypt.edu)
+	Author: Mohamed Shalan (mshalan@efabless.com)
 
 	Licensed under the Apache License, Version 2.0 (the "License");
 	you may not use this file except in compliance with the License.
@@ -21,9 +21,89 @@
 
 `timescale			1ns/1ps
 `default_nettype	none
+
+
+
+/*
+	Copyright 2020 AUCOHL
+
+    Author: Mohamed Shalan (mshalan@aucegypt.edu)
+	
+	Licensed under the Apache License, Version 2.0 (the "License"); 
+	you may not use this file except in compliance with the License. 
+	You may obtain a copy of the License at:
+
+	http://www.apache.org/licenses/LICENSE-2.0
+
+	Unless required by applicable law or agreed to in writing, software 
+	distributed under the License is distributed on an "AS IS" BASIS, 
+	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 
+	See the License for the specific language governing permissions and 
+	limitations under the License.
+*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+    
+
+
+
+
+
+
+                                                
+    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
 
 
 module EF_GPIO8_AHBL (
+
+
+
+
 	input wire          HCLK,
                                         input wire          HRESETn,
                                         input wire          HWRITE,
@@ -36,26 +116,44 @@ module EF_GPIO8_AHBL (
                                         output wire [31:0]  HRDATA,
                                         output wire         IRQ
 ,
-	input	[7:0]	io_in,
-	output	[7:0]	io_out,
-	output	[7:0]	io_oe
+	input	wire	[8-1:0]	io_in,
+	output	wire	[8-1:0]	io_out,
+	output	wire	[8-1:0]	io_oe
 );
 
-	localparam	DATAI_REG_OFFSET = 16'd0;
-	localparam	DATAO_REG_OFFSET = 16'd4;
-	localparam	DIR_REG_OFFSET = 16'd8;
-	localparam	IM_REG_OFFSET = 16'd3840;
-	localparam	MIS_REG_OFFSET = 16'd3844;
-	localparam	RIS_REG_OFFSET = 16'd3848;
-	localparam	IC_REG_OFFSET = 16'd3852;
+	localparam	DATAI_REG_OFFSET = 16'h0000;
+	localparam	DATAO_REG_OFFSET = 16'h0004;
+	localparam	DIR_REG_OFFSET = 16'h0008;
+	localparam	IM_REG_OFFSET = 16'hFF00;
+	localparam	MIS_REG_OFFSET = 16'hFF04;
+	localparam	RIS_REG_OFFSET = 16'hFF08;
+	localparam	IC_REG_OFFSET = 16'hFF0C;
 
-	wire		clk = HCLK;
+    reg [0:0] GCLK_REG;
+    wire clk_g;
+    wire clk_gated_en = GCLK_REG[0];
+    ef_gating_cell clk_gate_cell(
+        
+
+
+ // USE_POWER_PINS
+        .clk(HCLK),
+        .clk_en(clk_gated_en),
+        .clk_o(clk_g)
+    );
+    
+	wire		clk = clk_g;
 	wire		rst_n = HRESETn;
 
 
 	reg  last_HSEL, last_HWRITE; reg [31:0] last_HADDR; reg [1:0] last_HTRANS;
-                                        always@ (posedge HCLK) begin
-                                            if(HREADY) begin
+                                        always@ (posedge HCLK or negedge HRESETn) begin
+					   if(~HRESETn) begin
+					       last_HSEL       <= 1'b0;
+					       last_HADDR      <= 1'b0;
+					       last_HWRITE     <= 1'b0;
+					       last_HTRANS     <= 1'b0;
+				            end else if(HREADY) begin
                                                 last_HSEL       <= HSEL;
                                                 last_HADDR      <= HADDR;
                                                 last_HWRITE     <= HWRITE;
@@ -102,22 +200,27 @@ module EF_GPIO8_AHBL (
 	wire [1-1:0]	pin6_ne;
 	wire [1-1:0]	pin7_ne;
 
-
+	// Register Definitions
 	wire [8-1:0]	DATAI_WIRE;
 	assign	DATAI_WIRE = bus_in;
 
-	reg [8-1:0]	DATAO_REG;
+	reg [7:0]	DATAO_REG;
 	assign	bus_out = DATAO_REG;
 	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) DATAO_REG <= 0;
                                         else if(ahbl_we & (last_HADDR[16-1:0]==DATAO_REG_OFFSET))
                                             DATAO_REG <= HWDATA[8-1:0];
 
-	reg [8-1:0]	DIR_REG;
+	reg [7:0]	DIR_REG;
 	assign	bus_oe = DIR_REG;
 	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) DIR_REG <= 0;
                                         else if(ahbl_we & (last_HADDR[16-1:0]==DIR_REG_OFFSET))
                                             DIR_REG <= HWDATA[8-1:0];
 
+	localparam	GCLK_REG_OFFSET = 16'hFF10;
+	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) GCLK_REG <= 0;
+                                        else if(ahbl_we & (last_HADDR[16-1:0]==GCLK_REG_OFFSET))
+                                            GCLK_REG <= HWDATA[1-1:0];
+
 	reg [31:0] IM_REG;
 	reg [31:0] IC_REG;
 	reg [31:0] RIS_REG;
@@ -318,6 +421,7 @@ module EF_GPIO8_AHBL (
 			(last_HADDR[16-1:0] == MIS_REG_OFFSET)	? MIS_REG :
 			(last_HADDR[16-1:0] == RIS_REG_OFFSET)	? RIS_REG :
 			(last_HADDR[16-1:0] == IC_REG_OFFSET)	? IC_REG :
+			(last_HADDR[16-1:0] == GCLK_REG_OFFSET)	? GCLK_REG :
 			32'hDEADBEEF;
 
 	assign	HREADYOUT = 1'b1;
diff --git a/hdl/rtl/bus_wrappers/EF_GPIO8_AHBL.v b/hdl/rtl/bus_wrappers/EF_GPIO8_AHBL.v
index a434ff9..5ab2223 100644
--- a/hdl/rtl/bus_wrappers/EF_GPIO8_AHBL.v
+++ b/hdl/rtl/bus_wrappers/EF_GPIO8_AHBL.v
@@ -1,7 +1,7 @@
 /*
-	Copyright 2023 Efabless Corp.
+	Copyright 2024 Efabless Corp.
 
-	Author: Mohamed Shalan (mshalan@aucegypt.edu)
+	Author: Mohamed Shalan (mshalan@efabless.com)
 
 	Licensed under the Apache License, Version 2.0 (the "License");
 	you may not use this file except in compliance with the License.
@@ -22,26 +22,43 @@
 `timescale			1ns/1ps
 `default_nettype	none
 
-`define				AHBL_AW			16
+`define				AHBL_AW		16
 
 `include			"ahbl_wrapper.vh"
 
 module EF_GPIO8_AHBL (
+`ifdef USE_POWER_PINS
+	inout VPWR,
+	inout VGND,
+`endif
 	`AHBL_SLAVE_PORTS,
-	input	[7:0]	io_in,
-	output	[7:0]	io_out,
-	output	[7:0]	io_oe
+	input	wire	[8-1:0]	io_in,
+	output	wire	[8-1:0]	io_out,
+	output	wire	[8-1:0]	io_oe
 );
 
-	localparam	DATAI_REG_OFFSET = `AHBL_AW'd0;
-	localparam	DATAO_REG_OFFSET = `AHBL_AW'd4;
-	localparam	DIR_REG_OFFSET = `AHBL_AW'd8;
-	localparam	IM_REG_OFFSET = `AHBL_AW'd3840;
-	localparam	MIS_REG_OFFSET = `AHBL_AW'd3844;
-	localparam	RIS_REG_OFFSET = `AHBL_AW'd3848;
-	localparam	IC_REG_OFFSET = `AHBL_AW'd3852;
+	localparam	DATAI_REG_OFFSET = `AHBL_AW'h0000;
+	localparam	DATAO_REG_OFFSET = `AHBL_AW'h0004;
+	localparam	DIR_REG_OFFSET = `AHBL_AW'h0008;
+	localparam	IM_REG_OFFSET = `AHBL_AW'hFF00;
+	localparam	MIS_REG_OFFSET = `AHBL_AW'hFF04;
+	localparam	RIS_REG_OFFSET = `AHBL_AW'hFF08;
+	localparam	IC_REG_OFFSET = `AHBL_AW'hFF0C;
 
-	wire		clk = HCLK;
+    reg [0:0] GCLK_REG;
+    wire clk_g;
+    wire clk_gated_en = GCLK_REG[0];
+    ef_gating_cell clk_gate_cell(
+        `ifdef USE_POWER_PINS 
+        .vpwr(VPWR),
+        .vgnd(VGND),
+        `endif // USE_POWER_PINS
+        .clk(HCLK),
+        .clk_en(clk_gated_en),
+        .clk_o(clk_g)
+    );
+    
+	wire		clk = clk_g;
 	wire		rst_n = HRESETn;
 
 
@@ -83,18 +100,21 @@ module EF_GPIO8_AHBL (
 	wire [1-1:0]	pin6_ne;
 	wire [1-1:0]	pin7_ne;
 
-
+	// Register Definitions
 	wire [8-1:0]	DATAI_WIRE;
 	assign	DATAI_WIRE = bus_in;
 
-	reg [8-1:0]	DATAO_REG;
+	reg [7:0]	DATAO_REG;
 	assign	bus_out = DATAO_REG;
 	`AHBL_REG(DATAO_REG, 0, 8)
 
-	reg [8-1:0]	DIR_REG;
+	reg [7:0]	DIR_REG;
 	assign	bus_oe = DIR_REG;
 	`AHBL_REG(DIR_REG, 0, 8)
 
+	localparam	GCLK_REG_OFFSET = `AHBL_AW'hFF10;
+	`AHBL_REG(GCLK_REG, 0, 1)
+
 	reg [31:0] IM_REG;
 	reg [31:0] IC_REG;
 	reg [31:0] RIS_REG;
@@ -290,6 +310,7 @@ module EF_GPIO8_AHBL (
 			(last_HADDR[`AHBL_AW-1:0] == MIS_REG_OFFSET)	? MIS_REG :
 			(last_HADDR[`AHBL_AW-1:0] == RIS_REG_OFFSET)	? RIS_REG :
 			(last_HADDR[`AHBL_AW-1:0] == IC_REG_OFFSET)	? IC_REG :
+			(last_HADDR[`AHBL_AW-1:0] == GCLK_REG_OFFSET)	? GCLK_REG :
 			32'hDEADBEEF;
 
 	assign	HREADYOUT = 1'b1;
diff --git a/hdl/rtl/bus_wrappers/EF_GPIO8_APB.pp.v b/hdl/rtl/bus_wrappers/EF_GPIO8_APB.pp.v
index 3dca753..839ddbe 100644
--- a/hdl/rtl/bus_wrappers/EF_GPIO8_APB.pp.v
+++ b/hdl/rtl/bus_wrappers/EF_GPIO8_APB.pp.v
@@ -1,7 +1,7 @@
 /*
-	Copyright 2023 Efabless Corp.
+	Copyright 2024 Efabless Corp.
 
-	Author: Mohamed Shalan (mshalan@aucegypt.edu)
+	Author: Mohamed Shalan (mshalan@efabless.com)
 
 	Licensed under the Apache License, Version 2.0 (the "License");
 	you may not use this file except in compliance with the License.
@@ -61,6 +61,32 @@
 
 
 
+
+
+
+    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
 
 
 
@@ -72,6 +98,10 @@
 
 
 module EF_GPIO8_APB (
+
+
+
+
 	input wire          PCLK,
                                         input wire          PRESETn,
                                         input wire          PWRITE,
@@ -83,20 +113,33 @@ module EF_GPIO8_APB (
                                         output wire [31:0]  PRDATA,
                                         output wire         IRQ
 ,
-	input	[7:0]	io_in,
-	output	[7:0]	io_out,
-	output	[7:0]	io_oe
+	input	wire	[8-1:0]	io_in,
+	output	wire	[8-1:0]	io_out,
+	output	wire	[8-1:0]	io_oe
 );
 
-	localparam	DATAI_REG_OFFSET = 16'd0;
-	localparam	DATAO_REG_OFFSET = 16'd4;
-	localparam	DIR_REG_OFFSET = 16'd8;
-	localparam	IM_REG_OFFSET = 16'd3840;
-	localparam	MIS_REG_OFFSET = 16'd3844;
-	localparam	RIS_REG_OFFSET = 16'd3848;
-	localparam	IC_REG_OFFSET = 16'd3852;
-
-	wire		clk = PCLK;
+	localparam	DATAI_REG_OFFSET = 16'h0000;
+	localparam	DATAO_REG_OFFSET = 16'h0004;
+	localparam	DIR_REG_OFFSET = 16'h0008;
+	localparam	IM_REG_OFFSET = 16'hFF00;
+	localparam	MIS_REG_OFFSET = 16'hFF04;
+	localparam	RIS_REG_OFFSET = 16'hFF08;
+	localparam	IC_REG_OFFSET = 16'hFF0C;
+
+    reg [0:0] GCLK_REG;
+    wire clk_g;
+    wire clk_gated_en = GCLK_REG[0];
+    ef_gating_cell clk_gate_cell(
+        
+
+
+ // USE_POWER_PINS
+        .clk(PCLK),
+        .clk_en(clk_gated_en),
+        .clk_o(clk_g)
+    );
+    
+	wire		clk = clk_g;
 	wire		rst_n = PRESETn;
 
 
@@ -140,22 +183,27 @@ module EF_GPIO8_APB (
 	wire [1-1:0]	pin6_ne;
 	wire [1-1:0]	pin7_ne;
 
-
+	// Register Definitions
 	wire [8-1:0]	DATAI_WIRE;
 	assign	DATAI_WIRE = bus_in;
 
-	reg [8-1:0]	DATAO_REG;
+	reg [7:0]	DATAO_REG;
 	assign	bus_out = DATAO_REG;
 	always @(posedge PCLK or negedge PRESETn) if(~PRESETn) DATAO_REG <= 0;
                                         else if(apb_we & (PADDR[16-1:0]==DATAO_REG_OFFSET))
                                             DATAO_REG <= PWDATA[8-1:0];
 
-	reg [8-1:0]	DIR_REG;
+	reg [7:0]	DIR_REG;
 	assign	bus_oe = DIR_REG;
 	always @(posedge PCLK or negedge PRESETn) if(~PRESETn) DIR_REG <= 0;
                                         else if(apb_we & (PADDR[16-1:0]==DIR_REG_OFFSET))
                                             DIR_REG <= PWDATA[8-1:0];
 
+	localparam	GCLK_REG_OFFSET = 16'hFF10;
+	always @(posedge PCLK or negedge PRESETn) if(~PRESETn) GCLK_REG <= 0;
+                                        else if(apb_we & (PADDR[16-1:0]==GCLK_REG_OFFSET))
+                                            GCLK_REG <= PWDATA[1-1:0];
+
 	reg [31:0] IM_REG;
 	reg [31:0] IC_REG;
 	reg [31:0] RIS_REG;
@@ -357,8 +405,9 @@ module EF_GPIO8_APB (
 			(PADDR[16-1:0] == MIS_REG_OFFSET)	? MIS_REG :
 			(PADDR[16-1:0] == RIS_REG_OFFSET)	? RIS_REG :
 			(PADDR[16-1:0] == IC_REG_OFFSET)	? IC_REG :
+			(PADDR[16-1:0] == GCLK_REG_OFFSET)	? GCLK_REG :
 			32'hDEADBEEF;
 
-	assign PREADY = 1'b1;
+	assign	PREADY = 1'b1;
 
 endmodule
diff --git a/hdl/rtl/bus_wrappers/EF_GPIO8_APB.v b/hdl/rtl/bus_wrappers/EF_GPIO8_APB.v
index 82ca7bd..3b3f191 100644
--- a/hdl/rtl/bus_wrappers/EF_GPIO8_APB.v
+++ b/hdl/rtl/bus_wrappers/EF_GPIO8_APB.v
@@ -1,7 +1,7 @@
 /*
-	Copyright 2023 Efabless Corp.
+	Copyright 2024 Efabless Corp.
 
-	Author: Mohamed Shalan (mshalan@aucegypt.edu)
+	Author: Mohamed Shalan (mshalan@efabless.com)
 
 	Licensed under the Apache License, Version 2.0 (the "License");
 	you may not use this file except in compliance with the License.
@@ -22,26 +22,43 @@
 `timescale			1ns/1ps
 `default_nettype	none
 
-`define				APB_AW			16
+`define				APB_AW		16
 
 `include			"apb_wrapper.vh"
 
 module EF_GPIO8_APB (
+`ifdef USE_POWER_PINS
+	inout VPWR,
+	inout VGND,
+`endif
 	`APB_SLAVE_PORTS,
-	input	[7:0]	io_in,
-	output	[7:0]	io_out,
-	output	[7:0]	io_oe
+	input	wire	[8-1:0]	io_in,
+	output	wire	[8-1:0]	io_out,
+	output	wire	[8-1:0]	io_oe
 );
 
-	localparam	DATAI_REG_OFFSET = `APB_AW'd0;
-	localparam	DATAO_REG_OFFSET = `APB_AW'd4;
-	localparam	DIR_REG_OFFSET = `APB_AW'd8;
-	localparam	IM_REG_OFFSET = `APB_AW'd3840;
-	localparam	MIS_REG_OFFSET = `APB_AW'd3844;
-	localparam	RIS_REG_OFFSET = `APB_AW'd3848;
-	localparam	IC_REG_OFFSET = `APB_AW'd3852;
+	localparam	DATAI_REG_OFFSET = `APB_AW'h0000;
+	localparam	DATAO_REG_OFFSET = `APB_AW'h0004;
+	localparam	DIR_REG_OFFSET = `APB_AW'h0008;
+	localparam	IM_REG_OFFSET = `APB_AW'hFF00;
+	localparam	MIS_REG_OFFSET = `APB_AW'hFF04;
+	localparam	RIS_REG_OFFSET = `APB_AW'hFF08;
+	localparam	IC_REG_OFFSET = `APB_AW'hFF0C;
 
-	wire		clk = PCLK;
+    reg [0:0] GCLK_REG;
+    wire clk_g;
+    wire clk_gated_en = GCLK_REG[0];
+    ef_gating_cell clk_gate_cell(
+        `ifdef USE_POWER_PINS 
+        .vpwr(VPWR),
+        .vgnd(VGND),
+        `endif // USE_POWER_PINS
+        .clk(PCLK),
+        .clk_en(clk_gated_en),
+        .clk_o(clk_g)
+    );
+    
+	wire		clk = clk_g;
 	wire		rst_n = PRESETn;
 
 
@@ -83,18 +100,21 @@ module EF_GPIO8_APB (
 	wire [1-1:0]	pin6_ne;
 	wire [1-1:0]	pin7_ne;
 
-
+	// Register Definitions
 	wire [8-1:0]	DATAI_WIRE;
 	assign	DATAI_WIRE = bus_in;
 
-	reg [8-1:0]	DATAO_REG;
+	reg [7:0]	DATAO_REG;
 	assign	bus_out = DATAO_REG;
 	`APB_REG(DATAO_REG, 0, 8)
 
-	reg [8-1:0]	DIR_REG;
+	reg [7:0]	DIR_REG;
 	assign	bus_oe = DIR_REG;
 	`APB_REG(DIR_REG, 0, 8)
 
+	localparam	GCLK_REG_OFFSET = `APB_AW'hFF10;
+	`APB_REG(GCLK_REG, 0, 1)
+
 	reg [31:0] IM_REG;
 	reg [31:0] IC_REG;
 	reg [31:0] RIS_REG;
@@ -290,8 +310,9 @@ module EF_GPIO8_APB (
 			(PADDR[`APB_AW-1:0] == MIS_REG_OFFSET)	? MIS_REG :
 			(PADDR[`APB_AW-1:0] == RIS_REG_OFFSET)	? RIS_REG :
 			(PADDR[`APB_AW-1:0] == IC_REG_OFFSET)	? IC_REG :
+			(PADDR[`APB_AW-1:0] == GCLK_REG_OFFSET)	? GCLK_REG :
 			32'hDEADBEEF;
 
-	assign PREADY = 1'b1;
+	assign	PREADY = 1'b1;
 
 endmodule
diff --git a/hdl/rtl/bus_wrappers/EF_GPIO8_WB.pp.v b/hdl/rtl/bus_wrappers/EF_GPIO8_WB.pp.v
index 1990906..08bf3ab 100644
--- a/hdl/rtl/bus_wrappers/EF_GPIO8_WB.pp.v
+++ b/hdl/rtl/bus_wrappers/EF_GPIO8_WB.pp.v
@@ -1,5 +1,5 @@
 /*
-	Copyright 2023 Efabless Corp.
+	Copyright 2024 Efabless Corp.
 
 	Author: Mohamed Shalan (mshalan@efabless.com)
 
@@ -21,9 +21,66 @@
 
 `timescale			1ns/1ps
 `default_nettype	none
+
+
+
+/*
+	Copyright 2020 AUCOHL
+
+    Author: Mohamed Shalan (mshalan@aucegypt.edu)
+	
+	Licensed under the Apache License, Version 2.0 (the "License"); 
+	you may not use this file except in compliance with the License. 
+	You may obtain a copy of the License at:
+
+	http://www.apache.org/licenses/LICENSE-2.0
+
+	Unless required by applicable law or agreed to in writing, software 
+	distributed under the License is distributed on an "AS IS" BASIS, 
+	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 
+	See the License for the specific language governing permissions and 
+	limitations under the License.
+*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+                                        
 
 
 module EF_GPIO8_WB (
+
+
+
+
 	input   wire            ext_clk,
                                         input   wire            clk_i,
                                         input   wire            rst_i,
@@ -36,20 +93,33 @@ module EF_GPIO8_WB (
                                         output  reg             ack_o,
                                         input   wire            we_i,
                                         output  wire            IRQ,
-	input	[7:0]	io_in,
-	output	[7:0]	io_out,
-	output	[7:0]	io_oe
+	input	wire	[8-1:0]	io_in,
+	output	wire	[8-1:0]	io_out,
+	output	wire	[8-1:0]	io_oe
 );
 
-	localparam	DATAI_REG_OFFSET = 16'd0;
-	localparam	DATAO_REG_OFFSET = 16'd4;
-	localparam	DIR_REG_OFFSET = 16'd8;
-	localparam	IM_REG_OFFSET = 16'd3840;
-	localparam	MIS_REG_OFFSET = 16'd3844;
-	localparam	RIS_REG_OFFSET = 16'd3848;
-	localparam	IC_REG_OFFSET = 16'd3852;
+	localparam	DATAI_REG_OFFSET = 16'h0000;
+	localparam	DATAO_REG_OFFSET = 16'h0004;
+	localparam	DIR_REG_OFFSET = 16'h0008;
+	localparam	IM_REG_OFFSET = 16'hFF00;
+	localparam	MIS_REG_OFFSET = 16'hFF04;
+	localparam	RIS_REG_OFFSET = 16'hFF08;
+	localparam	IC_REG_OFFSET = 16'hFF0C;
 
-	wire		clk = clk_i;
+    reg [0:0] GCLK_REG;
+    wire clk_g;
+    wire clk_gated_en = GCLK_REG[0];
+    ef_gating_cell clk_gate_cell(
+        
+
+
+ // USE_POWER_PINS
+        .clk(clk_i),
+        .clk_en(clk_gated_en),
+        .clk_o(clk_g)
+    );
+    
+	wire		clk = clk_g;
 	wire		rst_n = (~rst_i);
 
 
@@ -94,17 +164,21 @@ module EF_GPIO8_WB (
 	wire [1-1:0]	pin6_ne;
 	wire [1-1:0]	pin7_ne;
 
+	// Register Definitions
 	wire [8-1:0]	DATAI_WIRE;
 	assign	DATAI_WIRE = bus_in;
 
-	reg [8-1:0]	DATAO_REG;
+	reg [7:0]	DATAO_REG;
 	assign	bus_out = DATAO_REG;
 	always @(posedge clk_i or posedge rst_i) if(rst_i) DATAO_REG <= 0; else if(wb_we & (adr_i[16-1:0]==DATAO_REG_OFFSET)) DATAO_REG <= dat_i[8-1:0];
 
-	reg [8-1:0]	DIR_REG;
+	reg [7:0]	DIR_REG;
 	assign	bus_oe = DIR_REG;
 	always @(posedge clk_i or posedge rst_i) if(rst_i) DIR_REG <= 0; else if(wb_we & (adr_i[16-1:0]==DIR_REG_OFFSET)) DIR_REG <= dat_i[8-1:0];
 
+	localparam	GCLK_REG_OFFSET = 16'hFF10;
+	always @(posedge clk_i or posedge rst_i) if(rst_i) GCLK_REG <= 0; else if(wb_we & (adr_i[16-1:0]==GCLK_REG_OFFSET)) GCLK_REG <= dat_i[1-1:0];
+
 	reg [31:0] IM_REG;
 	reg [31:0] IC_REG;
 	reg [31:0] RIS_REG;
diff --git a/hdl/rtl/bus_wrappers/EF_GPIO8_WB.v b/hdl/rtl/bus_wrappers/EF_GPIO8_WB.v
index 9913a3b..32dbb23 100644
--- a/hdl/rtl/bus_wrappers/EF_GPIO8_WB.v
+++ b/hdl/rtl/bus_wrappers/EF_GPIO8_WB.v
@@ -1,5 +1,5 @@
 /*
-	Copyright 2023 Efabless Corp.
+	Copyright 2024 Efabless Corp.
 
 	Author: Mohamed Shalan (mshalan@efabless.com)
 
@@ -27,21 +27,38 @@
 `include			"wb_wrapper.vh"
 
 module EF_GPIO8_WB (
+`ifdef USE_POWER_PINS
+	inout VPWR,
+	inout VGND,
+`endif
 	`WB_SLAVE_PORTS,
-	input	[7:0]	io_in,
-	output	[7:0]	io_out,
-	output	[7:0]	io_oe
+	input	wire	[8-1:0]	io_in,
+	output	wire	[8-1:0]	io_out,
+	output	wire	[8-1:0]	io_oe
 );
 
-	localparam	DATAI_REG_OFFSET = `WB_AW'd0;
-	localparam	DATAO_REG_OFFSET = `WB_AW'd4;
-	localparam	DIR_REG_OFFSET = `WB_AW'd8;
-	localparam	IM_REG_OFFSET = `WB_AW'd3840;
-	localparam	MIS_REG_OFFSET = `WB_AW'd3844;
-	localparam	RIS_REG_OFFSET = `WB_AW'd3848;
-	localparam	IC_REG_OFFSET = `WB_AW'd3852;
+	localparam	DATAI_REG_OFFSET = `WB_AW'h0000;
+	localparam	DATAO_REG_OFFSET = `WB_AW'h0004;
+	localparam	DIR_REG_OFFSET = `WB_AW'h0008;
+	localparam	IM_REG_OFFSET = `WB_AW'hFF00;
+	localparam	MIS_REG_OFFSET = `WB_AW'hFF04;
+	localparam	RIS_REG_OFFSET = `WB_AW'hFF08;
+	localparam	IC_REG_OFFSET = `WB_AW'hFF0C;
 
-	wire		clk = clk_i;
+    reg [0:0] GCLK_REG;
+    wire clk_g;
+    wire clk_gated_en = GCLK_REG[0];
+    ef_gating_cell clk_gate_cell(
+        `ifdef USE_POWER_PINS 
+        .vpwr(VPWR),
+        .vgnd(VGND),
+        `endif // USE_POWER_PINS
+        .clk(clk_i),
+        .clk_en(clk_gated_en),
+        .clk_o(clk_g)
+    );
+    
+	wire		clk = clk_g;
 	wire		rst_n = (~rst_i);
 
 
@@ -83,17 +100,21 @@ module EF_GPIO8_WB (
 	wire [1-1:0]	pin6_ne;
 	wire [1-1:0]	pin7_ne;
 
+	// Register Definitions
 	wire [8-1:0]	DATAI_WIRE;
 	assign	DATAI_WIRE = bus_in;
 
-	reg [8-1:0]	DATAO_REG;
+	reg [7:0]	DATAO_REG;
 	assign	bus_out = DATAO_REG;
 	`WB_REG(DATAO_REG, 0, 8)
 
-	reg [8-1:0]	DIR_REG;
+	reg [7:0]	DIR_REG;
 	assign	bus_oe = DIR_REG;
 	`WB_REG(DIR_REG, 0, 8)
 
+	localparam	GCLK_REG_OFFSET = `WB_AW'hFF10;
+	`WB_REG(GCLK_REG, 0, 1)
+
 	reg [31:0] IM_REG;
 	reg [31:0] IC_REG;
 	reg [31:0] RIS_REG;
diff --git a/ip/.gitignore b/ip/.gitignore
new file mode 100644
index 0000000..83fe78c
--- /dev/null
+++ b/ip/.gitignore
@@ -0,0 +1,3 @@
+*
+!dependencies.json
+!.gitignore
diff --git a/ip/dependencies.json b/ip/dependencies.json
new file mode 100644
index 0000000..bc86f84
--- /dev/null
+++ b/ip/dependencies.json
@@ -0,0 +1,7 @@
+{
+    "IP": [
+        {
+            "IP_Utilities": "v1.0.0"
+        }
+    ]
+}
\ No newline at end of file
diff --git a/verify/uvm-python/Makefile b/verify/uvm-python/Makefile
index f6e4240..33eca9d 100644
--- a/verify/uvm-python/Makefile
+++ b/verify/uvm-python/Makefile
@@ -4,7 +4,7 @@ MODULE   ?= top_module
 AHB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_GPIO8_AHBL.pp.v
 APB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_GPIO8_APB.pp.v
 WB_FILES ?= ""
-HDL_FILES ?= $(PWD)/../../hdl/rtl/EF_GPIO8.pp.v
+HDL_FILES ?= $(PWD)/../../hdl/rtl/EF_GPIO8.v $(PWD)/../../ip/IP_Utilities/rtl/aucohl_lib.v
 VERILOG_SOURCES ?=  $(PWD)/top.v $(AHB_FILES) $(APB_FILES) $(WB_FILES) $(HDL_FILES)
 RTL_MACROS += ""
 BUS_TYPE ?= APB