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<!DOCTYPE HTML>
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<title>direction - DSML 411lab</title>
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<body>
<div id="header">
<div class='language'><a class='language'href='direction.html'>中文</a> / English</div>
<a href="en_home.html" class="logo"><img src="images/logo.png" alt=""></a>
<ul>
<li>
<a href="en_home.html">news</a>
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<a href="en_about.html">home</a>
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<a href="en_direction.html">topics</a>
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<h1 style='border: 1px none powderblue;margin:10px;padding:10px;font-weight:bold;font-size=larger;text-shadow: 1px 1px 3px black;'>
Research Topics
</h1>
<hr style='border-width: 2px;'>
<p style="font-size: 18px;line-height: 30px;font-family: Calibri;">
半導體自1960年代以來演變至今近一甲子，其技術推動人類社會快速演變堪為自有文明歷史以來最深刻之改變。<br><br>
而這之中最重要的便是電晶體的發明使得電訊號首次能夠被人類安排與使用來實現各式各樣的功能，比如做為電訊號的開關
，或是放大與縮小和調變電訊號，從而能處理與計算和儲存電訊號，也可傳輸與接收電訊號，成為現代科技發展之基石。
隨著人類社會複雜地演化與文明生活渴求更便利更有效率的生活方式，人類需要電晶體的機會與場合越來越多，因此積體電路之發明
便是自然而然地迎合這樣之趨勢，讓有限與微小的矽基面積上聚合上億顆電晶體，在這些電晶體不同地搭配與組合下，
半導體技術成功地滿足現代社會各式各樣地需求，比如大量繁重的文書處理，精密的工業自動化與製造，各種精巧的隨身攜帶
電子用品能夠監控身理數據，與行動電話....等等。這是由於半導體的積體電路隨著技術的發展與演進可以提供更精巧且功能更強大的電晶體。
這便是電晶體之<b>"微縮"(scale down)。</b><br><br>
電晶體之微縮依循著<b>摩爾定律(Moore's law)</b>，摩爾定律不是一個物理或化學之嚴謹的定律。與此相反
摩爾定律是用來描述與歸納半導體產業與人類社會交互作用下的經濟行為，所以摩爾定律是一項經濟之定律，它描述著電晶體之面積必須隨著
一定時間縮小，從而使得電晶體越來越細小越來越便宜但功能卻越來越強大。
隨著半導體的從業人員大量地投入研發工作，電晶體已經微縮至20奈米(一奈米等於十個負九次方米)以下逐漸地面臨到物理極限，而減慢了
微縮的腳步，但人類對未來的想像與美好生活的憧憬是沒有極限且不會停止的，因此另一股趨動半導體技術演進地力量油然而生，在既有地技術平台上
附加更多價值，產生更多應用，結合其它領域之技術利用半導體來實現，比如生醫領域，人工智慧領域，機械領域，等等，而附與半導體新的生命與面相
這便是<b>"超越摩爾定律"(More than Moore)</b>所要講述的。下圖是著名的<b>"Moore's law X More than Moore"</b>圖，y軸是Moore's law講地是電晶體之微縮以追求更小面積更便宜功能越強大之晶片，目前已觸及7nm，
還會繼續往5nm, 3nm, 2nm, 1nm繼續延伸；而X軸則是More than Moore讓單一顆晶片實現更多功能賦予更高價值。<br><br>
本實驗室即是依循這兩個面向，除了針對固有的電晶體微縮化所遭遇之課題繼續深入地鑽研與研究，包含了<b>三維電晶體(FinFET)</b>和<b>次世代之電晶體-穿隧型電晶體(Tunnel FET-TFET)</b>以外；亦強調在More than Moore上
的應用價值，比如<b>嵌入式記憶體(embedded memory)</b>和<b>類神經網路計算(Neuromorphic Computing)</b>...等等。除了固有的半導體物理，固態物理，和量子力學必須了解之外，本實驗室更強調活用這些機制在半導體上實現各式各樣之創新應用，為台灣與世界奉獻一己之力，歡迎加入我們的行列。<br>
</p>
<img style='width:55%;margin:3.5% 0 0 10%;'src="images/topic.png">
<div style='float:right;width:33%;'>
<div style='color:#37a537;padding:10% 0 0 0;'>
<div>1. Embedded Memory<a href='#RRAM'class='link1'>......read more</a></div><br><br>
<div>2. Neuromorphic Computing<a class='link1'>......read more</a></div>
</div>
</div>
<div style='color:#4a7ebb;margin:1% 0 0 8.6%;line-height:25px;'>
<div style='font-size:16px;'>
1. FinFETs<a href='#FinFet'class='link2'>......read more</a>
</div>
<div>2. Naonowire</div>
<div>
3. TFETs<a href='#TFET' class='link2'>......read more</a>
</div>
<div style='font-size:16px;'>4. NC-FETs</div>
</div>
<li><a name='FinFet'></a>
<div id='main'>
<button class="but"style='border-top-left-radius:4px;border-bottom-left-radius:4px;color:yellow;'>FinFet</button>
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<button class="but" onclick='myclick(3)'style='border-top-right-radius:4px;border-bottom-right-radius:4px;'>eNVM</button>
</div>
<div class='title'>Frabrication and Design of New Generation Nano CMOS Devices FinFET Structure</div>
<div class="pic">
<img class='show'src="images/finfet.gif">
</div>
<div class='article'>
<p>
<ul>
<li>FinFET new structures are applied in the design of various format of System on Chip</li>
<li>do the analysis of the simulation of the latest devices and process and modelize it</li>
<li>Analysis of thermal electronic and the researches of physical mechanism</li>
<li>the researches of Self-heating thermal resistance</li>
<li>the researches of CMOS devices with high-K oxide layer </li>
</ul>
</p>
</div>
<li>
<a name='TFET'></a>
<div id='main'>
<button class="but"style='border-top-left-radius:4px;border-bottom-left-radius:4px;' onclick='myclick(0)'>FinFet</button>
<button class="but" style='color:yellow;'>TFET</button>
<button class="but" onclick='myclick(2)'>RRAM</button>
<button class="but" onclick='myclick(3)'style='border-top-right-radius:4px;border-bottom-right-radius:4px;'>eNVM</button>
</div>
<div class='title'>Simulation and Process of Low Power Tunneling Transistors Structure (Tunneling FET)</div>
<div class="pic">
<img class='show' src="https://dsmlnctu.files.wordpress.com/2015/06/tfet.png">
</div>
<div class='article'>
<p>
<ul>
<li>Change the electrical mechanism of traditional FET and break through the slope of traditional subcritical value (lower than 60mV/dec)
<li>Have lower leakage current and also can be applied in low power system. Our team continuously developes new tunneling structures and improves various performance
<li>Potential Structure
</ul>
</p>
</div>
<li>
<a name='RRAM'></a>
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<button class="but" onclick='myclick(3)'style='border-top-right-radius:4px;border-bottom-right-radius:4px;'>eNVM</button>
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<div class='title'>Reliability and Process of New Generation Resistive Random Access Memory</div>
<div class="pic">
<img class='show'src="https://dsmlnctu.files.wordpress.com/2015/06/rram.png">
</div>
<div class='article'>
<p>
<ul>
<li>Simple structure. Be expected that replace of high density flash memory
<li>Recently, the operating mechanism of RRAM are researching.
<li>Our team analyzes the operating mechanism of RRAM with RTN technique
<li>Potential Structure
</ul>
</p>
</div>
<li>
<a name='eNVM'></a>
<div id='main'>
<button class="but"style='border-top-left-radius:4px;border-bottom-left-radius:4px;' onclick='myclick(0)'>FinFet</button>
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<button class="but" onclick='myclick(2)'>RRAM</button>
<button class="but" style='color:yellow;border-top-right-radius:4px;border-bottom-right-radius:4px;'>eNVM</button>
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<div class='title'>Write Once Memory Design of Fuse Breakdown Mechanism of Dielectric Layer and Reliable Analysis of Device Array</div>
<div class="pic">
<img class='show'src="https://dsmlnctu.files.wordpress.com/2015/06/otp.png">
</div>
<div class='article'>
<div style='float:left;width:48%;line-height:30px;padding:0 15px 10px 10px;font-size:20px;'>
<h3>Fuse</h3>
select transistor + 1 resistor<br>
<b>Write</b>：electons migrated by large current<br>
<b>Advantages</b>：smaller size and larger current density<br>
<b>Disadvantages</b>：need high current and waste energy
</div>
<div style='float:left;width:48%;line-height:30px;padding:0 0 10px;font-size:20px;'>
<h3>Anti-Fuse</h3>
select transistor + 1 storage transistor<br>
<b>Write</b>：break through dielectric layer with large voltage between Gate and tunnel<br>
<b>Advantages</b>：do not need additional mask<br>
<b>Disadvantages</b>：need high voltage and waste energy
</div>
</div>
</ul>
</div>
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<p>
<img src='images/IEEE.jpg'style='height:15px;margin:0 4px 0 0;'>
<a href='https://www.facebook.com/edsNCTUXNTHU/'target="_blank">IEEE Electron Device Society Taipei section 清交學生分會</a>
</p>
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