From d202b34b6411ea170904ebe9259e0b9f164566df Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Fri, 7 Feb 2025 14:14:17 -0800 Subject: [PATCH 1/2] update the location of assert for REG_ZR check --- src/coreclr/jit/emitarm64.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index 10d344b22c02fa..a040aa4ac1810b 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -5860,11 +5860,11 @@ void emitter::emitIns_R_R_I(instruction ins, else { assert(isGeneralRegisterOrSP(reg1)); - assert(isGeneralRegisterOrSP(reg2)); // Is it just a mov? if (imm == 0) { + assert(isGeneralRegisterOrSP(reg2)); emitIns_Mov(INS_mov, attr, reg1, reg2, /* canSkip */ true); return; } @@ -5875,6 +5875,9 @@ void emitter::emitIns_R_R_I(instruction ins, return; } + // reg2 can be alread encoded to zero + assert(isGeneralRegisterOrSP(reg2) || (reg2 == REG_ZR)); + reg1 = encodingSPtoZR(reg1); reg2 = encodingSPtoZR(reg2); } From 393ed4165612a2c677e68ad163e9c147db536d86 Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Fri, 7 Feb 2025 16:58:31 -0800 Subject: [PATCH 2/2] encodeZRtoSP() in caller --- src/coreclr/jit/emitarm64.cpp | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index a040aa4ac1810b..d0dbc6367be2fe 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -5860,11 +5860,11 @@ void emitter::emitIns_R_R_I(instruction ins, else { assert(isGeneralRegisterOrSP(reg1)); + assert(isGeneralRegisterOrSP(reg2)); // Is it just a mov? if (imm == 0) { - assert(isGeneralRegisterOrSP(reg2)); emitIns_Mov(INS_mov, attr, reg1, reg2, /* canSkip */ true); return; } @@ -5875,9 +5875,6 @@ void emitter::emitIns_R_R_I(instruction ins, return; } - // reg2 can be alread encoded to zero - assert(isGeneralRegisterOrSP(reg2) || (reg2 == REG_ZR)); - reg1 = encodingSPtoZR(reg1); reg2 = encodingSPtoZR(reg2); } @@ -8015,7 +8012,7 @@ void emitter::emitIns_R_S(instruction ins, emitAttr attr, regNumber reg1, int va regNumber rsvdReg = codeGen->rsGetRsvdReg(); // add rsvd, fp, #imm - emitIns_R_R_Imm(INS_add, EA_8BYTE, rsvdReg, reg2, imm); + emitIns_R_R_Imm(INS_add, EA_8BYTE, rsvdReg, encodingZRtoSP(reg2), imm); // str p0, [rsvd, #0, mul vl] emitIns_R_R_I(ins, attr, reg1, rsvdReg, 0); @@ -8288,7 +8285,7 @@ void emitter::emitIns_S_R(instruction ins, emitAttr attr, regNumber reg1, int va regNumber rsvdReg = codeGen->rsGetRsvdReg(); // add rsvd, fp, #imm - emitIns_R_R_Imm(INS_add, EA_8BYTE, rsvdReg, reg2, imm); + emitIns_R_R_Imm(INS_add, EA_8BYTE, rsvdReg, encodingZRtoSP(reg2), imm); // str p0, [rsvd, #0, mul vl] emitIns_R_R_I(ins, attr, reg1, rsvdReg, 0);