From 5cf9e2acc08b407a09209b7ec86531b5b8534ece Mon Sep 17 00:00:00 2001 From: Andy Ayers Date: Thu, 15 Aug 2024 15:24:56 -0700 Subject: [PATCH] JIT: update simd base type when combining simd nodes for bitwise ops If we merge two simd for bitwise ops (eg creating an AndNot), make sure to use the simd base type of the parent (And) node when specializing the operator. Fixes #106478. --- src/coreclr/jit/lowerxarch.cpp | 11 +++++--- .../JitBlue/Runtime_106478/Runtime_106478.cs | 28 +++++++++++++++++++ .../Runtime_106478/Runtime_106478.csproj | 8 ++++++ 3 files changed, 43 insertions(+), 4 deletions(-) create mode 100644 src/tests/JIT/Regression/JitBlue/Runtime_106478/Runtime_106478.cs create mode 100644 src/tests/JIT/Regression/JitBlue/Runtime_106478/Runtime_106478.csproj diff --git a/src/coreclr/jit/lowerxarch.cpp b/src/coreclr/jit/lowerxarch.cpp index fb8d63e5aaca27..0a1c884f3848cd 100644 --- a/src/coreclr/jit/lowerxarch.cpp +++ b/src/coreclr/jit/lowerxarch.cpp @@ -1430,10 +1430,9 @@ GenTree* Lowering::LowerHWIntrinsic(GenTreeHWIntrinsic* node) const uint8_t B = 0xCC; const uint8_t C = 0xAA; - var_types simdType = node->TypeGet(); - CorInfoType simdBaseJitType = node->GetSimdBaseJitType(); - var_types simdBaseType = node->GetSimdBaseType(); - unsigned simdSize = node->GetSimdSize(); + var_types simdType = node->TypeGet(); + var_types simdBaseType = node->GetSimdBaseType(); + unsigned simdSize = node->GetSimdSize(); GenTree* op1 = node->Op(1); GenTree* op2 = node->Op(2); @@ -1455,6 +1454,10 @@ GenTree* Lowering::LowerHWIntrinsic(GenTreeHWIntrinsic* node) bool userIsScalar = false; genTreeOps userOper = userIntrin->GetOperForHWIntrinsicId(&isScalar); + // userIntrin may have re-interpreted the base type + // + simdBaseType = userIntrin->GetSimdBaseType(); + if (GenTreeHWIntrinsic::OperIsBitwiseHWIntrinsic(userOper)) { if (isOperNot && (userOper == GT_AND)) diff --git a/src/tests/JIT/Regression/JitBlue/Runtime_106478/Runtime_106478.cs b/src/tests/JIT/Regression/JitBlue/Runtime_106478/Runtime_106478.cs new file mode 100644 index 00000000000000..7afa86b76c0606 --- /dev/null +++ b/src/tests/JIT/Regression/JitBlue/Runtime_106478/Runtime_106478.cs @@ -0,0 +1,28 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +// Found by Antigen +// Reduced from 30.05 KB to 2.35 KB. +// Further redued by hand + +using System; +using System.Runtime.Intrinsics; +using Xunit; + +public class Runtime_106478 +{ + static Vector512 s_v512_double_46 = Vector512.Create(4, -4.971830985915493, -0.9789473684210527, -1.956043956043956, 2, 74.25, 1.0533333333333332, 4.033898305084746); + Vector512 v512_int_101 = Vector512.Zero; + Vector512 p_v512_int_125 = Vector512.Zero; + + void Problem() + { + p_v512_int_125 = v512_int_101& Vector512.AsInt32(s_v512_double_46 ^ Vector512.AllBitsSet); + } + + [Fact] + public static void Test() + { + new Runtime_106478().Problem(); + } +} diff --git a/src/tests/JIT/Regression/JitBlue/Runtime_106478/Runtime_106478.csproj b/src/tests/JIT/Regression/JitBlue/Runtime_106478/Runtime_106478.csproj new file mode 100644 index 00000000000000..de6d5e08882e86 --- /dev/null +++ b/src/tests/JIT/Regression/JitBlue/Runtime_106478/Runtime_106478.csproj @@ -0,0 +1,8 @@ + + + True + + + + +