From 7f2b5ae6947aa3991418f967dca4480555555e29 Mon Sep 17 00:00:00 2001 From: Khushal Modi Date: Wed, 8 Jan 2025 11:37:05 -0800 Subject: [PATCH] fix formatting --- src/coreclr/jit/codegenxarch.cpp | 49 ++++++++++++++++---------------- src/coreclr/jit/emitxarch.cpp | 2 +- 2 files changed, 25 insertions(+), 26 deletions(-) diff --git a/src/coreclr/jit/codegenxarch.cpp b/src/coreclr/jit/codegenxarch.cpp index efe4b0a7e9d425..63b5d4a030e254 100644 --- a/src/coreclr/jit/codegenxarch.cpp +++ b/src/coreclr/jit/codegenxarch.cpp @@ -9288,24 +9288,24 @@ void CodeGen::genAmd64EmitterUnitTestsAvx10v2() return; } - //packed conversion instructions - theEmitter->emitIns_R_R(INS_vcvttps2dqs, EA_4BYTE, REG_XMM0, REG_XMM1); // xmm - theEmitter->emitIns_R_R(INS_vcvttps2dqs, EA_32BYTE, REG_XMM0, REG_XMM1);// ymm - theEmitter->emitIns_R_R(INS_vcvttps2dqs, EA_64BYTE, REG_XMM0, REG_XMM1);// zmm + // packed conversion instructions + theEmitter->emitIns_R_R(INS_vcvttps2dqs, EA_4BYTE, REG_XMM0, REG_XMM1); // xmm + theEmitter->emitIns_R_R(INS_vcvttps2dqs, EA_32BYTE, REG_XMM0, REG_XMM1); // ymm + theEmitter->emitIns_R_R(INS_vcvttps2dqs, EA_64BYTE, REG_XMM0, REG_XMM1); // zmm - theEmitter->emitIns_R_R(INS_vcvttps2udqs, EA_4BYTE, REG_XMM0, REG_XMM1);// xmm - theEmitter->emitIns_R_R(INS_vcvttps2udqs, EA_32BYTE, REG_XMM0, REG_XMM1);// ymm - theEmitter->emitIns_R_R(INS_vcvttps2udqs, EA_64BYTE, REG_XMM0, REG_XMM1);// zmm + theEmitter->emitIns_R_R(INS_vcvttps2udqs, EA_4BYTE, REG_XMM0, REG_XMM1); // xmm + theEmitter->emitIns_R_R(INS_vcvttps2udqs, EA_32BYTE, REG_XMM0, REG_XMM1); // ymm + theEmitter->emitIns_R_R(INS_vcvttps2udqs, EA_64BYTE, REG_XMM0, REG_XMM1); // zmm - theEmitter->emitIns_R_R(INS_vcvttpd2qqs, EA_8BYTE, REG_XMM0, REG_XMM1);// xmm - theEmitter->emitIns_R_R(INS_vcvttpd2qqs, EA_32BYTE, REG_XMM0, REG_XMM1);// ymm - theEmitter->emitIns_R_R(INS_vcvttpd2qqs, EA_64BYTE, REG_XMM0, REG_XMM1);// zmm + theEmitter->emitIns_R_R(INS_vcvttpd2qqs, EA_8BYTE, REG_XMM0, REG_XMM1); // xmm + theEmitter->emitIns_R_R(INS_vcvttpd2qqs, EA_32BYTE, REG_XMM0, REG_XMM1); // ymm + theEmitter->emitIns_R_R(INS_vcvttpd2qqs, EA_64BYTE, REG_XMM0, REG_XMM1); // zmm - theEmitter->emitIns_R_R(INS_vcvttpd2uqqs, EA_8BYTE, REG_XMM0, REG_XMM1);// xmm - theEmitter->emitIns_R_R(INS_vcvttpd2uqqs, EA_32BYTE, REG_XMM0, REG_XMM1);// ymm - theEmitter->emitIns_R_R(INS_vcvttpd2uqqs, EA_64BYTE, REG_XMM0, REG_XMM1);// zmm + theEmitter->emitIns_R_R(INS_vcvttpd2uqqs, EA_8BYTE, REG_XMM0, REG_XMM1); // xmm + theEmitter->emitIns_R_R(INS_vcvttpd2uqqs, EA_32BYTE, REG_XMM0, REG_XMM1); // ymm + theEmitter->emitIns_R_R(INS_vcvttpd2uqqs, EA_64BYTE, REG_XMM0, REG_XMM1); // zmm - //scalar conversion instructions + // scalar conversion instructions theEmitter->emitIns_R_R(INS_vcvttsd2sis32, EA_8BYTE, REG_XMM0, REG_XMM1); theEmitter->emitIns_R_R(INS_vcvttsd2sis64, EA_8BYTE, REG_XMM0, REG_XMM1); theEmitter->emitIns_R_R(INS_vcvttsd2usis32, EA_8BYTE, REG_XMM0, REG_XMM1); @@ -9315,16 +9315,15 @@ void CodeGen::genAmd64EmitterUnitTestsAvx10v2() theEmitter->emitIns_R_R(INS_vcvttss2usis32, EA_4BYTE, REG_XMM0, REG_XMM1); theEmitter->emitIns_R_R(INS_vcvttss2usis64, EA_4BYTE, REG_XMM0, REG_XMM1); + // minmax instruction + theEmitter->emitIns_R_R_R_I(INS_vminmaxss, EA_16BYTE, REG_XMM0, REG_XMM1, REG_XMM2, 0); + theEmitter->emitIns_R_R_R_I(INS_vminmaxsd, EA_16BYTE, REG_XMM0, REG_XMM1, REG_XMM2, 0); + theEmitter->emitIns_R_R_R_I(INS_vminmaxps, EA_32BYTE, REG_XMM0, REG_XMM1, REG_XMM2, 0); + theEmitter->emitIns_R_R_R_I(INS_vminmaxpd, EA_32BYTE, REG_XMM0, REG_XMM1, REG_XMM2, 0); + theEmitter->emitIns_R_R_R_I(INS_vminmaxps, EA_64BYTE, REG_XMM0, REG_XMM1, REG_XMM2, 0); + theEmitter->emitIns_R_R_R_I(INS_vminmaxpd, EA_64BYTE, REG_XMM0, REG_XMM1, REG_XMM2, 0); - //minmax instruction - theEmitter->emitIns_R_R_R_I(INS_vminmaxss, EA_16BYTE, REG_XMM0, REG_XMM1, REG_XMM2,0); - theEmitter->emitIns_R_R_R_I(INS_vminmaxsd, EA_16BYTE, REG_XMM0, REG_XMM1, REG_XMM2,0); - theEmitter->emitIns_R_R_R_I(INS_vminmaxps, EA_32BYTE, REG_XMM0, REG_XMM1, REG_XMM2,0); - theEmitter->emitIns_R_R_R_I(INS_vminmaxpd, EA_32BYTE, REG_XMM0, REG_XMM1, REG_XMM2,0); - theEmitter->emitIns_R_R_R_I(INS_vminmaxps, EA_64BYTE, REG_XMM0, REG_XMM1, REG_XMM2,0); - theEmitter->emitIns_R_R_R_I(INS_vminmaxpd, EA_64BYTE, REG_XMM0, REG_XMM1, REG_XMM2,0); - - //VCVT[,T]PS2I[,U]BS + // VCVT[,T]PS2I[,U]BS theEmitter->emitIns_R_R(INS_vcvtps2ibs, EA_16BYTE, REG_XMM0, REG_XMM1); theEmitter->emitIns_R_R(INS_vcvtps2ibs, EA_32BYTE, REG_XMM0, REG_XMM1); theEmitter->emitIns_R_R(INS_vcvtps2ibs, EA_32BYTE, REG_XMM0, REG_XMM1, INS_OPTS_EVEX_er_ru); @@ -9344,7 +9343,7 @@ void CodeGen::genAmd64EmitterUnitTestsAvx10v2() theEmitter->emitIns_R_R(INS_vcvttps2iubs, EA_32BYTE, REG_XMM0, REG_XMM1, INS_OPTS_EVEX_er_ru); theEmitter->emitIns_R_R(INS_vcvttps2iubs, EA_64BYTE, REG_XMM0, REG_XMM1); - //VPDPW[SU,US,UU]D[,S] + // VPDPW[SU,US,UU]D[,S] theEmitter->emitIns_R_R_R(INS_vpdpwsud, EA_16BYTE, REG_XMM0, REG_XMM1, REG_XMM2); theEmitter->emitIns_R_R_R(INS_vpdpwsud, EA_32BYTE, REG_XMM0, REG_XMM1, REG_XMM2); theEmitter->emitIns_R_R_R(INS_vpdpwsud, EA_64BYTE, REG_XMM0, REG_XMM1, REG_XMM2); @@ -9389,7 +9388,7 @@ void CodeGen::genAmd64EmitterUnitTestsAvx10v2() theEmitter->emitIns_R_R_R(INS_vpdpbuuds, EA_64BYTE, REG_XMM0, REG_XMM1, REG_XMM2); // VMPSADBW - theEmitter->emitIns_R_R_R_I(INS_vmpsadbw, EA_64BYTE, REG_XMM0, REG_XMM1, REG_XMM2, 0);// zmm + theEmitter->emitIns_R_R_R_I(INS_vmpsadbw, EA_64BYTE, REG_XMM0, REG_XMM1, REG_XMM2, 0); // zmm // VCOMXSD theEmitter->emitIns_R_R(INS_vcomxsd, EA_16BYTE, REG_XMM0, REG_XMM1); diff --git a/src/coreclr/jit/emitxarch.cpp b/src/coreclr/jit/emitxarch.cpp index 0dac1d570c0362..0b18977cfc4109 100644 --- a/src/coreclr/jit/emitxarch.cpp +++ b/src/coreclr/jit/emitxarch.cpp @@ -1494,7 +1494,7 @@ emitter::code_t emitter::AddEvexPrefix(const instrDesc* id, code_t code, emitAtt assert(emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2)); code &= ~(uBIT_IN_BYTE_EVEX_PREFIX); } - + unsigned roundingMode = id->idGetEvexbContext(); if (roundingMode == 1) {