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rsp_recompiler_analysis.c
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/*
* RSP Compiler plug in for Project 64 (A Nintendo 64 emulator).
*
* (c) Copyright 2001 jabo (jabo@emulation64.com) and
* zilmar (zilmar@emulation64.com)
*
* pj64 homepage: www.pj64.net
*
* Permission to use, copy, modify and distribute Project64 in both binary and
* source form, for non-commercial purposes, is hereby granted without fee,
* providing that this license information and copyright notice appear with
* all copies and any derived work.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event shall the authors be held liable for any damages
* arising from the use of this software.
*
* Project64 is freeware for PERSONAL USE only. Commercial users should
* seek permission of the copyright holders first. Commercial use includes
* charging money for Project64 or software derived from Project64.
*
* The copyright holders request that bug fixes and improvements to the code
* should be forwarded to them so if they want them.
*
*/
#include <string.h>
#include "rsp.h"
#include "rsp_recompiler_cpu.h"
#define RSP_SAFE_ANALYSIS /* makes optimization less risky (dlist useful) */
/************************************************************
** IsOpcodeNop
**
** Output: BOOLean whether opcode at PC is a NOP
** Input: PC
*************************************************************/
int32_t IsOpcodeNop(uint32_t PC)
{
RSPOPCODE RspOp;
RSP_LW_IMEM(PC, &RspOp.Hex);
if (RspOp.op == RSP_SPECIAL && RspOp.funct == RSP_SPECIAL_SLL)
{
return (RspOp.rd == 0) ? 1 : 0;
}
return 0;
}
/************************************************************
** IsNextInstructionMmx
**
** Output: determines EMMS status
** Input: PC
*************************************************************/
int32_t IsNextInstructionMmx(uint32_t PC)
{
RSPOPCODE RspOp;
if (IsMmxEnabled == 0)
{
return 0;
}
PC += 4;
if (PC >= 0x1000)
{
return 0;
}
RSP_LW_IMEM(PC, &RspOp.Hex);
if (RspOp.op != RSP_CP2)
{
return 0;
}
if ((RspOp.rs & 0x10) != 0)
{
switch (RspOp.funct)
{
case RSP_VECTOR_VMULF:
case RSP_VECTOR_VMUDL: /* Warning: Not all handled? */
case RSP_VECTOR_VMUDM:
case RSP_VECTOR_VMUDN:
case RSP_VECTOR_VMUDH:
if (1 == WriteToAccum(7, PC))
{
return 0;
}
else if ((RspOp.rs & 0x0f) >= 2 && (RspOp.rs & 0x0f) <= 7 && IsMmx2Enabled == 0)
{
return 0;
}
else
{
return 1;
}
case RSP_VECTOR_VAND:
case RSP_VECTOR_VOR:
case RSP_VECTOR_VXOR:
if (1 == WriteToAccum(Low16BitAccum, PC))
{
return 0;
}
else if ((RspOp.rs & 0x0f) >= 2 && (RspOp.rs & 0x0f) <= 7 && IsMmx2Enabled == 0)
{
return 0;
}
else
{
return 1;
}
case RSP_VECTOR_VADD:
/* Requires no accumulator write! & No flags! */
if (WriteToAccum(Low16BitAccum, RSPCompilePC) == 1)
{
return 0;
}
else if (UseRspFlags(RSPCompilePC) == 1)
{
return 0;
}
else if ((RspOp.rs & 0x0f) >= 2 && (RspOp.rs & 0x0f) <= 7 && IsMmx2Enabled == 0)
{
return 0;
}
else
{
return 1;
}
default:
return 0;
}
}
else
{
return 0;
}
}
/************************************************************
** WriteToAccum2
**
** Output:
** 1: Accumulation series
** 0: Accumulator is reset after this op
**
** Input: PC, Location in accumulator
*************************************************************/
#define HIT_BRANCH 0x2
uint32_t WriteToAccum2 (int32_t Location, int32_t PC, int32_t RecursiveCall)
{
RSPOPCODE RspOp;
uint32_t BranchTarget = 0;
int32_t BranchImmed = 0;
uint32_t JumpTarget = 0;
int32_t JumpUncond = 0;
int32_t Instruction_State = RSPNextInstruction;
if (Compiler.bAccum == 0)
{
return 1;
}
if (Instruction_State == DELAY_SLOT)
{
return 1;
}
do
{
PC += 4;
if (PC >= 0x1000)
{
return 1;
}
RSP_LW_IMEM(PC, &RspOp.Hex);
switch (RspOp.op)
{
case RSP_REGIMM:
switch (RspOp.rt)
{
case RSP_REGIMM_BLTZ:
case RSP_REGIMM_BGEZ:
case RSP_REGIMM_BLTZAL:
case RSP_REGIMM_BGEZAL:
Instruction_State = DO_DELAY_SLOT;
break;
default:
CompilerWarning("Unkown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
return 1;
}
break;
case RSP_SPECIAL:
switch (RspOp.funct)
{
case RSP_SPECIAL_SLL:
case RSP_SPECIAL_SRL:
case RSP_SPECIAL_SRA:
case RSP_SPECIAL_SLLV:
case RSP_SPECIAL_SRLV:
case RSP_SPECIAL_SRAV:
case RSP_SPECIAL_ADD:
case RSP_SPECIAL_ADDU:
case RSP_SPECIAL_SUB:
case RSP_SPECIAL_SUBU:
case RSP_SPECIAL_AND:
case RSP_SPECIAL_OR:
case RSP_SPECIAL_XOR:
case RSP_SPECIAL_NOR:
case RSP_SPECIAL_SLT:
case RSP_SPECIAL_SLTU:
case RSP_SPECIAL_BREAK:
break;
case RSP_SPECIAL_JR:
Instruction_State = DO_DELAY_SLOT;
break;
default:
CompilerWarning("Unkown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
return 1;
}
break;
case RSP_J:
case RSP_JAL:
if (!JumpTarget)
{
JumpUncond = 1;
JumpTarget = (RspOp.target << 2) & 0xFFC;
}
Instruction_State = DO_DELAY_SLOT;
break;
case RSP_BEQ:
case RSP_BNE:
case RSP_BLEZ:
case RSP_BGTZ:
Instruction_State = DO_DELAY_SLOT;
BranchTarget = (PC + ((int16_t)RspOp.offset << 2) + 4) & 0xFFC;
BranchImmed = (int16_t)RspOp.offset;
break;
case RSP_ADDI:
case RSP_ADDIU:
case RSP_SLTI:
case RSP_SLTIU:
case RSP_ANDI:
case RSP_ORI:
case RSP_XORI:
case RSP_LUI:
case RSP_CP0:
break;
case RSP_CP2:
if ((RspOp.rs & 0x10) != 0)
{
switch (RspOp.funct)
{
case RSP_VECTOR_VMULF:
case RSP_VECTOR_VMUDL:
case RSP_VECTOR_VMUDM:
case RSP_VECTOR_VMUDN:
case RSP_VECTOR_VMUDH:
return 0;
case RSP_VECTOR_VMACF:
case RSP_VECTOR_VMADL:
case RSP_VECTOR_VMADM:
case RSP_VECTOR_VMADN:
case RSP_VECTOR_VMADH:
return 1;
case RSP_VECTOR_VABS: // hope this is ok
case RSP_VECTOR_VADD:
case RSP_VECTOR_VADDC:
case RSP_VECTOR_VSUB:
case RSP_VECTOR_VSUBC:
case RSP_VECTOR_VAND:
case RSP_VECTOR_VOR:
case RSP_VECTOR_VXOR:
case RSP_VECTOR_VNXOR:
case RSP_VECTOR_VCR:
case RSP_VECTOR_VCH:
case RSP_VECTOR_VCL:
case RSP_VECTOR_VRCP:
case RSP_VECTOR_VRCPL: // hope this is ok
case RSP_VECTOR_VRCPH:
case RSP_VECTOR_VRSQL:
case RSP_VECTOR_VRSQH: // hope this is ok
case RSP_VECTOR_VLT:
case RSP_VECTOR_VEQ:
case RSP_VECTOR_VGE:
if (Location == Low16BitAccum)
{
return 0;
}
break;
case RSP_VECTOR_VMOV:
case RSP_VECTOR_VMRG:
break;
case RSP_VECTOR_VSAW:
return 1;
default:
CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
return 1;
}
}
else
{
switch (RspOp.rs)
{
case RSP_COP2_CF:
case RSP_COP2_CT:
case RSP_COP2_MT:
case RSP_COP2_MF:
break;
default:
CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
return 1;
}
}
break;
case RSP_LB:
case RSP_LH:
case RSP_LW:
case RSP_LBU:
case RSP_LHU:
case RSP_SB:
case RSP_SH:
case RSP_SW:
break;
case RSP_LC2:
switch (RspOp.rd)
{
case RSP_LSC2_SV:
case RSP_LSC2_DV:
case RSP_LSC2_RV:
case RSP_LSC2_QV:
case RSP_LSC2_LV:
case RSP_LSC2_UV:
case RSP_LSC2_PV:
case RSP_LSC2_TV:
break;
default:
CompilerWarning("Unkown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
return 1;
}
break;
case RSP_SC2:
switch (RspOp.rd)
{
case RSP_LSC2_BV:
case RSP_LSC2_SV:
case RSP_LSC2_LV:
case RSP_LSC2_DV:
case RSP_LSC2_QV:
case RSP_LSC2_RV:
case RSP_LSC2_PV:
case RSP_LSC2_UV:
case RSP_LSC2_HV:
case RSP_LSC2_FV:
case RSP_LSC2_WV:
case RSP_LSC2_TV:
break;
default:
CompilerWarning("Unkown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
return 1;
}
break;
default:
CompilerWarning("Unkown opcode in WriteToAccum\n%s",RSPOpcodeName(RspOp.Hex,PC));
return 1;
}
switch (Instruction_State)
{
case NORMAL:
break;
case DO_DELAY_SLOT:
Instruction_State = DELAY_SLOT;
break;
case DELAY_SLOT:
if (JumpUncond)
{
PC = JumpTarget - 0x04;
Instruction_State = NORMAL;
}
else
{
Instruction_State = FINISH_BLOCK;
}
JumpUncond = 0;
break;
}
}
while (Instruction_State != FINISH_BLOCK);
/***
** This is a tricky situation because most of the
** microcode does loops, so looping back and checking
** can prove effective, but it's still a branch..
***/
if (BranchTarget != 0 && RecursiveCall == 0)
{
uint32_t BranchTaken, BranchFall;
/* analysis of branch taken */
BranchTaken = WriteToAccum2(Location, BranchTarget - 4, 1);
/* analysis of branch as nop */
BranchFall = WriteToAccum2(Location, PC, 1);
if (BranchImmed < 0)
{
if (BranchTaken != 0)
{
/*
** took this back branch and couldnt find a place
** that resets the accum or hit a branch etc
**/
return 1;
}
else if (BranchFall == HIT_BRANCH)
{
/* risky? the loop ended, hit another branch after loop-back */
#if !defined(RSP_SAFE_ANALYSIS)
CPU_Message("WriteToDest: Backward branch hit, BranchFall = Hit branch (returning 0)");
return 0;
#endif
return 1;
}
else
{
/* otherwise this is completely valid */
return BranchFall;
}
}
else
{
if (BranchFall != 0)
{
/*
** took this forward branch and couldnt find a place
** that resets the accum or hit a branch etc
**/
return 1;
}
else if (BranchTaken == HIT_BRANCH)
{
/* risky? jumped forward, hit another branch */
#if !defined(RSP_SAFE_ANALYSIS)
CPU_Message("WriteToDest: Forward branch hit, BranchTaken = Hit branch (returning 0)");
return 0;
#endif
return 1;
}
else
{
/* otherwise this is completely valid */
return BranchTaken;
}
}
}
else
{
return HIT_BRANCH;
}
}
int32_t WriteToAccum (int32_t Location, int32_t PC)
{
uint32_t value = WriteToAccum2(Location, PC, 0);
if (value == HIT_BRANCH)
{
return 1; /* ??? */
}
else
{
return value;
}
}
/************************************************************
** WriteToVectorDest
**
** Output:
** 1: Destination is over-written later
** 0: Destination is used as a source later
**
** Input: PC, Register
*************************************************************/
int32_t WriteToVectorDest2 (uint32_t DestReg, int32_t PC, int32_t RecursiveCall)
{
RSPOPCODE RspOp;
uint32_t BranchTarget = 0;
int32_t BranchImmed = 0;
uint32_t JumpTarget = 0;
int32_t JumpUncond = 0;
int32_t Instruction_State = RSPNextInstruction;
if (Compiler.bDest == 0)
{
return 1;
}
if (Instruction_State == DELAY_SLOT)
{
return 1;
}
do
{
PC += 4;
if (PC >= 0x1000)
{
return 1;
}
RSP_LW_IMEM(PC, &RspOp.Hex);
switch (RspOp.op)
{
case RSP_REGIMM:
switch (RspOp.rt)
{
case RSP_REGIMM_BLTZ:
case RSP_REGIMM_BGEZ:
case RSP_REGIMM_BLTZAL:
case RSP_REGIMM_BGEZAL:
Instruction_State = DO_DELAY_SLOT;
break;
default:
CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
return 1;
}
break;
case RSP_SPECIAL:
switch (RspOp.funct)
{
case RSP_SPECIAL_SLL:
case RSP_SPECIAL_SRL:
case RSP_SPECIAL_SRA:
case RSP_SPECIAL_SLLV:
case RSP_SPECIAL_SRLV:
case RSP_SPECIAL_SRAV:
case RSP_SPECIAL_ADD:
case RSP_SPECIAL_ADDU:
case RSP_SPECIAL_SUB:
case RSP_SPECIAL_SUBU:
case RSP_SPECIAL_AND:
case RSP_SPECIAL_OR:
case RSP_SPECIAL_XOR:
case RSP_SPECIAL_NOR:
case RSP_SPECIAL_SLT:
case RSP_SPECIAL_SLTU:
case RSP_SPECIAL_BREAK:
break;
case RSP_SPECIAL_JR:
Instruction_State = DO_DELAY_SLOT;
break;
default:
CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
return 1;
}
break;
case RSP_J:
case RSP_JAL:
if (!JumpTarget)
{
JumpUncond = 1;
JumpTarget = (RspOp.target << 2) & 0xFFC;
}
Instruction_State = DO_DELAY_SLOT;
break;
case RSP_BEQ:
case RSP_BNE:
case RSP_BLEZ:
case RSP_BGTZ:
Instruction_State = DO_DELAY_SLOT;
BranchTarget = (PC + ((int16_t)RspOp.offset << 2) + 4) & 0xFFC;
BranchImmed = (int16_t)RspOp.offset;
break;
case RSP_ADDI:
case RSP_ADDIU:
case RSP_SLTI:
case RSP_SLTIU:
case RSP_ANDI:
case RSP_ORI:
case RSP_XORI:
case RSP_LUI:
case RSP_CP0:
break;
case RSP_CP2:
if ((RspOp.rs & 0x10) != 0)
{
switch (RspOp.funct)
{
case RSP_VECTOR_VMULF:
case RSP_VECTOR_VMUDL:
case RSP_VECTOR_VMUDM:
case RSP_VECTOR_VMUDN:
case RSP_VECTOR_VMUDH:
case RSP_VECTOR_VMACF:
case RSP_VECTOR_VMADL:
case RSP_VECTOR_VMADM:
case RSP_VECTOR_VMADN:
case RSP_VECTOR_VMADH:
case RSP_VECTOR_VADD:
case RSP_VECTOR_VADDC:
case RSP_VECTOR_VSUB:
case RSP_VECTOR_VSUBC:
case RSP_VECTOR_VAND:
case RSP_VECTOR_VOR:
case RSP_VECTOR_VXOR:
case RSP_VECTOR_VNXOR:
case RSP_VECTOR_VABS:
if (DestReg == RspOp.rd)
{
return 1;
}
if (DestReg == RspOp.rt)
{
return 1;
}
if (DestReg == RspOp.sa)
{
return 0;
}
break;
case RSP_VECTOR_VMOV:
if (DestReg == RspOp.rt)
{
return 1;
}
break;
case RSP_VECTOR_VCR:
case RSP_VECTOR_VRCP:
case RSP_VECTOR_VRCPH:
case RSP_VECTOR_VRSQH:
case RSP_VECTOR_VCH:
case RSP_VECTOR_VCL:
return 1;
case RSP_VECTOR_VMRG:
case RSP_VECTOR_VLT:
case RSP_VECTOR_VEQ:
case RSP_VECTOR_VGE:
if (DestReg == RspOp.rd)
{
return 1;
}
if (DestReg == RspOp.rt)
{
return 1;
}
if (DestReg == RspOp.sa)
{
return 0;
}
break;
case RSP_VECTOR_VSAW:
if (DestReg == RspOp.sa)
{
return 0;
}
break;
default:
CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
return 1;
}
}
else
{
switch (RspOp.rs)
{
case RSP_COP2_CF:
case RSP_COP2_CT:
break;
case RSP_COP2_MT:
/* if (DestReg == RspOp.rd) { return 0; } */
break;
case RSP_COP2_MF:
if (DestReg == RspOp.rd)
{
return 1;
}
break;
default:
CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
return 1;
}
}
break;
case RSP_LB:
case RSP_LH:
case RSP_LW:
case RSP_LBU:
case RSP_LHU:
case RSP_SB:
case RSP_SH:
case RSP_SW:
break;
case RSP_LC2:
switch (RspOp.rd)
{
case RSP_LSC2_SV:
case RSP_LSC2_DV:
case RSP_LSC2_RV:
break;
case RSP_LSC2_QV:
case RSP_LSC2_LV:
case RSP_LSC2_UV:
case RSP_LSC2_PV:
case RSP_LSC2_TV:
break;
default:
CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
return 1;
}
break;
case RSP_SC2:
switch (RspOp.rd)
{
case RSP_LSC2_BV:
case RSP_LSC2_SV:
case RSP_LSC2_LV:
case RSP_LSC2_DV:
case RSP_LSC2_QV:
case RSP_LSC2_RV:
case RSP_LSC2_PV:
case RSP_LSC2_UV:
case RSP_LSC2_HV:
case RSP_LSC2_FV:
case RSP_LSC2_WV:
case RSP_LSC2_TV:
if (DestReg == RspOp.rt)
{
return 1;
}
break;
default:
CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
return 1;
}
break;
default:
CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
return 1;
}
switch (Instruction_State)
{
case NORMAL:
break;
case DO_DELAY_SLOT:
Instruction_State = DELAY_SLOT;
break;
case DELAY_SLOT:
if (JumpUncond)
{
PC = JumpTarget - 0x04;
Instruction_State = NORMAL;
}
else
{
Instruction_State = FINISH_BLOCK;
}
JumpUncond = 0;
break;
}
}
while (Instruction_State != FINISH_BLOCK);
/***
** This is a tricky situation because most of the
** microcode does loops, so looping back and checking
** can prove effective, but it's still a branch..
***/
if (BranchTarget != 0 && RecursiveCall == 0)
{
uint32_t BranchTaken, BranchFall;
/* analysis of branch taken */
BranchTaken = WriteToVectorDest2(DestReg, BranchTarget - 4, 1);
/* analysis of branch as nop */
BranchFall = WriteToVectorDest2(DestReg, PC, 1);
if (BranchImmed < 0)
{
if (BranchTaken != 0)
{
/*
** took this back branch and found a place
** that needs this vector as a source
**/
return 1;
}
else if (BranchFall == HIT_BRANCH)
{
/* (dlist) risky? the loop ended, hit another branch after loop-back */
#if !defined(RSP_SAFE_ANALYSIS)
CPU_Message("WriteToDest: Backward branch hit, BranchFall = Hit branch (returning 0)");
return 0;
#endif
return 1;
}
else
{
/* otherwise this is completely valid */
return BranchFall;
}
}
else
{
if (BranchFall != 0)
{
/*
** took this forward branch and found a place
** that needs this vector as a source
**/
return 1;
}
else if (BranchTaken == HIT_BRANCH)
{
/* (dlist) risky? jumped forward, hit another branch */
#if !defined(RSP_SAFE_ANALYSIS)
CPU_Message("WriteToDest: Forward branch hit, BranchTaken = Hit branch (returning 0)");
return 0;
#endif
return 1;
}
else
{
/* otherwise this is completely valid */
return BranchTaken;
}
}
}
else
{
return HIT_BRANCH;
}
}
int32_t WriteToVectorDest (uint32_t DestReg, int32_t PC)
{
uint32_t value = WriteToVectorDest2(DestReg, PC, 0);
if (value == HIT_BRANCH)
{
return 1; /* ??? */
}
else
{
return value;
}
}
/************************************************************
** UseRspFlags
**
** Output:
** 1: Flags are determined not in use
** 0: Either unable to determine or are in use
**
** Input: PC
*************************************************************/
/* TODO: consider delay slots and such in a branch? */
int32_t UseRspFlags (int32_t PC)
{
RSPOPCODE RspOp;
int32_t Instruction_State = RSPNextInstruction;
if (Compiler.bFlags == 0)
{
return 1;
}
if (Instruction_State == DELAY_SLOT)
{
return 1;
}
do
{
PC -= 4;
if (PC < 0)
{
return 1;
}
RSP_LW_IMEM(PC, &RspOp.Hex);
switch (RspOp.op)
{
case RSP_REGIMM:
switch (RspOp.rt)
{
case RSP_REGIMM_BLTZ:
case RSP_REGIMM_BGEZ:
Instruction_State = DO_DELAY_SLOT;
break;
default:
CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
return 1;
}
break;
case RSP_SPECIAL:
switch (RspOp.funct)
{
case RSP_SPECIAL_SLL:
case RSP_SPECIAL_SRL:
case RSP_SPECIAL_SRA:
case RSP_SPECIAL_SLLV:
case RSP_SPECIAL_SRLV:
case RSP_SPECIAL_SRAV:
case RSP_SPECIAL_ADD:
case RSP_SPECIAL_ADDU:
case RSP_SPECIAL_SUB:
case RSP_SPECIAL_SUBU:
case RSP_SPECIAL_AND:
case RSP_SPECIAL_OR:
case RSP_SPECIAL_XOR:
case RSP_SPECIAL_NOR:
case RSP_SPECIAL_SLT:
case RSP_SPECIAL_SLTU:
case RSP_SPECIAL_BREAK:
break;
case RSP_SPECIAL_JR:
Instruction_State = DO_DELAY_SLOT;
break;
default:
CompilerWarning("Unkown opcode in WriteToVectorDest\n%s",RSPOpcodeName(RspOp.Hex,PC));
return 1;
}
break;
case RSP_J:
case RSP_JAL:
case RSP_BEQ:
case RSP_BNE:
case RSP_BLEZ:
case RSP_BGTZ:
Instruction_State = DO_DELAY_SLOT;
break;
case RSP_ADDI:
case RSP_ADDIU:
case RSP_SLTI:
case RSP_SLTIU:
case RSP_ANDI:
case RSP_ORI:
case RSP_XORI:
case RSP_LUI:
case RSP_CP0:
break;
case RSP_CP2:
if ((RspOp.rs & 0x10) != 0)
{
switch (RspOp.funct)
{
case RSP_VECTOR_VMULF:
case RSP_VECTOR_VMUDL:
case RSP_VECTOR_VMUDM:
case RSP_VECTOR_VMUDN:
case RSP_VECTOR_VMUDH:
break;
case RSP_VECTOR_VMACF:
case RSP_VECTOR_VMADL:
case RSP_VECTOR_VMADM:
case RSP_VECTOR_VMADN:
case RSP_VECTOR_VMADH:
break;