diff --git a/src/main/scala/diplomacy/SRAM.scala b/src/main/scala/diplomacy/SRAM.scala index 73b6d269d1c..5bd79302454 100644 --- a/src/main/scala/diplomacy/SRAM.scala +++ b/src/main/scala/diplomacy/SRAM.scala @@ -11,11 +11,13 @@ abstract class DiplomaticSRAM( val address: AddressSet, beatBytes: Int, devName: Option[String], - dtsCompat: Option[Seq[String]] = None)(implicit p: Parameters) extends LazyModule + dtsCompat: Option[Seq[String]] = None, + devOverride: Option[Device with DeviceRegName] = None)(implicit p: Parameters) extends LazyModule { - val device = devName + val device = devOverride.getOrElse(devName .map(new SimpleDevice(_, dtsCompat.getOrElse(Seq("sifive,sram0")))) .getOrElse(new MemoryDevice()) + ) val resources = device.reg("mem") diff --git a/src/main/scala/tilelink/SRAM.scala b/src/main/scala/tilelink/SRAM.scala index 7405d15c380..3c71b377830 100644 --- a/src/main/scala/tilelink/SRAM.scala +++ b/src/main/scala/tilelink/SRAM.scala @@ -23,8 +23,9 @@ class TLRAM( ecc: ECCParams = ECCParams(), sramReg: Boolean = false, // drive SRAM data output directly into a register => 1 cycle longer response val devName: Option[String] = None, - val dtsCompat: Option[Seq[String]] = None - )(implicit p: Parameters) extends DiplomaticSRAM(address, beatBytes, devName, dtsCompat) + val dtsCompat: Option[Seq[String]] = None, + val devOverride: Option[Device with DeviceRegName] = None + )(implicit p: Parameters) extends DiplomaticSRAM(address, beatBytes, devName, dtsCompat, devOverride) { val eccBytes = ecc.bytes val code = ecc.code @@ -35,7 +36,7 @@ class TLRAM( val node = TLManagerNode(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = List(address), - resources = device.reg("mem"), + resources = resources, regionType = if (cacheable) RegionType.UNCACHED else RegionType.IDEMPOTENT, executable = executable, supportsGet = TransferSizes(1, beatBytes),