diff --git a/src/main/scala/amba/axi4/Deinterleaver.scala b/src/main/scala/amba/axi4/Deinterleaver.scala index 7f560492dcd..384ba7ae7b3 100644 --- a/src/main/scala/amba/axi4/Deinterleaver.scala +++ b/src/main/scala/amba/axi4/Deinterleaver.scala @@ -72,7 +72,7 @@ class AXI4Deinterleaver(maxReadBytes: Int, buffer: BufferParams = BufferParams.d // correct type. val q = Wire(new QueueIO(out.r.bits.cloneType, beats)) q.suggestName(s"queue_wire_${i}") - assert(!q.enq.valid, s"ID ${i} should not be used") + assert(!q.enq.valid, cf"ID ${i.toString} should not be used") q := DontCare q } diff --git a/src/main/scala/devices/debug/Debug.scala b/src/main/scala/devices/debug/Debug.scala index ef93c3fad11..e2841ddbed6 100755 --- a/src/main/scala/devices/debug/Debug.scala +++ b/src/main/scala/devices/debug/Debug.scala @@ -1503,7 +1503,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I val flags = WireInit(VecInit(Seq.fill(1 << selectedHartReg.getWidth) {0.U.asTypeOf(new flagBundle())} )) assert ((hartSelFuncs.hartSelToHartId(selectedHartReg) < flags.size.U), - s"HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < ${flags.size} for it to work.") + cf"HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < ${flags.size.toString} for it to work.") flags(hartSelFuncs.hartSelToHartId(selectedHartReg)).go := goReg for (component <- 0 until nComponents) { diff --git a/src/main/scala/formal/FormalUtils.scala b/src/main/scala/formal/FormalUtils.scala index 04f2aba078f..8aeea02a0ce 100644 --- a/src/main/scala/formal/FormalUtils.scala +++ b/src/main/scala/formal/FormalUtils.scala @@ -68,24 +68,24 @@ object Property { val src_wrap = s"@[${proposed_src}]" if (dir==MonitorDirection.Monitor) { when(!cond) { - printf(s"assert:${proposed_src}:${prop_type.toString} ${message + "_" + line_info}") + printf(cf"assert:${proposed_src}:${prop_type.toString} ${message + "_" + line_info}") } } else if (dir==MonitorDirection.Receiver) { when(!cond) { - printf(s"assert:${proposed_src}:${prop_type.toString} ${message + "_" + line_info}") + printf(cf"assert:${proposed_src}:${prop_type.toString} ${message + "_" + line_info}") } } else if (dir==MonitorDirection.Driver) { when(!cond) { - printf(s"assume:${proposed_src}:${prop_type.toString} ${message + "_" + line_info}") + printf(cf"assume:${proposed_src}:${prop_type.toString} ${message + "_" + line_info}") } } else if (dir==MonitorDirection.Cover) { if (prop_type==PropertyClass.CoverDisableMonitor) { when(cond) { //We want to assert that the condition is never true, which is opposite of a normal assertion - printf(s"assert:${proposed_src}:${prop_type.toString} ${message + "_" + line_info}") + printf(cf"assert:${proposed_src}:${prop_type.toString} ${message + "_" + line_info}") } } else { when(cond) { - printf(s"cover:${proposed_src}:${prop_type.toString} ${message + "_" + line_info}") + printf(cf"cover:${proposed_src}:${prop_type.toString} ${message + "_" + line_info}") } } } diff --git a/src/main/scala/groundtest/TraceGen.scala b/src/main/scala/groundtest/TraceGen.scala index 5a48857acd5..0c88f46cb04 100644 --- a/src/main/scala/groundtest/TraceGen.scala +++ b/src/main/scala/groundtest/TraceGen.scala @@ -585,7 +585,7 @@ class TraceGenerator(val params: TraceGenParams)(implicit val p: Parameters) ext // Emit that this thread has completed when (donePulse) { - printf(s"FINISHED ${numGens}\n") + printf(cf"FINISHED ${numGens.toString}\n") } io.finished := done @@ -631,5 +631,5 @@ class TraceGenTileModuleImp(outer: TraceGenTile) extends GroundTestTileModuleImp status.timeout.bits := 0.U status.error.valid := false.B - assert(!tracegen.io.timeout, s"TraceGen tile ${outer.tileParams.hartId}: request timed out") + assert(!tracegen.io.timeout, cf"TraceGen tile ${outer.tileParams.hartId.toString}: request timed out") } diff --git a/src/main/scala/rocket/Events.scala b/src/main/scala/rocket/Events.scala index 4e577cdf509..090066f7ea0 100644 --- a/src/main/scala/rocket/Events.scala +++ b/src/main/scala/rocket/Events.scala @@ -17,7 +17,7 @@ class EventSet(val gate: (UInt, UInt) => Bool, val events: Seq[(String, () => Bo } def dump(): Unit = { for (((name, _), i) <- events.zipWithIndex) - when (check(1.U << i)) { printf(s"Event $name\n") } + when (check(1.U << i)) { printf(cf"Event $name\n") } } def withCovers: Unit = { events.zipWithIndex.foreach { diff --git a/src/main/scala/tilelink/Arbiter.scala b/src/main/scala/tilelink/Arbiter.scala index bf7c238dbce..e6840122b8e 100644 --- a/src/main/scala/tilelink/Arbiter.scala +++ b/src/main/scala/tilelink/Arbiter.scala @@ -197,7 +197,7 @@ class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(impli { def assertLowest(id: Int): Unit = { when (sources(id).valid) { - assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") + assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), cf"${id.toString} was valid but a higher valid source was granted ready.") } } @@ -212,7 +212,7 @@ class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(impl { def assertHighest(id: Int): Unit = { when (sources(id).valid) { - assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") + assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), cf"${id.toString} was valid but a lower valid source was granted ready.") } } diff --git a/src/main/scala/tilelink/PatternPusher.scala b/src/main/scala/tilelink/PatternPusher.scala index b30661323f9..741f4fc91f4 100644 --- a/src/main/scala/tilelink/PatternPusher.scala +++ b/src/main/scala/tilelink/PatternPusher.scala @@ -71,7 +71,8 @@ class TLPatternPusher(name: String, pattern: Seq[Pattern])(implicit p: Parameter } val (plegal, pbits) = pattern.map(_.bits(edgeOut)).unzip - assert (end || Vec(plegal)(step), s"Pattern pusher ${name} tried to push an illegal request") + val msg = s"Pattern pusher $name tried to push an illegal request" + assert(end || Vec(plegal)(step), msg) a.valid := io.run && ready && !end && !flight a.bits := Vec(pbits)(step) diff --git a/src/main/scala/unittest/UnitTest.scala b/src/main/scala/unittest/UnitTest.scala index 1efdc6f3b64..46af6d62e75 100644 --- a/src/main/scala/unittest/UnitTest.scala +++ b/src/main/scala/unittest/UnitTest.scala @@ -28,10 +28,10 @@ trait UnitTestModule extends MultiIOModule with HasUnitTestIO { abstract class UnitTest(val timeout: Int = 4096) extends Module with UnitTestLegacyModule { val testName = this.getClass.getSimpleName - when (io.start) { printf(s"Started UnitTest $testName\n") } + when (io.start) { printf(cf"Started UnitTest $testName\n") } val timed_out = SimpleTimer(timeout, io.start, io.finished) - assert(!timed_out, s"UnitTest $testName timed out") + assert(!timed_out, cf"UnitTest $testName timed out") } case object UnitTests extends Field[Parameters => Seq[UnitTest]] diff --git a/src/main/scala/util/PlusArg.scala b/src/main/scala/util/PlusArg.scala index 59a1b4ec3bc..11cfa74aa65 100644 --- a/src/main/scala/util/PlusArg.scala +++ b/src/main/scala/util/PlusArg.scala @@ -61,7 +61,8 @@ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: Str }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { - assert (io.count < max, s"Timeout exceeded: $docstring") + val msg = s"Timeout exceeded: $docstring" + assert (io.count < max, msg) } } diff --git a/src/main/scala/util/Replacement.scala b/src/main/scala/util/Replacement.scala index f3a48aa7e26..000ec945114 100644 --- a/src/main/scala/util/Replacement.scala +++ b/src/main/scala/util/Replacement.scala @@ -339,204 +339,204 @@ class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) { n_ways match { case 2 => { - assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) - assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) - assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0)) - assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1)) - assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0)) - assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1)) + assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), "get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) + assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), "get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) + assert(get_next_states(0)(0) === 1.U(plru.nBits.W), "get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0)) + assert(get_next_states(0)(1) === 0.U(plru.nBits.W), "get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1)) + assert(get_next_states(1)(0) === 1.U(plru.nBits.W), "get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0)) + assert(get_next_states(1)(1) === 0.U(plru.nBits.W), "get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1)) } case 3 => { - assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) - assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) - assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2)) - assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3)) - assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0)) - assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1)) - assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2)) - assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0)) - assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1)) - assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2)) - assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0)) - assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1)) - assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2)) - assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0)) - assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1)) - assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2)) + assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), "get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) + assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), "get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) + assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), "get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2)) + assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), "get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3)) + assert(get_next_states(0)(0) === 3.U(plru.nBits.W), "get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0)) + assert(get_next_states(0)(1) === 2.U(plru.nBits.W), "get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1)) + assert(get_next_states(0)(2) === 0.U(plru.nBits.W), "get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2)) + assert(get_next_states(1)(0) === 3.U(plru.nBits.W), "get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0)) + assert(get_next_states(1)(1) === 2.U(plru.nBits.W), "get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1)) + assert(get_next_states(1)(2) === 1.U(plru.nBits.W), "get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2)) + assert(get_next_states(2)(0) === 3.U(plru.nBits.W), "get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0)) + assert(get_next_states(2)(1) === 2.U(plru.nBits.W), "get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1)) + assert(get_next_states(2)(2) === 0.U(plru.nBits.W), "get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2)) + assert(get_next_states(3)(0) === 3.U(plru.nBits.W), "get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0)) + assert(get_next_states(3)(1) === 2.U(plru.nBits.W), "get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1)) + assert(get_next_states(3)(2) === 1.U(plru.nBits.W), "get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2)) } case 4 => { - assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) - assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) - assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2)) - assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3)) - assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4)) - assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5)) - assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6)) - assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7)) - assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0)) - assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1)) - assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2)) - assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3)) - assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0)) - assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1)) - assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2)) - assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3)) - assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0)) - assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1)) - assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2)) - assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3)) - assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0)) - assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1)) - assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2)) - assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3)) - assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0)) - assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1)) - assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2)) - assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3)) - assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0)) - assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1)) - assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2)) - assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3)) - assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0)) - assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1)) - assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2)) - assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3)) - assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0)) - assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1)) - assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2)) - assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3)) + assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), "get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) + assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), "get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) + assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), "get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2)) + assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), "get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3)) + assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), "get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4)) + assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), "get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5)) + assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), "get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6)) + assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), "get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7)) + assert(get_next_states(0)(0) === 5.U(plru.nBits.W), "get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0)) + assert(get_next_states(0)(1) === 4.U(plru.nBits.W), "get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1)) + assert(get_next_states(0)(2) === 2.U(plru.nBits.W), "get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2)) + assert(get_next_states(0)(3) === 0.U(plru.nBits.W), "get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3)) + assert(get_next_states(1)(0) === 5.U(plru.nBits.W), "get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0)) + assert(get_next_states(1)(1) === 4.U(plru.nBits.W), "get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1)) + assert(get_next_states(1)(2) === 3.U(plru.nBits.W), "get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2)) + assert(get_next_states(1)(3) === 1.U(plru.nBits.W), "get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3)) + assert(get_next_states(2)(0) === 7.U(plru.nBits.W), "get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0)) + assert(get_next_states(2)(1) === 6.U(plru.nBits.W), "get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1)) + assert(get_next_states(2)(2) === 2.U(plru.nBits.W), "get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2)) + assert(get_next_states(2)(3) === 0.U(plru.nBits.W), "get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3)) + assert(get_next_states(3)(0) === 7.U(plru.nBits.W), "get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0)) + assert(get_next_states(3)(1) === 6.U(plru.nBits.W), "get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1)) + assert(get_next_states(3)(2) === 3.U(plru.nBits.W), "get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2)) + assert(get_next_states(3)(3) === 1.U(plru.nBits.W), "get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3)) + assert(get_next_states(4)(0) === 5.U(plru.nBits.W), "get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0)) + assert(get_next_states(4)(1) === 4.U(plru.nBits.W), "get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1)) + assert(get_next_states(4)(2) === 2.U(plru.nBits.W), "get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2)) + assert(get_next_states(4)(3) === 0.U(plru.nBits.W), "get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3)) + assert(get_next_states(5)(0) === 5.U(plru.nBits.W), "get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0)) + assert(get_next_states(5)(1) === 4.U(plru.nBits.W), "get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1)) + assert(get_next_states(5)(2) === 3.U(plru.nBits.W), "get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2)) + assert(get_next_states(5)(3) === 1.U(plru.nBits.W), "get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3)) + assert(get_next_states(6)(0) === 7.U(plru.nBits.W), "get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0)) + assert(get_next_states(6)(1) === 6.U(plru.nBits.W), "get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1)) + assert(get_next_states(6)(2) === 2.U(plru.nBits.W), "get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2)) + assert(get_next_states(6)(3) === 0.U(plru.nBits.W), "get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3)) + assert(get_next_states(7)(0) === 7.U(plru.nBits.W), "get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0)) + assert(get_next_states(7)(1) === 6.U(plru.nBits.W), "get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1)) + assert(get_next_states(7)(2) === 3.U(plru.nBits.W), "get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2)) + assert(get_next_states(7)(3) === 1.U(plru.nBits.W), "get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3)) } case 5 => { - assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) - assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) - assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) - assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) - assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) - assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) - assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) - assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) - assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8)) - assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9)) - assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10)) - assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11)) - assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12)) - assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13)) - assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14)) - assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15)) - assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0)) - assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1)) - assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2)) - assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3)) - assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4)) - assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0)) - assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1)) - assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2)) - assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3)) - assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4)) - assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0)) - assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1)) - assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2)) - assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3)) - assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4)) - assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0)) - assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1)) - assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2)) - assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3)) - assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4)) - assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0)) - assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1)) - assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2)) - assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3)) - assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4)) - assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0)) - assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1)) - assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2)) - assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3)) - assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4)) - assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0)) - assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1)) - assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2)) - assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3)) - assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4)) - assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0)) - assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1)) - assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2)) - assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3)) - assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4)) - assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0)) - assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1)) - assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2)) - assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3)) - assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4)) - assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0)) - assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1)) - assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2)) - assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3)) - assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4)) - assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0)) - assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1)) - assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2)) - assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3)) - assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4)) - assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0)) - assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1)) - assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2)) - assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3)) - assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4)) - assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0)) - assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1)) - assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2)) - assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3)) - assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4)) - assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0)) - assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1)) - assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2)) - assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3)) - assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4)) - assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0)) - assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1)) - assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2)) - assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3)) - assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4)) - assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0)) - assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1)) - assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2)) - assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3)) - assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4)) + assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), "get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) + assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), "get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) + assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), "get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) + assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), "get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) + assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), "get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) + assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), "get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) + assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), "get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) + assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), "get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) + assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), "get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8)) + assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), "get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9)) + assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), "get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10)) + assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), "get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11)) + assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), "get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12)) + assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), "get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13)) + assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), "get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14)) + assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), "get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15)) + assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), "get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0)) + assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), "get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1)) + assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), "get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2)) + assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), "get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3)) + assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), "get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4)) + assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), "get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0)) + assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), "get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1)) + assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), "get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2)) + assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), "get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3)) + assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), "get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4)) + assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), "get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0)) + assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), "get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1)) + assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), "get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2)) + assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), "get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3)) + assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), "get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4)) + assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), "get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0)) + assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), "get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1)) + assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), "get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2)) + assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), "get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3)) + assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), "get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4)) + assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), "get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0)) + assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), "get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1)) + assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), "get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2)) + assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), "get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3)) + assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), "get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4)) + assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), "get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0)) + assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), "get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1)) + assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), "get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2)) + assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), "get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3)) + assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), "get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4)) + assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), "get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0)) + assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), "get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1)) + assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), "get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2)) + assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), "get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3)) + assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), "get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4)) + assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), "get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0)) + assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), "get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1)) + assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), "get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2)) + assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), "get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3)) + assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), "get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4)) + assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), "get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0)) + assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), "get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1)) + assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), "get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2)) + assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), "get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3)) + assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), "get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4)) + assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), "get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0)) + assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), "get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1)) + assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), "get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2)) + assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), "get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3)) + assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), "get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4)) + assert(get_next_states(10)(0) === 15.U(plru.nBits.W), "get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0)) + assert(get_next_states(10)(1) === 14.U(plru.nBits.W), "get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1)) + assert(get_next_states(10)(2) === 10.U(plru.nBits.W), "get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2)) + assert(get_next_states(10)(3) === 8.U(plru.nBits.W), "get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3)) + assert(get_next_states(10)(4) === 2.U(plru.nBits.W), "get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4)) + assert(get_next_states(11)(0) === 15.U(plru.nBits.W), "get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0)) + assert(get_next_states(11)(1) === 14.U(plru.nBits.W), "get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1)) + assert(get_next_states(11)(2) === 11.U(plru.nBits.W), "get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2)) + assert(get_next_states(11)(3) === 9.U(plru.nBits.W), "get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3)) + assert(get_next_states(11)(4) === 3.U(plru.nBits.W), "get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4)) + assert(get_next_states(12)(0) === 13.U(plru.nBits.W), "get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0)) + assert(get_next_states(12)(1) === 12.U(plru.nBits.W), "get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1)) + assert(get_next_states(12)(2) === 10.U(plru.nBits.W), "get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2)) + assert(get_next_states(12)(3) === 8.U(plru.nBits.W), "get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3)) + assert(get_next_states(12)(4) === 4.U(plru.nBits.W), "get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4)) + assert(get_next_states(13)(0) === 13.U(plru.nBits.W), "get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0)) + assert(get_next_states(13)(1) === 12.U(plru.nBits.W), "get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1)) + assert(get_next_states(13)(2) === 11.U(plru.nBits.W), "get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2)) + assert(get_next_states(13)(3) === 9.U(plru.nBits.W), "get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3)) + assert(get_next_states(13)(4) === 5.U(plru.nBits.W), "get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4)) + assert(get_next_states(14)(0) === 15.U(plru.nBits.W), "get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0)) + assert(get_next_states(14)(1) === 14.U(plru.nBits.W), "get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1)) + assert(get_next_states(14)(2) === 10.U(plru.nBits.W), "get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2)) + assert(get_next_states(14)(3) === 8.U(plru.nBits.W), "get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3)) + assert(get_next_states(14)(4) === 6.U(plru.nBits.W), "get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4)) + assert(get_next_states(15)(0) === 15.U(plru.nBits.W), "get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0)) + assert(get_next_states(15)(1) === 14.U(plru.nBits.W), "get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1)) + assert(get_next_states(15)(2) === 11.U(plru.nBits.W), "get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2)) + assert(get_next_states(15)(3) === 9.U(plru.nBits.W), "get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3)) + assert(get_next_states(15)(4) === 7.U(plru.nBits.W), "get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4)) } case 6 => { - assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) - assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) - assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) - assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) - assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) - assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) - assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) - assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) - assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8)) - assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9)) - assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10)) - assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11)) - assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12)) - assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13)) - assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14)) - assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15)) - assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16)) - assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17)) - assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18)) - assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19)) - assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20)) - assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21)) - assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22)) - assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23)) - assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24)) - assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25)) - assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26)) - assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27)) - assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28)) - assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29)) - assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30)) - assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31)) + assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), "get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) + assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), "get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) + assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), "get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) + assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), "get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) + assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), "get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) + assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), "get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) + assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), "get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) + assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), "get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) + assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), "get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8)) + assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), "get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9)) + assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), "get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10)) + assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), "get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11)) + assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), "get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12)) + assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), "get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13)) + assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), "get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14)) + assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), "get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15)) + assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), "get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16)) + assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), "get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17)) + assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), "get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18)) + assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), "get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19)) + assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), "get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20)) + assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), "get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21)) + assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), "get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22)) + assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), "get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23)) + assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), "get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24)) + assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), "get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25)) + assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), "get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26)) + assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), "get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27)) + assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), "get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28)) + assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), "get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29)) + assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), "get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30)) + assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), "get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31)) } case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways") }