diff --git a/src/integration/config/compile.yml b/src/integration/config/compile.yml index 2058ddde3..3ed726ba8 100644 --- a/src/integration/config/compile.yml +++ b/src/integration/config/compile.yml @@ -18,7 +18,6 @@ schema_version: 2.4.0 requires: - caliptra_top_defines - libs - - axi_sub - kv_defines_pkg - pv_defines_pkg - dv_defines_pkg @@ -66,6 +65,7 @@ schema_version: 2.4.0 requires: - asserts - libs + - caliptra_axi_sram - spiflash - caliptra_top - el2_veer_pkg diff --git a/src/integration/rtl/caliptra_reg.h b/src/integration/rtl/caliptra_reg.h index 1354a0b6e..9099d2fdb 100644 --- a/src/integration/rtl/caliptra_reg.h +++ b/src/integration/rtl/caliptra_reg.h @@ -5179,8 +5179,8 @@ #define MBOX_CSR_MBOX_LOCK (0x0) #define MBOX_CSR_MBOX_LOCK_LOCK_LOW (0) #define MBOX_CSR_MBOX_LOCK_LOCK_MASK (0x1) -#define CLP_MBOX_CSR_MBOX_USER (0x30020004) -#define MBOX_CSR_MBOX_USER (0x4) +#define CLP_MBOX_CSR_MBOX_ID (0x30020004) +#define MBOX_CSR_MBOX_ID (0x4) #define CLP_MBOX_CSR_MBOX_CMD (0x30020008) #define MBOX_CSR_MBOX_CMD (0x8) #define CLP_MBOX_CSR_MBOX_DLEN (0x3002000c) @@ -5216,8 +5216,8 @@ #define SHA512_ACC_CSR_LOCK (0x0) #define SHA512_ACC_CSR_LOCK_LOCK_LOW (0) #define SHA512_ACC_CSR_LOCK_LOCK_MASK (0x1) -#define CLP_SHA512_ACC_CSR_USER (0x30021004) -#define SHA512_ACC_CSR_USER (0x4) +#define CLP_SHA512_ACC_CSR_ID (0x30021004) +#define SHA512_ACC_CSR_ID (0x4) #define CLP_SHA512_ACC_CSR_MODE (0x30021008) #define SHA512_ACC_CSR_MODE (0x8) #define SHA512_ACC_CSR_MODE_MODE_LOW (0) @@ -5363,6 +5363,240 @@ #define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (0xa10) #define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_BASE_ADDR (0x30022000) +#define CLP_AXI_DMA_REG_ID (0x30022000) +#define AXI_DMA_REG_ID (0x0) +#define CLP_AXI_DMA_REG_CAP (0x30022004) +#define AXI_DMA_REG_CAP (0x4) +#define CLP_AXI_DMA_REG_CTRL (0x30022008) +#define AXI_DMA_REG_CTRL (0x8) +#define AXI_DMA_REG_CTRL_GO_LOW (0) +#define AXI_DMA_REG_CTRL_GO_MASK (0x1) +#define AXI_DMA_REG_CTRL_FLUSH_LOW (1) +#define AXI_DMA_REG_CTRL_FLUSH_MASK (0x2) +#define AXI_DMA_REG_CTRL_RSVD0_LOW (2) +#define AXI_DMA_REG_CTRL_RSVD0_MASK (0xfffc) +#define AXI_DMA_REG_CTRL_RD_ROUTE_LOW (16) +#define AXI_DMA_REG_CTRL_RD_ROUTE_MASK (0x30000) +#define AXI_DMA_REG_CTRL_RSVD1_LOW (18) +#define AXI_DMA_REG_CTRL_RSVD1_MASK (0xc0000) +#define AXI_DMA_REG_CTRL_RD_FIXED_LOW (20) +#define AXI_DMA_REG_CTRL_RD_FIXED_MASK (0x100000) +#define AXI_DMA_REG_CTRL_RSVD2_LOW (21) +#define AXI_DMA_REG_CTRL_RSVD2_MASK (0xe00000) +#define AXI_DMA_REG_CTRL_WR_ROUTE_LOW (24) +#define AXI_DMA_REG_CTRL_WR_ROUTE_MASK (0x3000000) +#define AXI_DMA_REG_CTRL_RSVD3_LOW (26) +#define AXI_DMA_REG_CTRL_RSVD3_MASK (0xc000000) +#define AXI_DMA_REG_CTRL_WR_FIXED_LOW (28) +#define AXI_DMA_REG_CTRL_WR_FIXED_MASK (0x10000000) +#define AXI_DMA_REG_CTRL_RSVD4_LOW (29) +#define AXI_DMA_REG_CTRL_RSVD4_MASK (0xe0000000) +#define CLP_AXI_DMA_REG_STATUS0 (0x3002200c) +#define AXI_DMA_REG_STATUS0 (0xc) +#define AXI_DMA_REG_STATUS0_BUSY_LOW (0) +#define AXI_DMA_REG_STATUS0_BUSY_MASK (0x1) +#define AXI_DMA_REG_STATUS0_ERROR_LOW (1) +#define AXI_DMA_REG_STATUS0_ERROR_MASK (0x2) +#define AXI_DMA_REG_STATUS0_RSVD0_LOW (2) +#define AXI_DMA_REG_STATUS0_RSVD0_MASK (0xfffc) +#define AXI_DMA_REG_STATUS0_AXI_DMA_FSM_PS_LOW (16) +#define AXI_DMA_REG_STATUS0_AXI_DMA_FSM_PS_MASK (0x30000) +#define AXI_DMA_REG_STATUS0_RSVD1_LOW (18) +#define AXI_DMA_REG_STATUS0_RSVD1_MASK (0xfffc0000) +#define CLP_AXI_DMA_REG_STATUS1 (0x30022010) +#define AXI_DMA_REG_STATUS1 (0x10) +#define CLP_AXI_DMA_REG_SRC_ADDR_L (0x30022014) +#define AXI_DMA_REG_SRC_ADDR_L (0x14) +#define CLP_AXI_DMA_REG_SRC_ADDR_H (0x30022018) +#define AXI_DMA_REG_SRC_ADDR_H (0x18) +#define CLP_AXI_DMA_REG_DST_ADDR_L (0x3002201c) +#define AXI_DMA_REG_DST_ADDR_L (0x1c) +#define CLP_AXI_DMA_REG_DST_ADDR_H (0x30022020) +#define AXI_DMA_REG_DST_ADDR_H (0x20) +#define CLP_AXI_DMA_REG_BYTE_COUNT (0x30022024) +#define AXI_DMA_REG_BYTE_COUNT (0x24) +#define CLP_AXI_DMA_REG_BLOCK_SIZE (0x30022028) +#define AXI_DMA_REG_BLOCK_SIZE (0x28) +#define AXI_DMA_REG_BLOCK_SIZE_SIZE_LOW (0) +#define AXI_DMA_REG_BLOCK_SIZE_SIZE_MASK (0xfff) +#define AXI_DMA_REG_BLOCK_SIZE_RSVD_LOW (12) +#define AXI_DMA_REG_BLOCK_SIZE_RSVD_MASK (0xfffff000) +#define CLP_AXI_DMA_REG_WRITE_DATA (0x3002202c) +#define AXI_DMA_REG_WRITE_DATA (0x2c) +#define CLP_AXI_DMA_REG_READ_DATA (0x30022030) +#define AXI_DMA_REG_READ_DATA (0x30) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_START (0x30022800) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x30022800) +#define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x800) +#define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (0x1) +#define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) +#define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (0x2) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x30022804) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x804) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_CMD_DEC_EN_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_CMD_DEC_EN_MASK (0x1) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_RD_EN_LOW (1) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_RD_EN_MASK (0x2) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_WR_EN_LOW (2) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_WR_EN_MASK (0x4) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_MBOX_LOCK_EN_LOW (3) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_MBOX_LOCK_EN_MASK (0x8) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_SHA_LOCK_EN_LOW (4) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_SHA_LOCK_EN_MASK (0x10) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_OFLOW_EN_LOW (5) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_OFLOW_EN_MASK (0x20) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_UFLOW_EN_LOW (6) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_UFLOW_EN_MASK (0x40) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x30022808) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x808) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_TXN_DONE_EN_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_TXN_DONE_EN_MASK (0x1) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_EMPTY_EN_LOW (1) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_EMPTY_EN_MASK (0x2) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_EMPTY_EN_LOW (2) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_EMPTY_EN_MASK (0x4) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_FULL_EN_LOW (3) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_FULL_EN_MASK (0x8) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_FULL_EN_LOW (4) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_FULL_EN_MASK (0x10) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x3002280c) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x80c) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x30022810) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x810) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x30022814) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x814) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_DEC_STS_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_DEC_STS_MASK (0x1) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_RD_STS_LOW (1) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_RD_STS_MASK (0x2) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_WR_STS_LOW (2) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_WR_STS_MASK (0x4) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_LOCK_STS_LOW (3) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_LOCK_STS_MASK (0x8) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_SHA_LOCK_STS_LOW (4) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_SHA_LOCK_STS_MASK (0x10) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_OFLOW_STS_LOW (5) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_OFLOW_STS_MASK (0x20) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_UFLOW_STS_LOW (6) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_UFLOW_STS_MASK (0x40) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x30022818) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x818) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_TXN_DONE_STS_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_TXN_DONE_STS_MASK (0x1) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_EMPTY_STS_LOW (1) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_EMPTY_STS_MASK (0x2) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_EMPTY_STS_LOW (2) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_EMPTY_STS_MASK (0x4) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_FULL_STS_LOW (3) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_FULL_STS_MASK (0x8) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_FULL_STS_LOW (4) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_FULL_STS_MASK (0x10) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x3002281c) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x81c) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_CMD_DEC_TRIG_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_CMD_DEC_TRIG_MASK (0x1) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_RD_TRIG_LOW (1) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_RD_TRIG_MASK (0x2) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_WR_TRIG_LOW (2) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_WR_TRIG_MASK (0x4) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_MBOX_LOCK_TRIG_LOW (3) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_MBOX_LOCK_TRIG_MASK (0x8) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_SHA_LOCK_TRIG_LOW (4) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_SHA_LOCK_TRIG_MASK (0x10) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_OFLOW_TRIG_LOW (5) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_OFLOW_TRIG_MASK (0x20) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_UFLOW_TRIG_LOW (6) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_UFLOW_TRIG_MASK (0x40) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x30022820) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x820) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_TXN_DONE_TRIG_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_TXN_DONE_TRIG_MASK (0x1) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_EMPTY_TRIG_LOW (1) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_EMPTY_TRIG_MASK (0x2) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_EMPTY_TRIG_LOW (2) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_EMPTY_TRIG_MASK (0x4) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_FULL_TRIG_LOW (3) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_FULL_TRIG_MASK (0x8) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_FULL_TRIG_LOW (4) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_FULL_TRIG_MASK (0x10) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_R (0x30022900) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_R (0x900) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_R (0x30022904) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_R (0x904) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_R (0x30022908) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_R (0x908) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_R (0x3002290c) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_R (0x90c) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_R (0x30022910) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_R (0x910) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_R (0x30022914) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_R (0x914) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_R (0x30022918) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_R (0x918) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_R (0x30022980) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_R (0x980) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_R (0x30022984) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_R (0x984) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_R (0x30022988) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_R (0x988) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_R (0x3002298c) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_R (0x98c) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_R (0x30022990) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_R (0x990) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R (0x30022a00) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R (0xa00) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R (0x30022a04) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R (0xa04) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R (0x30022a08) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R (0xa08) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R (0x30022a0c) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R (0xa0c) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R (0x30022a10) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R (0xa10) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R (0x30022a14) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R (0xa14) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R (0x30022a18) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R (0xa18) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R (0x30022a1c) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R (0xa1c) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R (0x30022a20) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R (0xa20) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R (0x30022a24) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R (0xa24) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R (0x30022a28) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R (0xa28) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R (0x30022a2c) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R (0xa2c) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R_PULSE_LOW (0) +#define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R_PULSE_MASK (0x1) #define CLP_SOC_IFC_REG_BASE_ADDR (0x30030000) #define CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL (0x30030000) #define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL (0x0) @@ -5440,42 +5674,42 @@ #define SOC_IFC_REG_CPTRA_SECURITY_STATE_SCAN_MODE_MASK (0x8) #define SOC_IFC_REG_CPTRA_SECURITY_STATE_RSVD_LOW (4) #define SOC_IFC_REG_CPTRA_SECURITY_STATE_RSVD_MASK (0xfffffff0) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_0 (0x30030048) -#define SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_0 (0x48) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_1 (0x3003004c) -#define SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_1 (0x4c) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_2 (0x30030050) -#define SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_2 (0x50) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_3 (0x30030054) -#define SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_3 (0x54) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_4 (0x30030058) -#define SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_4 (0x58) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0 (0x3003005c) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0 (0x5c) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0_LOCK_LOW (0) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0_LOCK_MASK (0x1) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_1 (0x30030060) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_1 (0x60) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_1_LOCK_LOW (0) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_1_LOCK_MASK (0x1) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_2 (0x30030064) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_2 (0x64) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_2_LOCK_LOW (0) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_2_LOCK_MASK (0x1) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_3 (0x30030068) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_3 (0x68) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_3_LOCK_LOW (0) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_3_LOCK_MASK (0x1) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_4 (0x3003006c) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_4 (0x6c) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_4_LOCK_LOW (0) -#define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_4_LOCK_MASK (0x1) -#define CLP_SOC_IFC_REG_CPTRA_TRNG_VALID_PAUSER (0x30030070) -#define SOC_IFC_REG_CPTRA_TRNG_VALID_PAUSER (0x70) -#define CLP_SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK (0x30030074) -#define SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK (0x74) -#define SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK_LOCK_LOW (0) -#define SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK_LOCK_MASK (0x1) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_0 (0x30030048) +#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_0 (0x48) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_1 (0x3003004c) +#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_1 (0x4c) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_2 (0x30030050) +#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_2 (0x50) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_3 (0x30030054) +#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_3 (0x54) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_4 (0x30030058) +#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_4 (0x58) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0 (0x3003005c) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0 (0x5c) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0_LOCK_LOW (0) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0_LOCK_MASK (0x1) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1 (0x30030060) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1 (0x60) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1_LOCK_LOW (0) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1_LOCK_MASK (0x1) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2 (0x30030064) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2 (0x64) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2_LOCK_LOW (0) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2_LOCK_MASK (0x1) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3 (0x30030068) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3 (0x68) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3_LOCK_LOW (0) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3_LOCK_MASK (0x1) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4 (0x3003006c) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4 (0x6c) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4_LOCK_LOW (0) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4_LOCK_MASK (0x1) +#define CLP_SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_ID (0x30030070) +#define SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_ID (0x70) +#define CLP_SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK (0x30030074) +#define SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK (0x74) +#define SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK_LOCK_LOW (0) +#define SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK_LOCK_MASK (0x1) #define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_0 (0x30030078) #define SOC_IFC_REG_CPTRA_TRNG_DATA_0 (0x78) #define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_1 (0x3003007c) @@ -5586,12 +5820,12 @@ #define SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK (0x1) #define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_LOW (1) #define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK (0x2) -#define CLP_SOC_IFC_REG_CPTRA_FUSE_VALID_PAUSER (0x30030108) -#define SOC_IFC_REG_CPTRA_FUSE_VALID_PAUSER (0x108) -#define CLP_SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK (0x3003010c) -#define SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK (0x10c) -#define SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK_LOCK_LOW (0) -#define SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK_LOCK_MASK (0x1) +#define CLP_SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_ID (0x30030108) +#define SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_ID (0x108) +#define CLP_SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK (0x3003010c) +#define SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK (0x10c) +#define SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK_LOCK_LOW (0) +#define SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK_LOCK_MASK (0x1) #define CLP_SOC_IFC_REG_CPTRA_WDT_CFG_0 (0x30030110) #define SOC_IFC_REG_CPTRA_WDT_CFG_0 (0x110) #define CLP_SOC_IFC_REG_CPTRA_WDT_CFG_1 (0x30030114) diff --git a/src/integration/rtl/caliptra_reg.rdl b/src/integration/rtl/caliptra_reg.rdl index 6f98b9bca..f92493fbf 100644 --- a/src/integration/rtl/caliptra_reg.rdl +++ b/src/integration/rtl/caliptra_reg.rdl @@ -44,6 +44,8 @@ addrmap clp { sha512_acc_csr sha512_acc_csr @ 0x3002_1000; + axi_dma_reg axi_dma_reg @ 0x3002_2000; + soc_ifc_reg soc_ifc_reg @ 0x3003_0000; }; diff --git a/src/integration/rtl/caliptra_reg_defines.svh b/src/integration/rtl/caliptra_reg_defines.svh index 56fe762f9..12601d5f6 100644 --- a/src/integration/rtl/caliptra_reg_defines.svh +++ b/src/integration/rtl/caliptra_reg_defines.svh @@ -5179,8 +5179,8 @@ `define MBOX_CSR_MBOX_LOCK (32'h0) `define MBOX_CSR_MBOX_LOCK_LOCK_LOW (0) `define MBOX_CSR_MBOX_LOCK_LOCK_MASK (32'h1) -`define CLP_MBOX_CSR_MBOX_USER (32'h30020004) -`define MBOX_CSR_MBOX_USER (32'h4) +`define CLP_MBOX_CSR_MBOX_ID (32'h30020004) +`define MBOX_CSR_MBOX_ID (32'h4) `define CLP_MBOX_CSR_MBOX_CMD (32'h30020008) `define MBOX_CSR_MBOX_CMD (32'h8) `define CLP_MBOX_CSR_MBOX_DLEN (32'h3002000c) @@ -5216,8 +5216,8 @@ `define SHA512_ACC_CSR_LOCK (32'h0) `define SHA512_ACC_CSR_LOCK_LOCK_LOW (0) `define SHA512_ACC_CSR_LOCK_LOCK_MASK (32'h1) -`define CLP_SHA512_ACC_CSR_USER (32'h30021004) -`define SHA512_ACC_CSR_USER (32'h4) +`define CLP_SHA512_ACC_CSR_ID (32'h30021004) +`define SHA512_ACC_CSR_ID (32'h4) `define CLP_SHA512_ACC_CSR_MODE (32'h30021008) `define SHA512_ACC_CSR_MODE (32'h8) `define SHA512_ACC_CSR_MODE_MODE_LOW (0) @@ -5363,6 +5363,240 @@ `define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'ha10) `define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_BASE_ADDR (32'h30022000) +`define CLP_AXI_DMA_REG_ID (32'h30022000) +`define AXI_DMA_REG_ID (32'h0) +`define CLP_AXI_DMA_REG_CAP (32'h30022004) +`define AXI_DMA_REG_CAP (32'h4) +`define CLP_AXI_DMA_REG_CTRL (32'h30022008) +`define AXI_DMA_REG_CTRL (32'h8) +`define AXI_DMA_REG_CTRL_GO_LOW (0) +`define AXI_DMA_REG_CTRL_GO_MASK (32'h1) +`define AXI_DMA_REG_CTRL_FLUSH_LOW (1) +`define AXI_DMA_REG_CTRL_FLUSH_MASK (32'h2) +`define AXI_DMA_REG_CTRL_RSVD0_LOW (2) +`define AXI_DMA_REG_CTRL_RSVD0_MASK (32'hfffc) +`define AXI_DMA_REG_CTRL_RD_ROUTE_LOW (16) +`define AXI_DMA_REG_CTRL_RD_ROUTE_MASK (32'h30000) +`define AXI_DMA_REG_CTRL_RSVD1_LOW (18) +`define AXI_DMA_REG_CTRL_RSVD1_MASK (32'hc0000) +`define AXI_DMA_REG_CTRL_RD_FIXED_LOW (20) +`define AXI_DMA_REG_CTRL_RD_FIXED_MASK (32'h100000) +`define AXI_DMA_REG_CTRL_RSVD2_LOW (21) +`define AXI_DMA_REG_CTRL_RSVD2_MASK (32'he00000) +`define AXI_DMA_REG_CTRL_WR_ROUTE_LOW (24) +`define AXI_DMA_REG_CTRL_WR_ROUTE_MASK (32'h3000000) +`define AXI_DMA_REG_CTRL_RSVD3_LOW (26) +`define AXI_DMA_REG_CTRL_RSVD3_MASK (32'hc000000) +`define AXI_DMA_REG_CTRL_WR_FIXED_LOW (28) +`define AXI_DMA_REG_CTRL_WR_FIXED_MASK (32'h10000000) +`define AXI_DMA_REG_CTRL_RSVD4_LOW (29) +`define AXI_DMA_REG_CTRL_RSVD4_MASK (32'he0000000) +`define CLP_AXI_DMA_REG_STATUS0 (32'h3002200c) +`define AXI_DMA_REG_STATUS0 (32'hc) +`define AXI_DMA_REG_STATUS0_BUSY_LOW (0) +`define AXI_DMA_REG_STATUS0_BUSY_MASK (32'h1) +`define AXI_DMA_REG_STATUS0_ERROR_LOW (1) +`define AXI_DMA_REG_STATUS0_ERROR_MASK (32'h2) +`define AXI_DMA_REG_STATUS0_RSVD0_LOW (2) +`define AXI_DMA_REG_STATUS0_RSVD0_MASK (32'hfffc) +`define AXI_DMA_REG_STATUS0_AXI_DMA_FSM_PS_LOW (16) +`define AXI_DMA_REG_STATUS0_AXI_DMA_FSM_PS_MASK (32'h30000) +`define AXI_DMA_REG_STATUS0_RSVD1_LOW (18) +`define AXI_DMA_REG_STATUS0_RSVD1_MASK (32'hfffc0000) +`define CLP_AXI_DMA_REG_STATUS1 (32'h30022010) +`define AXI_DMA_REG_STATUS1 (32'h10) +`define CLP_AXI_DMA_REG_SRC_ADDR_L (32'h30022014) +`define AXI_DMA_REG_SRC_ADDR_L (32'h14) +`define CLP_AXI_DMA_REG_SRC_ADDR_H (32'h30022018) +`define AXI_DMA_REG_SRC_ADDR_H (32'h18) +`define CLP_AXI_DMA_REG_DST_ADDR_L (32'h3002201c) +`define AXI_DMA_REG_DST_ADDR_L (32'h1c) +`define CLP_AXI_DMA_REG_DST_ADDR_H (32'h30022020) +`define AXI_DMA_REG_DST_ADDR_H (32'h20) +`define CLP_AXI_DMA_REG_BYTE_COUNT (32'h30022024) +`define AXI_DMA_REG_BYTE_COUNT (32'h24) +`define CLP_AXI_DMA_REG_BLOCK_SIZE (32'h30022028) +`define AXI_DMA_REG_BLOCK_SIZE (32'h28) +`define AXI_DMA_REG_BLOCK_SIZE_SIZE_LOW (0) +`define AXI_DMA_REG_BLOCK_SIZE_SIZE_MASK (32'hfff) +`define AXI_DMA_REG_BLOCK_SIZE_RSVD_LOW (12) +`define AXI_DMA_REG_BLOCK_SIZE_RSVD_MASK (32'hfffff000) +`define CLP_AXI_DMA_REG_WRITE_DATA (32'h3002202c) +`define AXI_DMA_REG_WRITE_DATA (32'h2c) +`define CLP_AXI_DMA_REG_READ_DATA (32'h30022030) +`define AXI_DMA_REG_READ_DATA (32'h30) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_START (32'h30022800) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h30022800) +`define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) +`define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) +`define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h30022804) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_CMD_DEC_EN_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_CMD_DEC_EN_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_RD_EN_LOW (1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_RD_EN_MASK (32'h2) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_WR_EN_LOW (2) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_WR_EN_MASK (32'h4) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_MBOX_LOCK_EN_LOW (3) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_MBOX_LOCK_EN_MASK (32'h8) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_SHA_LOCK_EN_LOW (4) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_SHA_LOCK_EN_MASK (32'h10) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_OFLOW_EN_LOW (5) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_OFLOW_EN_MASK (32'h20) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_UFLOW_EN_LOW (6) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_UFLOW_EN_MASK (32'h40) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h30022808) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_TXN_DONE_EN_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_TXN_DONE_EN_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_EMPTY_EN_LOW (1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_EMPTY_EN_MASK (32'h2) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_EMPTY_EN_LOW (2) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_EMPTY_EN_MASK (32'h4) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_FULL_EN_LOW (3) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_FULL_EN_MASK (32'h8) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_FULL_EN_LOW (4) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_FULL_EN_MASK (32'h10) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h3002280c) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h30022810) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h30022814) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_DEC_STS_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_DEC_STS_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_RD_STS_LOW (1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_RD_STS_MASK (32'h2) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_WR_STS_LOW (2) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_WR_STS_MASK (32'h4) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_LOCK_STS_LOW (3) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_LOCK_STS_MASK (32'h8) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_SHA_LOCK_STS_LOW (4) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_SHA_LOCK_STS_MASK (32'h10) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_OFLOW_STS_LOW (5) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_OFLOW_STS_MASK (32'h20) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_UFLOW_STS_LOW (6) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_UFLOW_STS_MASK (32'h40) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h30022818) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_TXN_DONE_STS_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_TXN_DONE_STS_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_EMPTY_STS_LOW (1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_EMPTY_STS_MASK (32'h2) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_EMPTY_STS_LOW (2) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_EMPTY_STS_MASK (32'h4) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_FULL_STS_LOW (3) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_FULL_STS_MASK (32'h8) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_FULL_STS_LOW (4) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_FULL_STS_MASK (32'h10) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h3002281c) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_CMD_DEC_TRIG_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_CMD_DEC_TRIG_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_RD_TRIG_LOW (1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_RD_TRIG_MASK (32'h2) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_WR_TRIG_LOW (2) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_WR_TRIG_MASK (32'h4) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_MBOX_LOCK_TRIG_LOW (3) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_MBOX_LOCK_TRIG_MASK (32'h8) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_SHA_LOCK_TRIG_LOW (4) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_SHA_LOCK_TRIG_MASK (32'h10) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_OFLOW_TRIG_LOW (5) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_OFLOW_TRIG_MASK (32'h20) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_UFLOW_TRIG_LOW (6) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_UFLOW_TRIG_MASK (32'h40) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h30022820) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_TXN_DONE_TRIG_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_TXN_DONE_TRIG_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_EMPTY_TRIG_LOW (1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_EMPTY_TRIG_MASK (32'h2) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_EMPTY_TRIG_LOW (2) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_EMPTY_TRIG_MASK (32'h4) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_FULL_TRIG_LOW (3) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_FULL_TRIG_MASK (32'h8) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_FULL_TRIG_LOW (4) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_FULL_TRIG_MASK (32'h10) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_R (32'h30022900) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_R (32'h900) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_R (32'h30022904) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_R (32'h904) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_R (32'h30022908) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_R (32'h908) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_R (32'h3002290c) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_R (32'h90c) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_R (32'h30022910) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_R (32'h910) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_R (32'h30022914) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_R (32'h914) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_R (32'h30022918) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_R (32'h918) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_R (32'h30022980) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_R (32'h980) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_R (32'h30022984) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_R (32'h984) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_R (32'h30022988) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_R (32'h988) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_R (32'h3002298c) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_R (32'h98c) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_R (32'h30022990) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_R (32'h990) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R (32'h30022a00) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R (32'ha00) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R (32'h30022a04) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R (32'ha04) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R (32'h30022a08) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R (32'ha08) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R (32'h30022a0c) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R (32'ha0c) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R (32'h30022a10) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R (32'ha10) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R (32'h30022a14) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R (32'ha14) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R (32'h30022a18) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R (32'ha18) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R (32'h30022a1c) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R (32'ha1c) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R (32'h30022a20) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R (32'ha20) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R (32'h30022a24) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R (32'ha24) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R (32'h30022a28) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R (32'ha28) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R (32'h30022a2c) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R (32'ha2c) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SOC_IFC_REG_BASE_ADDR (32'h30030000) `define CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL (32'h30030000) `define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL (32'h0) @@ -5440,42 +5674,42 @@ `define SOC_IFC_REG_CPTRA_SECURITY_STATE_SCAN_MODE_MASK (32'h8) `define SOC_IFC_REG_CPTRA_SECURITY_STATE_RSVD_LOW (4) `define SOC_IFC_REG_CPTRA_SECURITY_STATE_RSVD_MASK (32'hfffffff0) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_0 (32'h30030048) -`define SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_0 (32'h48) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_1 (32'h3003004c) -`define SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_1 (32'h4c) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_2 (32'h30030050) -`define SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_2 (32'h50) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_3 (32'h30030054) -`define SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_3 (32'h54) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_4 (32'h30030058) -`define SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_4 (32'h58) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0 (32'h3003005c) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0 (32'h5c) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0_LOCK_MASK (32'h1) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_1 (32'h30030060) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_1 (32'h60) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_1_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_1_LOCK_MASK (32'h1) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_2 (32'h30030064) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_2 (32'h64) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_2_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_2_LOCK_MASK (32'h1) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_3 (32'h30030068) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_3 (32'h68) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_3_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_3_LOCK_MASK (32'h1) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_4 (32'h3003006c) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_4 (32'h6c) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_4_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_4_LOCK_MASK (32'h1) -`define CLP_SOC_IFC_REG_CPTRA_TRNG_VALID_PAUSER (32'h30030070) -`define SOC_IFC_REG_CPTRA_TRNG_VALID_PAUSER (32'h70) -`define CLP_SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK (32'h30030074) -`define SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK (32'h74) -`define SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK_LOCK_MASK (32'h1) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_0 (32'h30030048) +`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_0 (32'h48) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_1 (32'h3003004c) +`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_1 (32'h4c) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_2 (32'h30030050) +`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_2 (32'h50) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_3 (32'h30030054) +`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_3 (32'h54) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_4 (32'h30030058) +`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_4 (32'h58) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0 (32'h3003005c) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0 (32'h5c) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0_LOCK_MASK (32'h1) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1 (32'h30030060) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1 (32'h60) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1_LOCK_MASK (32'h1) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2 (32'h30030064) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2 (32'h64) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2_LOCK_MASK (32'h1) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3 (32'h30030068) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3 (32'h68) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3_LOCK_MASK (32'h1) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4 (32'h3003006c) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4 (32'h6c) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4_LOCK_MASK (32'h1) +`define CLP_SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_ID (32'h30030070) +`define SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_ID (32'h70) +`define CLP_SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK (32'h30030074) +`define SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK (32'h74) +`define SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK_LOCK_MASK (32'h1) `define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_0 (32'h30030078) `define SOC_IFC_REG_CPTRA_TRNG_DATA_0 (32'h78) `define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_1 (32'h3003007c) @@ -5586,12 +5820,12 @@ `define SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK (32'h1) `define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_LOW (1) `define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK (32'h2) -`define CLP_SOC_IFC_REG_CPTRA_FUSE_VALID_PAUSER (32'h30030108) -`define SOC_IFC_REG_CPTRA_FUSE_VALID_PAUSER (32'h108) -`define CLP_SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK (32'h3003010c) -`define SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK (32'h10c) -`define SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK_LOCK_MASK (32'h1) +`define CLP_SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_ID (32'h30030108) +`define SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_ID (32'h108) +`define CLP_SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK (32'h3003010c) +`define SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK (32'h10c) +`define SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK_LOCK_MASK (32'h1) `define CLP_SOC_IFC_REG_CPTRA_WDT_CFG_0 (32'h30030110) `define SOC_IFC_REG_CPTRA_WDT_CFG_0 (32'h110) `define CLP_SOC_IFC_REG_CPTRA_WDT_CFG_1 (32'h30030114) diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv index 20bb36858..0ee9888a3 100755 --- a/src/integration/rtl/caliptra_top.sv +++ b/src/integration/rtl/caliptra_top.sv @@ -48,6 +48,10 @@ module caliptra_top axi_if.w_sub s_axi_w_if, axi_if.r_sub s_axi_r_if, + // AXI Manager INF + axi_if.w_mgr m_axi_w_if, + axi_if.r_mgr m_axi_r_if, + //QSPI Interface output logic qspi_clk_o, output logic [`CALIPTRA_QSPI_CS_WIDTH-1:0] qspi_cs_no, @@ -83,6 +87,8 @@ module caliptra_top output logic mailbox_data_avail, output logic mailbox_flow_done, + input logic recovery_data_avail, + input logic BootFSM_BrkPoint, //SoC Interrupts @@ -217,7 +223,8 @@ module caliptra_top wire soc_ifc_notif_intr; wire sha_error_intr; wire sha_notif_intr; - + wire dma_error_intr; + wire dma_notif_intr; logic [NUM_INTR-1:0] intr; kv_read_t [KV_NUM_READ-1:0] kv_read; @@ -397,6 +404,8 @@ always_comb begin intr[`VEER_INTR_VEC_SOC_IFC_NOTIF-1] = soc_ifc_notif_intr; intr[`VEER_INTR_VEC_SHA_ERROR -1] = sha_error_intr; intr[`VEER_INTR_VEC_SHA_NOTIF -1] = sha_notif_intr; + intr[`VEER_INTR_VEC_AXI_DMA_ERROR-1] = dma_error_intr; + intr[`VEER_INTR_VEC_AXI_DMA_NOTIF-1] = dma_notif_intr; intr[NUM_INTR-1:`VEER_INTR_VEC_MAX_ASSIGNED] = '0; end @@ -1196,22 +1205,30 @@ soc_ifc_top #( .AXI_ADDR_WIDTH(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)), .AXI_DATA_WIDTH(`CALIPTRA_AXI_DATA_WIDTH), .AXI_ID_WIDTH (`CALIPTRA_AXI_ID_WIDTH ), - .AXI_USER_WIDTH(`CALIPTRA_AXI_USER_WIDTH) + .AXI_USER_WIDTH(`CALIPTRA_AXI_USER_WIDTH), + .AXIM_ADDR_WIDTH(`CALIPTRA_AXI_DMA_ADDR_WIDTH), + .AXIM_DATA_WIDTH(CPTRA_AXI_DMA_DATA_WIDTH), + .AXIM_ID_WIDTH (CPTRA_AXI_DMA_ID_WIDTH), + .AXIM_USER_WIDTH(CPTRA_AXI_DMA_USER_WIDTH) ) soc_ifc_top1 ( - .clk(clk), - .clk_cg(clk_cg), + .clk (clk ), + .clk_cg (clk_cg ), .soc_ifc_clk_cg(soc_ifc_clk_cg), - .rdc_clk_cg(rdc_clk_cg), - .cptra_pwrgood(cptra_pwrgood), - .cptra_rst_b(cptra_rst_b), + .rdc_clk_cg (rdc_clk_cg ), + + .cptra_pwrgood(cptra_pwrgood), + .cptra_rst_b (cptra_rst_b ), + .ready_for_fuses(ready_for_fuses), .ready_for_fw_push(ready_for_fw_push), .ready_for_runtime(ready_for_runtime), .mailbox_data_avail(mailbox_data_avail), .mailbox_flow_done(mailbox_flow_done), + .recovery_data_avail(recovery_data_avail), + .security_state(cptra_security_state_Latched), .BootFSM_BrkPoint (BootFSM_BrkPoint), @@ -1241,6 +1258,11 @@ soc_ifc_top1 .hresp_o (responder_inst[`CALIPTRA_SLAVE_SEL_SOC_IFC].hresp), .hreadyout_o(responder_inst[`CALIPTRA_SLAVE_SEL_SOC_IFC].hreadyout), .hrdata_o (responder_inst[`CALIPTRA_SLAVE_SEL_SOC_IFC].hrdata), + + // AXI Manager INF + .m_axi_w_if(m_axi_w_if), + .m_axi_r_if(m_axi_r_if), + //SoC Interrupts .cptra_error_fatal (cptra_error_fatal), .cptra_error_non_fatal(cptra_error_non_fatal), @@ -1254,6 +1276,8 @@ soc_ifc_top1 .soc_ifc_notif_intr(soc_ifc_notif_intr), .sha_error_intr(sha_error_intr), .sha_notif_intr(sha_notif_intr), + .dma_error_intr(dma_error_intr), + .dma_notif_intr(dma_notif_intr), .timer_intr(timer_int), //Obfuscated UDS and FE .clear_obf_secrets(clear_obf_secrets_debugScanQ), //input - includes debug & scan modes to do the register clearing diff --git a/src/integration/rtl/config_defines.svh b/src/integration/rtl/config_defines.svh index aa572a15d..c750208ae 100755 --- a/src/integration/rtl/config_defines.svh +++ b/src/integration/rtl/config_defines.svh @@ -25,6 +25,7 @@ `define CALIPTRA_AXI_DATA_WIDTH 32 // bit-width AXI data `define CALIPTRA_AXI_USER_WIDTH 32 // bit-width AXI USER field `define CALIPTRA_AXI_ID_WIDTH 5 // bit-width AXI ID field + `define CALIPTRA_AXI_DMA_ADDR_WIDTH 48 `define CALIPTRA_QSPI_CS_WIDTH 2 `define CALIPTRA_QSPI_IO_WIDTH 4 `define CALIPTRA_SOC_SEC_STATE_WIDTH 3 @@ -77,8 +78,10 @@ `define VEER_INTR_VEC_SOC_IFC_NOTIF 20 `define VEER_INTR_VEC_SHA_ERROR 21 `define VEER_INTR_VEC_SHA_NOTIF 22 + `define VEER_INTR_VEC_AXI_DMA_ERROR 23 + `define VEER_INTR_VEC_AXI_DMA_NOTIF 24 // Used to tie-off unused upper intr bits - `define VEER_INTR_VEC_MAX_ASSIGNED `VEER_INTR_VEC_SHA_NOTIF + `define VEER_INTR_VEC_MAX_ASSIGNED `VEER_INTR_VEC_AXI_DMA_NOTIF //`define CALIPTRA_KV_NUM_READ 6 //`define CALIPTRA_KV_NUM_WRITE 4