From 65dd299af4c5407a5cc1ed6f6b8d3fa2e841ba77 Mon Sep 17 00:00:00 2001
From: Caleb Whitehead <cwhitehead@microsoft.com>
Date: Thu, 30 May 2024 11:39:52 -0700
Subject: [PATCH] Add component inf 'write' signal

---
 src/axi/rtl/axi_sub.sv     | 2 ++
 src/axi/rtl/axi_sub_arb.sv | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/src/axi/rtl/axi_sub.sv b/src/axi/rtl/axi_sub.sv
index 222e47d0f..cfdbfd984 100644
--- a/src/axi/rtl/axi_sub.sv
+++ b/src/axi/rtl/axi_sub.sv
@@ -52,6 +52,7 @@ module axi_sub import axi_pkg::*; #(
     //COMPONENT INF
     output logic          dv,
     output logic [AW-1:0] addr, // Byte address
+    output logic          write,
     output logic [UW-1:0] user,
     output logic [IW-1:0] id,
     output logic [DW-1:0] wdata, // Requires: Component dwidth == AXI dwidth
@@ -191,6 +192,7 @@ module axi_sub import axi_pkg::*; #(
         //COMPONENT INF
         .dv     (dv     ),
         .addr   (addr   ),
+        .write  (write  ),
         .user   (user   ),
         .id     (id     ),
         .wdata  (wdata  ),
diff --git a/src/axi/rtl/axi_sub_arb.sv b/src/axi/rtl/axi_sub_arb.sv
index e11935289..aa770372c 100644
--- a/src/axi/rtl/axi_sub_arb.sv
+++ b/src/axi/rtl/axi_sub_arb.sv
@@ -65,6 +65,7 @@ module axi_sub_arb import axi_pkg::*; #(
     //COMPONENT INF
     output logic          dv,
     output logic [AW-1:0] addr, // Byte address
+    output logic          write,
     output logic [UW-1:0] user,
     output logic [IW-1:0] id,
     output logic [DW-1:0] wdata, // Requires: Component dwidth == AXI dwidth
@@ -118,6 +119,7 @@ module axi_sub_arb import axi_pkg::*; #(
     always_comb begin
         dv      = r_dv || w_dv;
         addr    = r_win ? r_addr : w_addr;
+        write   = r_win ?      0 :      1;
         user    = r_win ? r_user : w_user;
         id      = r_win ? r_id   : w_id  ;
         last    = r_win ? r_last : w_last;