exercise.tex

\documentclass{vhdl-assignment}

\title{Exercise}
\date{November 27, 2023}

\begin{document}
\maketitle
\thispagestyle{fancy}

\begin{problem}{ALU}
    Design a simple ALU that can perform 4 instruction :
\begin{verbatim}
    ADD : opcode 0001 : Adds the datapaths to form data_1 + data_2
    SUB : opcode 0010 : Subtracts the datapaths to form data_1 - data_2
    AND : opcode 0011 : Takes the bitwise and of the datapaths data_1 & data_2
    NOT : opcode 0100 : Takes the bitwise Boolean complement of data_1
\end{verbatim}

    The output Zflag is trigger when the output is zero.

    Write testbench and simulate your design.

    \begin{lstlisting}[language=Verilog, numbers=none]
module Arithmetic_Logic_Unit(
    output reg [7:0] ALU_out,
    output ALU_Zflag,
    input [7:0] data_1, data_2,
    input [3:0] opcode);
    
    // your design

endmodule
    \end{lstlisting}
\end{problem}

\begin{problem}{Sequence Detector}
    A Sequence Detector is an FSM that detect a fix pattern in a stream of binary bits that are input to it.    
    \begin{enumerate}
        \item Design a "1011" Sequence Detector. Write testbench and simulate your design.
        \item Design a "110101" Sequence Detector. Write testbench and simulate your design.
    \end{enumerate}

    \begin{lstlisting}[language=Verilog, numbers=none]
module detector (
    input clk
    input rstn
    input in
    ouput out);

    // your design

end module
\end{lstlisting}
\end{problem}

\end{document}