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Assignment_3_solution.tex
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\documentclass{vhdl-assignment}
\usetikzlibrary{circuits.logic.IEC,calc}
\title{Assignment 3 : Structural Model}
\date{October 8, 2023}
\begin{document}
\maketitle
\thispagestyle{fancy}
\begin{problem}{Write testbench for all problems in Assignment 2}
\subsection*{1. Problem 1}
\verilog[Problem 1 testbench]{src/Assignment_1_Problem_1_tb.v}
Notice how the input I is defined to be 5 bits wide (line 2).
This is to prevent the for loop (line 6) looping infinitely.
Because if I is only 4bits, the variable itself never exceed 15.
This is completely optional, alternatively, you can manually break the simulation at a desire time point,
by typing the command "\verb|run 100|" in the transcript command windows (100 is the duration you want to run, change it to suit the simulation)
The above testbench should output something like following:
\begin{lstlisting}[caption=Problems 1 Testbench Output]
# 5 I=00000 F=1
# 10 I=00001 F=1
# 15 I=00010 F=0
# 20 I=00011 F=0
# 25 I=00100 F=1
# 30 I=00101 F=1
# 35 I=00110 F=1
# 40 I=00111 F=1
# 45 I=01000 F=0
# 50 I=01001 F=0
# 55 I=01010 F=0
# 60 I=01011 F=0
# 65 I=01100 F=0
# 70 I=01101 F=0
# 75 I=01110 F=0
# 80 I=01111 F=0
\end{lstlisting}
\subsection*{2. 4-to-1 Multiplexer}
\verilog[4-to-1 Multiplexer testbench]{src/Assignment_1_Problem_2_tb.v}
\begin{lstlisting}[caption=4-to-1 Multiplexer Testbench Output]
# 5 IN0= 1, IN1= 0, IN2= 1, IN3= 0
# 10 S1 = 0, S0 = 0, OUTPUT = 1
# 15 S1 = 0, S0 = 1, OUTPUT = 0
# 20 S1 = 1, S0 = 0, OUTPUT = 1
# 25 S1 = 1, S0 = 1, OUTPUT = 0
\end{lstlisting}
\pagebreak
\subsection*{3. Half Adder}
\verilog[Half Adder testbench]{src/Assignment_1_Problem_3_Half_Adder_tb.v}
\begin{lstlisting}[caption=Half Adder Testbench Output]
# 0 X= 0, Y=0, S= 0, C= 0
# 5 X= 0, Y=1, S= 1, C= 0
# 10 X= 1, Y=0, S= 1, C= 0
# 15 X= 1, Y=1, S= 0, C= 1
\end{lstlisting}
\subsection*{4. Full Adder}
\verilog[Full Adder testbench]{src/Assignment_1_Problem_3_Full_Adder_tb.v}
\begin{lstlisting}[caption=Full Adder Testbench Output]
# 0 X= 0, Y=0, Ci= 0, S= 0, Co= 0
# 5 X= 0, Y=0, Ci= 1, S= 1, Co= 0
# 10 X= 0, Y=1, Ci= 0, S= 1, Co= 0
# 15 X= 0, Y=1, Ci= 1, S= 0, Co= 1
# 20 X= 1, Y=0, Ci= 0, S= 1, Co= 0
# 25 X= 1, Y=0, Ci= 1, S= 0, Co= 1
# 30 X= 1, Y=1, Ci= 0, S= 0, Co= 1
# 35 X= 1, Y=1, Ci= 1, S= 1, Co= 1
\end{lstlisting}
\subsection*{5. 4-bit Ripple Carry Adder}
\verilog[4-bit Ripple Carry Adder testbench]{src/Assignment_1_Problem_3_Ripple_Carry_Adder_tb.v}
\begin{lstlisting}[caption=Full Adder Testbench Output]
# 0 X= 0000, Y=0000, Ci= 0, S= 0000, Co= 0
# 5 X= 0011, Y=0100, Ci= 0, S= 0111, Co= 0
# 10 X= 0010, Y=0101, Ci= 0, S= 0111, Co= 0
# 15 X= 1001, Y=1001, Ci= 0, S= 0010, Co= 1
# 20 X= 1010, Y=1111, Ci= 0, S= 1001, Co= 1
# 25 X= 1010, Y=0101, Ci= 1, S= 0000, Co= 1
\end{lstlisting}
\end{problem}
\newpage
\begin{problem}{8-to-3 Encoder and 3-to-8 Decoder}
\begin{enumerate}
\item Construct truth table.
\item Determine output function.
\item Write Verilog code and testbench for that circuit.
\end{enumerate}
\begin{figure}[H]
\centering
\begin{subfigure}{0.5\textwidth}
\centering
\begin{circuitikz}
\node[decoder_3_to_8] (Decoder0) {Decoder};
\node[left] (i0) at (Decoder0.lpin 1) {$i0$};
\node[left] (i1) at (Decoder0.lpin 2) {$i1$};
\node[left] (i2) at (Decoder0.lpin 3) {$i2$};
\node[right] (y0) at (Decoder0.rpin 1) {$y0$};
\node[right] (y1) at (Decoder0.rpin 2) {$y1$};
\node[right] (y2) at (Decoder0.rpin 3) {$y2$};
\node[right] (y3) at (Decoder0.rpin 4) {$y3$};
\node[right] (y4) at (Decoder0.rpin 5) {$y4$};
\node[right] (y5) at (Decoder0.rpin 6) {$y5$};
\node[right] (y6) at (Decoder0.rpin 7) {$y6$};
\node[right] (y7) at (Decoder0.rpin 8) {$y7$};
\end{circuitikz}
\caption{3-to-8 Decoder}
\end{subfigure}
\begin{subfigure}{0.4\textwidth}
\centering
\begin{circuitikz}
\node[encoder_8_to_3] (Encoder0) {Encoder};
\node[left] (i0) at (Encoder0.lpin 1) {$i0$};
\node[left] (i1) at (Encoder0.lpin 2) {$i1$};
\node[left] (i2) at (Encoder0.lpin 3) {$i2$};
\node[left] (i3) at (Encoder0.lpin 4) {$i3$};
\node[left] (i4) at (Encoder0.lpin 5) {$i4$};
\node[left] (i5) at (Encoder0.lpin 6) {$i5$};
\node[left] (i6) at (Encoder0.lpin 7) {$i6$};
\node[left] (i7) at (Encoder0.lpin 8) {$i7$};
\node[right] (y0) at (Encoder0.rpin 1) {$y0$};
\node[right] (y1) at (Encoder0.rpin 2) {$y1$};
\node[right] (y2) at (Encoder0.rpin 3) {$y2$};
\end{circuitikz}
\caption{8-to-3 Encoder}
\end{subfigure}
\caption{Encoder and Decoder}
\end{figure}
\subsection*{a. Decoder}
\begin{table}[H]
\begin{displaymath}
\begin{array}{c c c|c c c c c c c c}
i0 & i1 & i2 & y0 & y1 & y2 & y3 & y4 & y5 & y6 & y7 \\
\hline
0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\
0 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 \\
0 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 \\
0 & 1 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 \\
1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\
1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 \\
1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 \\
1 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 \\
\end{array}
\end{displaymath}
\caption[short]{Decoder 3-to-8 Truth Table}
\end{table}
\begin{equation*}
\Rightarrow
\begin{cases}
y0=i0'i1'i2' \\
y1=i0'i1'i2 \\
y2=i0'i1i2' \\
y3=i0'i1i2 \\
y4=i0i1'i2' \\
y5=i0i1'i2 \\
y6=i0i1i2' \\
y7=i0i1i2 \\
\end{cases}
\end{equation*}
\verilog[Decoder 3-to-8 and testbench]{src/Decoder_3_to_8.v}
\begin{lstlisting}[caption=Full Adder Testbench Output]
#
#
#
#
#
#
\end{lstlisting}
\subsection*{b. Encoder}
\end{problem}
\newpage
\begin{problem}{Flip-flops : D-FF, T-FF, JK-FF, SR-FF}
\begin{enumerate}
\item Construct truth table.
\item Determine output function.
\item Write Verilog code and testbench for that circuit.
\end{enumerate}
\begin{figure}[H]
\centering
\begin{subfigure}{0.2\textwidth}
\centering
\begin{circuitikz}
\node[D_FF]{};
\end{circuitikz}
\caption{D Flip-flop}
\end{subfigure}
\begin{subfigure}{0.2\textwidth}
\centering
\begin{circuitikz}
\node[T_FF]{};
\end{circuitikz}
\caption{T Flip-flop}
\end{subfigure}
\begin{subfigure}{0.2\textwidth}
\centering
\begin{circuitikz}
\node[SR_FF]{};
\end{circuitikz}
\caption{SR Flip-flop}
\end{subfigure}
\begin{subfigure}{0.2\textwidth}
\centering
\begin{circuitikz}
\node[JK_FF]{};
\end{circuitikz}
\caption{JK Flip-flop}
\end{subfigure}
\caption{Flip-flops}
\end{figure}
\end{problem}
\note{Using structural model. Flip flops include reset signal.}
\end{document}