Assignment_2.tex

\documentclass{vhdl-assignment}

\title{Assignment 2}
\date{25 Sep 2023}

\begin{document}
\maketitle
\thispagestyle{fancy}

\begin{problem}{}
    $F(A,B,C,D)=\sum m(0,2,3,8,9,10,11,12,13,14,15)$
    \begin{enumerate}
        \item Simplify F using Karnaugh Maps.
        \item Construct truth table.
        \item Draw the circuit.
        \item Design a \emph{Structural module} for this circuit (Using Verilog)
    \end{enumerate}
\end{problem}

\begin{problem}{Design a 4-to-1 Multiplexer}
    \begin{enumerate}
        \item Construct truth table.
        \item Determine output function.
        \item Draw the circuit.
        \item Design a \emph{Structural module} for this circuit (Using Verilog)
    \end{enumerate}
\end{problem}

\begin{problem}{Adder Circuit}
    For each of the following circuit, Construct truth table, Determine the output function and Write Verilog code 
    \begin{enumerate}
        \item Half Adder
        \item Full Adder
        \item Ripple Carry 4-bit Adder
        \item Ripple Carry 16-bit Adder
    \end{enumerate}
\end{problem}

\end{document}