diff --git a/.gitmodules b/.gitmodules index 49b0010b133..f4b85e64ae1 100644 --- a/.gitmodules +++ b/.gitmodules @@ -8,8 +8,8 @@ branch = v2.4.3 [submodule "freertos_kernel"] path = freertos_kernel - url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git - branch = V10.2.1-convergence-FreeRTOS-Source + url = https://github.com/sachin0x18/FreeRTOS-Kernel.git + branch = esp32/loadstore_exception_handlers [submodule "pkcs11"] path = libraries/3rdparty/pkcs11 url = https://github.com/amazon-freertos/pkcs11.git diff --git a/freertos_kernel b/freertos_kernel index 82e80521124..175b131abbb 160000 --- a/freertos_kernel +++ b/freertos_kernel @@ -1 +1 @@ -Subproject commit 82e80521124c6e96e5fdb3538a2533f994e2db8f +Subproject commit 175b131abbb46cc63436c23ab22caf13d364bb97 diff --git a/libraries/freertos_plus/standard/crypto/src/iot_crypto.c b/libraries/freertos_plus/standard/crypto/src/iot_crypto.c index e9e1795fc80..3e93e37b72a 100644 --- a/libraries/freertos_plus/standard/crypto/src/iot_crypto.c +++ b/libraries/freertos_plus/standard/crypto/src/iot_crypto.c @@ -256,7 +256,7 @@ void CRYPTO_ConfigureHeap( void ) /* * Ensure that the FreeRTOS heap is used. */ - mbedtls_platform_set_calloc_free( prvCalloc, vPortFree ); /*lint !e534 This function always return 0. */ + //mbedtls_platform_set_calloc_free( prvCalloc, vPortFree ); /*lint !e534 This function always return 0. */ } diff --git a/vendors/espressif/boards/esp32/components/mbedtls/Kconfig b/vendors/espressif/boards/esp32/components/mbedtls/Kconfig index 42c5aeff162..fd03812bf78 100644 --- a/vendors/espressif/boards/esp32/components/mbedtls/Kconfig +++ b/vendors/espressif/boards/esp32/components/mbedtls/Kconfig @@ -32,6 +32,16 @@ config MBEDTLS_DEFAULT_MEM_ALLOC config MBEDTLS_CUSTOM_MEM_ALLOC bool "Custom alloc mode" +config MBEDTLS_IRAM_8BIT_MEM_ALLOC + bool "Internal IRAM" + depends on ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY + help + Allows to use IRAM memory region as 8bit accessible region to store data. + + TLS input and output buffers will be allocated in IRAM section which is 32bit aligned + memory. Every unaligned (8bit or 16bit) access will result in an exception + and incur penalty of certain clock cycles per unaligned read/write. + endchoice #MBEDTLS_MEM_ALLOC_MODE config MBEDTLS_SSL_MAX_CONTENT_LEN diff --git a/vendors/espressif/boards/esp32/components/mbedtls/port/esp_mem.c b/vendors/espressif/boards/esp32/components/mbedtls/port/esp_mem.c index c7b8e706f98..ef9392e25b4 100644 --- a/vendors/espressif/boards/esp32/components/mbedtls/port/esp_mem.c +++ b/vendors/espressif/boards/esp32/components/mbedtls/port/esp_mem.c @@ -25,6 +25,16 @@ IRAM_ATTR void *esp_mbedtls_mem_calloc(size_t n, size_t size) return heap_caps_calloc(n, size, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT); #elif CONFIG_MBEDTLS_EXTERNAL_MEM_ALLOC return heap_caps_calloc(n, size, MALLOC_CAP_SPIRAM|MALLOC_CAP_8BIT); +#elif CONFIG_MBEDTLS_IRAM_8BIT_MEM_ALLOC +#ifdef CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN + if ((n*size) >= CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN || (n*size) >= CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN) { +#else + if ((n*size) >= CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN) { +#endif + return heap_caps_calloc_prefer(n, size, 2, MALLOC_CAP_INTERNAL|MALLOC_CAP_IRAM_8BIT, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT); + } else { + return heap_caps_calloc(n, size, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT); + } #else return calloc(n, size); #endif diff --git a/vendors/espressif/esp-idf/components/esp32/Kconfig b/vendors/espressif/esp-idf/components/esp32/Kconfig index 9245420f5ad..665954ce1a3 100644 --- a/vendors/espressif/esp-idf/components/esp32/Kconfig +++ b/vendors/espressif/esp-idf/components/esp32/Kconfig @@ -1047,6 +1047,17 @@ menu "ESP32-specific" To prevent interrupting DPORT workarounds, need to disable interrupt with a maximum used level in the system. + config ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY + bool "Enable IRAM as 8 bit accessible memory" + depends on FREERTOS_UNICORE + help + If enabled, application can use IRAM as byte accessible region for storing data + (Note: IRAM region cannot be used as task stack) + + This is possible due to handling of exceptions `LoadStoreError (3)` and `LoadStoreAlignmentError (9)` + Each unaligned read/write access will incur a penalty of maximum of 167 CPU cycles. + + endmenu # ESP32-Specific menu Wi-Fi diff --git a/vendors/espressif/esp-idf/components/heap/include/esp_heap_caps.h b/vendors/espressif/esp-idf/components/heap/include/esp_heap_caps.h index 5a7aa6bc2f3..cd645780954 100644 --- a/vendors/espressif/esp-idf/components/heap/include/esp_heap_caps.h +++ b/vendors/espressif/esp-idf/components/heap/include/esp_heap_caps.h @@ -16,6 +16,7 @@ #include #include #include "multi_heap.h" +#include #ifdef __cplusplus extern "C" { @@ -37,6 +38,12 @@ extern "C" { #define MALLOC_CAP_SPIRAM (1<<10) ///< Memory must be in SPI RAM #define MALLOC_CAP_INTERNAL (1<<11) ///< Memory must be internal; specifically it should not disappear when flash/spiram cache is switched off #define MALLOC_CAP_DEFAULT (1<<12) ///< Memory can be returned in a non-capability-specific memory allocation (e.g. malloc(), calloc()) call +#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY +#define MALLOC_CAP_IRAM_8BIT (1<<13) ///< Memory must be in IRAM and allow unaligned access +#else +#define MALLOC_CAP_IRAM_8BIT 0 +#endif + #define MALLOC_CAP_INVALID (1<<31) ///< Memory can't be used / list end marker /** diff --git a/vendors/espressif/esp-idf/components/soc/esp32/soc_memory_layout.c b/vendors/espressif/esp-idf/components/soc/esp32/soc_memory_layout.c index b3adc08b87c..5cf3a6088ed 100644 --- a/vendors/espressif/esp-idf/components/soc/esp32/soc_memory_layout.c +++ b/vendors/espressif/esp-idf/components/soc/esp32/soc_memory_layout.c @@ -45,14 +45,14 @@ const soc_memory_type_desc_t soc_memory_types[] = { //(This DRAM is also the region used by ROM during startup) { "D/IRAM", { 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL|MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }, true, true}, //Type 2: IRAM - { "IRAM", { MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL, 0, 0 }, false, false}, + { "IRAM", { MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL|MALLOC_CAP_IRAM_8BIT, 0, 0 }, false, false}, //Type 3-8: PID 2-7 IRAM - { "PID2IRAM", { MALLOC_CAP_PID2|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, false, false}, - { "PID3IRAM", { MALLOC_CAP_PID3|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, false, false}, - { "PID4IRAM", { MALLOC_CAP_PID4|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, false, false}, - { "PID5IRAM", { MALLOC_CAP_PID5|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, false, false}, - { "PID6IRAM", { MALLOC_CAP_PID6|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, false, false}, - { "PID7IRAM", { MALLOC_CAP_PID7|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, false, false}, + { "PID2IRAM", { MALLOC_CAP_PID2|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_IRAM_8BIT }, false, false}, + { "PID3IRAM", { MALLOC_CAP_PID3|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_IRAM_8BIT }, false, false}, + { "PID4IRAM", { MALLOC_CAP_PID4|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_IRAM_8BIT }, false, false}, + { "PID5IRAM", { MALLOC_CAP_PID5|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_IRAM_8BIT }, false, false}, + { "PID6IRAM", { MALLOC_CAP_PID6|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_IRAM_8BIT }, false, false}, + { "PID7IRAM", { MALLOC_CAP_PID7|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_IRAM_8BIT }, false, false}, //Type 9-14: PID 2-7 DRAM { "PID2DRAM", { MALLOC_CAP_PID2|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false}, { "PID3DRAM", { MALLOC_CAP_PID3|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},