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sensor.accel.3dof.lis3dh.spin2
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{
----------------------------------------------------------------------------------------------------
Filename: sensor.accel.3dof.lis3dh.spin2
Description: Driver for the ST LIS3DH 3DoF accelerometer
Author: Jesse Burt
Started: Mar 15, 2020
Updated: Jan 10, 2025
Copyright (c) 2025 - See end of file for terms of use.
----------------------------------------------------------------------------------------------------
}
#include "sensor.accel.common.spin2h"
CON
{ default I/O configuration - these can be overridden by the parent object }
' I2C
SCL = 0
SDA = 1
I2C_FREQ = 100_000
I2C_ADDR = 0
' SPI
CS = 0
SCK = 1
MOSI = 2
MISO = 3
SPI_FREQ = 1_000_000
' ADC resolution symbols
LOWPOWER = 8
NORMAL = 10
FULL = 12
' XYZ axis constants used throughout the driver
X_AXIS = 0
Y_AXIS = 1
Z_AXIS = 2
' Operating modes (dummy)
STANDBY = 0
MEASURE = 1
' FIFO modes
BYPASS = %00
FIFO = %01
STREAM = %10
STREAM2FIFO = %11
' Interrupt active state
HIGH = 0
LOW = 1
' Constants used for I2C mode only
SLAVE_WR = core.SLAVE_ADDR
SLAVE_RD = core.SLAVE_ADDR|1
I2C_MAX_FREQ = core.I2C_MAX_FREQ
' Indicate to user apps how many Degrees of Freedom each sub-sensor has
' (also imply whether or not it has a particular sensor)
ACCEL_DOF = 3
GYRO_DOF = 0
MAG_DOF = 0
BARO_DOF = 0
DOF = ACCEL_DOF + GYRO_DOF + MAG_DOF + BARO_DOF
' Scales and data rates used during calibration/bias/offset process
CAL_XL_SCL = 2
CAL_G_SCL = 0
CAL_M_SCL = 0
CAL_XL_DR = 400
CAL_G_DR = 0
CAL_M_DR = 0
VAR
long _CS
long _accel_time_res
byte _addr_bits
OBJ
{ SPI? }
#ifdef LIS3DH_SPI
spi: "com.spi.10mhz" ' SPI engine
#else
{ no, not SPI - default to I2C }
#define LIS3DH_I2C
i2c: "com.i2c" ' I2C engine
#endif
core: "core.con.lis3dh"
PUB null()
' This is not a top-level object
#ifdef LIS3DH_SPI
PUB start(): status
' Start the driver using default I/O settings
return startx(CS, SCK, MOSI, MISO)
PUB startx(CS_PIN, SCL_PIN, SDA_PIN, SDO_PIN, SCL_HZ=1_000_000): status
' Start using custom I/O pins
if ( lookdown(CS_PIN: 0..63) and lookdown(SCL_PIN: 0..63) and ...
lookdown(SDA_PIN: 0..63) and lookdown(SDO_PIN: 0..63) )
if ( status := spi.init(SCL_PIN, SDA_PIN, SDO_PIN, core.SPI_MODE, SCL_HZ) )
_CS := CS_PIN
pinh(_CS)
waitms(core.TPOR)
{ if SDA_PIN and SDO_PIN are the same, }
{ assume 3-wire SPI mode is wanted }
if ( SDA_PIN == SDO_PIN )
spi_mode(3)
if ( dev_id() == core.WHO_AM_I_RESP )
return status
' if this point is reached, something above failed
' Re-check I/O pin assignments, bus speed, connections, power
' Lastly - make sure you have at least one free core/cog
return FALSE
#elseifdef LIS3DH_I2C
PUB start(): status
' Start using "standard" Propeller I2C pins, and 100kHz
return startx(SCL, SDA, I2C_FREQ, I2C_ADDR)
PUB startx(SCL_PIN, SDA_PIN, I2C_HZ, ADDR_BITS): status
' Start using custom IO pins and I2C bus frequency
if ( lookdown(SCL_PIN: 0..63) and lookdown(SDA_PIN: 0..63) )
if ( status := i2c.init(SCL_PIN, SDA_PIN, I2C_HZ) )
_addr_bits := (abs(ADDR_BITS <> 0)) << 1
waitms(core.TPOR)
if ( dev_id() == core.WHO_AM_I_RESP )
return status
' if this point is reached, something above failed
' Re-check I/O pin assignments, bus speed, connections, power
' Lastly - make sure you have at least one free core/cog
return FALSE
#endif
PUB stop()
' Stop the driver
#ifdef LIS3DH_SPI
spi.deinit()
#elseifdef LIS3DH_I2C
i2c.deinit()
#endif
PUB defaults()
' Factory defaults
accel_scale(2)
accel_data_rate(0)
accel_axis_ena(%111)
PUB preset_active()
' Like defaults(), but
' * data rate set to 50Hz
accel_scale(2)
accel_data_rate(50)
accel_axis_ena(%111)
PUB preset_clickdet()
' Presets for click-detection
accel_adc_res(12)
accel_scale(4)
accel_data_rate(400)
accel_axis_ena(%111)
click_set_thresh(1_187500)
click_axis_ena(%11_00_00)
click_set_time(127_000)
dbl_click_set_win(637_500)
click_set_latency(150_000)
click_int_ena(TRUE)
PUB preset_freefall()
' Preset settings for free-fall detection
accel_data_rate(400)
accel_scale(2)
freefall_set_time(100_000)
freefall_set_thresh(0_320000)
freefall_axis_ena(%01_01_01) ' all axes low
int1_set_mask(%01000000)
PUB accel_adc_res(adc_res=-2): curr_res | tmp1, tmp2
' Set accelerometer ADC resolution, in bits
' Valid values:
' 8: 8-bit data output, Low-power mode
' 10: 10-bit data output, Normal mode
' 12: 12-bit data output, High-resolution mode
' Any other value polls the chip and returns the current setting
tmp1 := readreg(core.CTRL_REG1)
tmp2 := readreg(core.CTRL_REG4)
case adc_res
8:
tmp1 &= core.LPEN_MASK
tmp2 &= core.HR_MASK
tmp1 := (tmp1 | (1 << core.LPEN))
10:
tmp1 &= core.LPEN_MASK
tmp2 &= core.HR_MASK
12:
tmp1 &= core.LPEN_MASK
tmp2 &= core.HR_MASK
tmp2 := (tmp2 | (1 << core.HR))
other:
tmp1 := (tmp1 >> core.LPEN) & 1
tmp2 := (tmp2 >> core.HR) & 1
tmp1 := (tmp1 << 1) | tmp2
return lookupz(tmp1: 10, 12, 8)
writereg(core.CTRL_REG1, tmp1)
writereg(core.CTRL_REG4, tmp2)
PUB accel_axis_ena(mask=-2): c
' Enable data output for Accelerometer - per axis
' Valid values: 0 or 1, for each axis:
' Bits 210
' XYZ
' Any other value polls the chip and returns the current setting
c := readreg(core.CTRL_REG1)
case mask
%000..%111:
writereg(core.CTRL_REG1, ( (c & core.XYZEN_MASK) | (mask >< 3) ) )
other:
return c & core.XYZEN_BITS
PUB accel_bias(x, y, z)
' Read accelerometer calibration offset values
' x, y, z: pointers to copy offsets to
long[x] := _abias[X_AXIS]
long[y] := _abias[Y_AXIS]
long[z] := _abias[Z_AXIS]
PUB accel_data(ptr_x, ptr_y, ptr_z) | byte cmd_pkt[2], tmp[2]
' Read the accelerometer output registers
#ifdef LIS3DH_SPI
outa[_CS] := 0
spi.wr_byte(core.OUT_X_L | core.READ_BIT | core.MS_SPI)
spi.rdblock_lsbf(@tmp, 6)
outa[_CS] := 1
#elseifdef LIS3DH_I2C
cmd_pkt[0] := (SLAVE_WR | _addr_bits)
cmd_pkt[1] := core.OUT_X_L | core.MS_I2C
tmp[0] := tmp[1] := 0
i2c.start() ' S
i2c.wrblock_lsbf(@cmd_pkt, 2) ' W [SL|W] [REG]
i2c.start() ' Rs
i2c.wr_byte(SLAVE_RD | _addr_bits) ' W [SL|R]
i2c.rdblock_lsbf(@tmp, 6, i2c.NAK) ' R ... (send NAK after last byte)
i2c.stop() ' P
#endif
long[ptr_x] := (tmp.word[X_AXIS] signx 15) - _abias[X_AXIS]
long[ptr_y] := (tmp.word[Y_AXIS] signx 15) - _abias[X_AXIS]
long[ptr_z] := (tmp.word[Z_AXIS] signx 15) - _abias[X_AXIS]
PUB accel_data_overrun(): f
' Flag indicating previously acquired data has been overwritten
' Returns:
' Bits 3210 (decimal val):
' 3 (8): X, Y, and Z-axis data overrun
' 2 (4): Z-axis data overrun
' 1 (2): Y-axis data overrun
' 0 (1): X-axis data overrun
' Returns 0 otherwise
return ( (readreg(core.STATUS_REG) >> core.X_OR) & %1111 )
PUB accel_data_rate(rate=-2): c
' Set accelerometer output data rate, in Hz
' Valid values: See case table below
' Any other value polls the chip and returns the current setting
' NOTE: A value of 0 powers down the device
c := readreg(core.CTRL_REG1)
case rate
0, 1, 10, 25, 50, 100, 200, 400, 1344, 1600:
_accel_time_res := (1_000000 / rate)' calc timescale needed for some other functions
{ map rate in Hz to bitfield }
rate := lookdownz(rate: 0, 1, 10, 25, 50, 100, 200, 400, 1344, 1600) << core.ODR
writereg(core.CTRL_REG1, ((c & core.ODR_MASK) | rate) )
other:
c := (c >> core.ODR) & core.ODR_BITS
return lookupz(c: 0, 1, 10, 25, 50, 100, 200, 400, 1344, 1600)
PUB accel_data_rdy(): f
' Flagt indicating data is ready
' Returns: TRUE (-1) if data ready, FALSE otherwise
return ( ( (readreg(core.STATUS_REG) >> core.ZYXDA) & 1) == 1)
PUB accel_int(): s
' Read interrupt state
' Bit 6543210 (For each bit, 0: No interrupt, 1: Interrupt has been generated)
' 6: One or more interrupts have been generated
' 5: Z-axis high event
' 4: Z-axis low event
' 3: Y-axis high event
' 2: Y-axis low event
' 1: X-axis high event
' 0: X-axis low event
return readreg(core.INT1_SRC)
PUB accel_int_mask(): m
' Get interrupt mask
' Bits: 7..0
' 7: AND (1)/OR (0) combination of interrupts
' 6: 6-direction detection
' 5: Z-axis high event
' 4: Z-axis low event
' 3: Y-axis high event
' 2: Y-axis low event
' 1: X-axis high event
' 0: X-axis low event
return readreg(core.INT1_CFG)
PUB accel_int_polarity(state=-2): c
' Set interrupt pin active state/logic level
' Valid values: LOW (0), HIGH (1)
' Any other value polls the chip and returns the current setting
' NOTE: This affects INT1 and INT2 pins
c := readreg(core.CTRL_REG6)
case state
LOW, HIGH:
writereg(core.CTRL_REG6, ((c & core.INT_POL_MASK) | (state << core.INT_POL) ) )
other:
return ((c >> core.INT_POL) & 1)
PUB accel_int_set_mask(mask)
' Set interrupt mask
' Bits: 7..0
' 7: AND (1)/OR (0) combination of interrupts
' 6: 6-direction detection
' 5: Z-axis high event
' 4: Z-axis low event
' 3: Y-axis high event
' 2: Y-axis low event
' 1: X-axis high event
' 0: X-axis low event
' Valid values: %0000_0000..%1111_1111 (other bits masked off)
writereg(core.INT1_CFG, (mask & %1111_1111) )
PUB accel_int_thresh(): thresh | scl_fact
' Get interrupt threshold
' Returns: micro-g's
case accel_scale()
2: scl_fact := 16_000
4: scl_fact := 32_000
8: scl_fact := 62_000
16: scl_fact := 186_000 ' set scale factor for reg
return (readreg(core.INT1_THS) * scl_fact) ' scale to micro-g's
PUB accel_int_set_thresh(thresh) | scl_fact
' Set interrupt threshold, in micro-g's
' Valid values: 0..16_000000
case accel_scale()
2: scl_fact := 16_000
4: scl_fact := 32_000
8: scl_fact := 62_000
16: scl_fact := 186_000 ' set scale factor for reg
{ 0..16g's input; scale down to register range }
writereg(core.INT1_THS, ( (0 #> thresh <# 16_000000) / scl_fact) )
PUB accel_scale(scale=-2): c
' Set measurement range of the accelerometer, in g's
' Valid values: 2, 4, 8, 16
' Any other value polls the chip and returns the current setting
c := readreg(core.CTRL_REG4)
case scale
2, 4, 8, 16:
scale := lookdownz(scale: 2, 4, 8, 16)
_ares := lookupz(scale: 61, 122, 244, 732)
writereg(core.CTRL_REG4, ( (c & core.FS_MASK) | (scale << core.FS) ) )
other:
c := (c >> core.FS) & core.FS_BITS
return lookupz(c: 2, 4, 8, 16)
PUB accel_set_bias(x, y, z)
' Write accelerometer calibration offset values
' Valid values:
' -32768..32767
_abias[X_AXIS] := -32768 #> x <# 32767
_abias[Y_AXIS] := -32768 #> y <# 32767
_abias[Z_AXIS] := -32768 #> z <# 32767
PUB click_axis_ena(mask=-2): c
' Enable click detection per axis, and per click type
' Valid values:
' Bits: 5..0
' [5..4]: Z-axis double-click..single-click
' [3..2]: Y-axis double-click..single-click
' [1..0]: X-axis double-click..single-click
' Any other value polls the chip and returns the current setting
case mask
%000000..%111111:
writereg(core.CLICK_CFG, mask)
other:
return readreg(core.CLICK_CFG)
PUB clicked(): f
' Flag indicating the sensor was single or double-clicked
' Returns: TRUE (-1) if sensor was single-clicked or double-clicked
' FALSE (0) otherwise
return ( (clicked_int() & core.CLICKED_BITS) <> 0 )
PUB clicked_int(): s
' Clicked interrupt status
' Bits: 6..0
' 6: Interrupt active
' 5: Double-clicked
' 4: Single-clicked
' 3: Click sign (0: positive, 1: negative)
' 2: Z-axis clicked
' 1: Y-axis clicked
' 0: X-axis clicked
return readreg(core.CLICK_SRC)
PUB click_int_ena(state=-2): c
' Enable click interrupts on INT1
' Valid values: TRUE (-1 or 1), FALSE (0)
' Any other value polls the chip and returns the current setting
c := readreg(core.CTRL_REG3)
case abs(state)
0, 1:
writereg(core.CTRL_REG3, ((c & core.I1_CLICK_MASK) | (abs(state) << core.I1_CLICK) ) )
other:
return ( (c >> core.I1_CLICK) == 1 )
PUB click_latency(): l
' Get maximum elapsed interval between start of click and end of click
' Returns: microseconds
return (readreg(core.TIME_LATENCY) * _accel_time_res)
PUB click_set_latency(ltime)
' Set maximum elapsed interval between start of click and end of click, in uSec
' (i.e., time from set click_thresh() exceeded to falls back below threshold)
' Valid values:
' accel_data_rate Min time (uS, also step size) Max time (uS) (equiv. range in mS)
' 1 1_000_000 .. 255_000_000 1,000 .. 255,000
' 10 100_000 .. 25_500_000 100 .. 25,500
' 25 40_000 .. 10_200_000 40.0 .. 10,200
' 50 20_000 .. 5_100_000 20.0 .. 5,100
' 100 10_000 .. 2_550_000 10.0 .. 2,550
' 200 5_000 .. 1_275_000 5.0 .. 1,275
' 400 2_500 .. 637_500 2.5 .. 637.5
' 1344 744 .. 189_732 0.744 .. 189.732
' 1600 625 .. 159_375 0.625 .. 159.375
' NOTE: Minimum unit is dependent on the current accel_data_rate()
' NOTE: ST application note example uses accel_data_rate(400)
writereg(core.TIME_LATENCY, ( (0 #> ltime <# (_accel_time_res * 255) ) / _accel_time_res) )
PUB click_thresh(): t | ares
' Get threshold for recognizing a click
' Returns: micro-g's
' res. = scale / 128
return ( readreg(core.CLICK_THS) * ( (accel_scale() * 1_000000) / 128) )
PUB click_set_thresh(thresh) | ares
' Set threshold for recognizing a click, in micro-g's
' Valid values:
' accel_scale() Max thresh
' 2 1_984375 (= 1.984375g)
' 4 3_968750 (= 3.968750g)
' 8 7_937500 (= 7.937500g)
' 16 15_875000 (= 15.875000g)
' NOTE: Each LSB = (accel_scale()/128) * 1M (e.g., 4g scale lsb=31250ug = 0_031250ug = 0.03125g)
ares := (accel_scale() * 1_000000) / 128 ' res. = scale / 128
writereg(core.CLICK_THS, ( (0 #> thresh <# (127 * ares) ) / ares) )
PUB click_time(): t
' Get maximum elapsed interval between start of click and end of click
' Returns: microseconds
return (readreg(core.TIME_LIMIT) * _accel_time_res)
PUB click_set_time(ctime)
' Set maximum elapsed interval between start of click and end of click, in uSec
' (i.e., time from set click_set_thresh() exceeded to falls back below threshold)
' Valid values:
' AccelDataRate: Min time (uS, also step size) Max time (uS) (equiv. mS)
' 1 1_000_000 .. 127_000_000 127,000
' 10 100_000 .. 12_700_000 12,700
' 25 40_000 .. 5_080_000 5,080
' 50 20_000 .. 2_540_000 2,540
' 100 10_000 .. 1_270_000 1,127
' 200 5_000 .. 635_000 635
' 400 2_500 .. 317_500 317
' 1344 744 .. 94_494 94
' 1600 625 .. 79_375 79
' NOTE: Minimum unit is dependent on the current accel_data_rate()
' NOTE: ST application note example uses accel_data_rate(400)
writereg(core.TIME_LIMIT, ( (0 #> ctime <# (_accel_time_res * 127) ) / _accel_time_res) )
PUB dev_id(): id
' Read device identification
' Returns: $33
return readreg(core.WHO_AM_I)
PUB dbl_click_win(): d
' Get maximum elapsed interval between two consecutive clicks
' Returns: microseconds
return (readreg(core.TIME_WINDOW) * _accel_time_res)
PUB dbl_click_set_win(dctime)
' Set maximum elapsed interval between two consecutive clicks, in microseconds
' Valid values:
' accel_data_rate() Min time (uS/step size) Max time (uS) (equiv. range in mS)
' 1 1_000_000 255_000_000 1,000 .. 255,000
' 10 100_000 25_500_000 100 .. 25,500
' 25 40_000 10_200_000 40.0 .. 10,200
' 50 20_000 5_100_000 20.0 .. 5,100
' 100 10_000 2_550_000 10.0 .. 2,550
' 200 5_000 1_275_000 5.0 .. 1,275
' 400 2_500 637_500 2.5 .. 637.5
' 1344 744 189_732 0.744 .. 189.732
' 1600 625 159_375 0.625 .. 159.375
' NOTE: Minimum unit is dependent on the current output data rate set with accel_data_rate()
' NOTE: ST application note example uses 400
writereg(core.TIME_WINDOW, ( (0 #> dctime <# (_accel_time_res * 255) ) / _accel_time_res) )
PUB fifo_ena(state=-2): c
' Enable FIFO memory
' Valid values: FALSE (0), TRUE(1 or -1)
' Any other value polls the chip and returns the current setting
c := readreg(core.CTRL_REG5)
case abs(state)
0, 1:
writereg(core.CTRL_REG5, ((c & core.FIFO_EN_MASK) | (abs(state) << core.FIFO_EN) ) )
other:
return ( ( (c >> core.FIFO_EN) & 1) == 1)
PUB fifo_empty(): f
' Flag indicating FIFO is empty
' Returns: FALSE (0): FIFO contains at least one sample, TRUE(-1): FIFO is empty
return ( ( (readreg(core.FIFO_SRC_REG) >> core.EMPTY) & 1) == 1)
PUB fifo_full(): f
' Flag indicating FIFO is full
' Returns: FALSE (0): FIFO contains less than 32 samples, TRUE(-1): FIFO contains 32 samples
return ( ( (readreg(core.FIFO_SRC_REG) >> core.OVRN_FIFO) & 1) == 1)
PUB fifo_mode(mode=-2): c
' Set FIFO behavior
' Valid values:
' BYPASS (%00) - Bypass mode - FIFO off
' FIFO (%01) - FIFO mode
' STREAM (%10) - Stream mode
' STREAM2FIFO (%11) - Stream-to-FIFO mode
' Any other value polls the chip and returns the current setting
c := readreg(core.FIFO_CTRL_REG)
case mode
BYPASS, FIFO, STREAM, STREAM2FIFO:
writereg(core.FIFO_CTRL_REG, ((c & core.FM_MASK) | (mode << core.FM) ) )
other:
return ((c >> core.FM) & core.FM_BITS)
PUB fifo_thresh(thresh=-2): c
' Set FIFO threshold level
' Valid values: 1..32
' Any other value polls the chip and returns the current setting
c := readreg(core.FIFO_CTRL_REG)
case thresh
1..32:
writereg(core.FIFO_CTRL_REG, ( (c & core.FTH_MASK) | (thresh-1) ) )
other:
return ((c & core.FTH) + 1)
PUB fifo_nr_unread(): n
' Number of unread samples stored in FIFO
' Returns: 0..32
return readreg(core.FIFO_SRC_REG) & core.FSS_BITS
PUB freefall_axis_ena(mask)
' Enable free-fall detection, per axis mask
' Valid values: %000000..%111111
' Bits 5..0:
' 5: Z-axis high event
' 4: Z-axis low event
' 3: Y-axis high event
' 2: Y-axis low event
' 1: X-axis high event
' 0: X-axis low event
accel_int_set_mask(core.FFALL | mask) ' set AOI bit for free-fall det
PUB freefall_thresh(): t
' Get free-fall threshold
' Returns: micro-g's
return accel_int_thresh()
PUB freefall_set_thresh(thresh)
' Set free-fall threshold, in micro-g's
' Valid values: 0..8_001000 (0..8g's; clamped to range)
accel_int_set_thresh(thresh)
PUB freefall_time(): t
' Get minimum time duration required to recognize free-fall
' Returns: microseconds
return int1_duration()
PUB freefall_set_time(fftime)
' Set minimum time duration required to recognize free-fall, in microseconds
' Valid values: 0..maximum in table below (dependent on accel_data_rate())
' accel_data_rate() Step Max
' 1 1_000_000 127_000_000
' 10 100_000 12_700_000
' 25 40_000 5_080_000
' 50 20_000 2_540_000
' 100 10_000 1_270_000
' 200 5_000 635_000
' 400 2_500 317_500
' 1600 625 79_375
' 1344 744 94_494
' 5376 186 23_623
int1_set_duration(fftime)
PUB int_polarity(p): cp
' Set INT1/INT2 polarity/active state
' p:
' ACTIVE_HIGH (0): active-high on interrupt
' ACTIVE_LOW (1): active-low on interrupt
cp := readreg(core.CTRL_REG6)
case p
ACTIVE_HIGH, ACTIVE_LOW:
p := (cp & core.INT_POL_MASK) | (p << core.INT_POL)
writereg(core.CTRL_REG6, p)
other:
return (cp >> core.INT_POL) & 1
PUB int1_duration(): d
' Get currently set duration a condition must be true in order to assert an interrupt
' read and convert to usec
return (readreg(core.INT1_DUR) * _accel_time_res)
PUB int1_set_duration(dur)
' Set duration a condition must be true in order to assert an interrupt
' Valid values:
' accel_data_rate() Step Max
' 1 1_000_000 127_000_000
' 10 100_000 12_700_000
' 25 40_000 5_080_000
' 50 20_000 2_540_000
' 100 10_000 1_270_000
' 200 5_000 635_000
' 400 2_500 317_500
' 1600 625 79_375
' 1344 744 94_494
' 5376 186 23_623
' Any other value polls the chip and returns the current setting
writereg(core.INT1_DUR, ( (0 #> dur <# (_accel_time_res * 127)) / _accel_time_res) )
PUB int1_latch_ena(state=-2): c
' Latch interrupts on INT1 pin
' Valid values: TRUE (-1 or 1), FALSE (0)
' Any other value polls the chip and returns the current setting
c := readreg(core.CTRL_REG5)
case abs(state)
0, 1:
writereg(core.CTRL_REG5, ((c & core.LIR_INT1_MASK) | (abs(state) << core.LIR_INT1) ) )
other:
return ( ( (c >> core.LIR_INT1) & 1) == 1)
PUB int1_mask(): m
' Get INT1 mask
' Bit 7654321 (0 disables an interrupt, 1 enables)
' 7: Click
' 6: IA1
' 5: IA2
' 4: XYZ Data available
' 3: 321 Data available
' 2: FIFO watermark
' 1: FIFO overrun
' 0: -- unused/ignored --
return readreg(core.CTRL_REG3)
PUB int1_set_mask(mask)
' Set INT1 mask
' Bit 7654321 (0 disables an interrupt, 1 enables)
' 7: Click
' 6: IA1
' 5: IA2
' 4: XYZ Data available
' 3: 321 Data available
' 2: FIFO watermark
' 1: FIFO overrun
' 0: -- unused/ignored --
writereg(core.CTRL_REG3, (mask & core.CTRL_REG3_MASK) )
PUB int2_duration(): d
' Get currently set duration a condition must be true in order to assert an interrupt
' read and convert to usec
return (readreg(core.INT2_DUR) * _accel_time_res)
PUB int2_set_duration(dur)
' Set duration a condition must be true in order to assert an interrupt
' Valid values:
' accel_data_rate() Step Max
' 1 1_000_000 127_000_000
' 10 100_000 12_700_000
' 25 40_000 5_080_000
' 50 20_000 2_540_000
' 100 10_000 1_270_000
' 200 5_000 635_000
' 400 2_500 317_500
' 1600 625 79_375
' 1344 744 94_494
' 5376 186 23_623
' Any other value polls the chip and returns the current setting
writereg(core.INT2_DUR, ( (0 #> dur <# (_accel_time_res * 127)) / _accel_time_res) )
PUB int2_latch_ena(state=-2): c
' Latch interrupts on INT2 pin
' Valid values: TRUE (-1 or 1), FALSE (0)
' Any other value polls the chip and returns the current setting
c := readreg(core.CTRL_REG5)
case abs(state)
0, 1:
writereg(core.CTRL_REG5, ((c & core.LIR_INT2_MASK) | (abs(state) << core.LIR_INT2) ) )
other:
return ( ( (c >> core.LIR_INT2) & 1) == 1)
PUB int2_mask(): m
' Get INT2 mask
' Bit 7654321 (0 disables an interrupt, 1 enables)
' 7: Click
' 6: IA1
' 5: IA2
' 4: XYZ Data available
' 3: 321 Data available
' 2: FIFO watermark
' 1: FIFO overrun
' 0: -- unused/ignored --
return readreg(core.CTRL_REG6)
PUB int2_set_mask(mask)
' Set INT2 mask
' Bit 7654321 (0 disables an interrupt, 1 enables)
' 7: Click
' 6: IA1
' 5: IA2
' 4: Boot
' 3: Activity
' 2: unused/ignored
' 1: unused/ignored
' 0: unused/ignored
writereg(core.CTRL_REG6, (mask & core.CTRL_REG6_INTMASK) )
PRI readreg(reg_nr): v | byte cmd_pkt[2]
' Read nr_bytes from slave device into ptr_buff
case reg_nr
$07..$0D, $0F, $1E..$27, $2E..$3F:
other:
return
v := 0
#ifdef LIS3DH_SPI
reg_nr |= core.READ_BIT
pinl(_CS)
spi.wr_byte(reg_nr)
spi.rdblock_lsbf(@v, 1)
pinh(_CS)
#elseifdef LIS3DH_I2C
cmd_pkt[0] := (SLAVE_WR | _addr_bits)
cmd_pkt[1] := reg_nr
i2c.start() ' S
i2c.wrblock_lsbf(@cmd_pkt, 2) ' W [SL|W] [REG]
i2c.start() ' Rs
i2c.wr_byte(SLAVE_RD | _addr_bits) ' W [SL|R]
i2c.rdblock_lsbf(@v, 1, i2c.NAK) ' R ... (send NAK after last byte)
i2c.stop() ' P
#endif
PRI spi_mode(mode) | tmp
' Set SPI interface to 3 or 4-wire mode
if (mode == 3)
tmp := core.SPI_3W
elseif (mode == 4)
tmp := 0
writereg(core.CTRL_REG4, tmp)
PRI writereg(reg_nr, val) | byte cmd_pkt[2]
' Write nr_bytes from ptr_buff to slave device
case reg_nr
$1E..$26, $2E, $30, $32..$34, $36..$38, $3A..$3F:
other:
return
#ifdef LIS3DH_SPI
pinl(_CS)
spi.wr_byte(reg_nr)
spi.wrblock_lsbf(@val, 1)
pinh(_CS)
#elseifdef LIS3DH_I2C
cmd_pkt[0] := (SLAVE_WR | _addr_bits)
cmd_pkt[1] := reg_nr
i2c.start()
i2c.wrblock_lsbf(@cmd_pkt, 2)
i2c.wrblock_lsbf(@val, 1)
i2c.stop()
#endif
DAT
{
Copyright 2025 Jesse Burt
Permission is hereby granted, free of charge, to any person obtaining a copy of this software and
associated documentation files (the "Software"), to deal in the Software without restriction,
including without limitation the rights to use, copy, modify, merge, publish, distribute,
sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all copies or
substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT
NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
}