diff --git a/design/JNW_SIGMA_DELTA_A2D_SKY130A/JNW_SIGMA_DELTA_A2D.sch b/design/JNW_SIGMA_DELTA_A2D_SKY130A/JNW_SIGMA_DELTA_A2D.sch index a530e93..671fe60 100644 --- a/design/JNW_SIGMA_DELTA_A2D_SKY130A/JNW_SIGMA_DELTA_A2D.sch +++ b/design/JNW_SIGMA_DELTA_A2D_SKY130A/JNW_SIGMA_DELTA_A2D.sch @@ -1,20 +1,436 @@ -v {xschem version=3.0.0 file_version=1.2 } +v {xschem version=3.4.6RC file_version=1.2 +} G {} K {} V {} S {} E {} -T {Shift-I Insert new component -Shift-Z Zoom in -Ctrl-Z Zoom out -R Rotate -F Full view - -Manual: https://xschem.sourceforge.io/stefan/xschem_man/xschem_man.pdf -} -460 -630 0 0 0.6 0.6 {} -C {cborder/border_s.sym} 520 0 0 0 { -user="wulff" -company="wulff"} -C {devices/ipin.sym} -560 -840 0 0 {name=p1 lab=VDD_1V8} -C {devices/ipin.sym} -560 30 0 0 {name=p2 lab=VSS} -C {devices/ipin.sym} -560 -440 0 0 {name=p3 lab=PWRUP_1V8} +N -340 -600 -280 -600 {lab=IN} +N -270 -680 -270 -640 {lab=VSS} +N -250 -680 -250 -640 {lab=p1} +N -280 -470 -240 -470 {lab=VSS} +N -280 -490 -240 -490 {lab=p2} +N -200 -600 -200 -520 {lab=#net1} +N -220 -600 -200 -600 {lab=#net1} +N -60 -490 -20 -490 {lab=p1} +N 20 -600 20 -520 {lab=#net2} +N -200 -600 -120 -600 {lab=#net1} +N -60 -600 20 -600 {lab=#net2} +N 70 -680 70 -640 {lab=p2} +N 100 -600 120 -600 {lab=#net3} +N 20 -600 40 -600 {lab=#net2} +N 180 -560 200 -560 {lab=VMID} +N 180 -560 180 -530 {lab=VMID} +N 240 -550 240 -530 {lab=VSS} +N 120 -600 200 -600 {lab=#net3} +N 150 -680 210 -680 {lab=#net3} +N 150 -680 150 -600 {lab=#net3} +N 270 -680 340 -680 {lab=vo1} +N 340 -680 340 -610 {lab=vo1} +N 240 -630 240 -610 {lab=vo1} +N 240 -630 340 -630 {lab=vo1} +N 340 -610 340 -600 {lab=vo1} +N 340 -600 410 -600 {lab=vo1} +N 410 -600 470 -600 {lab=vo1} +N 480 -680 480 -640 {lab=VSS} +N 500 -680 500 -640 {lab=p2} +N 470 -490 510 -490 {lab=p1} +N 550 -600 550 -520 {lab=#net4} +N 530 -600 550 -600 {lab=#net4} +N 690 -490 730 -490 {lab=p2} +N 770 -600 770 -520 {lab=#net5} +N 550 -600 630 -600 {lab=#net4} +N 690 -600 770 -600 {lab=#net5} +N 770 -460 770 -450 {lab=VMID} +N 800 -680 800 -640 {lab=VSS} +N 820 -680 820 -640 {lab=p1} +N 850 -600 870 -600 {lab=#net6} +N 770 -600 790 -600 {lab=#net5} +N 930 -560 950 -560 {lab=VMID} +N 930 -560 930 -530 {lab=VMID} +N 990 -550 990 -530 {lab=VSS} +N 990 -530 990 -500 {lab=VSS} +N 990 -500 990 -470 {lab=VSS} +N 870 -600 950 -600 {lab=#net6} +N 900 -680 960 -680 {lab=#net6} +N 900 -680 900 -600 {lab=#net6} +N 1020 -680 1090 -680 {lab=#net7} +N 1090 -680 1090 -610 {lab=#net7} +N 990 -630 990 -610 {lab=#net7} +N 990 -630 1090 -630 {lab=#net7} +N 1090 -610 1090 -600 {lab=#net7} +N 1090 -600 1160 -600 {lab=#net7} +N 1190 -680 1190 -640 {lab=p1} +N 1220 -600 1240 -600 {lab=vo2} +N 1270 -600 1270 -570 {lab=vo2} +N 1240 -600 1270 -600 {lab=vo2} +N -280 -470 -280 -400 {lab=VSS} +N -40 -470 -40 -400 {lab=VSS} +N -40 -470 -20 -470 {lab=VSS} +N 240 -530 240 -400 {lab=VSS} +N 240 -400 680 -400 {lab=VSS} +N 710 -470 710 -400 {lab=VSS} +N 710 -470 730 -470 {lab=VSS} +N 490 -470 490 -400 {lab=VSS} +N 490 -470 510 -470 {lab=VSS} +N 990 -470 990 -400 {lab=VSS} +N 1270 -510 1270 -400 {lab=VSS} +N 990 -400 1270 -400 {lab=VSS} +N 550 -460 550 -320 {lab=#net8} +N 1440 -510 1440 -400 {lab=VSS} +N 1270 -400 1440 -400 {lab=VSS} +N 1440 -600 1440 -570 {lab=vcmp} +N 1440 -600 1770 -600 {lab=vcmp} +N 1730 -540 1770 -540 {lab=p2} +N 1440 -400 1830 -400 {lab=VSS} +N 1830 -510 1830 -400 {lab=VSS} +N 1800 -510 1800 -490 {lab=resb} +N 1770 -490 1800 -490 {lab=resb} +N 1730 -490 1770 -490 {lab=resb} +N 1870 -600 2030 -600 {lab=q} +N 550 -320 550 -270 {lab=#net8} +N 210 -130 260 -130 {lab=p1} +N 150 -100 150 -60 {lab=VSS} +N 150 -260 150 -220 {lab=VDD_1V8} +N 730 140 730 190 {lab=#net9} +N 1830 -680 1830 -640 {lab=VDD_1V8} +N 1830 -640 1830 -630 {lab=VDD_1V8} +N -320 -400 -280 -400 {lab=VSS} +N -340 -400 -320 -400 {lab=VSS} +N 240 -820 240 -780 {lab=res} +N 270 -740 290 -740 {lab=vo1} +N 190 -740 210 -740 {lab=#net3} +N 150 -740 190 -740 {lab=#net3} +N 150 -740 150 -680 {lab=#net3} +N 290 -740 340 -740 {lab=vo1} +N 340 -740 340 -680 {lab=vo1} +N 220 -790 220 -780 {lab=VSS} +N 990 -820 990 -780 {lab=res} +N 1020 -740 1040 -740 {lab=#net7} +N 940 -740 960 -740 {lab=#net6} +N 900 -740 940 -740 {lab=#net6} +N 900 -740 900 -680 {lab=#net6} +N 1040 -740 1090 -740 {lab=#net7} +N 1090 -740 1090 -680 {lab=#net7} +N 970 -790 970 -780 {lab=VSS} +N 1140 -90 1140 -40 {lab=VSS} +N 730 250 730 300 {lab=VSS} +N 1220 -150 1220 -40 {lab=VSS} +N 1220 -280 1220 -240 {lab=VDD_1V8} +N 1220 -240 1220 -230 {lab=VDD_1V8} +N 1140 -190 1180 -190 {lab=resb} +N 1260 -190 1310 -190 {lab=res} +N 1140 -190 1140 -150 {lab=resb} +N 720 -190 760 -190 {lab=q} +N 680 -160 680 -150 {lab=VH} +N 680 -150 680 -120 {lab=VH} +N 680 -120 680 -100 {lab=VH} +N 680 -240 680 -220 {lab=#net8} +N 550 -240 680 -240 {lab=#net8} +N 550 -270 550 -240 {lab=#net8} +N 590 -120 630 -120 {lab=qn} +N 550 -90 550 -80 {lab=VL} +N 550 -80 550 -50 {lab=VL} +N 550 -50 550 -30 {lab=VL} +N 550 -170 550 -150 {lab=#net8} +N 550 -240 550 -170 {lab=#net8} +N 720 -170 760 -170 {lab=VSS} +N 590 -100 630 -100 {lab=VSS} +N 680 -100 680 -30 {lab=VH} +N 1870 -540 2030 -540 {lab=qn} +N 210 -190 250 -190 {lab=q} +N -200 -460 -200 -320 {lab=#net10} +N -30 -190 10 -190 {lab=q2} +N -70 -160 -70 -150 {lab=VH} +N -70 -240 -70 -220 {lab=#net10} +N -200 -240 -70 -240 {lab=#net10} +N -160 -130 -120 -130 {lab=q2n} +N -200 -100 -200 -90 {lab=VL} +N -200 -80 -200 -50 {lab=VL} +N -200 -50 -200 -30 {lab=VL} +N -200 -170 -200 -150 {lab=#net10} +N -200 -240 -200 -170 {lab=#net10} +N -30 -170 10 -170 {lab=VSS} +N -160 -110 -120 -110 {lab=VSS} +N -70 -100 -70 -30 {lab=VH} +N 10 -190 110 -190 {lab=q2} +N -120 -130 -10 -130 {lab=q2n} +N -10 -130 110 -130 {lab=q2n} +N -70 -150 -70 -100 {lab=VH} +N -200 -90 -200 -80 {lab=VL} +N -200 -320 -200 -240 {lab=#net10} +N 180 -100 180 -90 {lab=resb} +N 180 -80 180 -50 {lab=resb} +N 180 -50 180 -30 {lab=resb} +N 180 -90 180 -80 {lab=resb} +N -280 -400 -40 -400 {lab=VSS} +N -40 -400 240 -400 {lab=VSS} +N 180 -530 180 -370 {lab=VMID} +N 770 -450 770 -370 {lab=VMID} +N 680 -400 710 -400 {lab=VSS} +N 710 -400 990 -400 {lab=VSS} +N 180 -370 770 -370 {lab=VMID} +N 930 -530 930 -370 {lab=VMID} +N 770 -370 930 -370 {lab=VMID} +N 20 -460 20 -370 {lab=VMID} +N 20 -370 180 -370 {lab=VMID} +N 1490 -250 1490 -200 {lab=VSS} +N 1490 -360 1490 -310 {lab=VMID} +N 1600 -250 1600 -200 {lab=VSS} +N 1600 -360 1600 -310 {lab=VH} +N 1700 -250 1700 -200 {lab=VSS} +N 1700 -360 1700 -310 {lab=VL} +N 150 -60 150 -30 {lab=VSS} +N 1170 -680 1170 -640 {lab=VSS} +N 50 -680 50 -640 {lab=VSS} +N 970 -820 970 -790 {lab=VSS} +N 220 -820 220 -790 {lab=VSS} +N 1050 290 1240 290 {lab=#net11} +N 1050 110 1050 290 {lab=#net11} +N 1050 110 1070 110 {lab=#net11} +N 1010 110 1050 110 {lab=#net11} +N 1150 110 1240 110 {lab=#net12} +N 1500 120 1520 120 {lab=p1e} +N 1460 120 1500 120 {lab=p1e} +N 1500 280 1520 280 {lab=p2e} +N 1460 280 1500 280 {lab=p2e} +N 1330 120 1380 120 {lab=#net13} +N 1330 280 1380 280 {lab=#net14} +N 1370 220 1370 280 {lab=#net14} +N 1370 220 1620 220 {lab=#net14} +N 1620 220 1620 260 {lab=#net14} +N 1620 260 1670 260 {lab=#net14} +N 1600 280 1670 280 {lab=#net15} +N 1370 120 1370 180 {lab=#net13} +N 1370 180 1620 180 {lab=#net13} +N 1620 140 1620 180 {lab=#net13} +N 1620 140 1670 140 {lab=#net13} +N 1600 120 1670 120 {lab=#net16} +N 1610 120 1610 170 {lab=#net16} +N 1210 230 1610 170 {lab=#net16} +N 1210 230 1210 270 {lab=#net16} +N 1210 270 1240 270 {lab=#net16} +N 1610 230 1610 280 {lab=#net15} +N 1210 170 1610 230 {lab=#net15} +N 1210 130 1210 170 {lab=#net15} +N 1210 130 1240 130 {lab=#net15} +N 970 150 990 150 {lab=VSS} +N 1110 150 1130 150 {lab=VSS} +N 1280 160 1300 160 {lab=VSS} +N 1420 160 1440 160 {lab=VSS} +N 1560 160 1580 160 {lab=VSS} +N 1710 170 1730 170 {lab=VSS} +N 1280 320 1300 320 {lab=VSS} +N 1420 320 1440 320 {lab=VSS} +N 1560 320 1580 320 {lab=VSS} +N 1710 310 1730 310 {lab=VSS} +N 970 70 990 70 {lab=VDD_1V8} +N 1110 70 1130 70 {lab=VDD_1V8} +N 1280 80 1300 80 {lab=VDD_1V8} +N 1420 80 1440 80 {lab=VDD_1V8} +N 1560 80 1580 80 {lab=VDD_1V8} +N 1710 90 1730 90 {lab=VDD_1V8} +N 1280 240 1300 240 {lab=VDD_1V8} +N 1420 240 1440 240 {lab=VDD_1V8} +N 1560 240 1580 240 {lab=VDD_1V8} +N 1710 230 1730 230 {lab=VDD_1V8} +N 1930 130 1950 130 {lab=p1n} +N 1890 130 1930 130 {lab=p1n} +N 1850 170 1870 170 {lab=VSS} +N 1850 90 1870 90 {lab=VDD_1V8} +N 1850 310 1870 310 {lab=VSS} +N 1850 230 1870 230 {lab=VDD_1V8} +N 1760 130 1810 130 {lab=p1} +N 1760 270 1810 270 {lab=p2} +N 1930 270 1950 270 {lab=p2n} +N 1890 270 1930 270 {lab=p2n} +N 1640 400 1660 400 {lab=p2en} +N 1600 400 1640 400 {lab=p2en} +N 1560 440 1580 440 {lab=VSS} +N 1560 360 1580 360 {lab=VDD_1V8} +N 1470 400 1520 400 {lab=p2e} +N 1470 280 1470 400 {lab=p2e} +N 1640 0 1660 0 {lab=p1en} +N 1600 0 1640 0 {lab=p1en} +N 1560 40 1580 40 {lab=VSS} +N 1560 -40 1580 -40 {lab=VDD_1V8} +N 1470 0 1520 0 {lab=p1e} +N 1470 0 1470 120 {lab=p1e} +N 730 120 730 140 {lab=#net9} +N 730 110 730 120 {lab=#net9} +N 730 110 930 110 {lab=#net9} +C {devices/ipin.sym} -340 -790 0 0 {name=p1 lab=VDD_1V8} +C {devices/ipin.sym} -340 -400 0 0 {name=p2 lab=VSS} +C {devices/ipin.sym} -340 -600 0 0 {name=p3 lab=IN} +C {devices/lab_wire.sym} -250 -680 0 0 {name=p6 sig_type=std_logic lab=p1} +C {devices/lab_wire.sym} -280 -490 0 0 {name=p9 sig_type=std_logic lab=p2} +C {devices/lab_wire.sym} -60 -490 0 0 {name=p8 sig_type=std_logic lab=p1} +C {devices/capa.sym} -90 -600 3 0 {name=C1 +m=1 +value=1p +footprint=1206 +device="ceramic capacitor"} +C {devices/lab_wire.sym} 70 -680 0 0 {name=p12 sig_type=std_logic lab=p2} +C {devices/vcvs.sym} 240 -580 0 0 {name=E1 value=-1000} +C {devices/capa.sym} 240 -680 3 0 {name=C2 +m=1 +value=2p +footprint=1206 +device="ceramic capacitor"} +C {devices/lab_wire.sym} 500 -680 0 0 {name=p16 sig_type=std_logic lab=p2} +C {devices/lab_wire.sym} 470 -490 0 0 {name=p17 sig_type=std_logic lab=p1 +} +C {devices/lab_wire.sym} 690 -490 0 0 {name=p18 sig_type=std_logic lab=p2} +C {devices/capa.sym} 660 -600 3 0 {name=C3 +m=1 +value=1p +footprint=1206 +device="ceramic capacitor"} +C {devices/lab_wire.sym} 820 -680 0 0 {name=p22 sig_type=std_logic lab=p1} +C {devices/vcvs.sym} 990 -580 0 0 {name=E2 value=-1000} +C {devices/capa.sym} 990 -680 3 0 {name=C4 +m=1 +value=2p +footprint=1206 +device="ceramic capacitor"} +C {devices/switch_ngspice.sym} 1190 -600 1 0 {name=S9 model=mysw} +C {devices/lab_wire.sym} 1190 -680 0 0 {name=p29 sig_type=std_logic lab=p1} +C {devices/capa.sym} 1270 -540 0 0 {name=C5 +m=1 +value=1p +footprint=1206 +device="ceramic capacitor"} +C {devices/switch_ngspice.sym} 820 -600 1 0 {name=S1 model=mysw} +C {devices/switch_ngspice.sym} 500 -600 1 0 {name=S2 model=mysw} +C {devices/switch_ngspice.sym} 70 -600 1 0 {name=S3 model=mysw} +C {devices/switch_ngspice.sym} -250 -600 1 0 {name=S4 model=mysw} +C {devices/switch_ngspice.sym} -200 -490 0 0 {name=S5 model=mysw} +C {devices/switch_ngspice.sym} 20 -490 0 0 {name=S6 model=mysw} +C {devices/switch_ngspice.sym} 550 -490 0 0 {name=S7 model=mysw} +C {devices/switch_ngspice.sym} 770 -490 0 0 {name=S8 model=mysw} +C {devices/vsource.sym} 1440 -540 0 0 {name=E3 value="TABLE \{V(vo2,VSS)\} = (899.9mV, 0V) (900.1mV, \{vdd\})"} +C {devices/lab_wire.sym} 1270 -600 0 1 {name=p7 sig_type=std_logic lab=vo2} +C {JNW_TR_SKY130A/JNWTR_DFRNQNX1_CV.sym} 1770 -540 0 0 {name=x1 } +C {devices/lab_wire.sym} 1730 -540 0 0 {name=p13 sig_type=std_logic lab=p2} +C {devices/lab_wire.sym} 1730 -490 0 0 {name=p19 sig_type=std_logic lab=resb} +C {devices/lab_wire.sym} 2030 -600 0 1 {name=p23 sig_type=std_logic lab=q} +C {JNW_TR_SKY130A/JNWTR_DFRNQNX1_CV.sym} 210 -130 0 1 {name=x2 } +C {devices/lab_wire.sym} 260 -130 0 1 {name=p26 sig_type=std_logic lab=p1} +C {devices/lab_wire.sym} 180 -30 3 1 {name=p31 sig_type=std_logic lab=resb} +C {devices/lab_wire.sym} 150 -260 0 0 {name=p32 sig_type=std_logic lab=VDD_1V8} +C {devices/vsource.sym} 1140 -120 0 0 {name=V1 value="dc 0 pwl(0, 0, \{per/2\}, 0, \{per/2+100p\} \{vdd\})" savecurrent=false} +C {devices/lab_wire.sym} 1140 -190 2 0 {name=p35 sig_type=std_logic lab=resb} +C {devices/vsource.sym} 730 220 0 0 {name=V2 value="dc 0 pulse(0, \{vdd\}, 5n, 100p, 100p, \{per/2-100p\}, \{per\})" savecurrent=false} +C {devices/lab_wire.sym} 1830 -680 0 0 {name=p4 sig_type=std_logic lab=VDD_1V8} +C {devices/lab_wire.sym} 340 -600 0 1 {name=p5 sig_type=std_logic lab=vo1} +C {devices/lab_wire.sym} 240 -820 0 0 {name=p10 sig_type=std_logic lab=res} +C {devices/switch_ngspice.sym} 240 -740 1 0 {name=S10 model=mysw} +C {devices/lab_wire.sym} 990 -820 0 0 {name=p11 sig_type=std_logic lab=res} +C {devices/switch_ngspice.sym} 990 -740 1 0 {name=S11 model=mysw} +C {JNW_TR_SKY130A/JNWTR_IVX2_CV.sym} 1180 -190 0 0 {name=x3 } +C {devices/lab_wire.sym} 1220 -280 0 0 {name=p14 sig_type=std_logic lab=VDD_1V8} +C {devices/lab_wire.sym} 1310 -190 2 0 {name=p15 sig_type=std_logic lab=res} +C {devices/switch_ngspice.sym} 680 -190 0 1 {name=S12 model=mysw} +C {devices/switch_ngspice.sym} 550 -120 0 1 {name=S13 model=mysw} +C {devices/lab_wire.sym} 760 -170 0 1 {name=p24 sig_type=std_logic lab=VSS +} +C {devices/lab_wire.sym} 630 -100 0 1 {name=p25 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 550 -30 3 1 {name=p27 sig_type=std_logic lab=VL} +C {devices/lab_wire.sym} 680 -30 3 1 {name=p28 sig_type=std_logic lab=VH} +C {devices/lab_wire.sym} 2030 -540 0 1 {name=p20 sig_type=std_logic lab=qn} +C {devices/lab_wire.sym} 760 -190 0 1 {name=p21 sig_type=std_logic lab=q} +C {devices/lab_wire.sym} 630 -120 0 1 {name=p30 sig_type=std_logic lab=qn} +C {devices/lab_wire.sym} 250 -190 0 1 {name=p34 sig_type=std_logic lab=q} +C {devices/switch_ngspice.sym} -70 -190 0 1 {name=S14 model=mysw} +C {devices/switch_ngspice.sym} -200 -130 0 1 {name=S15 model=mysw} +C {devices/lab_wire.sym} 10 -170 0 1 {name=p33 sig_type=std_logic lab=VSS +} +C {devices/lab_wire.sym} -120 -110 0 1 {name=p36 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} -200 -30 3 1 {name=p38 sig_type=std_logic lab=VL} +C {devices/lab_wire.sym} -70 -30 3 1 {name=p40 sig_type=std_logic lab=VH} +C {devices/lab_wire.sym} 150 -30 3 1 {name=p41 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 20 -370 0 1 {name=p42 sig_type=std_logic lab=VMID +} +C {devices/lab_wire.sym} 1490 -360 0 1 {name=p43 sig_type=std_logic lab=VMID +} +C {devices/vsource.sym} 1490 -280 0 0 {name=V4 value="dc \{vdd/2\}" savecurrent=false} +C {devices/lab_wire.sym} 1600 -360 0 1 {name=p44 sig_type=std_logic lab=VH +} +C {devices/vsource.sym} 1600 -280 0 0 {name=V5 value="dc \{vdd-0.25\}" savecurrent=false} +C {devices/lab_wire.sym} 1700 -360 0 1 {name=p45 sig_type=std_logic lab=VL +} +C {devices/vsource.sym} 1700 -280 0 0 {name=V6 value="dc 0.25" savecurrent=false} +C {devices/lab_wire.sym} 1650 -600 0 0 {name=p46 sig_type=std_logic lab=vcmp} +C {devices/lab_wire.sym} 40 -190 0 1 {name=p47 sig_type=std_logic lab=q2} +C {devices/lab_wire.sym} 40 -130 0 1 {name=p48 sig_type=std_logic lab=q2n} +C {devices/lab_wire.sym} 1140 -40 3 1 {name=p49 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 1220 -40 3 1 {name=p50 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 730 300 3 1 {name=p51 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 1490 -200 3 1 {name=p53 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 1600 -200 3 1 {name=p54 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 1700 -200 3 1 {name=p55 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} -270 -680 3 1 {name=p56 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 480 -680 3 1 {name=p57 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 800 -680 3 1 {name=p58 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 1170 -680 3 1 {name=p59 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 50 -680 3 1 {name=p60 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 220 -820 3 1 {name=p61 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 970 -820 3 1 {name=p62 sig_type=std_logic lab=VSS} +C {JNW_TR_SKY130A/JNWTR_IVX2_CV.sym} 930 110 0 0 {name=x4 } +C {JNW_TR_SKY130A/JNWTR_IVX2_CV.sym} 1070 110 0 0 {name=x5 } +C {JNW_TR_SKY130A/JNWTR_NDX1_CV.sym} 1240 130 0 0 {name=x6 } +C {JNW_TR_SKY130A/JNWTR_NDX1_CV.sym} 1240 290 0 0 {name=x7 } +C {JNW_TR_SKY130A/JNWTR_IVX2_CV.sym} 1380 120 0 0 {name=x8 } +C {JNW_TR_SKY130A/JNWTR_IVX2_CV.sym} 1520 120 0 0 {name=x9 } +C {JNW_TR_SKY130A/JNWTR_IVX2_CV.sym} 1380 280 0 0 {name=x10 } +C {JNW_TR_SKY130A/JNWTR_IVX2_CV.sym} 1520 280 0 0 {name=x11 } +C {JNW_TR_SKY130A/JNWTR_NDX1_CV.sym} 1670 140 0 0 {name=x12 } +C {JNW_TR_SKY130A/JNWTR_NDX1_CV.sym} 1670 280 0 0 {name=x13 } +C {devices/lab_wire.sym} 990 150 0 1 {name=p63 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 1130 150 0 1 {name=p64 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 1300 160 0 1 {name=p65 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 1440 160 0 1 {name=p66 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 1580 160 0 1 {name=p67 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 1730 170 0 1 {name=p68 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 1300 320 0 1 {name=p69 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 1440 320 0 1 {name=p70 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 1580 320 0 1 {name=p71 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 1730 310 0 1 {name=p72 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 990 70 0 1 {name=p73 sig_type=std_logic lab=VDD_1V8} +C {devices/lab_wire.sym} 1130 70 0 1 {name=p74 sig_type=std_logic lab=VDD_1V8} +C {devices/lab_wire.sym} 1300 80 0 1 {name=p75 sig_type=std_logic lab=VDD_1V8} +C {devices/lab_wire.sym} 1440 80 0 1 {name=p76 sig_type=std_logic lab=VDD_1V8} +C {devices/lab_wire.sym} 1580 80 0 1 {name=p77 sig_type=std_logic lab=VDD_1V8} +C {devices/lab_wire.sym} 1730 90 0 1 {name=p78 sig_type=std_logic lab=VDD_1V8} +C {devices/lab_wire.sym} 1300 240 0 1 {name=p79 sig_type=std_logic lab=VDD_1V8} +C {devices/lab_wire.sym} 1440 240 0 1 {name=p80 sig_type=std_logic lab=VDD_1V8} +C {devices/lab_wire.sym} 1580 240 0 1 {name=p81 sig_type=std_logic lab=VDD_1V8} +C {devices/lab_wire.sym} 1730 230 0 1 {name=p82 sig_type=std_logic lab=VDD_1V8} +C {JNW_TR_SKY130A/JNWTR_IVX2_CV.sym} 1810 130 0 0 {name=x14 } +C {devices/lab_wire.sym} 1870 170 0 1 {name=p83 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 1870 90 0 1 {name=p84 sig_type=std_logic lab=VDD_1V8} +C {JNW_TR_SKY130A/JNWTR_IVX2_CV.sym} 1810 270 0 0 {name=x15 } +C {devices/lab_wire.sym} 1870 310 0 1 {name=p85 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 1870 230 0 1 {name=p86 sig_type=std_logic lab=VDD_1V8} +C {devices/lab_wire.sym} 1780 130 0 1 {name=p87 sig_type=std_logic lab=p1 +} +C {devices/lab_wire.sym} 1780 270 0 1 {name=p88 sig_type=std_logic lab=p2 +} +C {devices/lab_wire.sym} 1930 130 0 1 {name=p89 sig_type=std_logic lab=p1n +} +C {devices/lab_wire.sym} 1930 270 0 1 {name=p90 sig_type=std_logic lab=p2n +} +C {JNW_TR_SKY130A/JNWTR_IVX2_CV.sym} 1520 400 0 0 {name=x16 } +C {devices/lab_wire.sym} 1580 440 0 1 {name=p91 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 1580 360 0 1 {name=p92 sig_type=std_logic lab=VDD_1V8} +C {devices/lab_wire.sym} 1490 400 0 1 {name=p93 sig_type=std_logic lab=p2e +} +C {devices/lab_wire.sym} 1640 400 0 1 {name=p94 sig_type=std_logic lab=p2en +} +C {JNW_TR_SKY130A/JNWTR_IVX2_CV.sym} 1520 0 0 0 {name=x17 } +C {devices/lab_wire.sym} 1580 40 0 1 {name=p95 sig_type=std_logic lab=VSS} +C {devices/lab_wire.sym} 1580 -40 0 1 {name=p96 sig_type=std_logic lab=VDD_1V8} +C {devices/lab_wire.sym} 1490 0 0 1 {name=p97 sig_type=std_logic lab=p1e +} +C {devices/lab_wire.sym} 1640 0 0 1 {name=p98 sig_type=std_logic lab=p1en +} diff --git a/models/initial_model.zcos b/models/initial_model.zcos new file mode 100644 index 0000000..20f8a78 Binary files /dev/null and b/models/initial_model.zcos differ diff --git a/sim/JNW_SIGMA_DELTA_A2D/tran.py b/sim/JNW_SIGMA_DELTA_A2D/tran.py index afe28d7..93371a9 100644 --- a/sim/JNW_SIGMA_DELTA_A2D/tran.py +++ b/sim/JNW_SIGMA_DELTA_A2D/tran.py @@ -1,18 +1,68 @@ #!/usr/bin/env python3 import pandas as pd import yaml +import ltspice as lt +import numpy as np +import matplotlib.pyplot as plt +from scipy.interpolate import interp1d +import math +import sys def main(name): # Delete next line if you want to use python post processing - return + # return yamlfile = name + ".yaml" + sys.stdout.write("Reading YAML file: " + yamlfile + "\n") # Read result yaml file with open(yamlfile) as fi: obj = yaml.safe_load(fi) + sys.stdout.write("Done reading YAML file: " + yamlfile + "\n") + + # Read raw file + rawfile = name + ".raw" + + sys.stdout.write("Reading RAW file: " + rawfile + "\n") + + rawdata = lt.Ltspice(rawfile) + + rawdata.parse() + + time = rawdata.get_time() + vq = rawdata.get_data('V(xdut.q)') + vqn = rawdata.get_data('V(xdut.qn)') + vres = rawdata.get_data('V(xdut.res)') + vresb = rawdata.get_data('V(xdut.resb)') + vcmp = rawdata.get_data('V(xdut.vcmp)') + p1 = rawdata.get_data('V(xdut.p1)') + p2 = rawdata.get_data('V(xdut.p2)') + vo1 = rawdata.get_data('V(xdut.vo1)') + vo2 = rawdata.get_data('V(xdut.vo2)') + sys.stdout.write("Done reading RAW file: " + rawfile + "\n") # Do something to parameters + vmid = 0.9 + vin = vmid+7e-3 + vfs = 0.5 + per = 1/16e6 + tstart = 1.5*per + N = 64 + dout = vq + t = time + ts = np.arange(tstart, tstart+N*per, per) + interp_func = interp1d(t, dout) + dsamp = interp_func(ts) + dsamp[dsamp > 0.9] = 1 + dsamp[dsamp < 0.9] = 0 + csum = np.cumsum(dsamp) + out = vmid-vfs/2 + np.cumsum(csum)*2.0/N/(N+1)*vfs + + obj['ts'] = ts.tolist() + obj['out'] = out.tolist() + sys.stdout.write("Write YAML file: " + yamlfile + "\n") # Save new yaml file with open(yamlfile,"w") as fo: yaml.dump(obj,fo) + + sys.stdout.write("Done writing YAML file: " + yamlfile + "\n") diff --git a/sim/JNW_SIGMA_DELTA_A2D/tran.spi b/sim/JNW_SIGMA_DELTA_A2D/tran.spi index 3da0ae4..ce68965 100644 --- a/sim/JNW_SIGMA_DELTA_A2D/tran.spi +++ b/sim/JNW_SIGMA_DELTA_A2D/tran.spi @@ -11,20 +11,24 @@ *----------------------------------------------------------------- * OPTIONS *----------------------------------------------------------------- -.option TNOM=27 GMIN=1e-15 reltol=1e-3 +.option TNOM=27 GMIN=1e-15 reltol=1e-4 *----------------------------------------------------------------- * PARAMETERS *----------------------------------------------------------------- .param TRF = 10p +.param vdd = 1.8 +.param AVDD = 1.8 +.param per = 1/16e6 -.param AVDD = {vdda} +.model mysw SW vt{vdd/2} ron=10k roff=1gig" *----------------------------------------------------------------- * FORCE *----------------------------------------------------------------- -VSS VSS 0 dc 0 -VDD VDD_1V8 VSS pwl 0 0 10n {AVDD} +V_ground VSS 0 dc 0 +V_sup VDD_1V8 VSS dc {AVDD} +V_IN IN VSS dc {vdd/2} sin({vdd/2} {vdd/4} 100k 1n 0 0) *----------------------------------------------------------------- * DUT @@ -34,8 +38,7 @@ VDD VDD_1V8 VSS pwl 0 0 10n {AVDD} *---------------------------------------------------------------- * PROBE *---------------------------------------------------------------- -.save all - +.save xdut.q xdut.qn xdut.res xdut.resb xdut.vcmp xdut.p1 xdut.p2 xdut.vo1 xdut.vo2 *---------------------------------------------------------------- * NGSPICE control @@ -46,14 +49,12 @@ set color0=white set color1=black unset askquit -optran 0 0 0 1n 1u 0 - +op -tran 1n 10n 1p +tran 0.25n 100u write quit - .endc .end diff --git a/sim/JNW_SIGMA_DELTA_A2D/xdut.spi b/sim/JNW_SIGMA_DELTA_A2D/xdut.spi new file mode 100644 index 0000000..af6cbe1 --- /dev/null +++ b/sim/JNW_SIGMA_DELTA_A2D/xdut.spi @@ -0,0 +1,2 @@ +*Automatic generated instance fron ../../tech/scripts/genxdut JNW_SIGMA_DELTA_A2D +XDUT VDD_1V8 VSS IN JNW_SIGMA_DELTA_A2D