rb_address_table.org

Module DRS adr = 0x0

Implements various control and monitoring functions of the DRS Logic

DRS.CHIP

Registers for configuring the DRS ASIC Directly

Node	Adr	Adr8	Bits	Perm	Def	Description
DMODE	0x0	0x0	1	rw	0x1	set 1 = continuous domino, 0=single shot
STANDBY_MODE	0x0	0x0	2	rw	0x0	set 1 = shutdown drs
TRANSPARENT_MODE	0x0	0x0	3	rw	0x0	set 1 = transparent mode
DRS_PLL_LOCK	0x0	0x0	4	r		DRS PLL Locked
CHANNEL_CONFIG	0x0	0x0	[31:24]	rw	0xFF	Write Shift Register Configuration
						# of chn - # of cells per ch - bit pattern
						8 - 1024 - 11111111b
						4 - 2048 - 01010101b
						2 - 4096 - 00010001b
						1 - 8192 - 00000001b
DTAP_FREQ	0x1	0x4	[15:0]	r		Frequency of DTAP in units of 100Hz
CLK_IDELAY	0x2	0x8	[4:0]	rw	0xF	DRS CLK IDELAY Setting 0-31 in 78 ps increments
CYLON_MODE	0x3	0xc	0	rw	0x0	1 for cylon mode
START_TIMER	0x3	0xc	[11:4]	rw	0x69	Number of clock cycles to delay before allowing triggers.
LOSS_OF_LOCK	0x4	0x10	0	r		Raw reading of LOL signal
LOSS_OF_LOCK_STABLE	0x4	0x10	1	r		Loss of lock stable over the past ~second

DRS.READOUT

Registers for configuring the readout state machine

Node	Adr	Adr8	Bits	Perm	Def	Description
ROI_MODE	0x10	0x40	0	rw	0x1	Set to 1 to enable Region of Interest Readout
BUSY	0x10	0x40	1	r		DRS is busy
ADC_LATENCY	0x10	0x40	[9:4]	rw	0x9	Latency from first sr clock to when ADC data should be valid
SAMPLE_COUNT	0x10	0x40	[21:12]	rw	0x3FF	Number of samples to read out (0 to 1023)
EN_SPIKE_REMOVAL	0x10	0x40	22	rw	0x1	set 1 to enable spike removal
READOUT_MASK	0x11	0x44	[8:0]	rw	0x1FF	8 bit mask, set a bit to 1 to enable readout of that channel. 9th is auto-read if any channel is enabled and AUTO_9TH_CHANNEL set to 1
AUTO_9TH_CHANNEL	0x11	0x44	9	rw	0x1	Set to 1 to auto read the 9th channel
START	0x12	0x48	0	w	Pulse	Write 1 to take the state machine out of idle mode
REINIT	0x13	0x4c	0	w	Pulse	Write 1 to reinitialize DRS state machine (restores to idle state)
CONFIGURE	0x14	0x50	0	w	Pulse	Write 1 to configure the DRS. Should be done before data taking
DRS_RESET	0x15	0x54	0	w	Pulse	Write 1 to completely reset the DRS state machine logic
DAQ_RESET	0x16	0x58	0	w	Pulse	Write 1 to completely reset the DAQ state machine logic
DMA_RESET	0x17	0x5c	0	w	Pulse	Write 1 to completely reset the DMA state machine logic
WAIT_VDD_CLKS	0x18	0x60	[15:0]	rw	0x14D	Number of ADC clocks to wait before reading out the drs, allowing vdd to stabilize; default=0x14d=10us
DRS_DIAGNOSTIC_MODE	0x19	0x64	0	rw	0x0	1 will make the DRS read out the cell ID instead of ADC data
POSNEG	0x1a	0x68	0	rw	0x0	1 to sample on positive edge, 0 on negative
SROUT_POSNEG	0x1a	0x68	1	rw	0x0	1 to sample on positive edge, 0 on negative
SROUT_LATENCY	0x1a	0x68	[6:4]	rw	0x2	Latency of the SROUT readout
DMA_CLEAR	0x1b	0x6c	0	w	Pulse	Write 1 to clear the DMA memory (write zeroes)
SOFT_RESET	0x1c	0x70	0	w	Pulse	Write 1 to soft reset the readout buffers.
SOFT_RESET_DRS_EN	0x1d	0x74	0	rw	0x0	Soft reset DRS.
SOFT_RESET_DAQ_EN	0x1d	0x74	1	rw	0x0	Soft reset DAQ.
SOFT_RESET_DMA_EN	0x1d	0x74	2	rw	0x1	Soft reset DMA.
SOFT_RESET_PTR_EN	0x1d	0x74	3	rw	0x1	Soft reset occupancy pointer.
SOFT_RESET_BUF_EN	0x1d	0x74	5	rw	0x1	Soft reset buffers.
SOFT_RESET_WAIT_DRS	0x1d	0x74	8	rw	0x1	Wait for DRS to idle.
SOFT_RESET_WAIT_DAQ	0x1d	0x74	9	rw	0x1	Wait for DAQ to idle.
SOFT_RESET_WAIT_DMA	0x1d	0x74	10	rw	0x1	Wait for DMA to idle.
SOFT_RESET_DONE	0x1d	0x74	15	r		Soft reset is finished.
SOFT_RESET_WATCHDOG_EN	0x1e	0x78	11	rw	0x1	Enable a watchdog timer for the soft reset module.
DRS_DEADTIME	0x1e	0x78	[15:0]	r		Measured last deadtime of the DRS in clock cycles

DRS.FPGA.DNA

FPGA Device DNA

Node	Adr	Adr8	Bits	Perm	Def	Description
DNA_LSBS	0x20	0x80	[31:0]	r		Device DNA [31:0]
DNA_MSBS	0x21	0x84	[24:0]	r		Device DNA [56:32]

DRS.FPGA.TIMESTAMP

Timestamp

Node	Adr	Adr8	Bits	Perm	Def	Description
TIMESTAMP_LSBS	0x24	0x90	[31:0]	r		Device TIMESTAMP [31:0]
TIMESTAMP_MSBS	0x25	0x94	[15:0]	r		Device TIMESTAMP [47:32]

DRS.FPGA.XADC

Zynq XADC

Node	Adr	Adr8	Bits	Perm	Def	Description
CALIBRATION	0x26	0x98	[11:0]	r		XADC Calibration
VCCPINT	0x26	0x98	[27:16]	r		XADC vccpint
VCCPAUX	0x27	0x9c	[11:0]	r		XADC Calibration
VCCODDR	0x27	0x9c	[27:16]	r		XADC vccoddr
TEMP	0x28	0xa0	[11:0]	r		XADC Temperature
VCCINT	0x28	0xa0	[27:16]	r		XADC vccint
VCCAUX	0x29	0xa4	[11:0]	r		XADC VCCAUX
VCCBRAM	0x29	0xa4	[27:16]	r		XADC vccbram

DRS.FPGA

FPGA Status

Node	Adr	Adr8	Bits	Perm	Def	Description
BOARD_ID	0x2a	0xa8	[7:0]	rw	0x0	Board ID Number
DRS_TEMP	0x2b	0xac	[15:0]	rw	0x3039	Copy of the I2C DRS temperature reading
RAT_HOUSEKEEPING	0x2c	0xb0	[31:0]	rw	0x0	32 bit RAT housekeeping data. Meaning is software defined.

DRS.DAQ

DAQ

Node	Adr	Adr8	Bits	Perm	Def	Description
INJECT_DEBUG_PACKET	0x30	0xc0	0	w	Pulse	Injects a fixed format debug packet into the DAQ
DAQ_FRAGMENT_EN	0x31	0xc4	0	rw	0x0	1 to enable daq fragments (header only packets) when the DRS is busy
DAQ_BUSY	0x31	0xc4	1	r		1 = DAQ is still busy reading out

DRS.TRIGGER

Trigger

Node	Adr	Adr8	Bits	Perm	Def	Description
FORCE_TRIGGER	0x40	0x100	0	w	Pulse	Generates a trigger
EXT_TRIGGER_EN	0x41	0x104	0	rw	0x0	Set to 1 to enable the external trigger
EXT_TRIGGER_ACTIVE_HI	0x41	0x104	1	rw	0x1	Set to 1 for active high external trigger
MT_TRIGGER_IS_LEVEL	0x41	0x104	2	rw	0x0	Set to 1 for mt level trigger on v2.4 boards
MT_LINK_ID	0x41	0x104	[8:3]	r		MT Link ID Received from MTB
CNT_MT_PRBS_ERRS	0x43	0x10c	[31:0]	r		Number of PRBS errors on the MT line
MT_PRBS_ERR_RESET	0x44	0x110	0	w	Pulse	Write 1 to reset the MT PRBS Error Counter
MT_TRIGGER_MODE	0x45	0x114	0	rw	0x0	1 to use the MT as the source of the trigger
CNT_MT_CRC_ERR	0x46	0x118	[15:0]	r		Number of MT CRC errors
TRIGGER_ENABLE	0x47	0x11c	0	rw	0x0	Set to 0 to stop all triggers. 1 to enable triggers.
MT_EVENT_CNT	0x48	0x120	[31:0]	r		Recevied event counter
MT_TRIGGER_RATE	0x49	0x124	[31:0]	r		Rate of triggers received from the MTB in Hz

DRS.COUNTERS

Counters

Node	Adr	Adr8	Bits	Perm	Def	Description
CNT_SEM_CORRECTION	0x50	0x140	[15:0]	r		Number of Single Event Errors corrected by the scrubber
CNT_SEM_UNCORRECTABLE	0x51	0x144	[19:16]	r		Number of Critical Single Event Errors (uncorrectable by scrubber)
CNT_READOUTS_COMPLETED	0x52	0x148	[31:0]	r		Number of readouts completed since reset
CNT_DMA_READOUTS_COMPLETED	0x53	0x14c	[31:0]	r		Number of readouts completed since reset
CNT_LOST_EVENT	0x54	0x150	[31:16]	r		Number of trigger lost due to deadtime
CNT_EVENT	0x55	0x154	[31:0]	r		Number of triggers received
TRIGGER_RATE	0x56	0x158	[31:0]	r		Rate of triggers in Hz
LOST_TRIGGER_RATE	0x57	0x15c	[31:0]	r		Rate of lost triggers in Hz
CNT_RESET	0x58	0x160	0	w	Pulse	Reset the counters

DRS

Implements various control and monitoring functions of the DRS Logic

Node	Adr	Adr8	Bits	Perm	Def	Description
TRIG_GEN_RATE	0x59	0x164	[31:0]	rw	0x0	Rate of generated triggers f_trig = (1/clk_period) * rate/0xffffffff

DRS.HOG

HOG Parameters

Node	Adr	Adr8	Bits	Perm	Def	Description
GLOBAL_DATE	0x60	0x180	[31:0]	r		HOG Global Date
GLOBAL_TIME	0x61	0x184	[31:0]	r		HOG Global Time
GLOBAL_VER	0x62	0x188	[31:0]	r		HOG Global Version
GLOBAL_SHA	0x63	0x18c	[31:0]	r		HOG Global SHA
REPO_SHA	0x64	0x190	[31:0]	r		HOG Repo SHA
TOP_VER	0x65	0x194	[31:0]	r		HOG Repo Version
HOG_SHA	0x66	0x198	[31:0]	r		HOG SHA
HOG_VER	0x67	0x19c	[31:0]	r		HOG Version

DRS

Implements various control and monitoring functions of the DRS Logic

Node	Adr	Adr8	Bits	Perm	Def	Description
CNT_SNAP	0x80	0x200	0	w	Pulse	1 to freeze counters for readout
CNT_SNAP_DIS	0x80	0x200	1	w	0x1	1 disables counter snapping; values continuously update
CNT_START_READOUT	0x81	0x204	[31:0]	r		Count the number of times the DRS readout has started
CNT_EVENT_WR_EN	0x82	0x208	[31:0]	r		Count the number of times the event queue has been written to
AUTO_PURGE_MODE	0x83	0x20c	0	rw	0x0	1 for the DAQ to automatically purge any remaining data from the DRS fifo after readout

DRS.DMA

DMA and ram buffer occupancy

Node	Adr	Adr8	Bits	Perm	Def	Description
RAM_A_OCC_RST	0x100	0x400	0	w	Pulse	Sets RAM buffer a counter to 0
RAM_B_OCC_RST	0x101	0x404	0	w	Pulse	Sets RAM buffer b counter to 0
RAM_A_OCCUPANCY	0x102	0x408	[31:0]	r		RAM buffer a occupancy
RAM_B_OCCUPANCY	0x103	0x40c	[31:0]	r		RAM buffer b occupancy
DMA_POINTER	0x104	0x410	[31:0]	r		DMA controller pointer
TOGGLE_RAM	0x105	0x414	0	w	Pulse	Write 1 to switch the dma buffer to the other half