mt_address_table.org

Module MT adr = 0x0

Implements various control and monitoring functions of the DRS Logic

MT

Implements various control and monitoring functions of the DRS Logic

Node	Adr	Adr8	Bits	Perm	Def	Description
LOOPBACK	0x0	0x0	[31:0]	rw	0x0	Loopback register
CLOCK_RATE	0x1	0x4	[31:0]	r		System clock frequency
FB_CLOCK_RATE_0	0x2	0x8	[31:0]	r		Feedback clock frequency
FB_CLOCK_RATE_1	0x3	0xc	[31:0]	r		Feedback clock frequency
FB_CLOCK_RATE_2	0x4	0x10	[31:0]	r		Feedback clock frequency
FB_CLOCK_RATE_3	0x5	0x14	[31:0]	r		Feedback clock frequency
FB_CLOCK_RATE_4	0x6	0x18	[31:0]	r		Feedback clock frequency
DSI_ON	0x7	0x1c	[4:0]	rw	0x1F	Bitmask 1 = enable DSI
FORCE_TRIGGER	0x8	0x20	0	w	Pulse	Write 1 to generate a trigger
TRIG_GEN_RATE	0x9	0x24	[31:0]	rw	0x0	Rate of generated triggers f_trig = (1/clk_period) * rate/0xffffffff
RESYNC	0xa	0x28	0	w	Pulse	Write 1 to resync
ANY_TRIG_IS_GLOBAL	0xb	0x2c	0	rw	0x0	1 makes the ANY trigger read all paddles.
TRACK_TRIG_IS_GLOBAL	0xb	0x2c	1	rw	0x0	1 makes the TRACK trigger read all paddles.
TRACK_CENTRAL_IS_GLOBAL	0xb	0x2c	2	rw	0x0	1 makes the TRACK central read all paddles.
TRACK_UMB_CENTRAL_IS_GLOBAL	0xb	0x2c	3	rw	0x0	1 makes the TRACK UMB central read all paddles.
EVENT_CNT_RESET	0xc	0x30	0	w	Pulse	Write 1 to reset the event counter
EVENT_CNT	0xd	0x34	[31:0]	r		Event Counter
TIU_EMULATION_MODE	0xe	0x38	0	rw	0x0	1 to emulate the TIU
TIU_USE_AUX_LINK	0xe	0x38	1	rw	0x0	1 to use J11; 0 to use J3
TIU_EMU_BUSY_CNT	0xe	0x38	[31:14]	rw	0xC350	Number of 10 ns clock cyles that the emulator will remain busy
TIU_BAD	0xf	0x3c	0	r		1 means that the tiu link is not working
TIU_BUSY_STUCK	0xf	0x3c	1	r		1 means the TIU has been stuck high for a long time
TIU_BUSY_IGNORE	0xf	0x3c	2	rw	0x0	1 means the the MTB should ignore the TIU busy flag (e.g. because it is stuck)
LT_INPUT_STRETCH	0xf	0x3c	[7:4]	rw	0xF	Number of clock cycles to stretch the LT inputs by
RB_INTEGRATION_WINDOW	0xf	0x3c	[12:8]	rw	0x1	Number of 100MHz clock cycles to integrate the LTB hits to determine which RBs to read out.
RB_READ_ALL_CHANNELS	0xf	0x3c	13	rw	0x1	Set to 1 to read all channels from RB for any trigger

MT.EVENT_QUEUE

DAQ Buffer

Node	Adr	Adr8	Bits	Perm	Def	Description
RESET	0x10	0x40	0	w	Pulse	DAQ Buffer Reset
DATA	0x11	0x44	[31:0]	r		DAQ Read Data
FULL	0x12	0x48	0	r		DAQ Buffer Full
EMPTY	0x12	0x48	1	r		DAQ Buffer Empty
NUM_EVENTS	0x13	0x4c	[13:0]	r		DAQ Buffer Number of Events
SIZE	0x13	0x4c	[31:16]	r		DAQ Buffer Head Event Size

MT

Implements various control and monitoring functions of the DRS Logic

Node	Adr	Adr8	Bits	Perm	Def	Description
INNER_TOF_THRESH	0x14	0x50	[7:0]	rw	0x3	Inner TOF hit threshold
OUTER_TOF_THRESH	0x14	0x50	[15:8]	rw	0x3	Outer TOF hit threshold
TOTAL_TOF_THRESH	0x14	0x50	[23:16]	rw	0x8	Total TOF hit threshold
GAPS_TRIGGER_EN	0x14	0x50	24	rw	0x0	Enable the gaps trigger.
REQUIRE_BETA	0x14	0x50	25	rw	0x1	Require beta in the gaps trigger
HIT_THRESH	0x14	0x50	[29:28]	rw	0x0	Threshold for the hit bitmap. Threshold must be > this number.
CONFIGURABLE_TRIGGER_EN	0x14	0x50	31	rw	0x0	Enable the configurable trigger
CUBE_SIDE_THRESH	0x15	0x54	[7:0]	rw	0x0	Threshold for the hit bitmap. Threshold must be > this number.
CUBE_TOP_THRESH	0x15	0x54	[15:8]	rw	0x0	Threshold for the hit bitmap. Threshold must be > this number.
CUBE_BOT_THRESH	0x15	0x54	[23:16]	rw	0x0	Threshold for the hit bitmap. Threshold must be > this number.
CUBE_CORNER_THRESH	0x15	0x54	[31:24]	rw	0x0	Threshold for the hit bitmap. Threshold must be > this number.
UMBRELLA_THRESH	0x16	0x58	[7:0]	rw	0x0	Threshold for the hit bitmap. Threshold must be > this number.
UMBRELLA_CENTER_THRESH	0x16	0x58	[15:8]	rw	0x0	Threshold for the hit bitmap. Threshold must be > this number.
CORTINA_THRESH	0x16	0x58	[23:16]	rw	0x0	Threshold for the hit bitmap. Threshold must be > this number.
TRIGGER_RATE	0x17	0x5c	[23:0]	r		Rate of triggers in Hz
LOST_TRIGGER_RATE	0x18	0x60	[23:0]	r		Rate of lost triggers in Hz
LT_LINK_READY0	0x1a	0x68	[9:0]	r		DSI 0 RX Link OK
LT_LINK_READY1	0x1b	0x6c	[9:0]	r		DSI 1 RX Link OK
LT_LINK_READY2	0x1c	0x70	[9:0]	r		DSI 2 RX Link OK
LT_LINK_READY3	0x1d	0x74	[9:0]	r		DSI 3 RX Link OK
LT_LINK_READY4	0x1e	0x78	[9:0]	r		DSI 4 RX Link OK

MT.HIT_COUNTERS

Counters

Node	Adr	Adr8	Bits	Perm	Def	Description
LT0	0x20	0x80	[23:0]	r		hit count on LT=0
LT1	0x21	0x84	[23:0]	r		hit count on LT=1
LT2	0x22	0x88	[23:0]	r		hit count on LT=2
LT3	0x23	0x8c	[23:0]	r		hit count on LT=3
LT4	0x24	0x90	[23:0]	r		hit count on LT=4
LT5	0x25	0x94	[23:0]	r		hit count on LT=5
LT6	0x26	0x98	[23:0]	r		hit count on LT=6
LT7	0x27	0x9c	[23:0]	r		hit count on LT=7
LT8	0x28	0xa0	[23:0]	r		hit count on LT=8
LT9	0x29	0xa4	[23:0]	r		hit count on LT=9
LT10	0x2a	0xa8	[23:0]	r		hit count on LT=10
LT11	0x2b	0xac	[23:0]	r		hit count on LT=11
LT12	0x2c	0xb0	[23:0]	r		hit count on LT=12
LT13	0x2d	0xb4	[23:0]	r		hit count on LT=13
LT14	0x2e	0xb8	[23:0]	r		hit count on LT=14
LT15	0x2f	0xbc	[23:0]	r		hit count on LT=15
LT16	0x30	0xc0	[23:0]	r		hit count on LT=16
LT17	0x31	0xc4	[23:0]	r		hit count on LT=17
LT18	0x32	0xc8	[23:0]	r		hit count on LT=18
LT19	0x33	0xcc	[23:0]	r		hit count on LT=19
LT20	0x34	0xd0	[23:0]	r		hit count on LT=20
LT21	0x35	0xd4	[23:0]	r		hit count on LT=21
LT22	0x36	0xd8	[23:0]	r		hit count on LT=22
LT23	0x37	0xdc	[23:0]	r		hit count on LT=23
LT24	0x38	0xe0	[23:0]	r		hit count on LT=24
RESET	0x39	0xe4	0	w	Pulse	Write 1 to reset hit counters.
SNAP	0x3a	0xe8	0	rw	0x1	1 to snap the hit counters.

MT

Implements various control and monitoring functions of the DRS Logic

Node	Adr	Adr8	Bits	Perm	Def	Description
ETH_RX_BAD_FRAME_CNT	0x3d	0xf4	[15:0]	r		Ethernet MAC bad frame error
ETH_RX_BAD_FCS_CNT	0x3d	0xf4	[31:16]	r		Ethernet MAC bad fcs
ANY_TRIG_PRESCALE	0x40	0x100	[31:0]	rw	0x0	Prescale value for the ANY trigger. 0 == 0% (off), 2**32-1 == 100%
TRACK_TRIGGER_PRESCALE	0x41	0x104	[31:0]	rw	0x0	Prescale value for the Inner + Outer Track Trigger. 0 == 0% (off), 2**32-1 == 100%
TRACK_CENTRAL_PRESCALE	0x42	0x108	[31:0]	rw	0x0	Prescale value for the Umbrella + Cube Top Track Trigger. 0 == 0% (off), 2**32-1 == 100%

MT.CHANNEL_MASK

1 to mask a channel

Node	Adr	Adr8	Bits	Perm	Def	Description
LT0	0x50	0x140	[7:0]	rw	0x0	1 to mask a channel of LT=0
LT1	0x51	0x144	[7:0]	rw	0x0	1 to mask a channel of LT=1
LT2	0x52	0x148	[7:0]	rw	0x0	1 to mask a channel of LT=2
LT3	0x53	0x14c	[7:0]	rw	0x0	1 to mask a channel of LT=3
LT4	0x54	0x150	[7:0]	rw	0x0	1 to mask a channel of LT=4
LT5	0x55	0x154	[7:0]	rw	0x0	1 to mask a channel of LT=5
LT6	0x56	0x158	[7:0]	rw	0x0	1 to mask a channel of LT=6
LT7	0x57	0x15c	[7:0]	rw	0x0	1 to mask a channel of LT=7
LT8	0x58	0x160	[7:0]	rw	0x0	1 to mask a channel of LT=8
LT9	0x59	0x164	[7:0]	rw	0x0	1 to mask a channel of LT=9
LT10	0x5a	0x168	[7:0]	rw	0x0	1 to mask a channel of LT=10
LT11	0x5b	0x16c	[7:0]	rw	0x0	1 to mask a channel of LT=11
LT12	0x5c	0x170	[7:0]	rw	0x0	1 to mask a channel of LT=12
LT13	0x5d	0x174	[7:0]	rw	0x0	1 to mask a channel of LT=13
LT14	0x5e	0x178	[7:0]	rw	0x0	1 to mask a channel of LT=14
LT15	0x5f	0x17c	[7:0]	rw	0x0	1 to mask a channel of LT=15
LT16	0x60	0x180	[7:0]	rw	0x0	1 to mask a channel of LT=16
LT17	0x61	0x184	[7:0]	rw	0x0	1 to mask a channel of LT=17
LT18	0x62	0x188	[7:0]	rw	0x0	1 to mask a channel of LT=18
LT19	0x63	0x18c	[7:0]	rw	0x0	1 to mask a channel of LT=19
LT20	0x64	0x190	[7:0]	rw	0x0	1 to mask a channel of LT=20
LT21	0x65	0x194	[7:0]	rw	0x0	1 to mask a channel of LT=21
LT22	0x66	0x198	[7:0]	rw	0x0	1 to mask a channel of LT=22
LT23	0x67	0x19c	[7:0]	rw	0x0	1 to mask a channel of LT=23
LT24	0x68	0x1a0	[7:0]	rw	0x0	1 to mask a channel of LT=24

MT.COARSE_DELAYS

Node	Adr	Adr8	Bits	Perm	Def	Description
LT0	0xc0	0x300	[3:0]	rw	0x0	Integer clock delay of LT LINK 0
LT1	0xc1	0x304	[3:0]	rw	0x0	Integer clock delay of LT LINK 1
LT2	0xc2	0x308	[3:0]	rw	0x0	Integer clock delay of LT LINK 2
LT3	0xc3	0x30c	[3:0]	rw	0x0	Integer clock delay of LT LINK 3
LT4	0xc4	0x310	[3:0]	rw	0x0	Integer clock delay of LT LINK 4
LT5	0xc5	0x314	[3:0]	rw	0x0	Integer clock delay of LT LINK 5
LT6	0xc6	0x318	[3:0]	rw	0x0	Integer clock delay of LT LINK 6
LT7	0xc7	0x31c	[3:0]	rw	0x0	Integer clock delay of LT LINK 7
LT8	0xc8	0x320	[3:0]	rw	0x0	Integer clock delay of LT LINK 8
LT9	0xc9	0x324	[3:0]	rw	0x0	Integer clock delay of LT LINK 9
LT10	0xca	0x328	[3:0]	rw	0x0	Integer clock delay of LT LINK 10
LT11	0xcb	0x32c	[3:0]	rw	0x0	Integer clock delay of LT LINK 11
LT12	0xcc	0x330	[3:0]	rw	0x0	Integer clock delay of LT LINK 12
LT13	0xcd	0x334	[3:0]	rw	0x0	Integer clock delay of LT LINK 13
LT14	0xce	0x338	[3:0]	rw	0x0	Integer clock delay of LT LINK 14
LT15	0xcf	0x33c	[3:0]	rw	0x0	Integer clock delay of LT LINK 15
LT16	0xd0	0x340	[3:0]	rw	0x0	Integer clock delay of LT LINK 16
LT17	0xd1	0x344	[3:0]	rw	0x0	Integer clock delay of LT LINK 17
LT18	0xd2	0x348	[3:0]	rw	0x0	Integer clock delay of LT LINK 18
LT19	0xd3	0x34c	[3:0]	rw	0x0	Integer clock delay of LT LINK 19
LT20	0xd4	0x350	[3:0]	rw	0x0	Integer clock delay of LT LINK 20
LT21	0xd5	0x354	[3:0]	rw	0x0	Integer clock delay of LT LINK 21
LT22	0xd6	0x358	[3:0]	rw	0x0	Integer clock delay of LT LINK 22
LT23	0xd7	0x35c	[3:0]	rw	0x0	Integer clock delay of LT LINK 23
LT24	0xd8	0x360	[3:0]	rw	0x0	Integer clock delay of LT LINK 24
LT25	0xd9	0x364	[3:0]	rw	0x0	Integer clock delay of LT LINK 25
LT26	0xda	0x368	[3:0]	rw	0x0	Integer clock delay of LT LINK 26
LT27	0xdb	0x36c	[3:0]	rw	0x0	Integer clock delay of LT LINK 27
LT28	0xdc	0x370	[3:0]	rw	0x0	Integer clock delay of LT LINK 28
LT29	0xdd	0x374	[3:0]	rw	0x0	Integer clock delay of LT LINK 29
LT30	0xde	0x378	[3:0]	rw	0x0	Integer clock delay of LT LINK 30
LT31	0xdf	0x37c	[3:0]	rw	0x0	Integer clock delay of LT LINK 31
LT32	0xe0	0x380	[3:0]	rw	0x0	Integer clock delay of LT LINK 32
LT33	0xe1	0x384	[3:0]	rw	0x0	Integer clock delay of LT LINK 33
LT34	0xe2	0x388	[3:0]	rw	0x0	Integer clock delay of LT LINK 34
LT35	0xe3	0x38c	[3:0]	rw	0x0	Integer clock delay of LT LINK 35
LT36	0xe4	0x390	[3:0]	rw	0x0	Integer clock delay of LT LINK 36
LT37	0xe5	0x394	[3:0]	rw	0x0	Integer clock delay of LT LINK 37
LT38	0xe6	0x398	[3:0]	rw	0x0	Integer clock delay of LT LINK 38
LT39	0xe7	0x39c	[3:0]	rw	0x0	Integer clock delay of LT LINK 39
LT40	0xe8	0x3a0	[3:0]	rw	0x0	Integer clock delay of LT LINK 40
LT41	0xe9	0x3a4	[3:0]	rw	0x0	Integer clock delay of LT LINK 41
LT42	0xea	0x3a8	[3:0]	rw	0x0	Integer clock delay of LT LINK 42
LT43	0xeb	0x3ac	[3:0]	rw	0x0	Integer clock delay of LT LINK 43
LT44	0xec	0x3b0	[3:0]	rw	0x0	Integer clock delay of LT LINK 44
LT45	0xed	0x3b4	[3:0]	rw	0x0	Integer clock delay of LT LINK 45
LT46	0xee	0x3b8	[3:0]	rw	0x0	Integer clock delay of LT LINK 46
LT47	0xef	0x3bc	[3:0]	rw	0x0	Integer clock delay of LT LINK 47
LT48	0xf0	0x3c0	[3:0]	rw	0x0	Integer clock delay of LT LINK 48
LT49	0xf1	0x3c4	[3:0]	rw	0x0	Integer clock delay of LT LINK 49

MT.RB_READOUT_CNTS

Counters

Node	Adr	Adr8	Bits	Perm	Def	Description
CNTS_0	0xf2	0x3c8	[7:0]	r		Readout count on RB=0
CNTS_1	0xf2	0x3c8	[15:8]	r		Readout count on RB=1
CNTS_2	0xf2	0x3c8	[23:16]	r		Readout count on RB=2
CNTS_3	0xf2	0x3c8	[31:24]	r		Readout count on RB=3
CNTS_4	0xf3	0x3cc	[7:0]	r		Readout count on RB=4
CNTS_5	0xf3	0x3cc	[15:8]	r		Readout count on RB=5
CNTS_6	0xf3	0x3cc	[23:16]	r		Readout count on RB=6
CNTS_7	0xf3	0x3cc	[31:24]	r		Readout count on RB=7
CNTS_8	0xf4	0x3d0	[7:0]	r		Readout count on RB=8
CNTS_9	0xf4	0x3d0	[15:8]	r		Readout count on RB=9
CNTS_10	0xf4	0x3d0	[23:16]	r		Readout count on RB=10
CNTS_11	0xf4	0x3d0	[31:24]	r		Readout count on RB=11
CNTS_12	0xf5	0x3d4	[7:0]	r		Readout count on RB=12
CNTS_13	0xf5	0x3d4	[15:8]	r		Readout count on RB=13
CNTS_14	0xf5	0x3d4	[23:16]	r		Readout count on RB=14
CNTS_15	0xf5	0x3d4	[31:24]	r		Readout count on RB=15
CNTS_16	0xf6	0x3d8	[7:0]	r		Readout count on RB=16
CNTS_17	0xf6	0x3d8	[15:8]	r		Readout count on RB=17
CNTS_18	0xf6	0x3d8	[23:16]	r		Readout count on RB=18
CNTS_19	0xf6	0x3d8	[31:24]	r		Readout count on RB=19
CNTS_20	0xf7	0x3dc	[7:0]	r		Readout count on RB=20
CNTS_21	0xf7	0x3dc	[15:8]	r		Readout count on RB=21
CNTS_22	0xf7	0x3dc	[23:16]	r		Readout count on RB=22
CNTS_23	0xf7	0x3dc	[31:24]	r		Readout count on RB=23
CNTS_24	0xf8	0x3e0	[7:0]	r		Readout count on RB=24
CNTS_25	0xf8	0x3e0	[15:8]	r		Readout count on RB=25
CNTS_26	0xf8	0x3e0	[23:16]	r		Readout count on RB=26
CNTS_27	0xf8	0x3e0	[31:24]	r		Readout count on RB=27
CNTS_28	0xf9	0x3e4	[7:0]	r		Readout count on RB=28
CNTS_29	0xf9	0x3e4	[15:8]	r		Readout count on RB=29
CNTS_30	0xf9	0x3e4	[23:16]	r		Readout count on RB=30
CNTS_31	0xf9	0x3e4	[31:24]	r		Readout count on RB=31
CNTS_32	0xfa	0x3e8	[7:0]	r		Readout count on RB=32
CNTS_33	0xfa	0x3e8	[15:8]	r		Readout count on RB=33
CNTS_34	0xfa	0x3e8	[23:16]	r		Readout count on RB=34
CNTS_35	0xfa	0x3e8	[31:24]	r		Readout count on RB=35
CNTS_36	0xfb	0x3ec	[7:0]	r		Readout count on RB=36
CNTS_37	0xfb	0x3ec	[15:8]	r		Readout count on RB=37
CNTS_38	0xfb	0x3ec	[23:16]	r		Readout count on RB=38
CNTS_39	0xfb	0x3ec	[31:24]	r		Readout count on RB=39
CNTS_40	0xfc	0x3f0	[7:0]	r		Readout count on RB=40
CNTS_41	0xfc	0x3f0	[15:8]	r		Readout count on RB=41
CNTS_42	0xfc	0x3f0	[23:16]	r		Readout count on RB=42
CNTS_43	0xfc	0x3f0	[31:24]	r		Readout count on RB=43
CNTS_44	0xfd	0x3f4	[7:0]	r		Readout count on RB=44
CNTS_45	0xfd	0x3f4	[15:8]	r		Readout count on RB=45
CNTS_46	0xfd	0x3f4	[23:16]	r		Readout count on RB=46
CNTS_47	0xfd	0x3f4	[31:24]	r		Readout count on RB=47
CNTS_48	0xfe	0x3f8	[7:0]	r		Readout count on RB=48
CNTS_49	0xfe	0x3f8	[15:8]	r		Readout count on RB=49
RESET	0xff	0x3fc	0	w	Pulse	Write 1 to reset hit counters.
SNAP	0x100	0x400	0	rw	0x1	1 to snap the hit counters.

MT.PULSER

LTB Channel Pulser

Node	Adr	Adr8	Bits	Perm	Def	Description
FIRE	0x100	0x400	0	w	Pulse	Write 1 to Fire the Pulser.
CH_0_24	0x101	0x404	[24:0]	rw	0x0	Set fire bits for channels 0 to 24
CH_25_49	0x102	0x408	[24:0]	rw	0x0	Set fire bits for channels 25 to 49
CH_50_74	0x103	0x40c	[24:0]	rw	0x0	Set fire bits for channels 50 to 74
CH_75_99	0x104	0x410	[24:0]	rw	0x0	Set fire bits for channels 75 to 99
CH_100_124	0x105	0x414	[24:0]	rw	0x0	Set fire bits for channels 100 to 124
CH_125_149	0x106	0x418	[24:0]	rw	0x0	Set fire bits for channels 125 to 149
CH_150_174	0x107	0x41c	[24:0]	rw	0x0	Set fire bits for channels 150 to 174
CH_175_199	0x108	0x420	[24:0]	rw	0x0	Set fire bits for channels 175 to 199

MT

Implements various control and monitoring functions of the DRS Logic

Node	Adr	Adr8	Bits	Perm	Def	Description
TIU_BUSY_LENGTH	0x11f	0x47c	[31:0]	r		Length in 10ns cycles of the last TIU busy flag

MT.XADC

Zynq XADC

Node	Adr	Adr8	Bits	Perm	Def	Description
CALIBRATION	0x120	0x480	[11:0]	r		XADC Calibration
VCCPINT	0x120	0x480	[27:16]	r		XADC vccpint
VCCPAUX	0x121	0x484	[11:0]	r		XADC Calibration
VCCODDR	0x121	0x484	[27:16]	r		XADC vccoddr
TEMP	0x122	0x488	[11:0]	r		XADC Temperature
VCCINT	0x122	0x488	[27:16]	r		XADC vccint
VCCAUX	0x123	0x48c	[11:0]	r		XADC VCCAUX
VCCBRAM	0x123	0x48c	[27:16]	r		XADC vccbram

MT.HOG

HOG Parameters

Node	Adr	Adr8	Bits	Perm	Def	Description
GLOBAL_DATE	0x200	0x800	[31:0]	r		HOG Global Date
GLOBAL_TIME	0x201	0x804	[31:0]	r		HOG Global Time
GLOBAL_VER	0x202	0x808	[31:0]	r		HOG Global Version
GLOBAL_SHA	0x203	0x80c	[31:0]	r		HOG Global SHA
TOP_SHA	0x204	0x810	[31:0]	r		HOG Top SHA
TOP_VER	0x205	0x814	[31:0]	r		HOG Top Version
HOG_SHA	0x206	0x818	[31:0]	r		HOG SHA
HOG_VER	0x207	0x81c	[31:0]	r		HOG Version

MT

Implements various control and monitoring functions of the DRS Logic

Node	Adr	Adr8	Bits	Perm	Def	Description
TRIG_CYCLIC_EN	0x240	0x900	0	rw	0x0	Interval of cyclic triggers
TRIG_CYCLIC_INTERVAL	0x241	0x904	[31:0]	rw	0x0	Interval of cyclic triggers
LT_LINK_EN0	0x242	0x908	[9:0]	rw	0x3FF	DSI 0 RX Link Enable
LT_LINK_EN1	0x243	0x90c	[9:0]	rw	0x3FF	DSI 1 RX Link Enable
LT_LINK_EN2	0x244	0x910	[9:0]	rw	0x3FF	DSI 2 RX Link Enable
LT_LINK_EN3	0x245	0x914	[9:0]	rw	0x3FF	DSI 3 RX Link Enable
LT_LINK_EN4	0x246	0x918	[9:0]	rw	0x3FF	DSI 4 RX Link Enable
LT_LINK_AUTOMASK	0x247	0x91c	0	rw	0x1	1 to enable automatic LT link masking
GAPS_TRIG_PRESCALE	0x248	0x920	[31:0]	rw	0xFFFFFFFF	Prescale value for the GAPS trigger. 0 == 0% (off), 2**32-1 == 100%
TRACK_UMB_CENTRAL_PRESCALE	0x249	0x924	[31:0]	rw	0x0	Prescale value for the Umbrella Center + Cube Top Track Trigger. 0 == 0% (off), 2**32-1 == 100%

Module SPI adr = 0x1000

SPI

Node	Adr	Adr8	Bits	Perm	Def	Description
d0	0x1000	0x4000	[31:0]	rw	~~	Data reg 0
d1	0x1001	0x4004	[31:0]	rw	~~	Data reg 1
d2	0x1002	0x4008	[31:0]	rw	~~	Data reg 2
d3	0x1003	0x400c	[31:0]	rw	~~	Data reg 3
ctrl	0x1004	0x4010	[31:0]	rw	~~	Control reg
divider	0x1005	0x4014	[31:0]	rw	~~	Clock divider reg
ss	0x1006	0x4018	[31:0]	rw	~~	Slave select reg

Module I2C adr = 0x1100

I2C master controller

I2C

I2C master controller

Node	Adr	Adr8	Bits	Perm	Def	Description
ps_lo	0x1100	0x4400	[7:0]	rw	~~	Prescale low byte
ps_hi	0x1101	0x4404	[7:0]	rw	~~	Prescale low byte
ctrl	0x1102	0x4408	[7:0]	rw	~~	Control
data	0x1103	0x440c	[7:0]	rw	~~	Data
cmd_stat	0x1104	0x4410	[7:0]	rw	~~	Command / status

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