From 5800525cad722c69aa6e8fff23cee798b02c2a99 Mon Sep 17 00:00:00 2001 From: Woo Date: Thu, 22 Feb 2024 15:29:18 -0600 Subject: [PATCH] feat(CMSIS): Enable SPIXF cache controller (SFCC) by default in SystemInit for MAX32572 --- Libraries/CMSIS/Device/Maxim/MAX32572/Source/system_max32572.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Source/system_max32572.c b/Libraries/CMSIS/Device/Maxim/MAX32572/Source/system_max32572.c index d574018ea0a..7c73ec788ed 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Source/system_max32572.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Source/system_max32572.c @@ -122,6 +122,9 @@ __weak void SystemInit(void) /* Make sure interrupts are enabled. */ __enable_irq(); + /* Enable SPIXF cache */ + MXC_SFCC_Enable(); + /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */ /* Grant full access, per "Table B3-24 CPACR bit assignments". */ /* DDI0403D "ARMv7-M Architecture Reference Manual" */