From d162ea6de37a2b4b67e10d000998dbefcfdfa6d1 Mon Sep 17 00:00:00 2001 From: Andrea Bocci Date: Fri, 31 Jan 2025 10:28:00 +0100 Subject: [PATCH 1/7] Protect usage of __SYCL_TARGET macros --- include/alpaka/kernel/SyclSubgroupSize.hpp | 257 ++++++++++++++------- 1 file changed, 168 insertions(+), 89 deletions(-) diff --git a/include/alpaka/kernel/SyclSubgroupSize.hpp b/include/alpaka/kernel/SyclSubgroupSize.hpp index 1c7124b664b..e682c597935 100644 --- a/include/alpaka/kernel/SyclSubgroupSize.hpp +++ b/include/alpaka/kernel/SyclSubgroupSize.hpp @@ -6,104 +6,183 @@ # ifdef __SYCL_DEVICE_ONLY__ -# if(__SYCL_TARGET_INTEL_GPU_BDW__) || /* Broadwell Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_SKL__) || /* Skylake Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_KBL__) || /* Kaby Lake Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_CFL__) || /* Coffee Lake Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_APL__) || /* Apollo Lake Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_GLK__) || /* Gemini Lake Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_WHL__) || /* Whiskey Lake Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_AML__) || /* Amber Lake Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_CML__) || /* Comet Lake Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_ICLLP__) || /* Ice Lake Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_EHL__) || /* Elkhart Lake or Jasper Lake Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_TGLLP__) || /* Tiger Lake Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_RKL__) || /* Rocket Lake Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_ADL_S__) || /* Alder Lake S or Raptor Lake S Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_ADL_P__) || /* Alder Lake P Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_ADL_N__) || /* Alder Lake N Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_DG1__) || /* DG1 Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_ACM_G10__) || /* Alchemist G10 Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_ACM_G11__) || /* Alchemist G11 Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_ACM_G12__) || /* Alchemist G12 Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_MTL_U__) || /* Meteor Lake U/S or Arrow Lake U/S Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_MTL_H__) || /* Meteor Lake H Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_ARL_H__) || /* Arrow Lake H Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_BMG_G21__) || /* Battlemage G21 Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_LNL_M__) /* Lunar Lake Intel graphics architecture */ +# if /* Broadwell Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_BDW__) && __SYCL_TARGET_INTEL_GPU_BDW__) \ + || /* Skylake Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_SKL__) && __SYCL_TARGET_INTEL_GPU_SKL__) \ + || /* Kaby Lake Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_KBL__) && __SYCL_TARGET_INTEL_GPU_KBL__) \ + || /* Coffee Lake Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_CFL__) && __SYCL_TARGET_INTEL_GPU_CFL__) \ + || /* Apollo Lake Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_APL__) && __SYCL_TARGET_INTEL_GPU_APL__) \ + || /* Gemini Lake Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_GLK__) && __SYCL_TARGET_INTEL_GPU_GLK__) \ + || /* Whiskey Lake Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_WHL__) && __SYCL_TARGET_INTEL_GPU_WHL__) \ + || /* Amber Lake Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_AML__) && __SYCL_TARGET_INTEL_GPU_AML__) \ + || /* Comet Lake Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_CML__) && __SYCL_TARGET_INTEL_GPU_CML__) \ + || /* Ice Lake Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_ICLLP__) && __SYCL_TARGET_INTEL_GPU_ICLLP__) \ + || /* Elkhart Lake or Jasper Lake Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_EHL__) && __SYCL_TARGET_INTEL_GPU_EHL__) \ + || /* Tiger Lake Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_TGLLP__) && __SYCL_TARGET_INTEL_GPU_TGLLP__) \ + || /* Rocket Lake Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_RKL__) && __SYCL_TARGET_INTEL_GPU_RKL__) \ + || /* Alder Lake S or Raptor Lake S Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_ADL_S__) && __SYCL_TARGET_INTEL_GPU_ADL_S__) \ + || /* Alder Lake P Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_ADL_P__) && __SYCL_TARGET_INTEL_GPU_ADL_P__) \ + || /* Alder Lake N Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_ADL_N__) && __SYCL_TARGET_INTEL_GPU_ADL_N__) \ + || /* DG1 Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_DG1__) && __SYCL_TARGET_INTEL_GPU_DG1__) \ + || /* Alchemist G10 Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_ACM_G10__) && __SYCL_TARGET_INTEL_GPU_ACM_G10__) \ + || /* Alchemist G11 Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_ACM_G11__) && __SYCL_TARGET_INTEL_GPU_ACM_G11__) \ + || /* Alchemist G12 Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_ACM_G12__) && __SYCL_TARGET_INTEL_GPU_ACM_G12__) \ + || /* Meteor Lake U/S or Arrow Lake U/S Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_MTL_U__) && __SYCL_TARGET_INTEL_GPU_MTL_U__) \ + || /* Meteor Lake H Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_MTL_H__) && __SYCL_TARGET_INTEL_GPU_MTL_H__) \ + || /* Arrow Lake H Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_ARL_H__) && __SYCL_TARGET_INTEL_GPU_ARL_H__) \ + || /* Battlemage G21 Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_BMG_G21__) && __SYCL_TARGET_INTEL_GPU_BMG_G21__) \ + || /* Lunar Lake Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_LNL_M__) && __SYCL_TARGET_INTEL_GPU_LNL_M__) # define SYCL_SUBGROUP_SIZE (8 | 16 | 32) -# elif(__SYCL_TARGET_INTEL_GPU_PVC__) || /* Ponte Vecchio Intel graphics architecture */ \ - (__SYCL_TARGET_INTEL_GPU_PVC_VG__) /* Ponte Vecchio VG Intel graphics architecture */ +# elif /* Ponte Vecchio Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_PVC__) && __SYCL_TARGET_INTEL_GPU_PVC__) \ + || /* Ponte Vecchio VG Intel graphics architecture */ \ + (defined(__SYCL_TARGET_INTEL_GPU_PVC_VG__) && __SYCL_TARGET_INTEL_GPU_PVC_VG__) # define SYCL_SUBGROUP_SIZE (16 | 32) -# elif(__SYCL_TARGET_INTEL_X86_64__) /* generate code ahead of time for x86_64 CPUs */ +# elif(/* generate code ahead of time for x86_64 CPUs */ \ + defined(__SYCL_TARGET_INTEL_X86_64__) && __SYCL_TARGET_INTEL_X86_64__) # define SYCL_SUBGROUP_SIZE (4 | 8 | 16 | 32 | 64) -# elif(__SYCL_TARGET_NVIDIA_GPU_SM50__) || /* NVIDIA Maxwell architecture (compute capability 5.0) */ \ - (__SYCL_TARGET_NVIDIA_GPU_SM52__) || /* NVIDIA Maxwell architecture (compute capability 5.2) */ \ - (__SYCL_TARGET_NVIDIA_GPU_SM53__) || /* NVIDIA Jetson TX1 / Nano (compute capability 5.3) */ \ - (__SYCL_TARGET_NVIDIA_GPU_SM60__) || /* NVIDIA Pascal architecture (compute capability 6.0) */ \ - (__SYCL_TARGET_NVIDIA_GPU_SM61__) || /* NVIDIA Pascal architecture (compute capability 6.1) */ \ - (__SYCL_TARGET_NVIDIA_GPU_SM62__) || /* NVIDIA Jetson TX2 (compute capability 6.2) */ \ - (__SYCL_TARGET_NVIDIA_GPU_SM70__) || /* NVIDIA Volta architecture (compute capability 7.0) */ \ - (__SYCL_TARGET_NVIDIA_GPU_SM72__) || /* NVIDIA Jetson AGX (compute capability 7.2) */ \ - (__SYCL_TARGET_NVIDIA_GPU_SM75__) || /* NVIDIA Turing architecture (compute capability 7.5) */ \ - (__SYCL_TARGET_NVIDIA_GPU_SM80__) || /* NVIDIA Ampere architecture (compute capability 8.0) */ \ - (__SYCL_TARGET_NVIDIA_GPU_SM86__) || /* NVIDIA Ampere architecture (compute capability 8.6) */ \ - (__SYCL_TARGET_NVIDIA_GPU_SM87__) || /* NVIDIA Jetson/Drive AGX Orin (compute capability 8.7) */ \ - (__SYCL_TARGET_NVIDIA_GPU_SM89__) || /* NVIDIA Ada Lovelace arch. (compute capability 8.9) */ \ - (__SYCL_TARGET_NVIDIA_GPU_SM90__) /* NVIDIA Hopper architecture (compute capability 9.0) */ - -# define SYCL_SUBGROUP_SIZE (32) - -# elif(__SYCL_TARGET_AMD_GPU_GFX700__) || /* AMD GCN 2.0 Sea Islands architecture (gfx 7.0) */ \ - (__SYCL_TARGET_AMD_GPU_GFX701__) || /* AMD GCN 2.0 Sea Islands architecture (gfx 7.0) */ \ - (__SYCL_TARGET_AMD_GPU_GFX702__) || /* AMD GCN 2.0 Sea Islands architecture (gfx 7.0) */ \ - (__SYCL_TARGET_AMD_GPU_GFX801__) || /* AMD GCN 3.0 Volcanic Islands architecture (gfx 8.0) */ \ - (__SYCL_TARGET_AMD_GPU_GFX802__) || /* AMD GCN 3.0 Volcanic Islands architecture (gfx 8.0) */ \ - (__SYCL_TARGET_AMD_GPU_GFX803__) || /* AMD GCN 4.0 Arctic Islands architecture (gfx 8.0) */ \ - (__SYCL_TARGET_AMD_GPU_GFX805__) || /* AMD GCN 3.0 Volcanic Islands architecture (gfx 8.0) */ \ - (__SYCL_TARGET_AMD_GPU_GFX810__) || /* AMD GCN 3.0 Volcanic Islands architecture (gfx 8.1) */ \ - (__SYCL_TARGET_AMD_GPU_GFX900__) || /* AMD GCN 5.0 Vega architecture (gfx 9.0) */ \ - (__SYCL_TARGET_AMD_GPU_GFX902__) || /* AMD GCN 5.0 Vega architecture (gfx 9.0) */ \ - (__SYCL_TARGET_AMD_GPU_GFX904__) || /* AMD GCN 5.0 Vega architecture (gfx 9.0) */ \ - (__SYCL_TARGET_AMD_GPU_GFX906__) || /* AMD GCN 5.1 Vega II architecture (gfx 9.0) */ \ - (__SYCL_TARGET_AMD_GPU_GFX908__) || /* AMD CDNA 1.0 Arcturus architecture (gfx 9.0) */ \ - (__SYCL_TARGET_AMD_GPU_GFX909__) || /* AMD GCN 5.0 Raven 2 architecture (gfx 9.0) */ \ - (__SYCL_TARGET_AMD_GPU_GFX90A__) || /* AMD CDNA 2.0 Aldebaran architecture (gfx 9.0) */ \ - (__SYCL_TARGET_AMD_GPU_GFX90C__) || /* AMD GCN 5.1 Renoir architecture (gfx 9.0) */ \ - (__SYCL_TARGET_AMD_GPU_GFX940__) || /* AMD CDNA 3.0 Aqua Vanjaram architecture (gfx 9.4) */ \ - (__SYCL_TARGET_AMD_GPU_GFX941__) || /* AMD CDNA 3.0 Aqua Vanjaram architecture (gfx 9.4) */ \ - (__SYCL_TARGET_AMD_GPU_GFX942__) /* AMD CDNA 3.0 Aqua Vanjaram architecture (gfx 9.4) */ - -# define SYCL_SUBGROUP_SIZE (64) - -# elif(__SYCL_TARGET_AMD_GPU_GFX1010__) || /* AMD RDNA 1.0 Navi 10 architecture (gfx 10.1) */ \ - (__SYCL_TARGET_AMD_GPU_GFX1011__) || /* AMD RDNA 1.0 Navi 12 architecture (gfx 10.1) */ \ - (__SYCL_TARGET_AMD_GPU_GFX1012__) || /* AMD RDNA 1.0 Navi 14 architecture (gfx 10.1) */ \ - (__SYCL_TARGET_AMD_GPU_GFX1013__) || /* AMD RDNA 2.0 Oberon architecture (gfx 10.1) */ \ - (__SYCL_TARGET_AMD_GPU_GFX1030__) || /* AMD RDNA 2.0 Navi 21 architecture (gfx 10.3) */ \ - (__SYCL_TARGET_AMD_GPU_GFX1031__) || /* AMD RDNA 2.0 Navi 22 architecture (gfx 10.3) */ \ - (__SYCL_TARGET_AMD_GPU_GFX1032__) || /* AMD RDNA 2.0 Navi 23 architecture (gfx 10.3) */ \ - (__SYCL_TARGET_AMD_GPU_GFX1033__) || /* AMD RDNA 2.0 Van Gogh architecture (gfx 10.3) */ \ - (__SYCL_TARGET_AMD_GPU_GFX1034__) || /* AMD RDNA 2.0 Navi 24 architecture (gfx 10.3) */ \ - (__SYCL_TARGET_AMD_GPU_GFX1035__) || /* AMD RDNA 2.0 Rembrandt Mobile architecture (gfx 10.3) */ \ - (__SYCL_TARGET_AMD_GPU_GFX1036__) || /* AMD RDNA 2.0 Raphael architecture (gfx 10.3) */ \ - (__SYCL_TARGET_AMD_GPU_GFX1100__) || /* AMD RDNA 3.0 Navi 31 architecture (gfx 11.0) */ \ - (__SYCL_TARGET_AMD_GPU_GFX1101__) || /* AMD RDNA 3.0 Navi 32 architecture (gfx 11.0) */ \ - (__SYCL_TARGET_AMD_GPU_GFX1102__) || /* AMD RDNA 3.0 Navi 33 architecture (gfx 11.0) */ \ - (__SYCL_TARGET_AMD_GPU_GFX1103__) || /* AMD RDNA 3.0 Phoenix mobile architecture (gfx 11.0) */ \ - (__SYCL_TARGET_AMD_GPU_GFX1150__) || /* AMD RDNA 3.5 Strix Point architecture (gfx 11.5) */ \ - (__SYCL_TARGET_AMD_GPU_GFX1151__) || /* AMD RDNA 3.5 Strix Halo architecture (gfx 11.5) */ \ - (__SYCL_TARGET_AMD_GPU_GFX1200__) || /* AMD RDNA 4.0 Navi 44 architecture (gfx 12.0) */ \ - (__SYCL_TARGET_AMD_GPU_GFX1201__) /* AMD RDNA 4.0 Navi 48 architecture (gfx 12.0) */ - -// starting from gfx10, HIP supports only wavefront size 32 -# define SYCL_SUBGROUP_SIZE (32) +# elif /* NVIDIA Maxwell architecture (compute capability 5.0) */ \ + (defined(__SYCL_TARGET_NVIDIA_GPU_SM50__) && __SYCL_TARGET_NVIDIA_GPU_SM50__) \ + || /* NVIDIA Maxwell architecture (compute capability 5.2) */ \ + (defined(__SYCL_TARGET_NVIDIA_GPU_SM52__) && __SYCL_TARGET_NVIDIA_GPU_SM52__) \ + || /* NVIDIA Jetson TX1 / Nano (compute capability 5.3) */ \ + (defined(__SYCL_TARGET_NVIDIA_GPU_SM53__) && __SYCL_TARGET_NVIDIA_GPU_SM53__) \ + || /* NVIDIA Pascal architecture (compute capability 6.0) */ \ + (defined(__SYCL_TARGET_NVIDIA_GPU_SM60__) && __SYCL_TARGET_NVIDIA_GPU_SM60__) \ + || /* NVIDIA Pascal architecture (compute capability 6.1) */ \ + (defined(__SYCL_TARGET_NVIDIA_GPU_SM61__) && __SYCL_TARGET_NVIDIA_GPU_SM61__) \ + || /* NVIDIA Jetson TX2 (compute capability 6.2) */ \ + (defined(__SYCL_TARGET_NVIDIA_GPU_SM62__) && __SYCL_TARGET_NVIDIA_GPU_SM62__) \ + || /* NVIDIA Volta architecture (compute capability 7.0) */ \ + (defined(__SYCL_TARGET_NVIDIA_GPU_SM70__) && __SYCL_TARGET_NVIDIA_GPU_SM70__) \ + || /* NVIDIA Jetson AGX (compute capability 7.2) */ \ + (defined(__SYCL_TARGET_NVIDIA_GPU_SM72__) && __SYCL_TARGET_NVIDIA_GPU_SM72__) \ + || /* NVIDIA Turing architecture (compute capability 7.5) */ \ + (defined(__SYCL_TARGET_NVIDIA_GPU_SM75__) && __SYCL_TARGET_NVIDIA_GPU_SM75__) \ + || /* NVIDIA Ampere architecture (compute capability 8.0) */ \ + (defined(__SYCL_TARGET_NVIDIA_GPU_SM80__) && __SYCL_TARGET_NVIDIA_GPU_SM80__) \ + || /* NVIDIA Ampere architecture (compute capability 8.6) */ \ + (defined(__SYCL_TARGET_NVIDIA_GPU_SM86__) && __SYCL_TARGET_NVIDIA_GPU_SM86__) \ + || /* NVIDIA Jetson/Drive AGX Orin (compute capability 8.7) */ \ + (defined(__SYCL_TARGET_NVIDIA_GPU_SM87__) && __SYCL_TARGET_NVIDIA_GPU_SM87__) \ + || /* NVIDIA Ada Lovelace arch. (compute capability 8.9) */ \ + (defined(__SYCL_TARGET_NVIDIA_GPU_SM89__) && __SYCL_TARGET_NVIDIA_GPU_SM89__) \ + || /* NVIDIA Hopper architecture (compute capability 9.0) */ \ + (defined(__SYCL_TARGET_NVIDIA_GPU_SM90__) && __SYCL_TARGET_NVIDIA_GPU_SM90__) + +# define SYCL_SUBGROUP_SIZE (32) /* CUDA supports warp size 32 */ + +# elif /* AMD GCN 2.0 Sea Islands architecture (gfx 7.0) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX700__) && __SYCL_TARGET_AMD_GPU_GFX700__) \ + || /* AMD GCN 2.0 Sea Islands architecture (gfx 7.0) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX701__) && __SYCL_TARGET_AMD_GPU_GFX701__) \ + || /* AMD GCN 2.0 Sea Islands architecture (gfx 7.0) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX702__) && __SYCL_TARGET_AMD_GPU_GFX702__) \ + || /* AMD GCN 3.0 Volcanic Islands architecture (gfx 8.0) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX801__) && __SYCL_TARGET_AMD_GPU_GFX801__) \ + || /* AMD GCN 3.0 Volcanic Islands architecture (gfx 8.0) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX802__) && __SYCL_TARGET_AMD_GPU_GFX802__) \ + || /* AMD GCN 4.0 Arctic Islands architecture (gfx 8.0) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX803__) && __SYCL_TARGET_AMD_GPU_GFX803__) \ + || /* AMD GCN 3.0 Volcanic Islands architecture (gfx 8.0) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX805__) && __SYCL_TARGET_AMD_GPU_GFX805__) \ + || /* AMD GCN 3.0 Volcanic Islands architecture (gfx 8.1) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX810__) && __SYCL_TARGET_AMD_GPU_GFX810__) \ + || /* AMD GCN 5.0 Vega architecture (gfx 9.0) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX900__) && __SYCL_TARGET_AMD_GPU_GFX900__) \ + || /* AMD GCN 5.0 Vega architecture (gfx 9.0) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX902__) && __SYCL_TARGET_AMD_GPU_GFX902__) \ + || /* AMD GCN 5.0 Vega architecture (gfx 9.0) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX904__) && __SYCL_TARGET_AMD_GPU_GFX904__) \ + || /* AMD GCN 5.1 Vega II architecture (gfx 9.0) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX906__) && __SYCL_TARGET_AMD_GPU_GFX906__) \ + || /* AMD CDNA 1.0 Arcturus architecture (gfx 9.0) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX908__) && __SYCL_TARGET_AMD_GPU_GFX908__) \ + || /* AMD GCN 5.0 Raven 2 architecture (gfx 9.0) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX909__) && __SYCL_TARGET_AMD_GPU_GFX909__) \ + || /* AMD CDNA 2.0 Aldebaran architecture (gfx 9.0) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX90A__) && __SYCL_TARGET_AMD_GPU_GFX90A__) \ + || /* AMD GCN 5.1 Renoir architecture (gfx 9.0) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX90C__) && __SYCL_TARGET_AMD_GPU_GFX90C__) \ + || /* AMD CDNA 3.0 Aqua Vanjaram architecture (gfx 9.4) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX940__) && __SYCL_TARGET_AMD_GPU_GFX940__) \ + || /* AMD CDNA 3.0 Aqua Vanjaram architecture (gfx 9.4) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX941__) && __SYCL_TARGET_AMD_GPU_GFX941__) \ + || /* AMD CDNA 3.0 Aqua Vanjaram architecture (gfx 9.4) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX942__) && __SYCL_TARGET_AMD_GPU_GFX942__) + +# define SYCL_SUBGROUP_SIZE (64) /* up to gfx9, HIP supports wavefront size 64 */ + +# elif /* AMD RDNA 1.0 Navi 10 architecture (gfx 10.1) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX1010__) && __SYCL_TARGET_AMD_GPU_GFX1010__) \ + || /* AMD RDNA 1.0 Navi 12 architecture (gfx 10.1) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX1011__) && __SYCL_TARGET_AMD_GPU_GFX1011__) \ + || /* AMD RDNA 1.0 Navi 14 architecture (gfx 10.1) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX1012__) && __SYCL_TARGET_AMD_GPU_GFX1012__) \ + || /* AMD RDNA 2.0 Oberon architecture (gfx 10.1) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX1013__) && __SYCL_TARGET_AMD_GPU_GFX1013__) \ + || /* AMD RDNA 2.0 Navi 21 architecture (gfx 10.3) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX1030__) && __SYCL_TARGET_AMD_GPU_GFX1030__) \ + || /* AMD RDNA 2.0 Navi 22 architecture (gfx 10.3) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX1031__) && __SYCL_TARGET_AMD_GPU_GFX1031__) \ + || /* AMD RDNA 2.0 Navi 23 architecture (gfx 10.3) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX1032__) && __SYCL_TARGET_AMD_GPU_GFX1032__) \ + || /* AMD RDNA 2.0 Van Gogh architecture (gfx 10.3) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX1033__) && __SYCL_TARGET_AMD_GPU_GFX1033__) \ + || /* AMD RDNA 2.0 Navi 24 architecture (gfx 10.3) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX1034__) && __SYCL_TARGET_AMD_GPU_GFX1034__) \ + || /* AMD RDNA 2.0 Rembrandt Mobile architecture (gfx 10.3) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX1035__) && __SYCL_TARGET_AMD_GPU_GFX1035__) \ + || /* AMD RDNA 2.0 Raphael architecture (gfx 10.3) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX1036__) && __SYCL_TARGET_AMD_GPU_GFX1036__) \ + || /* AMD RDNA 3.0 Navi 31 architecture (gfx 11.0) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX1100__) && __SYCL_TARGET_AMD_GPU_GFX1100__) \ + || /* AMD RDNA 3.0 Navi 32 architecture (gfx 11.0) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX1101__) && __SYCL_TARGET_AMD_GPU_GFX1101__) \ + || /* AMD RDNA 3.0 Navi 33 architecture (gfx 11.0) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX1102__) && __SYCL_TARGET_AMD_GPU_GFX1102__) \ + || /* AMD RDNA 3.0 Phoenix mobile architecture (gfx 11.0) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX1103__) && __SYCL_TARGET_AMD_GPU_GFX1103__) \ + || /* AMD RDNA 3.5 Strix Point architecture (gfx 11.5) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX1150__) && __SYCL_TARGET_AMD_GPU_GFX1150__) \ + || /* AMD RDNA 3.5 Strix Halo architecture (gfx 11.5) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX1151__) && __SYCL_TARGET_AMD_GPU_GFX1151__) \ + || /* AMD RDNA 4.0 Navi 44 architecture (gfx 12.0) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX1200__) && __SYCL_TARGET_AMD_GPU_GFX1200__) \ + || /* AMD RDNA 4.0 Navi 48 architecture (gfx 12.0) */ \ + (defined(__SYCL_TARGET_AMD_GPU_GFX1201__) && __SYCL_TARGET_AMD_GPU_GFX1201__) + +# define SYCL_SUBGROUP_SIZE (32) /* starting from gfx10, HIP supports wavefront size 32 */ # else // __SYCL_TARGET_* From 1279b4500f1a6bd318c8ecd8cdeff2d625359bb2 Mon Sep 17 00:00:00 2001 From: Andrea Bocci Date: Fri, 31 Jan 2025 11:10:30 +0100 Subject: [PATCH 2/7] Use explicit -Xsycl-target-backend for SYCL back-end options --- cmake/alpakaCommon.cmake | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/cmake/alpakaCommon.cmake b/cmake/alpakaCommon.cmake index 7c2ac35515e..aa905d36093 100644 --- a/cmake/alpakaCommon.cmake +++ b/cmake/alpakaCommon.cmake @@ -726,14 +726,14 @@ if(alpaka_ACC_SYCL_ENABLE) if(alpaka_SYCL_ONEAPI_FPGA_MODE STREQUAL "emulation") target_compile_definitions(alpaka INTERFACE "ALPAKA_FPGA_EMULATION") - alpaka_set_compiler_options(DEVICE target alpaka "-Xsemulator") - target_link_options(alpaka INTERFACE "-Xsemulator") + alpaka_set_compiler_options(DEVICE target alpaka "-Xsycl-target-backend=${alpaka_SYCL_ONEAPI_FPGA_TARGET}" "-emulator") + target_link_options(alpaka INTERFACE "-Xsycl-target-backend=${alpaka_SYCL_ONEAPI_FPGA_TARGET}" "-emulator") elseif(alpaka_SYCL_ONEAPI_FPGA_MODE STREQUAL "simulation") - alpaka_set_compiler_options(DEVICE target alpaka "-Xssimulation") - target_link_options(alpaka INTERFACE "-Xssimulation") + alpaka_set_compiler_options(DEVICE target alpaka "-Xsycl-target-backend=${alpaka_SYCL_ONEAPI_FPGA_TARGET}" "-simulation") + target_link_options(alpaka INTERFACE "-Xsycl-target-backend=${alpaka_SYCL_ONEAPI_FPGA_TARGET}" "-simulation") elseif(alpaka_SYCL_ONEAPI_FPGA_MODE STREQUAL "hardware") - alpaka_set_compiler_options(DEVICE target alpaka "-Xshardware") - target_link_options(alpaka INTERFACE "-Xshardware") + alpaka_set_compiler_options(DEVICE target alpaka "-Xsycl-target-backend=${alpaka_SYCL_ONEAPI_FPGA_TARGET}" "-hardware") + target_link_options(alpaka INTERFACE "-Xsycl-target-backend=${alpaka_SYCL_ONEAPI_FPGA_TARGET}" "-hardware") endif() if(NOT alpaka_SYCL_ONEAPI_FPGA_MODE STREQUAL "emulation") @@ -742,7 +742,7 @@ if(alpaka_ACC_SYCL_ENABLE) set(alpaka_SYCL_ONEAPI_FPGA_BSP "intel_a10gx_pac" CACHE STRING "Path to or name of the Intel FPGA board support package") set_property(CACHE alpaka_SYCL_ONEAPI_FPGA_BSP PROPERTY STRINGS "intel_a10gx_pac;intel_s10sx_pac") - target_link_options(alpaka INTERFACE "-Xsycl-target-backend=${alpaka_SYCL_ONEAPI_FPGA_TARGET} \"-board=${alpaka_SYCL_ONEAPI_FPGA_BSP}:${alpaka_SYCL_ONEAPI_FPGA_BOARD}\"") + target_link_options(alpaka INTERFACE "-Xsycl-target-backend=${alpaka_SYCL_ONEAPI_FPGA_TARGET}" "-board=${alpaka_SYCL_ONEAPI_FPGA_BSP}:${alpaka_SYCL_ONEAPI_FPGA_BOARD}") endif() endif() From 108a523e1c51fab158bb02c646e67bc9654427ab Mon Sep 17 00:00:00 2001 From: Andrea Bocci Date: Fri, 31 Jan 2025 11:10:54 +0100 Subject: [PATCH 3/7] Install the oneAPI FPGA support package --- script/install_oneapi.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/script/install_oneapi.sh b/script/install_oneapi.sh index 0159d2a16a6..8664430de4b 100755 --- a/script/install_oneapi.sh +++ b/script/install_oneapi.sh @@ -36,7 +36,7 @@ else components=( intel-oneapi-common-vars # Contains /opt/intel/oneapi/setvars.sh - has no version number intel-oneapi-compiler-dpcpp-cpp-"${ALPAKA_CI_ONEAPI_VERSION}" # Contains icpx compiler and SYCL runtime - intel-oneapi-runtime-opencl # Required to run SYCL tests on the CPU - has no version number + intel-oneapi-compiler-fpga-"${ALPAKA_CI_ONEAPI_VERSION}" # Containes the FPGA support package ) travis_retry sudo apt-get install -y "${components[@]}" From 6ae7a30c6f3459ba95688faf2082720ec880fee0 Mon Sep 17 00:00:00 2001 From: Andrea Bocci Date: Sun, 26 Jan 2025 19:37:38 +0100 Subject: [PATCH 4/7] Gitlab CI: enable the SYCL FPGA emulation backend --- script/before_install.sh | 4 ++++ script/job_generator/generate_job_yaml.py | 4 ++++ script/run_generate.sh | 1 + 3 files changed, 9 insertions(+) diff --git a/script/before_install.sh b/script/before_install.sh index 68b748a24f4..3180117a44f 100755 --- a/script/before_install.sh +++ b/script/before_install.sh @@ -115,6 +115,10 @@ if [ "${alpaka_ACC_SYCL_ENABLE}" == "OFF" ]; then echo_yellow "" export alpaka_SYCL_ONEAPI_CPU=${alpaka_SYCL_ONEAPI_CPU:=""} export alpaka_SYCL_ONEAPI_CPU_ISA=${alpaka_SYCL_ONEAPI_CPU_ISA:=""} + export alpaka_SYCL_ONEAPI_FPGA=${alpaka_SYCL_ONEAPI_FPGA:=""} + export alpaka_SYCL_ONEAPI_FPGA_MODE=${alpaka_SYCL_ONEAPI_FPGA_MODE:=""} + export alpaka_SYCL_ONEAPI_FPGA_BOARD=${alpaka_SYCL_ONEAPI_FPGA_BOARD:=""} + export alpaka_SYCL_ONEAPI_FPGA_BSP=${alpaka_SYCL_ONEAPI_FPGA_BSP:=""} fi #------------------------------------------------------------------------------- diff --git a/script/job_generator/generate_job_yaml.py b/script/job_generator/generate_job_yaml.py index bca6e9f6c71..8712b12d4f0 100644 --- a/script/job_generator/generate_job_yaml.py +++ b/script/job_generator/generate_job_yaml.py @@ -391,6 +391,10 @@ def job_variables(job: Dict[str, Tuple[str, str]]) -> Dict[str, str]: variables["ALPAKA_CI_ONEAPI_VERSION"] = job[DEVICE_COMPILER][VERSION] variables["alpaka_SYCL_ONEAPI_CPU"] = "ON" variables["alpaka_SYCL_ONEAPI_CPU_ISA"] = "avx2" + variables["alpaka_SYCL_ONEAPI_FPGA"] = "ON" + variables["alpaka_SYCL_ONEAPI_FPGA_MODE"] = "emulation" + variables["alpaka_SYCL_ONEAPI_FPGA_BOARD"] = "" + variables["alpaka_SYCL_ONEAPI_FPGA_BSP"] = "" return variables diff --git a/script/run_generate.sh b/script/run_generate.sh index 7f527b79e45..381f8b1db83 100755 --- a/script/run_generate.sh +++ b/script/run_generate.sh @@ -101,6 +101,7 @@ cd build/ $(env2cmake alpaka_CUDA_SHOW_REGISTER) $(env2cmake alpaka_CUDA_KEEP_FILES) $(env2cmake alpaka_CUDA_EXPT_EXTENDED_LAMBDA) \ $(env2cmake alpaka_ACC_GPU_HIP_ENABLE) $(env2cmake alpaka_ACC_GPU_HIP_ONLY_MODE) $(env2cmake CMAKE_HIP_ARCHITECTURES) $(env2cmake CMAKE_HIP_COMPILER) "$(env2cmake CMAKE_HIP_FLAGS)" \ $(env2cmake alpaka_ACC_SYCL_ENABLE) $(env2cmake alpaka_SYCL_ONEAPI_CPU) $(env2cmake alpaka_SYCL_ONEAPI_CPU_ISA) \ + $(env2cmake alpaka_SYCL_ONEAPI_FPGA) $(env2cmake alpaka_SYCL_ONEAPI_FPGA_MODE) $(env2cmake alpaka_SYCL_ONEAPI_FPGA_BOARD) "$(env2cmake alpaka_SYCL_ONEAPI_FPGA_BSP)" \ $(env2cmake alpaka_DEBUG) $(env2cmake alpaka_CI) $(env2cmake alpaka_CHECK_HEADERS) $(env2cmake alpaka_CXX_STANDARD) $(env2cmake alpaka_USE_MDSPAN) $(env2cmake CMAKE_INSTALL_PREFIX) \ .. From d5c43977068cdf8be0c3d1f1bc3475a67a61d0db Mon Sep 17 00:00:00 2001 From: Simeon Ehrig Date: Tue, 4 Feb 2025 13:11:53 +0100 Subject: [PATCH 5/7] CI job generator: generate for each SYCL job a CPU and FPGA version --- script/job_generator/alpaka_globals.py | 5 ++++ script/job_generator/generate_job_yaml.py | 19 ++++++++++----- script/job_generator/job_generator.py | 4 +++- script/job_generator/job_modifier.py | 28 +++++++++++++++++++++++ 4 files changed, 49 insertions(+), 7 deletions(-) diff --git a/script/job_generator/alpaka_globals.py b/script/job_generator/alpaka_globals.py index 1ca7d8fc2e0..9fbd2a6816f 100644 --- a/script/job_generator/alpaka_globals.py +++ b/script/job_generator/alpaka_globals.py @@ -26,3 +26,8 @@ # enable mdspan support MDSPAN: str = "mdspan" + +# enabled device for Intel SYCL backend +SYCL_DEVICE: str = "sycl_device" +SYCL_CPU: str = "sycl_cpu" +SYCL_FPGA: str = "sycl_fpga" diff --git a/script/job_generator/generate_job_yaml.py b/script/job_generator/generate_job_yaml.py index 8712b12d4f0..dc35ae84779 100644 --- a/script/job_generator/generate_job_yaml.py +++ b/script/job_generator/generate_job_yaml.py @@ -389,12 +389,14 @@ def job_variables(job: Dict[str, Tuple[str, str]]) -> Dict[str, str]: variables["ALPAKA_CI_CLANG_VER"] = "19" variables["ALPAKA_CI_STDLIB"] = "libstdc++" variables["ALPAKA_CI_ONEAPI_VERSION"] = job[DEVICE_COMPILER][VERSION] - variables["alpaka_SYCL_ONEAPI_CPU"] = "ON" - variables["alpaka_SYCL_ONEAPI_CPU_ISA"] = "avx2" - variables["alpaka_SYCL_ONEAPI_FPGA"] = "ON" - variables["alpaka_SYCL_ONEAPI_FPGA_MODE"] = "emulation" - variables["alpaka_SYCL_ONEAPI_FPGA_BOARD"] = "" - variables["alpaka_SYCL_ONEAPI_FPGA_BSP"] = "" + if job[SYCL_DEVICE][NAME] == SYCL_CPU: + variables["alpaka_SYCL_ONEAPI_CPU"] = "ON" + variables["alpaka_SYCL_ONEAPI_CPU_ISA"] = "avx2" + if job[SYCL_DEVICE][NAME] == SYCL_FPGA: + variables["alpaka_SYCL_ONEAPI_FPGA"] = "ON" + variables["alpaka_SYCL_ONEAPI_FPGA_MODE"] = "emulation" + variables["alpaka_SYCL_ONEAPI_FPGA_BOARD"] = "" + variables["alpaka_SYCL_ONEAPI_FPGA_BSP"] = "" return variables @@ -487,6 +489,11 @@ def create_job(job: Dict[str, Tuple[str, str]], container_version: float, gitlab if job[DEVICE_COMPILER][NAME] == CLANG_CUDA: job_name = job_name + "-cuda" + job[ALPAKA_ACC_GPU_CUDA_ENABLE][VERSION] + if job[SYCL_DEVICE][NAME] == SYCL_CPU: + job_name = job_name + "-cpu" + if job[SYCL_DEVICE][NAME] == SYCL_FPGA: + job_name = job_name + "-fpga" + if job[JOB_EXECUTION_TYPE][VERSION] == JOB_EXECUTION_COMPILE_ONLY: job_name += "_compile_only" diff --git a/script/job_generator/job_generator.py b/script/job_generator/job_generator.py index d079d59c08f..37ebf6c5965 100644 --- a/script/job_generator/job_generator.py +++ b/script/job_generator/job_generator.py @@ -31,7 +31,7 @@ JOB_UNKNOWN, WAVE_GROUP_NAMES, ) -from job_modifier import add_job_parameters +from job_modifier import add_job_parameters, add_sycl_fpga_jobs from verify import verify, verify_parameters from util import print_warn @@ -139,6 +139,8 @@ def get_args() -> argparse.Namespace: ) add_job_parameters(job_matrix) + + job_matrix = add_sycl_fpga_jobs(job_matrix) if args.print_combinations or args.all: print(f"number of combinations before reorder: {len(job_matrix)}") diff --git a/script/job_generator/job_modifier.py b/script/job_generator/job_modifier.py index 7eac92a54fc..8cf2d2ef393 100644 --- a/script/job_generator/job_modifier.py +++ b/script/job_generator/job_modifier.py @@ -135,3 +135,31 @@ def add_job_parameters(job_matrix: List[Dict[str, Tuple[str, str]]]): for job in job_matrix: if job[DEVICE_COMPILER][NAME] in [GCC, CLANG, ICPX]: job[JOB_EXECUTION_TYPE] = (JOB_EXECUTION_TYPE, JOB_EXECUTION_RUNTIME) + + +def add_sycl_fpga_jobs(job_matrix: List[Dict[str, Tuple[str, str]]]) -> List[Dict[str, Tuple[str, str]]]: + """Duplicate each job with enabled backend ALPAKA_ACC_SYCL_ENABLE and set + the SYCL_DEVICE to SYCL_CPU for the first and SYCL_FPGA for the second job. + All other jobs get a neutral SYCL_DEVICE entry. + + Args: + job_matrix (List[Dict[str, Tuple[str, str]]]): Job matrix + Return: + (List[Dict[str, Tuple[str, str]]]): Job matrix with duplicated and + extended jobs + """ + extended_job_matrix = [] + + for job in job_matrix: + if ALPAKA_ACC_SYCL_ENABLE in job: + for enabled_device in (SYCL_CPU, SYCL_FPGA): + extended_job = job.copy() + extended_job[SYCL_DEVICE] = (enabled_device, ON) + extended_job_matrix.append(extended_job) + else: + job[SYCL_DEVICE] = ("", "") + extended_job_matrix.append(job) + + + + return extended_job_matrix From 2ab700a1fe6ddaf684bd15a2f39fa5f9d12508e7 Mon Sep 17 00:00:00 2001 From: Simeon Ehrig Date: Tue, 4 Feb 2025 15:21:36 +0100 Subject: [PATCH 6/7] CI: extend default variables for enabled SYCL backend and disabled CPU or FPGA CI_FILTER: ^linux_icpx --- script/before_install.sh | 21 +++++++++++++++++++++ script/job_generator/generate_job_yaml.py | 2 ++ 2 files changed, 23 insertions(+) diff --git a/script/before_install.sh b/script/before_install.sh index 3180117a44f..02f261353ed 100755 --- a/script/before_install.sh +++ b/script/before_install.sh @@ -119,6 +119,27 @@ if [ "${alpaka_ACC_SYCL_ENABLE}" == "OFF" ]; then export alpaka_SYCL_ONEAPI_FPGA_MODE=${alpaka_SYCL_ONEAPI_FPGA_MODE:=""} export alpaka_SYCL_ONEAPI_FPGA_BOARD=${alpaka_SYCL_ONEAPI_FPGA_BOARD:=""} export alpaka_SYCL_ONEAPI_FPGA_BSP=${alpaka_SYCL_ONEAPI_FPGA_BSP:=""} +else + if !( [ "$alpaka_SYCL_ONEAPI_CPU" == "ON" ] || [ "$alpaka_SYCL_ONEAPI_FPGA" == "ON" ] ); then + echo_red "ERROR: the SYCL CPU or FPGA device needs to enabled" + exit 1 + fi + + if [ "$alpaka_SYCL_ONEAPI_CPU" == "ON" ] && [ "$alpaka_SYCL_ONEAPI_FPGA" == "ON" ]; then + echo_red "ERROR: the SYCL CPU or FPGA device cannot be enabled at the same time" + exit 1 + fi + + if [ "$alpaka_SYCL_ONEAPI_CPU" == "OFF" ]; then + echo_yellow "" + export alpaka_SYCL_ONEAPI_CPU_ISA="" + fi + if [ "$alpaka_SYCL_ONEAPI_FPGA" == "OFF" ]; then + echo_yellow "" + export alpaka_SYCL_ONEAPI_FPGA_MODE="" + export alpaka_SYCL_ONEAPI_FPGA_BOARD="" + export alpaka_SYCL_ONEAPI_FPGA_BSP="" + fi fi #------------------------------------------------------------------------------- diff --git a/script/job_generator/generate_job_yaml.py b/script/job_generator/generate_job_yaml.py index dc35ae84779..626057f8884 100644 --- a/script/job_generator/generate_job_yaml.py +++ b/script/job_generator/generate_job_yaml.py @@ -389,6 +389,8 @@ def job_variables(job: Dict[str, Tuple[str, str]]) -> Dict[str, str]: variables["ALPAKA_CI_CLANG_VER"] = "19" variables["ALPAKA_CI_STDLIB"] = "libstdc++" variables["ALPAKA_CI_ONEAPI_VERSION"] = job[DEVICE_COMPILER][VERSION] + variables["alpaka_SYCL_ONEAPI_CPU"] = "OFF" + variables["alpaka_SYCL_ONEAPI_FPGA"] = "OFF" if job[SYCL_DEVICE][NAME] == SYCL_CPU: variables["alpaka_SYCL_ONEAPI_CPU"] = "ON" variables["alpaka_SYCL_ONEAPI_CPU_ISA"] = "avx2" From 0534c309f5d8e24324d3149ad8005aae8d126aef Mon Sep 17 00:00:00 2001 From: Simeon Ehrig Date: Tue, 18 Feb 2025 11:16:23 +0100 Subject: [PATCH 7/7] disable SYCL FPGA debug build tests --- script/job_generator/job_modifier.py | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/script/job_generator/job_modifier.py b/script/job_generator/job_modifier.py index 8cf2d2ef393..a68ee2aa829 100644 --- a/script/job_generator/job_modifier.py +++ b/script/job_generator/job_modifier.py @@ -152,9 +152,14 @@ def add_sycl_fpga_jobs(job_matrix: List[Dict[str, Tuple[str, str]]]) -> List[Dic for job in job_matrix: if ALPAKA_ACC_SYCL_ENABLE in job: - for enabled_device in (SYCL_CPU, SYCL_FPGA): + extended_job = job.copy() + extended_job[SYCL_DEVICE] = (SYCL_CPU, ON) + extended_job_matrix.append(extended_job) + # TODO: a bug in the blockSharedSharingTest disallow testing the + # SYCL FPGA backend in debug mode + if job[BUILD_TYPE][VERSION] == CMAKE_RELEASE: extended_job = job.copy() - extended_job[SYCL_DEVICE] = (enabled_device, ON) + extended_job[SYCL_DEVICE] = (SYCL_FPGA, ON) extended_job_matrix.append(extended_job) else: job[SYCL_DEVICE] = ("", "")