-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathBasicMCUInFPGA.qsf
109 lines (107 loc) · 5.27 KB
/
BasicMCUInFPGA.qsf
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2016 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
# Date created = 16:50:48 April 12, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# BasicMCUInFPGA_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C7
set_global_assignment -name TOP_LEVEL_ENTITY BasicMCUInFPGA
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:50:48 APRIL 12, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_Y2 -to clk
set_location_assignment PIN_F17 -to stuck
set_location_assignment PIN_G19 -to digitalIO[0]
set_location_assignment PIN_F19 -to digitalIO[1]
set_location_assignment PIN_E19 -to digitalIO[2]
set_location_assignment PIN_F21 -to digitalIO[3]
set_location_assignment PIN_F18 -to digitalIO[4]
set_location_assignment PIN_E18 -to digitalIO[5]
set_location_assignment PIN_J19 -to digitalIO[6]
set_location_assignment PIN_H19 -to digitalIO[7]
set_location_assignment PIN_J17 -to digitalIO[8]
set_location_assignment PIN_G17 -to digitalIO[9]
set_location_assignment PIN_J15 -to digitalIO[10]
set_location_assignment PIN_H16 -to digitalIO[11]
set_location_assignment PIN_J16 -to digitalIO[12]
set_location_assignment PIN_F15 -to digitalIO[14]
set_location_assignment PIN_H17 -to digitalIO[13]
set_location_assignment PIN_G15 -to digitalIO[15]
set_location_assignment PIN_M23 -to butt
set_location_assignment PIN_E22 -to debug[1]
set_location_assignment PIN_E25 -to debug[2]
set_location_assignment PIN_E24 -to debug[3]
set_location_assignment PIN_E21 -to debug[0]
set_location_assignment PIN_G20 -to debug[5]
set_location_assignment PIN_G22 -to debug[6]
set_location_assignment PIN_G21 -to debug[7]
set_location_assignment PIN_H21 -to debug[4]
set_location_assignment PIN_G12 -to RXD
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VERILOG_FILE BasicMCUInFPGA.v
set_global_assignment -name VERILOG_FILE registerFile.v
set_global_assignment -name QIP_FILE Flash.qip
set_global_assignment -name QIP_FILE RAM.qip
set_global_assignment -name VERILOG_FILE instuctionSelector.v
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
set_global_assignment -name VERILOG_FILE debouncer.v
set_global_assignment -name VERILOG_FILE ClockDownscaler.v
set_global_assignment -name VERILOG_FILE UART.v
set_location_assignment PIN_M21 -to buttProg
set_location_assignment PIN_R24 -to reset
set_location_assignment PIN_H15 -to progMode
set_location_assignment PIN_AC28 -to inputs[1]
set_location_assignment PIN_AC27 -to inputs[2]
set_location_assignment PIN_AD27 -to inputs[3]
set_location_assignment PIN_AB27 -to inputs[4]
set_location_assignment PIN_AC26 -to inputs[5]
set_location_assignment PIN_AD26 -to inputs[6]
set_location_assignment PIN_AB26 -to inputs[7]
set_location_assignment PIN_AB28 -to inputs[0]
set_global_assignment -name VERILOG_FILE outputShifter.v
set_location_assignment PIN_G9 -to TXD
set_global_assignment -name VERILOG_FILE packetSende.v
set_location_assignment PIN_Y23 -to enableProg
set_global_assignment -name CDF_FILE output_files/Chain2.cdf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top