From 31aa018a6425e5ce8681325b2a6e8aa101ba53c2 Mon Sep 17 00:00:00 2001 From: Martin Zabel Date: Sat, 29 Oct 2016 00:36:58 +0200 Subject: [PATCH 01/97] Fixed submodule hashes. --- lib/cocotb | 2 +- lib/osvvm | 2 +- lib/vunit | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/cocotb b/lib/cocotb index 50df6e58..4391cdfe 160000 --- a/lib/cocotb +++ b/lib/cocotb @@ -1 +1 @@ -Subproject commit 50df6e58aeb8727d5d1f54339a90f0871c2fabc6 +Subproject commit 4391cdfe3b15e25c4b26c1ffa6b5837d13718ca6 diff --git a/lib/osvvm b/lib/osvvm index 407080c7..c3f8221b 160000 --- a/lib/osvvm +++ b/lib/osvvm @@ -1 +1 @@ -Subproject commit 407080c785e709f1e491e28c84e2d44f75c94d16 +Subproject commit c3f8221b891f0d03d7cf3477a0dc41c2e3b068b5 diff --git a/lib/vunit b/lib/vunit index 1e134142..48c9aaec 160000 --- a/lib/vunit +++ b/lib/vunit @@ -1 +1 @@ -Subproject commit 1e1341425b1988bcc97606a88ae43becdabb4290 +Subproject commit 48c9aaecb5d786b1fee680bb064b75664627c975 From bf59149c3061253ca01589bd14637255224aa744 Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Sat, 29 Oct 2016 23:59:43 +0200 Subject: [PATCH 02/97] Silence modelsim warnings for physical.vhdl --- src/common/physical.vhdl | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/common/physical.vhdl b/src/common/physical.vhdl index b9ec2d52..35d13135 100644 --- a/src/common/physical.vhdl +++ b/src/common/physical.vhdl @@ -382,6 +382,7 @@ package body physical is else report "to_baud: Unknown format" severity FAILURE; end if; + return 0 Bd; end function; -- inter-type arithmetic @@ -795,6 +796,7 @@ package body physical is elsif (scale = 1 ms) then return div(t, 1 ms); elsif (scale = 1 sec) then return div(t, 1 sec); else report "to_real: scale must have a value of '1 '" severity failure; + return 0.0; end if; end; @@ -807,6 +809,7 @@ package body physical is -- elsif (scale = 1 THz) then return div(f, 1 THz); else report "to_real: scale must have a value of '1 '" severity failure; end if; + return 0.0; end; function to_real(br : BAUD; scale : BAUD) return REAL is @@ -817,6 +820,7 @@ package body physical is elsif (scale = 1 GBd) then return div(br, 1 GBd); else report "to_real: scale must have a value of '1 '" severity failure; end if; + return 0.0; end; function to_real(mem : MEMORY; scale : MEMORY) return REAL is @@ -827,6 +831,7 @@ package body physical is elsif (scale = 1 GiB) then return div(mem, 1 GiB); else report "to_real: scale must have a value of '1 '" severity failure; end if; + return 0.0; end; -- convert physical types to standard type (INTEGER) @@ -840,6 +845,7 @@ package body physical is when others => null; end case; report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure; + return 0; end; function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer is @@ -851,6 +857,7 @@ package body physical is when others => null; end case; report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure; + return 0; end; function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer is @@ -862,6 +869,7 @@ package body physical is when others => null; end case; report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure; + return 0; end; function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return integer is @@ -873,6 +881,7 @@ package body physical is when others => null; end case; report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure; + return 0; end; -- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period From d7e7bf98ec204fb9ec4a188a50900b2fb3ccd212 Mon Sep 17 00:00:00 2001 From: Martin Zabel Date: Tue, 1 Nov 2016 18:20:39 +0100 Subject: [PATCH 03/97] Fixed cache_par_cocotb.py: Allow meta-values while receiving from output monitor. --- tb/cache/cache_par_cocotb.py | 62 ++++++++++++++++++++++++++---------- 1 file changed, 45 insertions(+), 17 deletions(-) diff --git a/tb/cache/cache_par_cocotb.py b/tb/cache/cache_par_cocotb.py index bbc196cc..19642118 100644 --- a/tb/cache/cache_par_cocotb.py +++ b/tb/cache/cache_par_cocotb.py @@ -59,8 +59,9 @@ class InputDriver(BusDriver): def __init__(self, dut): BusDriver.__init__(self, dut, None, dut.Clock) + class InputTransaction(object): - """Creates transaction to be send by InputDriver""" + """Transaction to be send by InputDriver""" def __init__(self, tb, request=0, readWrite=0, invalidate=0, replace=0, address=0, cacheLineIn=0): "tb must be an instance of the Testbench class" if (replace==1) and ((request==1) or (invalidate==1)): @@ -74,6 +75,34 @@ def __init__(self, tb, request=0, readWrite=0, invalidate=0, replace=0, address= self.Address = BinaryValue(address, tb.address_bits, False) self.CacheLineIn = BinaryValue(cacheLineIn, tb.data_bits, False) + +class OutputTransaction(object): + """Transaction to be expected / received by OutputMonitor.""" + def __init__(self, tb=None, cacheLineOut=None, cacheHit=0, cacheMiss=0, oldAddress=None): + """For expected transactions, value 'None' means don't care. tb must be an instance of the Testbench class.""" + if cacheLineOut is not None and isinstance(cacheLineOut, int): cacheLineOut = BinaryValue(cacheLineOut, tb.data_bits, False) + if cacheHit is not None and isinstance(cacheHit, int): cacheHit = BinaryValue(cacheHit, 1) + if cacheMiss is not None and isinstance(cacheMiss, int): cacheMiss = BinaryValue(cacheMiss, 1) + if oldAddress is not None and isinstance(oldAddress, int): oldAddress = BinaryValue(oldAddress, tb.address_bits, False) + self.value = (cacheLineOut, cacheHit, cacheMiss, oldAddress) + + def __eq__(self, other): + if not isinstance(other, OutputTransaction): + raise ValueError("Other value in comparison is not an OutputTransaction, was {0!s} instead.".format(type(other))) + + equal = True + for i, val1 in enumerate(self.value): + val2 = other.value[i] + if val1 is not None and val2 is not None: + if val1 != val2: equal = False + return equal + + def __ne__(self, other): + return not self.__eq__(other) + + def __str__(self): + return ", ".join([str(i) for i in self.value]) + # ============================================================================== class InputMonitor(BusMonitor): """Observes inputs of DUT.""" @@ -103,9 +132,11 @@ class OutputMonitor(BusMonitor): """Observes outputs of DUT.""" _signals = [ "CacheLineOut", "CacheHit", "CacheMiss", "OldAddress" ] - def __init__(self, dut, callback=None, event=None): + def __init__(self, dut, tb, callback=None, event=None): + """tb must be an instance of the Testbench class.""" BusMonitor.__init__(self, dut, None, dut.Clock, dut.Reset, callback=callback, event=event) self.name = "out" + self.tb = tb @coroutine def _monitor_recv(self): @@ -115,23 +146,19 @@ def _monitor_recv(self): # Capture signals at rising-edge of clock. yield clkedge - - vec = tuple([getattr(self.bus,i).value.integer for i in self._signals]) - self._recv(vec) + self._recv(OutputTransaction(self.tb, self.bus.CacheLineOut.value, self.bus.CacheHit.value, + self.bus.CacheMiss.value, self.bus.OldAddress.value)) # ============================================================================== class Testbench(object): class MyScoreboard(Scoreboard): def compare(self, got, exp, log, **_): - """Ignore received output if expected value is None""" - for i, val in enumerate(exp): - if val is not None: - if val != got[i]: - self.errors += 1 - log.error("Received transaction differed from expected output.") - log.warning("Expected: %s.\nReceived: %s." % (exp, got)) - if self._imm: - raise TestFailure("Received transaction differed from expected transaction.") + if got != exp: + self.errors += 1 + log.error("Received transaction differed from expected output.") + log.warning("Expected: {0!s}.\nReceived: {1!s}.".format(exp, got)) + if self._imm: + raise TestFailure("Received transaction differed from expected transaction.") def __init__(self, dut): @@ -159,10 +186,10 @@ def __init__(self, dut): # TODO: create LRU dictionary for each cache set self.lrus = tuple([LeastRecentlyUsedDict(size_limit=self.associativity) for _ in range(self.cache_sets)]) - init_val = (None, 0, 0, None) + init_val = OutputTransaction(self) self.input_drv = InputDriver(dut) - self.output_mon = OutputMonitor(dut) + self.output_mon = OutputMonitor(dut, self) # Create a scoreboard on the outputs self.expected_output = [ init_val ] @@ -209,7 +236,8 @@ def model(self, transaction): self.lrus[index][address] = cacheLineIn if DEBUG >= 1: print("=== model: lrus[{0}] = {1!s}".format(index, self.lrus[index].items())) - self.expected_output.append( (cacheLineOut, cacheHit, cacheMiss, oldAddress) ) + # convert all not None values to BinaryValue + self.expected_output.append( OutputTransaction(self, cacheLineOut, cacheHit, cacheMiss, oldAddress) ) def stop(self): """ From 427f62dc04e5f9752e79365a42ec12fc788907b5 Mon Sep 17 00:00:00 2001 From: Martin Zabel Date: Tue, 1 Nov 2016 18:28:57 +0100 Subject: [PATCH 04/97] lib/cocotb: merged commits from upstream into branch vlsi-eda/master. --- lib/cocotb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/cocotb b/lib/cocotb index 4391cdfe..b1a99bcf 160000 --- a/lib/cocotb +++ b/lib/cocotb @@ -1 +1 @@ -Subproject commit 4391cdfe3b15e25c4b26c1ffa6b5837d13718ca6 +Subproject commit b1a99bcf213c478d955ab9fd61d425ec11ff0e0a From 1965b94c87c55786d4a6e98b957cf96f0d4e80d4 Mon Sep 17 00:00:00 2001 From: Martin Zabel Date: Thu, 3 Nov 2016 16:15:18 +0100 Subject: [PATCH 05/97] Added missing return statements after "report failure" in common and simulation packages. Changed default of INIT parameter of ffdre to 1-bit vector. --- src/common/components.vhdl | 6 ++++-- src/common/config.vhdl | 21 ++++++++++----------- src/common/strings.vhdl | 7 +++++-- src/common/utils.vhdl | 3 ++- src/sim/sim_protected.v08.vhdl | 1 + 5 files changed, 22 insertions(+), 16 deletions(-) diff --git a/src/common/components.vhdl b/src/common/components.vhdl index 8fff218a..b12517d9 100644 --- a/src/common/components.vhdl +++ b/src/common/components.vhdl @@ -53,7 +53,7 @@ package components is function ffsr(q : std_logic; rst : std_logic := '0'; set : std_logic := '0') return std_logic; -- RS-FlipFlop with dominant set -- D-FlipFlops (Delay) function ffdre(q : std_logic; d : std_logic; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic := '0') return std_logic; -- D-FlipFlop with reset and enable - function ffdre(q : std_logic_vector; d : std_logic_vector; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic_vector := (7 downto 0 => '0')) return std_logic_vector; -- D-FlipFlop with reset and enable + function ffdre(q : std_logic_vector; d : std_logic_vector; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic_vector := (0 to 0 => '0')) return std_logic_vector; -- D-FlipFlop with reset and enable function ffdse(q : std_logic; d : std_logic; set : std_logic := '0'; en : std_logic := '1') return std_logic; -- D-FlipFlop with set and enable -- T-FlipFlops (Toggle) function fftre(q : std_logic; t : std_logic; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic := '0') return std_logic; -- T-FlipFlop with reset and enable @@ -112,6 +112,7 @@ package body components is return ((d and en) or (q and not en)) or rst; else report "Unsupported INIT value for synthesis." severity FAILURE; + return 'X'; end if; elsif (rst = '1') then return INIT; @@ -120,7 +121,7 @@ package body components is end if; end function; - function ffdre(q : std_logic_vector; d : std_logic_vector; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic_vector := (7 downto 0 => '0')) return std_logic_vector is + function ffdre(q : std_logic_vector; d : std_logic_vector; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic_vector := (0 to 0 => '0')) return std_logic_vector is constant INIT_I : std_logic_vector(q'range) := resize(INIT, q'length); variable Result : std_logic_vector(q'range); begin @@ -146,6 +147,7 @@ package body components is return ((not q and (t and en)) or (q and not (t and en))) or rst; else report "Unsupported INIT value for synthesis." severity FAILURE; + return 'X'; end if; elsif (rst = '1') then return INIT; diff --git a/src/common/config.vhdl b/src/common/config.vhdl index 8d84f7d3..a3b15483 100644 --- a/src/common/config.vhdl +++ b/src/common/config.vhdl @@ -735,7 +735,7 @@ package body config is when "LCM" => return VENDOR_LATTICE; -- MachXO device when "LFE" => return VENDOR_LATTICE; -- ECP devices when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure; - -- return statement is explicitly missing otherwise XST won't stop + return VENDOR_UNKNOWN; end case; end function; @@ -813,8 +813,8 @@ package body config is end case; when others => report "Unknown vendor in MY_DEVICE = " & MY_DEV & "." severity failure; - -- return statement is explicitly missing otherwise XST won't stop end case; + return DEVICE_UNKNOWN; end function; -- purpose: extract device from MY_DEVICE @@ -851,8 +851,8 @@ package body config is end case; when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure; - -- return statement is explicitly missing otherwise XST won't stop end case; + return DEVICE_FAMILY_UNKNOWN; end function; -- some devices share some common features: e.g. XADC, BlockRAM, ... @@ -897,7 +897,7 @@ package body config is when VENDOR_LATTICE => return extractFirstNumber(MY_DEV(6 to MY_DEV'high)); when VENDOR_XILINX => return extractFirstNumber(MY_DEV(5 to MY_DEV'high)); when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure; - -- return statement is explicitly missing otherwise XST won't stop + return 0; end case; end function; @@ -1010,9 +1010,8 @@ package body config is when DEVICE_ZYNQ_ULTRA_PLUS => return DEVICE_SUBTYPE_NONE; when others => report "Device sub-type is unknown for the given device." severity failure; - -- return statement is explicitly missing otherwise XST won't stop end case; - + return DEVICE_SUBTYPE_NONE; end function; function LUT_FANIN(DeviceString : string := C_DEVICE_STRING_EMPTY) return positive is @@ -1037,8 +1036,8 @@ package body config is when DEVICE_SPARTAN6 => return 6; when DEVICE_VIRTEX4 | DEVICE_VIRTEX5 | DEVICE_VIRTEX6 => return 6; - when others => report "LUT fan-in is unknown for the given device." severity failure; - -- return statement is explicitly missing otherwise XST won't stop + when others => report "LUT fan-in is unknown for the given device, using default (4)." severity failure; + return 4; end case; end function; @@ -1109,8 +1108,8 @@ package body config is end case; when others => report "Unknown device." severity failure; - -- return statement is explicitly missing otherwise XST won't stop end case; + return TRANSCEIVER_NONE; end function; -- purpose: extract architecture properties from DEVICE @@ -1152,7 +1151,7 @@ package body config is when DEVICE_STRATIX10 => return "Stratix 10"; when others => report "Unknown Altera device." severity failure; - -- return statement is explicitly missing otherwise XST won't stop + return ""; end case; end function; @@ -1167,7 +1166,7 @@ package body config is --when VENDOR_LATTICE => return "default"; when VENDOR_XILINX => return "auto"; when others => report "Unknown vendor." severity failure; - -- return statement is explicitly missing otherwise XST won't stop + return ""; end case; end if; end function; diff --git a/src/common/strings.vhdl b/src/common/strings.vhdl index d7f7ad42..edf08a57 100644 --- a/src/common/strings.vhdl +++ b/src/common/strings.vhdl @@ -178,6 +178,7 @@ package body strings is end loop; report "Unknown IPStyle: '" & str & "'" severity FAILURE; + return IPSTYLE_UNKNOWN; end function; -- to_char @@ -552,7 +553,8 @@ package body strings is when 'd' => return to_digit_dec(chr); when 'h' => return to_digit_hex(chr); when others => report "Unknown base character: " & base & "." severity FAILURE; - end case; -- return statement is explicitly missing otherwise XST won't stop + return -1; + end case; end function; -- to_natural* @@ -636,7 +638,8 @@ package body strings is when 'd' => return to_natural_dec(str); when 'h' => return to_natural_hex(str); when others => report "Unknown base character: " & base & "." severity FAILURE; - end case; -- return statement is explicitly missing otherwise XST won't stop + return -1; + end case; end function; -- to_raw* diff --git a/src/common/utils.vhdl b/src/common/utils.vhdl index e6a4d3e7..d47e6754 100644 --- a/src/common/utils.vhdl +++ b/src/common/utils.vhdl @@ -61,7 +61,7 @@ package utils is --+ Enums ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- Intellectual Property (IP) type - type T_IPSTYLE is (IPSTYLE_HARD, IPSTYLE_SOFT); + type T_IPSTYLE is (IPSTYLE_UNKNOWN, IPSTYLE_HARD, IPSTYLE_SOFT); -- Bit Order type T_BIT_ORDER is (LSB_FIRST, MSB_FIRST); @@ -1044,6 +1044,7 @@ package body utils is when ROUND_DOWN => return integer(floor(Result)); when others => report "scale: unsupported RoundingStyle." severity FAILURE; end case; + return integer(Result); end if; end function; diff --git a/src/sim/sim_protected.v08.vhdl b/src/sim/sim_protected.v08.vhdl index b97ea1c1..90f01159 100644 --- a/src/sim/sim_protected.v08.vhdl +++ b/src/sim/sim_protected.v08.vhdl @@ -480,6 +480,7 @@ package body sim_protected is return TRUE; end if; report "isAllFinalized: " severity ERROR; + return FALSE; else return FALSE; end if; From 165948ea244d9e218cc03fdfac55a7314f0ec5f1 Mon Sep 17 00:00:00 2001 From: Martin Zabel Date: Mon, 7 Nov 2016 16:47:45 +0100 Subject: [PATCH 06/97] Added adapter for Xilinx MIG IP core. Documented PoC.Mem interface. Minor fixes Python infrastructure and testbench for lut_Sine. --- .../mem/ddr3/ddr3_mem2mig_adapter_Series7.rst | 42 +++ .../ddr3/ddr3_mem2mig_adapter_Spartan6.rst | 42 +++ docs/PoC/mem/ddr3/index.rst | 25 ++ docs/PoC/misc/sync/sync_Bits.rst | 2 +- docs/PoC/misc/sync/sync_Pulse.rst | 2 +- docs/References/Interfaces/Memory.rst | 127 +++++++- py/PoC.py | 2 +- py/ToolChains/GHDL.py | 2 +- py/lib/CodeDOM.py | 2 +- py/lib/ExtendedConfigParser/__init__.py | 303 ++++++++++++++++++ py/lib/Functions.py | 1 - src/mem/README.md | 2 + src/mem/ddr3/README.md | 6 + .../ddr3/ddr3_mem2mig_adapter_Series7.vhdl | 133 ++++++++ .../ddr3/ddr3_mem2mig_adapter_Spartan6.vhdl | 130 ++++++++ src/mem/lut/lut_Sine.vhdl | 2 - tb/mem/lut/lut_Sine_tb.vhdl | 2 +- tools/precompile/compile-altera.ps1 | 13 +- tools/precompile/compile-lattice.ps1 | 13 +- tools/precompile/compile-osvvm.ps1 | 11 +- tools/precompile/compile-xilinx-ise.ps1 | 13 +- tools/precompile/compile-xilinx-vivado.ps1 | 13 +- 22 files changed, 863 insertions(+), 25 deletions(-) create mode 100644 docs/PoC/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst create mode 100644 docs/PoC/mem/ddr3/ddr3_mem2mig_adapter_Spartan6.rst create mode 100644 docs/PoC/mem/ddr3/index.rst create mode 100644 py/lib/ExtendedConfigParser/__init__.py create mode 100644 src/mem/ddr3/README.md create mode 100644 src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl create mode 100644 src/mem/ddr3/ddr3_mem2mig_adapter_Spartan6.vhdl diff --git a/docs/PoC/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst b/docs/PoC/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst new file mode 100644 index 00000000..cf988c31 --- /dev/null +++ b/docs/PoC/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst @@ -0,0 +1,42 @@ + +ddr3_mem2mig_adapter_Series7 +############################ + +Adapter between the :doc:`PoC.Mem ` +interface and the application interface ("app") +of the Xilinx MIG IP core for 7-Series FPGAs. + +Simplifies the application interface ("app") of the Xilinx MIG IP core. +The PoC.Mem interface provides single-cycle fully pipelined read/write access +to the memory. All accesses are word-aligned. Always all bytes of a word are +written to the memory. More details can be found +:doc:`here `. + +Generic parameters: + +* D_BITS: Data bus width of the PoC.Mem and "app" interface. Also size of one + word in bits. + +* DQ_BITS: Size of data bus between memory controller and external memory + (DIMM, SoDIMM). + +* MEM_A_BITS: Address bus width of the PoC.Mem interface. + +* APP_A_BTIS: Address bus width of the "app" interface. + +Containts only combinational logic. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 61-96 + +Source file: `mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl `_ + + + diff --git a/docs/PoC/mem/ddr3/ddr3_mem2mig_adapter_Spartan6.rst b/docs/PoC/mem/ddr3/ddr3_mem2mig_adapter_Spartan6.rst new file mode 100644 index 00000000..a0d9f221 --- /dev/null +++ b/docs/PoC/mem/ddr3/ddr3_mem2mig_adapter_Spartan6.rst @@ -0,0 +1,42 @@ + +ddr3_mem2mig_adapter_Spartan6 +############################# + +Adapter between the :doc:`PoC.Mem ` +interface and the User Interface of the Xilinx MIG IP core for the +Spartan-6 FPGA Memory Controller Block (MCB). The MCB can be configured to +have multiple ports. One instance of this adapter is required for every +port. The control signals for one port of the MIG IP core are prefixed by +"cX_pY", meaning port Y on controller X. + +Simplifies the User Interface ("user") of the Xilinx MIG IP core (UG388). +The PoC.Mem interface provides single-cycle fully pipelined read/write access +to the memory. All accesses are word-aligned. Always all bytes of a word are +written to the memory. More details can be found +:doc:`here `. + +Generic parameters: + +* D_BITS: Data bus width of the PoC.Mem and MIG / MCBinterface. Also size of + one word in bits. + +* MEM_A_BITS: Address bus width of the PoC.Mem interface. + +* APP_A_BTIS: Address bus width of the MIG / MCB interface. + +Containts only combinational logic. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/ddr3/ddr3_mem2mig_adapter_Spartan6.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 61-95 + +Source file: `mem/ddr3/ddr3_mem2mig_adapter_Spartan6.vhdl `_ + + + diff --git a/docs/PoC/mem/ddr3/index.rst b/docs/PoC/mem/ddr3/index.rst new file mode 100644 index 00000000..cad695f0 --- /dev/null +++ b/docs/PoC/mem/ddr3/index.rst @@ -0,0 +1,25 @@ +ddr3 +==== + +The namespace `PoC.mem.ddr3` is designated for own implementations of +DDR3 memory controllers as well as for adapters for vendor-specific +implementations. At the top-level, all controllers and adapters +provide the same simple memory interface to the user application. + +.. **Package** + +**Entities** + + * :doc:`PoC.mem.ddr3.mem2mig_adapter_Series7 + ` - Adapter for the Xilinx MIG core + for 7-Series FPGAs + * :doc:`PoC.mem.ddr3.mem2mig_adapter_Spartan6 + ` - Adapter for the Xilinx MIG core + for Spartan-6 FPGAs + + +.. toctree:: + :hidden: + + ddr3_mem2mig_adapter_Series7 + ddr3_mem2mig_adapter_Spartan6 diff --git a/docs/PoC/misc/sync/sync_Bits.rst b/docs/PoC/misc/sync/sync_Bits.rst index 0c88cfae..51c5225d 100644 --- a/docs/PoC/misc/sync/sync_Bits.rst +++ b/docs/PoC/misc/sync/sync_Bits.rst @@ -5,7 +5,7 @@ sync_Bits This module synchronizes multiple flag bits into clock-domain ``Clock``. The clock-domain boundary crossing is done by two synchronizer D-FFs. All bits are independent from each other. If a known vendor like Altera or Xilinx -are recognized, a vendor specific implementation is choosen. +are recognized, a vendor specific implementation is chosen. .. ATTENTION:: Use this synchronizer only for long time stable signals (flags). diff --git a/docs/PoC/misc/sync/sync_Pulse.rst b/docs/PoC/misc/sync/sync_Pulse.rst index 90c685ff..7667bf73 100644 --- a/docs/PoC/misc/sync/sync_Pulse.rst +++ b/docs/PoC/misc/sync/sync_Pulse.rst @@ -5,7 +5,7 @@ sync_Pulse This module synchronizes multiple pulsed bits into the clock-domain ``Clock``. The clock-domain boundary crossing is done by two synchronizer D-FFs. All bits are independent from each other. If a known vendor like Altera or Xilinx are -recognized, a vendor specific implementation is choosen. +recognized, a vendor specific implementation is chosen. .. ATTENTION:: Use this synchronizer for very short signals (pulse). diff --git a/docs/References/Interfaces/Memory.rst b/docs/References/Interfaces/Memory.rst index c02c66c9..5821e8c3 100644 --- a/docs/References/Interfaces/Memory.rst +++ b/docs/References/Interfaces/Memory.rst @@ -2,5 +2,128 @@ PoC.Mem ####### -.. TODO:: - Define the PoC.Memory interface used in ... +PoC.Mem is a single-cycle, pipelined memory interface used by various +memory controllers and related components like caches. Memory accesses +are always word aligned, and during writes a mask defines which bytes +are actually written to the memory (if supported by the memory +controller). + + +Configuration +************* + +Each entity may have an individual configuration, especially if it has +two PoC.Mem interfaces or if it adapts between PoC.Mem and another +interface. + +The typical configuration parameters are: + ++--------------------+------------------------------------------------+ +| Parameter | Description | ++====================+================================================+ +| ADDR_BITS or | Number of address bits. Each address identifies| +| A_BITS | exactly one memory word. | ++--------------------+------------------------------------------------+ +| DATA_BITS or | Size of a memory word in bits. DATA_BITS must | +| D_BITS | be divisible by 8. | ++--------------------+------------------------------------------------+ + +A memory word consists of DATA_BITS/8 bytes. + +Individual bytes are only addressed during writes by the write +mask. The write mask has one mask-bit for each byte in a memory word. + +For example, a 1 KiByte memory with a 32-bit datapath has the +following configuration: + +* 4 bytes per memory word, +* ADDR_BITS=8 because log_2(1 KiByte / 4 bytes) = 8, and +* DATA_BITS=32 which is the datapath size in bits. + + +Interface signals +***************** + +The following signal names are typically prefixed in the port list of +a concrete entity to separate the PoC.Mem interface from other +interfaces of the entity. Moreover, clock and reset may be shared +with other interfaces of the entity. + +The PoC.Mem interface consists of the following signals: + ++--------------------+------------------------------------------------+ +| Signal | Description | ++====================+================================================+ +| clk | The clock. All other signals are synchronous | +| | to the rising edge of this clock. | ++--------------------+------------------------------------------------+ +| rst | High-active synchronous reset. | ++--------------------+------------------------------------------------+ +| rdy | High-active ready for request. | ++--------------------+------------------------------------------------+ +| req | High-active request. | ++--------------------+------------------------------------------------+ +| write | '1' if write request, '0' if read request | ++--------------------+------------------------------------------------+ +| addr | The (word) address. | ++--------------------+------------------------------------------------+ +| wdata | The data to be written to the memory. | ++--------------------+------------------------------------------------+ +| wmask | Write-mask, for each byte: '0' = write byte, | +| (optional) | '1' = mask byte from write. Signal/port is | +| | omitted if write mask is not supported. | ++--------------------+------------------------------------------------+ +| rstb | High-active read-strobe. | ++--------------------+------------------------------------------------+ +| rdata | The read-data returned from the memory. | ++--------------------+------------------------------------------------+ + +The interface is actually splitted into two parts: + +* the request part: signals ``rdy``, ``req``, ``write``, ``addr``, + ``wdata`` and ``wmask``, and + +* the read-reply part: signals ``rstb`` and ``rdata``. + + +Operation +********* + +The request and the read-reply part operate indepent of each other to +support pipelined reading from memory. The pipeline depth is defined +by the actual memory controller. If a user application does support +only a specific number of outstanding reads, then the application must +limit the number of issued reads on its own. + + +Requests +++++++++ + +If ``req`` is low, then no request is issued to the memory in the current +clock cycle. The state of the signals ``write``, ``addr``, ``wdata`` +and ``wmask`` doesn't care. + +If ``req`` is high, then a request is issued to the memory in the current +clock cycle as given by ``write``, ``addr``, ``wdata`` and +``wmask``. The request will be accepted by the memory, if ``rdy`` is +high in the same clock cycle, otherwise the request will be ignored. +``wdata`` and ``wmask`` doesn't care if a read request is issued. + +``rdy`` does not depend on ``req`` in the current clock cycle. ``rdy`` +may go low in the following clock cycle after a request has been +issued or a synchronous reset has been applied. + + +Read Replies +++++++++++++ + +If ``rstb`` is high in the current clock cycle, then ``rdata`` +delivers the requested read data (read reply). Otherwise, if ``rstb`` +is low, then ``rdata`` is unknown. The user application has to +immediatly handle the incoming read data, because it cannot +signal ready or acknowledge. + +After issuing a read request, the memory responds with a read reply in +the following clock cycle (i.e. synchronous read) or any later clock +cycle depending on the pipeline depth. For each read request, a read +reply is generated. Read requests are not reordered. diff --git a/py/PoC.py b/py/PoC.py index 9f42ef74..95ced25b 100644 --- a/py/PoC.py +++ b/py/PoC.py @@ -71,7 +71,7 @@ from lib.pyAttribute.ArgParseAttributes import ArgParseMixin from lib.pyAttribute.ArgParseAttributes import CommandAttribute, CommandGroupAttribute, ArgumentAttribute, SwitchArgumentAttribute, DefaultAttribute from lib.pyAttribute.ArgParseAttributes import CommonArgumentAttribute, CommonSwitchArgumentAttribute -from lib.ConfigParser import ExtendedConfigParser +from lib.ExtendedConfigParser import ExtendedConfigParser from lib.Functions import Init, Exit from lib.Parser import ParserException from lib.pyAttribute import Attribute diff --git a/py/ToolChains/GHDL.py b/py/ToolChains/GHDL.py index 1af50cc1..3fe21b5c 100644 --- a/py/ToolChains/GHDL.py +++ b/py/ToolChains/GHDL.py @@ -184,7 +184,7 @@ def __init__(self, platform, dryrun, binaryDirectoryPath, version, backend, logg #self.Parameters[self.Executable] = executablePath if (platform == "Windows"): - if (backend not in ["mcode"]): raise GHDLException("GHDL for Windows does not support backend '{0}'.".format(backend)) + if (backend not in ["llvm", "mcode"]): raise GHDLException("GHDL for Windows does not support backend '{0}'.".format(backend)) elif (platform == "Linux"): if (backend not in ["gcc", "llvm", "mcode"]): raise GHDLException("GHDL for Linux does not support backend '{0}'.".format(backend)) elif (platform == "Darwin"): diff --git a/py/lib/CodeDOM.py b/py/lib/CodeDOM.py index 4aa3acce..62d52c00 100644 --- a/py/lib/CodeDOM.py +++ b/py/lib/CodeDOM.py @@ -195,7 +195,7 @@ def RightChild(self): __PARSER_NAME__ = None __PARSER_LHS_EXPRESSIONS__ = None __PARSER_RHS_EXPRESSIONS__ = None - __PARSER_OPERATOR__ = None + __PARSER_OPERATOR__ = None @classmethod def GetParser(cls): diff --git a/py/lib/ExtendedConfigParser/__init__.py b/py/lib/ExtendedConfigParser/__init__.py new file mode 100644 index 00000000..b4af9d24 --- /dev/null +++ b/py/lib/ExtendedConfigParser/__init__.py @@ -0,0 +1,303 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# Python Module: Derived and extended configparser from Python standard library +# +# Description: +# ------------------------------------ +# - Improved interpolation algorithm +# - Added an interpolation cache +# - Added recursive interpolation (indirect addressing): ${key1.${key2:opt2}:opt1} +# - Added %{keyword} interpolation, to access the section name: %{parent} +# - Added support for multiple DEFAULT sections [CONFIG.DEFAULT] for all [CONFIG.**] sections +# +# License: +# ============================================================================== +# Copyright 2007-2016 Patrick Lehmann - Dresden, Germany +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +# +import re +from collections import OrderedDict as _default_dict, ChainMap as _ChainMap +from configparser import ConfigParser, SectionProxy, Interpolation, MAX_INTERPOLATION_DEPTH, DEFAULTSECT, _UNSET, ConverterMapping +from configparser import NoSectionError, InterpolationDepthError, InterpolationSyntaxError, NoOptionError, InterpolationMissingOptionError + +class ExtendedSectionProxy(SectionProxy): + def __getitem__(self, key): + if not self._parser.has_option(self._name, key): + raise KeyError(self._name + ":" + key) + return self._parser.get(self._name, key) + +# Monkey patching ... (a.k.a. duck punshing +import configparser +configparser.SectionProxy = ExtendedSectionProxy + + +class ExtendedInterpolation(Interpolation): + _KEYCRE = re.compile(r"\$\{(?P[^}]+)\}") + _KEYCRE2 = re.compile(r"\$\[(?P[^\]]+)\}") + + def __init__(self): + self._cache = dict() + + def clear_cache(self): + self._cache = dict() + + def before_get(self, parser, section, option, value, defaults): + # print("before_get: {0}:{1} = '{2}'".format(section, option, value)) + try: + result = self.GetCached(section, option) + except KeyError: + result = self.interpolate(parser, section, option, value, defaults) + self.UpdateCache(section, option, result) + # print("before_get: => '{0}'\n".format(result)) + return result + + def before_set(self, parser, section, option, value): + tmp_value = value.replace("$$", "") # escaped dollar signs + tmp_value = self._KEYCRE.sub("", tmp_value) # valid syntax + if '$' in tmp_value: + raise ValueError("invalid interpolation syntax in {0!r} at position {1}".format(value, tmp_value.find("$"))) + return value + + def interpolate(self, parser, section, option, value, _, depth=0): + if depth > MAX_INTERPOLATION_DEPTH: raise InterpolationDepthError(option, section, value) + + # short cut operations if empty or a normal string + if (value == ""): + # print("interpol: SHORT -> empty string") + return "" + elif (("$" not in value) and ("%" not in value)): + # print("interpol: SHORT -> {0}".format(value)) + return value + + # print("interpol: PREPARE section={0} option={1} value='{2}'".format(section, option, value)) + rawValue = value + rest = "" + + while (len(rawValue) > 0): + beginPos = rawValue.find("%") + if (beginPos < 0): + rest += rawValue + rawValue = "" + else: + rest += rawValue[:beginPos] + if (rawValue[beginPos + 1] == "%"): + rest += "%" + rawValue = rawValue[1:] + elif (rawValue[beginPos + 1] == "{"): + endPos = rawValue.find("}", beginPos) + if (endPos < 0): + raise InterpolationSyntaxError(option, section, "bad interpolation variable reference {0!r}".format(rawValue)) + path = rawValue[beginPos + 2:endPos] + rawValue = rawValue[endPos + 1:] + rest += self.GetSpecial(section, option, path) + + # print("interpol: BEGIN section={0} option={1} value='{2}'".format(section, option, rest)) + result = "" + while (len(rest) > 0): + # print("interpol: LOOP rest='{0}'".format(rest)) + beginPos = rest.find("$") + if (beginPos < 0): + result += rest + rest = "" + else: + result += rest[:beginPos] + if (rest[beginPos + 1] == "$"): + result += "$" + rest = rest[1:] + elif (rest[beginPos + 1] == "{"): + endPos = rest.find("}", beginPos) + nextPos = rest.rfind("$", beginPos, endPos) + if (endPos < 0): raise InterpolationSyntaxError(option, section, "bad interpolation variable reference {0!r}".format(rest)) + if ((nextPos > 0) and (nextPos < endPos)): # an embedded $-sign + path = rest[nextPos+2:endPos] + # print("interpol: path='{0}'".format(path)) + innervalue = self.GetValue(parser, section, option, path) + # innervalue = self.interpolate(parser, section, option, path, map, depth + 1) + # print("interpol: innervalue='{0}'".format(innervalue)) + rest = rest[beginPos:nextPos] + innervalue + rest[endPos + 1:] + # print("interpol: new rest='{0}'".format(rest)) + else: + path = rest[beginPos+2:endPos] + rest = rest[endPos+1:] + result += self.GetValue(parser, section, option, path) + + # print("interpol: LOOP END - result='{0}'".format(result)) + + # print("interpol: RESULT => '{0}'".format(result)) + return result + + def GetSpecial(self, section, option, path): + parts = section.split(".") + if (path == "Root"): + return parts[0] + elif (path == "Parent"): + return ".".join(parts[1:-1]) + elif (path == "ParentWithRoot"): + return ".".join(parts[:-1]) + elif (path == "GrantParent"): + return ".".join(parts[1:-2]) + elif (path == "Path"): + return ".".join(parts[1:]) + elif (path == "PathWithRoot"): + return section + elif (path == "Name"): + return parts[-1] + else: + raise InterpolationSyntaxError(option, section, "Unknown keyword '{0}'in special operator.".format(path)) + + def GetValue(self, parser, section, option, path): + path = path.split(":") + if (len(path) == 1): + sec = section + opt = parser.optionxform(path[0]) + elif (len(path) == 2): + sec = path[0] + opt = parser.optionxform(path[1]) + else: + raise InterpolationSyntaxError(option, section, "More than one ':' found.") + + try: + return self.GetCached(sec, opt) + except KeyError: + pass + + try: + value = parser.get(sec, opt, raw=True) + # print("GetValue: successful parser access: '{0}'".format(value)) + except (KeyError, NoSectionError, NoOptionError) as ex: + raise InterpolationMissingOptionError(option, section, "", ":".join(path)) from ex + + if (("$" in value) or ("%" in value)): + value = self.interpolate(parser, sec, opt, value, {}) + + self.UpdateCache(sec, opt, value) + return value + + def GetCached(self, section, option): + # print("GetCached: {0}:{1}".format(section, option)) + if (section not in self._cache): + raise KeyError(section) + sect = self._cache[section] + if (option not in sect): + raise KeyError("{0}:{1}".format(section, option)) + + value = sect[option] + # print("GetCached: found: {0}".format(value)) + return value + + def UpdateCache(self, section, option, value): + # print("UpdateCache: {0}:{1} <- {2}".format(section, option, value)) + if (section in self._cache): + sect = self._cache[section] + if (option in sect): raise Exception("This value is already cached.") + sect[option] = value + else: + self._cache[section] = {option : value} + + +class ExtendedConfigParser(ConfigParser): + _DEFAULT_INTERPOLATION = ExtendedInterpolation() + + def __init__(self, defaults=None, dict_type=_default_dict, allow_no_value=False, *, delimiters=('=', ':'), comment_prefixes=('#', ';'), inline_comment_prefixes=None, + strict=True, empty_lines_in_values=True, default_section=DEFAULTSECT, interpolation=_UNSET, converters=_UNSET): + # replacement of ConfigParser.__init__, do not call super-class constructor + self._dict = dict_type + self._defaults = dict_type() + self._sections = dict_type() + self._proxies = dict_type() + self._cache = dict() + + self._comment_prefixes = tuple(comment_prefixes or ()) + self._inline_comment_prefixes = tuple(inline_comment_prefixes or ()) + self._strict = strict + self._allow_no_value = allow_no_value + self._empty_lines_in_values = empty_lines_in_values + self.default_section = default_section + + self._converters = ConverterMapping(self) + if (converters is not _UNSET): + self._converters.update(converters) + + self._proxies[default_section] = SectionProxy(self, default_section) + + if defaults: + for key, value in defaults.items(): + self._defaults[self.optionxform(key)] = value + + self._delimiters = tuple(delimiters) + if delimiters == ('=', ':'): + self._optcre = self.OPTCRE_NV if allow_no_value else self.OPTCRE + else: + d = "|".join(re.escape(d) for d in delimiters) + if allow_no_value: self._optcre = re.compile(self._OPT_NV_TMPL.format(delim=d), re.VERBOSE) + else: self._optcre = re.compile(self._OPT_TMPL.format(delim=d), re.VERBOSE) + + if (interpolation is None): self._interpolation = Interpolation() + elif (interpolation is _UNSET): self._interpolation = ExtendedInterpolation() + else: self._interpolation = interpolation + + @property + def Interpolation(self): + return self._interpolation + + def _unify_values(self, section, variables): + """Create a sequence of lookups with 'variables' taking priority over + the 'section' which takes priority over the DEFAULTSECT. + + """ + try: + sectiondict = self._sections[section] + except KeyError: + if section != self.default_section: + raise NoSectionError(section) + else: + sectiondict = {} + + # Update with the entry specific variables + vardict = {} + if variables: + for key, value in variables.items(): + if value is not None: + value = str(value) + vardict[self.optionxform(key)] = value + prefix = section.split(".",1)[0] + ".DEFAULT" + # print("searched for {0}".format(prefix)) + try: + defaultdict = self._sections[prefix] + return _ChainMap(vardict, sectiondict, defaultdict, self._defaults) + except KeyError: + return _ChainMap(vardict, sectiondict, self._defaults) + + def has_option(self, section, option): + """Check for the existence of a given option in a given section. + If the specified `section' is None or an empty string, DEFAULT is + assumed. If the specified `section' does not exist, returns False.""" + option = self.optionxform(option) + if ((not section) or (section == self.default_section)): + sect = self._defaults + else: + prefix = section.split(".", 1)[0] + ".DEFAULT" + if ((prefix in self) and (option in self._sections[prefix])): + return True + if (section not in self._sections): + return False + else: + sect = self._sections[section] + return option in sect diff --git a/py/lib/Functions.py b/py/lib/Functions.py index eeee5536..40aca8f1 100644 --- a/py/lib/Functions.py +++ b/py/lib/Functions.py @@ -175,4 +175,3 @@ def printNotConfiguredException(cls, ex): print("{RED}ERROR:{NOCOLOR} {message}".format(message=ex.message, **Init.Foreground)) print(" Please run {YELLOW}'poc.[sh/ps1] configure'{NOCOLOR} in PoC root directory.".format(**Init.Foreground)) Exit.exit(1) - diff --git a/src/mem/README.md b/src/mem/README.md index 6b58b595..95be40f6 100644 --- a/src/mem/README.md +++ b/src/mem/README.md @@ -6,6 +6,7 @@ implementations. ## Sub-Namespace(s) + - [`PoC.mem.ddr3`][mem_ddr3] - Adapter and Wrapper for DDR3 controllers - [`PoC.mem.is61lv`][mem_is61lv] - ISSI - IS61LV SRAM controller - [`PoC.mem.is61nlp`][mem_is61nlp] - ISSI - IS61NLP SRAM controller - [`PoC.mem.lut`][mem_lut] - Lookup-Table (LUT) implementations @@ -21,6 +22,7 @@ The package [`PoC.mem`][mem.pkg] holds all component declarations for this names [mem.pkg]: mem.pkg.vhdl + [mem_ddr3]: ddr3 [mem_is61lv]: is61lv [mem_is61nlp]: is61nlp [mem_lut]: lut diff --git a/src/mem/ddr3/README.md b/src/mem/ddr3/README.md new file mode 100644 index 00000000..c03a1291 --- /dev/null +++ b/src/mem/ddr3/README.md @@ -0,0 +1,6 @@ +# Namespace `PoC.mem.ddr3 + +The namespace `PoC.mem.ddr3` is designated for own implementations of +DDR3 memory controllers as well as for adapters for vendor-specific +implementations. At the top-level, all controllers and adapters +provide the same simple memory interface to the user application. diff --git a/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl b/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl new file mode 100644 index 00000000..a558841e --- /dev/null +++ b/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl @@ -0,0 +1,133 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Authors: Martin Zabel +-- +-- Module: Adapter for the Xilinx MIG IP core on 7-Series FPGAs. +-- +-- Description: +-- ------------------------------------ +-- Adapter between the :doc:`PoC.Mem ` +-- interface and the application interface ("app") +-- of the Xilinx MIG IP core for 7-Series FPGAs. +-- +-- Simplifies the application interface ("app") of the Xilinx MIG IP core. +-- The PoC.Mem interface provides single-cycle fully pipelined read/write access +-- to the memory. All accesses are word-aligned. Always all bytes of a word are +-- written to the memory. More details can be found +-- :doc:`here `. +-- +-- Generic parameters: +-- +-- * D_BITS: Data bus width of the PoC.Mem and "app" interface. Also size of one +-- word in bits. +-- +-- * DQ_BITS: Size of data bus between memory controller and external memory +-- (DIMM, SoDIMM). +-- +-- * MEM_A_BITS: Address bus width of the PoC.Mem interface. +-- +-- * APP_A_BTIS: Address bus width of the "app" interface. +-- +-- Containts only combinational logic. +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library poc; +use poc.utils.all; + +entity ddr3_mem2mig_adapter_Series7 is + + generic ( + D_BITS : positive; + DQ_BITS : positive; + MEM_A_BITS : positive; + APP_A_BITS : positive + ); + + port ( + -- PoC.Mem interface + mem_req : in std_logic; + mem_write : in std_logic; + mem_addr : in unsigned(MEM_A_BITS-1 downto 0); + mem_wdata : in std_logic_vector(D_BITS-1 downto 0); + mem_rdy : out std_logic; + mem_rstb : out std_logic; + mem_rdata : out std_logic_vector(D_BITS-1 downto 0); + + -- Xilinx MIG IP Core interface + init_calib_complete : in std_logic; + app_rd_data : in std_logic_vector((D_BITS)-1 downto 0); + app_rd_data_end : in std_logic; + app_rd_data_valid : in std_logic; + app_rdy : in std_logic; + app_wdf_rdy : in std_logic; + app_addr : out std_logic_vector(APP_A_BITS-1 downto 0); + app_cmd : out std_logic_vector(2 downto 0); + app_en : out std_logic; + app_wdf_data : out std_logic_vector((D_BITS)-1 downto 0); + app_wdf_end : out std_logic; + app_wdf_mask : out std_logic_vector((D_BITS)/8-1 downto 0); + app_wdf_wren : out std_logic + ); + +end entity ddr3_mem2mig_adapter_Series7; + +architecture rtl of ddr3_mem2mig_adapter_Series7 is + -- The smallest addressable unit of the "app" interface has DQ_BITS bits. + -- The smallest addressable unit of the "mem" interface has D_BITS bits. + -- The burst length is then D_BITS / DQ_BITS. + constant BL : positive := D_BITS / DQ_BITS; + constant BL_BITS : natural := log2ceil(BL); + + signal mem_rdy_i : std_logic; + +begin -- architecture rtl + + -- command & FIFO control + mem_rdy_i <= init_calib_complete and app_rdy and app_wdf_rdy; + mem_rdy <= mem_rdy_i; + + app_en <= mem_rdy_i and mem_req; + app_wdf_wren <= mem_rdy_i and mem_req and mem_write; + app_wdf_end <= mem_rdy_i and mem_req and mem_write; -- 1 "mem" word / burst + app_cmd <= "00" & (not mem_write); + + -- address + process (mem_addr) is + begin -- process + app_addr <= (others => '0'); + app_addr(MEM_A_BITS+BL_BITS-1 downto BL_BITS) <= std_logic_vector(mem_addr); + end process; + + -- write data & mask + app_wdf_data <= mem_wdata; + app_wdf_mask <= (others => '0'); -- all bytes + + -- read reply + mem_rstb <= app_rd_data_valid; + mem_rdata <= app_rd_data; + +end architecture rtl; diff --git a/src/mem/ddr3/ddr3_mem2mig_adapter_Spartan6.vhdl b/src/mem/ddr3/ddr3_mem2mig_adapter_Spartan6.vhdl new file mode 100644 index 00000000..a0a2b4bf --- /dev/null +++ b/src/mem/ddr3/ddr3_mem2mig_adapter_Spartan6.vhdl @@ -0,0 +1,130 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Authors: Martin Zabel +-- +-- Module: Adapter for the Xilinx MIG IP core on Spartan-6 FPGAs. +-- +-- Description: +-- ------------------------------------ +-- Adapter between the :doc:`PoC.Mem ` +-- interface and the User Interface of the Xilinx MIG IP core for the +-- Spartan-6 FPGA Memory Controller Block (MCB). The MCB can be configured to +-- have multiple ports. One instance of this adapter is required for every +-- port. The control signals for one port of the MIG IP core are prefixed by +-- "cX_pY", meaning port Y on controller X. +-- +-- Simplifies the User Interface ("user") of the Xilinx MIG IP core (UG388). +-- The PoC.Mem interface provides single-cycle fully pipelined read/write access +-- to the memory. All accesses are word-aligned. Always all bytes of a word are +-- written to the memory. More details can be found +-- :doc:`here `. +-- +-- Generic parameters: +-- +-- * D_BITS: Data bus width of the PoC.Mem and MIG / MCBinterface. Also size of +-- one word in bits. +-- +-- * MEM_A_BITS: Address bus width of the PoC.Mem interface. +-- +-- * APP_A_BTIS: Address bus width of the MIG / MCB interface. +-- +-- Containts only combinational logic. +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library poc; +use poc.utils.all; + +entity ddr3_mem2mig_adapter_Spartan6 is + + generic ( + D_BITS : positive; + MEM_A_BITS : positive; + APP_A_BITS : positive + ); + + port ( + -- PoC.Mem interface + mem_req : in std_logic; + mem_write : in std_logic; + mem_addr : in unsigned(MEM_A_BITS-1 downto 0); + mem_wdata : in std_logic_vector(D_BITS-1 downto 0); + mem_rdy : out std_logic; + mem_rstb : out std_logic; + mem_rdata : out std_logic_vector(D_BITS-1 downto 0); + + -- Xilinx MIG IP Core interface + mig_calib_done : in std_logic; + mig_cmd_full : in std_logic; + mig_wr_full : in std_logic; + mig_rd_empty : in std_logic; + mig_rd_data : in std_logic_vector((D_BITS)-1 downto 0); + mig_cmd_instr : out std_logic_vector(2 downto 0); + mig_cmd_en : out std_logic; + mig_cmd_bl : out std_logic_vector(5 downto 0); + mig_cmd_byte_addr : out std_logic_vector(APP_A_BITS-1 downto 0); + mig_wr_data : out std_logic_vector((D_BITS)-1 downto 0); + mig_wr_mask : out std_logic_vector((D_BITS)/8-1 downto 0); + mig_wr_en : out std_logic; + mig_rd_en : out std_logic + ); + +end entity ddr3_mem2mig_adapter_Spartan6; + +architecture rtl of ddr3_mem2mig_adapter_Spartan6 is + -- The number of bits addressing the byte within the MIG address. + constant BYTE_ADDR_BITS : positive := log2ceil(D_BITS/8); + + signal mem_rdy_i : std_logic; + +begin -- architecture rtl + + -- command & FIFO control + mem_rdy_i <= mig_calib_done and (not mig_cmd_full) and (not mig_wr_full); + mem_rdy <= mem_rdy_i; + + mig_cmd_en <= mem_rdy_i and mem_req; + mig_wr_en <= mem_rdy_i and mem_req and mem_write; + mig_cmd_instr <= "00" & (not mem_write); -- with-out auto precharge + mig_cmd_bl <= "000000"; -- 1 word of D_BITS + + -- address + process (mem_addr) is + begin -- process + mig_cmd_byte_addr <= (others => '0'); + mig_cmd_byte_addr(MEM_A_BITS+BYTE_ADDR_BITS-1 downto BYTE_ADDR_BITS) <= std_logic_vector(mem_addr); + end process; + + -- write data & mask + mig_wr_data <= mem_wdata; + mig_wr_mask <= (others => '0'); -- all bytes + + -- read reply + mig_rd_en <= not mig_rd_empty; + mem_rstb <= not mig_rd_empty; + mem_rdata <= mig_rd_data; + +end architecture rtl; diff --git a/src/mem/lut/lut_Sine.vhdl b/src/mem/lut/lut_Sine.vhdl index 7af50ea5..708ff38d 100644 --- a/src/mem/lut/lut_Sine.vhdl +++ b/src/mem/lut/lut_Sine.vhdl @@ -132,9 +132,7 @@ begin variable y : REAL; begin for i in Result'range loop - report "x=" & str_format(x, 3) & " y=" & str_format((sin(x) * AMPLITUDE_I), 3) severity note; Result(i) := integer(sin(x) * AMPLITUDE_I); - x := x + STEP; end loop; return Result; diff --git a/tb/mem/lut/lut_Sine_tb.vhdl b/tb/mem/lut/lut_Sine_tb.vhdl index e66ad3ff..b3303a81 100644 --- a/tb/mem/lut/lut_Sine_tb.vhdl +++ b/tb/mem/lut/lut_Sine_tb.vhdl @@ -76,7 +76,7 @@ begin simWaitUntilRisingEdge(Clock, 4); for i in 0 to 1023 loop - lut_in <= to_slv(i, lut_in'length); + lut_in <= to_slv(i mod 2**lut_in'length, lut_in'length); wait until rising_edge(Clock); end loop; diff --git a/tools/precompile/compile-altera.ps1 b/tools/precompile/compile-altera.ps1 index 21403541..f7f287cd 100644 --- a/tools/precompile/compile-altera.ps1 +++ b/tools/precompile/compile-altera.ps1 @@ -70,6 +70,13 @@ $WorkingDir = Get-Location $PoCRootDir = Convert-Path (Resolve-Path ($PSScriptRoot + $PoCRootDir)) $PoCPS1 = "$PoCRootDir\poc.ps1" +# set default values +$EnableVerbose = $PSCmdlet.MyInvocation.BoundParameters["Verbose"] +$EnableDebug = $PSCmdlet.MyInvocation.BoundParameters["Debug"] +if ($EnableVerbose -eq $null) { $EnableVerbose = $false } +if ($EnableDebug -eq $null) { $EnableDebug = $false } +if ($EnableDebug -eq $true) { $EnableVerbose = $true } + Import-Module $PSScriptRoot\precompile.psm1 -Verbose:$false -Debug:$false -Scope Local -ArgumentList "$WorkingDir" # Display help if no command was selected @@ -103,7 +110,7 @@ if ($GHDL) $GHDLAlteraScript = "$GHDLScriptDir\compile-altera.ps1" if (-not (Test-Path $GHDLAlteraScript -PathType Leaf)) - { Write-Host "[ERROR]: Altera compile script from GHDL is not executable." -ForegroundColor Red + { Write-Host "[ERROR]: Altera compile script '$GHDLAlteraScript' from GHDL not found." -ForegroundColor Red Exit-PrecompileScript -1 } @@ -115,7 +122,7 @@ if ($GHDL) { $env:GHDL = $GHDLBinDir } if ($VHDL93) - { $Command = "$GHDLAlteraScript -All -VHDL93 -Source $SourceDir -Output $DestDir\$AlteraDirName" + { $Command = "$GHDLAlteraScript -All -VHDL93 -Source $SourceDir -Output $DestDir\$AlteraDirName -Verbose:`$$EnableVerbose -Debug:`$$EnableDebug" Invoke-Expression $Command if ($LastExitCode -ne 0) { Write-Host "[ERROR]: While executing vendor library compile script from GHDL." -ForegroundColor Red @@ -123,7 +130,7 @@ if ($GHDL) } } if ($VHDL2008) - { $Command = "$GHDLAlteraScript -All -VHDL2008 -Source $SourceDir -Output $DestDir\$AlteraDirName" + { $Command = "$GHDLAlteraScript -All -VHDL2008 -Source $SourceDir -Output $DestDir\$AlteraDirName -Verbose:`$$EnableVerbose -Debug:`$$EnableDebug" Invoke-Expression $Command if ($LastExitCode -ne 0) { Write-Host "[ERROR]: While executing vendor library compile script from GHDL." -ForegroundColor Red diff --git a/tools/precompile/compile-lattice.ps1 b/tools/precompile/compile-lattice.ps1 index 2de77ce3..f5d03bfb 100644 --- a/tools/precompile/compile-lattice.ps1 +++ b/tools/precompile/compile-lattice.ps1 @@ -70,6 +70,13 @@ $WorkingDir = Get-Location $PoCRootDir = Convert-Path (Resolve-Path ($PSScriptRoot + $PoCRootDir)) $PoCPS1 = "$PoCRootDir\poc.ps1" +# set default values +$EnableVerbose = $PSCmdlet.MyInvocation.BoundParameters["Verbose"] +$EnableDebug = $PSCmdlet.MyInvocation.BoundParameters["Debug"] +if ($EnableVerbose -eq $null) { $EnableVerbose = $false } +if ($EnableDebug -eq $null) { $EnableDebug = $false } +if ($EnableDebug -eq $true) { $EnableVerbose = $true } + Import-Module $PSScriptRoot\precompile.psm1 -Verbose:$false -Debug:$false -ArgumentList "$WorkingDir" # Display help if no command was selected @@ -103,7 +110,7 @@ if ($GHDL) $GHDLLatticeScript = "$GHDLScriptDir\compile-lattice.ps1" if (-not (Test-Path $GHDLLatticeScript -PathType Leaf)) - { Write-Host "[ERROR]: Lattice compile script from GHDL is not executable." -ForegroundColor Red + { Write-Host "[ERROR]: Lattice compile script '$GHDLLatticeScript' from GHDL not found." -ForegroundColor Red Exit-PrecompileScript -1 } @@ -115,7 +122,7 @@ if ($GHDL) { $env:GHDL = $GHDLBinDir } if ($VHDL93) - { $Command = "$GHDLLatticeScript -All -VHDL93 -Source $SourceDir -Output $DestDir\$LatticeDirName" + { $Command = "$GHDLLatticeScript -All -VHDL93 -Source $SourceDir -Output $DestDir\$LatticeDirName -Verbose:`$$EnableVerbose -Debug:`$$EnableDebug" Invoke-Expression $Command if ($LastExitCode -ne 0) { Write-Host "[ERROR]: While executing vendor library compile script from GHDL." -ForegroundColor Red @@ -123,7 +130,7 @@ if ($GHDL) } } if ($VHDL2008) - { $Command = "$GHDLLatticeScript -All -VHDL2008 -Source $SourceDir -Output $DestDir\$LatticeDirName" + { $Command = "$GHDLLatticeScript -All -VHDL2008 -Source $SourceDir -Output $DestDir\$LatticeDirName -Verbose:`$$EnableVerbose -Debug:`$$EnableDebug" Invoke-Expression $Command if ($LastExitCode -ne 0) { Write-Host "[ERROR]: While executing vendor library compile script from GHDL." -ForegroundColor Red diff --git a/tools/precompile/compile-osvvm.ps1 b/tools/precompile/compile-osvvm.ps1 index b8352a09..2d925736 100644 --- a/tools/precompile/compile-osvvm.ps1 +++ b/tools/precompile/compile-osvvm.ps1 @@ -66,6 +66,13 @@ $WorkingDir = Get-Location $PoCRootDir = Convert-Path (Resolve-Path ($PSScriptRoot + $PoCRootDir)) $PoCPS1 = "$PoCRootDir\poc.ps1" +# set default values +$EnableVerbose = $PSCmdlet.MyInvocation.BoundParameters["Verbose"] +$EnableDebug = $PSCmdlet.MyInvocation.BoundParameters["Debug"] +if ($EnableVerbose -eq $null) { $EnableVerbose = $false } +if ($EnableDebug -eq $null) { $EnableDebug = $false } +if ($EnableDebug -eq $true) { $EnableVerbose = $true } + Import-Module $PSScriptRoot\precompile.psm1 -Verbose:$false -Debug:$false -ArgumentList "$WorkingDir" # Display help if no command was selected @@ -99,7 +106,7 @@ if ($GHDL) $GHDLOSVVMScript = "$GHDLScriptDir\compile-osvvm.ps1" if (-not (Test-Path $GHDLOSVVMScript -PathType Leaf)) - { Write-Host "[ERROR]: OSVVM compile script from GHDL is not executable." -ForegroundColor Red + { Write-Host "[ERROR]: OSVVM compile script '$GHDLOSVVMScript' from GHDL not found." -ForegroundColor Red Exit-PrecompileScript -1 } @@ -107,7 +114,7 @@ if ($GHDL) if (-not (Test-Path env:GHDL)) { $env:GHDL = $GHDLBinDir } - $Command = "$GHDLOSVVMScript -All -Source $SourceDirectory -Output $DestDir" + $Command = "$GHDLOSVVMScript -All -Source $SourceDirectory -Output $DestDir -Verbose:`$$EnableVerbose -Debug:`$$EnableDebug" Invoke-Expression $Command if ($LastExitCode -ne 0) { Write-Host "[ERROR]: While executing vendor library compile script from GHDL." -ForegroundColor Red diff --git a/tools/precompile/compile-xilinx-ise.ps1 b/tools/precompile/compile-xilinx-ise.ps1 index 9ccf83f2..9609e176 100644 --- a/tools/precompile/compile-xilinx-ise.ps1 +++ b/tools/precompile/compile-xilinx-ise.ps1 @@ -74,6 +74,13 @@ $WorkingDir = Get-Location $PoCRootDir = Convert-Path (Resolve-Path ($PSScriptRoot + $PoCRootDir)) $PoCPS1 = "$PoCRootDir\poc.ps1" +# set default values +$EnableVerbose = $PSCmdlet.MyInvocation.BoundParameters["Verbose"] +$EnableDebug = $PSCmdlet.MyInvocation.BoundParameters["Debug"] +if ($EnableVerbose -eq $null) { $EnableVerbose = $false } +if ($EnableDebug -eq $null) { $EnableDebug = $false } +if ($EnableDebug -eq $true) { $EnableVerbose = $true } + Import-Module $PSScriptRoot\precompile.psm1 -Verbose:$false -Debug:$false -ArgumentList "$WorkingDir" # Display help if no command was selected @@ -108,7 +115,7 @@ if ($GHDL) $GHDLXilinxScript = "$GHDLScriptDir\compile-xilinx-ise.ps1" if (-not (Test-Path $GHDLXilinxScript -PathType Leaf)) - { Write-Host "[ERROR]: Xilinx compile script from GHDL is not executable." -ForegroundColor Red + { Write-Host "[ERROR]: Xilinx compile script '$GHDLXilinxScript' from GHDL not found." -ForegroundColor Red Exit-PrecompileScript -1 } @@ -120,7 +127,7 @@ if ($GHDL) { $env:GHDL = $GHDLBinDir } if ($VHDL93) - { $Command = "$GHDLXilinxScript -All -VHDL93 -Source $SourceDir -Output $DestDir\$XilinxDirName2" + { $Command = "$GHDLXilinxScript -All -VHDL93 -Source $SourceDir -Output $DestDir\$XilinxDirName2 -Verbose:`$$EnableVerbose -Debug:`$$EnableDebug" Invoke-Expression $Command if ($LastExitCode -ne 0) { Write-Host "[ERROR]: Error while compiling Xilinx ISE libraries." -ForegroundColor Red @@ -128,7 +135,7 @@ if ($GHDL) } } if ($VHDL2008) - { $Command = "$GHDLXilinxScript -All -VHDL2008 -Source $SourceDir -Output $DestDir\$XilinxDirName2" + { $Command = "$GHDLXilinxScript -All -VHDL2008 -Source $SourceDir -Output $DestDir\$XilinxDirName2 -Verbose:`$$EnableVerbose -Debug:`$$EnableDebug" Invoke-Expression $Command if ($LastExitCode -ne 0) { Write-Host "[ERROR]: Error while compiling Xilinx ISE libraries." -ForegroundColor Red diff --git a/tools/precompile/compile-xilinx-vivado.ps1 b/tools/precompile/compile-xilinx-vivado.ps1 index 74bf01e7..912dc168 100644 --- a/tools/precompile/compile-xilinx-vivado.ps1 +++ b/tools/precompile/compile-xilinx-vivado.ps1 @@ -74,6 +74,13 @@ $WorkingDir = Get-Location $PoCRootDir = Convert-Path (Resolve-Path ($PSScriptRoot + $PoCRootDir)) $PoCPS1 = "$PoCRootDir\poc.ps1" +# set default values +$EnableVerbose = $PSCmdlet.MyInvocation.BoundParameters["Verbose"] +$EnableDebug = $PSCmdlet.MyInvocation.BoundParameters["Debug"] +if ($EnableVerbose -eq $null) { $EnableVerbose = $false } +if ($EnableDebug -eq $null) { $EnableDebug = $false } +if ($EnableDebug -eq $true) { $EnableVerbose = $true } + Import-Module $PSScriptRoot\precompile.psm1 -Verbose:$false -Debug:$false -ArgumentList "$WorkingDir" # Display help if no command was selected @@ -108,7 +115,7 @@ if ($GHDL) $GHDLXilinxScript = "$GHDLScriptDir\compile-xilinx-vivado.ps1" if (-not (Test-Path $GHDLXilinxScript -PathType Leaf)) - { Write-Host "[ERROR]: Xilinx compile script from GHDL is not executable." -ForegroundColor Red + { Write-Host "[ERROR]: Xilinx compile script '$GHDLXilinxScript' from GHDL not found." -ForegroundColor Red Exit-PrecompileScript -1 } @@ -120,7 +127,7 @@ if ($GHDL) { $env:GHDL = $GHDLBinDir } if ($VHDL93) - { $Command = "$GHDLXilinxScript -All -VHDL93 -Source $SourceDir -Output $DestDir\$XilinxDirName2" + { $Command = "$GHDLXilinxScript -All -VHDL93 -Source $SourceDir -Output $DestDir\$XilinxDirName2 -Verbose:`$$EnableVerbose -Debug:`$$EnableDebug" Invoke-Expression $Command if ($LastExitCode -ne 0) { Write-Host "[ERROR]: While executing vendor library compile script from GHDL." -ForegroundColor Red @@ -128,7 +135,7 @@ if ($GHDL) } } if ($VHDL2008) - { $Command = "$GHDLXilinxScript -All -VHDL2008 -Source $SourceDir -Output $DestDir\$XilinxDirName2" + { $Command = "$GHDLXilinxScript -All -VHDL2008 -Source $SourceDir -Output $DestDir\$XilinxDirName2 -Verbose:`$$EnableVerbose -Debug:`$$EnableDebug" Invoke-Expression $Command if ($LastExitCode -ne 0) { Write-Host "[ERROR]: While executing vendor library compile script from GHDL." -ForegroundColor Red From 2104a29b3770e2f4e39ff1c34784296ef45d0977 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 8 Nov 2016 02:06:53 +0100 Subject: [PATCH 07/97] Added autoprogram to automatically document PoC's command line interface. Renamed PoC package to allow external tools to discover PoC module in same path. --- docs/GetInvolved/index.rst | 2 +- docs/PoC/arith/arith.pkg.rst | 34 +-- docs/PoC/fifo/fifo_cc_got_tempgot.rst | 21 +- docs/PoC/fifo/fifo_cc_got_tempput.rst | 21 +- docs/PoC/index.rst | 8 - docs/PoC/io/pmod/pmod_SSD.rst | 20 +- docs/PoC/io/vga/vga_phy_ch7301c.rst | 59 +++-- docs/PoC/io/vga/vga_timing.rst | 80 +++---- docs/PoC/misc/sync/index.rst | 2 +- docs/QuickStart.rst | 7 +- docs/References/CommandReference.rst | 28 +-- docs/conf.py | 3 +- py/Base/Compiler.py | 4 +- py/Base/Project.py | 2 +- py/Base/Shared.py | 2 +- py/Base/Simulator.py | 4 +- py/Compiler/ISECompiler.py | 2 +- py/Compiler/LSECompiler.py | 2 +- py/Compiler/QuartusCompiler.py | 2 +- py/Compiler/VivadoCompiler.py | 2 +- py/Compiler/XCICompiler.py | 2 +- py/Compiler/XCOCompiler.py | 2 +- py/Compiler/XSTCompiler.py | 2 +- py/{PoC => DataBase}/Config.py | 0 py/{PoC => DataBase}/Entity.py | 0 py/{PoC => DataBase}/Query.py | 0 py/{PoC => DataBase}/Solution.py | 18 +- py/{PoC => DataBase}/TestCase.py | 0 py/{PoC => DataBase}/__init__.py | 0 py/PoC.py | 26 +- py/Simulator/CocotbSimulator.py | 4 +- py/Simulator/GHDLSimulator.py | 2 +- py/Simulator/QuestaSimulator.py | 2 +- py/ToolChains/GHDL.py | 6 +- src/fifo/fifo_cc_got_tempgot.vhdl | 19 +- src/fifo/fifo_cc_got_tempput.vhdl | 19 +- src/io/pmod/pmod_SSD.vhdl | 20 +- tools/ReadTheDocs/requirements.txt | 2 + tools/Travis-CI/config.private.ini | 2 +- tools/Travis-CI/ghdl/compile-osvvm.sh | 223 ------------------ tools/Travis-CI/ghdl/config.sh | 70 ------ tools/Travis-CI/ghdl/ghdl.grcrules | 15 -- .../Travis-CI/ghdl/ghdl.skipwarning.grcrules | 14 -- tools/Travis-CI/ghdl/shared.sh | 198 ---------------- 44 files changed, 215 insertions(+), 736 deletions(-) rename py/{PoC => DataBase}/Config.py (100%) rename py/{PoC => DataBase}/Entity.py (100%) rename py/{PoC => DataBase}/Query.py (100%) rename py/{PoC => DataBase}/Solution.py (95%) rename py/{PoC => DataBase}/TestCase.py (100%) rename py/{PoC => DataBase}/__init__.py (100%) create mode 100644 tools/ReadTheDocs/requirements.txt delete mode 100755 tools/Travis-CI/ghdl/compile-osvvm.sh delete mode 100644 tools/Travis-CI/ghdl/config.sh delete mode 100644 tools/Travis-CI/ghdl/ghdl.grcrules delete mode 100644 tools/Travis-CI/ghdl/ghdl.skipwarning.grcrules delete mode 100644 tools/Travis-CI/ghdl/shared.sh diff --git a/docs/GetInvolved/index.rst b/docs/GetInvolved/index.rst index c8ad85ae..61de8765 100644 --- a/docs/GetInvolved/index.rst +++ b/docs/GetInvolved/index.rst @@ -13,7 +13,7 @@ interresting project, please send us feedback or get listed on our If you are more familiar with PoC and it's components, you might start asking youself how components internally work. Please read our more advanced topics in the online help, read our inline source code comments or start a discussion on -`Gitter <#discuss-with-us-on-gitter>`_ to ask us directly. +`Gitter <#talk-to-us-on-gitter>`_ to ask us directly. Now you should be very familiar with our work and you might be interessted in developing own components and contribute them to the main repository. See the diff --git a/docs/PoC/arith/arith.pkg.rst b/docs/PoC/arith/arith.pkg.rst index bbf3b007..72c72851 100644 --- a/docs/PoC/arith/arith.pkg.rst +++ b/docs/PoC/arith/arith.pkg.rst @@ -6,29 +6,29 @@ This package holds all component declarations for this namespace. .. rubric:: Exported Enumerations - * ``tArch`` - * ``tBlocking`` - * ``tSkipping`` +* ``tArch`` +* ``tBlocking`` +* ``tSkipping`` .. rubric:: Exported Functions - * ``arith_div_latency`` +* ``arith_div_latency`` .. rubric:: Exported Components - * :doc:`PoC.arith.addw ` - * :doc:`PoC.arith.carrychain_inc_xilinx ` - * :doc:`PoC.arith.counter_bcd ` - * :doc:`PoC.arith.counter_gray ` - * :doc:`PoC.arith.div ` - * :doc:`PoC.arith.firstone ` - * :doc:`PoC.arith.inc_ovcy_xilinx ` - * :doc:`PoC.arith.muls_wide ` - * :doc:`PoC.arith.prefix_and_xilinx ` - * :doc:`PoC.arith.prefix_or_xilinx ` - * :doc:`PoC.arith.prng ` - * :doc:`PoC.arith.same ` - * :doc:`PoC.arith.sqrt ` +* :doc:`PoC.arith.addw ` +* PoC.arith.carrychain_inc_xilinx +* :doc:`PoC.arith.counter_bcd ` +* :doc:`PoC.arith.counter_gray ` +* :doc:`PoC.arith.div ` +* :doc:`PoC.arith.firstone ` +* PoC.arith.inc_ovcy_xilinx +* :doc:`PoC.arith.muls_wide ` +* PoC.arith.prefix_and_xilinx +* PoC.arith.prefix_or_xilinx +* :doc:`PoC.arith.prng ` +* :doc:`PoC.arith.same ` +* :doc:`PoC.arith.sqrt ` Source file: `arith/arith.pkg.vhdl `_ diff --git a/docs/PoC/fifo/fifo_cc_got_tempgot.rst b/docs/PoC/fifo/fifo_cc_got_tempgot.rst index 1cca8eec..7596e4a3 100644 --- a/docs/PoC/fifo/fifo_cc_got_tempgot.rst +++ b/docs/PoC/fifo/fifo_cc_got_tempgot.rst @@ -31,14 +31,19 @@ If a fill state is not of interest, set ``*STATE_*_BITS = 0``. ``fstate_rd`` and ``estate_wr`` are combinatorial outputs and include an address comparator (subtractor) in their path. -Examples: -- FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full - fstate_rd == 1 => 1/2 full (half full) +**Examples:** -- FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full - fstate_rd == 1 => 1/4 full - fstate_rd == 2 => 2/4 full - fstate_rd == 3 => 3/4 full +* FSTATE_RD_BITS = 1: + + * fstate_rd == 0 => 0/2 full + * fstate_rd == 1 => 1/2 full (half full) + +* FSTATE_RD_BITS = 2: + + * fstate_rd == 0 => 0/4 full + * fstate_rd == 1 => 1/4 full + * fstate_rd == 2 => 2/4 full + * fstate_rd == 3 => 3/4 full @@ -48,7 +53,7 @@ Examples: :language: vhdl :tab-width: 2 :linenos: - :lines: 80-109 + :lines: 85-114 Source file: `fifo/fifo_cc_got_tempgot.vhdl `_ diff --git a/docs/PoC/fifo/fifo_cc_got_tempput.rst b/docs/PoC/fifo/fifo_cc_got_tempput.rst index 40a9a611..b94c840a 100644 --- a/docs/PoC/fifo/fifo_cc_got_tempput.rst +++ b/docs/PoC/fifo/fifo_cc_got_tempput.rst @@ -31,14 +31,19 @@ If a fill state is not of interest, set ``*STATE_*_BITS = 0``. ``fstate_rd`` and ``estate_wr`` are combinatorial outputs and include an address comparator (subtractor) in their path. -Examples: -- FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full - fstate_rd == 1 => 1/2 full (half full) +**Examples:** -- FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full - fstate_rd == 1 => 1/4 full - fstate_rd == 2 => 2/4 full - fstate_rd == 3 => 3/4 full +* FSTATE_RD_BITS = 1: + + * fstate_rd == 0 => 0/2 full + * fstate_rd == 1 => 1/2 full (half full) + +* FSTATE_RD_BITS = 2: + + * fstate_rd == 0 => 0/4 full + * fstate_rd == 1 => 1/4 full + * fstate_rd == 2 => 2/4 full + * fstate_rd == 3 => 3/4 full @@ -48,7 +53,7 @@ Examples: :language: vhdl :tab-width: 2 :linenos: - :lines: 80-109 + :lines: 85-114 Source file: `fifo/fifo_cc_got_tempput.vhdl `_ diff --git a/docs/PoC/index.rst b/docs/PoC/index.rst index ea416c0b..3b8755cf 100644 --- a/docs/PoC/index.rst +++ b/docs/PoC/index.rst @@ -24,13 +24,5 @@ Namespaces for Entities: mem/index misc/index net/index - -.. only:: PoCInternal - - .. toctree:: - sata/index - -.. toctree:: - sort/index xil/index diff --git a/docs/PoC/io/pmod/pmod_SSD.rst b/docs/PoC/io/pmod/pmod_SSD.rst index 113c74ef..b0482c82 100644 --- a/docs/PoC/io/pmod/pmod_SSD.rst +++ b/docs/PoC/io/pmod/pmod_SSD.rst @@ -6,16 +6,16 @@ This module drives a dual-digit 7-segment display (Pmod_SSD). The module expects two binary encoded 4-bit ``Digit`` signals and drives a 2x6 bit Pmod connector (7 anode bits, 1 cathode bit). --- code-block:. none - - Segment Pos./ Index - AAA | 000 - F B | 5 1 - F B | 5 1 - GGG | 666 - E C | 4 2 - E C | 4 2 - DDD DOT | 333 7 +.. code-block:: none + + Segment Pos./ Index + AAA | 000 + F B | 5 1 + F B | 5 1 + GGG | 666 + E C | 4 2 + E C | 4 2 + DDD DOT | 333 7 diff --git a/docs/PoC/io/vga/vga_phy_ch7301c.rst b/docs/PoC/io/vga/vga_phy_ch7301c.rst index b8889bf5..f1614b64 100644 --- a/docs/PoC/io/vga/vga_phy_ch7301c.rst +++ b/docs/PoC/io/vga/vga_phy_ch7301c.rst @@ -2,31 +2,38 @@ vga_phy_ch7301c ############### - The clock frequency must be the same as used for the timing module, - e.g., 25 MHZ for VGA 640x480. A phase-shifted clock must be provided: - - clk0 : 0 degrees - - clk90 : 90 degrees - - pixel_data(23 downto 16) : red - pixel_data(15 downto 8) : green - pixel_data( 7 downto 0) : blue - - The "reset_b"-pin must be driven by other logic (such as the reset button). - - The IIC_interface is not part of this modules, as an IIC-master controls - several slaves. The following registers must be set, see - tests/ml505/vga_test_ml505.vhdl for an example. - - Register Value Description - ----------------------------------- - 0x49 PM 0xC0 Enable DVI, RGB bypass off - or 0xD0 Enable DVI, RGB bypass on - 0x33 TPCP 0x08 if clk_freq <= 65 MHz else 0x06 - 0x34 TPD 0x16 if clk_freq <= 65 MHz else 0x26 - 0x36 TPF 0x60 if clk_freq <= 65 MHz else 0xA0 - 0x1F IDF 0x80 when using SMT (VS0, HS0) - or 0x90 when using CVT (VS1, HS0) - 0x21 DC 0x09 Enable DAC if RGB bypass is on +The clock frequency must be the same as used for the timing module, +e.g., 25 MHZ for VGA 640x480. A phase-shifted clock must be provided: +- clk0 : 0 degrees +- clk90 : 90 degrees + +pixel_data(23 downto 16) : red +pixel_data(15 downto 8) : green +pixel_data( 7 downto 0) : blue + +The ``reset_b``-pin must be driven by other logic (such as the reset button). + +The IIC_interface is not part of this modules, as an IIC-master controls +several slaves. The following registers must be set, see +tests/ml505/vga_test_ml505.vhdl for an example. + ++----------+--------------------------------------+---------------------------------+ +| Register | Value | Description | ++==========+======================================+=================================+ +|0x49 PM | 0xC0 | Enable DVI, RGB bypass off | +| | 0xD0 | Enable DVI, RGB bypass on | ++----------+--------------------------------------+---------------------------------+ +|0x33 TPCP | 0x08 if clk_freq <= 65 MHz else 0x06 | | ++----------+--------------------------------------+---------------------------------+ +|0x34 TPD | 0x16 if clk_freq <= 65 MHz else 0x26 | | ++----------+--------------------------------------+---------------------------------+ +|0x36 TPF | 0x60 if clk_freq <= 65 MHz else 0xA0 | | ++----------+--------------------------------------+---------------------------------+ +|0x1F IDF | 0x80 | when using SMT (VS0, HS0) | +| | 0x90 | when using CVT (VS1, HS0) | ++----------+--------------------------------------+---------------------------------+ +|0x21 DC | 0x09 | Enable DAC if RGB bypass is on | ++----------+--------------------------------------+---------------------------------+ @@ -36,7 +43,7 @@ vga_phy_ch7301c :language: vhdl :tab-width: 2 :linenos: - :lines: 63-76 + :lines: 70-83 Source file: `io/vga/vga_phy_ch7301c.vhdl `_ diff --git a/docs/PoC/io/vga/vga_timing.rst b/docs/PoC/io/vga/vga_timing.rst index 445402bf..fdde46c5 100644 --- a/docs/PoC/io/vga/vga_timing.rst +++ b/docs/PoC/io/vga/vga_timing.rst @@ -2,46 +2,46 @@ vga_timing ########## - Configuration: - -------------- - MODE = 0: VGA mode with 640x480 pixels, 60 Hz, frequency(clk) ~ 25 MHz - MODE = 1: HD 720p with 1280x720 pixels, 60 Hz, frequency(clk) = 74,5 MHz - MODE = 2: HD 1080p with 1920x1080 pixels, 60 Hz, frequency(clk) = 138,5 MHz - - MODE = 2 uses reduced blanking => only suitable for LCDs. - - For MODE = 0, CVT can be configured: - - CVT = false: Use Safe Mode Timing (SMT). - The legacy fall-back mode supported by CRTs as well as LCDs. - HSync: low-active. VSync: low-active. - frequency(clk) = 25.175 MHz. (25 MHz works => 31 kHz / 59 Hz) - - CVT = true: The "new" Coordinated Video Timing (since 2003). - The CVT supports some new features, such as reduced blanking (for LCDs) or - aspect ratio encoding. See the web for more details. - Standard CRT-based timing (CVT-GTF) has been implemented for best - compatibility: - HSync: low-active. VSync: high-active. - frequency(clk) = 23.75 MHz. (25 MHz works => 31 kHz / 62 Hz) - - Usage: - ------ - The frequency of 'clk' must be equal to the pixel clock frequency of the - selected video mode, see also above. - - When using analog output, the VGA color signals must be blanked, during - horizontal and vertical beam return. This could be achieved by - combinatorial "anding" the color value with "beam_on" (part of "phy_ctrl") - inside the PHY. - - When using digital output (DVI), then "beam_on" is equal to "DE" - (Data Enable) of the DVI transmitter. - - xvalid and yvalid show if xpos respectivly ypos are in a valid range. - beam_on is '1' iff both xvalid and yvalid = '1'. - - xpos and ypos also show the pixel location during blanking. - This might be useful in some applications. But be careful, that the ranges - differ between SMT and CVT. +Configuration: +-------------- +MODE = 0: VGA mode with 640x480 pixels, 60 Hz, frequency(clk) ~ 25 MHz +MODE = 1: HD 720p with 1280x720 pixels, 60 Hz, frequency(clk) = 74,5 MHz +MODE = 2: HD 1080p with 1920x1080 pixels, 60 Hz, frequency(clk) = 138,5 MHz + +MODE = 2 uses reduced blanking => only suitable for LCDs. + +For MODE = 0, CVT can be configured: +- CVT = false: Use Safe Mode Timing (SMT). + The legacy fall-back mode supported by CRTs as well as LCDs. + HSync: low-active. VSync: low-active. + frequency(clk) = 25.175 MHz. (25 MHz works => 31 kHz / 59 Hz) +- CVT = true: The "new" Coordinated Video Timing (since 2003). + The CVT supports some new features, such as reduced blanking (for LCDs) or + aspect ratio encoding. See the web for more details. + Standard CRT-based timing (CVT-GTF) has been implemented for best + compatibility: + HSync: low-active. VSync: high-active. + frequency(clk) = 23.75 MHz. (25 MHz works => 31 kHz / 62 Hz) + +Usage: +------ +The frequency of ``clk`` must be equal to the pixel clock frequency of the +selected video mode, see also above. + +When using analog output, the VGA color signals must be blanked, during +horizontal and vertical beam return. This could be achieved by +combinatorial "anding" the color value with "beam_on" (part of "phy_ctrl") +inside the PHY. + +When using digital output (DVI), then "beam_on" is equal to "DE" +(Data Enable) of the DVI transmitter. + +xvalid and yvalid show if xpos respectivly ypos are in a valid range. +beam_on is '1' iff both xvalid and yvalid = '1'. + +xpos and ypos also show the pixel location during blanking. +This might be useful in some applications. But be careful, that the ranges +differ between SMT and CVT. diff --git a/docs/PoC/misc/sync/index.rst b/docs/PoC/misc/sync/index.rst index 8468f00f..8c7caf2f 100644 --- a/docs/PoC/misc/sync/index.rst +++ b/docs/PoC/misc/sync/index.rst @@ -5,7 +5,7 @@ The namespace ``PoC.misc.sync`` offers different clock-domain-crossing (CDC) synchronizer circuits. All synchronizers are based on the basic 2 flip-flop synchonizer called :doc:`sync_Bits `. PoC has two platform specific implementations for Altera and Xilinx, which are choosen, -if the appropriate ``MY_DEVICE`` constant is configured in :doc:`my_config.vhdl `. +if the appropriate ``MY_DEVICE`` constant is configured in ``my_config.vhdl``. **Decision Table:** diff --git a/docs/QuickStart.rst b/docs/QuickStart.rst index 8e12e863..12f45cc1 100644 --- a/docs/QuickStart.rst +++ b/docs/QuickStart.rst @@ -106,7 +106,7 @@ clone the PoC-Library as a Git `submodule `. -.. code-block:: powershell +.. code-block:: PowerShell cd ProjectRoot mkdir lib | cd @@ -117,13 +117,14 @@ list of steps can be found at :doc:`Integration `. git add .gitmodules lib\PoC git commit -m "Added new git submodule PoC in 'lib\PoC' (PoC-Library)." + .. rubric:: 2. Configuring PoC The PoC-Library should be configured to explore its full potential. See :doc:`Configuration ` for more details. The following command lines will start the configuration process: -.. code-block:: powershell +.. code-block:: PowerShell cd ProjectRoot .\lib\PoC\poc.ps1 configure @@ -137,7 +138,7 @@ target information. Copy the following two template files into your project's source folder. Rename these files to \*.vhdl and configure the VHDL constants in the files: -.. code-block:: powershell +.. code-block:: PowerShell cd ProjectRoot cp lib\PoC\src\common\my_config.vhdl.template src\common\my_config.vhdl diff --git a/docs/References/CommandReference.rst b/docs/References/CommandReference.rst index 5aea0ba5..fd6fe437 100644 --- a/docs/References/CommandReference.rst +++ b/docs/References/CommandReference.rst @@ -4,29 +4,5 @@ Command Reference .. contents:: Contents of this Page - -Headline 4 -********************** - -Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. -At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor -sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et -accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet - - -Headline 5 -********************** - -Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. -At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor -sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et -accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet - - -Headline 6 -******************* - -Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. -At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor -sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et -accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet +.. autoprogram:: PoCSphinx:parser + :prog: PoC.py diff --git a/docs/conf.py b/docs/conf.py index fdbd4b99..278a4800 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -38,6 +38,7 @@ 'sphinx.ext.ifconfig', 'sphinx.ext.viewcode', # 'sphinx.ext.githubpages', + 'sphinxcontrib.autoprogram', 'poc' ] @@ -313,4 +314,4 @@ # Example configuration for intersphinx: refer to the Python standard library. -intersphinx_mapping = {'https://docs.python.org/': None} +intersphinx_mapping = {'https://docs.python.org/2/': None} diff --git a/py/Base/Compiler.py b/py/Base/Compiler.py index f2b62193..565bca70 100644 --- a/py/Base/Compiler.py +++ b/py/Base/Compiler.py @@ -53,8 +53,8 @@ from Base.Project import VHDLVersion, Environment, FileTypes from Base.Shared import Shared, to_time from Parser.RulesParser import CopyRuleMixIn, ReplaceRuleMixIn, DeleteRuleMixIn, AppendLineRuleMixIn -from PoC.Solution import RulesFile -from PoC.TestCase import SynthesisSuite, Synthesis, CompileStatus +from DataBase.Solution import RulesFile +from DataBase.TestCase import SynthesisSuite, Synthesis, CompileStatus class CompilerException(ExceptionBase): diff --git a/py/Base/Project.py b/py/Base/Project.py index e1c4fdd7..781abeb9 100644 --- a/py/Base/Project.py +++ b/py/Base/Project.py @@ -38,7 +38,7 @@ from lib.Functions import merge from Base.Exceptions import CommonException from Parser.FilesParser import VHDLSourceFileMixIn, VerilogSourceFileMixIn, CocotbSourceFileMixIn -from PoC.Config import Board, Device +from DataBase.Config import Board, Device # TODO: nested filesets diff --git a/py/Base/Shared.py b/py/Base/Shared.py index eaf1f65d..cd9f7904 100644 --- a/py/Base/Shared.py +++ b/py/Base/Shared.py @@ -49,7 +49,7 @@ from Base.Exceptions import CommonException, SkipableCommonException from Base.Logging import ILogable from Base.Project import ToolChain, Tool, VHDLVersion, Environment -from PoC.Solution import VirtualProject, FileListFile +from DataBase.Solution import VirtualProject, FileListFile # local helper function diff --git a/py/Base/Simulator.py b/py/Base/Simulator.py index dc50ef81..72e79f64 100644 --- a/py/Base/Simulator.py +++ b/py/Base/Simulator.py @@ -50,8 +50,8 @@ from Base.Logging import LogEntry from Base.Project import Environment, VHDLVersion from Base.Shared import Shared, to_time -from PoC.Entity import WildCard -from PoC.TestCase import TestCase, SimulationStatus, TestSuite +from DataBase.Entity import WildCard +from DataBase.TestCase import TestCase, SimulationStatus, TestSuite VHDL_TESTBENCH_LIBRARY_NAME = "test" diff --git a/py/Compiler/ISECompiler.py b/py/Compiler/ISECompiler.py index eb6be960..1bf881c2 100644 --- a/py/Compiler/ISECompiler.py +++ b/py/Compiler/ISECompiler.py @@ -43,7 +43,7 @@ # load dependencies from Base.Project import ToolChain, Tool from Base.Compiler import Compiler as BaseCompiler -from PoC.Entity import WildCard, FQN, EntityTypes +from DataBase.Entity import WildCard, FQN, EntityTypes from Compiler.XCOCompiler import Compiler as XCOCompiler from Compiler.XSTCompiler import Compiler as XSTCompiler diff --git a/py/Compiler/LSECompiler.py b/py/Compiler/LSECompiler.py index a3cd3e3b..63af6ae6 100644 --- a/py/Compiler/LSECompiler.py +++ b/py/Compiler/LSECompiler.py @@ -48,7 +48,7 @@ from Base.Exceptions import PlatformNotSupportedException from Base.Compiler import Compiler as BaseCompiler, CompilerException, SkipableCompilerException, CompileState from Base.Project import ToolChain, Tool, VHDLVersion -from PoC.Entity import WildCard +from DataBase.Entity import WildCard from ToolChains.Lattice.Lattice import LatticeException from ToolChains.Lattice.Diamond import Diamond, SynthesisArgumentFile diff --git a/py/Compiler/QuartusCompiler.py b/py/Compiler/QuartusCompiler.py index 0b898598..787b4910 100644 --- a/py/Compiler/QuartusCompiler.py +++ b/py/Compiler/QuartusCompiler.py @@ -47,7 +47,7 @@ from Base.Project import ToolChain, Tool from Base.Compiler import Compiler as BaseCompiler, CompilerException, SkipableCompilerException, CompileState -from PoC.Entity import WildCard +from DataBase.Entity import WildCard from ToolChains.Altera.Quartus import QuartusException, Quartus, QuartusSettings, QuartusProjectFile diff --git a/py/Compiler/VivadoCompiler.py b/py/Compiler/VivadoCompiler.py index 23000667..85714e7a 100644 --- a/py/Compiler/VivadoCompiler.py +++ b/py/Compiler/VivadoCompiler.py @@ -48,7 +48,7 @@ from Base.Project import ToolChain, Tool, FileTypes from Base.Compiler import Compiler as BaseCompiler, CompilerException, SkipableCompilerException, CompileState -from PoC.Entity import WildCard +from DataBase.Entity import WildCard from ToolChains.Xilinx.Vivado import Vivado, VivadoException diff --git a/py/Compiler/XCICompiler.py b/py/Compiler/XCICompiler.py index a461e3f3..96f44017 100644 --- a/py/Compiler/XCICompiler.py +++ b/py/Compiler/XCICompiler.py @@ -49,7 +49,7 @@ from Base.Project import ToolChain, Tool from Base.Compiler import Compiler as BaseCompiler, CompilerException, SkipableCompilerException, CompileState -from PoC.Entity import WildCard +from DataBase.Entity import WildCard from ToolChains.Xilinx.Vivado import Vivado, VivadoException diff --git a/py/Compiler/XCOCompiler.py b/py/Compiler/XCOCompiler.py index 4cd5bcff..8bb90357 100644 --- a/py/Compiler/XCOCompiler.py +++ b/py/Compiler/XCOCompiler.py @@ -50,7 +50,7 @@ from Base.Project import ToolChain, Tool from Base.Compiler import Compiler as BaseCompiler, CompilerException, SkipableCompilerException, CompileState -from PoC.Entity import WildCard +from DataBase.Entity import WildCard from ToolChains.Xilinx.ISE import ISE, ISEException diff --git a/py/Compiler/XSTCompiler.py b/py/Compiler/XSTCompiler.py index dfcae207..7e84d5ca 100644 --- a/py/Compiler/XSTCompiler.py +++ b/py/Compiler/XSTCompiler.py @@ -47,7 +47,7 @@ from Base.Project import ToolChain, Tool from Base.Compiler import Compiler as BaseCompiler, CompilerException, SkipableCompilerException, CompileState -from PoC.Entity import WildCard +from DataBase.Entity import WildCard from ToolChains.Xilinx.Xilinx import XilinxProjectExportMixIn from ToolChains.Xilinx.ISE import ISE, ISEException diff --git a/py/PoC/Config.py b/py/DataBase/Config.py similarity index 100% rename from py/PoC/Config.py rename to py/DataBase/Config.py diff --git a/py/PoC/Entity.py b/py/DataBase/Entity.py similarity index 100% rename from py/PoC/Entity.py rename to py/DataBase/Entity.py diff --git a/py/PoC/Query.py b/py/DataBase/Query.py similarity index 100% rename from py/PoC/Query.py rename to py/DataBase/Query.py diff --git a/py/PoC/Solution.py b/py/DataBase/Solution.py similarity index 95% rename from py/PoC/Solution.py rename to py/DataBase/Solution.py index c05c0f26..b86ce7c8 100644 --- a/py/PoC/Solution.py +++ b/py/DataBase/Solution.py @@ -32,9 +32,6 @@ # ============================================================================== # entry point -from PoC.Entity import Visibility - - if __name__ != "__main__": # place library initialization code here pass @@ -44,16 +41,17 @@ # load dependencies -from collections import OrderedDict -from textwrap import dedent +from collections import OrderedDict +from textwrap import dedent -from lib.Decorators import ILazyLoadable, LazyLoadTrigger +from lib.Decorators import ILazyLoadable, LazyLoadTrigger from Base.Exceptions import CommonException from Base.Configuration import ConfigurationException -from Base.Project import Project as BaseProject, File, FileTypes, VHDLSourceFile, VerilogSourceFile, CocotbSourceFile #, ProjectFile -from Parser.FilesParser import FilesParserMixIn -from Parser.RulesParser import RulesParserMixIn -from PoC import __POC_SOLUTION_KEYWORD__ +from Base.Project import Project as BaseProject, File, FileTypes, VHDLSourceFile, VerilogSourceFile, CocotbSourceFile #, ProjectFile +from Parser.FilesParser import FilesParserMixIn +from Parser.RulesParser import RulesParserMixIn +from DataBase import __POC_SOLUTION_KEYWORD__ +from DataBase.Entity import Visibility class Base(ILazyLoadable): diff --git a/py/PoC/TestCase.py b/py/DataBase/TestCase.py similarity index 100% rename from py/PoC/TestCase.py rename to py/DataBase/TestCase.py diff --git a/py/PoC/__init__.py b/py/DataBase/__init__.py similarity index 100% rename from py/PoC/__init__.py rename to py/DataBase/__init__.py diff --git a/py/PoC.py b/py/PoC.py index 95ced25b..76223964 100644 --- a/py/PoC.py +++ b/py/PoC.py @@ -32,7 +32,7 @@ # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================== - +# from argparse import RawDescriptionHelpFormatter from collections import OrderedDict from configparser import Error as ConfigParser_Error, DuplicateOptionError @@ -56,10 +56,10 @@ from Compiler.XCOCompiler import Compiler as XCOCompiler from Compiler.XSTCompiler import Compiler as XSTCompiler from Compiler.VivadoCompiler import Compiler as VivadoCompiler -from PoC.Config import Board -from PoC.Entity import NamespaceRoot, FQN, EntityTypes, WildCard, TestbenchKind, NetlistKind -from PoC.Solution import Repository -from PoC.Query import Query +from DataBase.Config import Board +from DataBase.Entity import NamespaceRoot, FQN, EntityTypes, WildCard, TestbenchKind, NetlistKind +from DataBase.Solution import Repository +from DataBase.Query import Query from Simulator.ActiveHDLSimulator import Simulator as ActiveHDLSimulator from Simulator.CocotbSimulator import Simulator as CocotbSimulator from Simulator.GHDLSimulator import Simulator as GHDLSimulator @@ -140,7 +140,7 @@ class __ConfigFiles__: Project = None - def __init__(self, debug, verbose, quiet, dryRun): + def __init__(self, debug, verbose, quiet, dryRun, sphinx=False): # Call the initializer of ILogable # -------------------------------------------------------------------------- if quiet: severity = Severity.Quiet @@ -151,15 +151,12 @@ def __init__(self, debug, verbose, quiet, dryRun): logger = Logger(self, severity, printToStdOut=True) ILogable.__init__(self, logger=logger) - # Do some basic checks - self.__CheckEnvironment() - # Call the constructor of the ArgParseMixin # -------------------------------------------------------------------------- description = dedent("""\ This is the PoC-Library Service Tool. """) - epilog = "Epidingsbums" + epilog = "Pile-of-Cores" class HelpFormatter(RawDescriptionHelpFormatter): def __init__(self, *args, **kwargs): @@ -167,6 +164,10 @@ def __init__(self, *args, **kwargs): super().__init__(*args, **kwargs) ArgParseMixin.__init__(self, description=description, epilog=epilog, formatter_class=HelpFormatter, add_help=False) + if sphinx: return + + # Do some basic checks + self.__CheckEnvironment() # declare members # -------------------------------------------------------------------------- @@ -1160,5 +1161,6 @@ def main(): # mccabe:disable=MC0001 if __name__ == "__main__": Exit.versionCheck((3,5,0)) main() -else: - Exit.printThisIsNoLibraryFile(PoC.HeadLine) +# else: +# print(__name__) +# Exit.printThisIsNoLibraryFile(PoC.HeadLine) diff --git a/py/Simulator/CocotbSimulator.py b/py/Simulator/CocotbSimulator.py index 692598d9..8e6725b9 100644 --- a/py/Simulator/CocotbSimulator.py +++ b/py/Simulator/CocotbSimulator.py @@ -49,8 +49,8 @@ from Base.Project import FileTypes, ToolChain, Tool from Base.Simulator import SimulatorException, Simulator as BaseSimulator -from PoC.Config import Vendors -from PoC.Entity import WildCard +from DataBase.Config import Vendors +from DataBase.Entity import WildCard from ToolChains.GNU import Make diff --git a/py/Simulator/GHDLSimulator.py b/py/Simulator/GHDLSimulator.py index 173fe967..cc91b2ba 100644 --- a/py/Simulator/GHDLSimulator.py +++ b/py/Simulator/GHDLSimulator.py @@ -201,7 +201,7 @@ def _RunSimulation(self, testbench): testbench.WaveformFile = waveformFilePath if testbench.WaveformOptionFile.exists(): - ghdl.RunOptions[ghdl.SwitchWaveformSelect] = testbench.WaveformOptionFile + ghdl.RunOptions[ghdl.SwitchWaveformOptionFile] = testbench.WaveformOptionFile testbench.Result = ghdl.Run() diff --git a/py/Simulator/QuestaSimulator.py b/py/Simulator/QuestaSimulator.py index 177490fa..752f9844 100644 --- a/py/Simulator/QuestaSimulator.py +++ b/py/Simulator/QuestaSimulator.py @@ -45,7 +45,7 @@ from Base.Exceptions import NotConfiguredException from Base.Project import FileTypes, ToolChain, Tool from Base.Simulator import SimulatorException, Simulator as BaseSimulator, VHDL_TESTBENCH_LIBRARY_NAME, SkipableSimulatorException -from PoC.Config import Vendors +from DataBase.Config import Vendors from ToolChains.Mentor.QuestaSim import QuestaSim, QuestaSimException diff --git a/py/ToolChains/GHDL.py b/py/ToolChains/GHDL.py index 3fe21b5c..69f6d021 100644 --- a/py/ToolChains/GHDL.py +++ b/py/ToolChains/GHDL.py @@ -309,8 +309,8 @@ class SwitchFastWaveform(metaclass=LongValuedFlagArgument): class SwitchGHDLWaveform(metaclass=LongValuedFlagArgument): _name = "wave" - class SwitchWaveformSelect(metaclass=LongValuedFlagArgument): - _name = "wave-opt-file" # requires GHDL update + class SwitchWaveformOptionFile(metaclass=LongValuedFlagArgument): + _name = "read-opt-file" # requires GHDL update RunOptions = CommandLineArgumentList( SwitchIEEEAsserts, @@ -318,7 +318,7 @@ class SwitchWaveformSelect(metaclass=LongValuedFlagArgument): SwitchVCDGZWaveform, SwitchFastWaveform, SwitchGHDLWaveform, - SwitchWaveformSelect + SwitchWaveformOptionFile ) def GetGHDLAnalyze(self): diff --git a/src/fifo/fifo_cc_got_tempgot.vhdl b/src/fifo/fifo_cc_got_tempgot.vhdl index 998a1555..ee1115e9 100644 --- a/src/fifo/fifo_cc_got_tempgot.vhdl +++ b/src/fifo/fifo_cc_got_tempgot.vhdl @@ -40,14 +40,19 @@ -- ``fstate_rd`` and ``estate_wr`` are combinatorial outputs and include an address -- comparator (subtractor) in their path. -- --- Examples: --- - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full --- fstate_rd == 1 => 1/2 full (half full) +-- **Examples:** -- --- - FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full --- fstate_rd == 1 => 1/4 full --- fstate_rd == 2 => 2/4 full --- fstate_rd == 3 => 3/4 full +-- * FSTATE_RD_BITS = 1: +-- +-- * fstate_rd == 0 => 0/2 full +-- * fstate_rd == 1 => 1/2 full (half full) +-- +-- * FSTATE_RD_BITS = 2: +-- +-- * fstate_rd == 0 => 0/4 full +-- * fstate_rd == 1 => 1/4 full +-- * fstate_rd == 2 => 2/4 full +-- * fstate_rd == 3 => 3/4 full -- -- License: -- ============================================================================= diff --git a/src/fifo/fifo_cc_got_tempput.vhdl b/src/fifo/fifo_cc_got_tempput.vhdl index 169c7837..71078ca9 100644 --- a/src/fifo/fifo_cc_got_tempput.vhdl +++ b/src/fifo/fifo_cc_got_tempput.vhdl @@ -40,14 +40,19 @@ -- ``fstate_rd`` and ``estate_wr`` are combinatorial outputs and include an address -- comparator (subtractor) in their path. -- --- Examples: --- - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full --- fstate_rd == 1 => 1/2 full (half full) +-- **Examples:** -- --- - FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full --- fstate_rd == 1 => 1/4 full --- fstate_rd == 2 => 2/4 full --- fstate_rd == 3 => 3/4 full +-- * FSTATE_RD_BITS = 1: +-- +-- * fstate_rd == 0 => 0/2 full +-- * fstate_rd == 1 => 1/2 full (half full) +-- +-- * FSTATE_RD_BITS = 2: +-- +-- * fstate_rd == 0 => 0/4 full +-- * fstate_rd == 1 => 1/4 full +-- * fstate_rd == 2 => 2/4 full +-- * fstate_rd == 3 => 3/4 full -- -- License: -- ============================================================================= diff --git a/src/io/pmod/pmod_SSD.vhdl b/src/io/pmod/pmod_SSD.vhdl index 8476986b..291fb7c3 100644 --- a/src/io/pmod/pmod_SSD.vhdl +++ b/src/io/pmod/pmod_SSD.vhdl @@ -12,20 +12,20 @@ -- expects two binary encoded 4-bit ``Digit`` signals and drives a 2x6 bit -- Pmod connector (7 anode bits, 1 cathode bit). -- --- -- code-block:. none +-- .. code-block:: none -- --- Segment Pos./ Index --- AAA | 000 --- F B | 5 1 --- F B | 5 1 --- GGG | 666 --- E C | 4 2 --- E C | 4 2 --- DDD DOT | 333 7 +-- Segment Pos./ Index +-- AAA | 000 +-- F B | 5 1 +-- F B | 5 1 +-- GGG | 666 +-- E C | 4 2 +-- E C | 4 2 +-- DDD DOT | 333 7 -- -- License: -- ============================================================================= --- Copyright 2007-2015 Technische Universitaet Dresden - Germany +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/tools/ReadTheDocs/requirements.txt b/tools/ReadTheDocs/requirements.txt new file mode 100644 index 00000000..cf8fed3f --- /dev/null +++ b/tools/ReadTheDocs/requirements.txt @@ -0,0 +1,2 @@ +-r ../../requirements.txt +sphinxcontrib-autoprogram diff --git a/tools/Travis-CI/config.private.ini b/tools/Travis-CI/config.private.ini index fec7939f..7bd4c30b 100644 --- a/tools/Travis-CI/config.private.ini +++ b/tools/Travis-CI/config.private.ini @@ -1,5 +1,5 @@ [INSTALL.PoC] -Version = 1.0.0 +Version = 1.1.0 InstallationDirectory = /home/travis/build/VLSI-EDA/PoC [SOLUTION.Solutions] diff --git a/tools/Travis-CI/ghdl/compile-osvvm.sh b/tools/Travis-CI/ghdl/compile-osvvm.sh deleted file mode 100755 index ab9c553f..00000000 --- a/tools/Travis-CI/ghdl/compile-osvvm.sh +++ /dev/null @@ -1,223 +0,0 @@ -#! /usr/bin/env bash -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# -# ============================================================================== -# Authors: Patrick Lehmann -# -# Bash Script: Script to compile the OSVVM library for GHDL on Linux -# -# Description: -# ------------------------------------ -# This is a Bash script (executable) which: -# - creates a subdirectory in the current working directory -# - compiles all OSVVM packages -# -# ============================================================================== -# Copyright (C) 2015-2016 Patrick Lehmann -# -# GHDL is free software; you can redistribute it and/or modify it under -# the terms of the GNU General Public License as published by the Free -# Software Foundation; either version 2, or (at your option) any later -# version. -# -# GHDL is distributed in the hope that it will be useful, but WITHOUT ANY -# WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# for more details. -# -# You should have received a copy of the GNU General Public License -# along with GHDL; see the file COPYING. If not, write to the Free -# Software Foundation, 59 Temple Place - Suite 330, Boston, MA -# 02111-1307, USA. -# ============================================================================== - -# --------------------------------------------- -# work around for Darwin (Mac OS) -READLINK=readlink; if [[ $(uname) == "Darwin" ]]; then READLINK=greadlink; fi - -# save working directory -WorkingDir=$(pwd) -ScriptDir="$(dirname $0)" -ScriptDir="$($READLINK -f $ScriptDir)" - -# source configuration file from GHDL's 'vendors' library directory -source $ScriptDir/config.sh -source $ScriptDir/shared.sh - -# command line argument processing -NO_COMMAND=1 -SUPPRESS_WARNINGS=0 -HALT_ON_ERROR=0 -GHDLBinDir="" -DestDir="" -SrcDir="" -while [[ $# > 0 ]]; do - key="$1" - case $key in - -c|--clean) - CLEAN=TRUE - NO_COMMAND=0 - ;; - -a|--all) - COMPILE_ALL=TRUE - NO_COMMAND=0 - ;; - --osvvm) - COMPILE_OSVVM=TRUE - NO_COMMAND=0 - ;; - -h|--help) - HELP=TRUE - NO_COMMAND=0 - ;; - -n|--no-warnings) - SUPPRESS_WARNINGS=1 - ;; - -H|--halt-on-error) - HALT_ON_ERROR=1 - ;; - --ghdl) - GHDLBinDir="$2" - shift # skip argument - ;; - --src) - SrcDir="$2" - shift # skip argument - ;; - --out) - DestDir="$2" - shift # skip argument - ;; - *) # unknown option - echo 1>&2 -e "${COLORED_ERROR} Unknown command line option '$key'.${ANSI_NOCOLOR}" - exit -1 - ;; - esac - shift # skip argument or value -done - -# makes no sense to enable it for OSVVM -SKIP_EXISTING_FILES=0 - -if [ $NO_COMMAND -eq 1 ]; then - HELP=TRUE -fi - -if [ "$HELP" == "TRUE" ]; then - test $NO_COMMAND -eq 1 && echo 1>&2 -e "\n${COLORED_ERROR} No command selected." - echo "" - echo "Synopsis:" - echo " A script to compile the simulation library 'OSVVM' for GHDL on Linux." - echo " A library folder 'osvvm/v08' will be created relative to the current" - echo " working directory." - echo "" - echo " Use the adv. options or edit 'config.sh' to supply paths and default params." - echo "" - echo "Usage:" - echo " compile-osvvm.sh | [] []" - echo "" - echo "Common commands:" - echo " -h --help Print this help page" - echo " -c --clean Remove all generated files" - echo "" - echo "Libraries:" - echo " -a --all Compile all libraries." - echo " --osvvm Compile library osvvm." - echo "" - echo "Library compile options:" - echo " -H --halt-on-error Halt on error(s)." - echo "" - echo "Advanced options:" - echo " --ghdl Path to GHDL's binary e.g. /usr/local/bin/ghdl." - echo " --out Name of the output directory." - echo " --src Path to the source directory." - echo "" - echo "Verbosity:" - echo " -n --no-warnings Suppress all warnings. Show only error messages." - echo "" - exit 0 -fi - -if [ "$COMPILE_ALL" == "TRUE" ]; then - COMPILE_OSVVM=TRUE -fi - - -# -> $SourceDirectories -# -> $DestinationDirectories -# -> $SrcDir -# -> $DestDir -# -> $GHDLBinDir -# <= $SourceDirectory -# <= $DestinationDirectory -# <= $GHDLBinary -SetupDirectories OSVVM "OSVVM" - -# create "osvvm" directory and change to it -# => $DestinationDirectory -CreateDestinationDirectory -cd $DestinationDirectory - - -# => $SUPPRESS_WARNINGS -# <= $GRC_COMMAND -SetupGRCat - - -# define global GHDL Options -GHDL_OPTIONS=(-fexplicit -frelaxed-rules --no-vital-checks --warn-binding --mb-comments) - - -# Cleanup directory -# ============================================================================== -if [ "$CLEAN" == "TRUE" ]; then - echo -e "${ANSI_YELLOW}Cleaning up directory ...${ANSI_NOCOLOR}" - rm *.o 2> /dev/null - rm *.cf 2> /dev/null -fi - - -# create local set of GHDL parameters -GHDL_PARAMS=(${GHDL_OPTIONS[@]}) -GHDL_PARAMS+=(--std=08) -VHDLVersion="v08" - -# Library osvvm -# ============================================================================== -# compile osvvm packages -ERRORCOUNT=0 -if [ "$COMPILE_OSVVM" == "TRUE" ]; then - Library="osvvm" - Files=( - NamePkg.vhd - OsvvmGlobalPkg.vhd - TextUtilPkg.vhd - TranscriptPkg.vhd - AlertLogPkg.vhd - MemoryPkg.vhd - MessagePkg.vhd - SortListPkg_int.vhd - RandomBasePkg.vhd - RandomPkg.vhd - CoveragePkg.vhd - OsvvmContext.vhd - ) - - # append absolute source path - SourceFiles=() - for File in ${Files[@]}; do - SourceFiles+=("$SourceDirectory/$File") - done - - GHDLCompilePackages -fi - -echo "--------------------------------------------------------------------------------" -echo -n "Compiling OSVVM packages " -if [ $ERRORCOUNT -gt 0 ]; then - echo -e $COLORED_FAILED -else - echo -e $COLORED_SUCCESSFUL -fi diff --git a/tools/Travis-CI/ghdl/config.sh b/tools/Travis-CI/ghdl/config.sh deleted file mode 100644 index 6eb3125f..00000000 --- a/tools/Travis-CI/ghdl/config.sh +++ /dev/null @@ -1,70 +0,0 @@ -#! /bin/bash -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# -# ============================================================================== -# Authors: Patrick Lehmann -# -# Bash Script: Configurable directories to local installed tools -# -# Description: -# ------------------------------------ -# This Bash file exports variables containing the users local tool environment. -# -# ============================================================================== -# Copyright (C) 2015-2016 Patrick Lehmann -# -# GHDL is free software; you can redistribute it and/or modify it under -# the terms of the GNU General Public License as published by the Free -# Software Foundation; either version 2, or (at your option) any later -# version. -# -# GHDL is distributed in the hope that it will be useful, but WITHOUT ANY -# WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# for more details. -# -# You should have received a copy of the GNU General Public License -# along with GHDL; see the file COPYING. If not, write to the Free -# Software Foundation, 59 Temple Place - Suite 330, Boston, MA -# 02111-1307, USA. -# ============================================================================== - - -# Configure -# - vendor tool chain installation paths or -# - library root directories -# in the following dictionary. -# -# These values are used if no command line argument (--src) is passed to a -# compile script. Empty strings means not configured. -declare -A InstallationDirectories -InstallationDirectories[AlteraQuartus]="" # "/opt/altera/16.0/quartus" -InstallationDirectories[LatticeDiamond]="" # "/usr/local/diamond/3.7_x64" -InstallationDirectories[OSVVM]="" # "~/git/github/osvvm" -InstallationDirectories[VUnit]="" # "~/git/github/vunit" -InstallationDirectories[XilinxISE]="" # "/opt/Xilinx/14.7/ISE_DS/ISE" -InstallationDirectories[XilinxVivado]="" # "/opt/Xilinx/Vivado/2016.2" - -# Configure preferred output directories for each library set: -declare -A DestinationDirectories -DestinationDirectories[AlteraQuartus]="altera" -DestinationDirectories[LatticeDiamond]="lattice" -DestinationDirectories[OSVVM]="." # "osvvm" -DestinationDirectories[VUnit]="." # "vunit_lib" -DestinationDirectories[XilinxISE]="xilinx-ise" -DestinationDirectories[XilinxVivado]="xilinx-vivado" - -# Declare source directories depending on the installation paths: -declare -A SourceDirectories -SourceDirectories[AlteraQuartus]="eda/sim_lib" -SourceDirectories[XilinxISE]="vhdl/src" -SourceDirectories[XilinxVivado]="data/vhdl/src" -SourceDirectories[LatticeDiamond]="cae_library/simulation/vhdl" -SourceDirectories[OSVVM]="." -SourceDirectories[VUnit]="vunit/vhdl" - -# input files greater than $LARGE_FILESIZE are skipped if '--skip-largefiles' is set -LARGE_FILESIZE=125000 - diff --git a/tools/Travis-CI/ghdl/ghdl.grcrules b/tools/Travis-CI/ghdl/ghdl.grcrules deleted file mode 100644 index 1bc60783..00000000 --- a/tools/Travis-CI/ghdl/ghdl.grcrules +++ /dev/null @@ -1,15 +0,0 @@ -# color warnings -regexp=^.*?:\d+:\d+:warning: .* -colours=yellow -count=stop -========= - -# color errors -regexp=^.*?:\d+:\d+: .* -colours=red -count=stop -========= - -# skip additional message line on Linux -regexp=^ghdl: compilation error -skip=yes diff --git a/tools/Travis-CI/ghdl/ghdl.skipwarning.grcrules b/tools/Travis-CI/ghdl/ghdl.skipwarning.grcrules deleted file mode 100644 index 0609b060..00000000 --- a/tools/Travis-CI/ghdl/ghdl.skipwarning.grcrules +++ /dev/null @@ -1,14 +0,0 @@ -# skip warnings -regexp=^.*?:\d+:\d+:warning: .* -skip=yes -========= - -# color errors -regexp=^.*?:\d+:\d+: .* -colours=red -count=stop -========= - -# skip additional message line on Linux -regexp=^ghdl: compilation error -skip=yes diff --git a/tools/Travis-CI/ghdl/shared.sh b/tools/Travis-CI/ghdl/shared.sh deleted file mode 100644 index 3c413bec..00000000 --- a/tools/Travis-CI/ghdl/shared.sh +++ /dev/null @@ -1,198 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# -# ============================================================================== -# Authors: Patrick Lehmann -# -# Bash Script: This is a Bash resource file. -# -# Description: -# ------------------------------------ -# TODO -# -# ============================================================================== -# Copyright (C) 2015 Patrick Lehmann -# -# GHDL is free software; you can redistribute it and/or modify it under -# the terms of the GNU General Public License as published by the Free -# Software Foundation; either version 2, or (at your option) any later -# version. -# -# GHDL is distributed in the hope that it will be useful, but WITHOUT ANY -# WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# for more details. -# -# You should have received a copy of the GNU General Public License -# along with GHDL; see the file COPYING. If not, write to the Free -# Software Foundation, 59 Temple Place - Suite 330, Boston, MA -# 02111-1307, USA. -# ============================================================================== - -ANSI_RED="\e[31m" -ANSI_GREEN="\e[32m" -ANSI_YELLOW="\e[33m" -ANSI_BLUE="\e[34m" -ANSI_MAGENTA="\e[35m" -ANSI_CYAN="\e[36;1m" -ANSI_NOCOLOR="\e[0m" - -# red texts -COLORED_ERROR="$ANSI_RED[ERROR]$ANSI_NOCOLOR" -COLORED_FAILED="$ANSI_RED[FAILED]$ANSI_NOCOLOR" - -# green texts -COLORED_DONE="$ANSI_GREEN[DONE]$ANSI_NOCOLOR" -COLORED_SUCCESSFUL="$ANSI_GREEN[SUCCESSFUL]$ANSI_NOCOLOR" - -# set bash options -set -o pipefail - -SetupDirectories() { - Index=$1 - Name=$2 - - # source directory - # ---------------------- - # If a command line argument ('--src') was passed in, use it, else use the default value - # from config.sh - if [ ! -z "$SrcDir" ]; then - SourceDirectory=${SrcDir%/} # remove trailing slashes - elif [ ! -z "$EnvSourceDir" ]; then - SourceDirectory=$EnvSourceDir # fall back to environment variable - elif [ ! -z "${InstallationDirectories[$Index]}" ]; then - SourceDirectory=${InstallationDirectories[$Index]}/${SourceDirectories[$Index]} # fall back to value from config.sh - fi - # output directory - # ---------------------- - # If a command line argument ('--out') was passed in, use it, else use the default value - # from config.sh - if [ ! -z "$DestDir" ]; then - DestinationDirectory=${DestDir%/} # remove trailing slashes - else - DestinationDirectory=${DestinationDirectories[$Index]} # fall back to value from config.sh - fi - - if [ -z $SourceDirectory ] || [ -z $DestinationDirectory ]; then - echo 1>&2 -e "${COLORED_ERROR} $Name is not configured in '$ScriptDir/config.sh'${ANSI_NOCOLOR}" - echo 1>&2 -e " Use adv. options '--src' and '--out' or configure 'config.sh'." - exit -1 - elif [ ! -d $SourceDirectory ]; then - echo 1>&2 -e "${COLORED_ERROR} Path '$SourceDirectory' does not exist.${ANSI_NOCOLOR}" - exit -1 - fi - - # Resolve paths to an absolute paths - SourceDirectory=$(readlink -f $SourceDirectory) - if [[ ! "$DestinationDirectory" = /* ]]; then - DestinationDirectory=$WorkingDir/$DestinationDirectory - fi - - # Use GHDL binary directory from command line argument, if set - if [ ! -z "$GHDLBinDir" ]; then - GHDLBinary=${GHDLBinDir%/}/ghdl # remove trailing slashes - if [[ ! -x "$GHDLBinary" ]]; then - echo 1>&2 -e "${COLORED_ERROR} GHDL not found or is not executable.${ANSI_NOCOLOR}" - exit -1 - fi - elif [ ! -z "$GHDL" ]; then - if [ ! \( -f "$GHDL" -a -x "$GHDL" \) ]; then - echo 1>&2 -e "${COLORED_ERROR} Found GHDL environment variable, but '$GHDL' is not executable.${ANSI_NOCOLOR}" - exit -1 - fi - GHDLBinary=$GHDL - else # fall back to GHDL found via PATH - GHDLBinary=$(which ghdl 2>/dev/null) - if [ $? -ne 0 ]; then - echo 1>&2 -e "${COLORED_ERROR} GHDL not found in PATH.${ANSI_NOCOLOR}" - echo 1>&2 -e " Use adv. options '--ghdl' to set the GHDL binary directory." - exit -1 - fi - fi -} - -SetupGRCat() { - if [ -z "$(which grcat 2>/dev/null)" ]; then - # if grcat (generic colourizer) is not installed, use a dummy pipe command like 'cat' - GRC_COMMAND="cat" - elif [ $SUPPRESS_WARNINGS -eq 1 ]; then - GRC_COMMAND="grcat $ScriptDir/ghdl.skipwarning.grcrules" - else - GRC_COMMAND="grcat $ScriptDir/ghdl.grcrules" - fi -} - -CreateDestinationDirectory() { - if [ -d "$DestinationDirectory" ]; then - echo -e "${ANSI_YELLOW}Vendor directory '$DestinationDirectory' already exists.${ANSI_NOCOLOR}" - elif [ -f "$DestinationDirectory" ]; then - echo 1>&2 -e "${COLORED_ERROR} Vendor directory '$DestinationDirectory' already exists as a file.${ANSI_NOCOLOR}" - exit -1 - else - echo -e "${ANSI_YELLOW}Creating vendor directory: '$DestinationDirectory'${ANSI_NOCOLOR}" - mkdir -p "$DestinationDirectory" - fi -} - -GHDLSetup() { - if [ $VHDLStandard -eq 93 ]; then - VHDLVersion="v93" - VHDLStandard="93c" - VHDLFlavor="synopsys" - elif [ $VHDLStandard -eq 2008 ]; then - VHDLVersion="v08" - VHDLStandard="08" - VHDLFlavor="standard" - fi -} - -GHDLCompileLibrary() { - # assembling output directory - LibraryDirectory=$DestinationDirectory/$Library/$VHDLVersion - mkdir -p $LibraryDirectory - cd $LibraryDirectory - echo -e "${ANSI_YELLOW}Compiling library '$Library'...${ANSI_NOCOLOR}" - - for File in ${SourceFiles[@]}; do - FileName=$(basename "$File") - FileSize=($(wc -c $File)) - if [ $SKIP_EXISTING_FILES -eq 1 ] && [ -e "${FileName%.*}.o" ]; then - echo -e "${ANSI_CYAN}Skipping existing file '$File'${ANSI_NOCOLOR}" - elif [ $SKIP_LARGE_FILES -eq 1 ] && [ ${FileSize[0]} -gt $LARGE_FILESIZE ]; then - echo -e "${ANSI_CYAN}Skipping large file '$File'${ANSI_NOCOLOR}" - else - echo -e "${ANSI_CYAN}Analyzing file '$File'${ANSI_NOCOLOR}" - $GHDLBinary -a ${GHDL_PARAMS[@]} --work=$Library "$File" 2>&1 | $GRC_COMMAND - if [ $? -ne 0 ]; then - let ERRORCOUNT++ - test $HALT_ON_ERROR -eq 1 && return 1 - fi - fi - done - return 0 -} - -GHDLCompilePackages() { - # assembling output directory - LibraryDirectory=$DestinationDirectory/$Library/$VHDLVersion - mkdir -p $LibraryDirectory - cd $LibraryDirectory - echo -e "${ANSI_YELLOW}Compiling library '$Library'...${ANSI_NOCOLOR}" - - for File in ${SourceFiles[@]}; do - FileName=$(basename "$File") - if [ $SKIP_EXISTING_FILES -eq 1 ] && [ -e "${FileName%.*}.o" ]; then - echo -e "${ANSI_CYAN}Skipping existing package '$File'${ANSI_NOCOLOR}" - else - echo -e "${ANSI_CYAN}Analyzing package '$File'${ANSI_NOCOLOR}" - $GHDLBinary -a ${GHDL_PARAMS[@]} --work=$Library "$File" 2>&1 | $GRC_COMMAND - if [ $? -ne 0 ]; then - let ERRORCOUNT++ - test $HALT_ON_ERROR -eq 1 && return 1 - fi - fi - done - return 0 -} - From e05cd0bf21fcda2cbfd43b5cdafe14a8af08a81f Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 8 Nov 2016 02:14:08 +0100 Subject: [PATCH 08/97] Added a minimal version to autoprogram dependency. --- tools/ReadTheDocs/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/ReadTheDocs/requirements.txt b/tools/ReadTheDocs/requirements.txt index cf8fed3f..5314194f 100644 --- a/tools/ReadTheDocs/requirements.txt +++ b/tools/ReadTheDocs/requirements.txt @@ -1,2 +1,2 @@ +sphinxcontrib-autoprogram>=0.1.3 -r ../../requirements.txt -sphinxcontrib-autoprogram From f18522336fe8a8f492537a3839c36ff813b5a30e Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 8 Nov 2016 02:28:43 +0100 Subject: [PATCH 09/97] ReadTheDocs: Fixed yaml file. --- .readthedocs.yml | 5 +++++ readthedocs.yml | 5 ----- tools/ReadTheDocs/requirements.txt | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) create mode 100644 .readthedocs.yml delete mode 100644 readthedocs.yml diff --git a/.readthedocs.yml b/.readthedocs.yml new file mode 100644 index 00000000..8b91f62b --- /dev/null +++ b/.readthedocs.yml @@ -0,0 +1,5 @@ +formats: + - pdf +requirements_file: tools/ReadTheDocs/requirements.txt +python: + version: 3 diff --git a/readthedocs.yml b/readthedocs.yml deleted file mode 100644 index e8d6ad67..00000000 --- a/readthedocs.yml +++ /dev/null @@ -1,5 +0,0 @@ -formats: - - pdf -requirements_file: requirements.txt -python: - version: 3 diff --git a/tools/ReadTheDocs/requirements.txt b/tools/ReadTheDocs/requirements.txt index 5314194f..453cbc7e 100644 --- a/tools/ReadTheDocs/requirements.txt +++ b/tools/ReadTheDocs/requirements.txt @@ -1,2 +1,2 @@ -sphinxcontrib-autoprogram>=0.1.3 -r ../../requirements.txt +sphinxcontrib-autoprogram>=0.1.3 From d1b24733356617a33fae8c66f5780fdb8f0ec0ca Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 8 Nov 2016 02:32:12 +0100 Subject: [PATCH 10/97] Added missing introspection file for autoprogram. --- docs/PoCSphinx.py | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 docs/PoCSphinx.py diff --git a/docs/PoCSphinx.py b/docs/PoCSphinx.py new file mode 100644 index 00000000..c341dbcf --- /dev/null +++ b/docs/PoCSphinx.py @@ -0,0 +1,40 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# Python Main Module: Entry point for Sphinx analysis tools (e.g. autoprogram). +# +# Description: +# ------------------------------------ +# Undocumented +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# distributed under the License is distributed on an "AS IS" BASIS,default +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +# +from sys import path as sys_path + +sys_path.append("../py") + +from PoC import PoC + +# entry point +parser = PoC(False, False, False, True, sphinx=True).MainParser From 40caacc51c1bd3676bb6b9f093d4cdda9b77e0ac Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 8 Nov 2016 02:43:11 +0100 Subject: [PATCH 11/97] Added a workaround for ReadTheDocs with old Python 3.4. --- py/lib/ExtendedConfigParser/__init__.py | 69 ++++++++++++++++++++++++- 1 file changed, 68 insertions(+), 1 deletion(-) diff --git a/py/lib/ExtendedConfigParser/__init__.py b/py/lib/ExtendedConfigParser/__init__.py index b4af9d24..fac6e50f 100644 --- a/py/lib/ExtendedConfigParser/__init__.py +++ b/py/lib/ExtendedConfigParser/__init__.py @@ -32,17 +32,84 @@ # limitations under the License. # ============================================================================== # +import functools import re -from collections import OrderedDict as _default_dict, ChainMap as _ChainMap +from sys import version_info + +from collections import OrderedDict as _default_dict, ChainMap as _ChainMap, MutableMapping from configparser import ConfigParser, SectionProxy, Interpolation, MAX_INTERPOLATION_DEPTH, DEFAULTSECT, _UNSET, ConverterMapping from configparser import NoSectionError, InterpolationDepthError, InterpolationSyntaxError, NoOptionError, InterpolationMissingOptionError +import itertools + + class ExtendedSectionProxy(SectionProxy): def __getitem__(self, key): if not self._parser.has_option(self._name, key): raise KeyError(self._name + ":" + key) return self._parser.get(self._name, key) +# WORKAROUND: Required for ReadTheDocs, which doesn't support Python 3.5 yet. +if (version_info < (3,5,0)): + class ConverterMapping(MutableMapping): + """Enables reuse of get*() methods between the parser and section proxies. + + If a parser class implements a getter directly, the value for the given + key will be ``None``. The presence of the converter name here enables + section proxies to find and use the implementation on the parser class. + """ + + GETTERCRE = re.compile(r"^get(?P.+)$") + + def __init__(self, parser): + self._parser = parser + self._data = {} + for getter in dir(self._parser): + m = self.GETTERCRE.match(getter) + if not m or not callable(getattr(self._parser, getter)): + continue + self._data[m.group('name')] = None # See class docstring. + + def __getitem__(self, key): + return self._data[key] + + def __setitem__(self, key, value): + try: + k = 'get' + key + except TypeError: + raise ValueError('Incompatible key: {} (type: {})' + ''.format(key, type(key))) + if k == 'get': + raise ValueError('Incompatible key: cannot use "" as a name') + self._data[key] = value + func = functools.partial(self._parser._get_conv, conv=value) + func.converter = value + setattr(self._parser, k, func) + for proxy in self._parser.values(): + getter = functools.partial(proxy.get, _impl=func) + setattr(proxy, k, getter) + + def __delitem__(self, key): + try: + k = 'get' + (key or None) + except TypeError: + raise KeyError(key) + del self._data[key] + for inst in itertools.chain((self._parser,), self._parser.values()): + try: + delattr(inst, k) + except AttributeError: + # don't raise since the entry was present in _data, silently + # clean up + continue + + def __iter__(self): + return iter(self._data) + + def __len__(self): + return len(self._data) + + # Monkey patching ... (a.k.a. duck punshing import configparser configparser.SectionProxy = ExtendedSectionProxy From 7ffb0b7504613089480e68c01cfc508927632642 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 8 Nov 2016 02:48:22 +0100 Subject: [PATCH 12/97] Removed old files. --- py/lib/ArgParseAttributes.py | 172 -------------- py/lib/ConfigParser.py | 304 ------------------------ py/lib/ExtendedConfigParser/__init__.py | 1 + py/lib/pyAttribute.py | 100 -------- 4 files changed, 1 insertion(+), 576 deletions(-) delete mode 100644 py/lib/ArgParseAttributes.py delete mode 100644 py/lib/ConfigParser.py delete mode 100644 py/lib/pyAttribute.py diff --git a/py/lib/ArgParseAttributes.py b/py/lib/ArgParseAttributes.py deleted file mode 100644 index b883df47..00000000 --- a/py/lib/ArgParseAttributes.py +++ /dev/null @@ -1,172 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# -# ============================================================================= -# _ _ _ _ _ _ -# _ __ _ _ / \ | |_| |_ _ __(_) |__ _ _| |_ ___ -# | '_ \| | | | / _ \| __| __| '__| | '_ \| | | | __/ _ \ -# | |_) | |_| |/ ___ \ |_| |_| | | | |_) | |_| | || __/ -# | .__/ \__, /_/ \_\__|\__|_| |_|_.__/ \__,_|\__\___| -# |_| |___/ -# -# ============================================================================= -# Authors: Patrick Lehmann -# -# Python package: ArgParse pyAttribute attributes -# -# Description: -# ------------------------------------ -# Predefined attributes for ArgParse -# -# License: -# ============================================================================ -# Copyright 2007-2016 Patrick Lehmann - Dresden, Germany -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# ============================================================================ - -from .pyAttribute import Attribute, AttributeHelperMixin - - -class CommandGroupAttribute(Attribute): - __groupName = "" - - def __init__(self, groupName): - super().__init__() - self.__groupName = groupName - - @property - def GroupName(self): - return self.__groupName - -class DefaultAttribute(Attribute): - __handler = None - - def __call__(self, func): - self.__handler = func - return super().__call__(func) - - @property - def Handler(self): - return self.__handler - -class CommandAttribute(Attribute): - __command = "" - __handler = None - __kwargs = None - - def __init__(self, command, **kwargs): - super().__init__() - self.__command = command - self.__kwargs = kwargs - - def __call__(self, func): - self.__handler = func - return super().__call__(func) - - @property - def Command(self): - return self.__command - - @property - def Handler(self): - return self.__handler - - @property - def KWArgs(self): - return self.__kwargs - -class ArgumentAttribute(Attribute): - __args = None - __kwargs = None - - def __init__(self, *args, **kwargs): - super().__init__() - self.__args = args - self.__kwargs = kwargs - - @property - def Args(self): - return self.__args - - @property - def KWArgs(self): - return self.__kwargs - -class SwitchArgumentAttribute(ArgumentAttribute): - def __init__(self, *args, **kwargs): - kwargs['action'] = "store_const" - kwargs['const'] = True - kwargs['default'] = False - super().__init__(*args, **kwargs) - -class CommonArgumentAttribute(ArgumentAttribute): - pass - -class CommonSwitchArgumentAttribute(SwitchArgumentAttribute): - pass - -class ArgParseMixin(AttributeHelperMixin): - __mainParser = None - __subParser = None - __subParsers = {} - - def __init__(self, **kwargs): - super().__init__() - - # create a commandline argument parser - import argparse - self.__mainParser = argparse.ArgumentParser(**kwargs) - self.__subParser = self.__mainParser.add_subparsers(help='sub-command help') - - for _,func in CommonArgumentAttribute.GetMethods(self): - for comAttribute in CommonArgumentAttribute.GetAttributes(func): - self.__mainParser.add_argument(*(comAttribute.Args), **(comAttribute.KWArgs)) - - for _,func in CommonSwitchArgumentAttribute.GetMethods(self): - for comAttribute in CommonSwitchArgumentAttribute.GetAttributes(func): - self.__mainParser.add_argument(*(comAttribute.Args), **(comAttribute.KWArgs)) - - for _,func in self.GetMethods(): - defAttributes = DefaultAttribute.GetAttributes(func) - if (len(defAttributes) != 0): - defAttribute = defAttributes[0] - self.__mainParser.set_defaults(func=defAttribute.Handler) - continue - - cmdAttributes = CommandAttribute.GetAttributes(func) - if (len(cmdAttributes) != 0): - cmdAttribute = cmdAttributes[0] - subParser = self.__subParser.add_parser(cmdAttribute.Command, **(cmdAttribute.KWArgs)) - subParser.set_defaults(func=cmdAttribute.Handler) - - for argAttribute in ArgumentAttribute.GetAttributes(func): - subParser.add_argument(*(argAttribute.Args), **(argAttribute.KWArgs)) - - self.__subParsers[cmdAttribute.Command] = subParser - continue - - def Run(self): - # parse command line options and process splitted arguments in callback functions - args = self.__mainParser.parse_args() - # because func is a function (unbound to an object), it MUST be called with self as a first parameter - args.func(self, args) - - @property - def MainParser(self): - return self.__mainParser - - @property - def SubParsers(self): - return self.__subParsers diff --git a/py/lib/ConfigParser.py b/py/lib/ConfigParser.py deleted file mode 100644 index 2924aa1e..00000000 --- a/py/lib/ConfigParser.py +++ /dev/null @@ -1,304 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# -# ============================================================================== -# Authors: Patrick Lehmann -# -# Python Class: Derived and extended configparser from Python standard library -# -# Description: -# ------------------------------------ -# - Improved interpolation algorithm -# - Added an interpolation cache -# - Added recursive interpolation (indirect addressing): ${key1.${key2:opt2}:opt1} -# - Added %{keyword} interpolation, to access the section name: %{parent} -# - Added support for multiple DEFAULT sections [CONFIG.DEFAULT] for all [CONFIG.**] sections -# -# License: -# ============================================================================== -# Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# ============================================================================== -# -import re -from collections import OrderedDict as _default_dict, ChainMap as _ChainMap -from configparser import ConfigParser, SectionProxy, Interpolation, MAX_INTERPOLATION_DEPTH, DEFAULTSECT, _UNSET, ConverterMapping -from configparser import NoSectionError, InterpolationDepthError, InterpolationSyntaxError, NoOptionError, InterpolationMissingOptionError - -class ExtendedSectionProxy(SectionProxy): - def __getitem__(self, key): - if not self._parser.has_option(self._name, key): - raise KeyError(self._name + ":" + key) - return self._parser.get(self._name, key) - -# Monkey patching ... (a.k.a. duck punshing -import configparser -configparser.SectionProxy = ExtendedSectionProxy - - -class ExtendedInterpolation(Interpolation): - _KEYCRE = re.compile(r"\$\{(?P[^}]+)\}") - _KEYCRE2 = re.compile(r"\$\[(?P[^\]]+)\}") - - def __init__(self): - self._cache = dict() - - def clear_cache(self): - self._cache = dict() - - def before_get(self, parser, section, option, value, defaults): - # print("before_get: {0}:{1} = '{2}'".format(section, option, value)) - try: - result = self.GetCached(section, option) - except KeyError: - result = self.interpolate(parser, section, option, value, defaults) - self.UpdateCache(section, option, result) - # print("before_get: => '{0}'\n".format(result)) - return result - - def before_set(self, parser, section, option, value): - tmp_value = value.replace("$$", "") # escaped dollar signs - tmp_value = self._KEYCRE.sub("", tmp_value) # valid syntax - if '$' in tmp_value: - raise ValueError("invalid interpolation syntax in {0!r} at position {1}".format(value, tmp_value.find("$"))) - return value - - def interpolate(self, parser, section, option, value, _, depth=0): - if depth > MAX_INTERPOLATION_DEPTH: raise InterpolationDepthError(option, section, value) - - # short cut operations if empty or a normal string - if (value == ""): - # print("interpol: SHORT -> empty string") - return "" - elif (("$" not in value) and ("%" not in value)): - # print("interpol: SHORT -> {0}".format(value)) - return value - - # print("interpol: PREPARE section={0} option={1} value='{2}'".format(section, option, value)) - rawValue = value - rest = "" - - while (len(rawValue) > 0): - beginPos = rawValue.find("%") - if (beginPos < 0): - rest += rawValue - rawValue = "" - else: - rest += rawValue[:beginPos] - if (rawValue[beginPos + 1] == "%"): - rest += "%" - rawValue = rawValue[1:] - elif (rawValue[beginPos + 1] == "{"): - endPos = rawValue.find("}", beginPos) - if (endPos < 0): - raise InterpolationSyntaxError(option, section, "bad interpolation variable reference {0!r}".format(rawValue)) - path = rawValue[beginPos + 2:endPos] - rawValue = rawValue[endPos + 1:] - rest += self.GetSpecial(section, option, path) - - # print("interpol: BEGIN section={0} option={1} value='{2}'".format(section, option, rest)) - result = "" - while (len(rest) > 0): - # print("interpol: LOOP rest='{0}'".format(rest)) - beginPos = rest.find("$") - if (beginPos < 0): - result += rest - rest = "" - else: - result += rest[:beginPos] - if (rest[beginPos + 1] == "$"): - result += "$" - rest = rest[1:] - elif (rest[beginPos + 1] == "{"): - endPos = rest.find("}", beginPos) - nextPos = rest.rfind("$", beginPos, endPos) - if (endPos < 0): raise InterpolationSyntaxError(option, section, "bad interpolation variable reference {0!r}".format(rest)) - if ((nextPos > 0) and (nextPos < endPos)): # an embedded $-sign - path = rest[nextPos+2:endPos] - # print("interpol: path='{0}'".format(path)) - innervalue = self.GetValue(parser, section, option, path) - # innervalue = self.interpolate(parser, section, option, path, map, depth + 1) - # print("interpol: innervalue='{0}'".format(innervalue)) - rest = rest[beginPos:nextPos] + innervalue + rest[endPos + 1:] - # print("interpol: new rest='{0}'".format(rest)) - else: - path = rest[beginPos+2:endPos] - rest = rest[endPos+1:] - result += self.GetValue(parser, section, option, path) - - # print("interpol: LOOP END - result='{0}'".format(result)) - - # print("interpol: RESULT => '{0}'".format(result)) - return result - - def GetSpecial(self, section, option, path): - parts = section.split(".") - if (path == "Root"): - return parts[0] - elif (path == "Parent"): - return ".".join(parts[1:-1]) - elif (path == "ParentWithRoot"): - return ".".join(parts[:-1]) - elif (path == "GrantParent"): - return ".".join(parts[1:-2]) - elif (path == "Path"): - return ".".join(parts[1:]) - elif (path == "PathWithRoot"): - return section - elif (path == "Name"): - return parts[-1] - else: - raise InterpolationSyntaxError(option, section, "Unknown keyword '{0}'in special operator.".format(path)) - - def GetValue(self, parser, section, option, path): - path = path.split(":") - if (len(path) == 1): - sec = section - opt = parser.optionxform(path[0]) - elif (len(path) == 2): - sec = path[0] - opt = parser.optionxform(path[1]) - else: - raise InterpolationSyntaxError(option, section, "More than one ':' found.") - - try: - return self.GetCached(sec, opt) - except KeyError: - pass - - try: - value = parser.get(sec, opt, raw=True) - # print("GetValue: successful parser access: '{0}'".format(value)) - except (KeyError, NoSectionError, NoOptionError) as ex: - raise InterpolationMissingOptionError(option, section, "", ":".join(path)) from ex - - if (("$" in value) or ("%" in value)): - value = self.interpolate(parser, sec, opt, value, {}) - - self.UpdateCache(sec, opt, value) - return value - - def GetCached(self, section, option): - # print("GetCached: {0}:{1}".format(section, option)) - if (section not in self._cache): - raise KeyError(section) - sect = self._cache[section] - if (option not in sect): - raise KeyError("{0}:{1}".format(section, option)) - - value = sect[option] - # print("GetCached: found: {0}".format(value)) - return value - - def UpdateCache(self, section, option, value): - # print("UpdateCache: {0}:{1} <- {2}".format(section, option, value)) - if (section in self._cache): - sect = self._cache[section] - if (option in sect): raise Exception("This value is already cached.") - sect[option] = value - else: - self._cache[section] = {option : value} - - -class ExtendedConfigParser(ConfigParser): - _DEFAULT_INTERPOLATION = ExtendedInterpolation() - - def __init__(self, defaults=None, dict_type=_default_dict, allow_no_value=False, *, delimiters=('=', ':'), comment_prefixes=('#', ';'), inline_comment_prefixes=None, - strict=True, empty_lines_in_values=True, default_section=DEFAULTSECT, interpolation=_UNSET, converters=_UNSET): - # replacement of ConfigParser.__init__, do not call super-class constructor - self._dict = dict_type - self._defaults = dict_type() - self._sections = dict_type() - self._proxies = dict_type() - self._cache = dict() - - self._comment_prefixes = tuple(comment_prefixes or ()) - self._inline_comment_prefixes = tuple(inline_comment_prefixes or ()) - self._strict = strict - self._allow_no_value = allow_no_value - self._empty_lines_in_values = empty_lines_in_values - self.default_section = default_section - - self._converters = ConverterMapping(self) - if (converters is not _UNSET): - self._converters.update(converters) - - self._proxies[default_section] = SectionProxy(self, default_section) - - if defaults: - for key, value in defaults.items(): - self._defaults[self.optionxform(key)] = value - - self._delimiters = tuple(delimiters) - if delimiters == ('=', ':'): - self._optcre = self.OPTCRE_NV if allow_no_value else self.OPTCRE - else: - d = "|".join(re.escape(d) for d in delimiters) - if allow_no_value: self._optcre = re.compile(self._OPT_NV_TMPL.format(delim=d), re.VERBOSE) - else: self._optcre = re.compile(self._OPT_TMPL.format(delim=d), re.VERBOSE) - - if (interpolation is None): self._interpolation = Interpolation() - elif (interpolation is _UNSET): self._interpolation = ExtendedInterpolation() - else: self._interpolation = interpolation - - @property - def Interpolation(self): - return self._interpolation - - def _unify_values(self, section, variables): - """Create a sequence of lookups with 'variables' taking priority over - the 'section' which takes priority over the DEFAULTSECT. - - """ - try: - sectiondict = self._sections[section] - except KeyError: - if section != self.default_section: - raise NoSectionError(section) - else: - sectiondict = {} - - # Update with the entry specific variables - vardict = {} - if variables: - for key, value in variables.items(): - if value is not None: - value = str(value) - vardict[self.optionxform(key)] = value - prefix = section.split(".",1)[0] + ".DEFAULT" - # print("searched for {0}".format(prefix)) - try: - defaultdict = self._sections[prefix] - return _ChainMap(vardict, sectiondict, defaultdict, self._defaults) - except KeyError: - return _ChainMap(vardict, sectiondict, self._defaults) - - def has_option(self, section, option): - """Check for the existence of a given option in a given section. - If the specified `section' is None or an empty string, DEFAULT is - assumed. If the specified `section' does not exist, returns False.""" - option = self.optionxform(option) - if ((not section) or (section == self.default_section)): - sect = self._defaults - else: - prefix = section.split(".", 1)[0] + ".DEFAULT" - if ((prefix in self) and (option in self._sections[prefix])): - return True - if (section not in self._sections): - return False - else: - sect = self._sections[section] - return option in sect diff --git a/py/lib/ExtendedConfigParser/__init__.py b/py/lib/ExtendedConfigParser/__init__.py index fac6e50f..e833ca11 100644 --- a/py/lib/ExtendedConfigParser/__init__.py +++ b/py/lib/ExtendedConfigParser/__init__.py @@ -51,6 +51,7 @@ def __getitem__(self, key): # WORKAROUND: Required for ReadTheDocs, which doesn't support Python 3.5 yet. if (version_info < (3,5,0)): + print("Patching ConfigParser for ReadTheDocs. " + str(version_info)) class ConverterMapping(MutableMapping): """Enables reuse of get*() methods between the parser and section proxies. diff --git a/py/lib/pyAttribute.py b/py/lib/pyAttribute.py deleted file mode 100644 index b315dd8f..00000000 --- a/py/lib/pyAttribute.py +++ /dev/null @@ -1,100 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# -# ============================================================================= -# _ _ _ _ _ _ -# _ __ _ _ / \ | |_| |_ _ __(_) |__ _ _| |_ ___ -# | '_ \| | | | / _ \| __| __| '__| | '_ \| | | | __/ _ \ -# | |_) | |_| |/ ___ \ |_| |_| | | | |_) | |_| | || __/ -# | .__/ \__, /_/ \_\__|\__|_| |_|_.__/ \__,_|\__\___| -# |_| |___/ -# -# ============================================================================= -# Authors: Patrick Lehmann -# -# Python package: pyAttribute base classes -# -# Description: -# ------------------------------------ -# Implements user defined attributes for Python -# -# License: -# ============================================================================ -# Copyright 2007-2016 Patrick Lehmann - Dresden, Germany -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# ============================================================================ - -class Attribute: - __AttributesMemberName__ = "__pyattr__" - _debug = False - - def __call__(self, func): - self._AppendAttribute(func, self) - return func - - @staticmethod - def _AppendAttribute(func, attribute): - # inherit attributes and append myself or create a new attributes list - if (Attribute.__AttributesMemberName__ in func.__dict__): - func.__dict__[Attribute.__AttributesMemberName__].append(attribute) - else: - func.__setattr__(Attribute.__AttributesMemberName__, [attribute]) - - def __str__(self): - return self.__name__ - - @classmethod - def GetMethods(cls, cl): - methods = {} - for funcname,func in cl.__class__.__dict__.items(): - if hasattr(func, '__dict__'): - if (Attribute.__AttributesMemberName__ in func.__dict__): - attributes = func.__dict__[Attribute.__AttributesMemberName__] - if isinstance(attributes, list): - for attribute in attributes: - if isinstance(attribute, cls): - methods[funcname] = func - return methods.items() - - @classmethod - def GetAttributes(cls, method): - if (Attribute.__AttributesMemberName__ in method.__dict__): - attributes = method.__dict__[Attribute.__AttributesMemberName__] - if isinstance(attributes, list): - return [attribute for attribute in attributes if isinstance(attribute, cls)] - return list() - - -class AttributeHelperMixin: - def GetMethods(self): - return { - funcname: func - for funcname, func in self.__class__.__dict__.items() - if hasattr(func, '__dict__') - }.items() - - def HasAttribute(self, method): - if (Attribute.__AttributesMemberName__ in method.__dict__): - attributeList = method.__dict__[Attribute.__AttributesMemberName__] - return (isinstance(attributeList, list) and (len(attributeList) != 0)) - else: - return False - - def GetAttributes(self, method): - if (Attribute.__AttributesMemberName__ in method.__dict__): - attributeList = method.__dict__[Attribute.__AttributesMemberName__] - if isinstance(attributeList, list): - return attributeList - return list() From cbfe464cf99652b65827cfc83b35bec2e75dfd18 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 8 Nov 2016 02:51:14 +0100 Subject: [PATCH 13/97] Import must be moved into else branch. --- py/lib/ExtendedConfigParser/__init__.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/py/lib/ExtendedConfigParser/__init__.py b/py/lib/ExtendedConfigParser/__init__.py index e833ca11..756a74c8 100644 --- a/py/lib/ExtendedConfigParser/__init__.py +++ b/py/lib/ExtendedConfigParser/__init__.py @@ -37,7 +37,7 @@ from sys import version_info from collections import OrderedDict as _default_dict, ChainMap as _ChainMap, MutableMapping -from configparser import ConfigParser, SectionProxy, Interpolation, MAX_INTERPOLATION_DEPTH, DEFAULTSECT, _UNSET, ConverterMapping +from configparser import ConfigParser, SectionProxy, Interpolation, MAX_INTERPOLATION_DEPTH, DEFAULTSECT, _UNSET from configparser import NoSectionError, InterpolationDepthError, InterpolationSyntaxError, NoOptionError, InterpolationMissingOptionError import itertools @@ -109,6 +109,8 @@ def __iter__(self): def __len__(self): return len(self._data) +else: + from configparser import ConverterMapping # Monkey patching ... (a.k.a. duck punshing From d9b757f7771d0b9d6fff26a7089e7fce19a10c82 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 8 Nov 2016 02:56:41 +0100 Subject: [PATCH 14/97] Removed debug message. --- py/lib/ExtendedConfigParser/__init__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/py/lib/ExtendedConfigParser/__init__.py b/py/lib/ExtendedConfigParser/__init__.py index 756a74c8..00336355 100644 --- a/py/lib/ExtendedConfigParser/__init__.py +++ b/py/lib/ExtendedConfigParser/__init__.py @@ -49,9 +49,9 @@ def __getitem__(self, key): raise KeyError(self._name + ":" + key) return self._parser.get(self._name, key) + # WORKAROUND: Required for ReadTheDocs, which doesn't support Python 3.5 yet. if (version_info < (3,5,0)): - print("Patching ConfigParser for ReadTheDocs. " + str(version_info)) class ConverterMapping(MutableMapping): """Enables reuse of get*() methods between the parser and section proxies. From e176b669e6b22a0938f58476ef360c2914445f49 Mon Sep 17 00:00:00 2001 From: Martin Zabel Date: Tue, 8 Nov 2016 10:02:41 +0100 Subject: [PATCH 15/97] Published missing files. --- py/Wrapper/PoC.psm1 | 400 +++++++++++++++++++++++++++++++++++++ py/Wrapper/PowerShell.psm1 | 47 +++++ 2 files changed, 447 insertions(+) create mode 100644 py/Wrapper/PoC.psm1 create mode 100644 py/Wrapper/PowerShell.psm1 diff --git a/py/Wrapper/PoC.psm1 b/py/Wrapper/PoC.psm1 new file mode 100644 index 00000000..039d7cf6 --- /dev/null +++ b/py/Wrapper/PoC.psm1 @@ -0,0 +1,400 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# PowerShell Script: Wrapper Script to execute +# +# Description: +# ------------------------------------ +# This is a PowerShell wrapper script (executable) which: +# - +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +# +# Module parameters +[CmdletBinding()] +param( + [Parameter(Mandatory=$true)][string] $PoC_RootDir +) +# +# ============================================================================== +# find suitable python version for PoC +$PythonVersion_Major, $PythonVersion_Minor = (3, 5) + +$Py_exe = "py.exe" +$Command = "$Py_exe -{0} -c `"import sys; sys.exit(not (0x{0:00}{1:00}0000 < sys.hexversion < 0x04000000))`"" -f ($PythonVersion_Major, $PythonVersion_Minor) +Invoke-Expression $Command | Out-Null +if ($LastExitCode -eq 0) +{ $Python_Interpreter = $Py_exe + $Python_Parameters = (,"-$PythonVersion_Major") +} +else +{ Write-Host "[ERROR]: No suitable Python interpreter found." -ForegroundColor Red + Write-Host "The script requires Python $PythonMinVersion." -ForegroundColor Yellow + return 1 +} + +Export-ModuleMember -Variable "Python_Interpreter" +Export-ModuleMember -Variable "Python_Parameters" + +# ============================================================================== +$PoC_PythonPath = "py" +$PoC_FrontEndPy = "PoC.py" +$PoC_ModulePath = "py\Wrapper" +$PoC_HookPath = "$PoC_ModulePath\Hooks" +$PoC_FrontEnd = "poc.ps1" + +$PoC_PythonDir = "$PoC_RootDir\$PoC_PythonPath" +$PoC_ModuleDir = "$PoC_RootDir\$PoC_ModulePath" +$PoC_HookDir = "$PoC_RootDir\$PoC_HookPath" + +$env:PoCRootDirectory = $PoC_RootDir + +Export-ModuleMember -Variable "PoC_RootDir" +Export-ModuleMember -Variable "PoC_PythonDir" +Export-ModuleMember -Variable "PoC_FrontEndPy" +Export-ModuleMember -Variable "PoC_ModuleDir" +Export-ModuleMember -Variable "PoC_FrontEnd" + +# ============================================================================== +$PoC_Environments = @{ + "Aldec" = @{ + "PreHookFile" = "Aldec.pre.ps1"; + "PostHookFile" = "Aldec.post.ps1"; + "Tools" = @{ + "ActiveHDL" = @{ + "Load" = $false; + "Commands" = @("asim"); + "PSModule" = "Aldec.ActiveHDL.psm1"; + "PreHookFile" = "Aldec.ActiveHDL.pre.ps1"; + "PostHookFile" = "Aldec.ActiveHDL.post.ps1" + # }; + # "RevieraPRO" = @{ + # "Load" = $false; + # "Commands" = @("rpro"); + # "PSModule" = "Aldec.RevieraPRO.psm1"; + # "PreHookFile" = "Aldec.RevieraPRO.pre.ps1"; + # "PostHookFile" = "Aldec.RevieraPRO.post.ps1" + } + }}; + "Altera" = @{ + "PreHookFile" = "Altera.pre.ps1"; + "PostHookFile" = "Altera.post.ps1"; + "Tools" = @{ + "Quartus" = @{ + "Load" = $false; + "Commands" = @("quartus"); + "PSModule" = "Altera.Quartus.psm1"; + "PreHookFile" = "Altera.Quartus.pre.ps1"; + "PostHookFile" = "Altera.Quartus.post.ps1" + } + }}; + "GHDL_GTKWave" = @{ + "PreHookFile" = ""; + "PostHookFile" = ""; + "Tools" = @{ + "GHDL" = @{ + "Load" = $false; + "Commands" = @("ghdl"); + "PSModule" = "GHDL.psm1"; + "PreHookFile" = "GHDL.pre.ps1"; + "PostHookFile" = "GHDL.post.ps1"}; + "GTKWave" = @{ + "Load" = $false; + "Commands" = @("ghdl"); + "PSModule" = "GTKWave.psm1"; + "PreHookFile" = "GTKWave.pre.ps1"; + "PostHookFile" = "GTKWave.post.ps1"} + }}; + "Lattice" = @{ + "PreHookFile" = "Lattice.pre.ps1"; + "PostHookFile" = "Lattice.post.ps1"; + "Tools" = @{ + "Diamond" = @{ + "Load" = $false; + "Commands" = @("lse"); + "PSModule" = "Lattice.Diamond.psm1"; + "PreHookFile" = "Lattice.Diamond.pre.ps1"; + "PostHookFile" = "Lattice.Diamond.post.ps1" + }; + "ActiveHDL" = @{ + "Load" = $false; + "Commands" = @("asim"); + "PSModule" = "Lattice.ActiveHDL.psm1"; + "PreHookFile" = "Lattice.ActiveHDL.pre.ps1"; + "PostHookFile" = "Lattice.ActiveHDL.post.ps1" + } + }}; + "Mentor" = @{ + "PreHookFile" = "Mentor.pre.ps1"; + "PostHookFile" = "Mentor.post.ps1"; + "Tools" = @{ + "PrecisionRTL" = @{ + "Load" = $false; + "Commands" = @("prtl"); + "PSModule" = "Mentor.PrecisionRTL.psm1"; + "PreHookFile" = "Mentor.PrecisionRTL.pre.ps1"; + "PostHookFile" = "Mentor.PrecisionRTL.post.ps1"}; + "QuestaSim" = @{ + "Load" = $false; + "Commands" = @("vsim", "qsim"); + "PSModule" = "Mentor.QuestaSim.psm1"; + "PreHookFile" = "Mentor.QuestaSim.pre.ps1"; + "PostHookFile" = "Mentor.QuestaSim.post.ps1" + } + }}; + "PowerShell" = @{ + "PreHookFile" = ""; + "PostHookFile" = ""; + "Tools" = @{ + "PowerShell" = @{ + "Load" = $false; + "Commands" = @("ps"); + "PSModule" = "PowerShell.psm1"; + "PreHookFile" = "PowerShell.pre.ps1"; + "PostHookFile" = "PowerShell.post.ps1"} + }}; + "Sphinx" = @{ + "PreHookFile" = ""; + "PostHookFile" = ""; + "Tools" = @{ + "Sphinx" = @{ + "Load" = $false; + "Commands" = @("docs"); + "PSModule" = "Sphinx.psm1"; + "PreHookFile" = "Sphinx.pre.ps1"; + "PostHookFile" = "Sphinx.post.ps1"} + }}; + "Xilinx" = @{ + "PreHookFile" = "Xilinx.pre.ps1"; + "PostHookFile" = "Xilinx.post.ps1"; + "Tools" = @{ + "ISE" = @{ + "Load" = $false; + "Commands" = @("ise", "isim", "xst", "coregen"); + "PSModule" = "Xilinx.ISE.psm1"; + "PreHookFile" = "Xilinx.ISE.pre.ps1"; + "PostHookFile" = "Xilinx.ISE.post.ps1" + }; + "Vivado" = @{ + "Load" = $false; + "Commands" = @("xsim", "vivado"); + "PSModule" = "Xilinx.Vivado.psm1"; + "PreHookFile" = "Xilinx.Vivado.pre.ps1"; + "PostHookFile" = "Xilinx.Vivado.post.ps1" + }; + } # Tools + } # Xilinx +} + +function Get-PoCEnvironmentArray +{ <# + .SYNOPSIS + undocumented + .DESCRIPTION + undocumented + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)] $Values + ) + + # set default values + $Debug = $false + $PoCEnv = $PoC_Environments + + # search parameters for specific options like '-D' to enable batch script debug mode + # TODO: restrict to first n=2? parameters + foreach ($param in $Values) + { if (-not $Debug -and ($param -cmatch "^-\w*D\w*")) + { $Debug = $true; continue } + + $breakIt = $false + foreach ($VendorName in $PoCEnv.Keys) + { foreach ($ToolName in $PoCEnv[$VendorName]['Tools'].Keys) + { foreach ($Command in $PoCEnv[$VendorName]['Tools'][$ToolName]['Commands']) + { if ($param -ceq $Command) + { $PoCEnv[$VendorName]['Tools'][$ToolName]['Load'] = $true + return $Debug, $PoCEnv + } + } # Command + } # ToolName + } # VendorName + } # param + return $Debug, $PoCEnv +} + +# TODO: build an overload of Get-PoCEnvironmentArray +function Set-PoCEnvironmentArray +{ <# + .SYNOPSIS + undocumented + .DESCRIPTION + undocumented + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)] $Value + ) + # copy the array and set load to true + $PoCEnv = $PoC_Environments + $VendorName, $ToolName = $Value.Split(".") + $PoCEnv[$VendorName]['Tools'][$ToolName]['Load'] = $true + return $PoCEnv +} + +Export-ModuleMember -Function "Get-PoCEnvironmentArray" +Export-ModuleMember -Function "Set-PoCEnvironmentArray" + +# ============================================================================== +function Invoke-OpenEnvironment +{ <# + .SYNOPSIS + undocumented + .DESCRIPTION + undocumented + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)] $LoadEnv + ) + $Debug = $false # $true + + # execute vendor and tool pre-hook files if present + foreach ($VendorName in $LoadEnv.Keys) + { foreach ($ToolName in $LoadEnv[$VendorName]['Tools'].Keys) + { if ($LoadEnv[$VendorName]['Tools'][$ToolName]['Load']) + { if ($Debug -eq $true) { Write-Host "Loading $VendorName.$ToolName environment..." -ForegroundColor Yellow } + + # if exists, source the vendor pre-hook file + $VendorPreHookFile = "$PoC_HookDir\$($LoadEnv[$VendorName]['PreHookFile'])" + if (Test-Path $VendorPreHookFile -PathType Leaf) + { if ($Debug -eq $true) { Write-Host " Loading Vendor pre-hook file: $VendorPreHookFile" -ForegroundColor Yellow } + . ($VendorPreHookFile) + } + + # if exists, source the tool pre-hook file + $ToolPreHookFile = "$PoC_HookDir\$($LoadEnv[$VendorName]['Tools'][$ToolName]['PreHookFile'])" + if (Test-Path $ToolPreHookFile -PathType Leaf) + { if ($Debug -eq $true) { Write-Host " Loading Tool pre-hook file: $ToolPreHookFile" -ForegroundColor Yellow } + . ($ToolPreHookFile) + } + + $ModuleFile = "$PoC_ModuleDir\$($LoadEnv[$VendorName]['Tools'][$ToolName]['PSModule'])" + if (Test-Path $ModuleFile -PathType Leaf) + { $ModuleName = (Get-Item $ModuleFile).BaseName + # unload module if still loaded + if (Get-Module $ModuleName) + { if ($Debug -eq $true) { Write-Host " Unloading module: $ModuleName" -ForegroundColor Yellow } + Remove-Module $ModuleName + } + + # load module + if ($Debug -eq $true) { Write-Host " Loading module: $ModuleFile" -ForegroundColor Yellow } + Import-Module $ModuleFile -ArgumentList @($Python_Interpreter, $Python_Parameters, $PoC_FrontEndPy) + # invoke Open-Environment hook + return Open-Environment + } + elseif ($Debug -eq $true) + { Write-Host "[ERROR]: Module '$ModuleFile' not found." -ForegroundColor Red + return 0 + } + } + } + } + return 1 +} + +function Invoke-CloseEnvironment +{ <# + .SYNOPSIS + undocumented + .DESCRIPTION + undocumented + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)] $LoadEnv + ) + $Debug = $false # $true + + # execute vendor and tool post-hook files if present + foreach ($VendorName in $LoadEnv.Keys) + { foreach ($ToolName in $LoadEnv[$VendorName]['Tools'].Keys) + { if ($LoadEnv[$VendorName]['Tools'][$ToolName]['Load']) + { # if exists, source the tool pre-hook file + $ToolPostHookFile = "$PoC_HookDir\$($LoadEnv[$VendorName]['Tools'][$ToolName]['PostHookFile'])" + if (Test-Path $ToolPostHookFile -PathType Leaf) + { . ($ToolPostHookFile) } + + # if exists, source the vendor pre-hook file + $VendorPostHookFile = "$PoC_HookDir\$($LoadEnv[$VendorName]['PostHookFile'])" + if (Test-Path $VendorPostHookFile -PathType Leaf) + { . ($VendorPostHookFile) } + + $ModuleFile = "$PoC_ModuleDir\$($LoadEnv[$VendorName]['Tools'][$ToolName]['PSModule'])" + if (Test-Path $ModuleFile -PathType Leaf) + { $ModuleName = (Get-Item $ModuleFile).BaseName + if (Get-Module $ModuleName) + { $PyWrapper_ExitCode = Close-Environment + Remove-Module $ModuleName + } + } + } + } + } +} + +Export-ModuleMember -Function "Invoke-OpenEnvironment" +Export-ModuleMember -Function "Invoke-CloseEnvironment" + +function PoCQuery +{ <# + .SYNOPSIS + PoC front-end function + .DESCRIPTION + undocumented + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)][string] $Query + ) + return Invoke-Expression "$Python_Interpreter $Python_Parameters $PoC_PythonDir\$PoC_FrontEndPy query $Query" +} + +Export-ModuleMember -Function "PoCQuery" + +function poc +{ <# + .SYNOPSIS + PoC front-end function + .DESCRIPTION + undocumented + #> + # $env:PoCRootDirectory = $PoC_RootDir + + $Expr = "$Python_Interpreter $Python_Parameters $PoC_FrontEndPy $args" + Invoke-Expression $Expr + return $LastExitCode +} + +Export-ModuleMember -Function "poc" diff --git a/py/Wrapper/PowerShell.psm1 b/py/Wrapper/PowerShell.psm1 new file mode 100644 index 00000000..7e1e7351 --- /dev/null +++ b/py/Wrapper/PowerShell.psm1 @@ -0,0 +1,47 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# PowerShell Module: +# +# Description: +# ------------------------------------ +# TODO: +# - +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +# +function Open-Environment +{ $Debug = $false + + Write-Host "Loading module PoC..." + Import-Module "${env:PoCRootDirectory}\py\Wrapper\PoC.psm1" -Scope Global -ArgumentList @($Py_Interpreter, $Py_Parameters, $PoC_Query) + + return 1 +} + +function Close-Environment +{ return 0 +} + +Export-ModuleMember -Function 'Open-Environment' +Export-ModuleMember -Function 'Close-Environment' From 5b5539426f8bfd48ca6a9fa45cc0e142ac22eafa Mon Sep 17 00:00:00 2001 From: Martin Zabel Date: Tue, 8 Nov 2016 11:13:10 +0100 Subject: [PATCH 16/97] Moved mem2mig adapter for Spartan6 to mem/ddr2. --- src/mem/README.md | 1 + src/mem/ddr2/README.md | 6 ++++++ .../ddr2_mem2mig_adapter_Spartan6.vhdl} | 6 +++--- src/mem/ddr3/README.md | 2 +- 4 files changed, 11 insertions(+), 4 deletions(-) create mode 100644 src/mem/ddr2/README.md rename src/mem/{ddr3/ddr3_mem2mig_adapter_Spartan6.vhdl => ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl} (97%) diff --git a/src/mem/README.md b/src/mem/README.md index 95be40f6..7a2f75f1 100644 --- a/src/mem/README.md +++ b/src/mem/README.md @@ -7,6 +7,7 @@ implementations. ## Sub-Namespace(s) - [`PoC.mem.ddr3`][mem_ddr3] - Adapter and Wrapper for DDR3 controllers + - [`PoC.mem.ddr2`][mem_ddr2] - Adapter and Wrapper for DDR3 controllers - [`PoC.mem.is61lv`][mem_is61lv] - ISSI - IS61LV SRAM controller - [`PoC.mem.is61nlp`][mem_is61nlp] - ISSI - IS61NLP SRAM controller - [`PoC.mem.lut`][mem_lut] - Lookup-Table (LUT) implementations diff --git a/src/mem/ddr2/README.md b/src/mem/ddr2/README.md new file mode 100644 index 00000000..ee50faf8 --- /dev/null +++ b/src/mem/ddr2/README.md @@ -0,0 +1,6 @@ +# Namespace `PoC.mem.ddr2` + +The namespace `PoC.mem.ddr2` is designated for own implementations of +DDR2 memory controllers as well as for adapters for vendor-specific +implementations. At the top-level, all controllers and adapters +provide the same simple memory interface to the user application. diff --git a/src/mem/ddr3/ddr3_mem2mig_adapter_Spartan6.vhdl b/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl similarity index 97% rename from src/mem/ddr3/ddr3_mem2mig_adapter_Spartan6.vhdl rename to src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl index a0a2b4bf..881c30bc 100644 --- a/src/mem/ddr3/ddr3_mem2mig_adapter_Spartan6.vhdl +++ b/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl @@ -58,7 +58,7 @@ use ieee.numeric_std.all; library poc; use poc.utils.all; -entity ddr3_mem2mig_adapter_Spartan6 is +entity ddr2_mem2mig_adapter_Spartan6 is generic ( D_BITS : positive; @@ -92,9 +92,9 @@ entity ddr3_mem2mig_adapter_Spartan6 is mig_rd_en : out std_logic ); -end entity ddr3_mem2mig_adapter_Spartan6; +end entity ddr2_mem2mig_adapter_Spartan6; -architecture rtl of ddr3_mem2mig_adapter_Spartan6 is +architecture rtl of ddr2_mem2mig_adapter_Spartan6 is -- The number of bits addressing the byte within the MIG address. constant BYTE_ADDR_BITS : positive := log2ceil(D_BITS/8); diff --git a/src/mem/ddr3/README.md b/src/mem/ddr3/README.md index c03a1291..7457cfb2 100644 --- a/src/mem/ddr3/README.md +++ b/src/mem/ddr3/README.md @@ -1,4 +1,4 @@ -# Namespace `PoC.mem.ddr3 +# Namespace `PoC.mem.ddr3` The namespace `PoC.mem.ddr3` is designated for own implementations of DDR3 memory controllers as well as for adapters for vendor-specific From f0bd8df190ce2acfbf68188db6c8adf7e49d6803 Mon Sep 17 00:00:00 2001 From: Martin Zabel Date: Tue, 8 Nov 2016 12:30:17 +0100 Subject: [PATCH 17/97] Updated documentation. --- .../ddr2_mem2mig_adapter_Spartan6.rst} | 6 +++--- docs/PoC/mem/ddr2/index.rst | 21 +++++++++++++++++++ docs/PoC/mem/ddr3/index.rst | 4 ---- docs/PoC/mem/index.rst | 2 ++ 4 files changed, 26 insertions(+), 7 deletions(-) rename docs/PoC/mem/{ddr3/ddr3_mem2mig_adapter_Spartan6.rst => ddr2/ddr2_mem2mig_adapter_Spartan6.rst} (84%) create mode 100644 docs/PoC/mem/ddr2/index.rst diff --git a/docs/PoC/mem/ddr3/ddr3_mem2mig_adapter_Spartan6.rst b/docs/PoC/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst similarity index 84% rename from docs/PoC/mem/ddr3/ddr3_mem2mig_adapter_Spartan6.rst rename to docs/PoC/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst index a0d9f221..ff96714a 100644 --- a/docs/PoC/mem/ddr3/ddr3_mem2mig_adapter_Spartan6.rst +++ b/docs/PoC/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst @@ -1,5 +1,5 @@ -ddr3_mem2mig_adapter_Spartan6 +ddr2_mem2mig_adapter_Spartan6 ############################# Adapter between the :doc:`PoC.Mem ` @@ -30,13 +30,13 @@ Containts only combinational logic. .. rubric:: Entity Declaration: -.. literalinclude:: ../../../../src/mem/ddr3/ddr3_mem2mig_adapter_Spartan6.vhdl +.. literalinclude:: ../../../../src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl :language: vhdl :tab-width: 2 :linenos: :lines: 61-95 -Source file: `mem/ddr3/ddr3_mem2mig_adapter_Spartan6.vhdl `_ +Source file: `mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl `_ diff --git a/docs/PoC/mem/ddr2/index.rst b/docs/PoC/mem/ddr2/index.rst new file mode 100644 index 00000000..6b9ea515 --- /dev/null +++ b/docs/PoC/mem/ddr2/index.rst @@ -0,0 +1,21 @@ +ddr2 +==== + +The namespace `PoC.mem.ddr2` is designated for own implementations of +DDR2 memory controllers as well as for adapters for vendor-specific +implementations. At the top-level, all controllers and adapters +provide the same simple memory interface to the user application. + +.. **Package** + +**Entities** + + * :doc:`PoC.mem.ddr2.mem2mig_adapter_Spartan6 + ` - Adapter for the Xilinx MIG core + for Spartan-6 FPGAs + + +.. toctree:: + :hidden: + + ddr2_mem2mig_adapter_Spartan6 diff --git a/docs/PoC/mem/ddr3/index.rst b/docs/PoC/mem/ddr3/index.rst index cad695f0..3477c198 100644 --- a/docs/PoC/mem/ddr3/index.rst +++ b/docs/PoC/mem/ddr3/index.rst @@ -13,13 +13,9 @@ provide the same simple memory interface to the user application. * :doc:`PoC.mem.ddr3.mem2mig_adapter_Series7 ` - Adapter for the Xilinx MIG core for 7-Series FPGAs - * :doc:`PoC.mem.ddr3.mem2mig_adapter_Spartan6 - ` - Adapter for the Xilinx MIG core - for Spartan-6 FPGAs .. toctree:: :hidden: ddr3_mem2mig_adapter_Series7 - ddr3_mem2mig_adapter_Spartan6 diff --git a/docs/PoC/mem/index.rst b/docs/PoC/mem/index.rst index 7ac07d59..0bda8857 100644 --- a/docs/PoC/mem/index.rst +++ b/docs/PoC/mem/index.rst @@ -9,6 +9,7 @@ implementations. **Sub-Namespaces** * :doc:`PoC.mem.ddr3 ` - DDR3 memory controllers + * :doc:`PoC.mem.ddr2 ` - DDR2 memory controllers * :doc:`PoC.mem.is61lv ` - ISSI - IS61LV SRAM controller * :doc:`PoC.mem.is61nlp ` - ISSI - IS61NLP SRAM controller * :doc:`PoC.mem.lut ` - Lookup-Table (LUT) implementations @@ -25,6 +26,7 @@ implementations. :hidden: ddr3/index + ddr2/index is61lv/index is61nlp/index lut/index From ccd8fa323a056fa41dc525aa0235eb528b5148ee Mon Sep 17 00:00:00 2001 From: Martin Zabel Date: Tue, 8 Nov 2016 17:12:36 +0100 Subject: [PATCH 18/97] Fixed detection of installed Git. Updated documentation. --- docs/PoC/misc/sync/sync_Strobe.rst | 5 +- docs/PoC/sort/sortnet/sortnet_BitonicSort.rst | 5 +- .../sync/sync_Strobe.png} | Bin .../sync/sync_Strobe.svg} | 0 .../sort/sortnet/sortnet_BitonicSort.png | Bin 0 -> 44826 bytes .../sort/sortnet/sortnet_BitonicSort.svg | 1502 +++++++++++++++++ py/PoC.py | 2 + py/ToolChains/GHDL.py | 2 +- py/ToolChains/Git.py | 122 +- py/ToolChains/PoC.py | 50 +- py/ToolChains/__init__.py | 2 +- sim/mem/lut/lut_Sine_tb.wdo | 26 + src/misc/sync/sync_Strobe.vhdl | 3 + src/sort/sortnet/sortnet_BitonicSort.vhdl | 3 + 14 files changed, 1683 insertions(+), 39 deletions(-) rename docs/_static/{images/sync_strobe.png => misc/sync/sync_Strobe.png} (100%) rename docs/_static/{images/sync_strobe.svg => misc/sync/sync_Strobe.svg} (100%) create mode 100644 docs/_static/sort/sortnet/sortnet_BitonicSort.png create mode 100644 docs/_static/sort/sortnet/sortnet_BitonicSort.svg create mode 100644 sim/mem/lut/lut_Sine_tb.wdo diff --git a/docs/PoC/misc/sync/sync_Strobe.rst b/docs/PoC/misc/sync/sync_Strobe.rst index 84e566a8..a59b2d2a 100644 --- a/docs/PoC/misc/sync/sync_Strobe.rst +++ b/docs/PoC/misc/sync/sync_Strobe.rst @@ -12,6 +12,9 @@ suppressed by a rising edge detection. .. ATTENTION:: Use this synchronizer only for one-cycle high-active signals (strobes). +.. image:: ../../../_static/misc/sync/sync_Strobe.svg + :target: ../../../_static/misc/sync/sync_Strobe.svg + Constraints: This module uses sub modules which need to be constrained. Please attend to the notes of the instantiated sub modules. @@ -24,7 +27,7 @@ Constraints: :language: vhdl :tab-width: 2 :linenos: - :lines: 51-63 + :lines: 54-66 Source file: `misc/sync/sync_Strobe.vhdl `_ diff --git a/docs/PoC/sort/sortnet/sortnet_BitonicSort.rst b/docs/PoC/sort/sortnet/sortnet_BitonicSort.rst index 01d04f8e..9addb1d6 100644 --- a/docs/PoC/sort/sortnet/sortnet_BitonicSort.rst +++ b/docs/PoC/sort/sortnet/sortnet_BitonicSort.rst @@ -4,6 +4,9 @@ sortnet_BitonicSort This sorting network uses the *bitonic sort* algorithm. +.. image:: ../../../_static/sort/sortnet/sortnet_BitonicSort.svg + :target: ../../../_static/sort/sortnet/sortnet_BitonicSort.svg + .. rubric:: Entity Declaration: @@ -12,7 +15,7 @@ This sorting network uses the *bitonic sort* algorithm. :language: vhdl :tab-width: 2 :linenos: - :lines: 43-69 + :lines: 46-72 Source file: `sort/sortnet/sortnet_BitonicSort.vhdl `_ diff --git a/docs/_static/images/sync_strobe.png b/docs/_static/misc/sync/sync_Strobe.png similarity index 100% rename from docs/_static/images/sync_strobe.png rename to docs/_static/misc/sync/sync_Strobe.png diff --git a/docs/_static/images/sync_strobe.svg b/docs/_static/misc/sync/sync_Strobe.svg similarity index 100% rename from docs/_static/images/sync_strobe.svg rename to docs/_static/misc/sync/sync_Strobe.svg diff --git a/docs/_static/sort/sortnet/sortnet_BitonicSort.png b/docs/_static/sort/sortnet/sortnet_BitonicSort.png new file mode 100644 index 0000000000000000000000000000000000000000..b87e5d8ebc99e8bf3e2394249420ab3acccf9b31 GIT binary patch literal 44826 zcmbrl1yCGO+qQ`W5}csHLvRo75(w@DcXxM(1b270;O_2BaCdii9dw)b{r<0Nw`!}l zY73dEshRGcneKD$=X$OaA}1q?1dj_30Re#|F7{Ia0s{IgaR2rbEbza`BE}53fz_83 z{R#2*{*&Ea7zY9I6+-;y4@KAXlT{O4MWv;#%eNaTahnffpCI$^ze$()!sHvA!&Lj` z{vq(FtU4;yU#$-d)xuE3()<8<*iKGN+%9Ev|ALD4Nq7%Yk324Y9XtJ)hjYBnKsb?*(n6ctwLAFbl`w}|_R)kop~Ud<<}fR$qzzlgv$|cq zoR3CvS6qRkNU@}Ux=?lTjL-&i6J;k=GU5}@tdCMUwiU-viDvY?Sn-c}|I zBXgD(3e0|XW$#x7q1`H_WDH?9m?koe-O&v0#^zi~qA%fCh3e&ZLAg@mvH4;fz%zIV zWoa)gi-wUUVSW}UEHB^T8rSqur1i*qXO|TOSUy>Zo7#MsJ&MJ$@~9J&vC*nrPaEhu zt*iDvobT)JFBVezE0Jf?PT*yljDur^Xs+CrcB|FfBezC?Ty;~O4~t~ zYj5qr>*pvg58k>EeYe@Vb1Q~+mj%8~X352#mmwT{ zob?Ih&Vbe1Zx|hEdljrmab-i`_u^kU{9x5T)xY982$pJfWTAO&C0#k3!8y(GNrQfr z!&FyQEehp~_FFW^4!s8RJn)>UgZ9Qf5_M2kc}|x)0)|4FDpI+&lT{;RqD1o0smGP& z1@-iD;Qyh)^T2??VA%Fu2*N&lB@BMTB$AE&w|adX23|XUh~-90-Tk=;o;M$&Y=u() zA*94HUBLo0n&I>NO($*(f~Tvvd+@VgBjiG}6T0xn>lC+j15jT{Jy)H2b!8LCsIaLi z83qB%5Gp~i`^V7eAY)#b2qq>42E`+I|73X>{eCrY{TzCuo7;LLV4k0pkxH#-MJ#9T zVB)Ax){Za=p?@Fg0gST77@@`808wRdEb`39kVm2EFX8mK?9QT2pzeiQIl0?+em%?M z%t^4~y&9mX91nT%z}tw1P9VLEtQ8qDi`VZ1Vk=FUno@v9Wk|O~Rj$y)SuXxXK}|C> zXj%#>UhZ=;UR+J_(H~UDFMv+vpH{%!SuMY$&&+yhJ8~5xM zubKlED0N%ASsL}9sJ717 z-LKZB!NFwyp~&*yYrJ98Y9(d0pu$LMv_L=l<8>2^Tn5|bI;w8%v0I-C8jXtszYc=@ zHJJS_HPpyL%3EV5NVO>GJ(kr+$UYw6TUBu0EzPfA9QD|k6QUf>CAc-NY0}WoAL^%J zFWnK4DP}I4nM@P$UtEv#o6xJ(*`X9dha8$3`zx0f@5UprT@Pq&jY`bmk{Q ziE?EKMQY5q4ih#ljoGtL$a^j)Rm%&FPDqQ~>^>LIz|m61TSf;W;!HVCWdC?OojAwe z)V{Ey!Jed&5RK)lYBJ$_^{;$WmA`g-U=hF z$EF3F=-CPef~3+Cn=49Fo3N+5TV~q)48ESeWa?7 zqYiSV(6yb9ocEbhcz2f-w6|uD&O2sGl3rV6Sr}%S5Sgg;5w4%}G~q<`8jmCn*#&tY zGs$*vTXySG`L^%4UY)P)jW3mShLEhfsVN*Q}L1&#O3eGz_HRj9Cu+C?FtJpdpd^wM7=Z#pXsS%BH4f+D>i#!RX$m5{m z=ZwbQ`t++GXcJ90HEC$ESd`JL_qwbFDAHM@+rb~*%(}5zLZbFxTF<|Y>BEs5=@~bo zNY*`AuxQY#rq}CikBFl$#wCrT(5Or@*1|AIrMZuI$mLAxUs3k#Hs5kdk)va4yXq~* zl1UE9651W?kcisea^?vt6uTTbCM#NR&L3R6n``GC z%E6EVn{012v0Fr!mDg*$-jZf#DjKdP*y(G~aY{_7QccF-l ziTxr6^I>ECeq?J3l$D!b6U(WhIneYQ`j5C;^7v+7@f1R*NKk!xtXGI(KIts}u$cJf zD7W=?%f9x{a)ryi4Cce>vv33bI7RiTR5sB%y>;~}jgTql!H>!aFmu0yv;3_YaVU4+L`N{hMqQ@(728 zPLWnPoNG~Pnl?jCrJ!JLvY6EjksK!^j2!|UPLw;*O#M>uEg68P`i_+sV+Z{R{oUw5 zR}CBu#g=P=0>Nc$%(gHjTI4h`lCN<*Coub>mybKw&Mo5id#6b?(D@km%<)L7PelL% zpZV6`AMZT^mbQw^ zKBBDG1`N3ek9~RwWvkV|-rWJy3Fb17`wQ|fkZqsWm@dHQZ~dpYGoG(_&gYx0m_E4* z#T@;& zKl+@n^zV5+L0q`D$1hv5?r)E&(G7C2$TBDhuTj_sE9Y(Q&z7pS8C#83t02>XxSVdl zHBe~2Vp-g^&igX2FV_sLQT(sB?0mo<{lR+F_1Fpezz8W7Q@{EM&&^t=MMPTW-IOLU zy7BYe{`|rWWKDQ&Mbxyqz%-fC%}lV(JneY8ie^t;(w;ucf!f_wnBLggjPMO=*&%wQ z*8IAD_|^b|NDwg|)r>VR_g=Eo6stLFqiibb-*D2y@8#rIGL=+zcABo~v-)G)wI~GY zhW^APK+qc~HZUd^YIWk?djKxCSbU0(GEXmbH%kov@>^vB?}ocW61=u*lg;(|`4b#A1<|albi;UzizyW^gOAm5Y-(#jXERh{s}> zGn3C*n>K#QOXd=>>|K1MW;*AI`fjlGkov}kgShhjvF*DtdP?L<9plsrkF%vT3^2$$ zEPr1AC?4C#DlKJrwb9$!7)3CV#WqUfkoEOF49~SYSpY+x;&l@-YmKNUOulSugX74^ zhmD~a5~wveb$D%WaVlA#XSnyjW?^ByQLQz2v$0i)+y!U& zd*?sVwDd^v3=}LRM7oLbnEAv12%KB&w#qMXpS@fTGNHQ2N21cxS9QNxC z=P))u4;C&~d7wb(yt;7e@Gu3P1v#fB{JB1p4RgK7xHl&}=XQ-=?&Ub4A|VU7g#MU4 zTV%GFFTQYPN~>(WIuIX3)bCTY1@0V8OYzws`EEis>*AagCXT|Z;K2L(81+{D05&mA zjK|m;`L?|M299R$d?NI9@qP}$wrPn8@f+h3pE;Z^)Y5pYvlv#>;$klnxjS-_NP;8~ zR4SS@4WBl3qE3(~gC01)POmbW*uT!9DY zXgx~AM1Zb|HuF6PIuW@r6E-eKynZOvqzwHdQ6Ol8@w7=D`e#`$FF)U~GMCajXX9&s zUtd11v~jHnMT36O`0f z>HPK#hHg4h4#$mlN$q*4z*VpeddX%$;xyHq` z{&nuZ~AVl%@Aw-QT%%_V9*M zo87n`zMSi#D>f7!I0$iBaq=;=h4U=|dB%QB%=$=Ri2X??SD|=crp<5e_qm+!;uy~t zWF)$4XMm;}+;e_kYj)0;D^1Rn_F*p0#(`roBT400wKks=O&_W?Gsthbazha#msUTn z2(yzYs6Je^94iL%&V}e-@1ElnXQ@#aqsHAS$m8JoBdQfkYzmgEQ26pWC;-<_&9W$d z>wdE;F^_93WN6npXZlbsYokN$2k{U-i6@`)67}=0QGuJ0kr7z%cj2D*2IxrY{DYwL zN4wiu6`!=ph9F{U^%H~xCvH1#f*%RRQB1kBVWUpA%8AuJ%eeQYl^tAUMS_0c-G+oK zS;x)Sx!8m)N1W`==x4~lb*wP2xcAr?_V;Pmhs!y<^Xbgg*~wlX5t>Y1HR>Z*+3a}K z%*-H@S_jN28r<-5(W72|Jhf?`upQfNKWn4V7xHe{N9NBSPagKOmE5>%o~&PC>j1U8 z5OB2Jn6#!lMe>b>CiTZj6Zrvhn!!$<jR z4$X>GgYA#V*)~sig1dnV1@j=bptup47k>knN*x)BFtr1bty3az{n-Yq6_&d{zBG5& zoo~NqmtAIftXInx?Nq?rF-(<7tMm*w1bsWGUeU9de|EVZj` zH+#T60kFh$baZAr|6(eQosYt}y5RNdU(!@!jV912CRA%2UtsyvuV_r}Pkv-ISV4z^ z&1Q8x>z|`iL6agR>`?^2Y@GS-9z7S*$7~Bf+b^He=fYky+JVe*C!NNTlYlPM0nGcHeHy>wv?BygV$8~^=IEO_OF`;7po)b zCyiO4I>S`3y!}QG5g&NVL&2#he|l0ury6y-J!;TUkqq`8l!|8JR#a;h=XENA-$`th zP>s+kUH8sckCxjFj)#nf6JNgkEbd-{3kuRL|D@MlXEDDv-=M<3N#s3FzQz|=0y9y{G1ShsT)EF9Mvw8r?m(bsx43rRp-P_SHF=FL#ogp!tFyMG)j z8-kfUd_OdX#NXa2Q8{|1fg;2#MbIv1&v{AJ=3=VRX1(&SOoqDmRq!u%*MHH2#fK&n zWzs4+O+6#_B6>U(`yxQXB z3#Z+RdIe7x2>u2JGi-qr1L%23&jYuGN1_yMNettszhj4O``|CjC1Ktx}C8uQtM`& z*KOrm<|l&-r?VJ@lMRa1az;xe-vt%Z!l|wONwmJ=!N0*aNT?X@- zN|iK3n;X|*QF9iV=_9K_?m5OXnUpFS=7v(R(6X8?NDy%!QDPHNsC0qbT!;lXA91d}GkbYO?RuFXPL&GHv!V0*BodV648-LW{tnh%hjc)w{N#p;!{2F9TejyWVY11jjRf~0!}j`WLXRv4vudL z%IJoq%q}mJ{38r2eXa@4pC5jWZZjm&?GGCbo5iAz`{;NxW_Rj2v;;GT&{@!kBPI0i z>i22Y+BG4od=nY%!1n!E*%W>}#?7u-48*S=H-DZC#6d%J)W$O>9_FWb?6!}m5N&p# z)AZ?9l`fxQ$||T#QgYgL$9i?6^NIQZD&po>>qKZd1=Ybf?`8bh7a~EkB^ZMT-Al9; zQR$i%qZL&|$Qy65SVaweDa51|PJBFZXEG43Q(d^QK(hOki34A&ejRZLhA66Uj{eLa?ViSu^ybqH5U{mI{I zgGf$irf#WZpk|0gPUF*iW~3P!O=pp>U{ZHOnPD%{|j6_Eg?0h1G-P#Xq$kj+JgJWHe!$qCAN`vTJTE3exE4oaZBa z5I}{*Wb|+2y9q{HTlx#_^NrWsb2IHq@y~p@hNjBp`ZN@8wUNm5mFNT<2~p(}8+>Li z{U8?V(4MPxtjp6sD3o;c@Ge|a{1=a&v}#Z6!)%s)l^;4A<7OV7tIf~>x|6Vy8wkeB zVzl!d^%+mcZ*C_dj7rn-c?=}N@(vwU#{sIQ@buG};8m~70MEC531cl5;imh%j)ev@ z0(LEDNEwsaO!D~^Pwe?MdzIwc*vNf99V~})jq_|uc=d?DMw8X<=nAdg4CM@oh^YP8 z&0f_uW2B@g4sL)*p2jS)*B+#eLk3HV?PS1&iJMKajHro=Uc0tSc|XX{oh-n0O;~HW zncQg=k=%$#!eTV2+66Jb{h$PpRXlT{cd;w}bqdAE{r*o_`$3I*5 z;HH-)sxqzHj}SO?8rOIG{01y3z3Gd^rF@dSAN^0#=F2r2;l!z`aoc~K{GGRU*{o{~ zu&55rMKzi-V8Zd=TA^nUhS}}te0zOD0Jz3PwE^g}T}ZJVY@9IVn7mrxkQs?K#a-sv z5U+spG|T4w4KVELv3&V5Q&201FYtTWkB^JcPyXcNjvc4%BFzt{rfuu-vkVMEb!`-Z zyvd1L7b5dfS$T{)cWC*&uB0{Si>J1DOhVo5fe0P9_O)osu%*A!Y2G+$R;e2LasFHQ zbM`z5WchIPn-7~?WTc>eMxf};Xqb%g3fX&n~!7Ka1EilEWyztMNbaC1HrGcu!?qZ+g>8#6B| zs4khq0Rv+p4jF3iD(u*}JbLx^s(tLHrdDn?S#!6pi~%F5$%I?J;8Iaj=G%7SmDXsv zh!#sPS-WU?xKw{kCN5no2Zzi~JGd+qtL!KLm40Eodc=J9iC<;vuN$*_qZOW?y+bL4pwC)0mw6f~_F4ygtOcgq)Q0_wS)nY=e3Qb|ca^(T6?#}~6~?HlyVy6Mr2 zu64#IBve_NonG7B6SkYq@w^c^$#Dp;V($2ZQWwY%J3NvE-uqr&sB5<&Z@taI)_ z5HG{fFfw+pm$`)wn4+bnr_@%WmJbQ#Hs3{*Zrxws|CM$;_k2#<)K80`%!}Nk>+A4E zZpG^_yo7EIfRg>8ub)dpRZjKyz%{37NFnb64&^HeneYL4cE+65y_~Jcwg0dudErAI zr!r+l8wW~|2=Qw$-Wpn7ObjPz(HNq3QzwCoo=(rzOu<|UPp(5OE>vq#rnjmnQe-pUr!WrXSZ8+ z+yOLSrw%cTd!>%JEsTV_#_QF}i}0O?cz?5hTFQ{gE>S66F-9L6-M!4F43%4%Y&Z1o z+%N)HyDxCja@7Qb=xi{e(X^hY59euH=48*Nn=#TUy_WkBDuC z!%H8Dkgqc6Dwij>K8WVCbL)2UKIgC`mC8J!wc6pWyq;6`Y#3{uN<2o<(C{$2FD-Bl z8~pASs?vtn>kh|bKb!Lw;yU=5w5bJtQl6?a<|1^m)2TB3oaKFu#4wsEoVBee$hNy1 zvtK`HV#}R#g-q9btk&i_xC#^&x>o_%5mGkObgZ0OWlmpRKwK?mOXGBoH@!ak4`J8vw=Wiy{AW{Q6e2mJAKT*Oo{Eclx>S)qnkog*Hw$X&eB z{=3^wpVy?)>jep5>H+*9t3}QepxjQ0BS*7>x2zoVCRlbjt!3D_bg%vr(Z;l`3{W!o z1iWzl#-LqHTIC>!(Na!=P#98np5%ho7W=5czd*LSPX5Di!* z#+V0~i*frUd1&qgDe>?7vrOSsT}hwsGPmwL0weA(((fD$V(e%o<^HUrbncrV#5zXeM9cnn z+Dm<;(`A*nqYBEgH`{@599g*kLeI1NC%1>$d5ET`0PLRh2n_SlSTr~AUddDPuxPrM z)UHqof1u;(P#uB@^u@`{v7iDtnDo{R>hcC|`(Qo?8X^n7@QQdAg{wSKmaqvWuUkMw z0^VlTDX7d-46@nwK$kq771fvhyor|-h@~9kQtg?EX42nAdw9MK$w5S+NU4&=F!70E#)Di)>Aq_6>zwq;mj!%~bA8aSTN8|81Vt7s z^$6H<5kIP-uM}C5f+gdim=<*%%A(oZZT136c-;DyA1?zWEl|0X@Z;?-GUW!c9bn_+ z8Z%Am(_0h22eCAg3DgBGptk#(VSL4m9J!2Ma~K~>nqju+{5d@c4enbD)YUbS zPnFsJm^w(gOam0l|AzQWM1kWUUcp3MLPucbBeQbxw@0SW_ViKQD^y~!GZ6hORijxX zk3&}{^6f;knVJ0jeJNtMzfVLGasNCz$5emWoe&W(IhV3mEyd9L=4=aa70r*{4TGihxycqFo?UIUFP?E`CbD#TF`Zj_Y^l>6`MTVo;$I| z(d#@t;;p@IipFklJzN%pCWqle6vy4X_{c}xcEwKV{*Mcg92+{6%Bye&oF(Dz&_G3S zwPZCdlsZ1Z>%sZ9_9Tx1bDPu7z@_5>4dJ5AkwPOH`N@nA$ebdjAqRIm?m2Z+L;jp7 zo0pG3LA7M}JXDzZqi~j~#D#&d>3J%8?|QqWvuP7t@}!wiV(#$!==w5@ef8hspC^}D z_RmidO2vwO!lLNd1QB4lFg;%NpMQVgvRCo571kQ_S|x#cU;jV>$1kW2hG=qn=I~8@ zfls$)-(|x~iuyuNL!|I?!ki`ibUo_@1}0vu90K52wVm0%gMLDtxf+FuDTt@a^_=-{ z6R2hOX-FB$!#mx6f|*gItXSThWvnM#d31PDhr%&@$wB|z-%5O(=ptPFL@;PG!naE_K23lsTEHfXh zR~wWYn8CqmGI^@1Ud80=YP#QjkJY!Z;aLQ5f1ne}IE?Y5za0p_)$HU8XP;243`yFr zF{3h+|3Ku;mHk`Z+P~jWC8!fZ(?Hs`BbVIdvgW9zdaS|l!5CaBk+|ZXH=CnpW0vcY zwK7%EUX=J=wJcse9Guvs{&lIr1pR6@KM!wLIE)?34FDSb<*#M7Xxbd&$x88_U7Wuw zJ-3JJ!c`2wx)Wv|T%NPW-6o z>c!_w@UQd`%f=L_6x)o6(wI}(4NMy=^hQkv{Cgb^tqIu^DSu~l75v-0bf+q>3*<(k z>Tzw;23l-ej_f0t>(+!Wkf}lr8$kXQIW`{cNeojj*xIW$upnILG_vGyc9vT#v_Ig8MOy4!-&c@>z~i!k2Hatij6`PDpJ1pIxNV2 z`RqD?bRr83eZ1qQy;WzcJsC0?#T^=HA4vU6CIDPxb{%@B+Yn55-ehqM*(Spv9rcCb zWmcA7UQ-!a@s!ka)z6{HUg1<3486N+npbzS)Tva&lQuh8QQoY+0ShF6s)r<<*wnLy zATmBR%8IhD@A=^s8#C2ziD0>oJWm{b@AV?i*0Nz*cq;NG*#JFYOXBKIkB(0F&`#Un zsVs44kpMJWICI>eQ?y{0tysj91(F_%bn<*UZB&6IHgkX5Y(1|@ZCv@Wvg9OaH#a4i z9?-m#3ibA^737YHFg)~Ndx@5F1x)-9{@br>%?Q5huiCQS;<{NN7n)Z?Q5kv&fPJS_ zz7pMQyW4dcskievb84M1U=bO#+gwvSA2|IimR(cMn?L-XE-3qZ$udW4IPrv*&SZbe zNU++7kikfsApki-E`9yn;C!Hy>ifYY(Jk(BBd1?o9sKJxD0F+^%!xyMkf9fi!nuNa zXtjThAWZ`@E&$5!W`ud1Gy0!e-A11?*`**L83=~%`A%kQKl z4MoJR4!@6J>wpDqW$mmeiB{eX4q)KXs_azzb@*U6tHbj!=20KGCSJ9;M@n57o!mDn zXh#Nql1svr(?xvt)O-O0WC+3M6!_3V<`O zTrM52IO%Qh?|zF4!e`jg=vPL%`VTi{@0W*Vf#QWw+Bdq?Tcp!y$Ttb{D;pg)u+q+y zv+Nj-5Vgo&VQ9#2S=KW+Z?N*rtbI#R`vPfGm&q`}s)r5-HoLNP=%WoK0vOEti$6UDcw#cduvn#&)MewbkXk-|* z)aKK3DSsptWb1xcmxEhFeBiO>p$FLwEBT@uyl|8m?dILYOmqhWYYvw@SGo8gImK-Y<(X2u^Uvrx=nDZuJdN+LHqO-Ut<0`V z!IbHQXiC7g=3QtBQFOM?BY_96H9qo_U2aK7sdHL=k9j>-ND{S7xw6If_BJ!3h-BA# zin(%tLpGDbGoTH*^4wy1eYZE-lDQR{zTn#1D&k1%P&eP|&yY(u)wC}(?p`cS|cb-hSia)l{7jCMsv7>41^K&+0AAbqf zEQsH^c7TsetkdoUMit8L$5O_erjPy(m*rQ*zP&UodLNfh3pp!i-Vc>pOf5SeXQr=l zDGEzaZ2UK{=jP^ay`x>iP^SI%tD!=G>`GbBiC7{F=-tUsyV&U3rtj{^^5sui7jCo8 zPq%7mVDa2!%ekQwx%(?=G*-WDqxf%WYdx^adfmXCk99C_C}k>JuJ!as@ygdS-?Q## z_6kAu#)qyFCaS0&@_B~JRZJaL+YD2~*Sd7D0SaN7p#0h}LuWeV$uXa0>_x;*;Cg3% zp}1^`z_{|Qi|1K6JF~UGo9{MoO&jl&wKjY9E%JDu&I-CYx9zzDqj=3hN+DEa%GE!E zvV}I7qLz?nK-4iyTYDyzj~G5TQqHaAB5~&(TdhWxekF7Veegb(djab(c~Z)1`DDns zy;v77F&y~3rP5%qd#%v`eE<|J-fP9KQXVhhuJMRR!QWB+G0Y@~Q@8yOn#K*&{l-y( zLB9?B?Gt38PD_296fySsnSl4vB}?c;y0z~cj>GZC5BZ|1k%! z33wcOZz10E2;eVZ?S+$4UA1#RRiqBqXYtu)m3hvf<95eD=CA=pjImUiI_6P{JV^jG zQLJM=ETciA=sEq(!7AB`nOLl2sv(;=OiAKbOG+AFF(eJIb@qP4@6j=_J!31HW6=pH z;sUqPt4ElWWK>^1uS0(mSJ zMionW)krL^K!TP?tm@sV&lRl|KCRZtUQI<+)_1P*A<3MBHFP~m&fd23;RsG4!-3ms zQ-+vyhui_!S}bXRf-3b_^ZHP)R^-_B#v*NY@Pikh(mzmIsUqCm6cj!t+3jPy8KUQF z$@u#IHEU634+{3%P$P}<#t!4uH{P=+dPM*dnB)5d-XAvGZpogUJWn5+gje zDIm!Kk_NEJRx+MJQC%>hGXT{gQJy{APUep6-XS9 zAM8wLf_z?A)f@Fy@2!bxbQqe5(*ejTh%Y(gyy-`_m=Y%R_+yn>{_8|3)0{pUH+0yDMV#)6WL3QBj9Ju5CYcIe+V zXck$q_pVslnNqiSg zOr@9*Y187(bQccxx8xbtQKFQ{CF&wx-kr9Zw}Kd$Y#v=6H}8PJTe}_BH>0^3IPa~q zX1?!7EuJ_l&Pn7_5A|)8DbF}_??PSoa2q$gmpM&m&klZ%&o80h@b@p>A&csksTyHA z&=Oa7p}IEh5t7sn9rf-73pPC9H|msfAG{!WRpc?wns?#h5s;xSCb=tPqm#Q9_cgz2 zT7P$hMPK@w*yN&0BfzOCUjrz>hI1^ML2K7h>s}EfWwc`_{7uf;5)qT%I`mUV&6O}Q zF>xTP@veRuK(EZIMBWPQqhis&x1Zj758L)s7ka9R?it)JnWqy>ZGv{(DhxR(rLoK- zLHDrFC-(*K8H_dRUBpYW&QzwcZXK1WAWog*4T4KhX-7Q2Ic!V?$YnQ8<(S5Fj%3&w zoq8dBzm-~6MB~JuZz7%SFXQ^vn}2yM;u2fkX@4`G2Svfo)8y(-W+Js%;(~U^D(63R zHVb9Lu<9deLVG4kEB1Ch&WLH+IXm)N)b5kwtD2j9AxXI4687s_A5KBH&wxakBAG~A zj0%rDWdJBkGPQ{W1Aps}C^1yxTR$GJjUomkjjA~Hqz5g=#0>{FuAzo{m~|($-M*l- zv3p6|kevV$PYr~%-7g}@6ey{XR zWts~SxFVBmFRO@qc0;LcTh;b2CiJ?%f_8kBNw<>NOgxN)d3&}|J4oZ5eQ#_;gkz6B zjpMokg-h#$>qFGyma7r|Ra{5KOqF7Pn0hf|UaR%^w-3U9SwBZTuX zHQcbR*B;^3d zMMZbIAf)zKw)_k-Cfb&-Jtre$OY~Xi)}TDwynh`9^q>o{kb`L~s%zy_(s1JSb77VP zC|(@sKMNF%{J$8ccP-lYCkU3KV-;@CD-rAyfYk@E_?T12nDVK~n&YoI9EI(%1Qy-~ zhEtnkpDM>en6kXXuYO9roIs<<#duYGxQ@JD9~(PqGS|Upgb_~A=xptR-(+l!;CgQ~ z?cN7KuYVz`0*#2GTUgvKzBcUdTs*R`+ZjJOzr(;ynd0u{xVYXw!eJAKjw_Cr!leB{ zHT!3(>o2d|crGU!n<_fHVa*Ig*Kfls)*~`B)zy=NJ}Q;d223eU7d;5WiL`18+A84J zxP>N;#zlQ%zzF-4Sj&UkZ}@EvKNVi=7G6DfS4ox+u*LlKOWB8*4jg-o+?@!e_=F#L zVZNtG^(Bw?eNcsTJKQq^X5U|B%k^OvV>taYllz}TN2M~j2*?vO9#|jSGE?VGxpJYH z-o}=3-ZpwI#|JkTi`i}0QoJHVSX;eRbMpd*0lBpg1Zwq#0HtK6@_9Y}g#HQY%l(WW zXz?zi9)k^h2=(iOY_BcX!|94yW zp@b%x$?#&(@5uN6sgurFr@w4%e&l@1eBxA9AEH265j}UdiVBfdFcY^}!k-NEvgo!Z zlPHY`)L5uvfj(Kmj|VPABHVQv^Qm#2j*o2*Yflf)-s$w%*L)A(R}L>`o*N-lALn(- zmYNtx7R4ge>IN03f7yDkGYctzIS2p+iL34(gs!ehb*9kaOmc3YOM$Zo4~35cK}fAC zN1+P?#9u@l$El$p(f~;bP5f2$dMI7PN^QL{a#uh{G|X34x`|W);3`rs)VF}K4rn*e z$L%QAsP)$^1b9h_p2YDjOqzw3C)@s)LH0F74SHZu-Q0lJ1A6(S#q{rMPIe0J*Gttn zVY)UQneO@D;57IcI_|a0L6UEeVf=FyNWa)3Bq=rcXb8H?y~*Fl z^ae1KprdsZf5wqkE0xR4?rF6)>7S@tB7a1{qRTb9-bk*ua?I$-7f3x(E zK@OW&yrsufQQWw5bv-?{fjF4_i)7MZgFSYW&s7C5MW9J56h7D&nXU<;4S>}Vd3i_c zltCba^`>Q$ibIsGbz~%HG(svl_=eI@n~#BnTAT{JLpi6;UOdWzl0W5w#M=dIt> zqH1I20Ha;gdiBib3j+vP$D@DQ^fB!oB0p6G0I2BD`B1WV89J(=TJ46Agh)h9Lsa-9 z3Yp+w62R&<3=dGghe=vk4W8D?JUG7Tejn9yT2C%%tR_e@_9$kAyf~a-;w^bwB?4DGy&r92y~vT{h>NZm83)O|g8yyBAW{~G zNz4_z{YaTh^A*bgV;%O z9`6i8W-$5n<)4IPsgvb9x*QUT%|~x`dR|b^;{_H_u!r+8Y&;A&4u(&O?xpwV;Vt1Q zkaz%J2gG|vHnpAK5f`a3-B47yc(bH#u_r^&58HsvZj>|6obX+hRhFK9CC;@@K@5ye zm{l!~I)cGjsYl>l`p{v~PAZ-glaM$7^YS#y)3LWA4|(s+!sc#eIL5)zlGFZQp_X*O za;v5`2-O{E`)|hun$6pVL3#Pdp3PJTQN2*6?D<1n zMG_A~Ww za-c{VuG%GL#SeQ`A9WgUm%Da-Ia__N==4U4^h{^#O0Y?5#p4Y2`XsvD?&4(KfJ+tf zL2s9O$coK63!~#{ShY5#bQ~uDbZjLTaWd;-HtdU>Lp@{4GGJE6l^{VjmwI^bCbRJ8 z=>AE*RQCD)zuxQ@0pZK-Yj=#GUU_n$YyhZ-z9Uz;NI6#P?>q2ww(lL$n&0*%jf9+q zqzXRn83uYE-1zo&&Rh}P9_!;vJ-<&B$Zx+$%Qr7KH}Xkq;;>IyS?kaYaUJ`ruF!mV0x1)GY3TFC6?S5`i4Q=-p7 z%ffnUoOW0UjDIBgALVTyF>gdJ&r61_`->(&Ibo`F4%GSk`+EFDuhz_0FUW1~ zVw&Q^(Cls#fzgaC(eBNoIR*L`_fM1Q8_a;x3^lYAaMNUEuv(BmT;qn(P*)LDH-<|Td}}A9Pq3aiHpfNzADy;q|I>!uqP*Km zvfzxt@tx~L5v%Ek;pH@+Xo=PgXPiSp-Uc#E%pEMuxXf5uo}J-S6!6U2lh~;I}eX!_KOq@n3_LAuY0$ttK-IHC;fNmrlkG#O;ldbBoJi)%_ z_O;4w4p{3QM zh0-wm>yK#+qQ}}c8!EGId)bzK2G9q4BxhE`;UOz%RT~9)J|u|1YNa*^m`@9V^l+MrbSTC|f zaKn&$C%LtsIJ*rVOi*kjo6`qj`k)FSDhkAt!A`b5=B{X+tX8}A_XHs9BVgnD*VWbK z$B>A2q%IaS9HDEr$r`@xB^ct=^}(&AztkNubf~|6`~{1W`)jz%Bg%P?a05KfSEv(& z9L_y#ehm9-z5|;Y2!a=cL1F6AFC7 zKlR`IVWumzJam?|U#j}%JLjTE{@22lOIWOzOd3MgQlH3mDv{F^)MQ%|q=5cF?>anR zVYD4dKnr|UZ*C%%L?8XMqlS$QY|qyO?I04!(aT#{^3=k9tvA^|6#b4@iLbToj!LF8 zCiF07%L8S44f$Yq>AC39OkVsWiF#&pI-0rS0_Raomb#qdDNK)NtEE*4+WkkiAn5OE zdgO(?3`!`4IEYOU2BIr;Bs1 z6qSw3RQ$c^_=HU8zdHedWT5d!XuDEUzU=zS3=I6m7cTf;$>_B?&T7}+5W0%i+WpxQ z5cXIzXPcS9WMn{Xf)_UV&!SPf5Fix(S4gaq|8Xox3&ZGoqFW6JQlEKmB8%6Ba!dH% zfYm@GH{hpd@Anh(h1&_Eg4Tpv%kqxW@e79t<=Fco?&1_ist{8c>aV~=)H`=#`F>7Z zSl~~U(_r&IegHrtCrLY}%^GK1d{Y-*!2SQK7Zg7B$yPcqrHv+yV>C&08h0W^!;$GY z844L5H-Jv@V7JJ`cDC?&&+<>+WRaWo89v*|W5jG4HlzDV@H>6$0W!WdFH7^qkUWV$ zfOkJ+V-}IB)N%^3Q_ui0p?kQLt)g9jCm7Ioqj4+$hJ z)sB;MDS24=NgV{q#7+AX#L&-Jx5^ri2vsa8$%mR|TZFbQSzLHs`x{~AcnpbjOF0jVY zG={nXLdHu`Re7M{1b@a{X>@9QxyIr9fn%QAi67`#Swt#z4tUTv2b*C7BCUb^Vldls{I@7z0b7qK zQDr^VNxUc_^aj}M7j%hldZtzNQKUq{R;o!>WqlF|&?=xWDi0e!C_-L7?o5?rX^ zp#h*2CtsgE)kjhc^x5tf#X!Cw6)rnmy(`%ne~z^3_r1VM<=en|MI3%x0Rf+0^>La- z@#<<#=R4aypEsfM?Ng>HoYhL3n?=Gc5&CYmT?))VUXpfheo@jr`U6{&&x5mC*zOpS`Qr`l`0xo9Sr^TAlaHSLaf7D-emt+`jN3@Ev2>#lzWh?I7^D;l@t; zk}ITQd+n~v;;ED=S+(@5dS@76a5=l?cdF(ZC*d`ycrlk>T!3-9v#?OFhVJ1qm)q&? zgN)_XL*O5-t4E}Vvu(2eoX@keOW8`&8=j)PKkhlxg)gvw8~U}aD~BXNUrgiH2%qUU z%*ygQ!s>m!vu5k$J_t98v37NhEgmP<6m`E2f@55n>!ssp>nHn7Jk?b#1y2+9V<72lSI?htkW~dtcc22D z06!5?IJDFTmz|;7PD3YIOZXPBQHYV6oUWUh`|4<(A9VU!%&?Y{tMD1C7Iye*A>~)P zJU^VzR3!9_mZ1CpeM}b5aAyAGPJQ%*p*7V;cg+6i_Jw zk)Qf_eTGmv# z*}iUaz#vFvz<|qJpTo_)*(a+ zVjE$T!*h9oZ%QPi*!s;2f38#yBkyTh!nXZH&}h7$tWDx1iply05$_2aINbf@L-HsLCpxd;js4-hx` ze1Q~weq^G8MUki!z8z;PE0c7Zoi4noH!6&AJwm{9^jutf7WLgHS=5+|xS;cW_m}kh zlz74SV^y&TNKOkU4fIvWpU(N`{4P-205rC^iUzs{x(amW&)gC*hBe>BcfK2EiKy@_ zpMNK374P4nt^V%hKO0q?5I!TA9MkdA0&FA`cmPpR(f7`>z=d&Ju?~W?owz*Plb~Fh z78H;aHRu6{E|Qzu1er92%Mt~N-lzh9CPuKEYp&-UgNVK9A_;$cS#{Im=Au2-=w{`7 z1h2&C?t}l!GAz7>ykgS4xyN)jczDMmW85-Qq4(+W(F4^U1G!C^JUK^86SYVpNQEv# zxEt?gI+HhpaYxiC6WJu#JTHFT76w@wx{1Ef*%? zg`q$V1ohYk&zlFYrr75X=u}Uo?)B^Sz~%W?#*>unH|0fQ2b-?+YD6ao%Tk98 zgjOk4en5(rGzHF$528VkH+de-g4+q(_mbE_*5K856cvcJqw!iE*9rKE|3SwRSePNfHO|D;AuuoA=r#2 zNB^9h;XzSoA>aA(tlx2>3w>`k_|3_rNteUr0Nt<4 z{jY&`-l6Hn&5`x*5*poz6;U@>-~#VAg@*35;Hn3?w=fNi=yNlYaspYR)wkIRhGbRU zm`WNLe7*)IReynMh{#*RArNm)pU4%?s-i2WOC0}-Lx8=^`pp76vvzQaL8ZiCQ0(km z9*%kF8lCdi)Sx{6Y!gy0nP|dD^Q?8>hZ4fINCm2zyS`or{Ox_HNda0O!mLA{go8OO zu1FM`29|e(E~<8t`@vYz$IO;ktYi-`RL}ktT`XRC%N=-@0iDFUp%5qi{pVLlv3BEp zWQ^K_8EZ6xGw~te~(pe2$WxF4zWyr!IGS>aivCr?#V|cU^&m^ieqR0zg zf?paOM5!pKu$1HQ6MEM=RvbJ{!phH! zH;4$MHQ}8w;<$F^i=O`ZFo}myfmY$;BWX>s)&!Ii2_KL*k)ycl16R>a*;HnSK4^WD&mD$Agg}Q__aF_BwgCSAm~wd zoP5+{(gF8ZPF8_#qH*5;_5c*+D zLxtw@(lVn$PmQlIk(NH1+45l?FC9%x%W>V*t?RVZp-iQ6$z^CTsUsNquvD*kk-o4B zWPq)+h2)t^UZbEV0*AsSTs-xq(h?-f+2;0985ASs;mECO26krm#&|4nY`N!OzQ@xf z(kD<;@#1x$ku)$rKv_>JZQ4}XN?D2vW@C|1 zx~PsrQD!zm01g)FshYcQ1oUdS34Mw%?%2E#q!6VPmwqLtLzM}^zs|`cksKz0!J>+Iuhhb?rjK3SYwY$ddWN0U+gWAY)_Q@* z0ez*0WQ>$s1f036NBMtutC#9B%_jT_N7%8YEjIkROPDmA}m{`|u!u(w*(|+ppZrz8a#~j5xWzRt$jgelXNxyA@jps_NG;Ua~9* zz-y=euVd4rDoT2P@7p&~NYFyOH>;w{xx75@`FEmurF4JREjD<=w~y`lozZi0eQ?+E zvSRnOt6jVxr935j_RUo1VtQtV$;_6rzV*Im9(s=6>D_Zazg4(h!3Xb~%gbY-L8TV{ zN-f*U={v$XMjd4ccxR0gIJ8$5S-IHAf%lT;>6vQqMH69S%HE1gD&@8{qOX65 zu*)?zot=bxVpAF6X(096eGpk4Sri$}IrW&7#{F6wyJ5-HV^t3hs5 zdxR5fVkaU9Et<+Q8y}Wr`Fn3#2&F!Sy;=Aubo^keS^dxF*F)tZo zE1cNr>i53(d_J8@D?(imucIH&&o3*l&OD2lMX?ANcm)8jgps;jzw=%=kRC>p_Q)jF zm-sNgTFhsT;C;TkVZg4&j4eTpKC55)XAc5UGElBl{oRJQF!S5)_>Ir)%ZM^SuU;N? z^0Oj0r`Ti8K`74)OCWUGu_JZ0lkn-AV-YyVbZj_OBM98)h=h`pkzIH0C@cjg=TE=S zR!3IuhUOGS;w+&5*^9$_lE?xH(cY5SyZ0=iKfy-bz{34C9}W)2wxJW(G6muz@3sm( zX2@9(0^!j6h*J`QO-UbErD7}eC0xR|AhED)S5BKxMTW82#eAvr7hMRBbBGd|#2c?} zg-R>-T@cil9!iv!uC^KpSYNq zSn=xEiVQjB%B5*jhRLjrP9DFf7N0(A80O{sS=eesV|^+J?8xCz6$O!Cl?@(FWAe`< zJru;VL^p)=ID3O7B_$sR(&nK=^4O43QBRrEo`A4!v>Z7IG*&pjnimfki#>WR`YBp! z{Fw>|;@kWg+hkRhD8R|-`}qyU<&~|jfY5-cWCS$UQpw)l`=W&+H|nLG?)G>LmJs{q zeS$dJgLqFgS!7x)&>-6SOA+1zw{*r)Sq4uT42X-|`t#7n5SnKbDba}WSiudS@DLZn`hef6+V8OSwm6Y23hh?1t;B4AX;p&Q?>UpXgm ziQF#_+}2%!y-+NhzMbWxs%-!d;P6Ll;B@1#_{BxfzzP-F-}|}c&(6}m)w_^%v5)nL zrHM4w`;$gf*JF^HRR%48)FN58*7{dqxow2^ED+;}UinL#Vy!8-BCJpLk$K zd4IFJ?5a=MG6jBDCnXKVsa&^By_>f|;ro8a33gh$J6>vJI(3+Kp06_KprZf2Hv0us zE>uavx1BkivSnO6em;gH;fb6@J!)0!;=qzOK5a4#K#f)ods1jIN}~4;`~qWMGcb5P zKbmQYo()dW{}D&`rFP(IXV_%4$oxU8k2EvbkYoD()87?IkCgNukyp{Y$xSaZlpTjW zjvqVWLpwZMR!;r46%`C0bKfsp*XwdzoRmb#e}Dl-s7;CW>yfJ=k2j88^a~<{8n_@O zRxlsr3R)3A;3XcWmcX2`=(jp&79Dx~l?(&Wan~^;m5zHJ8eOb$2ty8T9Tq)CY0fWh zhJN&mZXRsVZT_Vh&Znp;uRzBki55+KjS3AUeeXO*9!I>h9PLeyjX0>86mx8}F5 z6;HJ5LO`1Nm8>B)=6raV3=@V78?nU3Ogt~U|IiDe#*PQt~J9jhK2XFSc`}_2^ zGuz@D52XrJ=&_%iJ;dQNCF5{^h>Wl@N*v*`EP6yr6s$(L-H~D=g0Y3lDr9`HT!}h; zs+=_dzNE*FN!i@`_Va^Si5dm?KEUkI+n`He<0`>wo;%SIhz-oj30G+i6%e#m;STW% zw*j_kM`gmTOwyrC7iqfHh8E!;lSW20oI(1npp%^lxt~vAv44(yZNAv`Lb3rob??4q zf}}!77;MCH^&>sP8{Nptu#W`y6{!OFam1ys_FtiBi-Ms5+}J@Arf}p?^iZw%sxY_f zSM^oQ#-)KRXFist+aiu>LS&sz6RKahNSKWc5J2APGmMBU|8kRUI2dS{F1-h@&4pD5 zL5z>MhNpesxcnDgPq|dX+}>cT_g2*V()3oL06A-omQyf~$$4zFLB+oz9C&Ml6C#~7 zd4ly4T8)abT`KoaSMhmcaQyH*=x+WEo3{Q$#*7jtntb=_;%QW!+oH5ao3@tdNsX*| zwGg~nB9Ws#&{s&H zf@~s3XsB7xvA3xeDTAkwm-HAng67H+EDo$YQS0Jsc=L=Snj-iub2pr#9#JTvI?*g2 zFL6V0jS5gFRJ>ziiXBTch@4GPu+^wll`v4XRsW{NQ2+eWVmzh&b3Rwd2feoIMr1eF zkf-+Q{5o9HQqP0!`%hPM3kw&B0Zam(pxIQ7atzZ{hOFC2HT{f4Ps2ob@i_uIvgW*0Tv`yyS%r?@R^UZO(nO;sngCtjwNnPu74kqUQ(? z=ba%GGA{SJ&F(YN^s#V-0Qu2b^LJFD9mL3GURnmS!jkaT;AvCu3w?@Em}pr{2IKg`a&qd^Yn&{qOSQ)dc54kWZn}5F)}s^ok&OC zz{0>FUZVqqP6c#;VKg}f7gi3H9#v)8h+~JT6bv9%poO($xH+|*KVn)-hRGdQqQ{|q7nqV)|Tojx~&ifPDf$p$|MsjO{O z3UY?4KL&q)_CxmG8|N0hT87vsy+!IC@&q)!~dD0bMNx&g8323NHdTFr$qkm znA*&^zLQ{Y>5!4uTyWK~l#$dppS?AZh(6|2M@-JskK3B&P~0WxD7LgHdW$2tKgvQm zz*X;vN1R);B9fmae9rn3Q?TQMzVNi*w9nD$kK9SE*ezBy_m|yye&_zr%iW>7CLV`&AZ9&iwo^+Pn_r4Nuz(28-AG0e&s_ z+}GAtZ;ci0@ydyW|GrIK(RlTHlK*==;M^bq^-&V;zQtbAJU!2cWVKM?I%%aP#Dzr| zD$)OYl_fD2DSp%%S*M=7=J=e7?e`|Fy(<)H>MVT88)AuTL)uW>=zTP^x;)-{4@U>T zs}&YLT+fm}k2_X*Lr^(_7;}1L4L7jnZqU|ipMc~X!%B(E5;Oc$rw;s!(Mdr&>K_k6 zr1Raa=qLRS!|;*vIPhnyXr#I3X06{VOKemlK3YqT?}vv_HUULq({#((hD0-uLc17kI#&Sp^#ZKU4%l=<}2im z!&#Fp4n;wU8yiM3!E8Sui(Lm*vL$L>-fJ)1p6?mc`s7(7Tc9A5K8ZTKZ&QoLA>!SdtR2mT(XDJUba(IZa%t;A%%7fR=R(X7c{xL9puk8@kVf)fp7dGG-~b1Jv9b+COk`Q0^S zqVoLRzhlUSpSy|y+Y~j(mjeyjRFnaDy-v!?=2o`+G~NQOOEMpfcbd1TGqFR;%-qb=$JM4y`S zig?9LOwln3m97n?yI==x0^pIZ8wG)-^UGMT`z|yWei|5gvb=DD_an3gN3l|+k-1dV zjzvla!3_$cVK9#?skLA4gf8XBoLM5YP9|F^Fdni?N;#3*Slqvib=W zV-WB_I=aC7|LlR=q`478G9ptTk;Qf4v3mS;3t&LAW5)`N2hLHw>a{DLysubf||ltumd%#KijVSzw~J`ms1OcA@$aJdn0Sq8&cA zMLtmLYEh&Z^`ubOAq7AJw6QR0!;}o5mU6M=xzVfJ#2pM#=eI-aL1GKZbM}aWbEqc( zH}+#`q>#7gR`gA>O${O6)o$^hK6r?>w|?H{c*R#Mb)#j1SkgvSKD^~`HCXM#+%{_> zVdxn8#p4*8juzDEx{3L$)o<_0)mu}OdOpjDNw%5Wg9AMzQ_ah}r+9G#K^t1O-%SF||6@oeb!)4zEm3N@)c^ zG#@XAQ}{m`yU%^($uUHWUaXftO~=G!uhV8rrT^(7%nwto*Ce6i%e^J(It&oW`?z8$45o@&gl3fuPTqa=pc6=g!E-bFqr)ggG)YiI6~c8)hO) zhev_B2DW89+2mJICfqK_eAmjAqFBR0GqYjitzVf{4?CyS7W>9?P93&2Zvuf3fjQkl zTf$}>{v)BxKGFp$i`0t?c>1VtZvz{cH2l6hu&uKpU(L=7ni>Pv{*I03O%~4E$i0qqGCVa=a*uDJx*Qg109}A3@6ZDKZv+7-kl@xsT z4LTe5e9J!hXuY&`yU~I2DrDmDV4;or$D0xkm-2Bi&dy&okLWXRW;k1~rxIv(jL$tW zBmX>V_tLd$4ol_!LcjRY%V*DuFU1)OIKP@UyT4g$`KXzVczruWg@!8ebj}VB13CYk zucDvE84nw=@;J`r;^O5tXAAVKn+=~29ddi^{VjE{*YIiQoXP0q^TzZbeu8rnl7@Ll ze_JsBm*b=hO|?n|0A7DMV?=7P%6O@ukLB`{sns8>vsIXaBd+eTWeo^I;!Vk)vAI}U z5FxhiB2bvMn7qO++oT&2z_q|MIm#u`5{?}Z;Fu?Y|4@X^K#)- zS;4F|#_rDh-P#FjvHC*Dbxs1I619$#iWQx%8AS;bZ+>K2^{z0RYb_=|ND46D@HOQi zfQTia4B2<_KP~DtmoQ0_Fy{V|>pC(pk(Ijii=7<;J?fB>Az3g{SsLGdijq)(* zT5!=6J%8PKpvQ@|ecb!r>1Tc2@+bw7mzYtf(sA@ox0*c&DLIlZxi)SNGN&CfyIqD~ zb8@16r6(wOu|LHtyK;fP8Ykw`FI+-Z%zTl39r|3msdN&;d6D-v9Pdv~)WMWI^9}Wp zEMbUvZDg-3k6EcUL(-?K&n_Tr^84#ZweGL%n}J8I}N*)#2Ke^dm1Ll-@;3P>NCv z$%@>R<;ZH2%TQ%+efG0dEU(xBFE^^O zH*}|%haNGM-&^i0`Ta1zFn}6rFPnhkw76$iAQnh1Qwmo~Y+cpA4hZr~JH4(aYOVbQ zZ4NE2TrLre*1aB-R@>#XKwiwsd3AMh*|2x8&_$G+CD;7Ruwt6Lz7>A$shOssgGi6( zv}Y^yZC?Kg?tZ(GEuH75Zz&BP`GxNCg~Lj7we+4_=?9vlkkHVVNHnq^tcB`i&InM~ zpso>xeX(^iAQvnU3c*(UM(7|Rao%@dFWF4?d`{&mFL%-XHxYg5M8q2rZo;U??0sau z!x(zUNli(q*~ytNN0}X7+`-&$M^M9RMnvu@ELV^6GibZQEB^BbqXh%NeCHDt+PC@P zzKW4)1X^1)tQqr(4*I7C<3G=A+F!%^o!61xig~qiB5|}VT`mn9M`n^4tnT0d=2E62 ztod4Nkd89JwB%9C6WZqUc$QbdGv7Vf;&|y;=oKwNKcTYibXEXzQggIq<$dyWm;@?W zuS3VOgL=GbEyN+$#^{z9{Vh4qm|~ZulDr&W!1-qHS_=;Er|xXX)#Z@AsrY9T6O;L} zjD)0zB$Ni?`1VeGwS)=C&7`8kfWq>2ynYQ}#`Lpttdo zBe>+y7_bE?^z?UsiYOj`y^(I+&t5>af!V(e^L4uZ94UePa&8(Fb>NXpyw1Ar62`$i zuMgwX?cv;2TU43x_cIAxSy0oV+^EEdDl+>z(m1rW) zpDMKmyv1TPY!CK0ugS!6MT?m?VqS9u`c@`zBmggqK}7REdj)mH(1~#kZv|;dUl9R# z1Y~MQGeapDzNL=`qCKzCL2r}|4tz6eT*&j8~L6zu>%JpUdR^;x0=x~^=cF$**c37C3BER-O~9jyx=08IMU4dCd*L2Hg}B- zh;=8BOfk_eI|@e2!ax7O<1i_Z{G`>wvAB@FxZw0A5Tp^bhzgh^a_=VR99;Ot}gmuWqNgJd$kzI)On6qNT7XkkfC>5#s}`=D$~S;iq=L*R6*`tyuGaTt`!5XwY(+{L%v#eSsy zTevzSQgJf}dLgIo?rUJQpQH9KDz6_0zkaSVcRbgj{Hrk2hrz=|fE5+5#sCZm7q3~W zp!tPmwd5D6yIb)^PuJjp`_0N)2TNLm=*=W@V!mb+xCE#E%vMo$uf-Sp4#@&BS$r|b zp!xAh#`wQ0aNyHJo+6tqa_@{|j>+*2ts48gxBGdhWG~!cz<&zGT?(epVv$s&G(gdjc@e!l0I=+c3xp4f{Jp5`GZ>#GOs;ZpuA(^EL_GNXl3aVBpe|8zw=)E; zMxtEpV@f4+S3Wx6ynAT@9vJ@mmKIYf{~bvcG`SX2=)5Y+CK0*kVM>X`AY(C|pc>&4 z$3SU`*~EUOZ4DMD=f&n&ZOG)#*5W=>G$eX`676fzGp`{h!FoUdD^4C&KUkWL-#ldT zay;JfQeYss*p64c)fMw`LAKM>^o~$tGQT)hDkh}z@;JZ(ey`8Ogh6}=;OXkK$`D~5 z(%qocDW_zz446`Isw1sARzDQ1ccEk9#tc;1XI(Ntk&-LTQ@fk``^8*s=XWNsMi0hM z461xhD2F2JN$&`hQF5tQe5f+%-`xN31&Eh$p_7D!_!CDG>e;39Rn8VegC9S{U%Z3($ShL;X)63{a3VcjSMLjtJ2lZy>OX~C1TNGbzfp*Nb*(snnle2x&Kg#wK)5;?V0ALUvtVUBXU~5a1Yi&G9 zwNT*j+DJIZ5OIFm1j6pugpj!!1#+Vk7 zK)M*q(vd)3s3`bFxJc!A|KBL-d?W-mT_qrM{hvtu?k;4QeWhGrKvp5H_U^R5HNgMx zA>5$j`pYYvU&k98&~xb^x|3ewRAiSW`=!fPznBukFoPYnLn(Wp^>sId93aPN$Sb=F zePii~rb@dzoLRy`j~U1idSL)R%{RBT2@6z{XxemmsG|8i{q%;U`1o9;b(p_EAWk^I ziA??lp5lr+C7t_!4b4&8D$(TR@~a|kMtt)V=bSC~Hk(l$Lu{0NY|@u%`=70T z5Mh)JPfkr41>gv2vRm-T`bQytkdczQK|#EA+WRZ@?X^nts6d@)O5!vFA_|O%n{=bk zUclKYIXNr#$@e;FgXGEWEw*n4^Iy7(>aa}CD3o2M)U_06+JwlW`-r&&A!g{o5Yp92 zPHk;=m?TTUqEM}e&}j;$ZT9(oV+>rJX*9QWqd*c=?T^%BC+6Iptibd zHWC>r9wjTD5bJ^s%}*{wMD*i*q~xF~vbU>aeh^huAmIxdIR%3e*@@A?x<%5a+od-= z?-Ck5T)ad_hn0M&-m^t>9<%+6K=kdiL~(--^oPg&B{!9_xeO6=_GA)Zmq-zP#GfMB z8)M0aQLcBo99`^OX#VhK(f<;gQWv_wXgERg=Eda?^LN_t9W<5r7(m-cW18fyX&DOxmcUtW$Nn_!q$gU4sxoJsjsQ2$6(iBhoa?A*3*n?r(256lm*PAa59<^ zDjZ8tW%A}P+Y{g%hs}U}fKQ5wQGo5#Fae;weM$0pT)k>S?iZ`B0swk>qP(|juxFPSdXE>)8B0A~>(2>10BoxQfvJ3_FB?Q7G5<+w+JIn zBCPJ*m{Jg6KjeeIx{HhwJE?v=j_giMT>J4wQ)3aDTp}27ka*v_x5#U(MTERrkqVDQ z=c}Syt(D=fALivP-qTneYZ7!nAnER4beB)vSVb%@zMka!8D>n162@J(h?9znDjvi( z;GrRv!CwNp36Ty}3_1>i1zJcJf$T8ho1HLCwYNSixZb)^k!ipL+>q z?SJc7R~Jc?A@-{Sg|UdyvdA-%;L3D`h=!P$uXaY6aOQDKf4D7ZxtM9GTEnoa?bX(P zF5ARpC2jRbcCC4;z(JHFpSA5o!~gNkH>*1llW<}u_xPzH85y|~ZDIu@hJ=g-{x-ScdH?;mk<-0A{0TmFQE0Pi4go}T3g(;4D^ed(@nSsqwx_#RX) za!GH{chwpoMhaYMo{P-3{_BvK)9@esVQ6I7*l6PVQ~Q7^okD;_r#Qg$``hBPu%44x zNVIt5(=g_o)vO)*+axL2A>z~D|622w<37xsl#G1e{P7wxQ+}mN?9$nsrxix|Y`>ruoJ1XwokY0ysjd_FJ`eej+=!R_Xs%u( zJLw1@acKW8Ip!Q#D6qr!jf$(}{8x#5`WJM9`INhjKvCqL)zi?@AglctHSYhCw0$_H z+FRE8#Br8fue>i9l!8r4kw*lX8C)L7s!HKh>1;bX`a-0Kb6As!WS&l;jGzwbLHY*A zQBa_BYky+(9O%NpPhc4v4#waKOtVQc9uZWz!)-Jr|E8MuCY$%iM;A=m`Ll;n$B*vT ziRtq-k%P8U*2X~ds}skxt(L#d!IhVNKG{7g-&p<4*?T?^2}%^=gU5nzaVj~wmfeA$ zKK+3q=^^k5rY7$Z3oF$AX%?g}g&uolK(BuYoE&xTwjraSoBfy8w>iJZlOSiJWoD?% z3>MK^*!0$bI0Y*er#kNmRlsSciBVPNS5s0AB9W)7hy+vW$? zef~Rk75UDW*`d@fddYO&VqI zxs1=!xsKSbn!-^;9OTf*3*EiSvHCTq0_w;ddd&CRPt`mYutgYojt>bmiC@Xo1P+{d zbgJhC0`-g>HWCowYC=@Le);X2wwlxDWQVWMh z$;DQy^`Hz^X>d&nV;!kDChMuiU}@KG4b0h15hB;=RJVTpl2B>$cZ7|}Y(=q5DTSV78;D*NJ#|p^`36;@A{;g*NWa@GVwZyUxuwhB{% zyn8cpe7U zu7KrIJMHZI3ph}ryw1I4|A(3l-EDxmns>@y5B1aW_$p=v-#aJ}lCFgV+yfr@fu1pS zx}DL;5o|KTm|pV%GcuOYn`VFhBBMYoQ2ktSqFj_JzS9pEG3eMlZ%GUBhO(Rh8~IY8 zIu?h{bQDxS#u6+;`o;q62R%#927kMET z+xy|l)IWQ@b0)%pltS9tJ$g7#6t8%@K29PsS+bv!6A`)b1R!L#G!w8b)nUkkn@@ll zY28g=EXiT40%Pw_62WAjm9WRpPCSr+VctdA7#+CRj*~sOD4FWENSjywEOw(TK;NRE z0O9E1I2FP#u1+9ITOgyM2kI%@?K?PxD6RUa-%yDUoC85FnWGuh4)?$cRmlz16OvP9 zw|E$bRvK3~R}V2ukKw&gjCtbZy0Mxlpu)QqcU0LPnJimxhX+)8#s1 zN|)mRu02t=}TrZ~08}7f_aiVcRKELg| zrU?CbRm$N~2}l;XbqO!jjKsE#=Z+KbM%?r}T{#^wgSGoV3+b>C^LaHU%mp|_LDuHy z$;&->(f>&S-uVb`tEm;t*e-dLe88XE7YVz6fB<}25=~yJ24{nzHks0)fLt=(FSL~I zwCnm!gn%;(KY`KNVs8WQsWQkwgGmX*tD#{Aw>|#KX+G!}BA>34^!pAKx|!QGuNAyA zQ!@Aw*D|khD>KI9IFQ_E_3^eWU>65xs|bY%0LTKbP-;qx>y9x>>Iqi61luL0wWznLr*B9;?@MM9N9~866GexL>&?zg=A2Ungh5y=hLJP+ zxC)o4#$ZD1xg-{Sod+slH!skx_}3UC%U!%jN?@4g{a;)5u5Qay=frqRfv0QIwEUL;Yjh&?w7LI*vL4>Vq&n)T8cm-R4-&%ri+)kBeu_oQ*VSwx>!z0F z-u*y&%sSgt+Ip+rvZBZY>B3d-+^0OhreFhZ@wAQMpW zI;e586P5?|BxaCHlap++MW~;8?XN>@B3zOhwB9-j1zF*a6VN8Fu`-unO`|N7LQk$8 zo7jbnM{L-sZ48)o0G;2mSk; z_Zn8oa`8nBqxk%p%sLflGH5vi*>rgQ=A6O9`zGVsWZMNCXguCs@#D?a9T!8DWDEL} z2IqW+{x1*G-e>o*e@7G;^t-`Qv?1?)-#Xj53U(lK4Ne&%(RpU)@WLP}4G}|JJa6%}hmjeF{1`Nb^F6XD|i_isX)dr40v|=PJu6b{;F3|&e7S*iFiS(IPD;?UoF#0O+5%J&!;ADTn<;^OdM$fe^vy5@+$BBJkMuo{jSNNAKRs4@ks32u?gAc*^6 z@%pHizP7cg@^~Q>E?LfNs)oY)CPCg*_CKKRU|T)}eE7_-sl#iXr{6qToS-ZYiertt z7$6v{ltipwszQH?z@%4Kr6v6}I|(V1F7q;>NR{cPPM5&-Z+3)n)8iK$%V4^El6Nbh z*94-um_J@lcvBf|kqn=2?>4;lM(L(_nB!n-K^(#@_}$+EUF8&Hb^23SJ1emmq%;*q z7Om#P7PwHQopT&Y*tkSpRpgwC)pF6SKM?&}&TYi8gWFn6;a8Rl!<_`b3p6S*`2C+M%2 zL6E(C^poqsHcc@ecF^$N_8837rWAd(A=$1P=TabI35PKau;tvke2^Pj!kGt@k}j5y z#kySeVN_Ec?Or4;gVnfq=gs0uFH7&>+;yQ)Pr8tERSxER^OuxfJiz$gPt&3$p&S74UJp zC&?GQb90An?+OOt^sMj{x_LQWFQX@XFycz4Nz~5+*H(`6glt(qQZyu5#kwb9cg;#V z>=-6-D0J{HunSSUm*+{iXo7*biMi8CSnfa6RM# z&{W#RLrHk{6 zp|92h$$;~nAEI@4iyR&#g(_b;K*olhnFkj*2aVmju$M7`&`{KNpI@^<1zzOqYB+%zX^$S8XsnFP?fcd6-(YY^uR$hp2K1QtQh_b8 zTJ@Jc$qM^}+VUZyHCU)^F&fQ#KHffAS;Kj;yh`BpvbKjFBgs>n0*cCMzF2dmnqR0u zJ{yVr%SatWaq%~~2TClBWmihUocW;7lonXtbFI!j;;~vHn^>e@f0v=qGnE?=S#Tow zJzGff_;g_`EiHkCb-uj7p^v7*NIVg*-><1&NKS;!=VP^0^Z#k=D}&;Qnza`Q?h=AK z1P>O1yK8Xw;O+!l+%*s+Sa5e|3BJJsgy8P(7IfiGzPH}`?$5hbTXkw?>dfrynd$DQ zpMILjCA|KHBVVSp`avg>CHh13;nY4eKI)gnoi}d~K!4obj$4c%j-+mA=x~}=AHkOQ zXkpEDFK|XBGc+uM=yRJpQeE(3YF+S1q0s<#;v+;shqdgsOZ}!-^mpt$yC?+6%(mme zA(MrL-G{uRdL(~CNI=cPGKw!o=URMYI#**vjevw9W~{>CBLtW1C@+ud28AaI`{Z>x zew`nxrmhwYAP+#v>Vl(=zS;sfyk`BoKBOv2E+F23-)yn3A%3nKOfp<2mcI=AR&5uM-k~2ra`~cNE z!4zP+YyHu=7Stn(iXf2faP-|~|J=p$lXQ|?ma$&kKPooC%44|qcMTnoch#(e zej^#7q9tYZ+)&4H@BbY?# zUt&<5e<0Xv4FGlPky|GIXvyodanfI8VhxkY94(OXXLQ*5A*Q`gCD`eex)7(aVrF7v z8VKpd0>_)9$!^ahhRa`Rh?Ie^s*NM#wG1re=DlG8iypSoX&cW{UjHq@7wVi{qcG?s zvOvb{>!+2SeK3%*WvWRdFkK(2k-E_uJ&%E!pDi?63vQqHE;ieHNl789ID4zY6= z=UW4X)dDPb$Du$rmXTk&Wyf`9w%P{_)0uC%#0N5j z6YN>;I<@9~o%iqYG2bcWC3x@sF!j!nW`3VgLT9nPZG0PeL4FLo$N0y}c1EuH1T>~7 zxNVBOn2V^Lq!;)$#9LbcZ{66)@yXDeMzC=>1lFB17*=Dn?kekb7&fi>%dqoRX)Eki z{`bEa9K&bxcFhvS71@|w6zS2aqzh~8Mjalw$&ELkfW}H;FR^S~9*{+S`ojfS z`PbzTKE3>4)&hhlgD=85R~ogU2C2~$ZiCyLr-IJZ`gaeebAF1^$7v4pQKI9y{k^Y8 zfgFl`>&k>|;uc^Z=(>OfTKQqUggEMyJLF%5{^mnD%!je(jekObqK%z`mvXV8*A200rC z60a04&UfzCesPoXA_ZYP8!Wwqm=O)+34Na!mNRa&8v9lomF-9*4Vtc^r*UBYN3Wd7 z%L@&+pQHUfh%DOKHP7%5Ys~z7Ki>rwC8~V=PWYKmpv7^tLi9pjp3h~Iu4YxKZ+oM^ zckjIv_K*9XosOTlb*njoTl;Bjd>#)3ixJ@#12EWvSGoM1DNKjso05oHqqQaz5|4w&|R7?0%B=T`mCXONk1K`W2g^2C+-aPp8&JZ8$sB@Xn)0mBQ7kM&&_Loz}xUjY(K%=U@oLU8K=jbI; zL)wVICT&sBM3Fcq1WKxk#;&1uAs?5p0mp53{`ZcZIe_6z1kyDA&EAx0qK_Czo=57V z+7<7`7;eMj>c)G%Q~iH(bqyzcJF=t&3+B7!NPm$Bf5 zoaeL(A7Pecpc&=}e(G%z979V9{X!(un$UwjRSI!DPu9^4Tam>=0BTheBmtsz<#W*| z%Z*z6w;)iS<2@GAH|rpY{5B#0iBi+D=*!?}FhU%UX#Lf{YvSF*29Fc7HN?*Nj}Bec z{(O}O29T7@_uwyFTy-yNVEY=;mCo>7R5vOCVP*4qB0$~%Ib*C9ONaf@iZ*r?ln1^I zhOPmS?`G zE}@gcx*mvqv{D#PW0hE~mco(pE7Ws6-Y(OC)a+Kye)7?NmX^M|NC?IQk@2~H`N~Fn zz|TJ)uiDApg$t?6C> zIuIznv;l-XugQMXGs)6Y5&UtnGVGuSn{!=O1gk3Hz>$^)<61B44VJ_E-7gKUX8A#)Z!t76G*V$Io&$FLVjg>7^Pqt-;_<} zVKcQ$aVC~uHxZOuzdzHCzv;|i2D}tAg#3wQFo{6lFXQ5A!3GSC#5DP!#-E9UFH4ZA zo|1|t?DZE11;-R5aBp#KcE$w7kUI5HZGA^c z=o_LcIHqE>e5ZIDe`>pUy!7KN@{fc*k=vgySz&v((T11XLbh(sr|o;odxqn~KZo7- zI6u#G&#BK85Jtfd0Fd)6gs^AX25(5>F|9%nOV62Z>7N{5+1w-r%NUWve= z`-^4(PWf*0aYUCn*>t#x3EpxW zX5Qb=X+N|sv-Bp8GV(iUZ!R2fU5EcDh86X(UWhY|10*4zdrOO*o z(cdz#Z=*!Kz6@_Y;LTVwm;Uw?x9mDcJ!pFtxZQeE@poP4NjO46eXg3$yX)dnu~9gT zv}<*r4hbS-t9t<$SJbI0h&Xwdkl_1(g@w$FC}DJvwe=VQN8#?)3^@*nXbSRXQAT=3 zG|*}mL$32v@Oz2QuTdq+cS7~)>D6?(JHt#VhiBG!u~1zB$3t?Op`4}!l)<=Ogd@rq z*FK-J{l4G{J&r)KPk$B@tn#qPf3ppLICZ{xFd?d!3wv9t1P>aJl`)q97K*jU*?H;> zFZkE_IljV$vi)ntZE(-i0tm9^?{TM z)m2MM4yDA%M9#xMZ`Fnzm)%9C%j}@3JShtLk?E_C|1wej)CFHBI=YQ+m3C*-1tn3N z13!hy4?^kJU%jch_reho%>Y&%PPCNIO}#AQSTX?wG!W~x;k7t2d0AdA=hWk|g`d`E6QCbJ|0e5RktOSjC1y>H zPd)bbW4XrzgTLTlJCCKZ-w#&9C*4XSmgI+t(b3XL; z9Uh!IlYtpLMbMaCP_O*K zKPFKs$0F8y#7avoX7+EeVr4r1)Ufd7M#gVZrPRMEsnb76lBfGMb856uTg6LyEknB< z7?#mRJ%^d23knNL0_zu=1h6 zxwRlZI|yO3fHFf)<|nR%SY?FaiO@01oAvkOWPt3D0PIKQBV-zQMs3E5v&;;H+x zq>AUC+Wn!A_{O|l@?xdmXm!&gC<^%uaIg>F2^I}BC)$z!BuGzDL-YGeY*c8Gv6*Yo zh@>H#&=cgelDSFP^}yV4c~x(*B2dBy;>*qnpWjB2l6oJIllCjlQ0Qu!^m3kx2aZolj?OM;z1XiwF#(l-+m$84P1deIAE_0vb+8kA;1ko-abTewsa$ zB`ckDNLcV}C;^?BG0ba8+@5;quN_l@dXQfGKd1kC^7n7LVW|pu<}bky(KtA`>sA$k z-t~rZTK|zM5n{RVHDrG$dHXD{EAU99Qh?Vj8A`FC7Bp8iVFspicC{ zbsF3!f@7#zOar@aV{OUV0?2cQPy9bP9ysjT;12K-_6RTr4|V}KtIQ8k9`az*1&V|l9b}}-#DLk z_6qHhTSBox1oMt^$2g%GcWJ-sF<0h_5fl_hE_ww?sgvdEHlc4heEqMg;4FAD@^uu? z7wv1wb(?I|JR3Xr$*)gW?9C+H2n4*$j^ws2(+c?7$RroNO`W)PUq?~@@Z*O1Ki%+x zdV(lc$V(uwcQ8QT3}WIR+^ADy?oyk3w^gO*#6+Z4GSgdxHW1Y7aE1$-hLRyI&!JLd zXppYHT$&6)yfBNu+6fJPOfESMV`XQKxxZ@DHo{aB7eT_Xf+V>JI^u2B9Y?3T>`o(k zoXrqBgYTFN3KkONTMN;K#N|w-HfF00Zr_ihuZr8**^z-f&OSulE41{fN9QVtN^yCJ z$zN6Ggm$BHvh`=2UHQZEO#19vAs%3x?=r|*OXDccW3%<|M)=U><*|H`KYKOzIM?KT zN<3T2I@tBRxp}~w*JF}HT-s<{i3PCJ#aRq;&mZy8fCew_QWD6c@gY8JK0O6P1?8;KjzX`*R<7X?7 zTT<^<<#f+evr3UiGLXyr|ECt#7e>9>?z2@;y1SVeO9}T;5ME+F!-$O9oc{KzA03^r zt(Yx8`-eXwvPv#M$9;Hm|3$*RcyLzq_A75ff^GN-L?m>@Dl*LVkcK+Uha?U09lbdx z!_8SFd1QjAO>2!(4)&&yfB{4{rz6AIWCsbfx>z?^Y=@gG!AhvH*Dr0QZ&R~Swa`@l zymk+T-rb6{8g6&nmtBeb!yO5~4V%u7x$?%&sb48{5>bN>ip|WNZwGgaE#Pdz*sZM0 zCz5Hgmb9IhrRW_{aWf2MQiP-IH8u5)Yx1#%g!g~#jLv&M`4pa1esJ(8^Or<%T|JDC zm&N4+@mUfl{%Z z@XEfiFlqd5(RcF_GvyA3b2fmNPej76QEoWxy#0T=ti1t3|#O$OiGEvDg5fT zO`dL18&3@MK~I(onAEx(ZbLsBkc>?)N`Y74aQOa*Yu6g`6jV`i!QDDGeh~_$=xD$n zNg1}1Y*&fZ=48vTsC}&o&?SiiF?7cNG&Uq9r$+`FL8!Q@iZwWG)BhaFz7AeIK){d0 z3fA3Teos?4gVx*|6t$02di4rKAryl?4MY&X9$yb$*bw7li1IJFc6KNv7W93oT3%k} zDG_^f|MpNM^Si&R@W9akFwJoUU{Peh3 zXSAA^F{B@7@k=$&kFE|pnnJ=2iY`zA)Jig3CUie-oV@g~Xm4jj$%^o_yA~ghhBnju z#!Ik*kE%&aNF#g2DZGOZ`{Eg`E@39so(BcnOptdsEp2l?Ja#`VH7eDo#jx2+unC8j zui(7~*@WwFO#<=db@J!H!w>s4=}Jf-OEJ*H_36<$8J19pfs7;owTJ?%!ZG~5-4@6v zSZBazSs?_ac=`?2f*O`*+#dguN6^tpD?B00t2CfDj8Zj6;}B2Z(H)f*%5oNYJKx>E z7b$0}E)P~7DfC=IDft`c%k9Rk*j}l_{g)GwSKJL!lzPXjR*}TflCpETX*YkPP1oe| zOgHLKKkFq1uSN6+l0L;*`pzh1#%s&JQ&s^@fSw-=?_1tPU{)Q1OEBW~#YkNf(LJ8H zT2hh}ww9mrcJhZtsllqIktK(i1usp#1&@XwZ!9KpdQJZK@9TiW%fX2VVPs$sXi+vl znm;cyE#Xrx##%%Z{?gx{x%rojA3oeLp@w`>@WvmK(?8k7L!|WKnJj0CeyeNyQ;FBv zfK}rMgJ6VED7-PPtYPO>&b9zyA&M)Tfdsqfvs6J@69EViZN<2l91qx2U|}H_pb`%b zw!z0g^2icsBsO=%+}vDHK?1_18Ah3-B%C3V?0Mobt85k3L0GG916(Qygq0#MC9cWu zI;vKQJIPE`LDd3lQ>qD`G%X(<8}l6fU9QA{Znw}tPh+u_DM-b&8mG;Lni?m1Sac7S zu7d^6B^$pS8%Dp$WIIPkjZ}wv2}P`6)DIb!_@;2aL^h9_JY!KK-QM*{ ztiuz?`cwid$n(zQ1e;(+ieT2rq*l({nT`^AI4lu@ zO*)Fy44o|L$8}OohuUhCPKYtBj+Z=1@ZYNVdruZf&v+-;bm%o&{Z*1nI9#qrU;3KT z`AeO^I@Q9%ujT9xV&Wh^nuJp_(e0c*?&CB@lB%t_xe<+j(MqrS*@J(Ls~YQ(o14Q) z#(8(%$mAsk_14pzM9;AO+2Seif`;N72Swp&_gXno=ww)UZC6NM0)?bQrCb$w=k@i$ z^1=act(MM~l(>kDk`-jczH#wl%^BQ3U1Nmvdwp|k2Y-sOh3V1N z*y^Ab(BuP~qj^k@d}Y}Jv7U-{=R--z zH5~$tk$~799Fei4k}WQ^_9w)kpa=!HPnUnIkjVX(yS>1y3UzS~S=$ zDagr0gQ5Q6Y1QBRnkd1jE$Sc?$(&*bH=LG zVq?*}?%fHG%-{Xso6&S}c6Xt)6J{OS@;#SV5e-IRoxXP6%_R-nYvtwT&RmGR2on^P z9)Bt+{ZVrFF2;AqG63!85QGI8Y?Lgf{z!|F^9_JGd!B*{4!0gFQ3hx<^9}BA)5bDG z?`;0EtPFg<^*&1|Gzt8?_ja`~1b#tPAoUsT$$f@7aiNq)pKTU=^V-2n(D;5G!69%9 zGhc%y45u~4r{`L+Tq?wD1!88hXsbl=yIXCq-vIR`-LatR3I54#^HtCy6T(qzAiays zEtV>un!1jT#Su0HZW;@_cBM&vJr2b+=k2iu==`9?5x6{1&#JZ(*SZYMpyGH~ZjVSM_!<&CwZxZ4KmyQ#r@ zd`CDVFbKuzez6q&)3~f%8ipe=q}-Op-t>qD;HXtg4TvpSgp*e(!#D-%W{;~s$|}ln zIk-2m@|@RBT?**F%Kh8^5{*B^#7e-yEzz0MYt#2o+alnAuE~r`fD?3MGI^~najHc& zQK(-l8{hT00^hd+oxhzgFDEpl!3`v)CQa|ApaAd$b~%=Qk^}c!8w|soJzEaXQ=QRf zTk~edJn}y6d*cUovuF1X)maOB{);}bb@C=x)>oSlX(E6iQR!RM42w2O4xwv`_1;*2 zP}aFS4cBf-1xc(nSgIZn5z&Y zJS|uTRqW*H@mO=bj#5^4xUJjxvmkFhe>NGUeFa<1D#10t<$e=rSEFbDsva$!!hrHc z)%~&@D++p;0Idi})UJIa5N?(K;oLEfK1aC9WH=b{sqU z7a-tC9R)5=5xBMgX2SUsRqJtF&07f!`yBkcyKLT&8oabw7?S#=_C&0NDHZ2v-BnBe~}5Hn2C#nf{ag=^6kwHg1PMiS5m$l%6fJ%Fcerryh3)T zx;$AUJPt5Gx*TR?@GuzSSZTXY0J2o!%;v^xAbtX@x&*yXPSFPvPP<-zkeIkUDuu6C zxX!Ai86Y9)xWEPKSs2whPxqcf%})0IO^iYG9t;Oi445k_ILt0KAHw&dj#^F@LMOV) z*)U;?4>vclMZQ@9gJ9_6oDRg~d6${FSF!U?SYSXh8L4C;<(M3E^7{P(wiq4W#?0U@ zTF$u9)xXdosC&#$b6v?!SoBf62?Oir=5R`wO7X(95ta{`SQ~^ShsXBMNLZ0vCK$9d zo!J?uPK04qMiBGhm|kPpd*HrzNEr*I`IXJ}TKym%-b6nIRiT*dVi-W!h;OX6t9gb`QrT09q`4Em2Z^qgYdK@9T z16gE((N>1VyPUDeJWaIr>GqId(Wg6FK;#E*m6;2^9~s-s=?y4V0bE);Zx_#S4(hlz zhmZ^}@Eh{wpo23pxXOzH9}~{JC5*JRUfLWb;AJp8{VCte;BPL;P_-d0)mJcf!|S}; zAzN;B&NHYX43CU#B@*$!Bdr#^4$@_9ckfZY`~#K@l8Q6M*2~YWgM3Lr0CHJHK7U~^ z--hGr%3c8`3lP2^K~pnQi?a!LR>9uo!-@=iA(wo-HcO~(&^3!d0p>D|X*6JC{KXe5 z*N%ag>{pXhS`4_m3NigHVlRS}>55~7Vhpklk-17IdP+zH#=`Nlt@o=0U%yiC@^()m zGH@5*3rgbR3`|?8%_1uPow+{oyFG;^FxAmklrv5a_u^sWy=6Ow_O1XpW6i)xd# z?JFWcHWSNbM}s>%pi9IB!By~!Z~)-%ju38C2#VfgpYm0axo+(!2A*+bQ*q0q;arbJA)v%f>~H+u&k8*UpyJn>b_!(;L5c zYcsrO5r=kc4Ds2qeIe$co*wFey8Fu8Z#zBCJQ?-QbGCrWYm#&sfVXOc$pZLJ*PH2eN03Em-0rWe=($z@)0&pg@A%HIIE9+mrHSGhULjZ3*&Yda z98JpaH)S|3G?CXnf5!C5jnrg-{sec0220M@daaJMYw!<^vKr-m`}Xjuv2&fg%Al1U zOU(FogPS_}j~o(p*mOJK!PNsET=Vqw^oNy|7M*ueD4^=Cg8IF6?c>J_4jO~zfpay4 zaFt;eIZO2?_s2*+_d}uWXSC(Hg|Fka=OLk5cN1M~cdoZ^cPy`oKA5$snt0l=(e=Dfu~R5T6r6oE~yW6qb|@^t3c$6K&iE=0sijw9-|cFxh9MY;~h z-5p_CAsUPgTr-K%$xp(*o-&EXIpHdyI1*9Vmk-Rkz+?b|gmWfN{-1$F)Di&7{Aaw$ zI}Hcy`*%Parl;7yk&0f|Y@9JcWutt=!3zcNmf + + +image/svg+xml \ No newline at end of file diff --git a/py/PoC.py b/py/PoC.py index 76223964..a80e2880 100644 --- a/py/PoC.py +++ b/py/PoC.py @@ -405,6 +405,8 @@ def HandleConfiguration(self, args): nxt = True except SkipConfigurationException: break + except ConfigurationException: + raise except ExceptionBase as ex: print(" {RED}FAULT:{NOCOLOR} {0}".format(ex.message, **Init.Foreground)) diff --git a/py/ToolChains/GHDL.py b/py/ToolChains/GHDL.py index 69f6d021..91b176dd 100644 --- a/py/ToolChains/GHDL.py +++ b/py/ToolChains/GHDL.py @@ -310,7 +310,7 @@ class SwitchGHDLWaveform(metaclass=LongValuedFlagArgument): _name = "wave" class SwitchWaveformOptionFile(metaclass=LongValuedFlagArgument): - _name = "read-opt-file" # requires GHDL update + _name = "read-wave-opt" # requires GHDL update RunOptions = CommandLineArgumentList( SwitchIEEEAsserts, diff --git a/py/ToolChains/Git.py b/py/ToolChains/Git.py index 07e14b72..6a2bfc48 100644 --- a/py/ToolChains/Git.py +++ b/py/ToolChains/Git.py @@ -50,7 +50,8 @@ from Base.Exceptions import PlatformNotSupportedException, CommonException from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException, SkipConfigurationException -from Base.Executable import Executable, ExecutableArgument, CommandLineArgumentList, CommandArgument, LongFlagArgument, ValuedFlagArgument, StringArgument +from Base.Executable import Executable, ExecutableArgument, CommandLineArgumentList, CommandArgument, LongFlagArgument, ValuedFlagArgument, StringArgument, \ + LongValuedFlagArgument, LongTupleArgument from Base.ToolChain import ToolChainException @@ -86,9 +87,13 @@ def __init__(self, host): def ConfigureForAll(self): try: - self._ConfigureInstallationDirectory() - binPath = self._ConfigureBinaryDirectory() - self.__WriteGitSection(binPath) + if (not self._AskInstalled("Is Git installed on your system?")): + self.ClearSection() + else: + self._host.PoCConfig[self._section]['Version'] = self._template[self._host.Platform][self._section]['Version'] + self._ConfigureInstallationDirectory() + binPath = self._ConfigureBinaryDirectory() + self.__WriteGitSection(binPath) except ConfigurationException: self.ClearSection() raise @@ -126,7 +131,6 @@ def _GetDefaultInstallationDirectory(self): gitPath = binaryDirectoryPath / "git.exe" if gitPath.exists(): return binaryDirectoryPath.parent.as_posix() - raise GitException("No Git installation found.") elif (self._host.Platform in ["Linux", "Darwin"]): try: name = check_output(["which", "git"], universal_newlines=True).strip() @@ -161,7 +165,7 @@ def __WriteGitSection(self, binPath): # get version and backend output = check_output([str(gitPath), "--version"], universal_newlines=True) version = None - versionRegExpStr = r"^git version (\d\.\d\.\d+).*" + versionRegExpStr = r"^git version (\d+\.\d+\.\d+).*" versionRegExp = re_compile(versionRegExpStr) for line in output.split('\n'): if version is None: @@ -325,6 +329,20 @@ def GetGitRevParse(self): return git + def GetGitRevList(self): + git = GitRevList(self._platform, self._dryrun, self._binaryDirectoryPath, logger=self._Logger) + git.Clear() + git.RevListParameters[GitRevList.Command] = True + + return git + + def GetGitDescribe(self): + git = GitDescribe(self._platform, self._dryrun, self._binaryDirectoryPath, logger=self._Logger) + git.Clear() + git.DescribeParameters[GitDescribe.Command] = True + + return git + def GetGitConfig(self): git = GitConfig(self._platform, self._dryrun, self._binaryDirectoryPath, logger=self._Logger) git.Clear() @@ -414,6 +432,98 @@ def Execute(self): return output +class GitRevList(GitSCM): + def Clear(self): + super().Clear() + for param in self.RevListParameters: + # if isinstance(param, ExecutableArgument): + # print("{0}".format(param.Value)) + # elif isinstance(param, NamedCommandLineArgument): + # print("{0}".format(param.Name)) + if (param is not self.Command): + # print(" clearing: {0} = {1} to None".format(param.Name, param.Value)) + self.RevListParameters[param] = None + + class Command(metaclass=CommandArgument): + _name = "rev-list" + + class SwitchTags(metaclass=LongFlagArgument): + _name = "tags" + + class SwitchMaxCount(metaclass=LongValuedFlagArgument): + _name = "max-count" + + RevListParameters = CommandLineArgumentList( + Command, + SwitchTags, + SwitchMaxCount + ) + + def Execute(self): + parameterList = self.Parameters.ToArgumentList() + parameterList += self.RevListParameters.ToArgumentList() + self.LogVerbose("command: {0}".format(" ".join(parameterList))) + + if (self._dryrun): + self.LogDryRun("Start process: {0}".format(" ".join(parameterList))) + return + + try: + self.StartProcess(parameterList) + except Exception as ex: + raise GitException("Failed to launch Git.") from ex + + # FIXME: Replace GetReader with a shorter call to e.g. GetLine and/or GetLines + output = "" + for line in self.GetReader(): + output += line + + return output + +class GitDescribe(GitSCM): + def Clear(self): + super().Clear() + for param in self.DescribeParameters: + # if isinstance(param, ExecutableArgument): + # print("{0}".format(param.Value)) + # elif isinstance(param, NamedCommandLineArgument): + # print("{0}".format(param.Name)) + if (param is not self.Command): + # print(" clearing: {0} = {1} to None".format(param.Name, param.Value)) + self.DescribeParameters[param] = None + + class Command(metaclass=CommandArgument): + _name = "describe" + + class SwitchTags(metaclass=LongTupleArgument): + _name = "tags" + + DescribeParameters = CommandLineArgumentList( + Command, + SwitchTags + ) + + def Execute(self): + parameterList = self.Parameters.ToArgumentList() + parameterList += self.DescribeParameters.ToArgumentList() + self.LogVerbose("command: {0}".format(" ".join(parameterList))) + + if (self._dryrun): + self.LogDryRun("Start process: {0}".format(" ".join(parameterList))) + return + + try: + self.StartProcess(parameterList) + except Exception as ex: + raise GitException("Failed to launch Git.") from ex + + # FIXME: Replace GetReader with a shorter call to e.g. GetLine and/or GetLines + output = "" + for line in self.GetReader(): + output += line + + return output + class GitConfig(GitSCM): def Clear(self): super().Clear() diff --git a/py/ToolChains/PoC.py b/py/ToolChains/PoC.py index 5ccc2a96..38777172 100644 --- a/py/ToolChains/PoC.py +++ b/py/ToolChains/PoC.py @@ -47,6 +47,7 @@ from subprocess import check_output, check_call, CalledProcessError from Base.Configuration import Configuration as BaseConfiguration +from ToolChains.Git import Git class Configuration(BaseConfiguration): @@ -55,7 +56,7 @@ class Configuration(BaseConfiguration): _template = { "ALL": { "INSTALL.PoC": { - "Version": "1.0.0", + "Version": "1.1.0", "InstallationDirectory": None }, "SOLUTION.Solutions": {} @@ -63,13 +64,25 @@ class Configuration(BaseConfiguration): } def ConfigureForAll(self): - try: - latestTagHash = check_output(["git", "rev-list", "--tags", "--max-count=1"], universal_newlines=True).strip() - latestTagName = check_output(["git", "describe", "--tags", latestTagHash], universal_newlines=True).strip() - latestTagName = latestTagName - self._host.LogNormal(" PoC version: {0} (found in git)".format(latestTagName)) - self._host.PoCConfig['INSTALL.PoC']['Version'] = latestTagName - except CalledProcessError: + success = False + if (len(self._host.PoCConfig['INSTALL.Git']) != 0): + try: + binaryDirectoryPath = Path(self._host.PoCConfig['INSTALL.Git']['BinaryDirectory']) + git = Git(self._host.Platform, self._host.DryRun, binaryDirectoryPath, logger=self._host.Logger) + gitRevList = git.GetGitRevList() + gitRevList.RevListParameters[gitRevList.SwitchTags] = True + gitRevList.RevListParameters[gitRevList.SwitchMaxCount] = 1 + latestTagHash = gitRevList.Execute().strip() + gitDescribe = git.GetGitDescribe() + gitDescribe.DescribeParameters[gitDescribe.SwitchTags] = latestTagHash + latestTagName = gitDescribe.Execute().strip() + self._host.LogNormal(" PoC version: {0} (found in git)".format(latestTagName)) + self._host.PoCConfig['INSTALL.PoC']['Version'] = latestTagName + success = True + except CalledProcessError: + pass + + if not success: print("WARNING: Can't get version information from latest git tag.") pocVersion = self._template['ALL']['INSTALL.PoC']['Version'] self._host.LogNormal(" PoC version: {0} (found in default configuration)".format(pocVersion)) @@ -79,27 +92,6 @@ def ConfigureForAll(self): self._host.LogNormal(" Installation directory: {0!s} (found in environment variable)".format(pocInstallationDirectory)) self._host.PoCConfig['INSTALL.PoC']['InstallationDirectory'] = pocInstallationDirectory.as_posix() - def __CheckForGit(self): - try: - check_call(["git", "--version"]) - return True - except OSError: - return False - - def __IsUnderGitControl(self): - try: - response = check_output(["git", "rev-parse", "--is-inside-work-tree"], universal_newlines=True).strip() - return (response == "true") - except OSError: - return False - - def __GetCurrentBranchName(self): - try: - response = check_output(["git", "rev-parse", "--abbrev-ref", "HEAD"], universal_newlines=True).strip() - return response - except OSError: - return False - # LOCAL = git rev-parse @ # PS G:\git\PoC> git rev-parse "@" # 9c05494ef52c276dabec69dbf734a22f65939305 diff --git a/py/ToolChains/__init__.py b/py/ToolChains/__init__.py index 2d8e78a8..d4b087ef 100644 --- a/py/ToolChains/__init__.py +++ b/py/ToolChains/__init__.py @@ -64,8 +64,8 @@ Configurations = [ - PoC_Configuration, Git_Configuration, + PoC_Configuration, # Aldec products Aldec_Configuration, ActiveHDL_Configuration, diff --git a/sim/mem/lut/lut_Sine_tb.wdo b/sim/mem/lut/lut_Sine_tb.wdo new file mode 100644 index 00000000..4385dbcb --- /dev/null +++ b/sim/mem/lut/lut_Sine_tb.wdo @@ -0,0 +1,26 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /lut_sine_tb/Clock +add wave -noupdate /lut_sine_tb/lut_in +add wave -noupdate -format Analog-Step -height 74 -max 127.0 /lut_sine_tb/lut_Q1_out +add wave -noupdate -format Analog-Step -height 74 -max 127.0 /lut_sine_tb/lut_Q2_out +add wave -noupdate -format Analog-Step -height 74 -max 127.0 -min -127.0 -radix decimal /lut_sine_tb/lut_Q3_out +add wave -noupdate -format Analog-Step -height 74 -max 127.0 -min -127.0 -radix decimal /lut_sine_tb/lut_Q4_out +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {490000000 fs} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 164 +configure wave -valuecolwidth 39 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 fs} {10899 ns} diff --git a/src/misc/sync/sync_Strobe.vhdl b/src/misc/sync/sync_Strobe.vhdl index 5a076969..b7a58471 100644 --- a/src/misc/sync/sync_Strobe.vhdl +++ b/src/misc/sync/sync_Strobe.vhdl @@ -19,6 +19,9 @@ -- .. ATTENTION:: -- Use this synchronizer only for one-cycle high-active signals (strobes). -- +-- .. image:: ../../../_static/misc/sync/sync_Strobe.svg +-- :target: ../../../_static/misc/sync/sync_Strobe.svg +-- -- Constraints: -- This module uses sub modules which need to be constrained. Please -- attend to the notes of the instantiated sub modules. diff --git a/src/sort/sortnet/sortnet_BitonicSort.vhdl b/src/sort/sortnet/sortnet_BitonicSort.vhdl index daa1a800..cb4641fd 100644 --- a/src/sort/sortnet/sortnet_BitonicSort.vhdl +++ b/src/sort/sortnet/sortnet_BitonicSort.vhdl @@ -10,6 +10,9 @@ -- ------------------------------------- -- This sorting network uses the *bitonic sort* algorithm. -- +-- .. image:: ../../../_static/sort/sortnet/sortnet_BitonicSort.svg +-- :target: ../../../_static/sort/sortnet/sortnet_BitonicSort.svg +-- -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany From 407e8705157ec227de28372772a9e00b6173d558 Mon Sep 17 00:00:00 2001 From: Martin Zabel Date: Thu, 10 Nov 2016 09:02:55 +0100 Subject: [PATCH 19/97] Updated documentation for: SDRAM controller, PoC.Mem namespace and its sub-namespaces. --- docs/PoC/mem/ddr2/index.rst | 2 +- docs/PoC/mem/ddr3/index.rst | 2 +- docs/PoC/mem/index.rst | 4 - docs/PoC/mem/is61lv/index.rst | 8 -- docs/PoC/mem/is61nlp/index.rst | 8 -- docs/PoC/mem/lut/index.rst | 8 +- docs/PoC/mem/ocram/index.rst | 2 +- docs/PoC/mem/ocrom/index.rst | 30 +++---- docs/PoC/mem/sdram/index.rst | 38 ++++++++- docs/PoC/mem/sdram/sdram_ctrl_de0.rst | 35 +++++--- docs/PoC/mem/sdram/sdram_ctrl_fsm.rst | 36 ++++---- docs/PoC/mem/sdram/sdram_ctrl_phy_de0.rst | 34 +++++--- docs/PoC/mem/sdram/sdram_ctrl_phy_s3esk.rst | 83 ++++++++++++------- docs/PoC/mem/sdram/sdram_ctrl_s3esk.rst | 29 +++++-- docs/References/Interfaces/Memory.rst | 2 +- py/config.entity.ini | 12 +-- py/config.structure.ini | 10 +-- src/mem/README.md | 32 ++----- src/mem/ddr2/README.md | 2 + .../ddr2/ddr2_mem2mig_adapter_Spartan6.files | 10 +++ src/mem/ddr3/README.md | 2 + .../ddr3/ddr3_mem2mig_adapter_Series7.files | 10 +++ src/mem/is61lv/README.md | 3 - src/mem/is61nlp/README.md | 3 - src/mem/lut/README.md | 14 +--- src/mem/ocram/README.md | 20 +---- src/mem/ocrom/README.md | 16 +--- src/mem/sdram/README.md | 35 +------- src/mem/sdram/sdram_ctrl_de0.vhdl | 31 ++++--- src/mem/sdram/sdram_ctrl_fsm.vhdl | 34 ++++---- src/mem/sdram/sdram_ctrl_phy_de0.vhdl | 32 ++++--- src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl | 75 +++++++++++------ src/mem/sdram/sdram_ctrl_s3esk.vhdl | 25 ++++-- 33 files changed, 370 insertions(+), 317 deletions(-) delete mode 100644 docs/PoC/mem/is61lv/index.rst delete mode 100644 docs/PoC/mem/is61nlp/index.rst create mode 100644 src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.files create mode 100644 src/mem/ddr3/ddr3_mem2mig_adapter_Series7.files delete mode 100644 src/mem/is61lv/README.md delete mode 100644 src/mem/is61nlp/README.md diff --git a/docs/PoC/mem/ddr2/index.rst b/docs/PoC/mem/ddr2/index.rst index 6b9ea515..a65f9d39 100644 --- a/docs/PoC/mem/ddr2/index.rst +++ b/docs/PoC/mem/ddr2/index.rst @@ -1,7 +1,7 @@ ddr2 ==== -The namespace `PoC.mem.ddr2` is designated for own implementations of +The namespace ``PoC.mem.ddr2`` is designated for own implementations of DDR2 memory controllers as well as for adapters for vendor-specific implementations. At the top-level, all controllers and adapters provide the same simple memory interface to the user application. diff --git a/docs/PoC/mem/ddr3/index.rst b/docs/PoC/mem/ddr3/index.rst index 3477c198..99902c1a 100644 --- a/docs/PoC/mem/ddr3/index.rst +++ b/docs/PoC/mem/ddr3/index.rst @@ -1,7 +1,7 @@ ddr3 ==== -The namespace `PoC.mem.ddr3` is designated for own implementations of +The namespace ``PoC.mem.ddr3`` is designated for own implementations of DDR3 memory controllers as well as for adapters for vendor-specific implementations. At the top-level, all controllers and adapters provide the same simple memory interface to the user application. diff --git a/docs/PoC/mem/index.rst b/docs/PoC/mem/index.rst index 0bda8857..c9bdd898 100644 --- a/docs/PoC/mem/index.rst +++ b/docs/PoC/mem/index.rst @@ -10,8 +10,6 @@ implementations. * :doc:`PoC.mem.ddr3 ` - DDR3 memory controllers * :doc:`PoC.mem.ddr2 ` - DDR2 memory controllers - * :doc:`PoC.mem.is61lv ` - ISSI - IS61LV SRAM controller - * :doc:`PoC.mem.is61nlp ` - ISSI - IS61NLP SRAM controller * :doc:`PoC.mem.lut ` - Lookup-Table (LUT) implementations * :doc:`PoC.mem.ocram ` - On-Chip RAM abstraction layer * :doc:`PoC.mem.ocrom ` - On-Chip ROM abstraction layer @@ -27,8 +25,6 @@ implementations. ddr3/index ddr2/index - is61lv/index - is61nlp/index lut/index ocram/index ocrom/index diff --git a/docs/PoC/mem/is61lv/index.rst b/docs/PoC/mem/is61lv/index.rst deleted file mode 100644 index cda93f51..00000000 --- a/docs/PoC/mem/is61lv/index.rst +++ /dev/null @@ -1,8 +0,0 @@ - -is61lv -====== - -These are IS61LV entities.... - -.. toctree:: - diff --git a/docs/PoC/mem/is61nlp/index.rst b/docs/PoC/mem/is61nlp/index.rst deleted file mode 100644 index 5a697cca..00000000 --- a/docs/PoC/mem/is61nlp/index.rst +++ /dev/null @@ -1,8 +0,0 @@ - -is61nlp -======== - -These are IS61NLP entities.... - -.. toctree:: - diff --git a/docs/PoC/mem/lut/index.rst b/docs/PoC/mem/lut/index.rst index 0bd93772..6336bbb7 100644 --- a/docs/PoC/mem/lut/index.rst +++ b/docs/PoC/mem/lut/index.rst @@ -2,8 +2,14 @@ lut === -These are Lookup-Table entities.... +The namespace ``PoC.mem.lut`` offers different lookup-tables (LUTs). + +**Entities** + + * :doc:`lut_Sine ` - a Sine implementation with 1,2 or 4 quadrants. + .. toctree:: + :hidden: lut_Sine diff --git a/docs/PoC/mem/ocram/index.rst b/docs/PoC/mem/ocram/index.rst index a824c7ed..68beb118 100644 --- a/docs/PoC/mem/ocram/index.rst +++ b/docs/PoC/mem/ocram/index.rst @@ -2,7 +2,7 @@ ocram ===== -These are On-Chip RAM (OCRAM) entities... +The namespace ``PoC.mem.ocram`` offers different on-chip RAM abstractions. **Package** diff --git a/docs/PoC/mem/ocrom/index.rst b/docs/PoC/mem/ocrom/index.rst index 5a5b0260..f899db1f 100644 --- a/docs/PoC/mem/ocrom/index.rst +++ b/docs/PoC/mem/ocrom/index.rst @@ -2,36 +2,26 @@ ocrom ===== -These are On-Chip ROM (OCROM) entities.... +The namespace ``PoC.mem.ocrom`` offers different on-chip ROM abstractions. -# Namespace `PoC.mem.ocrom` +**Package** -The namespace `PoC.mem.ocrom` offers different on-chip ROM abstractions. +The package PoC.mem.ocrom holds all component declarations for this namespace. +.. code-block:: VHDL -## Package(s) + library PoC; + use PoC.ocrom.all; -The package [`ocrom`][ocrom.pkg] holds all component declarations for this namespace. -```VHDL -library PoC; -use PoC.ocrom.all; -``` - - -## Entities - - - [`ocrom_sp`][ocrom_sp] is a on-chip RAM with a single port interface. - - [`ocrom_dp`][ocrom_dp] is a on-chip RAM with a dual port interface. - - - [ocrom.pkg]: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocrom/ocrom.pkg.vhdl - [ocrom_sp]: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocrom/ocrom_sp.vhdl - [ocrom_dp]: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocrom/ocrom_dp.vhdl +**Entities** + - :doc:`ocrom_sp ` is a on-chip RAM with a single port interface. + - :doc:`ocrom_dp ` is a on-chip RAM with a dual port interface. .. toctree:: + :hidden: ocrom_sp ocrom_dp diff --git a/docs/PoC/mem/sdram/index.rst b/docs/PoC/mem/sdram/index.rst index eee9bb1b..4c2bdef1 100644 --- a/docs/PoC/mem/sdram/index.rst +++ b/docs/PoC/mem/sdram/index.rst @@ -2,7 +2,43 @@ sdram ===== -These are SDRAM entities.... +The namespace ``PoC.mem.sdram`` offers components for the access of external SDRAMs. +A common finite state-machine is used to address the memory via banks, rows and +columns. Different physical layers are provide for the single-data-rate (SDR) or +double-data-rate (DDR, DDR2, ...) data bus. One has to instantiate the specific +module required by the FPGA board. + +SDRAM Controller for the Altera DE0 Board +----------------------------------------- + +The module :doc:`sdram_ctrl_de0 ` combines the finite state machine +:doc:`sdram_ctrl_fsm ` and the DE0 specific physical layer +:doc:`sdram_ctrl_phy_de0 `. It has been tested with the +IS42S16400F SDR memory at a frequency of 133 MHz. A usage example +is given in PoC-Examples_. + + +SDRAM Controller for the Xilinx Spartan-3E Starter Kit (S3ESK) +-------------------------------------------------------------- + +The module :doc:`sdram_ctrl_s3esk ` combines the finite state +machine :doc:`sdram_ctrl_fsm ` and the S3ESK specific physical layer +:doc:`sdram_ctrl_phy_s3esk `. It has been tested with the +MT46V32M16-6T DDR memory at a frequency of 100 MHz (DDR-200). A usage +example is given in PoC-Examples_. + +*Note*: See also :doc:`PoC.xil.mig ` for board specific memory controller +implementations created by Xilinx's Memory Interface Generator (MIG). + + + +.. _PoC-Examples: https://github.com/VLSI-EDA/PoC-Examples .. toctree:: + :hidden: + sdram_ctrl_fsm + sdram_ctrl_de0 + sdram_ctrl_phy_de0 + sdram_ctrl_s3esk + sdram_ctrl_phy_s3esk diff --git a/docs/PoC/mem/sdram/sdram_ctrl_de0.rst b/docs/PoC/mem/sdram/sdram_ctrl_de0.rst index a0b80eda..05e2bdca 100644 --- a/docs/PoC/mem/sdram/sdram_ctrl_de0.rst +++ b/docs/PoC/mem/sdram/sdram_ctrl_de0.rst @@ -3,23 +3,34 @@ sdram_ctrl_de0 ############## Complete controller for ISSI SDR-SDRAM for Altera DE0 Board. -SDRAM Device: IS42S16400F - -CLK_PERIOD = clock period in nano seconds. All SDRAM timings are -calculated for the device stated above. -CL = cas latency, choose according to clock frequency. -BL = burst length. +SDRAM Device: IS42S16400F -Command, address and write data is sampled with clk. +Configuration +************* + ++------------+----------------------------------------------------+ +| Parameter | Description | ++============+====================================================+ +| CLK_PERIOD | Clock period in nano seconds. All SDRAM timings are| +| | calculated for the device stated above. | ++------------+----------------------------------------------------+ +| CL | CAS latency, choose according to clock frequency. | ++------------+----------------------------------------------------+ +| BL | Burst length. Choose BL=1 for single cycle memory | +| | transactions as required for the PoC.Mem interface.| ++------------+----------------------------------------------------+ Tested with: CLK_PERIOD = 7.5 (133 MHz), CL=2, BL=1. -Read data is aligned with clk. Either process data in this clock -domain, or connect a FIFO to transfer data into another clock domain of your -choice. +Operation +********* + +Command, address and write data is sampled with ``clk``. +Read data is also aligned with ``clk``. -For description on 'clkout' see sdram_ctrl_phy_de0.vhdl. +For description on ``clkout`` see +:doc:`sdram_ctrl_phy_de0 `. Synchronous resets are used. @@ -31,7 +42,7 @@ Synchronous resets are used. :language: vhdl :tab-width: 2 :linenos: - :lines: 77-109 + :lines: 88-120 Source file: `mem/sdram/sdram_ctrl_de0.vhdl `_ diff --git a/docs/PoC/mem/sdram/sdram_ctrl_fsm.rst b/docs/PoC/mem/sdram/sdram_ctrl_fsm.rst index 4db5364f..ff3bd7e9 100644 --- a/docs/PoC/mem/sdram/sdram_ctrl_fsm.rst +++ b/docs/PoC/mem/sdram/sdram_ctrl_fsm.rst @@ -3,12 +3,13 @@ sdram_ctrl_fsm ############## This file contains the FSM as well as parts of the datapath. -The board specific physical layer is defined in another file -sdram_ctrl_phy_*.vhdl +The board specific physical layer is defined in another file. + +Configuration +************* -Generics: ---------- SDRAM_TYPE activates some special cases: + - 0 for SDR-SDRAM - 1 for DDR-SDRAM - 2 for DDR2-SDRAM (no special support yet like ODT) @@ -23,16 +24,19 @@ by the physical interface for DDR interfaces. Furthermore, the memory array is divided into 2**R_BITS rows, 2**C_BITS columns and 2**B_BITS banks. -For example, the MT46V32M16 has 512 Mbit = 8M x 4 banks x 16 bit = -32M cells x 16 bit, with 8K rows and 1K columns. -- A_BITS = log2ceil(32M) = 25 -- D_BITS = 16 -- data-path width of phy on user side: 32-bit because of DDR -- R_BITS = log2ceil(8K) = 13 -- C_BITS = log2ceil(1K) = 10 -- B_BITS = log2ceil(4) = 2 +.. NOTE:: + For example, the MT46V32M16 has 512 Mbit = 8M x 4 banks x 16 bit = + 32M cells x 16 bit, with 8K rows and 1K columns. Thus, the configuration + is: + + - A_BITS = :math:`\log_2(32\,\mbox{M}) = 25` + - D_BITS = 16 + - data-path width of phy on user side: 32-bit because of DDR + - R_BITS = :math:`\log_2(8\,\mbox{K}) = 13` + - C_BITS = :math:`\log_2(1\,\mbox{K}) = 10` + - B_BITS = :math:`\log_2(4) = 2` -Set cas latency (CL, MR_CL) and burst length (BL, MR_BL) according to +Set CAS latency (CL, MR_CL) and burst length (BL, MR_BL) according to your needs. If you have a DDR-SDRAM then set INIT_DLL = true, otherwise false. @@ -52,8 +56,8 @@ specified in number of average refresh periods (specified by T_REFI): INIT_WAIT = ceil(wait_time / clock_period / T_REFI) e.g. INIT_WAIT = ceil(200 us / 10 ns / 700) = 29 -Signals: --------- +Operation +********* After user_cmd_valid is asserted high, the command (user_write) and address (user_addr) must be hold until user_got_cmd is asserted. @@ -74,7 +78,7 @@ The write data must directly connected to the physical layer. :language: vhdl :tab-width: 2 :linenos: - :lines: 120-164 + :lines: 124-168 Source file: `mem/sdram/sdram_ctrl_fsm.vhdl `_ diff --git a/docs/PoC/mem/sdram/sdram_ctrl_phy_de0.rst b/docs/PoC/mem/sdram/sdram_ctrl_phy_de0.rst index 49030a40..d1c05adb 100644 --- a/docs/PoC/mem/sdram/sdram_ctrl_phy_de0.rst +++ b/docs/PoC/mem/sdram/sdram_ctrl_phy_de0.rst @@ -2,22 +2,32 @@ sdram_ctrl_phy_de0 ################## -Physical layer used by module 'sdram_ctrl_de0' +Physical layer used by module :doc:`sdram_ctrl_de0 `. -Instantiates input and output buffer components and adjusts timing for +Instantiates input and output buffer components and adjusts the timing for the Altera DE0 board. -Command signals and write data are sampled with clk. -Read data is also aligned with clk. +Clock and Reset Signals +*********************** -clk : Base clock for command and write data path. -rst : Reset for clk. ++-----------+-----------------------------------------------------------+ +| Port | Description | ++===========+===========================================================+ +|clk | Base clock for command and write data path. | ++-----------+-----------------------------------------------------------+ +|rst | Reset for ``clk``. | ++-----------+-----------------------------------------------------------+ + +Command signals and write data are sampled with ``clk``. +Read data is also aligned with ``clk``. + +Write and read enable (wren_nxt, rden_nxt) must be hold for: + +* 1 clock cycle if BL = 1, +* 2 clock cycles if BL = 2, or +* 4 clock cycles if BL = 4, or +* 8 clock cycles if BL = 8. -Write and read enable (wren_nxt, rden_nxt) must be hold for - 1 clock cycle if BL = 1, - 2 clock cycles if BL = 2, or - 4 clock cycles if BL = 4, or - 8 clock cycles if BL = 8. They must be first asserted with the read and write command. Proper delay is included in this unit. @@ -34,7 +44,7 @@ Synchronous resets are used. Reset must be hold for at least two cycles. :language: vhdl :tab-width: 2 :linenos: - :lines: 79-112 + :lines: 89-122 Source file: `mem/sdram/sdram_ctrl_phy_de0.vhdl `_ diff --git a/docs/PoC/mem/sdram/sdram_ctrl_phy_s3esk.rst b/docs/PoC/mem/sdram/sdram_ctrl_phy_s3esk.rst index e5625bd2..65ebdfdc 100644 --- a/docs/PoC/mem/sdram/sdram_ctrl_phy_s3esk.rst +++ b/docs/PoC/mem/sdram/sdram_ctrl_phy_s3esk.rst @@ -2,39 +2,62 @@ sdram_ctrl_phy_s3esk #################### -Physical layer used by module 'sdram_ctrl_s3esk' +Physical layer used by module :doc:`sdram_ctrl_s3esk `. -Instantiates input and output buffer components and adjusts timing for +Instantiates input and output buffer components and adjusts the timing for the Spartan-3E Starter Kit Board. -Command signals and write data are sampled with clk. - -Read data is aligned with clk_fb90_n. Either process data in this clock +Clock and Reset Signals +*********************** + ++-----------+-----------------------------------------------------------+ +| Port | Description | ++===========+===========================================================+ +|clk | Base clock for command and write data path. | ++-----------+-----------------------------------------------------------+ +|clk_n | ``clk`` phase shifted by 180 degrees. | ++-----------+-----------------------------------------------------------+ +|clk90 | ``clk`` phase shifted by 90 degrees. | ++-----------+-----------------------------------------------------------+ +|clk90_n | ``clk`` phase shifted by 270 degrees. | ++-----------+-----------------------------------------------------------+ +|clk_fb | Driven by external feedback (sd_ck_fb) of DDR-SDRAM clock | +|(on PCB) | (sd_ck_p). Actually unused, just referenced below. | ++-----------+-----------------------------------------------------------+ +|clk_fb90 | ``clk_fb`` phase shifted by 90 degrees. | ++-----------+-----------------------------------------------------------+ +|clk_fb90_n | ``clk_fb`` phase shifted by 270 degrees. | ++-----------+-----------------------------------------------------------+ +|rst | Reset for ``clk``. | ++-----------+-----------------------------------------------------------+ +|rst180 | Reset for ``clk_n`` | ++-----------+-----------------------------------------------------------+ +|rst90 | Reset for ``clk90``. | ++-----------+-----------------------------------------------------------+ +|rst270 | Reset for ``clk270``. | ++-----------+-----------------------------------------------------------+ +|rst_fb90 | Reset for ``clk_fb90``. | ++-----------+-----------------------------------------------------------+ +|rst_fb90_n | Reset for ``clk_fb90_n``. | ++-----------+-----------------------------------------------------------+ + + +Operation +********* + +Command signals and write data are sampled with the rising edge of ``clk``. + +Read data is aligned with ``clk_fb90_n``. Either process data in this clock domain, or connect a FIFO to transfer data into another clock domain of your choice. This FIFO should capable of storing at least one burst (size BL/2) + start of next burst (size 1). -clk : base clock for command and write data path. -clk_n : clk phase shifted by 180 degrees. -clk90 : clk phase shifted by 90 degrees. -clk90_n : clk phase shifted by 270 degrees. - -clk_fb : driven by external feedback (sd_ck_fb) of DDR-SDRAM clock - (sd_ck_p). (Actually unused, just for reference.) -clk_fb90 : clk_fb phase shifted by 90 degrees. -clk_fb90_n : clk_fb phase shifted by 270 degrees. - -rst : Reset for clk. -rst180 : Reset for clk_n. -rst90 : Reset for clk90. -rst270 : Reset for clk270. -rst_fb90 : Reset for clk_fb90. -rst_fb90_n : Reset for clk_fb90_n. - -Write and read enable (wren_nxt, rden_nxt) must be hold for - 1 clock cycle if BL = 2, - 2 clock cycles if BL = 4, or - 4 clock cycles if BL = 8. +Write and read enable (``wren_nxt``, ``rden_nxt``) must be hold for: + +* 1 clock cycle if BL = 2, +* 2 clock cycles if BL = 4, or +* 4 clock cycles if BL = 8. + They must be first asserted with the read and write command. Proper delay is included in this unit. @@ -42,10 +65,10 @@ The first word to write must be asserted with the write command. Proper delay is included in this unit. The SDRAM clock is regenerated in this module. The following timing is -chosen for minimum latency. (Should work up to 100 MHz.) - rising_edge(clk90) triggers rising_edge(sd_ck_p) - rising_edge(clk90_n) triggers falling_edge(sd_ck_p) +chosen for minimum latency (should work up to 100 MHz): +* ``rising_edge(clk90)`` triggers ``rising_edge(sd_ck_p)``, +* ``rising_edge(clk90_n)`` triggers ``falling_edge(sd_ck_p)``. XST options: Disable equivalent register removal. @@ -59,7 +82,7 @@ Synchronous resets are used. Reset must be hold for at least two cycles. :language: vhdl :tab-width: 2 :linenos: - :lines: 104-148 + :lines: 127-171 Source file: `mem/sdram/sdram_ctrl_phy_s3esk.vhdl `_ diff --git a/docs/PoC/mem/sdram/sdram_ctrl_s3esk.rst b/docs/PoC/mem/sdram/sdram_ctrl_s3esk.rst index 4b464ed1..f4bee22a 100644 --- a/docs/PoC/mem/sdram/sdram_ctrl_s3esk.rst +++ b/docs/PoC/mem/sdram/sdram_ctrl_s3esk.rst @@ -3,19 +3,32 @@ sdram_ctrl_s3esk ################ Controller for Micron DDR-SDRAM on Spartan-3E Starter Kit Board. -SDRAM Device: MT46V32M16-6T -CLK_PERIOD = clock period in nano seconds. All SDRAM timings are -calculated for the device stated above. +SDRAM Device: MT46V32M16-6T -CL = cas latency, choose according to clock frequency. -BL = burst length. +Configuration +************* + ++------------+----------------------------------------------------+ +| Parameter | Description | ++============+====================================================+ +| CLK_PERIOD | Clock period in nano seconds. All SDRAM timings are| +| | calculated for the device stated above. | ++------------+----------------------------------------------------+ +| CL | CAS latency, choose according to clock frequency. | ++------------+----------------------------------------------------+ +| BL | Burst length. Choose BL=2 for single cycle memory | +| | transactions as required for the PoC.Mem interface.| ++------------+----------------------------------------------------+ Tested with: CLK_PERIOD = 10.0, CL=2, BL=2. -Command, address and write data is sampled with clk. +Operation +********* + +Command, address and write data are sampled with the rising edge of ``clk``. -Read data is aligned with clk_fb90_n. Either process data in this clock +Read data is aligned with ``clk_fb90_n``. Either process data in this clock domain, or connect a FIFO to transfer data into another clock domain of your choice. This FIFO should capable of storing at least one burst (size BL/2) + start of next burst (size 1). @@ -30,7 +43,7 @@ Synchronous resets are used. :language: vhdl :tab-width: 2 :linenos: - :lines: 76-119 + :lines: 89-132 Source file: `mem/sdram/sdram_ctrl_s3esk.vhdl `_ diff --git a/docs/References/Interfaces/Memory.rst b/docs/References/Interfaces/Memory.rst index 5821e8c3..76eae7bf 100644 --- a/docs/References/Interfaces/Memory.rst +++ b/docs/References/Interfaces/Memory.rst @@ -37,7 +37,7 @@ For example, a 1 KiByte memory with a 32-bit datapath has the following configuration: * 4 bytes per memory word, -* ADDR_BITS=8 because log_2(1 KiByte / 4 bytes) = 8, and +* ADDR_BITS=8 because :math:`\log_2(1\,\mbox{KiByte} / 4\,\mbox{bytes}) = 8`, and * DATA_BITS=32 which is the datapath size in bits. diff --git a/py/config.entity.ini b/py/config.entity.ini index 4e08e0c7..fcccf200 100644 --- a/py/config.entity.ini +++ b/py/config.entity.ini @@ -390,17 +390,13 @@ HDLParameters = CLOCK_FREQ=100MHz; BAUDRATE=115200Bd # PoC.mem # ============================================================================== -# PoC.mem.ddr3 -# ------------------------------------------------------------------------------ -[IP.mem.ddr3.mem2mig_adapter_Series7] -#tb = VHDLTestbench -#[TB.mem.lut.mem2mig_adapter_Series7.tb] - -# PoC.mem.is61lv +# PoC.mem.ddr2 # ------------------------------------------------------------------------------ +[IP.mem.ddr2.mem2mig_adapter_Spartan6] -# PoC.mem.is61nlp +# PoC.mem.ddr3 # ------------------------------------------------------------------------------ +[IP.mem.ddr3.mem2mig_adapter_Series7] # PoC.mem.lut # ------------------------------------------------------------------------------ diff --git a/py/config.structure.ini b/py/config.structure.ini index efedd020..07f10c83 100644 --- a/py/config.structure.ini +++ b/py/config.structure.ini @@ -193,21 +193,19 @@ ft245 = Entity [PoC.lib] [PoC.mem] +ddr2 = Namespace ddr3 = Namespace -is61lv = Namespace -is61nlp = Namespace lut = Namespace ocram = Namespace ocrom = Namespace sdram = Namespace +[PoC.mem.ddr2] +mem2mig_adapter_Spartan6 = Entity + [PoC.mem.ddr3] mem2mig_adapter_Series7 = Entity -[PoC.mem.is61lv] - -[PoC.mem.is61nlp] - [PoC.mem.lut] Sine = Entity diff --git a/src/mem/README.md b/src/mem/README.md index 7a2f75f1..cd035aaa 100644 --- a/src/mem/README.md +++ b/src/mem/README.md @@ -6,27 +6,11 @@ implementations. ## Sub-Namespace(s) - - [`PoC.mem.ddr3`][mem_ddr3] - Adapter and Wrapper for DDR3 controllers - - [`PoC.mem.ddr2`][mem_ddr2] - Adapter and Wrapper for DDR3 controllers - - [`PoC.mem.is61lv`][mem_is61lv] - ISSI - IS61LV SRAM controller - - [`PoC.mem.is61nlp`][mem_is61nlp] - ISSI - IS61NLP SRAM controller - - [`PoC.mem.lut`][mem_lut] - Lookup-Table (LUT) implementations - - [`PoC.mem.ocram`][mem_ocram] - On-Chip RAM abstraction layer - - [`PoC.mem.ocrom`][mem_ocrom] - On-Chip ROM abstraction layer - - [`PoC.mem.sdram`][mem_sdram] - SDRAM controllers - - -## Package - -The package [`PoC.mem`][mem.pkg] holds all component declarations for this namespace. - - - [mem.pkg]: mem.pkg.vhdl - - [mem_ddr3]: ddr3 - [mem_is61lv]: is61lv - [mem_is61nlp]: is61nlp - [mem_lut]: lut - [mem_ocram]: ocram - [mem_ocrom]: ocrom - [mem_sdram]: sdram + - [`PoC.mem.ddr3`](ddr3) - Adapter and Wrapper for DDR3 controllers + - [`PoC.mem.ddr2`](ddr2) - Adapter and Wrapper for DDR3 controllers + - [`PoC.mem.lut`](lut) - Lookup-Table (LUT) implementations + - [`PoC.mem.ocram`](ocram) - On-Chip RAM abstraction layer + - [`PoC.mem.ocrom`](ocrom) - On-Chip ROM abstraction layer + - [`PoC.mem.sdram`](sdram) - SDRAM controllers + +Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/PoC/mem/index.html). diff --git a/src/mem/ddr2/README.md b/src/mem/ddr2/README.md index ee50faf8..8174dc17 100644 --- a/src/mem/ddr2/README.md +++ b/src/mem/ddr2/README.md @@ -4,3 +4,5 @@ The namespace `PoC.mem.ddr2` is designated for own implementations of DDR2 memory controllers as well as for adapters for vendor-specific implementations. At the top-level, all controllers and adapters provide the same simple memory interface to the user application. + +Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/PoC/mem/ddr2/index.html). diff --git a/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.files b/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.files new file mode 100644 index 00000000..2bfa30d0 --- /dev/null +++ b/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.files @@ -0,0 +1,10 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# ============================================================================== +# Note: all files are relative to PoC root directory +# +# Common PoC packages for configuration, synthesis and simulation +include "src/common/common.files" # load common packages + +vhdl poc "src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl" diff --git a/src/mem/ddr3/README.md b/src/mem/ddr3/README.md index 7457cfb2..c305d45a 100644 --- a/src/mem/ddr3/README.md +++ b/src/mem/ddr3/README.md @@ -4,3 +4,5 @@ The namespace `PoC.mem.ddr3` is designated for own implementations of DDR3 memory controllers as well as for adapters for vendor-specific implementations. At the top-level, all controllers and adapters provide the same simple memory interface to the user application. + +Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/PoC/mem/ddr3/index.html). diff --git a/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.files b/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.files new file mode 100644 index 00000000..35d104f3 --- /dev/null +++ b/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.files @@ -0,0 +1,10 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# ============================================================================== +# Note: all files are relative to PoC root directory +# +# Common PoC packages for configuration, synthesis and simulation +include "src/common/common.files" # load common packages + +vhdl poc "src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl" diff --git a/src/mem/is61lv/README.md b/src/mem/is61lv/README.md deleted file mode 100644 index 2db59ad5..00000000 --- a/src/mem/is61lv/README.md +++ /dev/null @@ -1,3 +0,0 @@ -# Namespace `PoC.mem.is61lv` - -*No files published, yet.* diff --git a/src/mem/is61nlp/README.md b/src/mem/is61nlp/README.md deleted file mode 100644 index f0148a10..00000000 --- a/src/mem/is61nlp/README.md +++ /dev/null @@ -1,3 +0,0 @@ -# Namespace `PoC.mem.is61nlp` - -*No files published, yet.* diff --git a/src/mem/lut/README.md b/src/mem/lut/README.md index 8e95b859..b30ca7d5 100644 --- a/src/mem/lut/README.md +++ b/src/mem/lut/README.md @@ -2,16 +2,4 @@ The namespace `PoC.mem.lut` offers different lookup-tables (LUTs). - -## Package(s) - -The package [`PoC.lut`][lut.pkg] holds all component declarations for this namespace. - - -## Entities - - - [`lut_Sine`][lut_Sine] - a Sine implementation with 1,2 or 4 quadrants. - - - [lut.pkg]: lut.pkg.vhdl - [lut_Sine]: lut_Sine.vhdl +Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/PoC/mem/lut/index.html). diff --git a/src/mem/ocram/README.md b/src/mem/ocram/README.md index 9da40b4a..f71bcc4d 100644 --- a/src/mem/ocram/README.md +++ b/src/mem/ocram/README.md @@ -2,22 +2,4 @@ The namespace `PoC.mem.ocram` offers different on-chip RAM abstractions. - -## Package(s) - -The package [`PoC.ocram`][ocram.pkg] holds all component declarations for this namespace. - - -## Entities - - - [`ocram_sp`][ocram_sp] is a on-chip RAM with a single port interface. - - [`ocram_sdp`][ocram_sp] is a on-chip RAM with a simple dual port interface. - - [`ocram_esdp`][ocram_sp] is a on-chip RAM with a extended simple dual port interface. - - [`ocram_tdp`][ocram_sp] is a on-chip RAM with a true dual port interface. - - - [ocram.pkg]: ocram.pkg.vhdl - [ocram_sp]: ocram_sp.vhdl - [ocram_sdp]: ocram_sdp.vhdl - [ocram_esdp]: ocram_esdp.vhdl - [ocram_tdp]: ocram_tdp.vhdl +Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/PoC/mem/ocram/index.html). diff --git a/src/mem/ocrom/README.md b/src/mem/ocrom/README.md index 5b6a46ca..9144b65a 100644 --- a/src/mem/ocrom/README.md +++ b/src/mem/ocrom/README.md @@ -2,18 +2,4 @@ The namespace `PoC.mem.ocrom` offers different on-chip ROM abstractions. - -## Package(s) - -The package [`PoC.ocrom`][ocrom.pkg] holds all component declarations for this namespace. - - -## Entities - - - [`ocrom_sp`][ocrom_sp] is a on-chip RAM with a single port interface. - - [`ocrom_dp`][ocrom_dp] is a on-chip RAM with a dual port interface. - - - [ocrom.pkg]: ocrom.pkg.vhdl - [ocrom_sp]: ocrom_sp.vhdl - [ocrom_dp]: ocrom_dp.vhdl +Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/PoC/mem/ocrom/index.html). diff --git a/src/mem/sdram/README.md b/src/mem/sdram/README.md index 6ff8a28d..c98e79d6 100644 --- a/src/mem/sdram/README.md +++ b/src/mem/sdram/README.md @@ -6,37 +6,4 @@ columns. Different physical layers are provide for the single-data-rate (SDR) or double-data-rate (DDR, DDR2, ...) data bus. One has to instantiate the specific module required by the FPGA board. - -## Entities - -#### SDRAM Controller for the Altera DE0 Board - -The module [`sdram_ctrl_de0`][sdram_ctrl_de0] combines the finite state machine -[`sdram_ctrl_fsm`][sdram_ctrl_fsm] and the DE0 specific physical layer -[`sdram_ctrl_phy_de0`][sdram_ctrl_phy_de0]. It has been tested with the -IS42S16400F SDR memory at a frequency of 133 MHz. A [usage example][ex_mem_sdram] -is given in [PoC-Examples][PoCEx]. - - -#### SDRAM Controller for the Xilinx Spartan-3E Starter Kit (S3ESK) - -The module [`sdram_ctrl_s3esk`][sdram_ctrl_s3esk] combines the finite state -machine [`sdram_ctrl_fsm`][sdram_ctrl_fsm] and the S3ESK specific physical layer -[`sdram_ctrl_phy_s3esk`][sdram_ctrl_phy_s3esk]. It has been tested with the -MT46V32M16-6T DDR memory at a frequency of 100 MHz (DDR-200). A [usage -example][ex_mem_sdram] is given in [PoC-Examples][PoCEx]. - -*Note*: See [`PoC.xil.mig`][src_xil_mig] for board specific memory controller -implementations created by Xilinx's Memory Interface Generator (MIG). - - [sdram_ctrl_fsm]: sdram_ctrl_fsm.vhdl - [sdram_ctrl_de0]: sdram_ctrl_de0.vhdl - [sdram_ctrl_phy_de0]: sdram_ctrl_phy_de0.vhdl - [sdram_ctrl_s3esk]: sdram_ctrl_s3esk.vhdl - [sdram_ctrl_phy_s3esk]: sdram_ctrl_phy_s3esk.vhdl - - [src_xil_mig]: ../../xil/mig - - [PoCEx]: https://github.com/VLSI-EDA/PoC-Examples - [ex_mem_sdram]: https://github.com/VLSI-EDA/PoC-Examples/tree/master/src/mem/sdram - +Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/PoC/mem/sdram/index.html). diff --git a/src/mem/sdram/sdram_ctrl_de0.vhdl b/src/mem/sdram/sdram_ctrl_de0.vhdl index 42c2adde..5c048696 100644 --- a/src/mem/sdram/sdram_ctrl_de0.vhdl +++ b/src/mem/sdram/sdram_ctrl_de0.vhdl @@ -9,23 +9,34 @@ -- Description: -- ------------------------------------- -- Complete controller for ISSI SDR-SDRAM for Altera DE0 Board. --- SDRAM Device: IS42S16400F -- --- CLK_PERIOD = clock period in nano seconds. All SDRAM timings are --- calculated for the device stated above. +-- SDRAM Device: IS42S16400F -- --- CL = cas latency, choose according to clock frequency. --- BL = burst length. +-- Configuration +-- ************* -- --- Command, address and write data is sampled with clk. +-- +------------+----------------------------------------------------+ +-- | Parameter | Description | +-- +============+====================================================+ +-- | CLK_PERIOD | Clock period in nano seconds. All SDRAM timings are| +-- | | calculated for the device stated above. | +-- +------------+----------------------------------------------------+ +-- | CL | CAS latency, choose according to clock frequency. | +-- +------------+----------------------------------------------------+ +-- | BL | Burst length. Choose BL=1 for single cycle memory | +-- | | transactions as required for the PoC.Mem interface.| +-- +------------+----------------------------------------------------+ -- -- Tested with: CLK_PERIOD = 7.5 (133 MHz), CL=2, BL=1. -- --- Read data is aligned with clk. Either process data in this clock --- domain, or connect a FIFO to transfer data into another clock domain of your --- choice. +-- Operation +-- ********* +-- +-- Command, address and write data is sampled with ``clk``. +-- Read data is also aligned with ``clk``. -- --- For description on 'clkout' see sdram_ctrl_phy_de0.vhdl. +-- For description on ``clkout`` see +-- :doc:`sdram_ctrl_phy_de0 `. -- -- Synchronous resets are used. -- diff --git a/src/mem/sdram/sdram_ctrl_fsm.vhdl b/src/mem/sdram/sdram_ctrl_fsm.vhdl index 1fa749f1..9184536a 100644 --- a/src/mem/sdram/sdram_ctrl_fsm.vhdl +++ b/src/mem/sdram/sdram_ctrl_fsm.vhdl @@ -9,12 +9,13 @@ -- Description: -- ------------------------------------- -- This file contains the FSM as well as parts of the datapath. --- The board specific physical layer is defined in another file --- sdram_ctrl_phy_*.vhdl +-- The board specific physical layer is defined in another file. +-- +-- Configuration +-- ************* -- --- Generics: --- --------- -- SDRAM_TYPE activates some special cases: +-- -- - 0 for SDR-SDRAM -- - 1 for DDR-SDRAM -- - 2 for DDR2-SDRAM (no special support yet like ODT) @@ -29,16 +30,19 @@ -- Furthermore, the memory array is divided into -- 2**R_BITS rows, 2**C_BITS columns and 2**B_BITS banks. -- --- For example, the MT46V32M16 has 512 Mbit = 8M x 4 banks x 16 bit = --- 32M cells x 16 bit, with 8K rows and 1K columns. --- - A_BITS = log2ceil(32M) = 25 --- - D_BITS = 16 --- - data-path width of phy on user side: 32-bit because of DDR --- - R_BITS = log2ceil(8K) = 13 --- - C_BITS = log2ceil(1K) = 10 --- - B_BITS = log2ceil(4) = 2 +-- .. NOTE:: +-- For example, the MT46V32M16 has 512 Mbit = 8M x 4 banks x 16 bit = +-- 32M cells x 16 bit, with 8K rows and 1K columns. Thus, the configuration +-- is: +-- +-- - A_BITS = :math:`\log_2(32\,\mbox{M}) = 25` +-- - D_BITS = 16 +-- - data-path width of phy on user side: 32-bit because of DDR +-- - R_BITS = :math:`\log_2(8\,\mbox{K}) = 13` +-- - C_BITS = :math:`\log_2(1\,\mbox{K}) = 10` +-- - B_BITS = :math:`\log_2(4) = 2` -- --- Set cas latency (CL, MR_CL) and burst length (BL, MR_BL) according to +-- Set CAS latency (CL, MR_CL) and burst length (BL, MR_BL) according to -- your needs. -- -- If you have a DDR-SDRAM then set INIT_DLL = true, otherwise false. @@ -58,8 +62,8 @@ -- INIT_WAIT = ceil(wait_time / clock_period / T_REFI) -- e.g. INIT_WAIT = ceil(200 us / 10 ns / 700) = 29 -- --- Signals: --- -------- +-- Operation +-- ********* -- -- After user_cmd_valid is asserted high, the command (user_write) and address -- (user_addr) must be hold until user_got_cmd is asserted. diff --git a/src/mem/sdram/sdram_ctrl_phy_de0.vhdl b/src/mem/sdram/sdram_ctrl_phy_de0.vhdl index 50608c78..3ffc7b34 100644 --- a/src/mem/sdram/sdram_ctrl_phy_de0.vhdl +++ b/src/mem/sdram/sdram_ctrl_phy_de0.vhdl @@ -8,22 +8,32 @@ -- -- Description: -- ------------------------------------- --- Physical layer used by module 'sdram_ctrl_de0' +-- Physical layer used by module :doc:`sdram_ctrl_de0 `. -- --- Instantiates input and output buffer components and adjusts timing for +-- Instantiates input and output buffer components and adjusts the timing for -- the Altera DE0 board. -- --- Command signals and write data are sampled with clk. --- Read data is also aligned with clk. +-- Clock and Reset Signals +-- *********************** -- --- clk : Base clock for command and write data path. --- rst : Reset for clk. +-- +-----------+-----------------------------------------------------------+ +-- | Port | Description | +-- +===========+===========================================================+ +-- |clk | Base clock for command and write data path. | +-- +-----------+-----------------------------------------------------------+ +-- |rst | Reset for ``clk``. | +-- +-----------+-----------------------------------------------------------+ +-- +-- Command signals and write data are sampled with ``clk``. +-- Read data is also aligned with ``clk``. +-- +-- Write and read enable (wren_nxt, rden_nxt) must be hold for: +-- +-- * 1 clock cycle if BL = 1, +-- * 2 clock cycles if BL = 2, or +-- * 4 clock cycles if BL = 4, or +-- * 8 clock cycles if BL = 8. -- --- Write and read enable (wren_nxt, rden_nxt) must be hold for --- 1 clock cycle if BL = 1, --- 2 clock cycles if BL = 2, or --- 4 clock cycles if BL = 4, or --- 8 clock cycles if BL = 8. -- They must be first asserted with the read and write command. Proper delay is -- included in this unit. -- diff --git a/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl b/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl index a6555e8d..084ea664 100644 --- a/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl +++ b/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl @@ -8,39 +8,62 @@ -- -- Description: -- ------------------------------------- --- Physical layer used by module 'sdram_ctrl_s3esk' +-- Physical layer used by module :doc:`sdram_ctrl_s3esk `. -- --- Instantiates input and output buffer components and adjusts timing for +-- Instantiates input and output buffer components and adjusts the timing for -- the Spartan-3E Starter Kit Board. -- --- Command signals and write data are sampled with clk. +-- Clock and Reset Signals +-- *********************** -- --- Read data is aligned with clk_fb90_n. Either process data in this clock +-- +-----------+-----------------------------------------------------------+ +-- | Port | Description | +-- +===========+===========================================================+ +-- |clk | Base clock for command and write data path. | +-- +-----------+-----------------------------------------------------------+ +-- |clk_n | ``clk`` phase shifted by 180 degrees. | +-- +-----------+-----------------------------------------------------------+ +-- |clk90 | ``clk`` phase shifted by 90 degrees. | +-- +-----------+-----------------------------------------------------------+ +-- |clk90_n | ``clk`` phase shifted by 270 degrees. | +-- +-----------+-----------------------------------------------------------+ +-- |clk_fb | Driven by external feedback (sd_ck_fb) of DDR-SDRAM clock | +-- |(on PCB) | (sd_ck_p). Actually unused, just referenced below. | +-- +-----------+-----------------------------------------------------------+ +-- |clk_fb90 | ``clk_fb`` phase shifted by 90 degrees. | +-- +-----------+-----------------------------------------------------------+ +-- |clk_fb90_n | ``clk_fb`` phase shifted by 270 degrees. | +-- +-----------+-----------------------------------------------------------+ +-- |rst | Reset for ``clk``. | +-- +-----------+-----------------------------------------------------------+ +-- |rst180 | Reset for ``clk_n`` | +-- +-----------+-----------------------------------------------------------+ +-- |rst90 | Reset for ``clk90``. | +-- +-----------+-----------------------------------------------------------+ +-- |rst270 | Reset for ``clk270``. | +-- +-----------+-----------------------------------------------------------+ +-- |rst_fb90 | Reset for ``clk_fb90``. | +-- +-----------+-----------------------------------------------------------+ +-- |rst_fb90_n | Reset for ``clk_fb90_n``. | +-- +-----------+-----------------------------------------------------------+ +-- +-- +-- Operation +-- ********* +-- +-- Command signals and write data are sampled with the rising edge of ``clk``. +-- +-- Read data is aligned with ``clk_fb90_n``. Either process data in this clock -- domain, or connect a FIFO to transfer data into another clock domain of your -- choice. This FIFO should capable of storing at least one burst (size BL/2) -- + start of next burst (size 1). -- --- clk : base clock for command and write data path. --- clk_n : clk phase shifted by 180 degrees. --- clk90 : clk phase shifted by 90 degrees. --- clk90_n : clk phase shifted by 270 degrees. --- --- clk_fb : driven by external feedback (sd_ck_fb) of DDR-SDRAM clock --- (sd_ck_p). (Actually unused, just for reference.) --- clk_fb90 : clk_fb phase shifted by 90 degrees. --- clk_fb90_n : clk_fb phase shifted by 270 degrees. +-- Write and read enable (``wren_nxt``, ``rden_nxt``) must be hold for: -- --- rst : Reset for clk. --- rst180 : Reset for clk_n. --- rst90 : Reset for clk90. --- rst270 : Reset for clk270. --- rst_fb90 : Reset for clk_fb90. --- rst_fb90_n : Reset for clk_fb90_n. +-- * 1 clock cycle if BL = 2, +-- * 2 clock cycles if BL = 4, or +-- * 4 clock cycles if BL = 8. -- --- Write and read enable (wren_nxt, rden_nxt) must be hold for --- 1 clock cycle if BL = 2, --- 2 clock cycles if BL = 4, or --- 4 clock cycles if BL = 8. -- They must be first asserted with the read and write command. Proper delay is -- included in this unit. -- @@ -48,10 +71,10 @@ -- delay is included in this unit. -- -- The SDRAM clock is regenerated in this module. The following timing is --- chosen for minimum latency. (Should work up to 100 MHz.) --- rising_edge(clk90) triggers rising_edge(sd_ck_p) --- rising_edge(clk90_n) triggers falling_edge(sd_ck_p) +-- chosen for minimum latency (should work up to 100 MHz): -- +-- * ``rising_edge(clk90)`` triggers ``rising_edge(sd_ck_p)``, +-- * ``rising_edge(clk90_n)`` triggers ``falling_edge(sd_ck_p)``. -- -- XST options: Disable equivalent register removal. -- diff --git a/src/mem/sdram/sdram_ctrl_s3esk.vhdl b/src/mem/sdram/sdram_ctrl_s3esk.vhdl index a898f2f9..cf0e43f5 100644 --- a/src/mem/sdram/sdram_ctrl_s3esk.vhdl +++ b/src/mem/sdram/sdram_ctrl_s3esk.vhdl @@ -9,19 +9,32 @@ -- Description: -- ------------------------------------- -- Controller for Micron DDR-SDRAM on Spartan-3E Starter Kit Board. +-- -- SDRAM Device: MT46V32M16-6T -- --- CLK_PERIOD = clock period in nano seconds. All SDRAM timings are --- calculated for the device stated above. +-- Configuration +-- ************* -- --- CL = cas latency, choose according to clock frequency. --- BL = burst length. +-- +------------+----------------------------------------------------+ +-- | Parameter | Description | +-- +============+====================================================+ +-- | CLK_PERIOD | Clock period in nano seconds. All SDRAM timings are| +-- | | calculated for the device stated above. | +-- +------------+----------------------------------------------------+ +-- | CL | CAS latency, choose according to clock frequency. | +-- +------------+----------------------------------------------------+ +-- | BL | Burst length. Choose BL=2 for single cycle memory | +-- | | transactions as required for the PoC.Mem interface.| +-- +------------+----------------------------------------------------+ -- -- Tested with: CLK_PERIOD = 10.0, CL=2, BL=2. -- --- Command, address and write data is sampled with clk. +-- Operation +-- ********* +-- +-- Command, address and write data are sampled with the rising edge of ``clk``. -- --- Read data is aligned with clk_fb90_n. Either process data in this clock +-- Read data is aligned with ``clk_fb90_n``. Either process data in this clock -- domain, or connect a FIFO to transfer data into another clock domain of your -- choice. This FIFO should capable of storing at least one burst (size BL/2) -- + start of next burst (size 1). From b1bf18a4fe5ba9679f02d37b1053d11e6b62b839 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 10 Nov 2016 23:55:02 +0100 Subject: [PATCH 20/97] Fixed copyright line. --- docs/PoCSphinx.py | 2 +- docs/conf.py | 2 +- docs/poc.py | 2 +- poc.ps1 | 2 +- poc.sh | 2 +- py/Base/Compiler.py | 2 +- py/Base/Configuration.py | 2 +- py/Base/Exceptions.py | 2 +- py/Base/Executable.py | 2 +- py/Base/Logging.py | 2 +- py/Base/Project.py | 2 +- py/Base/Shared.py | 2 +- py/Base/Simulator.py | 2 +- py/Base/ToolChain.py | 2 +- py/Base/__init__.py | 2 +- py/Compiler/ISECompiler.py | 2 +- py/Compiler/LSECompiler.py | 2 +- py/Compiler/QuartusCompiler.py | 2 +- py/Compiler/VivadoCompiler.py | 2 +- py/Compiler/XCICompiler.py | 2 +- py/Compiler/XCOCompiler.py | 2 +- py/Compiler/XSTCompiler.py | 2 +- py/Compiler/__init__.py | 2 +- py/DataBase/Config.py | 2 +- py/DataBase/Entity.py | 2 +- py/DataBase/Query.py | 2 +- py/DataBase/Solution.py | 2 +- py/DataBase/TestCase.py | 2 +- py/DataBase/__init__.py | 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py/config.defaults.ini | 2 +- py/config.entity.ini | 2 +- py/config.structure.ini | 2 +- py/lib/Functions.py | 2 +- py/lib/__init__.py | 2 +- sim/arith/arith_convert_bin2bcd_tb.wdo | 28 +++++++++++++++++++ src/arith/arith.pkg.vhdl | 2 +- src/arith/arith_addw.vhdl | 2 +- src/arith/arith_carrychain_inc.vhdl | 2 +- src/arith/arith_convert_bin2bcd.vhdl | 2 +- src/arith/arith_counter_bcd.vhdl | 2 +- src/arith/arith_counter_free.vhdl | 2 +- src/arith/arith_counter_gray.vhdl | 2 +- src/arith/arith_counter_ring.vhdl | 2 +- src/arith/arith_div.vhdl | 2 +- src/arith/arith_firstone.vhdl | 2 +- src/arith/arith_prefix_and.vhdl | 2 +- src/arith/arith_prefix_or.vhdl | 2 +- src/arith/arith_prng.vhdl | 2 +- src/arith/arith_same.vhdl | 2 +- src/arith/arith_scaler.vhdl | 2 +- src/arith/arith_shifter_barrel.vhdl | 2 +- src/arith/arith_sqrt.vhdl | 2 +- src/arith/xilinx/arith_addw_xilinx.vhdl | 2 +- .../xilinx/arith_carrychain_inc_xilinx.vhdl | 2 +- src/arith/xilinx/arith_inc_ovcy_xilinx.vhdl | 2 +- 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tools/git/git-alias.setup.ps1 | 2 +- tools/git/git-alias.setup.sh | 2 +- tools/git/hooks/pre-commit.d/whitespace.sh | 2 +- tools/git/hooks/run-hook.sh | 2 +- tools/precompile/compile-altera.ps1 | 2 +- tools/precompile/compile-altera.sh | 2 +- tools/precompile/compile-lattice.ps1 | 2 +- tools/precompile/compile-lattice.sh | 2 +- tools/precompile/compile-osvvm.ps1 | 2 +- tools/precompile/compile-osvvm.sh | 2 +- tools/precompile/compile-xilinx-ise.ps1 | 2 +- tools/precompile/compile-xilinx-ise.sh | 2 +- tools/precompile/compile-xilinx-vivado.ps1 | 2 +- tools/precompile/compile-xilinx-vivado.sh | 2 +- tools/precompile/shared.sh | 2 +- 382 files changed, 409 insertions(+), 381 deletions(-) create mode 100644 sim/arith/arith_convert_bin2bcd_tb.wdo diff --git a/docs/PoCSphinx.py b/docs/PoCSphinx.py index c341dbcf..4600f848 100644 --- a/docs/PoCSphinx.py +++ b/docs/PoCSphinx.py @@ -14,7 +14,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/docs/conf.py b/docs/conf.py index 278a4800..9241066a 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -62,7 +62,7 @@ # General information about the project. project = 'The PoC-Library' -copyright = '2007-2016 Technische Universitaet Dresden - Germany, Chair for VLSI-Design, Diagnostics and Architecture' +copyright = '2007-2016 Technische Universitaet Dresden - Germany, Chair of VLSI-Design, Diagnostics and Architecture' author = 'Patrick Lehmann, Thomas B. Preusser, Martin Zabel' # The version info for the project you're documenting, acts as replacement for diff --git a/docs/poc.py b/docs/poc.py index 47e9112e..84f447cd 100644 --- a/docs/poc.py +++ b/docs/poc.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/poc.ps1 b/poc.ps1 index 4228bfe7..49e7f67a 100644 --- a/poc.ps1 +++ b/poc.ps1 @@ -16,7 +16,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/poc.sh b/poc.sh index dd9a270a..c481bcb3 100755 --- a/poc.sh +++ b/poc.sh @@ -18,7 +18,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Base/Compiler.py b/py/Base/Compiler.py index 565bca70..c9a70ced 100644 --- a/py/Base/Compiler.py +++ b/py/Base/Compiler.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Base/Configuration.py b/py/Base/Configuration.py index 63fe308d..8298d01b 100644 --- a/py/Base/Configuration.py +++ b/py/Base/Configuration.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Base/Exceptions.py b/py/Base/Exceptions.py index d19b183e..bc0dc08b 100644 --- a/py/Base/Exceptions.py +++ b/py/Base/Exceptions.py @@ -16,7 +16,7 @@ # License: # ============================================================================== # Copyright 2007-2015 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Base/Executable.py b/py/Base/Executable.py index 645c3b67..6f98a120 100644 --- a/py/Base/Executable.py +++ b/py/Base/Executable.py @@ -16,7 +16,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Base/Logging.py b/py/Base/Logging.py index 7a4dee56..82c5e0c8 100644 --- a/py/Base/Logging.py +++ b/py/Base/Logging.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Base/Project.py b/py/Base/Project.py index 781abeb9..f1dc3752 100644 --- a/py/Base/Project.py +++ b/py/Base/Project.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Base/Shared.py b/py/Base/Shared.py index cd9f7904..c40e8688 100644 --- a/py/Base/Shared.py +++ b/py/Base/Shared.py @@ -16,7 +16,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Base/Simulator.py b/py/Base/Simulator.py index 72e79f64..73fa7e6f 100644 --- a/py/Base/Simulator.py +++ b/py/Base/Simulator.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Base/ToolChain.py b/py/Base/ToolChain.py index cf0d3d73..29975f63 100644 --- a/py/Base/ToolChain.py +++ b/py/Base/ToolChain.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Base/__init__.py b/py/Base/__init__.py index 72e3442d..c461076d 100644 --- a/py/Base/__init__.py +++ b/py/Base/__init__.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2015 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Compiler/ISECompiler.py b/py/Compiler/ISECompiler.py index 1bf881c2..84891d16 100644 --- a/py/Compiler/ISECompiler.py +++ b/py/Compiler/ISECompiler.py @@ -16,7 +16,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Compiler/LSECompiler.py b/py/Compiler/LSECompiler.py index 63af6ae6..246bb15c 100644 --- a/py/Compiler/LSECompiler.py +++ b/py/Compiler/LSECompiler.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Compiler/QuartusCompiler.py b/py/Compiler/QuartusCompiler.py index 787b4910..9ea22590 100644 --- a/py/Compiler/QuartusCompiler.py +++ b/py/Compiler/QuartusCompiler.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Compiler/VivadoCompiler.py b/py/Compiler/VivadoCompiler.py index 85714e7a..f6728725 100644 --- a/py/Compiler/VivadoCompiler.py +++ b/py/Compiler/VivadoCompiler.py @@ -16,7 +16,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Compiler/XCICompiler.py b/py/Compiler/XCICompiler.py index 96f44017..57fcf9d6 100644 --- a/py/Compiler/XCICompiler.py +++ b/py/Compiler/XCICompiler.py @@ -16,7 +16,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Compiler/XCOCompiler.py b/py/Compiler/XCOCompiler.py index 8bb90357..7c9c5be3 100644 --- a/py/Compiler/XCOCompiler.py +++ b/py/Compiler/XCOCompiler.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Compiler/XSTCompiler.py b/py/Compiler/XSTCompiler.py index 7e84d5ca..4bc4f9af 100644 --- a/py/Compiler/XSTCompiler.py +++ b/py/Compiler/XSTCompiler.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Compiler/__init__.py b/py/Compiler/__init__.py index 2d70fe94..8a2a1fb4 100644 --- a/py/Compiler/__init__.py +++ b/py/Compiler/__init__.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/DataBase/Config.py b/py/DataBase/Config.py index 0b429c83..aaf5c6a5 100644 --- a/py/DataBase/Config.py +++ b/py/DataBase/Config.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/DataBase/Entity.py b/py/DataBase/Entity.py index 6ce64d56..29048b29 100644 --- a/py/DataBase/Entity.py +++ b/py/DataBase/Entity.py @@ -16,7 +16,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/DataBase/Query.py b/py/DataBase/Query.py index 0a2f009b..17b8e707 100644 --- a/py/DataBase/Query.py +++ b/py/DataBase/Query.py @@ -14,7 +14,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/DataBase/Solution.py b/py/DataBase/Solution.py index b86ce7c8..5cacf1b3 100644 --- a/py/DataBase/Solution.py +++ b/py/DataBase/Solution.py @@ -16,7 +16,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/DataBase/TestCase.py b/py/DataBase/TestCase.py index b3413edd..82b9694a 100644 --- a/py/DataBase/TestCase.py +++ b/py/DataBase/TestCase.py @@ -14,7 +14,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/DataBase/__init__.py b/py/DataBase/__init__.py index 78c2cfdc..da726182 100644 --- a/py/DataBase/__init__.py +++ b/py/DataBase/__init__.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2015 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Parser/FilesCodeDOM.py b/py/Parser/FilesCodeDOM.py index 75088fd2..2d79e99e 100644 --- a/py/Parser/FilesCodeDOM.py +++ b/py/Parser/FilesCodeDOM.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Parser/FilesParser.py b/py/Parser/FilesParser.py index c293b6e7..0720a8b2 100644 --- a/py/Parser/FilesParser.py +++ b/py/Parser/FilesParser.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Parser/RulesCodeDOM.py b/py/Parser/RulesCodeDOM.py index 831bb6a9..8e04212f 100644 --- a/py/Parser/RulesCodeDOM.py +++ b/py/Parser/RulesCodeDOM.py @@ -14,7 +14,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Parser/RulesParser.py b/py/Parser/RulesParser.py index 10e21414..9214976d 100644 --- a/py/Parser/RulesParser.py +++ b/py/Parser/RulesParser.py @@ -14,7 +14,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Parser/__init__.py b/py/Parser/__init__.py index 2d70fe94..8a2a1fb4 100644 --- a/py/Parser/__init__.py +++ b/py/Parser/__init__.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/PoC.py b/py/PoC.py index a80e2880..857709b0 100644 --- a/py/PoC.py +++ b/py/PoC.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Processor/__init__.py b/py/Processor/__init__.py index 32a31622..228b0ae3 100644 --- a/py/Processor/__init__.py +++ b/py/Processor/__init__.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2015 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Simulator/ActiveHDLSimulator.py b/py/Simulator/ActiveHDLSimulator.py index e0e6c706..f5b29ef3 100644 --- a/py/Simulator/ActiveHDLSimulator.py +++ b/py/Simulator/ActiveHDLSimulator.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Simulator/CocotbSimulator.py b/py/Simulator/CocotbSimulator.py index 8e6725b9..c7d709eb 100644 --- a/py/Simulator/CocotbSimulator.py +++ b/py/Simulator/CocotbSimulator.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Simulator/GHDLSimulator.py b/py/Simulator/GHDLSimulator.py index cc91b2ba..ff591127 100644 --- a/py/Simulator/GHDLSimulator.py +++ b/py/Simulator/GHDLSimulator.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Simulator/ISESimulator.py b/py/Simulator/ISESimulator.py index b23cb037..8acd9448 100644 --- a/py/Simulator/ISESimulator.py +++ b/py/Simulator/ISESimulator.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Simulator/QuestaSimulator.py b/py/Simulator/QuestaSimulator.py index 752f9844..5df6a7b4 100644 --- a/py/Simulator/QuestaSimulator.py +++ b/py/Simulator/QuestaSimulator.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Simulator/VivadoSimulator.py b/py/Simulator/VivadoSimulator.py index e7f3bb7e..5864a18b 100644 --- a/py/Simulator/VivadoSimulator.py +++ b/py/Simulator/VivadoSimulator.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Simulator/__init__.py b/py/Simulator/__init__.py index 1b1d35e3..5c242809 100644 --- a/py/Simulator/__init__.py +++ b/py/Simulator/__init__.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Aldec/ActiveHDL.py b/py/ToolChains/Aldec/ActiveHDL.py index e0091afe..b50aa70f 100644 --- a/py/ToolChains/Aldec/ActiveHDL.py +++ b/py/ToolChains/Aldec/ActiveHDL.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Aldec/Aldec.py b/py/ToolChains/Aldec/Aldec.py index a3ef1822..f530254f 100644 --- a/py/ToolChains/Aldec/Aldec.py +++ b/py/ToolChains/Aldec/Aldec.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Aldec/__init__.py b/py/ToolChains/Aldec/__init__.py index e7bdd2cf..896b9579 100644 --- a/py/ToolChains/Aldec/__init__.py +++ b/py/ToolChains/Aldec/__init__.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Altera/Altera.py b/py/ToolChains/Altera/Altera.py index ffcea33a..a59e272f 100644 --- a/py/ToolChains/Altera/Altera.py +++ b/py/ToolChains/Altera/Altera.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Altera/ModelSim.py b/py/ToolChains/Altera/ModelSim.py index e3b1c9f6..ce5a524d 100644 --- a/py/ToolChains/Altera/ModelSim.py +++ b/py/ToolChains/Altera/ModelSim.py @@ -18,7 +18,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Altera/Quartus.py b/py/ToolChains/Altera/Quartus.py index e4114e13..5c596961 100644 --- a/py/ToolChains/Altera/Quartus.py +++ b/py/ToolChains/Altera/Quartus.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Altera/__init__.py b/py/ToolChains/Altera/__init__.py index e7bdd2cf..896b9579 100644 --- a/py/ToolChains/Altera/__init__.py +++ b/py/ToolChains/Altera/__init__.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/GHDL.py b/py/ToolChains/GHDL.py index 91b176dd..8119dc71 100644 --- a/py/ToolChains/GHDL.py +++ b/py/ToolChains/GHDL.py @@ -18,7 +18,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/GNU.py b/py/ToolChains/GNU.py index 8aa66d33..3fbabca9 100644 --- a/py/ToolChains/GNU.py +++ b/py/ToolChains/GNU.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/GTKWave.py b/py/ToolChains/GTKWave.py index 21deeeb8..4c6b84f2 100644 --- a/py/ToolChains/GTKWave.py +++ b/py/ToolChains/GTKWave.py @@ -18,7 +18,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Git.py b/py/ToolChains/Git.py index 6a2bfc48..e3dda915 100644 --- a/py/ToolChains/Git.py +++ b/py/ToolChains/Git.py @@ -18,7 +18,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Lattice/ActiveHDL.py b/py/ToolChains/Lattice/ActiveHDL.py index 48dfd293..7eac20bd 100644 --- a/py/ToolChains/Lattice/ActiveHDL.py +++ b/py/ToolChains/Lattice/ActiveHDL.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Lattice/Diamond.py b/py/ToolChains/Lattice/Diamond.py index 0e8e8b6e..b5b51c3f 100644 --- a/py/ToolChains/Lattice/Diamond.py +++ b/py/ToolChains/Lattice/Diamond.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Lattice/Lattice.py b/py/ToolChains/Lattice/Lattice.py index 480b9c1b..5242f0dc 100644 --- a/py/ToolChains/Lattice/Lattice.py +++ b/py/ToolChains/Lattice/Lattice.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Lattice/Synopsys.py b/py/ToolChains/Lattice/Synopsys.py index d70c980f..b3f22653 100644 --- a/py/ToolChains/Lattice/Synopsys.py +++ b/py/ToolChains/Lattice/Synopsys.py @@ -16,7 +16,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Lattice/__init__.py b/py/ToolChains/Lattice/__init__.py index e7bdd2cf..896b9579 100644 --- a/py/ToolChains/Lattice/__init__.py +++ b/py/ToolChains/Lattice/__init__.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Mentor/Mentor.py b/py/ToolChains/Mentor/Mentor.py index 3f59bf07..6365671d 100644 --- a/py/ToolChains/Mentor/Mentor.py +++ b/py/ToolChains/Mentor/Mentor.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Mentor/QuestaSim.py b/py/ToolChains/Mentor/QuestaSim.py index 9786324a..a7328566 100644 --- a/py/ToolChains/Mentor/QuestaSim.py +++ b/py/ToolChains/Mentor/QuestaSim.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Mentor/__init__.py b/py/ToolChains/Mentor/__init__.py index df2e8cb8..c4506a37 100644 --- a/py/ToolChains/Mentor/__init__.py +++ b/py/ToolChains/Mentor/__init__.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/PoC.py b/py/ToolChains/PoC.py index 38777172..64c9bf03 100644 --- a/py/ToolChains/PoC.py +++ b/py/ToolChains/PoC.py @@ -18,7 +18,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Synopsys/Synopsys.py b/py/ToolChains/Synopsys/Synopsys.py index a95863b2..4efdb8da 100644 --- a/py/ToolChains/Synopsys/Synopsys.py +++ b/py/ToolChains/Synopsys/Synopsys.py @@ -16,7 +16,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Synopsys/__init__.py b/py/ToolChains/Synopsys/__init__.py index 8d446c1c..7183c8d9 100644 --- a/py/ToolChains/Synopsys/__init__.py +++ b/py/ToolChains/Synopsys/__init__.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Xilinx/HardwareServer.py b/py/ToolChains/Xilinx/HardwareServer.py index 0a25724c..90f74151 100644 --- a/py/ToolChains/Xilinx/HardwareServer.py +++ b/py/ToolChains/Xilinx/HardwareServer.py @@ -16,7 +16,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Xilinx/ISE.py b/py/ToolChains/Xilinx/ISE.py index dbf107b9..bbb3a661 100644 --- a/py/ToolChains/Xilinx/ISE.py +++ b/py/ToolChains/Xilinx/ISE.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Xilinx/LabTools.py b/py/ToolChains/Xilinx/LabTools.py index fe2e1b18..96f77320 100644 --- a/py/ToolChains/Xilinx/LabTools.py +++ b/py/ToolChains/Xilinx/LabTools.py @@ -16,7 +16,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Xilinx/Vivado.py b/py/ToolChains/Xilinx/Vivado.py index 9714bb2b..d2e5b0b3 100644 --- a/py/ToolChains/Xilinx/Vivado.py +++ b/py/ToolChains/Xilinx/Vivado.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Xilinx/Xilinx.py b/py/ToolChains/Xilinx/Xilinx.py index 7a7edfa3..b88ac27d 100644 --- a/py/ToolChains/Xilinx/Xilinx.py +++ b/py/ToolChains/Xilinx/Xilinx.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/Xilinx/__init__.py b/py/ToolChains/Xilinx/__init__.py index 8d446c1c..7183c8d9 100644 --- a/py/ToolChains/Xilinx/__init__.py +++ b/py/ToolChains/Xilinx/__init__.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/ToolChains/__init__.py b/py/ToolChains/__init__.py index d4b087ef..4785d091 100644 --- a/py/ToolChains/__init__.py +++ b/py/ToolChains/__init__.py @@ -16,7 +16,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Wrapper/Lattice.Diamond.psm1 b/py/Wrapper/Lattice.Diamond.psm1 index 90d8dfd1..b6452b81 100644 --- a/py/Wrapper/Lattice.Diamond.psm1 +++ b/py/Wrapper/Lattice.Diamond.psm1 @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Wrapper/Lattice.Diamond.sh b/py/Wrapper/Lattice.Diamond.sh index 10cf450c..0c1bc2ce 100644 --- a/py/Wrapper/Lattice.Diamond.sh +++ b/py/Wrapper/Lattice.Diamond.sh @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Wrapper/PoC.psm1 b/py/Wrapper/PoC.psm1 index 039d7cf6..ae73157e 100644 --- a/py/Wrapper/PoC.psm1 +++ b/py/Wrapper/PoC.psm1 @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Wrapper/PowerShell.psm1 b/py/Wrapper/PowerShell.psm1 index 7e1e7351..0c944237 100644 --- a/py/Wrapper/PowerShell.psm1 +++ b/py/Wrapper/PowerShell.psm1 @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Wrapper/Sphinx.psm1 b/py/Wrapper/Sphinx.psm1 index 3e3a1ab0..2d89d4ed 100644 --- a/py/Wrapper/Sphinx.psm1 +++ b/py/Wrapper/Sphinx.psm1 @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Wrapper/Sphinx.sh b/py/Wrapper/Sphinx.sh index 2d8680e8..b64901d0 100644 --- a/py/Wrapper/Sphinx.sh +++ b/py/Wrapper/Sphinx.sh @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Wrapper/Xilinx.ISE.psm1 b/py/Wrapper/Xilinx.ISE.psm1 index e9a26675..c0b274d5 100644 --- a/py/Wrapper/Xilinx.ISE.psm1 +++ b/py/Wrapper/Xilinx.ISE.psm1 @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Wrapper/Xilinx.ISE.sh b/py/Wrapper/Xilinx.ISE.sh index bc718e32..ca5a0823 100644 --- a/py/Wrapper/Xilinx.ISE.sh +++ b/py/Wrapper/Xilinx.ISE.sh @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Wrapper/Xilinx.Vivado.psm1 b/py/Wrapper/Xilinx.Vivado.psm1 index 993d16a6..4dd0178e 100644 --- a/py/Wrapper/Xilinx.Vivado.psm1 +++ b/py/Wrapper/Xilinx.Vivado.psm1 @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Wrapper/Xilinx.Vivado.sh b/py/Wrapper/Xilinx.Vivado.sh index cc5c0457..9bff3e35 100644 --- a/py/Wrapper/Xilinx.Vivado.sh +++ b/py/Wrapper/Xilinx.Vivado.sh @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/Wrapper/wrapper.sh b/py/Wrapper/wrapper.sh index d5e14d90..a7130fbc 100644 --- a/py/Wrapper/wrapper.sh +++ b/py/Wrapper/wrapper.sh @@ -18,7 +18,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/__init__.py b/py/__init__.py index 32a31622..228b0ae3 100644 --- a/py/__init__.py +++ b/py/__init__.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2015 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/config.boards.ini b/py/config.boards.ini index ea331074..218b1f08 100644 --- a/py/config.boards.ini +++ b/py/config.boards.ini @@ -13,7 +13,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/config.defaults.ini b/py/config.defaults.ini index 818f38ed..d77d3d86 100644 --- a/py/config.defaults.ini +++ b/py/config.defaults.ini @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/config.entity.ini b/py/config.entity.ini index fcccf200..b2071912 100644 --- a/py/config.entity.ini +++ b/py/config.entity.ini @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/config.structure.ini b/py/config.structure.ini index 07f10c83..48cef497 100644 --- a/py/config.structure.ini +++ b/py/config.structure.ini @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/lib/Functions.py b/py/lib/Functions.py index 40aca8f1..90dc5a2d 100644 --- a/py/lib/Functions.py +++ b/py/lib/Functions.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/lib/__init__.py b/py/lib/__init__.py index 32a31622..228b0ae3 100644 --- a/py/lib/__init__.py +++ b/py/lib/__init__.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2015 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/sim/arith/arith_convert_bin2bcd_tb.wdo b/sim/arith/arith_convert_bin2bcd_tb.wdo new file mode 100644 index 00000000..339a6161 --- /dev/null +++ b/sim/arith/arith_convert_bin2bcd_tb.wdo @@ -0,0 +1,28 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /arith_convert_bin2bcd_tb/Clock +add wave -noupdate /arith_convert_bin2bcd_tb/Reset +add wave -noupdate /arith_convert_bin2bcd_tb/Start +add wave -noupdate -radix decimal /arith_convert_bin2bcd_tb/Conv1_Binary +add wave -noupdate -expand /arith_convert_bin2bcd_tb/Conv1_BCDDigits +add wave -noupdate -radix decimal /arith_convert_bin2bcd_tb/Conv2_Binary +add wave -noupdate -expand /arith_convert_bin2bcd_tb/Conv2_BCDDigits +add wave -noupdate /arith_convert_bin2bcd_tb/Conv2_Sign +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 fs} 0} +quietly wave cursor active 0 +configure wave -namecolwidth 279 +configure wave -valuecolwidth 130 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 fs} {1113 ns} diff --git a/src/arith/arith.pkg.vhdl b/src/arith/arith.pkg.vhdl index 8d05380e..225372c0 100644 --- a/src/arith/arith.pkg.vhdl +++ b/src/arith/arith.pkg.vhdl @@ -16,7 +16,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/arith/arith_addw.vhdl b/src/arith/arith_addw.vhdl index ca5aedf4..0b364c4d 100644 --- a/src/arith/arith_addw.vhdl +++ b/src/arith/arith_addw.vhdl @@ -27,7 +27,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/arith/arith_carrychain_inc.vhdl b/src/arith/arith_carrychain_inc.vhdl index b60a2fe3..c97fc0e8 100644 --- a/src/arith/arith_carrychain_inc.vhdl +++ b/src/arith/arith_carrychain_inc.vhdl @@ -15,7 +15,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/arith/arith_convert_bin2bcd.vhdl b/src/arith/arith_convert_bin2bcd.vhdl index 861573b5..4c282368 100644 --- a/src/arith/arith_convert_bin2bcd.vhdl +++ b/src/arith/arith_convert_bin2bcd.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/arith/arith_counter_bcd.vhdl b/src/arith/arith_counter_bcd.vhdl index 928aa965..ae1edf3e 100644 --- a/src/arith/arith_counter_bcd.vhdl +++ b/src/arith/arith_counter_bcd.vhdl @@ -25,7 +25,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/arith/arith_counter_free.vhdl b/src/arith/arith_counter_free.vhdl index f4f8e6f5..f141c2a9 100644 --- a/src/arith/arith_counter_free.vhdl +++ b/src/arith/arith_counter_free.vhdl @@ -20,7 +20,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/arith/arith_counter_gray.vhdl b/src/arith/arith_counter_gray.vhdl index 904d166e..369e58f0 100644 --- a/src/arith/arith_counter_gray.vhdl +++ b/src/arith/arith_counter_gray.vhdl @@ -15,7 +15,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2014 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/arith/arith_counter_ring.vhdl b/src/arith/arith_counter_ring.vhdl index a19955d4..9a97d415 100644 --- a/src/arith/arith_counter_ring.vhdl +++ b/src/arith/arith_counter_ring.vhdl @@ -16,7 +16,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/arith/arith_div.vhdl b/src/arith/arith_div.vhdl index c2252374..56a2a6bc 100644 --- a/src/arith/arith_div.vhdl +++ b/src/arith/arith_div.vhdl @@ -17,7 +17,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universität Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/arith/arith_firstone.vhdl b/src/arith/arith_firstone.vhdl index 3d0cb990..2fba6875 100644 --- a/src/arith/arith_firstone.vhdl +++ b/src/arith/arith_firstone.vhdl @@ -26,7 +26,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universität Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/arith/arith_prefix_and.vhdl b/src/arith/arith_prefix_and.vhdl index ac665127..ca6afea0 100644 --- a/src/arith/arith_prefix_and.vhdl +++ b/src/arith/arith_prefix_and.vhdl @@ -16,7 +16,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universität Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/arith/arith_prefix_or.vhdl b/src/arith/arith_prefix_or.vhdl index 8e60f3db..3a6a527c 100644 --- a/src/arith/arith_prefix_or.vhdl +++ b/src/arith/arith_prefix_or.vhdl @@ -16,7 +16,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universität Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/arith/arith_prng.vhdl b/src/arith/arith_prng.vhdl index 63bc2074..3b006088 100644 --- a/src/arith/arith_prng.vhdl +++ b/src/arith/arith_prng.vhdl @@ -20,7 +20,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2014 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/arith/arith_same.vhdl b/src/arith/arith_same.vhdl index 37ce7eb4..4210ebfd 100644 --- a/src/arith/arith_same.vhdl +++ b/src/arith/arith_same.vhdl @@ -20,7 +20,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universität Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/arith/arith_scaler.vhdl b/src/arith/arith_scaler.vhdl index b2c99c2a..d2008f42 100644 --- a/src/arith/arith_scaler.vhdl +++ b/src/arith/arith_scaler.vhdl @@ -27,7 +27,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/arith/arith_shifter_barrel.vhdl b/src/arith/arith_shifter_barrel.vhdl index 36418e88..4ffae759 100644 --- a/src/arith/arith_shifter_barrel.vhdl +++ b/src/arith/arith_shifter_barrel.vhdl @@ -19,7 +19,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/arith/arith_sqrt.vhdl b/src/arith/arith_sqrt.vhdl index 77731924..c125cc2a 100644 --- a/src/arith/arith_sqrt.vhdl +++ b/src/arith/arith_sqrt.vhdl @@ -15,7 +15,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2014 Technische Universität Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/arith/xilinx/arith_addw_xilinx.vhdl b/src/arith/xilinx/arith_addw_xilinx.vhdl index b1900767..df5356c3 100644 --- a/src/arith/xilinx/arith_addw_xilinx.vhdl +++ b/src/arith/xilinx/arith_addw_xilinx.vhdl @@ -29,7 +29,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/arith/xilinx/arith_carrychain_inc_xilinx.vhdl b/src/arith/xilinx/arith_carrychain_inc_xilinx.vhdl index fb5ea857..850224b7 100644 --- a/src/arith/xilinx/arith_carrychain_inc_xilinx.vhdl +++ b/src/arith/xilinx/arith_carrychain_inc_xilinx.vhdl @@ -16,7 +16,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/arith/xilinx/arith_inc_ovcy_xilinx.vhdl b/src/arith/xilinx/arith_inc_ovcy_xilinx.vhdl index f299993c..71952d58 100644 --- a/src/arith/xilinx/arith_inc_ovcy_xilinx.vhdl +++ b/src/arith/xilinx/arith_inc_ovcy_xilinx.vhdl @@ -11,7 +11,7 @@ -- -- ============================================================================= -- Copyright 2007-2015 Technische Universität Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/arith/xilinx/arith_prefix_and_xilinx.vhdl b/src/arith/xilinx/arith_prefix_and_xilinx.vhdl index d423b880..dfaee08a 100644 --- a/src/arith/xilinx/arith_prefix_and_xilinx.vhdl +++ b/src/arith/xilinx/arith_prefix_and_xilinx.vhdl @@ -15,7 +15,7 @@ -- -- ============================================================================= -- Copyright 2007-2016 Technische Universität Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/arith/xilinx/arith_prefix_or_xilinx.vhdl b/src/arith/xilinx/arith_prefix_or_xilinx.vhdl index 8c172a12..3e49b1dd 100644 --- a/src/arith/xilinx/arith_prefix_or_xilinx.vhdl +++ b/src/arith/xilinx/arith_prefix_or_xilinx.vhdl @@ -15,7 +15,7 @@ -- -- ============================================================================= -- Copyright 2007-2016 Technische Universität Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/bus_Arbiter.vhdl b/src/bus/bus_Arbiter.vhdl index a965b2fe..6592a577 100644 --- a/src/bus/bus_Arbiter.vhdl +++ b/src/bus/bus_Arbiter.vhdl @@ -16,7 +16,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/stream/stream.pkg.vhdl b/src/bus/stream/stream.pkg.vhdl index dbe7a86a..9802eaab 100644 --- a/src/bus/stream/stream.pkg.vhdl +++ b/src/bus/stream/stream.pkg.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/stream/stream_Buffer.vhdl b/src/bus/stream/stream_Buffer.vhdl index e854a1c9..be66668c 100644 --- a/src/bus/stream/stream_Buffer.vhdl +++ b/src/bus/stream/stream_Buffer.vhdl @@ -16,7 +16,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/stream/stream_DeMux.vhdl b/src/bus/stream/stream_DeMux.vhdl index e9c904c3..d4629884 100644 --- a/src/bus/stream/stream_DeMux.vhdl +++ b/src/bus/stream/stream_DeMux.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/stream/stream_FrameGenerator.vhdl b/src/bus/stream/stream_FrameGenerator.vhdl index 76a8e802..0c25fe20 100644 --- a/src/bus/stream/stream_FrameGenerator.vhdl +++ b/src/bus/stream/stream_FrameGenerator.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/stream/stream_Mirror.vhdl b/src/bus/stream/stream_Mirror.vhdl index c0190fb7..b7aac21f 100644 --- a/src/bus/stream/stream_Mirror.vhdl +++ b/src/bus/stream/stream_Mirror.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/stream/stream_Mux.vhdl b/src/bus/stream/stream_Mux.vhdl index 9fdbda4b..66bdc720 100644 --- a/src/bus/stream/stream_Mux.vhdl +++ b/src/bus/stream/stream_Mux.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/stream/stream_Source.vhdl b/src/bus/stream/stream_Source.vhdl index 92bd855b..b86afa73 100644 --- a/src/bus/stream/stream_Source.vhdl +++ b/src/bus/stream/stream_Source.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/cache/cache.pkg.vhdl b/src/cache/cache.pkg.vhdl index 24729cb4..5014e128 100644 --- a/src/cache/cache.pkg.vhdl +++ b/src/cache/cache.pkg.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/cache/cache_par.vhdl b/src/cache/cache_par.vhdl index e38470d0..fc008b61 100644 --- a/src/cache/cache_par.vhdl +++ b/src/cache/cache_par.vhdl @@ -49,7 +49,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/cache/cache_replacement_policy.vhdl b/src/cache/cache_replacement_policy.vhdl index 6db18718..b158d6ea 100644 --- a/src/cache/cache_replacement_policy.vhdl +++ b/src/cache/cache_replacement_policy.vhdl @@ -56,7 +56,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/cache/cache_tagunit_par.vhdl b/src/cache/cache_tagunit_par.vhdl index 05cf42a9..3b2c11ea 100644 --- a/src/cache/cache_tagunit_par.vhdl +++ b/src/cache/cache_tagunit_par.vhdl @@ -49,7 +49,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/cache/cache_tagunit_seq.vhdl b/src/cache/cache_tagunit_seq.vhdl index 2241aa10..c48d3248 100644 --- a/src/cache/cache_tagunit_seq.vhdl +++ b/src/cache/cache_tagunit_seq.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2014 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/comm/comm.pkg.vhdl b/src/comm/comm.pkg.vhdl index a64df347..e1d95f62 100644 --- a/src/comm/comm.pkg.vhdl +++ b/src/comm/comm.pkg.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/comm/comm_crc.vhdl b/src/comm/comm_crc.vhdl index 0fe5fe8b..e0a02b63 100644 --- a/src/comm/comm_crc.vhdl +++ b/src/comm/comm_crc.vhdl @@ -20,7 +20,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/comm/comm_scramble.vhdl b/src/comm/comm_scramble.vhdl index cfc2f4be..fa624ee0 100644 --- a/src/comm/comm_scramble.vhdl +++ b/src/comm/comm_scramble.vhdl @@ -15,7 +15,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/comm/remote/remote_terminal_control.vhdl b/src/comm/remote/remote_terminal_control.vhdl index 64ea4d92..8c57f5f2 100644 --- a/src/comm/remote/remote_terminal_control.vhdl +++ b/src/comm/remote/remote_terminal_control.vhdl @@ -63,7 +63,7 @@ -- Authors: Thomas B. Preußer ------------------------------------------------------------------------------- -- Copyright 2007-2014 Technische Universität Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/common/common.vhdl b/src/common/common.vhdl index 543dc865..ea127942 100644 --- a/src/common/common.vhdl +++ b/src/common/common.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/common/components.vhdl b/src/common/components.vhdl index b12517d9..3be522de 100644 --- a/src/common/components.vhdl +++ b/src/common/components.vhdl @@ -19,7 +19,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/common/config.vhdl b/src/common/config.vhdl index a3b15483..6952d5c1 100644 --- a/src/common/config.vhdl +++ b/src/common/config.vhdl @@ -16,7 +16,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/common/debug.vhdl b/src/common/debug.vhdl index 0a852a93..d6d961d5 100644 --- a/src/common/debug.vhdl +++ b/src/common/debug.vhdl @@ -16,7 +16,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/common/fileio.v08.vhdl b/src/common/fileio.v08.vhdl index 75e7de2e..999d73da 100644 --- a/src/common/fileio.v08.vhdl +++ b/src/common/fileio.v08.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/common/fileio.v93.vhdl b/src/common/fileio.v93.vhdl index b9adab8c..58f21020 100644 --- a/src/common/fileio.v93.vhdl +++ b/src/common/fileio.v93.vhdl @@ -22,7 +22,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/common/math.vhdl b/src/common/math.vhdl index 3cfc0ba4..2b366418 100644 --- a/src/common/math.vhdl +++ b/src/common/math.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/common/physical.vhdl b/src/common/physical.vhdl index 35d13135..b8b07d7e 100644 --- a/src/common/physical.vhdl +++ b/src/common/physical.vhdl @@ -39,7 +39,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/common/protected.v08.vhdl b/src/common/protected.v08.vhdl index edc86a65..9888f27c 100644 --- a/src/common/protected.v08.vhdl +++ b/src/common/protected.v08.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/common/strings.vhdl b/src/common/strings.vhdl index edf08a57..258eb28b 100644 --- a/src/common/strings.vhdl +++ b/src/common/strings.vhdl @@ -15,7 +15,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/common/utils.vhdl b/src/common/utils.vhdl index d47e6754..d9acc0fc 100644 --- a/src/common/utils.vhdl +++ b/src/common/utils.vhdl @@ -16,7 +16,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/common/vectors.vhdl b/src/common/vectors.vhdl index 21a40b04..74ed0e57 100644 --- a/src/common/vectors.vhdl +++ b/src/common/vectors.vhdl @@ -15,7 +15,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/dstruct/dstruct.pkg.vhdl b/src/dstruct/dstruct.pkg.vhdl index 1a5f41f2..4cf10013 100644 --- a/src/dstruct/dstruct.pkg.vhdl +++ b/src/dstruct/dstruct.pkg.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/dstruct/dstruct_deque.vhdl b/src/dstruct/dstruct_deque.vhdl index 879c11f5..aeb995ac 100644 --- a/src/dstruct/dstruct_deque.vhdl +++ b/src/dstruct/dstruct_deque.vhdl @@ -15,7 +15,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/dstruct/dstruct_stack.vhdl b/src/dstruct/dstruct_stack.vhdl index e714a6d8..6baba137 100644 --- a/src/dstruct/dstruct_stack.vhdl +++ b/src/dstruct/dstruct_stack.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/fifo/fifo.pkg.vhdl b/src/fifo/fifo.pkg.vhdl index 22106658..b53b3f75 100644 --- a/src/fifo/fifo.pkg.vhdl +++ b/src/fifo/fifo.pkg.vhdl @@ -17,7 +17,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/fifo/fifo_cc_got.vhdl b/src/fifo/fifo_cc_got.vhdl index 48168c3f..9c72d7ac 100644 --- a/src/fifo/fifo_cc_got.vhdl +++ b/src/fifo/fifo_cc_got.vhdl @@ -70,7 +70,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/fifo/fifo_cc_got_tempgot.vhdl b/src/fifo/fifo_cc_got_tempgot.vhdl index ee1115e9..9e6ed12f 100644 --- a/src/fifo/fifo_cc_got_tempgot.vhdl +++ b/src/fifo/fifo_cc_got_tempgot.vhdl @@ -57,7 +57,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2014 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/fifo/fifo_cc_got_tempput.vhdl b/src/fifo/fifo_cc_got_tempput.vhdl index 71078ca9..1d74b684 100644 --- a/src/fifo/fifo_cc_got_tempput.vhdl +++ b/src/fifo/fifo_cc_got_tempput.vhdl @@ -57,7 +57,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2014 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/fifo/fifo_glue.vhdl b/src/fifo/fifo_glue.vhdl index 19cfe72a..eaebf5b7 100644 --- a/src/fifo/fifo_glue.vhdl +++ b/src/fifo/fifo_glue.vhdl @@ -15,7 +15,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/fifo/fifo_ic_assembly.vhdl b/src/fifo/fifo_ic_assembly.vhdl index c81ff3ab..d5902887 100644 --- a/src/fifo/fifo_ic_assembly.vhdl +++ b/src/fifo/fifo_ic_assembly.vhdl @@ -24,7 +24,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/fifo/fifo_ic_got.vhdl b/src/fifo/fifo_ic_got.vhdl index 3e21ea18..2076e577 100644 --- a/src/fifo/fifo_ic_got.vhdl +++ b/src/fifo/fifo_ic_got.vhdl @@ -50,7 +50,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2014 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/fifo/fifo_shift.vhdl b/src/fifo/fifo_shift.vhdl index 09bba2c2..ec1c73c7 100644 --- a/src/fifo/fifo_shift.vhdl +++ b/src/fifo/fifo_shift.vhdl @@ -19,7 +19,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2014 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/ddrio/ddrio.pkg.vhdl b/src/io/ddrio/ddrio.pkg.vhdl index 22b24cb9..f26d0634 100644 --- a/src/io/ddrio/ddrio.pkg.vhdl +++ b/src/io/ddrio/ddrio.pkg.vhdl @@ -15,7 +15,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/ddrio/ddrio_in.vhdl b/src/io/ddrio/ddrio_in.vhdl index 63bafdc0..6d349520 100644 --- a/src/io/ddrio/ddrio_in.vhdl +++ b/src/io/ddrio/ddrio_in.vhdl @@ -36,7 +36,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/ddrio/ddrio_in_altera.vhdl b/src/io/ddrio/ddrio_in_altera.vhdl index 74a29328..cb982694 100644 --- a/src/io/ddrio/ddrio_in_altera.vhdl +++ b/src/io/ddrio/ddrio_in_altera.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/ddrio/ddrio_in_xilinx.vhdl b/src/io/ddrio/ddrio_in_xilinx.vhdl index f3292e11..d158a86a 100644 --- a/src/io/ddrio/ddrio_in_xilinx.vhdl +++ b/src/io/ddrio/ddrio_in_xilinx.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/ddrio/ddrio_inout.vhdl b/src/io/ddrio/ddrio_inout.vhdl index b8a11b2f..24806b2e 100644 --- a/src/io/ddrio/ddrio_inout.vhdl +++ b/src/io/ddrio/ddrio_inout.vhdl @@ -42,7 +42,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/ddrio/ddrio_inout_altera.vhdl b/src/io/ddrio/ddrio_inout_altera.vhdl index 94c8300d..d40ba6c1 100644 --- a/src/io/ddrio/ddrio_inout_altera.vhdl +++ b/src/io/ddrio/ddrio_inout_altera.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/ddrio/ddrio_inout_xilinx.vhdl b/src/io/ddrio/ddrio_inout_xilinx.vhdl index 37052639..5ea5d7f3 100644 --- a/src/io/ddrio/ddrio_inout_xilinx.vhdl +++ b/src/io/ddrio/ddrio_inout_xilinx.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/ddrio/ddrio_out.vhdl b/src/io/ddrio/ddrio_out.vhdl index 2131087c..77c7874b 100644 --- a/src/io/ddrio/ddrio_out.vhdl +++ b/src/io/ddrio/ddrio_out.vhdl @@ -29,7 +29,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/ddrio/ddrio_out_altera.vhdl b/src/io/ddrio/ddrio_out_altera.vhdl index 814fb955..e94408d5 100644 --- a/src/io/ddrio/ddrio_out_altera.vhdl +++ b/src/io/ddrio/ddrio_out_altera.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/ddrio/ddrio_out_xilinx.vhdl b/src/io/ddrio/ddrio_out_xilinx.vhdl index 3b0b5c69..8982b20a 100644 --- a/src/io/ddrio/ddrio_out_xilinx.vhdl +++ b/src/io/ddrio/ddrio_out_xilinx.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/io.pkg.vhdl b/src/io/io.pkg.vhdl index 457646af..bd692040 100644 --- a/src/io/io.pkg.vhdl +++ b/src/io/io.pkg.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/io_7SegmentMux_BCD.vhdl b/src/io/io_7SegmentMux_BCD.vhdl index 828fcb9a..86183775 100644 --- a/src/io/io_7SegmentMux_BCD.vhdl +++ b/src/io/io_7SegmentMux_BCD.vhdl @@ -16,7 +16,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/io_7SegmentMux_HEX.vhdl b/src/io/io_7SegmentMux_HEX.vhdl index 54248335..54047844 100644 --- a/src/io/io_7SegmentMux_HEX.vhdl +++ b/src/io/io_7SegmentMux_HEX.vhdl @@ -15,7 +15,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/io_Debounce.vhdl b/src/io/io_Debounce.vhdl index 80c21890..6f5aba8e 100644 --- a/src/io/io_Debounce.vhdl +++ b/src/io/io_Debounce.vhdl @@ -25,7 +25,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/io_FanControl.vhdl b/src/io/io_FanControl.vhdl index 840121f5..e06bdece 100644 --- a/src/io/io_FanControl.vhdl +++ b/src/io/io_FanControl.vhdl @@ -32,7 +32,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/io_FrequencyCounter.vhdl b/src/io/io_FrequencyCounter.vhdl index 63f12f97..d271cae0 100644 --- a/src/io/io_FrequencyCounter.vhdl +++ b/src/io/io_FrequencyCounter.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2014 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/io_GlitchFilter.vhdl b/src/io/io_GlitchFilter.vhdl index 75a92e8b..e46ff41c 100644 --- a/src/io/io_GlitchFilter.vhdl +++ b/src/io/io_GlitchFilter.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/io_KeyPadScanner.vhdl b/src/io/io_KeyPadScanner.vhdl index 3725c5fb..e0112934 100644 --- a/src/io/io_KeyPadScanner.vhdl +++ b/src/io/io_KeyPadScanner.vhdl @@ -17,7 +17,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/io_PulseWidthModulation.vhdl b/src/io/io_PulseWidthModulation.vhdl index dcbcc3e3..cdd8a051 100644 --- a/src/io/io_PulseWidthModulation.vhdl +++ b/src/io/io_PulseWidthModulation.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/io_TimingCounter.vhdl b/src/io/io_TimingCounter.vhdl index bda4aaba..642a854e 100644 --- a/src/io/io_TimingCounter.vhdl +++ b/src/io/io_TimingCounter.vhdl @@ -16,7 +16,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/pmod/pmod.pkg.vhdl b/src/io/pmod/pmod.pkg.vhdl index d2d7c786..e58638a2 100644 --- a/src/io/pmod/pmod.pkg.vhdl +++ b/src/io/pmod/pmod.pkg.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/pmod/pmod_KYPD.vhdl b/src/io/pmod/pmod_KYPD.vhdl index 1c243cde..ba2fc1b6 100644 --- a/src/io/pmod/pmod_KYPD.vhdl +++ b/src/io/pmod/pmod_KYPD.vhdl @@ -18,7 +18,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/pmod/pmod_SSD.vhdl b/src/io/pmod/pmod_SSD.vhdl index 291fb7c3..8ebc5826 100644 --- a/src/io/pmod/pmod_SSD.vhdl +++ b/src/io/pmod/pmod_SSD.vhdl @@ -26,7 +26,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/pmod/pmod_USBUART.vhdl b/src/io/pmod/pmod_USBUART.vhdl index c306ed40..b62b8a9c 100644 --- a/src/io/pmod/pmod_USBUART.vhdl +++ b/src/io/pmod/pmod_USBUART.vhdl @@ -16,7 +16,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/uart/uart.pkg.vhdl b/src/io/uart/uart.pkg.vhdl index 33d9a34c..669692b5 100644 --- a/src/io/uart/uart.pkg.vhdl +++ b/src/io/uart/uart.pkg.vhdl @@ -11,7 +11,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/uart/uart_bclk.vhdl b/src/io/uart/uart_bclk.vhdl index 6c75d937..0d42dcf5 100644 --- a/src/io/uart/uart_bclk.vhdl +++ b/src/io/uart/uart_bclk.vhdl @@ -20,7 +20,7 @@ -- License: -- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/uart/uart_fifo.vhdl b/src/io/uart/uart_fifo.vhdl index 48bb44c2..0c643b2f 100644 --- a/src/io/uart/uart_fifo.vhdl +++ b/src/io/uart/uart_fifo.vhdl @@ -22,7 +22,7 @@ -- License: -- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/uart/uart_ft245.vhdl b/src/io/uart/uart_ft245.vhdl index ff8ef8c4..8ebd89b4 100644 --- a/src/io/uart/uart_ft245.vhdl +++ b/src/io/uart/uart_ft245.vhdl @@ -15,7 +15,7 @@ -- License: -- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/uart/uart_rx.vhdl b/src/io/uart/uart_rx.vhdl index 51d4ff36..9c663ba6 100644 --- a/src/io/uart/uart_rx.vhdl +++ b/src/io/uart/uart_rx.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2008-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/io/uart/uart_tx.vhdl b/src/io/uart/uart_tx.vhdl index 1e2a9633..27445dc0 100644 --- a/src/io/uart/uart_tx.vhdl +++ b/src/io/uart/uart_tx.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl b/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl index 881c30bc..6e62941c 100644 --- a/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl +++ b/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl @@ -36,7 +36,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl b/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl index a558841e..f2539019 100644 --- a/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl +++ b/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl @@ -36,7 +36,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/mem/lut/lut_Sine.vhdl b/src/mem/lut/lut_Sine.vhdl index 708ff38d..9fa76d2c 100644 --- a/src/mem/lut/lut_Sine.vhdl +++ b/src/mem/lut/lut_Sine.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/mem/mem.pkg.vhdl b/src/mem/mem.pkg.vhdl index 54a329fd..3c804d06 100644 --- a/src/mem/mem.pkg.vhdl +++ b/src/mem/mem.pkg.vhdl @@ -17,7 +17,7 @@ -- License: -- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/mem/ocram/altera/ocram_sp_altera.vhdl b/src/mem/ocram/altera/ocram_sp_altera.vhdl index 5d66f7f1..88aeb930 100644 --- a/src/mem/ocram/altera/ocram_sp_altera.vhdl +++ b/src/mem/ocram/altera/ocram_sp_altera.vhdl @@ -18,7 +18,7 @@ -- License: -- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/mem/ocram/altera/ocram_tdp_altera.vhdl b/src/mem/ocram/altera/ocram_tdp_altera.vhdl index c9cb2532..23a1ccf6 100644 --- a/src/mem/ocram/altera/ocram_tdp_altera.vhdl +++ b/src/mem/ocram/altera/ocram_tdp_altera.vhdl @@ -18,7 +18,7 @@ -- License: -- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/mem/ocram/ocram.pkg.vhdl b/src/mem/ocram/ocram.pkg.vhdl index 11776b08..365f90f5 100644 --- a/src/mem/ocram/ocram.pkg.vhdl +++ b/src/mem/ocram/ocram.pkg.vhdl @@ -17,7 +17,7 @@ -- License: -- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/mem/ocram/ocram_esdp.vhdl b/src/mem/ocram/ocram_esdp.vhdl index 3f80baf2..82d4615d 100644 --- a/src/mem/ocram/ocram_esdp.vhdl +++ b/src/mem/ocram/ocram_esdp.vhdl @@ -68,7 +68,7 @@ -- License: -- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/mem/ocram/ocram_sdp.vhdl b/src/mem/ocram/ocram_sdp.vhdl index f06913a2..12a7d3b1 100644 --- a/src/mem/ocram/ocram_sdp.vhdl +++ b/src/mem/ocram/ocram_sdp.vhdl @@ -35,7 +35,7 @@ -- License: -- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/mem/ocram/ocram_sp.vhdl b/src/mem/ocram/ocram_sp.vhdl index fecbd731..63846c2a 100644 --- a/src/mem/ocram/ocram_sp.vhdl +++ b/src/mem/ocram/ocram_sp.vhdl @@ -37,7 +37,7 @@ -- License: -- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/mem/ocram/ocram_tdp.vhdl b/src/mem/ocram/ocram_tdp.vhdl index 517157a1..123ccd09 100644 --- a/src/mem/ocram/ocram_tdp.vhdl +++ b/src/mem/ocram/ocram_tdp.vhdl @@ -53,7 +53,7 @@ -- License: -- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/mem/ocrom/ocrom.pkg.vhdl b/src/mem/ocrom/ocrom.pkg.vhdl index 63cacbf9..86fd84ac 100644 --- a/src/mem/ocrom/ocrom.pkg.vhdl +++ b/src/mem/ocrom/ocrom.pkg.vhdl @@ -17,7 +17,7 @@ -- License: -- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/mem/ocrom/ocrom_dp.vhdl b/src/mem/ocrom/ocrom_dp.vhdl index e0779a9b..887a0963 100644 --- a/src/mem/ocrom/ocrom_dp.vhdl +++ b/src/mem/ocrom/ocrom_dp.vhdl @@ -25,7 +25,7 @@ -- License: -- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/mem/ocrom/ocrom_sp.vhdl b/src/mem/ocrom/ocrom_sp.vhdl index 90fc6cbb..7591b45a 100644 --- a/src/mem/ocrom/ocrom_sp.vhdl +++ b/src/mem/ocrom/ocrom_sp.vhdl @@ -18,7 +18,7 @@ -- License: -- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/mem/sdram/sdram_ctrl_de0.vhdl b/src/mem/sdram/sdram_ctrl_de0.vhdl index 5c048696..a5990ec3 100644 --- a/src/mem/sdram/sdram_ctrl_de0.vhdl +++ b/src/mem/sdram/sdram_ctrl_de0.vhdl @@ -43,7 +43,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/mem/sdram/sdram_ctrl_fsm.vhdl b/src/mem/sdram/sdram_ctrl_fsm.vhdl index 9184536a..2d196089 100644 --- a/src/mem/sdram/sdram_ctrl_fsm.vhdl +++ b/src/mem/sdram/sdram_ctrl_fsm.vhdl @@ -79,7 +79,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/mem/sdram/sdram_ctrl_phy_de0.vhdl b/src/mem/sdram/sdram_ctrl_phy_de0.vhdl index 3ffc7b34..d699c236 100644 --- a/src/mem/sdram/sdram_ctrl_phy_de0.vhdl +++ b/src/mem/sdram/sdram_ctrl_phy_de0.vhdl @@ -45,7 +45,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl b/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl index 084ea664..4cd652c2 100644 --- a/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl +++ b/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl @@ -83,7 +83,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/mem/sdram/sdram_ctrl_s3esk.vhdl b/src/mem/sdram/sdram_ctrl_s3esk.vhdl index cf0e43f5..27bd1aff 100644 --- a/src/mem/sdram/sdram_ctrl_s3esk.vhdl +++ b/src/mem/sdram/sdram_ctrl_s3esk.vhdl @@ -44,7 +44,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/filter/filter_and.vhdl b/src/misc/filter/filter_and.vhdl index 50198d9a..c226a7f0 100644 --- a/src/misc/filter/filter_and.vhdl +++ b/src/misc/filter/filter_and.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2014 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/filter/filter_mean.vhdl b/src/misc/filter/filter_mean.vhdl index bb9e09c9..c1cd12e4 100644 --- a/src/misc/filter/filter_mean.vhdl +++ b/src/misc/filter/filter_mean.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2014 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/filter/filter_or.vhdl b/src/misc/filter/filter_or.vhdl index 1107ee7d..aebdf664 100644 --- a/src/misc/filter/filter_or.vhdl +++ b/src/misc/filter/filter_or.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2014 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/gearbox/gearbox_down_cc.vhdl b/src/misc/gearbox/gearbox_down_cc.vhdl index f7025ae2..2f5d7ac2 100644 --- a/src/misc/gearbox/gearbox_down_cc.vhdl +++ b/src/misc/gearbox/gearbox_down_cc.vhdl @@ -17,7 +17,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/gearbox/gearbox_down_dc.vhdl b/src/misc/gearbox/gearbox_down_dc.vhdl index eff98181..a68a4d0e 100644 --- a/src/misc/gearbox/gearbox_down_dc.vhdl +++ b/src/misc/gearbox/gearbox_down_dc.vhdl @@ -22,7 +22,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/gearbox/gearbox_up_cc.vhdl b/src/misc/gearbox/gearbox_up_cc.vhdl index d90f8d82..e3c34051 100644 --- a/src/misc/gearbox/gearbox_up_cc.vhdl +++ b/src/misc/gearbox/gearbox_up_cc.vhdl @@ -17,7 +17,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/gearbox/gearbox_up_dc.vhdl b/src/misc/gearbox/gearbox_up_dc.vhdl index 9345ea59..0e451df3 100644 --- a/src/misc/gearbox/gearbox_up_dc.vhdl +++ b/src/misc/gearbox/gearbox_up_dc.vhdl @@ -23,7 +23,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/misc_Delay.vhdl b/src/misc/misc_Delay.vhdl index 64c296d0..2f98d094 100644 --- a/src/misc/misc_Delay.vhdl +++ b/src/misc/misc_Delay.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/misc_FrequencyMeasurement.vhdl b/src/misc/misc_FrequencyMeasurement.vhdl index b9dddfb2..2d4a7df3 100644 --- a/src/misc/misc_FrequencyMeasurement.vhdl +++ b/src/misc/misc_FrequencyMeasurement.vhdl @@ -15,7 +15,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/stat/stat_Average.vhdl b/src/misc/stat/stat_Average.vhdl index ef65907b..b29a09f1 100644 --- a/src/misc/stat/stat_Average.vhdl +++ b/src/misc/stat/stat_Average.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/stat/stat_Histogram.vhdl b/src/misc/stat/stat_Histogram.vhdl index e7a5fbb6..01e20119 100644 --- a/src/misc/stat/stat_Histogram.vhdl +++ b/src/misc/stat/stat_Histogram.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/stat/stat_Maximum.vhdl b/src/misc/stat/stat_Maximum.vhdl index 0fec5823..fa2d4990 100644 --- a/src/misc/stat/stat_Maximum.vhdl +++ b/src/misc/stat/stat_Maximum.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/stat/stat_Minimum.vhdl b/src/misc/stat/stat_Minimum.vhdl index 5651278c..a3c5f8bb 100644 --- a/src/misc/stat/stat_Minimum.vhdl +++ b/src/misc/stat/stat_Minimum.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/sync/sync.pkg.vhdl b/src/misc/sync/sync.pkg.vhdl index 792021d4..7623da0d 100644 --- a/src/misc/sync/sync.pkg.vhdl +++ b/src/misc/sync/sync.pkg.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/sync/sync_Bits.vhdl b/src/misc/sync/sync_Bits.vhdl index e5668c5a..05f5e167 100644 --- a/src/misc/sync/sync_Bits.vhdl +++ b/src/misc/sync/sync_Bits.vhdl @@ -41,7 +41,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/sync/sync_Bits_Altera.vhdl b/src/misc/sync/sync_Bits_Altera.vhdl index 060aed89..b2707f22 100644 --- a/src/misc/sync/sync_Bits_Altera.vhdl +++ b/src/misc/sync/sync_Bits_Altera.vhdl @@ -22,7 +22,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/sync/sync_Bits_Xilinx.vhdl b/src/misc/sync/sync_Bits_Xilinx.vhdl index fb5278d7..c3d17c4f 100644 --- a/src/misc/sync/sync_Bits_Xilinx.vhdl +++ b/src/misc/sync/sync_Bits_Xilinx.vhdl @@ -43,7 +43,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/sync/sync_Command.vhdl b/src/misc/sync/sync_Command.vhdl index 85516c59..05f9d0cb 100644 --- a/src/misc/sync/sync_Command.vhdl +++ b/src/misc/sync/sync_Command.vhdl @@ -24,7 +24,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/sync/sync_Pulse.vhdl b/src/misc/sync/sync_Pulse.vhdl index 64aff09d..eb6f9189 100644 --- a/src/misc/sync/sync_Pulse.vhdl +++ b/src/misc/sync/sync_Pulse.vhdl @@ -41,7 +41,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/sync/sync_Pulse_Altera.vhdl b/src/misc/sync/sync_Pulse_Altera.vhdl index 82cd9165..9870bed9 100644 --- a/src/misc/sync/sync_Pulse_Altera.vhdl +++ b/src/misc/sync/sync_Pulse_Altera.vhdl @@ -25,7 +25,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/sync/sync_Pulse_Xilinx.vhdl b/src/misc/sync/sync_Pulse_Xilinx.vhdl index 9505e2d9..c19691b1 100644 --- a/src/misc/sync/sync_Pulse_Xilinx.vhdl +++ b/src/misc/sync/sync_Pulse_Xilinx.vhdl @@ -44,7 +44,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/sync/sync_Reset.vhdl b/src/misc/sync/sync_Reset.vhdl index d5f7fb1f..ee1e77d5 100644 --- a/src/misc/sync/sync_Reset.vhdl +++ b/src/misc/sync/sync_Reset.vhdl @@ -33,7 +33,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/sync/sync_Reset_Altera.vhdl b/src/misc/sync/sync_Reset_Altera.vhdl index ea130fd2..eab1b4a2 100644 --- a/src/misc/sync/sync_Reset_Altera.vhdl +++ b/src/misc/sync/sync_Reset_Altera.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/sync/sync_Reset_Xilinx.vhdl b/src/misc/sync/sync_Reset_Xilinx.vhdl index 4ca69ea8..0ee610ee 100644 --- a/src/misc/sync/sync_Reset_Xilinx.vhdl +++ b/src/misc/sync/sync_Reset_Xilinx.vhdl @@ -26,7 +26,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/sync/sync_Strobe.vhdl b/src/misc/sync/sync_Strobe.vhdl index b7a58471..cdf9427c 100644 --- a/src/misc/sync/sync_Strobe.vhdl +++ b/src/misc/sync/sync_Strobe.vhdl @@ -29,7 +29,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/sync/sync_Vector.vhdl b/src/misc/sync/sync_Vector.vhdl index 122ff1f5..25ee37cb 100644 --- a/src/misc/sync/sync_Vector.vhdl +++ b/src/misc/sync/sync_Vector.vhdl @@ -23,7 +23,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/arp/arp_BroadCast_Receiver.vhdl b/src/net/arp/arp_BroadCast_Receiver.vhdl index ef3ff7ba..3c132fb8 100644 --- a/src/net/arp/arp_BroadCast_Receiver.vhdl +++ b/src/net/arp/arp_BroadCast_Receiver.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/arp/arp_BroadCast_Requester.vhdl b/src/net/arp/arp_BroadCast_Requester.vhdl index 8c4093ea..d87662b8 100644 --- a/src/net/arp/arp_BroadCast_Requester.vhdl +++ b/src/net/arp/arp_BroadCast_Requester.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/arp/arp_Cache.vhdl b/src/net/arp/arp_Cache.vhdl index 4a2aa693..39e2e841 100644 --- a/src/net/arp/arp_Cache.vhdl +++ b/src/net/arp/arp_Cache.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/arp/arp_IPPool.vhdl b/src/net/arp/arp_IPPool.vhdl index a2c98d6c..4089a4a9 100644 --- a/src/net/arp/arp_IPPool.vhdl +++ b/src/net/arp/arp_IPPool.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/arp/arp_UniCast_Receiver.vhdl b/src/net/arp/arp_UniCast_Receiver.vhdl index 8ec0f2d5..1182071a 100644 --- a/src/net/arp/arp_UniCast_Receiver.vhdl +++ b/src/net/arp/arp_UniCast_Receiver.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/arp/arp_UniCast_Responder.vhdl b/src/net/arp/arp_UniCast_Responder.vhdl index 4a2202fd..0a65c9d3 100644 --- a/src/net/arp/arp_UniCast_Responder.vhdl +++ b/src/net/arp/arp_UniCast_Responder.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/arp/arp_Wrapper.vhdl b/src/net/arp/arp_Wrapper.vhdl index 0cfa0463..c03ee27a 100644 --- a/src/net/arp/arp_Wrapper.vhdl +++ b/src/net/arp/arp_Wrapper.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/icmpv4/icmpv4_RX.vhdl b/src/net/icmpv4/icmpv4_RX.vhdl index d21a2cef..88de084f 100644 --- a/src/net/icmpv4/icmpv4_RX.vhdl +++ b/src/net/icmpv4/icmpv4_RX.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/icmpv4/icmpv4_TX.vhdl b/src/net/icmpv4/icmpv4_TX.vhdl index 968eb7f0..40a1f0bc 100644 --- a/src/net/icmpv4/icmpv4_TX.vhdl +++ b/src/net/icmpv4/icmpv4_TX.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/icmpv4/icmpv4_Wrapper.vhdl b/src/net/icmpv4/icmpv4_Wrapper.vhdl index c830fd19..0f2593c5 100644 --- a/src/net/icmpv4/icmpv4_Wrapper.vhdl +++ b/src/net/icmpv4/icmpv4_Wrapper.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/ipv4/ipv4_FrameLoopback.vhdl b/src/net/ipv4/ipv4_FrameLoopback.vhdl index 576e358f..2fff1a5b 100644 --- a/src/net/ipv4/ipv4_FrameLoopback.vhdl +++ b/src/net/ipv4/ipv4_FrameLoopback.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/ipv4/ipv4_RX.vhdl b/src/net/ipv4/ipv4_RX.vhdl index a49c4ea1..b4e7dcb6 100644 --- a/src/net/ipv4/ipv4_RX.vhdl +++ b/src/net/ipv4/ipv4_RX.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/ipv4/ipv4_TX.vhdl b/src/net/ipv4/ipv4_TX.vhdl index 328c4c8d..e318ac15 100644 --- a/src/net/ipv4/ipv4_TX.vhdl +++ b/src/net/ipv4/ipv4_TX.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/ipv4/ipv4_Wrapper.vhdl b/src/net/ipv4/ipv4_Wrapper.vhdl index 23cc65e3..6227e76e 100644 --- a/src/net/ipv4/ipv4_Wrapper.vhdl +++ b/src/net/ipv4/ipv4_Wrapper.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/ipv6/ipv6_FrameLoopback.vhdl b/src/net/ipv6/ipv6_FrameLoopback.vhdl index 9de601dd..87bf7e04 100644 --- a/src/net/ipv6/ipv6_FrameLoopback.vhdl +++ b/src/net/ipv6/ipv6_FrameLoopback.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/ipv6/ipv6_RX.vhdl b/src/net/ipv6/ipv6_RX.vhdl index 7f871366..d4459e9d 100644 --- a/src/net/ipv6/ipv6_RX.vhdl +++ b/src/net/ipv6/ipv6_RX.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/ipv6/ipv6_TX.vhdl b/src/net/ipv6/ipv6_TX.vhdl index 982837e5..a53ee9d5 100644 --- a/src/net/ipv6/ipv6_TX.vhdl +++ b/src/net/ipv6/ipv6_TX.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/ipv6/ipv6_Wrapper.vhdl b/src/net/ipv6/ipv6_Wrapper.vhdl index fd52f561..9ff501dd 100644 --- a/src/net/ipv6/ipv6_Wrapper.vhdl +++ b/src/net/ipv6/ipv6_Wrapper.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/mac/mac_FrameLoopback.vhdl b/src/net/mac/mac_FrameLoopback.vhdl index 6655dd4b..9264e952 100644 --- a/src/net/mac/mac_FrameLoopback.vhdl +++ b/src/net/mac/mac_FrameLoopback.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/mac/mac_RX_DestMAC_Switch.vhdl b/src/net/mac/mac_RX_DestMAC_Switch.vhdl index 358ca465..eb41e0ed 100644 --- a/src/net/mac/mac_RX_DestMAC_Switch.vhdl +++ b/src/net/mac/mac_RX_DestMAC_Switch.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/mac/mac_RX_SrcMAC_Filter.vhdl b/src/net/mac/mac_RX_SrcMAC_Filter.vhdl index bbb838fb..aa83ba17 100644 --- a/src/net/mac/mac_RX_SrcMAC_Filter.vhdl +++ b/src/net/mac/mac_RX_SrcMAC_Filter.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/mac/mac_RX_Type_Switch.vhdl b/src/net/mac/mac_RX_Type_Switch.vhdl index 23d4cac0..072970dc 100644 --- a/src/net/mac/mac_RX_Type_Switch.vhdl +++ b/src/net/mac/mac_RX_Type_Switch.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/mac/mac_TX_DestMAC_Prepender.vhdl b/src/net/mac/mac_TX_DestMAC_Prepender.vhdl index 7117b9bd..e81baa2d 100644 --- a/src/net/mac/mac_TX_DestMAC_Prepender.vhdl +++ b/src/net/mac/mac_TX_DestMAC_Prepender.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/mac/mac_TX_SrcMAC_Prepender.vhdl b/src/net/mac/mac_TX_SrcMAC_Prepender.vhdl index ff70cafc..d709a310 100644 --- a/src/net/mac/mac_TX_SrcMAC_Prepender.vhdl +++ b/src/net/mac/mac_TX_SrcMAC_Prepender.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/mac/mac_Wrapper.vhdl b/src/net/mac/mac_Wrapper.vhdl index fcd42e3a..f46763b8 100644 --- a/src/net/mac/mac_Wrapper.vhdl +++ b/src/net/mac/mac_Wrapper.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/net.pkg.vhdl b/src/net/net.pkg.vhdl index 96aa291b..ed9745ee 100644 --- a/src/net/net.pkg.vhdl +++ b/src/net/net.pkg.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/net_FrameChecksum.vhdl b/src/net/net_FrameChecksum.vhdl index c63d632a..b8bed727 100644 --- a/src/net/net_FrameChecksum.vhdl +++ b/src/net/net_FrameChecksum.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/net_FrameLoopback.vhdl b/src/net/net_FrameLoopback.vhdl index f57940c5..381a56b9 100644 --- a/src/net/net_FrameLoopback.vhdl +++ b/src/net/net_FrameLoopback.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/udp/udp_FrameLoopback.vhdl b/src/net/udp/udp_FrameLoopback.vhdl index defd96dc..bbf4ec72 100644 --- a/src/net/udp/udp_FrameLoopback.vhdl +++ b/src/net/udp/udp_FrameLoopback.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/udp/udp_RX.vhdl b/src/net/udp/udp_RX.vhdl index febd624d..16ae6f71 100644 --- a/src/net/udp/udp_RX.vhdl +++ b/src/net/udp/udp_RX.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/udp/udp_TX.vhdl b/src/net/udp/udp_TX.vhdl index 96c32444..850cf9d1 100644 --- a/src/net/udp/udp_TX.vhdl +++ b/src/net/udp/udp_TX.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/net/udp/udp_Wrapper.vhdl b/src/net/udp/udp_Wrapper.vhdl index 6c5acd3b..99f8f3e0 100644 --- a/src/net/udp/udp_Wrapper.vhdl +++ b/src/net/udp/udp_Wrapper.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/sim/sim_global.v08.vhdl b/src/sim/sim_global.v08.vhdl index 9d706a4b..02ebe003 100644 --- a/src/sim/sim_global.v08.vhdl +++ b/src/sim/sim_global.v08.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/sim/sim_global.v93.vhdl b/src/sim/sim_global.v93.vhdl index d3a594f7..0d4faeb3 100644 --- a/src/sim/sim_global.v93.vhdl +++ b/src/sim/sim_global.v93.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/sim/sim_protected.v08.vhdl b/src/sim/sim_protected.v08.vhdl index 90f01159..64b9568b 100644 --- a/src/sim/sim_protected.v08.vhdl +++ b/src/sim/sim_protected.v08.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/sim/sim_random.v08.vhdl b/src/sim/sim_random.v08.vhdl index ffc7a71f..b368ce8c 100644 --- a/src/sim/sim_random.v08.vhdl +++ b/src/sim/sim_random.v08.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/sim/sim_random.v93.vhdl b/src/sim/sim_random.v93.vhdl index 30df741f..60133790 100644 --- a/src/sim/sim_random.v93.vhdl +++ b/src/sim/sim_random.v93.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/sim/sim_simulation.v08.vhdl b/src/sim/sim_simulation.v08.vhdl index 6eec27c4..81a964b9 100644 --- a/src/sim/sim_simulation.v08.vhdl +++ b/src/sim/sim_simulation.v08.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/sim/sim_simulation.v93.vhdl b/src/sim/sim_simulation.v93.vhdl index e418fb15..aafd9644 100644 --- a/src/sim/sim_simulation.v93.vhdl +++ b/src/sim/sim_simulation.v93.vhdl @@ -15,7 +15,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/sim/sim_types.vhdl b/src/sim/sim_types.vhdl index d8fa1f68..332cd4e1 100644 --- a/src/sim/sim_types.vhdl +++ b/src/sim/sim_types.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/sim/sim_unprotected.v93.vhdl b/src/sim/sim_unprotected.v93.vhdl index 10a095cd..dfabf84a 100644 --- a/src/sim/sim_unprotected.v93.vhdl +++ b/src/sim/sim_unprotected.v93.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/sim/sim_waveform.vhdl b/src/sim/sim_waveform.vhdl index 4842ca53..3c70eeac 100644 --- a/src/sim/sim_waveform.vhdl +++ b/src/sim/sim_waveform.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/sort/sort_lru_cache.vhdl b/src/sort/sort_lru_cache.vhdl index 85e11403..b6671a56 100644 --- a/src/sort/sort_lru_cache.vhdl +++ b/src/sort/sort_lru_cache.vhdl @@ -28,7 +28,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/sort/sort_lru_list.vhdl b/src/sort/sort_lru_list.vhdl index 66ea7078..7277c142 100644 --- a/src/sort/sort_lru_list.vhdl +++ b/src/sort/sort_lru_list.vhdl @@ -26,7 +26,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/sort/sortnet/sortnet.pkg.vhdl b/src/sort/sortnet/sortnet.pkg.vhdl index 2a504a31..ea8cb441 100644 --- a/src/sort/sortnet/sortnet.pkg.vhdl +++ b/src/sort/sortnet/sortnet.pkg.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/sort/sortnet/sortnet_BitonicSort.vhdl b/src/sort/sortnet/sortnet_BitonicSort.vhdl index cb4641fd..1f945434 100644 --- a/src/sort/sortnet/sortnet_BitonicSort.vhdl +++ b/src/sort/sortnet/sortnet_BitonicSort.vhdl @@ -16,7 +16,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/sort/sortnet/sortnet_MergeSort_Streamed.vhdl b/src/sort/sortnet/sortnet_MergeSort_Streamed.vhdl index 0c8debae..855b4129 100644 --- a/src/sort/sortnet/sortnet_MergeSort_Streamed.vhdl +++ b/src/sort/sortnet/sortnet_MergeSort_Streamed.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/sort/sortnet/sortnet_OddEvenMergeSort.vhdl b/src/sort/sortnet/sortnet_OddEvenMergeSort.vhdl index 9fe3866d..5bc68056 100644 --- a/src/sort/sortnet/sortnet_OddEvenMergeSort.vhdl +++ b/src/sort/sortnet/sortnet_OddEvenMergeSort.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/sort/sortnet/sortnet_OddEvenSort.vhdl b/src/sort/sortnet/sortnet_OddEvenSort.vhdl index 7517134c..b79a5495 100644 --- a/src/sort/sortnet/sortnet_OddEvenSort.vhdl +++ b/src/sort/sortnet/sortnet_OddEvenSort.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/sort/sortnet/sortnet_Stream_Adapter.vhdl b/src/sort/sortnet/sortnet_Stream_Adapter.vhdl index e3dc377b..673dbc22 100644 --- a/src/sort/sortnet/sortnet_Stream_Adapter.vhdl +++ b/src/sort/sortnet/sortnet_Stream_Adapter.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/sort/sortnet/sortnet_Stream_Adapter2.vhdl b/src/sort/sortnet/sortnet_Stream_Adapter2.vhdl index cf6e88c4..c2eca86c 100644 --- a/src/sort/sortnet/sortnet_Stream_Adapter2.vhdl +++ b/src/sort/sortnet/sortnet_Stream_Adapter2.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/sort/sortnet/sortnet_Transform.vhdl b/src/sort/sortnet/sortnet_Transform.vhdl index ce9abc5b..f45db3f3 100644 --- a/src/sort/sortnet/sortnet_Transform.vhdl +++ b/src/sort/sortnet/sortnet_Transform.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/xil/reconfig/reconfig_icap_fsm.vhdl b/src/xil/reconfig/reconfig_icap_fsm.vhdl index 717b065a..f22deec9 100644 --- a/src/xil/reconfig/reconfig_icap_fsm.vhdl +++ b/src/xil/reconfig/reconfig_icap_fsm.vhdl @@ -17,7 +17,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/xil/reconfig/reconfig_icap_wrapper.vhdl b/src/xil/reconfig/reconfig_icap_wrapper.vhdl index a8a8b89f..5ebcf109 100644 --- a/src/xil/reconfig/reconfig_icap_wrapper.vhdl +++ b/src/xil/reconfig/reconfig_icap_wrapper.vhdl @@ -16,7 +16,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/xil/xil.pkg.vhdl b/src/xil/xil.pkg.vhdl index dc0368fd..7e5937dd 100644 --- a/src/xil/xil.pkg.vhdl +++ b/src/xil/xil.pkg.vhdl @@ -19,7 +19,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/xil/xil_BSCAN.vhdl b/src/xil/xil_BSCAN.vhdl index 8ccf5753..c92c6671 100644 --- a/src/xil/xil_BSCAN.vhdl +++ b/src/xil/xil_BSCAN.vhdl @@ -18,7 +18,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/xil/xil_ChipScopeICON.vhdl b/src/xil/xil_ChipScopeICON.vhdl index 999665ac..8e31ba0e 100644 --- a/src/xil/xil_ChipScopeICON.vhdl +++ b/src/xil/xil_ChipScopeICON.vhdl @@ -30,7 +30,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/xil/xil_ICAP.vhdl b/src/xil/xil_ICAP.vhdl index 5ee6828a..85b67625 100644 --- a/src/xil/xil_ICAP.vhdl +++ b/src/xil/xil_ICAP.vhdl @@ -18,7 +18,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/xil/xil_Reconfigurator.vhdl b/src/xil/xil_Reconfigurator.vhdl index ad6dc57e..a81a7079 100644 --- a/src/xil/xil_Reconfigurator.vhdl +++ b/src/xil/xil_Reconfigurator.vhdl @@ -21,7 +21,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/xil/xil_SystemMonitor_Series7.vhdl b/src/xil/xil_SystemMonitor_Series7.vhdl index 43c4b8cd..e2cf1174 100644 --- a/src/xil/xil_SystemMonitor_Series7.vhdl +++ b/src/xil/xil_SystemMonitor_Series7.vhdl @@ -30,7 +30,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/xil/xil_SystemMonitor_Virtex6.vhdl b/src/xil/xil_SystemMonitor_Virtex6.vhdl index a482932e..2a5cff37 100644 --- a/src/xil/xil_SystemMonitor_Virtex6.vhdl +++ b/src/xil/xil_SystemMonitor_Virtex6.vhdl @@ -30,7 +30,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/arith_addw_tb.vhdl b/tb/arith/arith_addw_tb.vhdl index 5b6d16f2..918e1dbf 100644 --- a/tb/arith/arith_addw_tb.vhdl +++ b/tb/arith/arith_addw_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================ -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/arith_convert_bin2bcd_tb.vhdl b/tb/arith/arith_convert_bin2bcd_tb.vhdl index ac48e544..85b654e7 100644 --- a/tb/arith/arith_convert_bin2bcd_tb.vhdl +++ b/tb/arith/arith_convert_bin2bcd_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/arith_counter_bcd_tb.vhdl b/tb/arith/arith_counter_bcd_tb.vhdl index a21f83e5..d7490b52 100644 --- a/tb/arith/arith_counter_bcd_tb.vhdl +++ b/tb/arith/arith_counter_bcd_tb.vhdl @@ -15,7 +15,7 @@ -- License: -- ============================================================================ -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/arith_div_tb.vhdl b/tb/arith/arith_div_tb.vhdl index c7a855e2..e129ad58 100644 --- a/tb/arith/arith_div_tb.vhdl +++ b/tb/arith/arith_div_tb.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/arith_firstone_tb.vhdl b/tb/arith/arith_firstone_tb.vhdl index aa7ae153..f2fefb87 100644 --- a/tb/arith/arith_firstone_tb.vhdl +++ b/tb/arith/arith_firstone_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/arith_prefix_and_tb.vhdl b/tb/arith/arith_prefix_and_tb.vhdl index 4c32dbf9..3f8c62a8 100644 --- a/tb/arith/arith_prefix_and_tb.vhdl +++ b/tb/arith/arith_prefix_and_tb.vhdl @@ -15,7 +15,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/arith_prefix_or_tb.vhdl b/tb/arith/arith_prefix_or_tb.vhdl index 3afced7b..f0a52894 100644 --- a/tb/arith/arith_prefix_or_tb.vhdl +++ b/tb/arith/arith_prefix_or_tb.vhdl @@ -15,7 +15,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/arith_prng_tb.vhdl b/tb/arith/arith_prng_tb.vhdl index 37a03a22..ddb4b4c2 100644 --- a/tb/arith/arith_prng_tb.vhdl +++ b/tb/arith/arith_prng_tb.vhdl @@ -16,7 +16,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/arith_scaler_tb.vhdl b/tb/arith/arith_scaler_tb.vhdl index 06354cf6..7c4d0230 100644 --- a/tb/arith/arith_scaler_tb.vhdl +++ b/tb/arith/arith_scaler_tb.vhdl @@ -9,7 +9,7 @@ -- ------------------------------------------------------------------------------- -- Copyright 2007-2016 Technische Universität Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/cache/cache_par_cocotb.py b/tb/cache/cache_par_cocotb.py index 19642118..62a70aca 100644 --- a/tb/cache/cache_par_cocotb.py +++ b/tb/cache/cache_par_cocotb.py @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/common/config_tb.vhdl b/tb/common/config_tb.vhdl index 31291c44..1b9ab0f8 100644 --- a/tb/common/config_tb.vhdl +++ b/tb/common/config_tb.vhdl @@ -15,7 +15,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/common/lru_dict.py b/tb/common/lru_dict.py index 2bfda85b..c1ef57fb 100644 --- a/tb/common/lru_dict.py +++ b/tb/common/lru_dict.py @@ -18,7 +18,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/common/my_config_AC701.vhdl b/tb/common/my_config_AC701.vhdl index 68587376..a9f2e348 100644 --- a/tb/common/my_config_AC701.vhdl +++ b/tb/common/my_config_AC701.vhdl @@ -17,7 +17,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/common/my_config_Atlys.vhdl b/tb/common/my_config_Atlys.vhdl index 41648244..6b04525f 100644 --- a/tb/common/my_config_Atlys.vhdl +++ b/tb/common/my_config_Atlys.vhdl @@ -17,7 +17,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/common/my_config_DE0.vhdl b/tb/common/my_config_DE0.vhdl index 87286302..03bbbaaa 100644 --- a/tb/common/my_config_DE0.vhdl +++ b/tb/common/my_config_DE0.vhdl @@ -17,7 +17,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/common/my_config_DE4.vhdl b/tb/common/my_config_DE4.vhdl index b3eb6f41..ddcc658d 100644 --- a/tb/common/my_config_DE4.vhdl +++ b/tb/common/my_config_DE4.vhdl @@ -17,7 +17,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/common/my_config_DE5.vhdl b/tb/common/my_config_DE5.vhdl index d959c567..d6c1d88b 100644 --- a/tb/common/my_config_DE5.vhdl +++ b/tb/common/my_config_DE5.vhdl @@ -17,7 +17,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/common/my_config_ECP5Versa.vhdl b/tb/common/my_config_ECP5Versa.vhdl index 05294d26..19833365 100644 --- a/tb/common/my_config_ECP5Versa.vhdl +++ b/tb/common/my_config_ECP5Versa.vhdl @@ -17,7 +17,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/common/my_config_GENERIC.vhdl b/tb/common/my_config_GENERIC.vhdl index 024bed05..1acc3a28 100644 --- a/tb/common/my_config_GENERIC.vhdl +++ b/tb/common/my_config_GENERIC.vhdl @@ -15,7 +15,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/common/my_config_KC705.vhdl b/tb/common/my_config_KC705.vhdl index 2d470bdf..9308f68f 100644 --- a/tb/common/my_config_KC705.vhdl +++ b/tb/common/my_config_KC705.vhdl @@ -17,7 +17,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/common/my_config_ML505.vhdl b/tb/common/my_config_ML505.vhdl index 78488af9..aa235b0a 100644 --- a/tb/common/my_config_ML505.vhdl +++ b/tb/common/my_config_ML505.vhdl @@ -17,7 +17,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/common/my_config_ML506.vhdl b/tb/common/my_config_ML506.vhdl index ffbddb7a..eea8a816 100644 --- a/tb/common/my_config_ML506.vhdl +++ b/tb/common/my_config_ML506.vhdl @@ -23,7 +23,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/common/my_config_ML605.vhdl b/tb/common/my_config_ML605.vhdl index 5b7e3573..04700114 100644 --- a/tb/common/my_config_ML605.vhdl +++ b/tb/common/my_config_ML605.vhdl @@ -17,7 +17,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/common/my_config_S2GXAV.vhdl b/tb/common/my_config_S2GXAV.vhdl index cdc9651a..527b7d35 100644 --- a/tb/common/my_config_S2GXAV.vhdl +++ b/tb/common/my_config_S2GXAV.vhdl @@ -17,7 +17,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/common/my_config_S3SK1000.vhdl b/tb/common/my_config_S3SK1000.vhdl index cbd8c2a5..807cb62d 100644 --- a/tb/common/my_config_S3SK1000.vhdl +++ b/tb/common/my_config_S3SK1000.vhdl @@ -25,7 +25,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/common/my_config_VC707.vhdl b/tb/common/my_config_VC707.vhdl index 95641bdc..7fa35c8d 100644 --- a/tb/common/my_config_VC707.vhdl +++ b/tb/common/my_config_VC707.vhdl @@ -17,7 +17,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/common/my_config_VC709.vhdl b/tb/common/my_config_VC709.vhdl index 5a3b5972..479572b8 100644 --- a/tb/common/my_config_VC709.vhdl +++ b/tb/common/my_config_VC709.vhdl @@ -17,7 +17,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/common/my_config_XUPV5.vhdl b/tb/common/my_config_XUPV5.vhdl index 1ad4698c..da9a799c 100644 --- a/tb/common/my_config_XUPV5.vhdl +++ b/tb/common/my_config_XUPV5.vhdl @@ -23,7 +23,7 @@ -- License: -- =========================================================================== -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/common/my_config_ZC706.vhdl b/tb/common/my_config_ZC706.vhdl index 73419598..d28154ec 100644 --- a/tb/common/my_config_ZC706.vhdl +++ b/tb/common/my_config_ZC706.vhdl @@ -17,7 +17,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/common/my_config_ZedBoard.vhdl b/tb/common/my_config_ZedBoard.vhdl index 8e983364..c4bf2059 100644 --- a/tb/common/my_config_ZedBoard.vhdl +++ b/tb/common/my_config_ZedBoard.vhdl @@ -17,7 +17,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/common/physical_tb.vhdl b/tb/common/physical_tb.vhdl index 5890443f..38fac959 100644 --- a/tb/common/physical_tb.vhdl +++ b/tb/common/physical_tb.vhdl @@ -15,7 +15,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/common/strings_tb.vhdl b/tb/common/strings_tb.vhdl index 446530ee..bcc51fb4 100644 --- a/tb/common/strings_tb.vhdl +++ b/tb/common/strings_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/common/utils.py b/tb/common/utils.py index 41fa90ac..c1aab3e1 100644 --- a/tb/common/utils.py +++ b/tb/common/utils.py @@ -19,7 +19,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/dstruct/dstruct_deque_tb.vhdl b/tb/dstruct/dstruct_deque_tb.vhdl index a15be47e..4ab0c163 100644 --- a/tb/dstruct/dstruct_deque_tb.vhdl +++ b/tb/dstruct/dstruct_deque_tb.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================ -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/dstruct/dstruct_stack_tb.vhdl b/tb/dstruct/dstruct_stack_tb.vhdl index bc269f3b..a4e22d98 100644 --- a/tb/dstruct/dstruct_stack_tb.vhdl +++ b/tb/dstruct/dstruct_stack_tb.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================ -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/fifo/fifo_cc_got_tb.vhdl b/tb/fifo/fifo_cc_got_tb.vhdl index 8a8585c1..f14c7da2 100644 --- a/tb/fifo/fifo_cc_got_tb.vhdl +++ b/tb/fifo/fifo_cc_got_tb.vhdl @@ -15,7 +15,7 @@ -- License: -- ============================================================================ -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/fifo/fifo_cc_got_tempput_tb.vhdl b/tb/fifo/fifo_cc_got_tempput_tb.vhdl index f44c7367..94f6b36a 100644 --- a/tb/fifo/fifo_cc_got_tempput_tb.vhdl +++ b/tb/fifo/fifo_cc_got_tempput_tb.vhdl @@ -15,7 +15,7 @@ -- License: -- ============================================================================ -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/fifo/fifo_ic_assembly_tb.vhdl b/tb/fifo/fifo_ic_assembly_tb.vhdl index 3b7b33a8..6c319e9e 100644 --- a/tb/fifo/fifo_ic_assembly_tb.vhdl +++ b/tb/fifo/fifo_ic_assembly_tb.vhdl @@ -10,7 +10,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/fifo/fifo_ic_got_tb.vhdl b/tb/fifo/fifo_ic_got_tb.vhdl index 8f169037..d2900d89 100644 --- a/tb/fifo/fifo_ic_got_tb.vhdl +++ b/tb/fifo/fifo_ic_got_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/io/ddrio/ddrio_in_tb.vhdl b/tb/io/ddrio/ddrio_in_tb.vhdl index fceb9144..624a4951 100644 --- a/tb/io/ddrio/ddrio_in_tb.vhdl +++ b/tb/io/ddrio/ddrio_in_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================ -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/io/ddrio/ddrio_inout_tb.vhdl b/tb/io/ddrio/ddrio_inout_tb.vhdl index a79c1273..57b6c942 100644 --- a/tb/io/ddrio/ddrio_inout_tb.vhdl +++ b/tb/io/ddrio/ddrio_inout_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================ -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/io/ddrio/ddrio_out_tb.vhdl b/tb/io/ddrio/ddrio_out_tb.vhdl index 234d99f9..78d7bacf 100644 --- a/tb/io/ddrio/ddrio_out_tb.vhdl +++ b/tb/io/ddrio/ddrio_out_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================ -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/io/io_Debounce_tb.vhdl b/tb/io/io_Debounce_tb.vhdl index ebd846dd..79fcc0d5 100644 --- a/tb/io/io_Debounce_tb.vhdl +++ b/tb/io/io_Debounce_tb.vhdl @@ -15,7 +15,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/io/uart/uart_rx_tb.vhdl b/tb/io/uart/uart_rx_tb.vhdl index bd0a76c1..d934554a 100644 --- a/tb/io/uart/uart_rx_tb.vhdl +++ b/tb/io/uart/uart_rx_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================ -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/mem/lut/lut_Sine_tb.vhdl b/tb/mem/lut/lut_Sine_tb.vhdl index b3303a81..bec2dc68 100644 --- a/tb/mem/lut/lut_Sine_tb.vhdl +++ b/tb/mem/lut/lut_Sine_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/mem/ocram/ocram_esdp_tb.vhdl b/tb/mem/ocram/ocram_esdp_tb.vhdl index 853304d8..eb28b482 100644 --- a/tb/mem/ocram/ocram_esdp_tb.vhdl +++ b/tb/mem/ocram/ocram_esdp_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/mem/ocram/ocram_sdp_tb.vhdl b/tb/mem/ocram/ocram_sdp_tb.vhdl index 48c6ede1..b42f4aca 100644 --- a/tb/mem/ocram/ocram_sdp_tb.vhdl +++ b/tb/mem/ocram/ocram_sdp_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/mem/ocram/ocram_sp_tb.vhdl b/tb/mem/ocram/ocram_sp_tb.vhdl index ea4b8285..cf9ed979 100644 --- a/tb/mem/ocram/ocram_sp_tb.vhdl +++ b/tb/mem/ocram/ocram_sp_tb.vhdl @@ -13,7 +13,7 @@ -- License: -- ============================================================================= -- Copyright 2016-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/mem/ocram/ocram_tdp_tb.vhdl b/tb/mem/ocram/ocram_tdp_tb.vhdl index 5c99222e..51cae942 100644 --- a/tb/mem/ocram/ocram_tdp_tb.vhdl +++ b/tb/mem/ocram/ocram_tdp_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/misc/gearbox/gearbox_down_cc_tb.vhdl b/tb/misc/gearbox/gearbox_down_cc_tb.vhdl index 619817d1..ed15ec6a 100644 --- a/tb/misc/gearbox/gearbox_down_cc_tb.vhdl +++ b/tb/misc/gearbox/gearbox_down_cc_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/misc/gearbox/gearbox_down_dc_tb.vhdl b/tb/misc/gearbox/gearbox_down_dc_tb.vhdl index e51a17dc..8fe725be 100644 --- a/tb/misc/gearbox/gearbox_down_dc_tb.vhdl +++ b/tb/misc/gearbox/gearbox_down_dc_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/misc/gearbox/gearbox_up_cc_tb.vhdl b/tb/misc/gearbox/gearbox_up_cc_tb.vhdl index 520d77e5..19ec5380 100644 --- a/tb/misc/gearbox/gearbox_up_cc_tb.vhdl +++ b/tb/misc/gearbox/gearbox_up_cc_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/misc/gearbox/gearbox_up_dc_tb.vhdl b/tb/misc/gearbox/gearbox_up_dc_tb.vhdl index 6918b696..d378782d 100644 --- a/tb/misc/gearbox/gearbox_up_dc_tb.vhdl +++ b/tb/misc/gearbox/gearbox_up_dc_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/misc/misc_bit_lz_tb.vhdl b/tb/misc/misc_bit_lz_tb.vhdl index 1d5d79bf..50b3cf8a 100644 --- a/tb/misc/misc_bit_lz_tb.vhdl +++ b/tb/misc/misc_bit_lz_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- =========================================================================== -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/misc/stat/stat_Average_tb.vhdl b/tb/misc/stat/stat_Average_tb.vhdl index d5362b75..5d7be6b4 100644 --- a/tb/misc/stat/stat_Average_tb.vhdl +++ b/tb/misc/stat/stat_Average_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/misc/stat/stat_Histogram_tb.vhdl b/tb/misc/stat/stat_Histogram_tb.vhdl index b89e50b4..c95c0fed 100644 --- a/tb/misc/stat/stat_Histogram_tb.vhdl +++ b/tb/misc/stat/stat_Histogram_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/misc/stat/stat_Maximum_tb.vhdl b/tb/misc/stat/stat_Maximum_tb.vhdl index e88c95b0..d26ce000 100644 --- a/tb/misc/stat/stat_Maximum_tb.vhdl +++ b/tb/misc/stat/stat_Maximum_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/misc/stat/stat_Minimum_tb.vhdl b/tb/misc/stat/stat_Minimum_tb.vhdl index 89a756be..e71ff99d 100644 --- a/tb/misc/stat/stat_Minimum_tb.vhdl +++ b/tb/misc/stat/stat_Minimum_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/misc/sync/sync_Bits_tb.vhdl b/tb/misc/sync/sync_Bits_tb.vhdl index 996a9df6..0a454aac 100644 --- a/tb/misc/sync/sync_Bits_tb.vhdl +++ b/tb/misc/sync/sync_Bits_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/misc/sync/sync_Command_tb.vhdl b/tb/misc/sync/sync_Command_tb.vhdl index 70e6a018..8b2096c3 100644 --- a/tb/misc/sync/sync_Command_tb.vhdl +++ b/tb/misc/sync/sync_Command_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/misc/sync/sync_Reset_tb.vhdl b/tb/misc/sync/sync_Reset_tb.vhdl index e271e9c0..550cc514 100644 --- a/tb/misc/sync/sync_Reset_tb.vhdl +++ b/tb/misc/sync/sync_Reset_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/misc/sync/sync_Strobe_tb.vhdl b/tb/misc/sync/sync_Strobe_tb.vhdl index 57bbdcfc..e2d9ee19 100644 --- a/tb/misc/sync/sync_Strobe_tb.vhdl +++ b/tb/misc/sync/sync_Strobe_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/misc/sync/sync_Vector_tb.vhdl b/tb/misc/sync/sync_Vector_tb.vhdl index abf44b5f..370582d3 100644 --- a/tb/misc/sync/sync_Vector_tb.vhdl +++ b/tb/misc/sync/sync_Vector_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/sim/sim_ClockGenerator_tb.vhdl b/tb/sim/sim_ClockGenerator_tb.vhdl index 06ae6049..ee948787 100644 --- a/tb/sim/sim_ClockGenerator_tb.vhdl +++ b/tb/sim/sim_ClockGenerator_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/sim/sim_Waveform_tb.vhdl b/tb/sim/sim_Waveform_tb.vhdl index 83c06cf8..56a6cf12 100644 --- a/tb/sim/sim_Waveform_tb.vhdl +++ b/tb/sim/sim_Waveform_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/sort/sort_lru_cache_cocotb.py b/tb/sort/sort_lru_cache_cocotb.py index 6207e296..c14ee192 100644 --- a/tb/sort/sort_lru_cache_cocotb.py +++ b/tb/sort/sort_lru_cache_cocotb.py @@ -14,7 +14,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/sort/sort_lru_cache_tb.vhdl b/tb/sort/sort_lru_cache_tb.vhdl index b94fe577..ecb8e492 100644 --- a/tb/sort/sort_lru_cache_tb.vhdl +++ b/tb/sort/sort_lru_cache_tb.vhdl @@ -15,7 +15,7 @@ -- License: -- ============================================================================ -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/sort/sort_lru_list_cocotb.py b/tb/sort/sort_lru_list_cocotb.py index dace1253..83421439 100644 --- a/tb/sort/sort_lru_list_cocotb.py +++ b/tb/sort/sort_lru_list_cocotb.py @@ -14,7 +14,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl b/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl index 3f305d96..dde6af29 100644 --- a/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl +++ b/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.vhdl b/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.vhdl index 35ece684..f2c7f151 100644 --- a/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.vhdl +++ b/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl b/tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl index a8df4fd1..f254ea5b 100644 --- a/tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl +++ b/tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/sort/sortnet/sortnet_Stream_Adapter2_tb.vhdl b/tb/sort/sortnet/sortnet_Stream_Adapter2_tb.vhdl index 25d2cf4d..e228e4cf 100644 --- a/tb/sort/sortnet/sortnet_Stream_Adapter2_tb.vhdl +++ b/tb/sort/sortnet/sortnet_Stream_Adapter2_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/sort/sortnet/sortnet_Stream_Adapter_tb.vhdl b/tb/sort/sortnet/sortnet_Stream_Adapter_tb.vhdl index c8b9d8d3..d7118fe0 100644 --- a/tb/sort/sortnet/sortnet_Stream_Adapter_tb.vhdl +++ b/tb/sort/sortnet/sortnet_Stream_Adapter_tb.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tcl/common/utils.tcl b/tcl/common/utils.tcl index b069e701..d49f0d12 100644 --- a/tcl/common/utils.tcl +++ b/tcl/common/utils.tcl @@ -13,7 +13,7 @@ # License: # ============================================================================ # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tcl/vivado/utils.tcl b/tcl/vivado/utils.tcl index d2beac6e..8e311721 100644 --- a/tcl/vivado/utils.tcl +++ b/tcl/vivado/utils.tcl @@ -14,7 +14,7 @@ # License: # ============================================================================ # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tools/Travis-CI/my_project.vhdl b/tools/Travis-CI/my_project.vhdl index 645986d3..675016e8 100644 --- a/tools/Travis-CI/my_project.vhdl +++ b/tools/Travis-CI/my_project.vhdl @@ -22,7 +22,7 @@ -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tools/git/build_md.py b/tools/git/build_md.py index 729b7600..00cb4223 100644 --- a/tools/git/build_md.py +++ b/tools/git/build_md.py @@ -9,7 +9,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tools/git/filters/normalize.pl b/tools/git/filters/normalize.pl index 150e15cd..17e918e4 100755 --- a/tools/git/filters/normalize.pl +++ b/tools/git/filters/normalize.pl @@ -9,7 +9,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tools/git/git-alias.setup.ps1 b/tools/git/git-alias.setup.ps1 index 153b7d06..66afb003 100644 --- a/tools/git/git-alias.setup.ps1 +++ b/tools/git/git-alias.setup.ps1 @@ -14,7 +14,7 @@ # License: # ============================================================================= # Copyright 2007-2015 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tools/git/git-alias.setup.sh b/tools/git/git-alias.setup.sh index ccd066d8..808efe23 100755 --- a/tools/git/git-alias.setup.sh +++ b/tools/git/git-alias.setup.sh @@ -15,7 +15,7 @@ # License: # ============================================================================= # Copyright 2007-2015 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tools/git/hooks/pre-commit.d/whitespace.sh b/tools/git/hooks/pre-commit.d/whitespace.sh index 6d120e6d..4f72c1f2 100755 --- a/tools/git/hooks/pre-commit.d/whitespace.sh +++ b/tools/git/hooks/pre-commit.d/whitespace.sh @@ -9,7 +9,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tools/git/hooks/run-hook.sh b/tools/git/hooks/run-hook.sh index 7370ee1b..3428cbe4 100755 --- a/tools/git/hooks/run-hook.sh +++ b/tools/git/hooks/run-hook.sh @@ -9,7 +9,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tools/precompile/compile-altera.ps1 b/tools/precompile/compile-altera.ps1 index f7f287cd..139c4944 100644 --- a/tools/precompile/compile-altera.ps1 +++ b/tools/precompile/compile-altera.ps1 @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tools/precompile/compile-altera.sh b/tools/precompile/compile-altera.sh index 8701c1c2..b3a39ff1 100755 --- a/tools/precompile/compile-altera.sh +++ b/tools/precompile/compile-altera.sh @@ -17,7 +17,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tools/precompile/compile-lattice.ps1 b/tools/precompile/compile-lattice.ps1 index f5d03bfb..33949a07 100644 --- a/tools/precompile/compile-lattice.ps1 +++ b/tools/precompile/compile-lattice.ps1 @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tools/precompile/compile-lattice.sh b/tools/precompile/compile-lattice.sh index 1838eea1..1740f728 100755 --- a/tools/precompile/compile-lattice.sh +++ b/tools/precompile/compile-lattice.sh @@ -18,7 +18,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tools/precompile/compile-osvvm.ps1 b/tools/precompile/compile-osvvm.ps1 index 2d925736..cd58974c 100644 --- a/tools/precompile/compile-osvvm.ps1 +++ b/tools/precompile/compile-osvvm.ps1 @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tools/precompile/compile-osvvm.sh b/tools/precompile/compile-osvvm.sh index 0a0e1237..a5e53aaf 100755 --- a/tools/precompile/compile-osvvm.sh +++ b/tools/precompile/compile-osvvm.sh @@ -18,7 +18,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tools/precompile/compile-xilinx-ise.ps1 b/tools/precompile/compile-xilinx-ise.ps1 index 9609e176..cf0044e7 100644 --- a/tools/precompile/compile-xilinx-ise.ps1 +++ b/tools/precompile/compile-xilinx-ise.ps1 @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tools/precompile/compile-xilinx-ise.sh b/tools/precompile/compile-xilinx-ise.sh index 859f39d0..38d3c70e 100755 --- a/tools/precompile/compile-xilinx-ise.sh +++ b/tools/precompile/compile-xilinx-ise.sh @@ -18,7 +18,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tools/precompile/compile-xilinx-vivado.ps1 b/tools/precompile/compile-xilinx-vivado.ps1 index 912dc168..1f7d5367 100644 --- a/tools/precompile/compile-xilinx-vivado.ps1 +++ b/tools/precompile/compile-xilinx-vivado.ps1 @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tools/precompile/compile-xilinx-vivado.sh b/tools/precompile/compile-xilinx-vivado.sh index d3b4a23e..ddcf685c 100755 --- a/tools/precompile/compile-xilinx-vivado.sh +++ b/tools/precompile/compile-xilinx-vivado.sh @@ -18,7 +18,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tools/precompile/shared.sh b/tools/precompile/shared.sh index f73bbbd4..fdfe07f4 100644 --- a/tools/precompile/shared.sh +++ b/tools/precompile/shared.sh @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. From dac72898e1876f4e78705c249052c87b9537eedd Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 10 Nov 2016 23:56:25 +0100 Subject: [PATCH 21/97] Documented pre-compile scripts. --- .../CmdRefs-PreCompile/Compile-Altera-ps1.rst | 30 ++++++++++++ .../CmdRefs-PreCompile/Compile-Altera-sh.rst | 30 ++++++++++++ .../Compile-Lattice-ps1.rst | 30 ++++++++++++ .../CmdRefs-PreCompile/Compile-Lattice-sh.rst | 30 ++++++++++++ .../CmdRefs-PreCompile/Compile-OSVVM-ps1.rst | 30 ++++++++++++ .../CmdRefs-PreCompile/Compile-OSVVM-sh.rst | 30 ++++++++++++ .../Compile-Xilinx-ISE-ps1.rst | 34 +++++++++++++ .../Compile-Xilinx-ISE-sh.rst | 30 ++++++++++++ .../Compile-Xilinx-Vivado-ps1.rst | 34 +++++++++++++ .../Compile-Xilinx-Vivado-sh.rst | 30 ++++++++++++ docs/References/CommandReference.rst | 49 +++++++++++++++++++ tools/precompile/compile-altera.ps1 | 12 ++--- tools/precompile/compile-altera.sh | 2 +- tools/precompile/compile-lattice.ps1 | 14 +++--- tools/precompile/compile-lattice.sh | 2 +- tools/precompile/compile-osvvm.ps1 | 8 +-- tools/precompile/compile-osvvm.sh | 3 +- tools/precompile/compile-xilinx-ise.ps1 | 16 +++--- tools/precompile/compile-xilinx-ise.sh | 2 +- tools/precompile/compile-xilinx-vivado.ps1 | 16 +++--- tools/precompile/compile-xilinx-vivado.sh | 2 +- tools/precompile/precompile.psm1 | 2 +- 22 files changed, 396 insertions(+), 40 deletions(-) create mode 100644 docs/References/CmdRefs-PreCompile/Compile-Altera-ps1.rst create mode 100644 docs/References/CmdRefs-PreCompile/Compile-Altera-sh.rst create mode 100644 docs/References/CmdRefs-PreCompile/Compile-Lattice-ps1.rst create mode 100644 docs/References/CmdRefs-PreCompile/Compile-Lattice-sh.rst create mode 100644 docs/References/CmdRefs-PreCompile/Compile-OSVVM-ps1.rst create mode 100644 docs/References/CmdRefs-PreCompile/Compile-OSVVM-sh.rst create mode 100644 docs/References/CmdRefs-PreCompile/Compile-Xilinx-ISE-ps1.rst create mode 100644 docs/References/CmdRefs-PreCompile/Compile-Xilinx-ISE-sh.rst create mode 100644 docs/References/CmdRefs-PreCompile/Compile-Xilinx-Vivado-ps1.rst create mode 100644 docs/References/CmdRefs-PreCompile/Compile-Xilinx-Vivado-sh.rst diff --git a/docs/References/CmdRefs-PreCompile/Compile-Altera-ps1.rst b/docs/References/CmdRefs-PreCompile/Compile-Altera-ps1.rst new file mode 100644 index 00000000..d9d0f88b --- /dev/null +++ b/docs/References/CmdRefs-PreCompile/Compile-Altera-ps1.rst @@ -0,0 +1,30 @@ +compile-altera.ps1 +------------------ + +.. option:: -Help + + Show the embedded help page(s). + +.. option:: -Clean + + Clean up directory before analyzing. + +.. option:: -All + + Pre-compile all libraries and packages for all simulators. + +.. option:: -GHDL + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: -Questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + +.. option:: -VHDL93 + + Set VHDL Standard to '93. + +.. option:: -VHDL2008 + + Set VHDL Standard to '08. diff --git a/docs/References/CmdRefs-PreCompile/Compile-Altera-sh.rst b/docs/References/CmdRefs-PreCompile/Compile-Altera-sh.rst new file mode 100644 index 00000000..9b0ea31c --- /dev/null +++ b/docs/References/CmdRefs-PreCompile/Compile-Altera-sh.rst @@ -0,0 +1,30 @@ +compile-altera.sh +----------------- + +.. option:: --help + + Show the embedded help page(s). + +.. option:: --clean + + Clean up directory before analyzing. + +.. option:: --all + + Pre-compile all libraries and packages for all simulators. + +.. option:: --ghdl + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: --questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + +.. option:: --vhdl93 + + Set VHDL Standard to '93. + +.. option:: --vhdl2008 + + Set VHDL Standard to '08. diff --git a/docs/References/CmdRefs-PreCompile/Compile-Lattice-ps1.rst b/docs/References/CmdRefs-PreCompile/Compile-Lattice-ps1.rst new file mode 100644 index 00000000..87955ead --- /dev/null +++ b/docs/References/CmdRefs-PreCompile/Compile-Lattice-ps1.rst @@ -0,0 +1,30 @@ +compile-lattice.ps1 +------------------- + +.. option:: -Help + + Show the embedded help page(s). + +.. option:: -Clean + + Clean up directory before analyzing. + +.. option:: -All + + Pre-compile all libraries and packages for all simulators. + +.. option:: -GHDL + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: -Questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + +.. option:: -VHDL93 + + Set VHDL Standard to '93. + +.. option:: -VHDL2008 + + Set VHDL Standard to '08. diff --git a/docs/References/CmdRefs-PreCompile/Compile-Lattice-sh.rst b/docs/References/CmdRefs-PreCompile/Compile-Lattice-sh.rst new file mode 100644 index 00000000..d19189ec --- /dev/null +++ b/docs/References/CmdRefs-PreCompile/Compile-Lattice-sh.rst @@ -0,0 +1,30 @@ +compile-lattice.sh +------------------ + +.. option:: --help + + Show the embedded help page(s). + +.. option:: --clean + + Clean up directory before analyzing. + +.. option:: --all + + Pre-compile all libraries and packages for all simulators. + +.. option:: --ghdl + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: --questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + +.. option:: --vhdl93 + + Set VHDL Standard to '93. + +.. option:: --vhdl2008 + + Set VHDL Standard to '08. diff --git a/docs/References/CmdRefs-PreCompile/Compile-OSVVM-ps1.rst b/docs/References/CmdRefs-PreCompile/Compile-OSVVM-ps1.rst new file mode 100644 index 00000000..9a241e42 --- /dev/null +++ b/docs/References/CmdRefs-PreCompile/Compile-OSVVM-ps1.rst @@ -0,0 +1,30 @@ +compile-osvvm.ps1 +------------------ + +.. option:: -Help + + Show the embedded help page(s). + +.. option:: -Clean + + Clean up directory before analyzing. + +.. option:: -All + + Pre-compile all libraries and packages for all simulators. + +.. option:: -GHDL + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: -Questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + +.. option:: -VHDL93 + + Set VHDL Standard to '93. + +.. option:: -VHDL2008 + + Set VHDL Standard to '08. diff --git a/docs/References/CmdRefs-PreCompile/Compile-OSVVM-sh.rst b/docs/References/CmdRefs-PreCompile/Compile-OSVVM-sh.rst new file mode 100644 index 00000000..1081b79e --- /dev/null +++ b/docs/References/CmdRefs-PreCompile/Compile-OSVVM-sh.rst @@ -0,0 +1,30 @@ +compile-osvvm.sh +---------------- + +.. option:: --help + + Show the embedded help page(s). + +.. option:: --clean + + Clean up directory before analyzing. + +.. option:: --all + + Pre-compile all libraries and packages for all simulators. + +.. option:: --ghdl + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: --questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + +.. option:: --vhdl93 + + Set VHDL Standard to '93. + +.. option:: --vhdl2008 + + Set VHDL Standard to '08. diff --git a/docs/References/CmdRefs-PreCompile/Compile-Xilinx-ISE-ps1.rst b/docs/References/CmdRefs-PreCompile/Compile-Xilinx-ISE-ps1.rst new file mode 100644 index 00000000..e756cf74 --- /dev/null +++ b/docs/References/CmdRefs-PreCompile/Compile-Xilinx-ISE-ps1.rst @@ -0,0 +1,34 @@ +compile-xilinx-ise.ps1 +---------------------- + +.. option:: -Help + + Show the embedded help page(s). + +.. option:: -Clean + + Clean up directory before analyzing. + +.. option:: -All + + Pre-compile all libraries and packages for all simulators. + +.. option:: -GHDL + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: -Questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + +.. option:: -ReLink + + Change the 'xilinx' symlink to 'xilinx-ise'. + +.. option:: -VHDL93 + + Set VHDL Standard to '93. + +.. option:: -VHDL2008 + + Set VHDL Standard to '08. diff --git a/docs/References/CmdRefs-PreCompile/Compile-Xilinx-ISE-sh.rst b/docs/References/CmdRefs-PreCompile/Compile-Xilinx-ISE-sh.rst new file mode 100644 index 00000000..c8269385 --- /dev/null +++ b/docs/References/CmdRefs-PreCompile/Compile-Xilinx-ISE-sh.rst @@ -0,0 +1,30 @@ +compile-xilinx-ise.sh +--------------------- + +.. option:: --help + + Show the embedded help page(s). + +.. option:: --clean + + Clean up directory before analyzing. + +.. option:: --all + + Pre-compile all libraries and packages for all simulators. + +.. option:: --ghdl + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: --questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + +.. option:: --vhdl93 + + Set VHDL Standard to '93. + +.. option:: --vhdl2008 + + Set VHDL Standard to '08. diff --git a/docs/References/CmdRefs-PreCompile/Compile-Xilinx-Vivado-ps1.rst b/docs/References/CmdRefs-PreCompile/Compile-Xilinx-Vivado-ps1.rst new file mode 100644 index 00000000..e48613b3 --- /dev/null +++ b/docs/References/CmdRefs-PreCompile/Compile-Xilinx-Vivado-ps1.rst @@ -0,0 +1,34 @@ +compile-xilinx-vivado.ps1 +------------------------- + +.. option:: -Help + + Show the embedded help page(s). + +.. option:: -Clean + + Clean up directory before analyzing. + +.. option:: -All + + Pre-compile all libraries and packages for all simulators. + +.. option:: -GHDL + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: -Questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + +.. option:: -ReLink + + Change the 'xilinx' symlink to 'xilinx-vivado'. + +.. option:: -VHDL93 + + Set VHDL Standard to '93. + +.. option:: -VHDL2008 + + Set VHDL Standard to '08. diff --git a/docs/References/CmdRefs-PreCompile/Compile-Xilinx-Vivado-sh.rst b/docs/References/CmdRefs-PreCompile/Compile-Xilinx-Vivado-sh.rst new file mode 100644 index 00000000..5ea1d216 --- /dev/null +++ b/docs/References/CmdRefs-PreCompile/Compile-Xilinx-Vivado-sh.rst @@ -0,0 +1,30 @@ +compile-xilinx-vivado.sh +------------------------ + +.. option:: --help + + Show the embedded help page(s). + +.. option:: --clean + + Clean up directory before analyzing. + +.. option:: --all + + Pre-compile all libraries and packages for all simulators. + +.. option:: --ghdl + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: --questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + +.. option:: --vhdl93 + + Set VHDL Standard to '93. + +.. option:: --vhdl2008 + + Set VHDL Standard to '08. diff --git a/docs/References/CommandReference.rst b/docs/References/CommandReference.rst index fd6fe437..fd3d0361 100644 --- a/docs/References/CommandReference.rst +++ b/docs/References/CommandReference.rst @@ -6,3 +6,52 @@ Command Reference .. autoprogram:: PoCSphinx:parser :prog: PoC.py + + +Pre-compile Scripts +******************* + +Pre-compile Altera Libraries +============================ + +.. toctree:: + + CmdRefs-PreCompile/Compile-Altera-ps1 + CmdRefs-PreCompile/Compile-Altera-sh + + +Pre-compile Lattice Libraries +============================= + +.. toctree:: + + CmdRefs-PreCompile/Compile-Lattice-ps1 + CmdRefs-PreCompile/Compile-Lattice-sh + + +Pre-compile OSVVM Libraries +=========================== + +.. toctree:: + + CmdRefs-PreCompile/Compile-OSVVM-ps1 + CmdRefs-PreCompile/Compile-OSVVM-sh + + +Pre-compile Xilinx ISE Libraries +================================ + + +.. toctree:: + + CmdRefs-PreCompile/Compile-Xilinx-ISE-ps1 + CmdRefs-PreCompile/Compile-Xilinx-ISE-sh + + +Pre-compile Xilinx Vivado Libraries +=================================== + +.. toctree:: + + CmdRefs-PreCompile/Compile-Xilinx-Vivado-ps1 + CmdRefs-PreCompile/Compile-Xilinx-Vivado-sh diff --git a/tools/precompile/compile-altera.ps1 b/tools/precompile/compile-altera.ps1 index 139c4944..e6c527da 100644 --- a/tools/precompile/compile-altera.ps1 +++ b/tools/precompile/compile-altera.ps1 @@ -42,24 +42,24 @@ # [CmdletBinding()] param( - # Pre-compile all libraries and packages for all simulators + # Pre-compile all libraries and packages for all simulators. [switch]$All = $false, - # Pre-compile the Altera Quartus libraries for GHDL + # Pre-compile the Altera Quartus libraries for GHDL. [switch]$GHDL = $false, - # Pre-compile the Altera Quartus libraries for QuestaSim + # Pre-compile the Altera Quartus libraries for QuestaSim. [switch]$Questa = $false, - # Set VHDL Standard to '93 + # Set VHDL Standard to '93. [switch]$VHDL93 = $false, - # # Set VHDL Standard to '08 + # Set VHDL Standard to '08. [switch]$VHDL2008 = $false, # Clean up directory before analyzing. [switch]$Clean = $false, - # Show the embedded help page(s) + # Show the embedded help page(s). [switch]$Help = $false ) diff --git a/tools/precompile/compile-altera.sh b/tools/precompile/compile-altera.sh index b3a39ff1..ea7370c4 100755 --- a/tools/precompile/compile-altera.sh +++ b/tools/precompile/compile-altera.sh @@ -101,7 +101,7 @@ if [ "$HELP" == "TRUE" ]; then echo " on Linux." echo "" echo "Usage:" - echo " compile-altera.sh [-c] [--help|--all|--ghdl|--vsim] []" + echo " compile-altera.sh [-c] [--help|--all|--ghdl|--questa] []" echo "" echo "Common commands:" echo " -h --help Print this help page" diff --git a/tools/precompile/compile-lattice.ps1 b/tools/precompile/compile-lattice.ps1 index 33949a07..327da60b 100644 --- a/tools/precompile/compile-lattice.ps1 +++ b/tools/precompile/compile-lattice.ps1 @@ -42,24 +42,24 @@ # [CmdletBinding()] param( - # Pre-compile all libraries and packages for all simulators + # Pre-compile all libraries and packages for all simulators. [switch]$All = $false, - # Pre-compile the Lattice Diamond libraries for GHDL + # Pre-compile the Lattice Diamond libraries for GHDL. [switch]$GHDL = $false, - # Pre-compile the Lattice Diamond libraries for QuestaSim + # Pre-compile the Lattice Diamond libraries for QuestaSim. [switch]$Questa = $false, - # Set VHDL Standard to '93 + # Set VHDL Standard to '93. [switch]$VHDL93 = $false, - # Set VHDL Standard to '08 + # Set VHDL Standard to '08. [switch]$VHDL2008 = $false, # Clean up directory before analyzing. [switch]$Clean = $false, - # Show the embedded help page(s) + # Show the embedded help page(s). [switch]$Help = $false ) @@ -104,7 +104,7 @@ if ($GHDL) $GHDLDirName = Get-GHDLDirectoryName $PoCPS1 # Assemble output directory - $DestDir="$PoCRootDir\$PrecompiledDir\$GHDLDirName" + $DestDir = "$PoCRootDir\$PrecompiledDir\$GHDLDirName" # Create and change to destination directory Initialize-DestinationDirectory $DestDir diff --git a/tools/precompile/compile-lattice.sh b/tools/precompile/compile-lattice.sh index 1740f728..c0c9669e 100755 --- a/tools/precompile/compile-lattice.sh +++ b/tools/precompile/compile-lattice.sh @@ -102,7 +102,7 @@ if [ "$HELP" == "TRUE" ]; then echo " on Linux." echo "" echo "Usage:" - echo " compile-lattice.sh [-c] [--help|--all|--ghdl|--vsim] []" + echo " compile-lattice.sh [-c] [--help|--all|--ghdl|--questa] []" echo "" echo "Common commands:" echo " -h --help Print this help page" diff --git a/tools/precompile/compile-osvvm.ps1 b/tools/precompile/compile-osvvm.ps1 index cd58974c..fdde6826 100644 --- a/tools/precompile/compile-osvvm.ps1 +++ b/tools/precompile/compile-osvvm.ps1 @@ -42,19 +42,19 @@ # [CmdletBinding()] param( - # Pre-compile all libraries and packages for all simulators + # Pre-compile all libraries and packages for all simulators. [switch]$All = $false, - # Pre-compile the OSVVM libraries for GHDL + # Pre-compile the OSVVM libraries for GHDL. [switch]$GHDL = $false, - # Pre-compile the OSVVM libraries for QuestaSim + # Pre-compile the OSVVM libraries for QuestaSim. [switch]$Questa = $false, # Clean up directory before analyzing. [switch]$Clean = $false, - # Show the embedded help page(s) + # Show the embedded help page(s). [switch]$Help = $false ) diff --git a/tools/precompile/compile-osvvm.sh b/tools/precompile/compile-osvvm.sh index a5e53aaf..f5129651 100755 --- a/tools/precompile/compile-osvvm.sh +++ b/tools/precompile/compile-osvvm.sh @@ -97,7 +97,7 @@ if [ "$HELP" == "TRUE" ]; then echo " on Linux." echo "" echo "Usage:" - echo " compile-osvvm.sh [-c] [--help|--all|--ghdl|--vsim]" + echo " compile-osvvm.sh [-c] [--help|--all|--ghdl|--questa]" echo "" echo "Common commands:" echo " -h --help Print this help page" @@ -239,4 +239,3 @@ if [ "$COMPILE_FOR_VSIM" == "TRUE" ]; then cd $WorkingDir fi - diff --git a/tools/precompile/compile-xilinx-ise.ps1 b/tools/precompile/compile-xilinx-ise.ps1 index cf0044e7..efc7ba8e 100644 --- a/tools/precompile/compile-xilinx-ise.ps1 +++ b/tools/precompile/compile-xilinx-ise.ps1 @@ -43,27 +43,27 @@ # [CmdletBinding()] param( - # Pre-compile all libraries and packages for all simulators + # Pre-compile all libraries and packages for all simulators. [switch]$All = $false, - # Pre-compile the Xilinx ISE libraries for GHDL + # Pre-compile the Xilinx ISE libraries for GHDL. [switch]$GHDL = $false, - # Pre-compile the Xilinx ISE libraries for QuestaSim + # Pre-compile the Xilinx ISE libraries for QuestaSim. [switch]$Questa = $false, - # Change the 'xilinx' symlink to 'xilinx-ise' + # Change the 'xilinx' symlink to 'xilinx-ise'. [switch]$ReLink = $false, - # Set VHDL Standard to '93 + # Set VHDL Standard to '93. [switch]$VHDL93 = $false, - # Set VHDL Standard to '08 + # Set VHDL Standard to '08. [switch]$VHDL2008 = $false, # Clean up directory before analyzing. [switch]$Clean = $false, - # Show the embedded help page(s) + # Show the embedded help page(s). [switch]$Help = $false ) @@ -109,7 +109,7 @@ if ($GHDL) $GHDLDirName = Get-GHDLDirectoryName $PoCPS1 # Assemble output directory - $DestDir="$PoCRootDir\$PrecompiledDir\$GHDLDirName" + $DestDir = "$PoCRootDir\$PrecompiledDir\$GHDLDirName" # Create and change to destination directory Initialize-DestinationDirectory $DestDir diff --git a/tools/precompile/compile-xilinx-ise.sh b/tools/precompile/compile-xilinx-ise.sh index 38d3c70e..ca3e8d0f 100755 --- a/tools/precompile/compile-xilinx-ise.sh +++ b/tools/precompile/compile-xilinx-ise.sh @@ -102,7 +102,7 @@ if [ "$HELP" == "TRUE" ]; then echo " on Linux." echo "" echo "Usage:" - echo " compile-xilinx-ise.sh [-c] [--help|--all|--ghdl|--vsim] []" + echo " compile-xilinx-ise.sh [-c] [--help|--all|--ghdl|--questa] []" echo "" echo "Common commands:" echo " -h --help Print this help page" diff --git a/tools/precompile/compile-xilinx-vivado.ps1 b/tools/precompile/compile-xilinx-vivado.ps1 index 1f7d5367..1f163188 100644 --- a/tools/precompile/compile-xilinx-vivado.ps1 +++ b/tools/precompile/compile-xilinx-vivado.ps1 @@ -43,27 +43,27 @@ # [CmdletBinding()] param( - # Pre-compile all libraries and packages for all simulators + # Pre-compile all libraries and packages for all simulators. [switch]$All = $false, - # Pre-compile the Xilinx Vivado libraries for GHDL + # Pre-compile the Xilinx Vivado libraries for GHDL. [switch]$GHDL = $false, - # Pre-compile the Xilinx Vivado libraries for QuestaSim + # Pre-compile the Xilinx Vivado libraries for QuestaSim. [switch]$Questa = $false, - # Change the 'xilinx' symlink to 'xilinx-vivado' + # Change the 'xilinx' symlink to 'xilinx-vivado'. [switch]$ReLink = $false, - # Set VHDL Standard to '93 + # Set VHDL Standard to '93. [switch]$VHDL93 = $false, - # Set VHDL Standard to '08 + # Set VHDL Standard to '08. [switch]$VHDL2008 = $false, # Clean up directory before analyzing. [switch]$Clean = $false, - # Show the embedded help page(s) + # Show the embedded help page(s). [switch]$Help = $false ) @@ -109,7 +109,7 @@ if ($GHDL) $GHDLDirName = Get-GHDLDirectoryName $PoCPS1 # Assemble output directory - $DestDir="$PoCRootDir\$PrecompiledDir\$GHDLDirName" + $DestDir = "$PoCRootDir\$PrecompiledDir\$GHDLDirName" # Create and change to destination directory Initialize-DestinationDirectory $DestDir diff --git a/tools/precompile/compile-xilinx-vivado.sh b/tools/precompile/compile-xilinx-vivado.sh index ddcf685c..65b2730f 100755 --- a/tools/precompile/compile-xilinx-vivado.sh +++ b/tools/precompile/compile-xilinx-vivado.sh @@ -102,7 +102,7 @@ if [ "$HELP" == "TRUE" ]; then echo " on Linux." echo "" echo "Usage:" - echo " compile-xilinx-vivado.sh [-c] [--help|--all|--ghdl|--vsim] []" + echo " compile-xilinx-vivado.sh [-c] [--help|--all|--ghdl|--questa] []" echo "" echo "Common commands:" echo " -h --help Print this help page" diff --git a/tools/precompile/precompile.psm1 b/tools/precompile/precompile.psm1 index 6fe8beb9..14a6c518 100644 --- a/tools/precompile/precompile.psm1 +++ b/tools/precompile/precompile.psm1 @@ -866,7 +866,7 @@ function Write-ColoredGHDLLine function Write-ColoredActiveHDLLine { <# .SYNOPSIS - This CmdLet colors GHDL output lines. + This CmdLet colors ActiveHDL output lines. .DESCRIPTION This CmdLet colors GHDL output lines. Warnings are prefixed with 'WARNING: ' From 88f3ff0da515b187b7488ccdf73ef195e93ba04e Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 10 Nov 2016 23:57:51 +0100 Subject: [PATCH 22/97] Implemented output filtering and coloring in PowerShell for QuestaSim executables. --- tools/precompile/compile-osvvm.ps1 | 6 +- tools/precompile/precompile.psm1 | 283 +++++++++++++++++++++++++++-- 2 files changed, 270 insertions(+), 19 deletions(-) diff --git a/tools/precompile/compile-osvvm.ps1 b/tools/precompile/compile-osvvm.ps1 index fdde6826..128b1cc2 100644 --- a/tools/precompile/compile-osvvm.ps1 +++ b/tools/precompile/compile-osvvm.ps1 @@ -168,9 +168,9 @@ if ($Questa) Write-Host "Compiling library '$Library' with vcom..." -ForegroundColor Yellow $ErrorCount += 0 foreach ($File in $SourceFiles) - { Write-Host "Compiling '$File'..." -ForegroundColor Cyan - $InvokeExpr = "$VSimBinDir\vcom.exe -2008 -work $Library " + $File + " 2>&1" - Invoke-Expression $InvokeExpr + { Write-Host "Compiling '$File'..." -ForegroundColor DarkCyan + $InvokeExpr = "$VSimBinDir\vcom.exe -suppress 1246 -2008 -work $Library " + $File + " 2>&1" + $ErrorRecordFound = Invoke-Expression $InvokeExpr | Restore-NativeCommandStream | Write-ColoredQuestaLine $SuppressWarnings " " -Verbose:$EnableVerbose -Debug:$EnableDebug if ($LastExitCode -ne 0) { $ErrorCount += 1 if ($HaltOnError) diff --git a/tools/precompile/precompile.psm1 b/tools/precompile/precompile.psm1 index 14a6c518..640a51e7 100644 --- a/tools/precompile/precompile.psm1 +++ b/tools/precompile/precompile.psm1 @@ -823,9 +823,10 @@ function Write-ColoredGHDLLine .PARAMETER InputObject A object stream is required as an input. - .PARAMETER SuppressWarnings Skip warning messages. (Show errors only.) + .PARAMETER Indent + Indentation string. #> [CmdletBinding()] param( @@ -833,27 +834,34 @@ function Write-ColoredGHDLLine $InputObject, [Parameter(Position=1)] - [switch]$SuppressWarnings = $false + [switch]$SuppressWarnings = $false, + [Parameter(Position=2)] + [string]$Indent = "" ) begin { $ErrorRecordFound = $false } process - { if (-not $InputObject) - { Write-Host "Empty pipeline!" } - elseif ($InputObject -is [string]) - { if ($InputObject.Contains("warning")) + { if ($InputObject -is [String]) + { if ($InputObject -match ":\d+:\d+:warning:\s") { if (-not $SuppressWarnings) - { Write-Host "WARNING: " -NoNewline -ForegroundColor Yellow + { Write-Host "${Indent}WARNING: " -NoNewline -ForegroundColor Yellow Write-Host $InputObject } } - else + elseif ($InputObject -match ":\d+:\d+:\s") { $ErrorRecordFound = $true - Write-Host "ERROR: " -NoNewline -ForegroundColor Red + Write-Host "${Indent}ERROR: " -NoNewline -ForegroundColor Red Write-Host $InputObject } + elseif ($InputObject -match ":error:\s") + { $ErrorRecordFound = $true + Write-Host "${Indent}ERROR: " -NoNewline -ForegroundColor Red + Write-Host $InputObject + } + else + { Write-Host "${Indent}$InputObject" } } else { Write-Host "Unsupported object in pipeline stream" } @@ -884,11 +892,21 @@ function Write-ColoredActiveHDLLine $InputObject, [Parameter(Position=1)] - [switch]$SuppressWarnings = $false + [switch]$SuppressWarnings = $false, + [Parameter(Position=2)] + [string]$Indent = "" ) begin - { $ErrorRecordFound = $false } + { # set default values + $EnableVerbose = $PSCmdlet.MyInvocation.BoundParameters["Verbose"] + $EnableDebug = $PSCmdlet.MyInvocation.BoundParameters["Debug"] + if ($EnableVerbose -eq $null) { $EnableVerbose = $false } + if ($EnableDebug -eq $null) { $EnableDebug = $false } + if ($EnableDebug -eq $true) { $EnableVerbose = $true } + + $ErrorRecordFound = $false + } process { if (-not $InputObject) @@ -896,19 +914,249 @@ function Write-ColoredActiveHDLLine elseif ($InputObject -is [string]) { if ($InputObject.Contains("WARNING")) { if (-not $SuppressWarnings) - { Write-Host "WARNING: " -NoNewline -ForegroundColor Yellow + { Write-Host "${Indent}WARNING: " -NoNewline -ForegroundColor Yellow Write-Host $InputObject } } elseif ($InputObject.Contains("ERROR")) - { if (-not $SuppressWarnings) - { Write-Host "ERROR: " -NoNewline -ForegroundColor Red - Write-Host $InputObject + { $ErrorRecordFound = $true + Write-Host "${Indent}ERROR: " -NoNewline -ForegroundColor Red + Write-Host $InputObject + } + else + { Write-Host "${Indent}$InputObject" } + } + else + { Write-Host "Unsupported object in pipeline stream" } + } + + end + { $ErrorRecordFound } +} + +function Write-ColoredQuestaVLibLine +{ <# + .SYNOPSIS + This CmdLet colors QuestaSim/ModelSim output lines. + + .DESCRIPTION + This CmdLet colors GHDL output lines. Warnings are prefixed with 'WARNING: ' + in yellow and errors are prefixed with 'ERROR: ' in red. + + .PARAMETER InputObject + A object stream is required as an input. + + .PARAMETER SuppressWarnings + Skip warning messages. (Show errors only.) + #> + [CmdletBinding()] + param( + [Parameter(ValueFromPipeline=$true)] + $InputObject, + + [Parameter(Position=1)] + [switch]$SuppressWarnings = $false, + [Parameter(Position=2)] + [string]$Indent = "" + ) + + begin + { # set default values + $EnableVerbose = $PSCmdlet.MyInvocation.BoundParameters["Verbose"] + $EnableDebug = $PSCmdlet.MyInvocation.BoundParameters["Debug"] + if ($EnableVerbose -eq $null) { $EnableVerbose = $false } + if ($EnableDebug -eq $null) { $EnableDebug = $false } + if ($EnableDebug -eq $true) { $EnableVerbose = $true } + + $ErrorRecordFound = $false + } + + process + { if (-not $InputObject) + { Write-Host "Empty pipeline!" } + elseif ($InputObject -is [string]) + { if ($InputObject.StartsWith("vlib ")) + { if ($EnableVerbose) { Write-Host "${Indent}$InputObject" -ForegroundColor Gray } } + elseif ($InputObject.StartsWith("** Warning:") -and -not $SuppressWarnings) + { Write-Host "${Indent}WARNING: " -NoNewline -ForegroundColor Yellow + Write-Host $InputObject.Substring(12) + } + elseif ($InputObject.StartsWith("** Fatal:") -or $InputObject.StartsWith("# ** Fatal:")) + { Write-Host "${Indent}ERROR: " -NoNewline -ForegroundColor Red + Write-Host $InputObject.Substring(10) + } + elseif ($InputObject.StartsWith("** Error:") -or $InputObject.StartsWith("# ** Error:")) + { Write-Host "${Indent}FATAL: " -NoNewline -ForegroundColor Red + Write-Host $InputObject.Substring(10) + } + elseif ($InputObject.StartsWith("QuestaSim-64 vlib")) + { if ($EnableDebug) { Write-Host "${Indent}$InputObject" -ForegroundColor DarkGray } } + else + { $ErrorRecordFound = $true + Write-Host "${Indent}$InputObject" + } + } + else + { Write-Host "Unsupported object in pipeline stream" } + } + + end + { $ErrorRecordFound } +} +function Write-ColoredQuestaVMapLine +{ <# + .SYNOPSIS + This CmdLet colors QuestaSim/ModelSim output lines. + + .DESCRIPTION + This CmdLet colors GHDL output lines. Warnings are prefixed with 'WARNING: ' + in yellow and errors are prefixed with 'ERROR: ' in red. + + .PARAMETER InputObject + A object stream is required as an input. + + .PARAMETER SuppressWarnings + Skip warning messages. (Show errors only.) + #> + [CmdletBinding()] + param( + [Parameter(ValueFromPipeline=$true)] + $InputObject, + + [Parameter(Position=1)] + [switch]$SuppressWarnings = $false, + [Parameter(Position=2)] + [string]$Indent = "" + ) + + begin + { # set default values + $EnableVerbose = $PSCmdlet.MyInvocation.BoundParameters["Verbose"] + $EnableDebug = $PSCmdlet.MyInvocation.BoundParameters["Debug"] + if ($EnableVerbose -eq $null) { $EnableVerbose = $false } + if ($EnableDebug -eq $null) { $EnableDebug = $false } + if ($EnableDebug -eq $true) { $EnableVerbose = $true } + + $ErrorRecordFound = $false + } + + process + { if (-not $InputObject) + { Write-Host "Empty pipeline!" } + elseif ($InputObject -is [string]) + { if ($InputObject.StartsWith("vmap ")) + { if ($EnableVerbose) { Write-Host "${Indent}$InputObject" -ForegroundColor Gray } } + elseif ($InputObject.StartsWith("** Warning:") -and -not $SuppressWarnings) + { Write-Host "${Indent}WARNING: " -NoNewline -ForegroundColor Yellow + Write-Host $InputObject.Substring(12) + } + elseif ($InputObject.StartsWith("** Fatal:") -or $InputObject.StartsWith("# ** Fatal:")) + { Write-Host "${Indent}ERROR: " -NoNewline -ForegroundColor Red + Write-Host $InputObject.Substring(10) + } + elseif ($InputObject.StartsWith("** Error:") -or $InputObject.StartsWith("# ** Error:")) + { Write-Host "${Indent}FATAL: " -NoNewline -ForegroundColor Red + Write-Host $InputObject.Substring(10) + } + elseif ($InputObject.StartsWith("QuestaSim-64 vmap")) + { if ($EnableDebug) { Write-Host "${Indent}$InputObject" -ForegroundColor DarkGray } } + else + { $ErrorRecordFound = $true + Write-Host "${Indent}$InputObject" + } + } + else + { Write-Host "Unsupported object in pipeline stream" } + } + + end + { $ErrorRecordFound } +} +function Write-ColoredQuestaVComLine +{ <# + .SYNOPSIS + This CmdLet colors QuestaSim/ModelSim output lines. + + .DESCRIPTION + This CmdLet colors GHDL output lines. Warnings are prefixed with 'WARNING: ' + in yellow and errors are prefixed with 'ERROR: ' in red. + + .PARAMETER InputObject + A object stream is required as an input. + + .PARAMETER SuppressWarnings + Skip warning messages. (Show errors only.) + #> + [CmdletBinding()] + param( + [Parameter(ValueFromPipeline=$true)] + $InputObject, + + [Parameter(Position=1)] + [switch]$SuppressWarnings = $false, + [Parameter(Position=2)] + [string]$Indent = "" + ) + + begin + { # set default values + $EnableVerbose = $PSCmdlet.MyInvocation.BoundParameters["Verbose"] + $EnableDebug = $PSCmdlet.MyInvocation.BoundParameters["Debug"] + if ($EnableVerbose -eq $null) { $EnableVerbose = $false } + if ($EnableDebug -eq $null) { $EnableDebug = $false } + if ($EnableDebug -eq $true) { $EnableVerbose = $true } + + $ErrorRecordFound = $false + } + + process + { if (-not $InputObject) + { Write-Host "Empty pipeline!" } + elseif ($InputObject -is [string]) + { if ($InputObject.StartsWith("vcom ")) + { if ($EnableVerbose) { Write-Host "${Indent}$InputObject" -ForegroundColor Gray } } + elseif ($InputObject.StartsWith("-- Loading ")) + { if ($EnableVerbose) { Write-Host "${Indent}$InputObject" -ForegroundColor Gray } } + elseif ($InputObject.StartsWith("-- Compiling ")) + { if ($EnableVerbose) { Write-Host "${Indent}$InputObject" -ForegroundColor Gray } } + elseif ($InputObject.StartsWith("** Warning:") -and -not $SuppressWarnings) + { Write-Host "${Indent}WARNING: " -NoNewline -ForegroundColor Yellow + Write-Host $InputObject.Substring(12) + } + elseif ($InputObject.StartsWith("** Fatal:") -or $InputObject.StartsWith("# ** Fatal:")) + { Write-Host "${Indent}ERROR: " -NoNewline -ForegroundColor Red + Write-Host $InputObject.Substring(10) + } + elseif ($InputObject.StartsWith("** Error:") -or $InputObject.StartsWith("# ** Error:")) + { Write-Host "${Indent}FATAL: " -NoNewline -ForegroundColor Red + Write-Host $InputObject.Substring(10) + } + elseif ($InputObject.StartsWith("Start time:")) + { if ($EnableVerbose) { Write-Host "${Indent}$InputObject" -ForegroundColor Gray } } + elseif ($InputObject.StartsWith("End time:")) + { if ($EnableVerbose) { Write-Host "${Indent}$InputObject" -ForegroundColor Gray } } + elseif ($InputObject.StartsWith("QuestaSim-64 vcom")) + { if ($EnableDebug) { Write-Host "${Indent}$InputObject" -ForegroundColor DarkGray } } + elseif ($InputObject -match "Errors: (\d+), Warnings: (\d+)") + { if ($EnableVerbose) + { if ($Matches[1] -eq 0) + { Write-Host "${Indent}Errors: 0" -NoNewline -ForegroundColor Gray } + else + { Write-Host "${Indent}Errors: ${Matches[1]}" -NoNewline -ForegroundColor Red } + Write-Host ", " -NoNewline + if ($Matches[2] -eq 0) + { Write-Host "Warnings: 0" -ForegroundColor Gray } + else + { Write-Host "Warnings: ${Matches[2]}" -ForegroundColor Yellow } + } + else + { if ($Matches[1] -gt 0) { Write-Host "${Indent}Errors: ${Matches[1]}" -ForegroundColor Red } + if ($Matches[2] -gt 0) { Write-Host "${Indent}Warnings: ${Matches[2]}" -ForegroundColor Yellow } } } else { $ErrorRecordFound = $true - Write-Host $InputObject + Write-Host "${Indent}$InputObject" } } else @@ -957,3 +1205,6 @@ Export-ModuleMember -Function 'Close-VivadoEnvironment' Export-ModuleMember -Function 'Restore-NativeCommandStream' Export-ModuleMember -Function 'Write-ColoredGHDLLine' Export-ModuleMember -Function 'Write-ColoredActiveHDLLine' +Export-ModuleMember -Function 'Write-ColoredQuestaVLibLine' +Export-ModuleMember -Function 'Write-ColoredQuestaVMapLine' +Export-ModuleMember -Function 'Write-ColoredQuestaVComLine' From 888877872413f9574a998b5f143b0c6191b03254 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 10 Nov 2016 23:59:09 +0100 Subject: [PATCH 23/97] Mark QuestaSim/ModelSim runs in GUI mode as "GUI RUN" instead of "SIM ERR". --- py/Base/Simulator.py | 16 ++++++++---- py/DataBase/TestCase.py | 5 ++-- py/PoC.py | 39 +++++++++++++++++----------- py/Simulator/QuestaSimulator.py | 2 +- py/ToolChains/Mentor/QuestaSim.py | 42 ++++++++++++++++++------------- 5 files changed, 64 insertions(+), 40 deletions(-) diff --git a/py/Base/Simulator.py b/py/Base/Simulator.py index 73fa7e6f..3ca939a3 100644 --- a/py/Base/Simulator.py +++ b/py/Base/Simulator.py @@ -50,8 +50,8 @@ from Base.Logging import LogEntry from Base.Project import Environment, VHDLVersion from Base.Shared import Shared, to_time -from DataBase.Entity import WildCard -from DataBase.TestCase import TestCase, SimulationStatus, TestSuite +from DataBase.Entity import WildCard +from DataBase.TestCase import TestCase, SimulationStatus, TestSuite VHDL_TESTBENCH_LIBRARY_NAME = "test" @@ -63,6 +63,9 @@ class SimulatorException(ExceptionBase): class SkipableSimulatorException(SimulatorException, SkipableException): pass +class PoCSimulationResultNotFoundException(SkipableSimulatorException): + pass + @unique class SimulationState(Enum): @@ -80,6 +83,7 @@ class SimulationResult(Enum): Failed = 2 NoAsserts = 3 Passed = 4 + GUIRun = 5 class Simulator(Shared): @@ -246,7 +250,8 @@ def PrintOverallSimulationReport(self): SimulationStatus.SimulationError: "RED", SimulationStatus.SimulationFailed: "RED", SimulationStatus.SimulationNoAsserts: "YELLOW", - SimulationStatus.SimulationSuccess: "GREEN" + SimulationStatus.SimulationSuccess: "GREEN", + SimulationStatus.SimulationGUIRun: "YELLOW" } __SIMULATION_REPORT_STATUS_TEXT_TABLE__ = { @@ -258,7 +263,8 @@ def PrintOverallSimulationReport(self): SimulationStatus.SimulationError: "SIM. ERROR", SimulationStatus.SimulationFailed: "FAILED", SimulationStatus.SimulationNoAsserts: "NO ASSERTS", - SimulationStatus.SimulationSuccess: "PASSED" + SimulationStatus.SimulationSuccess: "PASSED", + SimulationStatus.SimulationGUIRun: "GUI RUN" } def PrintSimulationReportLine(self, testObject, indent, nameColumnWidth): @@ -307,4 +313,4 @@ def PoCSimulationResultFilter(gen, simulationResult): yield line - if (state != 6): raise SkipableSimulatorException("No PoC Testbench Report in simulator output found.") + if (state != 6): raise PoCSimulationResultNotFoundException("No PoC Testbench Report in simulator output found.") diff --git a/py/DataBase/TestCase.py b/py/DataBase/TestCase.py index 82b9694a..c49044c1 100644 --- a/py/DataBase/TestCase.py +++ b/py/DataBase/TestCase.py @@ -54,6 +54,7 @@ class SimulationStatus(Enum): SimulationFailed = 10 SimulationNoAsserts = 15 SimulationSuccess = 20 + SimulationGUIRun = 30 @unique class CompileStatus(Enum): @@ -282,14 +283,14 @@ def __init__(self, testbench): @property def Testbench(self): return self._test - def UpdateStatus(self, testResult): if (testResult is testResult.NotRun): self._status = SimulationStatus.Unknown elif (testResult is testResult.Error): self._status = SimulationStatus.SimulationError elif (testResult is testResult.Failed): self._status = SimulationStatus.SimulationFailed elif (testResult is testResult.NoAsserts): self._status = SimulationStatus.SimulationNoAsserts elif (testResult is testResult.Passed): self._status = SimulationStatus.SimulationSuccess - else: raise IndentationError("Wuhu1") + elif (testResult is testResult.GUIRun): self._status = SimulationStatus.SimulationGUIRun + else: raise ValueError("Unsupported value in 'testResult'.") class Synthesis(TestBase): diff --git a/py/PoC.py b/py/PoC.py index 857709b0..ab5b8eff 100644 --- a/py/PoC.py +++ b/py/PoC.py @@ -77,20 +77,29 @@ from lib.pyAttribute import Attribute +__author__ = "Patrick Lehmann, Martin Zabel" +__copyright__ = "Copyright 2007-2016 Technische Universitaet Dresden - Germany, Chair of VLSI-Design, Diagnostics and Architecture" +__maintainer__ = "Patrick Lehmann" +__email__ = "Patrick.Lehmann@tu-dresden.de" +__version__ = "1.1.0" +__status__ = "Production" +__license__ = "Apache License 2.0" + + class PoCEntityAttribute(Attribute): def __call__(self, func): - self._AppendAttribute(func, ArgumentAttribute(metavar="", dest="FQN", type=str, nargs='+', help="A space separated list of PoC entities.")) + self._AppendAttribute(func, ArgumentAttribute(metavar="PoC Entity", dest="FQN", type=str, nargs='+', help="A space separated list of PoC entities.")) return func class BoardDeviceAttributeGroup(Attribute): def __call__(self, func): - self._AppendAttribute(func, ArgumentAttribute("--device", metavar="", dest="DeviceName", help="The target platform's device name.")) - self._AppendAttribute(func, ArgumentAttribute("--board", metavar="", dest="BoardName", help="The target platform's board name.")) + self._AppendAttribute(func, ArgumentAttribute("--device", metavar="DeviceName", dest="DeviceName", help="The target platform's device name.")) + self._AppendAttribute(func, ArgumentAttribute("--board", metavar="BoardName", dest="BoardName", help="The target platform's board name.")) return func class VHDLVersionAttribute(Attribute): def __call__(self, func): - self._AppendAttribute(func, ArgumentAttribute("--std", metavar="", dest="VHDLVersion", help="Simulate with VHDL-??")) + self._AppendAttribute(func, ArgumentAttribute("--std", metavar="VHDLVersion", dest="VHDLVersion", help="Simulate with VHDL-??")) return func class GUIModeAttribute(Attribute): @@ -298,8 +307,8 @@ def __PrepareForSynthesis(self): @CommonSwitchArgumentAttribute("-d", "--debug", dest="debug", help="enable debug mode") @CommonSwitchArgumentAttribute("-v", "--verbose", dest="verbose", help="print out detailed messages") @CommonSwitchArgumentAttribute("-q", "--quiet", dest="quiet", help="reduce messages to a minimum") - @CommonArgumentAttribute("--sln", metavar="", dest="SolutionID", help="Solution name") - @CommonArgumentAttribute("--prj", metavar="", dest="ProjectID", help="Solution name") + @CommonArgumentAttribute("--sln", metavar="SolutionID", dest="SolutionID", help="Solution name") + @CommonArgumentAttribute("--prj", metavar="ProjectID", dest="ProjectID", help="Solution name") def Run(self): ArgParseMixin.Run(self) @@ -333,7 +342,7 @@ def HandleDefault(self, _): # create the sub-parser for the "help" command # ---------------------------------------------------------------------------- @CommandAttribute("help", help="help help") - @ArgumentAttribute(metavar="", dest="Command", type=str, nargs="?", help="Print help page(s) for a command.") + @ArgumentAttribute(metavar="Command", dest="Command", type=str, nargs="?", help="Print help page(s) for a command.") def HandleHelp(self, args): self.PrintHeadline() if (args.Command is None): @@ -352,7 +361,7 @@ def HandleHelp(self, args): # ---------------------------------------------------------------------------- @CommandGroupAttribute("Configuration commands") # mccabe:disable=MC0001 @CommandAttribute("configure", help="Configure vendor tools for PoC.") - @ArgumentAttribute(metavar="", dest="ToolChain", type=str, nargs="?", help="Specify a tool chain to be configured.") + @ArgumentAttribute(metavar="ToolChain", dest="ToolChain", type=str, nargs="?", help="Specify a tool chain to be configured.") def HandleConfiguration(self, args): self.PrintHeadline() @@ -508,7 +517,7 @@ def HandleListSolution(self, _): #args # ---------------------------------------------------------------------------- @CommandGroupAttribute("Configuration commands") @CommandAttribute("remove-solution", help="Add a solution to PoC.") - @ArgumentAttribute(metavar="", dest="SolutionID", type=str, help="Solution name.") + @ArgumentAttribute(metavar="SolutionID", dest="SolutionID", type=str, help="Solution name.") def HandleRemoveSolution(self, args): self.PrintHeadline() self.__PrepareForConfiguration() @@ -565,7 +574,7 @@ def HandleListProject(self, args): # ---------------------------------------------------------------------------- # @CommandGroupAttribute("Configuration commands") # @CommandAttribute("remove-project", help="Add a project to PoC.") - # @ArgumentAttribute(metavar="", dest="Project", type=str, help="Project name.") + # @ArgumentAttribute(metavar="Project", dest="Project", type=str, help="Project name.") # def HandleRemoveProject(self, args): # self.PrintHeadline() # self.__PrepareForConfiguration() @@ -599,7 +608,7 @@ def HandleListProject(self, args): # ---------------------------------------------------------------------------- # @CommandGroupAttribute("Configuration commands") # @CommandAttribute("remove-ipcore", help="Add a ipcore to PoC.") - # @ArgumentAttribute(metavar="", dest="IPCore", type=str, help="IPCore name.") + # @ArgumentAttribute(metavar="IPCore", dest="IPCore", type=str, help="IPCore name.") # def HandleRemoveIPCore(self, args): # self.PrintHeadline() # self.__PrepareForConfiguration() @@ -618,7 +627,7 @@ def HandleListProject(self, args): # ---------------------------------------------------------------------------- # @CommandGroupAttribute("Configuration commands") # @CommandAttribute("remove-testbench", help="Add a testbench to PoC.") - # @ArgumentAttribute(metavar="", dest="Testbench", type=str, help="Testbench name.") + # @ArgumentAttribute(metavar="Testbench", dest="Testbench", type=str, help="Testbench name.") # def HandleRemoveTestbench(self, args): # self.PrintHeadline() # self.__PrepareForConfiguration() @@ -628,7 +637,7 @@ def HandleListProject(self, args): # ---------------------------------------------------------------------------- @CommandGroupAttribute("Configuration commands") @CommandAttribute("query", help="Simulate a PoC Entity with Aldec Active-HDL") - @ArgumentAttribute(metavar="", dest="Query", type=str, help="todo help") + @ArgumentAttribute(metavar="Query", dest="Query", type=str, help="todo help") def HandleQueryConfiguration(self, args): self.__PrepareForConfiguration() query = Query(self) @@ -687,7 +696,7 @@ def _CheckISEEnvironment(self): @CommandGroupAttribute("Simulation commands") # mccabe:disable=MC0001 @CommandAttribute("list-testbench", help="List all testbenches") @PoCEntityAttribute() - @ArgumentAttribute("--kind", metavar="", dest="TestbenchKind", help="Testbench kind: VHDL | COCOTB") + @ArgumentAttribute("--kind", metavar="Kind", dest="TestbenchKind", help="Testbench kind: VHDL | COCOTB") def HandleListTestbenches(self, args): self.PrintHeadline() self.__PrepareForSimulation() @@ -920,7 +929,7 @@ def HandleCocotbSimulation(self, args): @CommandGroupAttribute("Simulation commands") @CommandAttribute("list-netlist", help="List all netlists") @PoCEntityAttribute() - @ArgumentAttribute("--kind", metavar="", dest="NetlistKind", help="Netlist kind: Lattice | Quartus | XST | CoreGen") + @ArgumentAttribute("--kind", metavar="Kind", dest="NetlistKind", help="Netlist kind: Lattice | Quartus | XST | CoreGen") def HandleListNetlist(self, args): self.PrintHeadline() self.__PrepareForSynthesis() diff --git a/py/Simulator/QuestaSimulator.py b/py/Simulator/QuestaSimulator.py index 5df6a7b4..80fcc9bd 100644 --- a/py/Simulator/QuestaSimulator.py +++ b/py/Simulator/QuestaSimulator.py @@ -158,7 +158,7 @@ def _RunSimulation(self, testbench): def _RunSimulationWithGUI(self, testbench): tclGUIFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['vSimGUIScript'] - tclWaveFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['vSimWaveScript'] + tclWaveFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['vSimWaveScript'] # create a QuestaSimulator instance vsim = self._toolChain.GetSimulator() diff --git a/py/ToolChains/Mentor/QuestaSim.py b/py/ToolChains/Mentor/QuestaSim.py index a7328566..7c8cf469 100644 --- a/py/ToolChains/Mentor/QuestaSim.py +++ b/py/ToolChains/Mentor/QuestaSim.py @@ -48,7 +48,7 @@ from Base.Exceptions import PlatformNotSupportedException from Base.Logging import LogEntry, Severity from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException -from Base.Simulator import SimulationResult, PoCSimulationResultFilter +from Base.Simulator import SimulationResult, PoCSimulationResultFilter, PoCSimulationResultNotFoundException from Base.Executable import Executable from Base.Executable import ExecutableArgument, ShortFlagArgument, ShortTupleArgument, PathArgument, StringArgument, CommandLineArgumentList from ToolChains.Mentor.Mentor import MentorException @@ -296,51 +296,54 @@ class Executable(metaclass=ExecutableArgument): _value = None class FlagQuietMode(metaclass=ShortFlagArgument): - _name = "quiet" # Do not report 'Loading...' messages" + _name = "quiet" # Do not report 'Loading...' messages" _value = None class FlagBatchMode(metaclass=ShortFlagArgument): - _name = "batch" + _name = "batch" _value = None class FlagGuiMode(metaclass=ShortFlagArgument): - _name = "gui" + _name = "gui" _value = None class SwitchBatchCommand(metaclass=ShortTupleArgument): - _name = "do" + _name = "do" _value = None class FlagCommandLineMode(metaclass=ShortFlagArgument): - _name = "c" + _name = "c" _value = None class SwitchModelSimIniFile(metaclass=ShortTupleArgument): - _name = "modelsimini" + _name = "modelsimini" _value = None class FlagOptimization(metaclass=ShortFlagArgument): - _name = "vopt" + _name = "vopt" _value = None class FlagReportAsError(metaclass=ShortTupleArgument): - _name = "error" + _name = "error" _value = None class SwitchTimeResolution(metaclass=ShortTupleArgument): - _name = "t" # -t [1|10|100]fs|ps|ns|us|ms|sec Time resolution limit + _name = "t" # -t [1|10|100]fs|ps|ns|us|ms|sec Time resolution limit _value = None class ArgLogFile(metaclass=ShortTupleArgument): - _name = "l" # what's the difference to -logfile ? + _name = "l" # what's the difference to -logfile ? _value = None + class ArgKeepStdOut(metaclass=ShortFlagArgument): + _name = "keepstdout" + class ArgVHDLLibraryName(metaclass=ShortTupleArgument): - _name = "lib" + _name = "lib" _value = None class ArgOnFinishMode(metaclass=ShortTupleArgument): - _name = "onfinish" + _name = "onfinish" _value = None # Customize the kernel shutdown behavior at the end of simulation; Valid modes: ask, stop, exit, final (Default: ask) class SwitchTopLevel(metaclass=StringArgument): @@ -357,6 +360,7 @@ class SwitchTopLevel(metaclass=StringArgument): FlagOptimization, FlagReportAsError, ArgLogFile, + ArgKeepStdOut, ArgVHDLLibraryName, SwitchTimeResolution, ArgOnFinishMode, @@ -372,10 +376,10 @@ def Simulate(self): except Exception as ex: raise QuestaSimException("Failed to launch vsim run.") from ex - self._hasOutput = False + self._hasOutput = False self._hasWarnings = False - self._hasErrors = False - simulationResult = CallByRefParam(SimulationResult.Error) + self._hasErrors = False + simulationResult = CallByRefParam(SimulationResult.Error) try: iterator = iter(PoCSimulationResultFilter(QuestaVSimFilter(self.GetReader()), simulationResult)) @@ -394,6 +398,9 @@ def Simulate(self): line.IndentBy(self.Logger.BaseIndent + 1) self.Log(line) + except PoCSimulationResultNotFoundException: + if self.Parameters[self.FlagGuiMode]: + simulationResult <<= SimulationResult.GUIRun except StopIteration: pass finally: @@ -402,6 +409,7 @@ def Simulate(self): return simulationResult.value + class QuestaVHDLLibraryTool(Executable, QuestaSimMixIn): def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): QuestaSimMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) @@ -425,7 +433,7 @@ def HasWarnings(self): def HasErrors(self): return self._hasErrors - class Executable(metaclass=ExecutableArgument): pass + class Executable(metaclass=ExecutableArgument): pass class SwitchLibraryName(metaclass=StringArgument): pass Parameters = CommandLineArgumentList( From b8312dac8526d1490cec1117186e04d54b83cdc0 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 10 Nov 2016 23:59:53 +0100 Subject: [PATCH 24/97] Fixed `<<=` operator in CallByRefParam. --- py/lib/Functions.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/py/lib/Functions.py b/py/lib/Functions.py index 90dc5a2d..03a85829 100644 --- a/py/lib/Functions.py +++ b/py/lib/Functions.py @@ -48,8 +48,9 @@ class CallByRefParam: def __init__(self, value=None): self.value = value - def __lshift__(self, other): + def __ilshift__(self, other): self.value = other + return self def __eq__(self, other): return self.value == other def __ne__(self, other): return self.value != other From 07031db10ba8a86eda55712c8299cc3c57043722 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 11 Nov 2016 00:03:26 +0100 Subject: [PATCH 25/97] Published tristate_driver procedures for T_IO_TRISTATE and the IIC bus. --- py/lib/Functions.py | 1 - src/io/iic/iic.pkg.vhdl | 152 ++++++++++++++++++++++++++++++++++++++++ src/io/io.pkg.vhdl | 20 ++++++ 3 files changed, 172 insertions(+), 1 deletion(-) create mode 100644 src/io/iic/iic.pkg.vhdl diff --git a/py/lib/Functions.py b/py/lib/Functions.py index 03a85829..e63008f3 100644 --- a/py/lib/Functions.py +++ b/py/lib/Functions.py @@ -30,7 +30,6 @@ # limitations under the License. # ============================================================================== # - from functools import reduce from operator import or_ from sys import version_info diff --git a/src/io/iic/iic.pkg.vhdl b/src/io/iic/iic.pkg.vhdl new file mode 100644 index 00000000..7456512a --- /dev/null +++ b/src/io/iic/iic.pkg.vhdl @@ -0,0 +1,152 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Patrick Lehmann +-- +-- Package: VHDL package for component declarations, types and +-- functions associated to the PoC.io.iic namespace +-- +-- Description: +-- ------------------------------------- +-- For detailed documentation see below. +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany, +-- Chair of VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +library PoC; +use PoC.utils.all; +use PoC.physical.all; +use PoC.io.all; + + +package iic is + type T_IO_IIC_SERIAL is record + Clock : T_IO_TRISTATE; + Data : T_IO_TRISTATE; + end record; + + type T_IO_IIC_SERIAL_PCB is record + Clock : std_logic; + Data : std_logic; + end record; + + type T_IO_IIC_SERIAL_VECTOR is array(natural range <>) of T_IO_IIC_SERIAL; + type T_IO_IIC_SERIAL_PCB_VECTOR is array(natural range <>) of T_IO_IIC_SERIAL_PCB; + + -- Drive std_logic values from Tri-State signals and in reverse. + -- Use this procedure only in simulation + procedure io_tristate_driver ( + signal pad : inout T_IO_IIC_SERIAL_PCB; + signal iot : inout T_IO_IIC_SERIAL + ); + + -- IICBusController + -- ========================================================================================================================================================== + type T_IO_IIC_BUSMODE is ( + IO_IIC_BUSMODE_SMBUS, -- 100 kHz; additional timing restrictions + IO_IIC_BUSMODE_STANDARDMODE, -- 100 kHz + IO_IIC_BUSMODE_FASTMODE, -- 400 kHz + IO_IIC_BUSMODE_FASTMODEPLUS, -- 1.000 kHz + IO_IIC_BUSMODE_HIGHSPEEDMODE, -- 3.400 kHz + IO_IIC_BUSMODE_ULTRAFASTMODE -- 5.000 kHz; unidirectional + ); + + type T_IO_IICBUS_COMMAND is ( + IO_IICBUS_CMD_NONE, + IO_IICBUS_CMD_SEND_START_CONDITION, + IO_IICBUS_CMD_SEND_RESTART_CONDITION, + IO_IICBUS_CMD_SEND_STOP_CONDITION, + IO_IICBUS_CMD_SEND_LOW, + IO_IICBUS_CMD_SEND_HIGH, + IO_IICBUS_CMD_RECEIVE + ); + + type T_IO_IICBUS_STATUS is ( + IO_IICBUS_STATUS_RESETING, + IO_IICBUS_STATUS_IDLE, + IO_IICBUS_STATUS_SENDING, + IO_IICBUS_STATUS_SEND_COMPLETE, + IO_IICBUS_STATUS_RECEIVING, + IO_IICBUS_STATUS_RECEIVED_START_CONDITION, + IO_IICBUS_STATUS_RECEIVED_STOP_CONDITION, + IO_IICBUS_STATUS_RECEIVED_LOW, + IO_IICBUS_STATUS_RECEIVED_HIGH, + IO_IICBUS_STATUS_ERROR, + IO_IICBUS_STATUS_BUS_ERROR + ); + + -- IICController + -- ========================================================================================================================================================== + type T_IO_IIC_COMMAND is ( + IO_IIC_CMD_NONE, + IO_IIC_CMD_QUICKCOMMAND_READ, -- use this to check for an device address + IO_IIC_CMD_QUICKCOMMAND_WRITE, + IO_IIC_CMD_SEND_BYTES, + IO_IIC_CMD_RECEIVE_BYTES, + IO_IIC_CMD_PROCESS_CALL + ); + + type T_IO_IIC_STATUS is ( + IO_IIC_STATUS_IDLE, + IO_IIC_STATUS_EXECUTING, + IO_IIC_STATUS_EXECUTE_OK, + IO_IIC_STATUS_EXECUTE_FAILED, + IO_IIC_STATUS_SENDING, + IO_IIC_STATUS_SEND_COMPLETE, + IO_IIC_STATUS_RECEIVING, + IO_IIC_STATUS_RECEIVE_COMPLETE, + IO_IIC_STATUS_CALLING, + IO_IIC_STATUS_CALL_COMPLETE, + IO_IIC_STATUS_ERROR + ); + + type T_IO_IIC_ERROR is ( + IO_IIC_ERROR_NONE, + IO_IIC_ERROR_ADDRESS_ERROR, + IO_IIC_ERROR_ACK_ERROR, + IO_IIC_ERROR_BUS_ERROR, + IO_IIC_ERROR_FSM + ); + + type T_IO_IIC_COMMAND_VECTOR is array(natural range <>) of T_IO_IIC_COMMAND; + type T_IO_IIC_STATUS_VECTOR is array(natural range <>) of T_IO_IIC_STATUS; + type T_IO_IIC_ERROR_VECTOR is array(natural range <>) of T_IO_IIC_ERROR; +end package; + + +package body iic is + procedure io_tristate_driver ( + signal pad : inout T_IO_IIC_SERIAL_PCB; + signal iot : inout T_IO_IIC_SERIAL + ) is + begin + pad.Clock <= ite((iot.Clock.t = '1'), 'Z', iot.Clock.o); + iot.Clock.i <= pad.Clock; + iot.Clock.t <= 'Z'; -- drive all record members + iot.Clock.o <= 'Z'; -- drive all record members + pad.Data <= ite((iot.Data.t = '1'), 'Z', iot.Data.o); + iot.Data.i <= pad.Data; + iot.Data.t <= 'Z'; -- drive all record members + iot.Data.o <= 'Z'; -- drive all record members + end procedure; +end package body; diff --git a/src/io/io.pkg.vhdl b/src/io/io.pkg.vhdl index bd692040..7bcbf99f 100644 --- a/src/io/io.pkg.vhdl +++ b/src/io/io.pkg.vhdl @@ -57,6 +57,13 @@ package io is type T_IO_DATARATE is (IO_DATARATE_SDR, IO_DATARATE_DDR, IO_DATARATE_QDR); + -- Drive a std_logic_vector from a Tri-State bus and in reverse. + -- Use this procedure only in simulation + procedure io_tristate_driver ( + signal pad : inout std_logic_vector; + signal tristate : inout T_IO_TRISTATE_VECTOR + ); + type T_IO_7SEGMENT_CHAR is ( IO_7SEGMENT_CHAR_0, IO_7SEGMENT_CHAR_1, IO_7SEGMENT_CHAR_2, IO_7SEGMENT_CHAR_3, IO_7SEGMENT_CHAR_4, IO_7SEGMENT_CHAR_5, IO_7SEGMENT_CHAR_6, IO_7SEGMENT_CHAR_7, @@ -159,6 +166,19 @@ end package; package body io is + procedure io_tristate_driver ( + signal pad : inout std_logic_vector; + signal tristate : inout T_IO_TRISTATE_VECTOR + ) is + begin + for k in pad'range loop + pad(k) <= ite((tristate(k).t = '1'), 'Z', tristate(k).o); + tristate(k).i <= pad(k); + tristate(k).t <= 'Z'; -- drive all record members + tristate(k).o <= 'Z'; -- drive all record members + end loop; + end procedure; + function io_7SegmentDisplayEncoding(hex : std_logic_vector(3 downto 0); dot : std_logic := '0'; WITH_DOT : boolean := FALSE) return std_logic_vector is constant DOT_INDEX : positive := ite(WITH_DOT, 7, 6); variable Result : std_logic_vector(ite(WITH_DOT, 7, 6) downto 0); From 1236c7c91723376262d3ad756b6cf8702aed585c Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 12 Nov 2016 08:31:05 +0100 Subject: [PATCH 26/97] Updated documentation. Automatically documented Python Infrastructure. --- .gitignore | 1 + docs/GetInvolved/Authors.rst | 5 +- docs/GetInvolved/index.rst | 2 +- docs/{PoC => IPCores}/alt/index.rst | 0 docs/{PoC => IPCores}/arith/arith.pkg.rst | 0 docs/{PoC => IPCores}/arith/arith_addw.rst | 0 .../arith/arith_bcdcollect.rst | 0 .../arith/arith_carrychain_inc.rst | 0 docs/{PoC => IPCores}/arith/arith_cca.rst | 0 .../arith/arith_convert_bin2bcd.rst | 0 .../arith/arith_counter_bcd.rst | 0 .../arith/arith_counter_free.rst | 0 .../arith/arith_counter_gray.rst | 0 .../arith/arith_counter_ring.rst | 0 docs/{PoC => IPCores}/arith/arith_div.rst | 0 .../{PoC => IPCores}/arith/arith_firstone.rst | 0 .../arith/arith_muls_wide.rst | 0 .../arith/arith_prefix_and.rst | 0 .../arith/arith_prefix_or.rst | 0 docs/{PoC => IPCores}/arith/arith_prng.rst | 0 docs/{PoC => IPCores}/arith/arith_same.rst | 0 docs/{PoC => IPCores}/arith/arith_scaler.rst | 0 .../arith/arith_shifter_barrel.rst | 0 docs/{PoC => IPCores}/arith/arith_sqrt.rst | 0 docs/{PoC => IPCores}/arith/index.rst | 0 docs/{PoC => IPCores}/bus/bus_Arbiter.rst | 0 docs/{PoC => IPCores}/bus/index.rst | 0 docs/{PoC => IPCores}/bus/stream/index.rst | 0 .../bus/stream/stream_Buffer.rst | 0 .../bus/stream/stream_DeMux.rst | 0 .../bus/stream/stream_FrameGenerator.rst | 0 .../bus/stream/stream_Mirror.rst | 0 .../bus/stream/stream_Mux.rst | 0 .../bus/stream/stream_Sink.rst | 0 .../bus/stream/stream_Source.rst | 0 docs/{PoC => IPCores}/bus/wb/index.rst | 0 .../bus/wb/wb_fifo_adapter.rst | 0 docs/{PoC => IPCores}/bus/wb/wb_ocram.rst | 0 .../bus/wb/wb_uart_wrapper.rst | 0 docs/{PoC => IPCores}/cache/cache_par.rst | 0 .../cache/cache_replacement_policy.rst | 0 .../cache/cache_tagunit_par.rst | 0 .../cache/cache_tagunit_seq.rst | 0 docs/{PoC => IPCores}/cache/index.rst | 0 docs/{PoC => IPCores}/comm/comm_crc.rst | 0 docs/{PoC => IPCores}/comm/comm_scramble.rst | 0 docs/{PoC => IPCores}/comm/index.rst | 0 docs/{PoC => IPCores}/common/components.rst | 0 docs/{PoC => IPCores}/common/config.rst | 0 docs/{PoC => IPCores}/common/context.rst | 0 docs/{PoC => IPCores}/common/fileio.rst | 0 docs/{PoC => IPCores}/common/index.rst | 0 docs/{PoC => IPCores}/common/math.rst | 0 docs/{PoC => IPCores}/common/strings.rst | 0 docs/{PoC => IPCores}/common/utils.rst | 0 docs/{PoC => IPCores}/common/vectors.rst | 0 docs/{PoC => IPCores}/fifo/fifo.pkg.rst | 0 docs/{PoC => IPCores}/fifo/fifo_cc_got.rst | 0 .../fifo/fifo_cc_got_tempgot.rst | 0 .../fifo/fifo_cc_got_tempput.rst | 0 docs/{PoC => IPCores}/fifo/fifo_dc_got_sm.rst | 0 docs/{PoC => IPCores}/fifo/fifo_glue.rst | 0 .../fifo/fifo_ic_assembly.rst | 0 docs/{PoC => IPCores}/fifo/fifo_ic_got.rst | 0 docs/{PoC => IPCores}/fifo/fifo_shift.rst | 0 docs/{PoC => IPCores}/fifo/index.rst | 0 docs/{PoC => IPCores}/index.rst | 0 docs/{PoC => IPCores}/io/ddrio/ddrio_in.rst | 0 .../{PoC => IPCores}/io/ddrio/ddrio_inout.rst | 0 docs/{PoC => IPCores}/io/ddrio/ddrio_out.rst | 0 docs/{PoC => IPCores}/io/ddrio/index.rst | 0 .../io/iic/iic_BusController.rst | 0 .../io/iic/iic_Controller.rst | 0 .../io/iic/iic_Controller_SFF8431.rst | 0 .../io/iic/iic_Switch_PCA9548A.rst | 0 docs/{PoC => IPCores}/io/iic/index.rst | 0 docs/{PoC => IPCores}/io/index.rst | 0 docs/{PoC => IPCores}/io/io.pkg.rst | 0 .../io/io_7SegmentMux_BCD.rst | 0 .../io/io_7SegmentMux_HEX.rst | 0 docs/{PoC => IPCores}/io/io_Debounce.rst | 0 docs/{PoC => IPCores}/io/io_FanControl.rst | 0 .../io/io_FrequencyCounter.rst | 0 docs/{PoC => IPCores}/io/io_GlitchFilter.rst | 0 docs/{PoC => IPCores}/io/io_KeyPadScanner.rst | 0 .../io/io_PulseWidthModulation.rst | 0 docs/{PoC => IPCores}/io/io_TimingCounter.rst | 0 docs/{PoC => IPCores}/io/jtag/index.rst | 0 docs/{PoC => IPCores}/io/lcd/BCDDigit.rst | 0 docs/{PoC => IPCores}/io/lcd/index.rst | 0 .../{PoC => IPCores}/io/lcd/lcd_LCDBuffer.rst | 0 .../io/lcd/lcd_LCDBusController.rst | 0 .../io/lcd/lcd_LCDController_KS0066U.rst | 0 .../io/lcd/lcd_LCDSynchronizer.rst | 0 .../{PoC => IPCores}/io/lcd/lcd_dotmatrix.rst | 0 docs/{PoC => IPCores}/io/mdio/index.rst | 0 .../io/mdio/mdio_BusController.rst | 0 .../io/mdio/mdio_Controller.rst | 0 .../io/mdio/mdio_IIC_Adapter.rst | 0 docs/{PoC => IPCores}/io/ow/index.rst | 0 .../io/ow/ow_BusController.rst | 0 docs/{PoC => IPCores}/io/ow/ow_Controller.rst | 0 docs/{PoC => IPCores}/io/pio/index.rst | 0 docs/{PoC => IPCores}/io/pio/pio_fifo_in.rst | 0 docs/{PoC => IPCores}/io/pio/pio_fifo_out.rst | 0 docs/{PoC => IPCores}/io/pio/pio_in.rst | 0 docs/{PoC => IPCores}/io/pio/pio_out.rst | 0 docs/{PoC => IPCores}/io/pmod/index.rst | 0 docs/{PoC => IPCores}/io/pmod/pmod_KYPD.rst | 0 docs/{PoC => IPCores}/io/pmod/pmod_SSD.rst | 0 .../{PoC => IPCores}/io/pmod/pmod_USBUART.rst | 0 docs/{PoC => IPCores}/io/ps2/index.rst | 0 docs/{PoC => IPCores}/io/uart/index.rst | 0 docs/{PoC => IPCores}/io/uart/uart_bclk.rst | 0 docs/{PoC => IPCores}/io/uart/uart_fifo.rst | 0 docs/{PoC => IPCores}/io/uart/uart_ft245.rst | 0 docs/{PoC => IPCores}/io/uart/uart_rx.rst | 0 docs/{PoC => IPCores}/io/uart/uart_tx.rst | 0 docs/{PoC => IPCores}/io/vga/index.rst | 0 docs/{PoC => IPCores}/io/vga/vga_phy.rst | 0 .../io/vga/vga_phy_ch7301c.rst | 0 docs/{PoC => IPCores}/io/vga/vga_timing.rst | 0 .../ddr2/ddr2_mem2mig_adapter_Spartan6.rst | 0 docs/{PoC => IPCores}/mem/ddr2/index.rst | 0 .../mem/ddr3/ddr3_mem2mig_adapter_Series7.rst | 0 docs/{PoC => IPCores}/mem/ddr3/index.rst | 0 docs/{PoC => IPCores}/mem/index.rst | 0 docs/{PoC => IPCores}/mem/lut/index.rst | 0 docs/{PoC => IPCores}/mem/lut/lut_Sine.rst | 0 docs/{PoC => IPCores}/mem/mem.pkg.rst | 0 docs/{PoC => IPCores}/mem/ocram/index.rst | 0 .../{PoC => IPCores}/mem/ocram/ocram_esdp.rst | 0 docs/{PoC => IPCores}/mem/ocram/ocram_sdp.rst | 0 docs/{PoC => IPCores}/mem/ocram/ocram_sp.rst | 0 docs/{PoC => IPCores}/mem/ocram/ocram_tdp.rst | 0 docs/{PoC => IPCores}/mem/ocrom/index.rst | 0 docs/{PoC => IPCores}/mem/ocrom/ocrom_dp.rst | 0 docs/{PoC => IPCores}/mem/ocrom/ocrom_sp.rst | 0 docs/{PoC => IPCores}/mem/sdram/index.rst | 11 +- .../mem/sdram/sdram_ctrl_de0.rst | 0 .../mem/sdram/sdram_ctrl_fsm.rst | 0 .../mem/sdram/sdram_ctrl_phy_de0.rst | 0 .../mem/sdram/sdram_ctrl_phy_s3esk.rst | 0 .../mem/sdram/sdram_ctrl_s3esk.rst | 0 .../misc/filter/filter_and.rst | 0 .../misc/filter/filter_mean.rst | 0 .../misc/filter/filter_or.rst | 0 docs/{PoC => IPCores}/misc/filter/index.rst | 0 .../misc/gearbox/gearbox_down_cc.rst | 0 .../misc/gearbox/gearbox_down_dc.rst | 0 .../misc/gearbox/gearbox_up_cc.rst | 0 .../misc/gearbox/gearbox_up_dc.rst | 0 docs/{PoC => IPCores}/misc/gearbox/index.rst | 0 docs/{PoC => IPCores}/misc/index.rst | 0 docs/{PoC => IPCores}/misc/misc.pkg.rst | 0 .../misc/misc_BitwidthConverter.rst | 0 .../misc/misc_ByteAligner.rst | 0 docs/{PoC => IPCores}/misc/misc_Delay.rst | 0 .../misc/misc_FrequencyMeasurement.rst | 0 .../{PoC => IPCores}/misc/misc_PulseTrain.rst | 0 docs/{PoC => IPCores}/misc/misc_Sequencer.rst | 0 .../misc/misc_StrobeGenerator.rst | 0 .../misc/misc_StrobeLimiter.rst | 0 .../misc/misc_WordAligner.rst | 0 docs/{PoC => IPCores}/misc/misc_bit_lz.rst | 0 docs/{PoC => IPCores}/misc/stat/index.rst | 0 .../misc/stat/stat_Average.rst | 0 .../misc/stat/stat_Histogram.rst | 0 .../misc/stat/stat_Maximum.rst | 0 .../misc/stat/stat_Minimum.rst | 0 docs/{PoC => IPCores}/misc/sync/index.rst | 0 docs/{PoC => IPCores}/misc/sync/sync_Bits.rst | 0 .../misc/sync/sync_Command.rst | 0 .../{PoC => IPCores}/misc/sync/sync_Pulse.rst | 0 .../{PoC => IPCores}/misc/sync/sync_Reset.rst | 0 .../misc/sync/sync_Strobe.rst | 0 .../misc/sync/sync_Vector.rst | 0 .../net/arp/arp_BroadCast_Receiver.rst | 0 .../net/arp/arp_BroadCast_Requester.rst | 0 docs/{PoC => IPCores}/net/arp/arp_Cache.rst | 0 docs/{PoC => IPCores}/net/arp/arp_IPPool.rst | 0 docs/{PoC => IPCores}/net/arp/arp_Tester.rst | 0 .../net/arp/arp_UniCast_Receiver.rst | 0 .../net/arp/arp_UniCast_Responder.rst | 0 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py/Compiler/ISECompiler.py | 14 +- py/Compiler/LSECompiler.py | 15 +- py/Compiler/QuartusCompiler.py | 15 +- py/Compiler/VivadoCompiler.py | 17 +- py/Compiler/XCICompiler.py | 15 +- py/Compiler/XCOCompiler.py | 15 +- py/Compiler/XSTCompiler.py | 15 +- py/Compiler/__init__.py | 9 - py/DataBase/Config.py | 29 +- py/DataBase/Entity.py | 33 ++- py/DataBase/Query.py | 17 +- py/DataBase/Solution.py | 20 +- py/DataBase/TestCase.py | 21 +- py/Parser/FilesCodeDOM.py | 23 ++ py/Parser/FilesParser.py | 18 ++ py/Parser/RulesCodeDOM.py | 18 ++ py/Parser/RulesParser.py | 24 +- py/PoC.py | 26 +- py/Simulator/ActiveHDLSimulator.py | 18 +- py/Simulator/CocotbSimulator.py | 21 +- py/Simulator/GHDLSimulator.py | 37 ++- py/Simulator/ISESimulator.py | 18 +- py/Simulator/QuestaSimulator.py | 89 ++++-- py/Simulator/VivadoSimulator.py | 18 +- py/ToolChains/Aldec/ActiveHDL.py | 27 +- py/ToolChains/Aldec/Aldec.py | 17 +- py/ToolChains/Altera/Altera.py | 17 +- py/ToolChains/Altera/ModelSim.py | 17 +- py/ToolChains/Altera/Quartus.py | 28 +- py/ToolChains/GHDL.py | 27 +- py/ToolChains/GNU.py | 18 +- py/ToolChains/GTKWave.py | 22 +- py/ToolChains/Git.py | 24 +- py/ToolChains/Lattice/ActiveHDL.py | 10 +- py/ToolChains/Lattice/Diamond.py | 33 ++- py/ToolChains/Lattice/Lattice.py | 18 +- .../Lattice/{Synopsys.py => Synplify.py} | 22 +- py/ToolChains/Mentor/Mentor.py | 17 +- py/ToolChains/Mentor/QuestaSim.py | 25 +- py/ToolChains/PoC.py | 17 +- py/ToolChains/Synopsys/Synopsys.py | 18 +- py/ToolChains/Xilinx/ISE.py | 31 +- py/ToolChains/Xilinx/Vivado.py | 28 +- py/ToolChains/Xilinx/Xilinx.py | 19 +- py/config.defaults.ini | 7 +- py/lib/CodeDOM.py | 39 +++ py/lib/Decorators.py | 44 ++- py/lib/ExtendedConfigParser/__init__.py | 34 ++- py/lib/Functions.py | 10 + py/lib/Parser.py | 23 ++ py/lib/pyAttribute/ArgParseAttributes.py | 14 + py/lib/pyAttribute/__init__.py | 7 + sim/vSim.default.wdo | 2 +- tools/ReadTheDocs/requirements.txt | 1 + 357 files changed, 1358 insertions(+), 583 deletions(-) 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rename docs/{References => }/Interfaces/CommandStatusError.rst (100%) rename docs/{References => }/Interfaces/Memory.rst (100%) rename docs/{References => }/Interfaces/Stream.rst (100%) rename docs/{References => }/Interfaces/index.rst (66%) create mode 100644 docs/References/Database.rst delete mode 100644 docs/References/Glossary.rst create mode 100644 docs/References/more.rst create mode 100644 docs/genindex.rst rename py/ToolChains/Lattice/{Synopsys.py => Synplify.py} (81%) diff --git a/.gitignore b/.gitignore index a673e46e..77c55071 100644 --- a/.gitignore +++ b/.gitignore @@ -94,3 +94,4 @@ other/diamond/.spreadsheet_view.ini !.git* !.publish !README.md +docs/PyInfrastructure/ diff --git a/docs/GetInvolved/Authors.rst b/docs/GetInvolved/Authors.rst index bb7b061f..672eda18 100644 --- a/docs/GetInvolved/Authors.rst +++ b/docs/GetInvolved/Authors.rst @@ -1,5 +1,6 @@ -.. - Include this file. +.. This file is included. So it needs to marked as orphan to suppress warnings. + +:orphan: ========================= ============================================================ Contributor [#f1]_ Contact E-Mail diff --git a/docs/GetInvolved/index.rst b/docs/GetInvolved/index.rst index 61de8765..8282d047 100644 --- a/docs/GetInvolved/index.rst +++ b/docs/GetInvolved/index.rst @@ -212,7 +212,7 @@ Commit your porposed changes to your feature branch and push all changes to GitH :target: https://github.com/VLSI-EDA/PoC/pulls Go to your forked repository and klick on "Compare and Pull-Request" or go to -our PoC repository and create a new `pull request `_. +our PoC repository and create a new `pull request `_. If this is your first Pull-Request, you need to sign our Contributers License Agreement (CLA). diff --git a/docs/PoC/alt/index.rst b/docs/IPCores/alt/index.rst similarity index 100% rename from docs/PoC/alt/index.rst rename to docs/IPCores/alt/index.rst diff --git a/docs/PoC/arith/arith.pkg.rst b/docs/IPCores/arith/arith.pkg.rst similarity index 100% rename from docs/PoC/arith/arith.pkg.rst rename to docs/IPCores/arith/arith.pkg.rst diff --git a/docs/PoC/arith/arith_addw.rst b/docs/IPCores/arith/arith_addw.rst similarity index 100% rename from docs/PoC/arith/arith_addw.rst rename to docs/IPCores/arith/arith_addw.rst diff --git a/docs/PoC/arith/arith_bcdcollect.rst b/docs/IPCores/arith/arith_bcdcollect.rst similarity index 100% rename from docs/PoC/arith/arith_bcdcollect.rst rename to docs/IPCores/arith/arith_bcdcollect.rst diff --git a/docs/PoC/arith/arith_carrychain_inc.rst b/docs/IPCores/arith/arith_carrychain_inc.rst similarity index 100% rename from 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a/docs/PoC/mem/sdram/index.rst +++ b/docs/IPCores/mem/sdram/index.rst @@ -8,8 +8,7 @@ columns. Different physical layers are provide for the single-data-rate (SDR) or double-data-rate (DDR, DDR2, ...) data bus. One has to instantiate the specific module required by the FPGA board. -SDRAM Controller for the Altera DE0 Board ------------------------------------------ +.. rubric:: SDRAM Controller for the Altera DE0 Board The module :doc:`sdram_ctrl_de0 ` combines the finite state machine :doc:`sdram_ctrl_fsm ` and the DE0 specific physical layer @@ -18,8 +17,7 @@ IS42S16400F SDR memory at a frequency of 133 MHz. A usage example is given in PoC-Examples_. -SDRAM Controller for the Xilinx Spartan-3E Starter Kit (S3ESK) --------------------------------------------------------------- +.. rubric:: SDRAM Controller for the Xilinx Spartan-3E Starter Kit (S3ESK) The module :doc:`sdram_ctrl_s3esk ` combines the finite state machine :doc:`sdram_ctrl_fsm ` and the S3ESK specific physical layer @@ -27,8 +25,9 @@ machine :doc:`sdram_ctrl_fsm ` and the S3ESK specific physical l MT46V32M16-6T DDR memory at a frequency of 100 MHz (DDR-200). A usage example is given in PoC-Examples_. -*Note*: See also :doc:`PoC.xil.mig ` for board specific memory controller -implementations created by Xilinx's Memory Interface Generator (MIG). +.. Note:: + See also :doc:`PoC.xil.mig ` for board specific memory controller + implementations created by Xilinx's Memory Interface Generator (MIG). diff --git a/docs/PoC/mem/sdram/sdram_ctrl_de0.rst b/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst similarity index 100% rename from docs/PoC/mem/sdram/sdram_ctrl_de0.rst rename to docs/IPCores/mem/sdram/sdram_ctrl_de0.rst diff --git a/docs/PoC/mem/sdram/sdram_ctrl_fsm.rst b/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst similarity index 100% rename from docs/PoC/mem/sdram/sdram_ctrl_fsm.rst rename to docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst diff --git a/docs/PoC/mem/sdram/sdram_ctrl_phy_de0.rst b/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst similarity index 100% rename from docs/PoC/mem/sdram/sdram_ctrl_phy_de0.rst rename to docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst diff --git a/docs/PoC/mem/sdram/sdram_ctrl_phy_s3esk.rst b/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst similarity index 100% rename from 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docs/IPCores/xil/xil_DRP_BusSync.rst diff --git a/docs/PoC/xil/xil_ICAP.rst b/docs/IPCores/xil/xil_ICAP.rst similarity index 100% rename from docs/PoC/xil/xil_ICAP.rst rename to docs/IPCores/xil/xil_ICAP.rst diff --git a/docs/PoC/xil/xil_Reconfigurator.rst b/docs/IPCores/xil/xil_Reconfigurator.rst similarity index 100% rename from docs/PoC/xil/xil_Reconfigurator.rst rename to docs/IPCores/xil/xil_Reconfigurator.rst diff --git a/docs/PoC/xil/xil_SystemMonitor.rst b/docs/IPCores/xil/xil_SystemMonitor.rst similarity index 100% rename from docs/PoC/xil/xil_SystemMonitor.rst rename to docs/IPCores/xil/xil_SystemMonitor.rst diff --git a/docs/PoC/xil/xil_SystemMonitor_Series7.rst b/docs/IPCores/xil/xil_SystemMonitor_Series7.rst similarity index 100% rename from docs/PoC/xil/xil_SystemMonitor_Series7.rst rename to docs/IPCores/xil/xil_SystemMonitor_Series7.rst diff --git a/docs/PoC/xil/xil_SystemMonitor_Virtex6.rst b/docs/IPCores/xil/xil_SystemMonitor_Virtex6.rst similarity index 100% rename from docs/PoC/xil/xil_SystemMonitor_Virtex6.rst rename to docs/IPCores/xil/xil_SystemMonitor_Virtex6.rst diff --git a/docs/References/Interfaces/CommandStatusError.rst b/docs/Interfaces/CommandStatusError.rst similarity index 100% rename from docs/References/Interfaces/CommandStatusError.rst rename to docs/Interfaces/CommandStatusError.rst diff --git a/docs/References/Interfaces/Memory.rst b/docs/Interfaces/Memory.rst similarity index 100% rename from docs/References/Interfaces/Memory.rst rename to docs/Interfaces/Memory.rst diff --git a/docs/References/Interfaces/Stream.rst b/docs/Interfaces/Stream.rst similarity index 100% rename from docs/References/Interfaces/Stream.rst rename to docs/Interfaces/Stream.rst diff --git a/docs/References/Interfaces/index.rst b/docs/Interfaces/index.rst similarity index 66% rename from docs/References/Interfaces/index.rst rename to docs/Interfaces/index.rst index 895d4e56..7d67c720 100644 --- a/docs/References/Interfaces/index.rst +++ b/docs/Interfaces/index.rst @@ -1,6 +1,6 @@ -Interfaces -########## +IP Core Interfaces +################## .. toctree:: :maxdepth: 1 diff --git a/docs/References/Database.rst b/docs/References/Database.rst new file mode 100644 index 00000000..fdaedc98 --- /dev/null +++ b/docs/References/Database.rst @@ -0,0 +1,279 @@ + +IP Core Database +################ + +.. contents:: Contents of this Page + :local: + +Overview +******** + +PoC internal IP core database uses INI files and advanced interpolation rules +provided by ExtendedConfigParser_. +The database consists of 5 *.ini files which are in-memory merge to a single +configuration database: + +* ``py\config.boards.ini`` + This files contains all known :doc:`FPGA boards ` and + :doc:`FPGA devices `. +* ``py\config.defaults.ini`` + This files contains all default options and values for all supported nodes + types. +* ``py\config.entity.ini`` + This file contains all IP cores (entities) and theirs corresponding testbench + or netlist settings. +* ``py\config.private.ini`` + This files is created by ``.\poc.ps1 configure`` and contains settings for these + local PoC installation. This files must not be shared with other PoC instances. + See :doc:`Configuring PoC's Infrastructure ` on how + to configure PoC on a local system. +* ``py\config.structure.ini`` + Nodes in these file describe PoC's namespace tree and which IP cores are + assigned to which namespace. + +Additionally, the database refers to *.files and *.rules files. The first file +type describes in an imperative langauge, which files are needed to compile a +simulation or to run a synthesis. the latter file type comprises patch +instructions per IP core. See :doc:`Files Format ` and +:doc:`Rules Format ` for more details. + +.. _ExtendedConfigParser: https://github.com/Paebbels/ExtendedConfigParser + +Database Structure +****************** + +The database is stored in *.ini files, which define an associative array of +`sections` and option lines. The content itself is an associative array of +`options` and values. Section names are inclosed in square brackets ``[...]`` +and allow simple strings as names. A section name is case-sensitive. It is +followed by its section content, which consists of option lines. + +One option is stored per line. An option name is a case-sensitive simple string +separated by an equal sign ``=`` from its value. The value is string, starts +after the first non-whitespace character and end before the newline character at +the line end. The content can be of any character string. + +Values containing ``${...}`` and ``%{...}`` are raw values, which need to be +interpolated by the ExtendedConfigParser. See `Value Interpolation`_ and +`Node Interpolation`_ for more details. + +Sections can have a default section called ``DEFAULT``. Options not found in a +normal section are looked up in the default section. If found, the value of the +matching option name is the lookup result. + +.. productionlist:: + Document: `DocumentLine`* + DocumentLine: `SpecialSection` | `Section` | `CommentLine` | `EmptyLine` + CommentLine: "#" `CommentText` `LineBreak` + EmptyLine: `WhiteSpace`* `LineBreak` + SpecialSection: "[" `SimpleString` "]" + : (`OptionLine`)* + Section: "[" `FQSectionName` "]" + : (`OptionLine`)* + OptionLine: `Reference` | `Option` | `UserDefVariable` + Reference: `ReferenceName` `WhiteSpace`* "=" `WhiteSpace`* `Keyword` + Option: `OptionName` `WhiteSpace`* "=" `WhiteSpace`* `OptionValue` + UserDefVariable: `VariableName` `WhiteSpace`* "=" `WhiteSpace`* `VariableValue` + FQSectionName: `Prefix` "." `SectionName` + SectionName: `SectionNamePart` ("." `SectionNamePart`)* + SectionNamePart: `SimpleString` + ReferenceName: `SimpleString` + OptionName: `SimpleString` + VariableName: `SimpleString` + +.. rubric:: Example + +.. code-block:: ini + + [section1] + option1 = value1 + opt2 = val ue $2 + + [section2] + option1 = ${section1:option1} + opt2 = ${option1} + +.. topic:: **foo bar** + + | wichtige hinweise + | 2 leerzeichen + +Nodes +===== + +The database is build of nested associative arrays and generated in-memory from +5 *.ini files. This implies that all section names are required to be unique. +(Section merging is not allowed.) A fully qualified section name has a prefix +and a section name delimited by a dot character. The section name itself can +consist of parts also delimited by dot characters. All nodes with the same +prefix shape a node class. + +.. rubric:: The following table lists all used prefixes: + ++---------------+---------------------------------------------------------------------------------+ +| Prefix | Description | ++===============+=================================================================================+ +| ``INSTALL`` | A installed tool (chain) or program. | ++---------------+---------------------------------------------------------------------------------+ +| ``SOLUTION`` | Registered external solutions / projects. | ++---------------+---------------------------------------------------------------------------------+ +| ``CONFIG`` | Configurable PoC settings. | ++---------------+---------------------------------------------------------------------------------+ +| ``BOARD`` | A node to describe a known board. | ++---------------+---------------------------------------------------------------------------------+ +| ``CONST`` | A node to describe constraint file set for a known board. | ++---------------+---------------------------------------------------------------------------------+ +| ``PoC`` | Nodes to describe PoC's namespace structure. | ++---------------+---------------------------------------------------------------------------------+ +| ``IP`` | A node describing an IP core. | ++---------------+---------------------------------------------------------------------------------+ +| ``TB`` | A node describing testbenches. | ++---------------+---------------------------------------------------------------------------------+ +| ``COCOTB`` | A node describing Cocotb testbenches. | ++---------------+---------------------------------------------------------------------------------+ +| ``CG`` | A node storing Core Generator settings. | ++---------------+---------------------------------------------------------------------------------+ +| ``LSE`` | A node storing settings for LSE based netlist generation. | ++---------------+---------------------------------------------------------------------------------+ +| ``QMAP`` | A node storing settings for Quartus based netlist generation. | ++---------------+---------------------------------------------------------------------------------+ +| ``XST`` | A node storing settings for XST based netlist generation. | ++---------------+---------------------------------------------------------------------------------+ +| ``VIVADO`` | A node storing settings for Vivado based netlist generation. | ++---------------+---------------------------------------------------------------------------------+ +| ``XCI`` | A node storing settings for IP Catalog based netlist generation. | ++---------------+---------------------------------------------------------------------------------+ + +.. rubric:: The database has 3 special sections without prefixes: + ++---------------+------------------------------------------------------------------------------------+ +| Section Name | Description | ++===============+====================================================================================+ +| ``PoC`` | Root node for PoC's namespace hierarchy. | ++---------------+------------------------------------------------------------------------------------+ +| ``BOARDS`` | Lists all known boards. | ++---------------+------------------------------------------------------------------------------------+ +| ``SPECIAL`` | Section with dummy values. This is needed by synthesis and overwritten at runtime. | ++---------------+------------------------------------------------------------------------------------+ + + +.. rubric:: Example section names + +.. code-block:: ini + + [PoC] + [PoC.arith] + [PoC.bus] + [PoC.bus.stream] + [PoC.bus.wb] + +The fully qualified section name ``PoC.bus.stream`` has the prefix ``PoC`` and +the section name ``bus.stream``. The section name has two parts: ``bus`` and +``stream``. The dot delimited section name can be considered a path in a +hierarchical database. The parent node is ``PoC.bus`` and its grandparent is +``PoC``. (Note this is a special section. See the special sections table from +above.) + +Option lines can be of three kinds: + ++---------------------------+-----------------------------------------------------------------+ +| Option Line Kind | Distinguishing Characteristic | ++===========================+=================================================================+ +| **Reference** | The option name is called a (node) reference, if the value\ | +| | of an option is a predefined keyword for the current node\ | +| | class. Because the option's value is a keyword, it can not\ | +| | be an interpolated value. | ++---------------------------+-----------------------------------------------------------------+ +| **Option** | The option uses a defined option name valid for the current\ | +| | node class. The value can be a fixed or interpolated string. | ++---------------------------+-----------------------------------------------------------------+ +| **User Defined Variable** | Otherwise an option line is a user defined variable. It can\ | +| | have fixed or interpolated string values. | ++---------------------------+-----------------------------------------------------------------+ + +.. code-block:: ini + + [PoC] + Name = + Prefix = + arith = Namespace + bus = Namespace + + [PoC.arith] + addw = Entity + prng = Entity + + [PoC.bus] + stream = Namespace + wb = Namespace + Arbiter = Entity + + [PoC.bus.stream] + Buffer = Entity + DeMux = Entity + Mirror = Entity + Mux = Entity + + [PoC.bus.wb] + fifo_adapter = Entity + ocram_adapter = Entity + uart_wrapper = Entity + + + + + +References +========== + + + +:Whatever: this is handy to create new field + + +Options +======== + +Values +====== + +Value Interpolation +=================== + +Node Interpolation +================== + +Root Nodes +========== + +Supported Options +***************** + + +.. NOTE:: + See ``py\config.defaults.ini`` for predefined default values (options) and + predefined variables, which can be used as a shortcut. + +Files in detail +*************** + +config.structure.ini +==================== + +config.entity.ini +================= + +config.boards.ini +================= + +config.private.ini +================== + +User Defined Variables +********************** + + +.. |date| date:: %d.%m.%Y +.. |time| date:: %H:%M + +This document was generated on |date| at |time|. diff --git a/docs/References/Glossary.rst b/docs/References/Glossary.rst deleted file mode 100644 index afc37f7f..00000000 --- a/docs/References/Glossary.rst +++ /dev/null @@ -1,48 +0,0 @@ - -Glossary -######## - -Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. -At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor -sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et -accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet - -.. glossary:: - - cc - Common clock - All ports of a module use the same clock. - - dc - Dependent clock - The clock inputs of a module have a known relation in phase or are - multiples of a shared base clock. - - *flag*-signal - No documentation available. - - FWFT - First-word-fall-through - No documentation available. - - ic - Independent clock - The clock inputs have no known relation and are considdered independent. - Modules with ic interfaces implement clock domain crossing (CDC) circuits. - - OCRAM - On-Chip RAM - OCROM - On-Chip ROM - An On-Chip RAM is a embedded memory block, mostly called BlockRAM, - Dirstributed Memory, ... - - PoC.CSE - Command-Status-Error - A control and monitoring protocol in a layer-based architecture. - - PoC.Stream - A streaming optimized, FIFO-like on-chip protocol. - - PoCRoot - The PoC root directory. - - ProjectRoot - The project's root directory, which hosts PoC. - - *strobe*-signal - No documentation available. - diff --git a/docs/References/index.rst b/docs/References/index.rst index a25607cb..66868e83 100644 --- a/docs/References/index.rst +++ b/docs/References/index.rst @@ -5,13 +5,14 @@ References .. toctree:: :maxdepth: 1 + Interfaces/index + NamingConventions CommandReference + Database WrapperScriptHookFiles + PythonInfrastructure FileFormats/index - Interfaces/index - NamingConventions ListOfDevices ListOfBoards - Glossary KnownIssues Licenses/index diff --git a/docs/References/more.rst b/docs/References/more.rst new file mode 100644 index 00000000..0fea6380 --- /dev/null +++ b/docs/References/more.rst @@ -0,0 +1,14 @@ + +More References +############### + +.. toctree:: + :maxdepth: 1 + + ListOfDevices + ListOfBoards + WrapperScriptHookFiles + FileFormats/index + NamingConventions + KnownIssues + Licenses/index diff --git a/docs/UsingPoC/PrecompilingVendorLibraries.rst b/docs/UsingPoC/PrecompilingVendorLibraries.rst index 1f28f2c8..d5512571 100644 --- a/docs/UsingPoC/PrecompilingVendorLibraries.rst +++ b/docs/UsingPoC/PrecompilingVendorLibraries.rst @@ -4,7 +4,11 @@ Pre-Compiling Vendor Libraries .. contents:: Contents of this Page :local: + :depth: 2 + :backlinks: entry +.. index:: + single: Pre-compilation Overview ******** @@ -22,6 +26,9 @@ are located in ``\tools\precompile\`` and the output is stored in ``\temp\precompiled\\``. +.. index:: + pair: Pre-compilation; Supported Simulators + Supported Simulators ******************** @@ -46,9 +53,15 @@ The current set of pre-compile scripts support these simulators: +------------+------------------------------+--------------+--------------+---------------+--------------------+ +.. index:: + pair: Pre-compilation; Vendor Primitives + FPGA Vendor's Primitive Libraries ********************************* +.. index:: + pair: Pre-compilation; Altera + Altera ====== @@ -118,6 +131,9 @@ On Windows +-----+-----------+-------------------------------+ +.. index:: + pair: Pre-compilation; Lattice + Lattice ======== @@ -186,6 +202,10 @@ On Windows | | -VHDL2008 | Compile only for VHDL-2008 | +-----+-----------+-------------------------------+ + +.. index:: + pair: Pre-compilation; Xilinx ISE + Xilinx ISE ========== @@ -254,6 +274,10 @@ On Windows | | -VHDL2008 | Compile only for VHDL-2008 | +-----+-----------+-------------------------------+ + +.. index:: + pair: Pre-compilation; Xilinx Vivado + Xilinx Vivado ============= @@ -322,9 +346,16 @@ On Windows | | -VHDL2008 | Compile only for VHDL-2008 | +-----+-----------+-------------------------------+ + +.. index:: + pair: Pre-compilation; Third-Party Libraries + Third-Party Libraries ********************* +.. index:: + pair: Pre-compilation; OSVVM + OSVVM ===== @@ -382,13 +413,78 @@ On Windows +-----+-----------+-------------------------------+ +.. index:: + pair: Pre-compilation; UVVM + +UVVM +==== + +On Linux +-------- + +.. code-block:: Bash + + # Example 1 - Compile for all Simulators + ./tools/precompile/compile-uvvm.sh --all + # Example 2 - Compile only for GHDL + ./tools/precompile/compile-uvvm.sh --ghdl + +**List of command line arguments:** + ++------------------+-------------------------------+ +| Common Option | Description | ++=====+============+===============================+ +| -h | --help | Print embedded help page(s) | ++-----+------------+-------------------------------+ +| -c | --clean | Clean-up directories | ++-----+------------+-------------------------------+ +| -a | --all | Compile for all simulators | ++-----+------------+-------------------------------+ +| | --ghdl | Compile for GHDL | ++-----+------------+-------------------------------+ +| | --questa | Compile for QuestaSim | ++-----+------------+-------------------------------+ + + +On Windows +---------- + +.. code-block:: PowerShell + + # Example 1 - Compile for all Simulators + .\tools\precompile\compile-uvvm.ps1 -All + # Example 2 - Compile only for GHDL + .\tools\precompile\compile-uvvm.ps1 -GHDL + +**List of command line arguments:** + ++-----------------+-------------------------------+ +| Common Option | Description | ++=====+===========+===============================+ +| -h | -Help | Print embedded help page(s) | ++-----+-----------+-------------------------------+ +| -c | -Clean | Clean-up directories | ++-----+-----------+-------------------------------+ +| -a | -All | Compile for all simulators | ++-----+-----------+-------------------------------+ +| | -GHDL | Compile for GHDL | ++-----+-----------+-------------------------------+ +| | -Questa | Compile for QuestaSim | ++-----+-----------+-------------------------------+ + + +.. index:: + pair: Pre-compilation; Simulator Adapters + Simulator Adapters ****************** +.. index:: + pair: Pre-compilation; Cocotb + Cocotb ====== - On Linux -------- diff --git a/docs/conf.py b/docs/conf.py index 9241066a..8662d695 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -20,6 +20,8 @@ # add these directories to sys.path here. If the directory is relative to the # documentation root, use os.path.abspath to make it absolute, like shown here. sys.path.insert(0, os.path.abspath('.')) +sys.path.insert(0, os.path.abspath('../py')) + # -- General configuration ------------------------------------------------ @@ -31,20 +33,33 @@ # ones. extensions = [ 'sphinx.ext.autodoc', + 'sphinx.ext.inheritance_diagram', 'sphinx.ext.intersphinx', 'sphinx.ext.todo', - 'sphinx.ext.coverage', + # 'sphinx.ext.coverage', 'sphinx.ext.mathjax', 'sphinx.ext.ifconfig', 'sphinx.ext.viewcode', # 'sphinx.ext.githubpages', 'sphinxcontrib.autoprogram', + 'autoapi.sphinx', 'poc' ] if (not (tags.has('PoCExternal') or tags.has('PoCInternal'))): tags.add('PoCExternal') +# Extract Python documentation and generate ReST files. +autoapi_modules = { + 'PoC': {'output': 'PyInfrastructure'}, + 'Base': {'output': 'PyInfrastructure'}, + 'Compiler': {'output': 'PyInfrastructure'}, + 'DataBase': {'output': 'PyInfrastructure'}, + 'Parser': {'output': 'PyInfrastructure'}, + 'Simulator': {'output': 'PyInfrastructure'}, + 'ToolChains': {'output': 'PyInfrastructure'}, + 'lib': {'output': 'PyInfrastructure'} +} # Add any paths that contain templates here, relative to this directory. templates_path = ['_templates', '_themes'] @@ -70,9 +85,9 @@ # built documents. # # The short X.Y version. -version = '1.0' +version = '1.1' # The full version, including alpha/beta/rc tags. -release = '1.0.0' +release = '1.1.0' # The language for content autogenerated by Sphinx. Refer to documentation # for a list of supported languages. @@ -314,4 +329,6 @@ # Example configuration for intersphinx: refer to the Python standard library. -intersphinx_mapping = {'https://docs.python.org/2/': None} +intersphinx_mapping = { + 'python': ('http://docs.python.org/3.5/', None) +} diff --git a/docs/genindex.rst b/docs/genindex.rst new file mode 100644 index 00000000..7c6a7dd4 --- /dev/null +++ b/docs/genindex.rst @@ -0,0 +1,3 @@ + +Index +##### diff --git a/docs/index.rst b/docs/index.rst index c4978f7c..9aa83841 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -81,17 +81,37 @@ following `biblatex `_ entry to cite us: urldate={2016-10-28}, } - .. toctree:: + :caption: Introduction :hidden: WhatIsPoC/index QuickStart UsingPoC/index - PoC/index + GetInvolved/index + References/Licenses/License + +.. toctree:: + :caption: Main Documentation + :hidden: + + Interfaces/index + IPCores/index Miscelaneous/ThirdParty ConstraintFiles/index - References/index - GetInvolved/index + +.. toctree:: + :caption: References + :hidden: + + References/CommandReference + References/Database + PyInfrastructure/index + More ... + +.. toctree:: + :caption: Appendix + :hidden: + Miscelaneous/ChangeLog - References/Licenses/License + genindex diff --git a/docs/poc.py b/docs/poc.py index 84f447cd..e02adf07 100644 --- a/docs/poc.py +++ b/docs/poc.py @@ -57,7 +57,7 @@ def __init__(self, entitySourceCodeRange): #, entityName, entitySourceCodeRan class Extract: def __init__(self): self.sourceDirectory = Path("../src") - self.outputDirectory = Path("PoC") + self.outputDirectory = Path("IPCores") self.relSourceDirectory = Path("../../src") self.templateFile = Path("Entity.template") diff --git a/lib/OSVVM.files b/lib/OSVVM.files index 358a4529..6e398a8e 100644 --- a/lib/OSVVM.files +++ b/lib/OSVVM.files @@ -22,7 +22,7 @@ elseif (VHDLVersion = 2008) then if ?{OSVVM_LibraryPath} then library osvvm OSVVM_LibraryPath else - report "No precompiled QuestaSim/ModelSim library for GHDL found." + report "No precompiled OSVVM library for QuestaSim/ModelSim found." end if else # TODO self-compile section? diff --git a/py/Base/Compiler.py b/py/Base/Compiler.py index c9a70ced..65d06794 100644 --- a/py/Base/Compiler.py +++ b/py/Base/Compiler.py @@ -32,20 +32,11 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Class PoCCompiler") - - # load dependencies -import re -import shutil from enum import Enum, unique from pathlib import Path +from re import compile as re_compile, subn as re_subn, DOTALL as RE_DOTALL, MULTILINE as RE_MULTILINE, IGNORECASE as RE_IGNORECASE +from shutil import copy as shutil_copy from lib.Functions import Init from lib.Parser import ParserException @@ -53,31 +44,54 @@ from Base.Project import VHDLVersion, Environment, FileTypes from Base.Shared import Shared, to_time from Parser.RulesParser import CopyRuleMixIn, ReplaceRuleMixIn, DeleteRuleMixIn, AppendLineRuleMixIn -from DataBase.Solution import RulesFile -from DataBase.TestCase import SynthesisSuite, Synthesis, CompileStatus +from DataBase.Solution import RulesFile +from DataBase.TestCase import SynthesisSuite, Synthesis, CompileStatus + + +# required for autoapi.sphinx +__api__ = [ + 'CompilerException', + 'SkipableCompilerException', + 'CopyTask', + 'DeleteTask', + 'ReplaceTask', + 'AppendLineTask', + 'CompileState', + 'CompileResult', + 'Compiler' +] +__all__ = __api__ class CompilerException(ExceptionBase): + """Base exception for all CompilerExceptions.""" pass class SkipableCompilerException(CompilerException, SkipableException): + """Base class for all skipable CompilerException.""" pass class CopyTask(CopyRuleMixIn): + """This class represents a 'copy task' and inherits the partial class :ref:`CopyRuleMixIn`.""" pass class DeleteTask(DeleteRuleMixIn): + """This class represents a 'delete task' and inherits the partial class :ref:`DeleteRuleMixIn`.""" pass class ReplaceTask(ReplaceRuleMixIn): + """This class represents a 'replace task' and inherits the partial class :ref:`ReplaceRuleMixIn`.""" pass class AppendLineTask(AppendLineRuleMixIn): + """This class represents a 'append line task' and inherits the partial class :ref:`AppendLineRuleMixIn`.""" pass @unique class CompileState(Enum): + """Compile state enumeration.""" + Prepare = 0 PreCopy = 10 PrePatch = 11 @@ -98,6 +112,8 @@ class CompileState(Enum): @unique class CompileResult(Enum): + """Compilation result enumeration.""" + NotRun = 0 Error = 1 Failed = 2 @@ -105,6 +121,17 @@ class CompileResult(Enum): class Compiler(Shared): + """ + Base class for all Compiler classes. + + :param host: The hosting instance for this instance. + :type host: object + :param dryRun: Enable dry-run mode + :type dryRun: bool + :param noCleanUp: Don't clean up after a run. + :type noCleanUp: bool + """ + _ENVIRONMENT = Environment.Synthesis _vhdlVersion = VHDLVersion.VHDL93 @@ -114,6 +141,7 @@ class __Directories__(Shared.__Directories__): Destination = None def __init__(self, host, dryRun, noCleanUp): + """Constructur""" super().__init__(host, dryRun) self._noCleanUp = noCleanUp @@ -128,10 +156,12 @@ def __init__(self, host, dryRun, noCleanUp): def NoCleanUp(self): return self._noCleanUp def _PrepareCompiler(self): + """Prepare for compilation. This method forwards to :py:meth:`Base.Compiler.Compiler._Prepare`, which is un herited from:py:class:`Base.Shared.Shared`.""" self._Prepare() def TryRun(self, netlist, *args, **kwargs): """Try to run a testbench. Skip skipable exceptions by printing the error and its cause.""" + __COMPILE_STATE_TO_SYNTHESIS_STATUS__ = { CompileState.Prepare: CompileStatus.InternalError, CompileState.PreCopy: CompileStatus.SystemError, @@ -170,6 +200,8 @@ def TryRun(self, netlist, *args, **kwargs): synthesis.StopTimer() def Run(self, netlist, board): + """Run a testbench.""" + self.LogQuiet("{CYAN}IP core: {0!s}{NOCOLOR}".format(netlist.Parent, **Init.Foreground)) # # TODO: refactor # self.LogNormal("Checking for dependencies:") @@ -271,7 +303,7 @@ def _ParseCopyRules(self, rawList, copyTasks, text): copyRegExpStr = r"^\s*(?P.*?)" # Source filename copyRegExpStr += r"\s->\s" # Delimiter signs copyRegExpStr += r"(?P.*?)$" # Destination filename - copyRegExp = re.compile(copyRegExpStr) + copyRegExp = re_compile(copyRegExpStr) for item in rawList: preCopyRegExpMatch = copyRegExp.match(item) @@ -306,7 +338,7 @@ def _ExecuteCopyTasks(self, tasks, text): self.LogDryRun("Copy '{0!s}' to '{1!s}'.".format(task.SourcePath, task.DestinationPath)) else: try: - shutil.copy(str(task.SourcePath), str(task.DestinationPath)) + shutil_copy(str(task.SourcePath), str(task.DestinationPath)) except OSError as ex: raise CompilerException("Error while copying '{0!s}'.".format(task.SourcePath)) from ex @@ -338,7 +370,7 @@ def _ParseDeleteRules(self, rawList, deleteTasks, text): rawList = rawList.split("\n") deleteRegExpStr = r"^\s*(?P.*?)$" # filename - deleteRegExp = re.compile(deleteRegExpStr) + deleteRegExp = re_compile(deleteRegExpStr) for item in rawList: deleteRegExpMatch = deleteRegExp.match(item) @@ -436,7 +468,7 @@ def _ParseReplaceRules(self, rawList, replaceTasks, text): replaceRegExpStr += r"(?P[dim]{0,3}):\s+" # RegExp options replaceRegExpStr += r"\"(?P.*?)\"\s+->\s+" # Search regexp replaceRegExpStr += r"\"(?P.*?)\"$" # Replace regexp - replaceRegExp = re.compile(replaceRegExpStr) + replaceRegExp = re_compile(replaceRegExpStr) for item in rawList: replaceRegExpMatch = replaceRegExp.match(item) @@ -468,17 +500,17 @@ def _ExecuteReplaceTasks(self, tasks, text): self.LogDryRun("Patch '{0!s}'.".format(task.FilePath)) else: regExpFlags = 0 - if task.RegExpOption_CaseInsensitive: regExpFlags |= re.IGNORECASE - if task.RegExpOption_MultiLine: regExpFlags |= re.MULTILINE - if task.RegExpOption_DotAll: regExpFlags |= re.DOTALL + if task.RegExpOption_CaseInsensitive: regExpFlags |= RE_IGNORECASE + if task.RegExpOption_MultiLine: regExpFlags |= RE_MULTILINE + if task.RegExpOption_DotAll: regExpFlags |= RE_DOTALL # compile regexp - regExp = re.compile(task.SearchPattern, regExpFlags) + regExp = re_compile(task.SearchPattern, regExpFlags) # open file and read all lines with task.FilePath.open('r') as fileHandle: FileContent = fileHandle.read() # replace - NewContent,replaceCount = re.subn(regExp, task.ReplacePattern, FileContent) + NewContent,replaceCount = re_subn(regExp, task.ReplacePattern, FileContent) if (replaceCount == 0): self.LogWarning(" Search pattern '{0}' not found in file '{1!s}'.".format(task.SearchPattern, task.FilePath)) # open file to write the replaced data diff --git a/py/Base/Configuration.py b/py/Base/Configuration.py index 8298d01b..a05dc9f2 100644 --- a/py/Base/Configuration.py +++ b/py/Base/Configuration.py @@ -30,21 +30,21 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module Base.Configuration") - - +# load dependencies from collections import OrderedDict from pathlib import Path from Base.Exceptions import ExceptionBase +__api__ = [ + 'ConfigurationException', + 'SkipConfigurationException', + 'Configuration' +] +__all__ = __api__ + + class ConfigurationException(ExceptionBase): pass diff --git a/py/Base/Exceptions.py b/py/Base/Exceptions.py index bc0dc08b..1a1d8bef 100644 --- a/py/Base/Exceptions.py +++ b/py/Base/Exceptions.py @@ -30,14 +30,17 @@ # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================== - -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module Base.Exceptions") +# +__api__ = [ + 'ExceptionBase', + 'EnvironmentException', + 'PlatformNotSupportedException', + 'NotConfiguredException', + 'SkipableException', + 'CommonException', + 'SkipableCommonException' +] +__all__ = __api__ class ExceptionBase(Exception): diff --git a/py/Base/Executable.py b/py/Base/Executable.py index 6f98a120..7311aa70 100644 --- a/py/Base/Executable.py +++ b/py/Base/Executable.py @@ -31,14 +31,6 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module Base.Executable") - # load dependencies from pathlib import Path from subprocess import Popen as Subprocess_Popen @@ -49,6 +41,25 @@ from Base.Logging import ILogable +__api__ = [ + 'ExecutableException', + 'CommandLineArgument', + 'ExecutableArgument', + 'NamedCommandLineArgument', + 'CommandArgument', 'ShortCommandArgument', 'LongCommandArgument', 'WindowsCommandArgument', + 'StringArgument', + 'StringListArgument', + 'PathArgument', + 'FlagArgument', 'ShortFlagArgument', 'LongFlagArgument', 'WindowsFlagArgument', + 'ValuedFlagArgument', 'ShortValuedFlagArgument', 'LongValuedFlagArgument', + 'ValuedFlagListArgument', 'ShortValuedFlagListArgument', 'LongValuedFlagListArgument', + 'TupleArgument', 'ShortTupleArgument', 'LongTupleArgument', + 'CommandLineArgumentList', + 'Executable' +] +__all__ = __api__ + + class ExecutableException(BaseException): def __init__(self, message=""): super().__init__(message) diff --git a/py/Base/Logging.py b/py/Base/Logging.py index 82c5e0c8..4d41b6b2 100644 --- a/py/Base/Logging.py +++ b/py/Base/Logging.py @@ -32,20 +32,21 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module Base.PoCBase") - - +# load dependencies from enum import Enum, unique from lib.Functions import Init +__api__ = [ + 'Severity', + 'LogEntry', + 'Logger', + 'ILogable' +] +__all__ = __api__ + + @unique class Severity(Enum): Fatal = 30 diff --git a/py/Base/Project.py b/py/Base/Project.py index f1dc3752..e2ce7d23 100644 --- a/py/Base/Project.py +++ b/py/Base/Project.py @@ -41,6 +41,19 @@ from DataBase.Config import Board, Device +__api__ = [ + 'FileTypes', + 'Environment', 'ToolChain', 'Tool', 'VHDLVersion', + 'Project', + 'FileSet', + 'VHDLLibrary', + 'File', + 'ProjectFile', 'ConstraintFile', 'SettingsFile', 'SourceFile', + 'VHDLSourceFile', 'VerilogSourceFile', 'PythonSourceFile', 'CocotbSourceFile' +] +__all__ = __api__ + + # TODO: nested filesets class FileTypes(Flags): diff --git a/py/Base/Shared.py b/py/Base/Shared.py index c40e8688..c56d6081 100644 --- a/py/Base/Shared.py +++ b/py/Base/Shared.py @@ -31,15 +31,6 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Class PoCCompiler") - - # load dependencies import shutil from datetime import datetime @@ -52,6 +43,13 @@ from DataBase.Solution import VirtualProject, FileListFile +__api__ = [ + 'to_time', + 'Shared' +] +__all__ = __api__ + + # local helper function def to_time(seconds): """Convert n seconds to a str with pattern {min}:{sec:02}.""" diff --git a/py/Base/Simulator.py b/py/Base/Simulator.py index 3ca939a3..3fc38dbf 100644 --- a/py/Base/Simulator.py +++ b/py/Base/Simulator.py @@ -32,15 +32,6 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - pass - # place library initialization code here -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module Simulator.Base") - - # load dependencies from datetime import datetime from enum import Enum, unique @@ -54,21 +45,38 @@ from DataBase.TestCase import TestCase, SimulationStatus, TestSuite +# required for autoapi.sphinx +__api__ = [ + 'SimulatorException', + 'SkipableSimulatorException', + 'PoCSimulationResultNotFoundException', + 'SimulationState', + 'SimulationResult', + 'Simulator', + 'PoCSimulationResultFilter' +] +__all__ = __api__ + + VHDL_TESTBENCH_LIBRARY_NAME = "test" class SimulatorException(ExceptionBase): + """Base class for all SimulatorExceptions.""" pass class SkipableSimulatorException(SimulatorException, SkipableException): + """Base class for all skipable SimulatorExceptions.""" pass class PoCSimulationResultNotFoundException(SkipableSimulatorException): + """This exception is raised if the expected PoC simulation result string was not found in the simulator's output.""" pass @unique class SimulationState(Enum): + """Simulation state enumeration.""" Prepare = 0 Analyze = 1 Elaborate = 2 @@ -78,6 +86,7 @@ class SimulationState(Enum): @unique class SimulationResult(Enum): + """Simulation result enumeration.""" NotRun = 0 Error = 1 Failed = 2 @@ -87,15 +96,18 @@ class SimulationResult(Enum): class Simulator(Shared): + """Base class for all Simulator classes.""" + _ENVIRONMENT = Environment.Simulation _vhdlVersion = VHDLVersion.VHDL2008 class __Directories__(Shared.__Directories__): PreCompiled = None - def __init__(self, host, dryRun): + def __init__(self, host, dryRun, guiMode): super().__init__(host, dryRun) + self._guiMode = guiMode self._testSuite = TestSuite() # TODO: This includes not the read ini files phases ... self._state = SimulationState.Prepare self._analyzeTime = None @@ -202,7 +214,7 @@ def Run(self, testbench, board, vhdlVersion, vhdlGenerics=None, guiMode=False): self._RunSimulation(testbench) self._simulationTime = self._GetTimeDeltaSinceLastEvent() - if (guiMode is True): + if (self._guiMode is True): self.LogNormal("Executing waveform viewer...") self._state = SimulationState.View self._RunView(testbench) diff --git a/py/Base/ToolChain.py b/py/Base/ToolChain.py index 29975f63..214de0aa 100644 --- a/py/Base/ToolChain.py +++ b/py/Base/ToolChain.py @@ -31,18 +31,16 @@ # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================== +# +# load dependencies +from Base.Exceptions import ExceptionBase -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Class PoCCompiler") +__api__ = [ + 'ToolChainException' +] +__all__ = __api__ -# load dependencies -from Base.Exceptions import ExceptionBase class ToolChainException(ExceptionBase): pass diff --git a/py/Base/__init__.py b/py/Base/__init__.py index c461076d..793b2851 100644 --- a/py/Base/__init__.py +++ b/py/Base/__init__.py @@ -29,13 +29,4 @@ # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================== - -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Repository Service Tool") - -# load dependencies +# diff --git a/py/Compiler/ISECompiler.py b/py/Compiler/ISECompiler.py index 84891d16..33d12e5d 100644 --- a/py/Compiler/ISECompiler.py +++ b/py/Compiler/ISECompiler.py @@ -31,15 +31,6 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module Compiler.XCOCompiler") - - # load dependencies from Base.Project import ToolChain, Tool from Base.Compiler import Compiler as BaseCompiler @@ -48,6 +39,11 @@ from Compiler.XSTCompiler import Compiler as XSTCompiler +__api__ = [ + 'Compiler' +] +__all__ = __api__ + class Compiler(BaseCompiler): _TOOL_CHAIN = ToolChain.Xilinx_ISE _TOOL = Tool.Any diff --git a/py/Compiler/LSECompiler.py b/py/Compiler/LSECompiler.py index 246bb15c..ee8ad2e9 100644 --- a/py/Compiler/LSECompiler.py +++ b/py/Compiler/LSECompiler.py @@ -32,15 +32,6 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module Compiler.XSTCompiler") - - # load dependencies from datetime import datetime from pathlib import Path @@ -53,6 +44,12 @@ from ToolChains.Lattice.Diamond import Diamond, SynthesisArgumentFile +__api__ = [ + 'Compiler' +] +__all__ = __api__ + + class Compiler(BaseCompiler): _TOOL_CHAIN = ToolChain.Lattice_Diamond _TOOL = Tool.Lattice_LSE diff --git a/py/Compiler/QuartusCompiler.py b/py/Compiler/QuartusCompiler.py index 9ea22590..87f8f9ab 100644 --- a/py/Compiler/QuartusCompiler.py +++ b/py/Compiler/QuartusCompiler.py @@ -32,15 +32,6 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module Compiler.XSTCompiler") - - # load dependencies from datetime import datetime from pathlib import Path @@ -51,6 +42,12 @@ from ToolChains.Altera.Quartus import QuartusException, Quartus, QuartusSettings, QuartusProjectFile +__api__ = [ + 'Compiler' +] +__all__ = __api__ + + class Compiler(BaseCompiler): _TOOL_CHAIN = ToolChain.Altera_Quartus _TOOL = Tool.Altera_Quartus_Map diff --git a/py/Compiler/VivadoCompiler.py b/py/Compiler/VivadoCompiler.py index f6728725..3c53ce67 100644 --- a/py/Compiler/VivadoCompiler.py +++ b/py/Compiler/VivadoCompiler.py @@ -31,17 +31,6 @@ # limitations under the License. # ============================================================================== # -# entry point - - -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module Compiler.XSTCompiler") - - # load dependencies from datetime import datetime from pathlib import Path @@ -52,6 +41,12 @@ from ToolChains.Xilinx.Vivado import Vivado, VivadoException +__api__ = [ + 'Compiler' +] +__all__ = __api__ + + class Compiler(BaseCompiler): _TOOL_CHAIN = ToolChain.Xilinx_Vivado _TOOL = Tool.Xilinx_Synth diff --git a/py/Compiler/XCICompiler.py b/py/Compiler/XCICompiler.py index 57fcf9d6..f318ee65 100644 --- a/py/Compiler/XCICompiler.py +++ b/py/Compiler/XCICompiler.py @@ -31,15 +31,6 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module Compiler.XCICompiler") - - # load dependencies import shutil from datetime import datetime @@ -53,6 +44,12 @@ from ToolChains.Xilinx.Vivado import Vivado, VivadoException +__api__ = [ + 'Compiler' +] +__all__ = __api__ + + class Compiler(BaseCompiler): _TOOL_CHAIN = ToolChain.Xilinx_Vivado _TOOL = Tool.Xilinx_IPCatalog diff --git a/py/Compiler/XCOCompiler.py b/py/Compiler/XCOCompiler.py index 7c9c5be3..6c99253a 100644 --- a/py/Compiler/XCOCompiler.py +++ b/py/Compiler/XCOCompiler.py @@ -32,15 +32,6 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module Compiler.XCOCompiler") - - # load dependencies import shutil from datetime import datetime @@ -54,6 +45,12 @@ from ToolChains.Xilinx.ISE import ISE, ISEException +__api__ = [ + 'Compiler' +] +__all__ = __api__ + + class Compiler(BaseCompiler): _TOOL_CHAIN = ToolChain.Xilinx_ISE _TOOL = Tool.Xilinx_CoreGen diff --git a/py/Compiler/XSTCompiler.py b/py/Compiler/XSTCompiler.py index 4bc4f9af..70debbb8 100644 --- a/py/Compiler/XSTCompiler.py +++ b/py/Compiler/XSTCompiler.py @@ -32,15 +32,6 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module Compiler.XSTCompiler") - - # load dependencies from datetime import datetime from pathlib import Path @@ -52,6 +43,12 @@ from ToolChains.Xilinx.ISE import ISE, ISEException +__api__ = [ + 'Compiler' +] +__all__ = __api__ + + class Compiler(BaseCompiler, XilinxProjectExportMixIn): _TOOL_CHAIN = ToolChain.Xilinx_ISE _TOOL = Tool.Xilinx_XST diff --git a/py/Compiler/__init__.py b/py/Compiler/__init__.py index 8a2a1fb4..02303ff5 100644 --- a/py/Compiler/__init__.py +++ b/py/Compiler/__init__.py @@ -30,12 +30,3 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Repository Service Tool") - -# load dependencies diff --git a/py/DataBase/Config.py b/py/DataBase/Config.py index aaf5c6a5..511326ce 100644 --- a/py/DataBase/Config.py +++ b/py/DataBase/Config.py @@ -30,22 +30,26 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module PoC.Config") - - # load dependencies from enum import Enum, unique -from re import compile as RegExpCompile +from re import compile as re_compile from Base.Configuration import ConfigurationException +__api__ = [ + 'BaseEnum', + 'Vendors', + 'Families', 'GenericFamilies', 'XilinxFamilies', 'AlteraFamilies', 'LatticeFamilies', + 'Devices', + 'SubTypes', + 'Packages', + 'Device', + 'Board' +] +__all__ = __api__ + + class BaseEnum(Enum): def __str__(self): return self.name @@ -270,7 +274,7 @@ def _DecodeAltera(self, deviceString): deviceRegExpStr = r"(?P\d{1,2})" # generation deviceRegExpStr += r"(?P[acms])" # family deviceRegExpStr += r"(?P(ls|e|g|x|t|gs|gx|gt|gz|sx|st)?)" # subtype - deviceRegExp = RegExpCompile(deviceRegExpStr) + deviceRegExp = re_compile(deviceRegExpStr) deviceRegExpMatch = deviceRegExp.match(deviceString[2:].lower()) if (deviceRegExpMatch is not None): @@ -351,7 +355,7 @@ def _DecodeXilinx(self, deviceString): deviceRegExpStr += r"(?P[-1-5]{2})" # speed grade deviceRegExpStr += r"(?P[a-z]{1,3})" # package deviceRegExpStr += r"(?P\d{1,4})" # pin count - deviceRegExp = RegExpCompile(deviceRegExpStr) + deviceRegExp = re_compile(deviceRegExpStr) deviceRegExpMatch = deviceRegExp.match(deviceString[4:].lower()) if (deviceRegExpMatch is not None): @@ -513,6 +517,7 @@ def GetVariables(self): def __str__(self): return self.FullName + class Board: def __init__(self, host, boardName=None, device=None): # Board members diff --git a/py/DataBase/Entity.py b/py/DataBase/Entity.py index 29048b29..000e3212 100644 --- a/py/DataBase/Entity.py +++ b/py/DataBase/Entity.py @@ -30,16 +30,7 @@ # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================== - -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module PoC.Entity") - - +# # load dependencies from collections import OrderedDict from enum import Enum, unique @@ -51,6 +42,26 @@ from Base.Configuration import ConfigurationException +__api__ = [ + 'EntityTypes', + '_PoCEntityTypes_parser', + 'BaseFlags', + 'TestbenchKind', 'NetlistKind', + 'NamespaceRoot', + 'Visibility', + 'PathElement', + 'Namespace', + 'Library', + 'WildCard', 'StarWildCard', 'AskWildCard', + 'IPCore', + 'LazyPathElement', + 'Testbench', 'VHDLTestbench', 'CocoTestbench', + 'Netlist', 'XstNetlist', 'QuartusNetlist', 'LatticeNetlist', 'CoreGeneratorNetlist', 'VivadoNetlist', + 'FQN' +] +__all__ = __api__ + + @unique class EntityTypes(Enum): Unknown = 0 @@ -80,7 +91,7 @@ def _PoCEntityTypes_parser(cls, value): class BaseFlags(Flags): - __no_flags_name__ = "Unknown" + __no_flags_name__ = "Unknown" __all_flags_name__ = "All" diff --git a/py/DataBase/Query.py b/py/DataBase/Query.py index 17b8e707..511c8b30 100644 --- a/py/DataBase/Query.py +++ b/py/DataBase/Query.py @@ -29,21 +29,20 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module PoC.Query") - - +# +# load dependencies from pathlib import Path from Base.Exceptions import NotConfiguredException, PlatformNotSupportedException from Base.Configuration import ConfigurationException +__api__ = [ + 'Query' +] +__all__ = __api__ + + class Query: def __init__(self, host): self.__host = host diff --git a/py/DataBase/Solution.py b/py/DataBase/Solution.py index 5cacf1b3..a713da1b 100644 --- a/py/DataBase/Solution.py +++ b/py/DataBase/Solution.py @@ -30,16 +30,7 @@ # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================== - -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module PoC.Project") - - +# # load dependencies from collections import OrderedDict from textwrap import dedent @@ -54,6 +45,15 @@ from DataBase.Entity import Visibility +__api__ = [ + 'Base', + 'Repository', 'Solution', 'Project', + 'ISEProject', 'VivadoProject', 'QuartusProject', 'LatticeProject', 'VirtualProject', + 'FileListFile', 'RulesFile' +] +__all__ = __api__ + + class Base(ILazyLoadable): """ Base class for Repository, Solution and Project. diff --git a/py/DataBase/TestCase.py b/py/DataBase/TestCase.py index c49044c1..a10c53bd 100644 --- a/py/DataBase/TestCase.py +++ b/py/DataBase/TestCase.py @@ -29,20 +29,23 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module PoC.Query") - - +# +# load dependencies from collections import OrderedDict from datetime import datetime from enum import Enum, unique +__api__ = [ + 'SimulationStatus', 'CompileStatus', + 'ElementBase', + 'GroupBase', 'TestGroup', 'SynthesisGroup', + 'SuiteMixIn', 'TestSuite', 'SynthesisSuite', + 'TestBase', 'TestCase', 'Synthesis' +] +__all__ = __api__ + + @unique class SimulationStatus(Enum): Unknown = 0 diff --git a/py/Parser/FilesCodeDOM.py b/py/Parser/FilesCodeDOM.py index 2d79e99e..5a032387 100644 --- a/py/Parser/FilesCodeDOM.py +++ b/py/Parser/FilesCodeDOM.py @@ -30,6 +30,7 @@ # limitations under the License. # ============================================================================== # +# load dependencies from lib.Parser import MismatchingParserResult, MatchingParserResult, GreedyMatchingParserResult, StartOfDocumentToken from lib.Parser import SpaceToken, CharacterToken, StringToken, NumberToken from lib.CodeDOM import AndExpression, OrExpression, XorExpression, NotExpression, InExpression, NotInExpression, Literal, BinaryExpression @@ -38,6 +39,28 @@ from lib.CodeDOM import Statement, BlockStatement, ConditionalBlockStatement, Function, Expression, ListElement from lib.CodeDOM import StringLiteral, IntegerLiteral, Identifier + +__api__ = [ + 'BlockedStatement', + 'IfThenElseExpressions', 'ListElementExpressions', 'PathExpressions', + 'ListConstructorExpression', + 'SubDirectoryExpression', + 'ConcatenateExpression', + 'ExistsFunction', + 'VHDLStatement', 'VerilogStatement', 'CocotbStatement', + 'ConstraintStatement', + 'LDCStatement', 'SDCStatement', 'UCFStatement', 'XDCStatement', + 'InterpolateLiteral', + 'PathStatement', + 'ReportStatement', + 'LibraryStatement', + 'IncludeStatement', + 'IfStatement', 'ElseIfStatement', 'ElseStatement', 'IfElseIfElseStatement', + 'Document' +] +__all__ = __api__ + + DEBUG = False#True # ============================================================================== diff --git a/py/Parser/FilesParser.py b/py/Parser/FilesParser.py index 0720a8b2..97d4f789 100644 --- a/py/Parser/FilesParser.py +++ b/py/Parser/FilesParser.py @@ -30,6 +30,7 @@ # limitations under the License. # ============================================================================== # +# load dependencies from lib.Functions import Init from lib.Parser import ParserException from lib.CodeDOM import AndExpression, OrExpression, XorExpression, NotExpression, InExpression, NotInExpression @@ -42,6 +43,23 @@ from Parser.FilesCodeDOM import LDCStatement, SDCStatement, UCFStatement, XDCStatement from Parser.FilesCodeDOM import VHDLStatement, VerilogStatement, CocotbStatement + +__api__ = [ + 'FileReference', + 'IncludeFileMixIn', + 'VHDLSourceFileMixIn', + 'VerilogSourceFileMixIn', + 'CocotbSourceFileMixIn', + 'LDCSourceFileMixIn', + 'SDCSourceFileMixIn', + 'UCFSourceFileMixIn', + 'XDCSourceFileMixIn', + 'VHDLLibraryReference', + 'FilesParserMixIn' +] +__all__ = __api__ + + # to print the reconstructed files file after parsing, set DEBUG to True DEBUG = not True diff --git a/py/Parser/RulesCodeDOM.py b/py/Parser/RulesCodeDOM.py index 8e04212f..afdd14e8 100644 --- a/py/Parser/RulesCodeDOM.py +++ b/py/Parser/RulesCodeDOM.py @@ -29,12 +29,30 @@ # limitations under the License. # ============================================================================== # +# load dependencies from lib.Parser import MismatchingParserResult, MatchingParserResult, EmptyChoiseParserResult, StartOfDocumentToken from lib.Parser import SpaceToken, CharacterToken, StringToken from lib.CodeDOM import EmptyLine, CommentLine, BlockedStatement as BlockStatementBase, StringLiteral from lib.CodeDOM import Statement, BlockStatement +__api__ = [ + 'InFileStatements', + 'PreProcessStatements', + 'PostProcessStatements', + 'DocumentStatements', + 'CopyStatement', + 'DeleteStatement', + 'ReplaceStatement', + 'AppendLineStatement', + 'FileStatement', + 'ProcessRulesBlockStatement', + 'PreProcessRulesStatement', + 'PostProcessRulesStatement', + 'Document' +] +__all__ = __api__ + # ============================================================================== # Blocked Statements (Forward declaration) # ============================================================================== diff --git a/py/Parser/RulesParser.py b/py/Parser/RulesParser.py index 9214976d..557513ec 100644 --- a/py/Parser/RulesParser.py +++ b/py/Parser/RulesParser.py @@ -30,15 +30,27 @@ # ============================================================================== # from lib.Parser import ParserException -from Parser.RulesCodeDOM import Document, PreProcessRulesStatement, PostProcessRulesStatement, CopyStatement, ReplaceStatement, FileStatement, DeleteStatement, \ - AppendLineStatement +from Parser.RulesCodeDOM import Document, PreProcessRulesStatement, PostProcessRulesStatement, CopyStatement, ReplaceStatement, FileStatement, DeleteStatement, AppendLineStatement + + +__api__ = [ + 'Rule', + 'CopyRuleMixIn', + 'DeleteRuleMixIn', + 'ReplaceRuleMixIn', + 'AppendLineRuleMixIn', + 'RulesParserMixIn' +] +__all__ = __api__ class Rule: - pass + """Base class for all Rule and RuleMixIn classes.""" class CopyRuleMixIn(Rule): + """A partial class (MixIn) to represent a 'copy rule'.""" + def __init__(self, sourcePath, destinationPath): self._source = sourcePath self._destination = destinationPath @@ -53,6 +65,8 @@ def __str__(self): class DeleteRuleMixIn(Rule): + """A partial class (MixIn) to represent a 'delete rule'.""" + def __init__(self, filePath): self._source = filePath @@ -64,6 +78,8 @@ def __str__(self): class ReplaceRuleMixIn(Rule): + """A partial class (MixIn) to represent a 'replace rule'.""" + def __init__(self, filePath, searchPattern, replacePattern, multiLine, dotAll, caseInSensitive): self._filePath = filePath self._searchPattern = searchPattern @@ -89,6 +105,8 @@ def __str__(self): return "Replace rule: in '{0!s}' replace '{1}' with '{2}'".format(self._filePath, self._searchPattern, self._replacePattern) class AppendLineRuleMixIn(Rule): + """A partial class (MixIn) to represent a 'append line rule'.""" + def __init__(self, filePath, appendPattern): self._filePath = filePath self._appendPattern = appendPattern diff --git a/py/PoC.py b/py/PoC.py index ab5b8eff..f18330d8 100644 --- a/py/PoC.py +++ b/py/PoC.py @@ -33,6 +33,7 @@ # limitations under the License. # ============================================================================== # +# load dependencies from argparse import RawDescriptionHelpFormatter from collections import OrderedDict from configparser import Error as ConfigParser_Error, DuplicateOptionError @@ -85,6 +86,18 @@ __status__ = "Production" __license__ = "Apache License 2.0" +__api__ = [ + 'PoCEntityAttribute', + 'BoardDeviceAttributeGroup', + 'VHDLVersionAttribute', + 'GUIModeAttribute', + 'NoCleanUpAttribute', + 'PoC', + 'main' +] +__all__ = __api__ + + class PoCEntityAttribute(Attribute): def __call__(self, func): @@ -112,6 +125,7 @@ def __call__(self, func): self._AppendAttribute(func, SwitchArgumentAttribute("--no-cleanup", dest="NoCleanUp", help="Don't delete intermediate files. Skip post-delete rules.")) return func + class PoC(ILogable, ArgParseMixin): HeadLine = "The PoC-Library - Service Tool" @@ -805,6 +819,7 @@ def HandleActiveHDLSimulation(self, args): @BoardDeviceAttributeGroup() @VHDLVersionAttribute() @GUIModeAttribute() + @ArgumentAttribute("--reproducer", metavar="Name", dest="CreateReproducer", help="Create a bug reproducer") def HandleGHDLSimulation(self, args): self.PrintHeadline() self.__PrepareForSimulation() @@ -818,7 +833,7 @@ def HandleGHDLSimulation(self, args): vhdlVersion = self._ExtractVHDLVersion(args.VHDLVersion) simulator = GHDLSimulator(self, self.DryRun, args.GUIMode) - allPassed = simulator.RunAll(fqnList, board=board, vhdlVersion=vhdlVersion, guiMode=args.GUIMode) #, vhdlGenerics=None) + allPassed = simulator.RunAll(fqnList, board=board, vhdlVersion=vhdlVersion) #, vhdlGenerics=None) Exit.exit(0 if allPassed else 1) @@ -1114,6 +1129,15 @@ def HandleLSECompilation(self, args): # main program def main(): # mccabe:disable=MC0001 + """ + This is the entry point for PoC.py written as a function. + + 1. It extracts common flags from the script's arguments list, before :py:class:`argparse.ArgumentParser` is fully loaded. + 2. It initializes colorama for colored outputs + 3. It creates an instance of PoC and hands over to class based execution. All is wrapped in a big ``try..except`` block to catch every unhandled exception. + 4. Shutdown the script and return its exit code. + """ + dryRun = "--dryrun" in sys_argv debug = "-d" in sys_argv verbose = "-v" in sys_argv diff --git a/py/Simulator/ActiveHDLSimulator.py b/py/Simulator/ActiveHDLSimulator.py index f5b29ef3..3d78c156 100644 --- a/py/Simulator/ActiveHDLSimulator.py +++ b/py/Simulator/ActiveHDLSimulator.py @@ -30,15 +30,6 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module Simulator.ActiveHDLSimulator") - - # load dependencies from pathlib import Path @@ -48,14 +39,19 @@ from ToolChains.Aldec.ActiveHDL import ActiveHDL, ActiveHDLException +__api__ = [ + 'Simulator' +] +__all__ = __api__ + + class Simulator(BaseSimulator): _TOOL_CHAIN = ToolChain.Aldec_ActiveHDL _TOOL = Tool.Aldec_aSim def __init__(self, host, dryRun, guiMode): - super().__init__(host, dryRun) + super().__init__(host, dryRun, guiMode) - self._guiMode = guiMode self._vhdlVersion = None self._vhdlGenerics = None self._toolChain = None diff --git a/py/Simulator/CocotbSimulator.py b/py/Simulator/CocotbSimulator.py index c7d709eb..8f21a00a 100644 --- a/py/Simulator/CocotbSimulator.py +++ b/py/Simulator/CocotbSimulator.py @@ -32,17 +32,6 @@ # limitations under the License. # ============================================================================== # -# entry point - -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module Simulator.CocotbSimulator") - - # load dependencies import shutil from textwrap import dedent @@ -54,15 +43,19 @@ from ToolChains.GNU import Make +__api__ = [ + 'Simulator' +] +__all__ = __api__ + + class Simulator(BaseSimulator): _TOOL_CHAIN = ToolChain.Cocotb _TOOL = Tool.Cocotb_QuestaSim _COCOTB_SIMBUILD_DIRECTORY = "sim_build" def __init__(self, host, dryRun, guiMode): - super().__init__(host, dryRun) - - self._guiMode = guiMode + super().__init__(host, dryRun, guiMode) configSection = host.PoCConfig['CONFIG.DirectoryNames'] self.Directories.Working = host.Directories.Temp / configSection['CocotbFiles'] diff --git a/py/Simulator/GHDLSimulator.py b/py/Simulator/GHDLSimulator.py index ff591127..97c8cea4 100644 --- a/py/Simulator/GHDLSimulator.py +++ b/py/Simulator/GHDLSimulator.py @@ -32,15 +32,6 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module Simulator.GHDLSimulator") - - # load dependencies from pathlib import Path @@ -52,7 +43,15 @@ from ToolChains.GTKWave import GTKWave +__api__ = [ + 'Simulator' +] +__all__ = __api__ + + class Simulator(BaseSimulator): + """This class encapsulates the GHDL simulator.""" + _TOOL_CHAIN = ToolChain.GHDL_GTKWave _TOOL = Tool.GHDL @@ -60,9 +59,9 @@ class __Directories__(BaseSimulator.__Directories__): GTKWBinary = None def __init__(self, host, dryRun, guiMode): - super().__init__(host, dryRun) + """Constructor""" + super().__init__(host, dryRun, guiMode) - self._guiMode = guiMode self._vhdlGenerics = None self._toolChain = None @@ -70,7 +69,7 @@ def __init__(self, host, dryRun, guiMode): self.Directories.Working = host.Directories.Temp / ghdlFilesDirectoryName self.Directories.PreCompiled = host.Directories.PreCompiled / ghdlFilesDirectoryName - if (guiMode is True): + if (self._guiMode is True): # prepare paths for GTKWave, if configured sectionName = 'INSTALL.GTKWave' if (len(host.PoCConfig.options(sectionName)) != 0): @@ -82,6 +81,8 @@ def __init__(self, host, dryRun, guiMode): self._PrepareSimulator() def _PrepareSimulator(self): + """""" + # create the GHDL executable factory self.LogVerbose("Preparing GHDL simulator.") ghdlSection = self.Host.PoCConfig['INSTALL.GHDL'] @@ -91,6 +92,8 @@ def _PrepareSimulator(self): self._toolChain = GHDL(self.Host.Platform, self.DryRun, binaryPath, version, backend, logger=self.Logger) def _RunAnalysis(self, testbench): + """""" + # create a GHDLAnalyzer instance ghdl = self._toolChain.GetGHDLAnalyze() ghdl.Parameters[ghdl.FlagVerbose] = (self.Logger.LogLevel is Severity.Debug) @@ -121,6 +124,8 @@ def _RunAnalysis(self, testbench): raise SkipableSimulatorException("Error while analysing '{0!s}'.".format(file.Path)) def _SetVHDLVersionAndIEEEFlavor(self, ghdl): + """""" + ghdl.Parameters[ghdl.SwitchIEEEFlavor] = "synopsys" if (self._vhdlVersion is VHDLVersion.VHDL93): @@ -129,6 +134,8 @@ def _SetVHDLVersionAndIEEEFlavor(self, ghdl): ghdl.Parameters[ghdl.SwitchVHDLVersion] = repr(self._vhdlVersion)[-2:] def _SetExternalLibraryReferences(self, ghdl): + """""" + # add external library references externalLibraryReferences = [] for extLibrary in self._pocProject.ExternalVHDLLibraries: @@ -140,6 +147,8 @@ def _SetExternalLibraryReferences(self, ghdl): # running elaboration # ========================================================================== def _RunElaboration(self, testbench): + """""" + if (self._toolChain.Backend == "mcode"): return @@ -161,6 +170,8 @@ def _RunElaboration(self, testbench): raise SkipableSimulatorException("Error while elaborating '{0}.{1}'.".format(VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName)) def _RunSimulation(self, testbench): + """""" + # create a GHDLRun instance ghdl = self._toolChain.GetGHDLRun() ghdl.Parameters[ghdl.FlagVerbose] = (self.Logger.LogLevel is Severity.Debug) @@ -206,6 +217,8 @@ def _RunSimulation(self, testbench): testbench.Result = ghdl.Run() def _RunView(self, testbench): + """foo""" + if (not testbench.WaveformFile.exists()): raise SkipableSimulatorException("Waveform file '{0!s}' not found.".format(testbench.WaveformFile)) \ from FileNotFoundError(str(testbench.WaveformFile)) diff --git a/py/Simulator/ISESimulator.py b/py/Simulator/ISESimulator.py index 8acd9448..d9559436 100644 --- a/py/Simulator/ISESimulator.py +++ b/py/Simulator/ISESimulator.py @@ -32,15 +32,6 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module Simulator.ISESimulator") - - # load dependencies from pathlib import Path @@ -50,15 +41,20 @@ from ToolChains.Xilinx.ISE import ISE, ISESimulator, ISEException +__api__ = [ + 'Simulator' +] +__all__ = __api__ + + class Simulator(BaseSimulator, XilinxProjectExportMixIn): _TOOL_CHAIN = ToolChain.Xilinx_ISE _TOOL = Tool.Xilinx_iSim def __init__(self, host, dryRun, guiMode): - super().__init__(host, dryRun) + super().__init__(host, dryRun, guiMode) XilinxProjectExportMixIn.__init__(self) - self._guiMode = guiMode self._vhdlGenerics = None self._toolChain = None diff --git a/py/Simulator/QuestaSimulator.py b/py/Simulator/QuestaSimulator.py index 80fcc9bd..1bc5e5b2 100644 --- a/py/Simulator/QuestaSimulator.py +++ b/py/Simulator/QuestaSimulator.py @@ -30,15 +30,6 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module Simulator.vSimSimulator") - - # load dependencies from pathlib import Path @@ -49,14 +40,19 @@ from ToolChains.Mentor.QuestaSim import QuestaSim, QuestaSimException +__api__ = [ + 'Simulator' +] +__all__ = __api__ + + class Simulator(BaseSimulator): _TOOL_CHAIN = ToolChain.Mentor_QuestaSim _TOOL = Tool.Mentor_vSim def __init__(self, host, dryRun, guiMode): - super().__init__(host, dryRun) + super().__init__(host, dryRun, guiMode) - self._guiMode = guiMode self._vhdlVersion = None self._vhdlGenerics = None self._toolChain = None @@ -143,7 +139,8 @@ def _RunSimulation(self, testbench): if self._guiMode: return self._RunSimulationWithGUI(testbench) - tclBatchFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['vSimBatchScript'] + tclBatchFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['vSimBatchScript'] + tclDefaultBatchFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['vSimDefaultBatchScript'] # create a QuestaSimulator instance vsim = self._toolChain.GetSimulator() @@ -152,13 +149,29 @@ def _RunSimulation(self, testbench): vsim.Parameters[vsim.FlagReportAsError] = "3473" vsim.Parameters[vsim.SwitchTimeResolution] = "1fs" vsim.Parameters[vsim.FlagCommandLineMode] = True - vsim.Parameters[vsim.SwitchBatchCommand] = "do {0}".format(tclBatchFilePath.as_posix()) vsim.Parameters[vsim.SwitchTopLevel] = "{0}.{1}".format(VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName) + + # find a Tcl batch script for the BATCH mode + vsimBatchCommand = "" + if (tclBatchFilePath.exists()): + self.LogDebug("Found Tcl script for BATCH mode: '{0!s}'".format(tclBatchFilePath)) + vsimBatchCommand += "do {0};".format(tclBatchFilePath.as_posix()) + elif (tclDefaultBatchFilePath.exists()): + self.LogDebug("Falling back to default Tcl script for BATCH mode: '{0!s}'".format(tclDefaultBatchFilePath)) + vsimBatchCommand += "do {0};".format(tclDefaultBatchFilePath.as_posix()) + else: + raise QuestaSimException("No Tcl batch script for BATCH mode found.") \ + from FileNotFoundError(str(tclDefaultBatchFilePath)) + + vsim.Parameters[vsim.SwitchBatchCommand] = vsimBatchCommand + testbench.Result = vsim.Simulate() def _RunSimulationWithGUI(self, testbench): - tclGUIFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['vSimGUIScript'] - tclWaveFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['vSimWaveScript'] + tclGUIFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['vSimGUIScript'] + tclWaveFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['vSimWaveScript'] + tclDefaultGUIFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['vSimDefaultGUIScript'] + tclDefaultWaveFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['vSimDefaultWaveScript'] # create a QuestaSimulator instance vsim = self._toolChain.GetSimulator() @@ -170,11 +183,47 @@ def _RunSimulationWithGUI(self, testbench): vsim.Parameters[vsim.SwitchTopLevel] = "{0}.{1}".format(VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName) # vsim.Parameters[vsim.SwitchTitle] = testbenchName - if (tclWaveFilePath.exists()): - self.LogDebug("Found waveform script: '{0!s}'".format(tclWaveFilePath)) - vsim.Parameters[vsim.SwitchBatchCommand] = "do {0}; do {1}".format(tclWaveFilePath.as_posix(), tclGUIFilePath.as_posix()) + vsimDefaultWaveCommands = "add wave *" + + # find a Tcl batch script to load predefined signals in the waveform window + vsimBatchCommand = "" + self.LogDebug("'{0!s}'\n '{1!s}'".format(tclWaveFilePath, self.Host.Directories.Root)) + if (tclWaveFilePath != self.Host.Directories.Root): + if (tclWaveFilePath.exists()): + self.LogDebug("Found waveform script: '{0!s}'".format(tclWaveFilePath)) + vsimBatchCommand = "do {0};".format(tclWaveFilePath.as_posix()) + elif (tclDefaultWaveFilePath != self.Host.Directories.Root): + if (tclDefaultWaveFilePath.exists()): + self.LogDebug("Found default waveform script: '{0!s}'".format(tclDefaultWaveFilePath)) + vsimBatchCommand = "do {0};".format(tclDefaultWaveFilePath.as_posix()) + else: + self.LogDebug("Couldn't find default waveform script: '{0!s}'. Loading default command '{1}'.".format(tclDefaultWaveFilePath, vsimDefaultWaveCommands)) + vsimBatchCommand = "{0};".format(vsimDefaultWaveCommands) + else: + self.LogDebug("Couldn't find waveform script: '{0!s}'. Loading default command '{1}'.".format(tclWaveFilePath, vsimDefaultWaveCommands)) + vsim.Parameters[vsim.SwitchBatchCommand] = "{0};".format(vsimDefaultWaveCommands) + elif (tclDefaultWaveFilePath != self.Host.Directories.Root): + if (tclDefaultWaveFilePath.exists()): + self.LogDebug("Falling back to default waveform script: '{0!s}'".format(tclDefaultWaveFilePath)) + vsimBatchCommand = "do {0};".format(tclDefaultWaveFilePath.as_posix()) + else: + self.LogDebug("Couldn't find default waveform script: '{0!s}'. Loading default command '{1}'.".format(tclDefaultWaveFilePath, vsimDefaultWaveCommands)) + vsimBatchCommand = "{0};".format(vsimDefaultWaveCommands) else: - self.LogDebug("Didn't find waveform script: '{0!s}'. Loading default commands.".format(tclWaveFilePath)) - vsim.Parameters[vsim.SwitchBatchCommand] = "add wave *; do {0}".format(tclGUIFilePath.as_posix()) + self.LogWarning("No waveform script specified. Loading default command '{1}'.".format(vsimDefaultWaveCommands)) + vsimBatchCommand = "{0};".format(vsimDefaultWaveCommands) + + # find a Tcl batch script for the GUI mode + if (tclGUIFilePath.exists()): + self.LogDebug("Found Tcl script for GUI mode: '{0!s}'".format(tclGUIFilePath)) + vsimBatchCommand += "do {0};".format(tclGUIFilePath.as_posix()) + elif (tclDefaultGUIFilePath.exists()): + self.LogDebug("Falling back to default Tcl script for GUI mode: '{0!s}'".format(tclDefaultGUIFilePath)) + vsimBatchCommand += "do {0};".format(tclDefaultGUIFilePath.as_posix()) + else: + raise QuestaSimException("No Tcl batch script for GUI mode found.") \ + from FileNotFoundError(str(tclDefaultGUIFilePath)) + + vsim.Parameters[vsim.SwitchBatchCommand] = vsimBatchCommand testbench.Result = vsim.Simulate() diff --git a/py/Simulator/VivadoSimulator.py b/py/Simulator/VivadoSimulator.py index 5864a18b..a14fcf0f 100644 --- a/py/Simulator/VivadoSimulator.py +++ b/py/Simulator/VivadoSimulator.py @@ -32,15 +32,6 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module Simulator.VivadoSimulator") - - # load dependencies from pathlib import Path @@ -51,15 +42,20 @@ from ToolChains.Xilinx.Vivado import Vivado, VivadoException +__api__ = [ + 'Simulator' +] +__all__ = __api__ + + class Simulator(BaseSimulator, XilinxProjectExportMixIn): _TOOL_CHAIN = ToolChain.Xilinx_Vivado _TOOL = Tool.Xilinx_xSim def __init__(self, host, dryRun, guiMode): - super().__init__(host, dryRun) + super().__init__(host, dryRun, guiMode) XilinxProjectExportMixIn.__init__(self) - self._guiMode = guiMode self._vhdlVersion = None self._vhdlGenerics = None self._toolChain = None diff --git a/py/ToolChains/Aldec/ActiveHDL.py b/py/ToolChains/Aldec/ActiveHDL.py index b50aa70f..eb9a1af4 100644 --- a/py/ToolChains/Aldec/ActiveHDL.py +++ b/py/ToolChains/Aldec/ActiveHDL.py @@ -33,16 +33,7 @@ # ============================================================================== # # entry point -from subprocess import check_output - - -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module ToolChains.Aldec.ActiveHDL") - +from subprocess import check_output from lib.Functions import CallByRefParam from Base.Exceptions import PlatformNotSupportedException @@ -55,6 +46,22 @@ from ToolChains.Aldec.Aldec import AldecException +__api__ = [ + 'ActiveHDLException', + 'Configuration', + 'ActiveHDLMixIn', + 'ActiveHDL', + 'VHDLCompiler', + 'StandaloneSimulator', + 'Simulator', + 'ActiveHDLVHDLLibraryTool', + 'VHDLCompilerFilter', + 'SimulatorFilter', + 'VHDLLibraryToolFilter' +] +__all__ = __api__ + + class ActiveHDLException(AldecException): pass diff --git a/py/ToolChains/Aldec/Aldec.py b/py/ToolChains/Aldec/Aldec.py index f530254f..50fb7e0b 100644 --- a/py/ToolChains/Aldec/Aldec.py +++ b/py/ToolChains/Aldec/Aldec.py @@ -32,19 +32,18 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module ToolChains.Aldec.Aldec") - - +# load dependencies from Base.Configuration import Configuration as BaseConfiguration from Base.ToolChain import ToolChainException +__api__ = [ + 'AldecException', + 'Configuration' +] +__all__ = __api__ + + class AldecException(ToolChainException): pass diff --git a/py/ToolChains/Altera/Altera.py b/py/ToolChains/Altera/Altera.py index a59e272f..6f773f67 100644 --- a/py/ToolChains/Altera/Altera.py +++ b/py/ToolChains/Altera/Altera.py @@ -32,19 +32,18 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module Compiler.XSTCompiler") - - +# load dependencies from Base.Configuration import Configuration as BaseConfiguration from Base.ToolChain import ToolChainException +__api__ = [ + 'AlteraException', + 'Configuration' +] +__all__ = __api__ + + class AlteraException(ToolChainException): pass diff --git a/py/ToolChains/Altera/ModelSim.py b/py/ToolChains/Altera/ModelSim.py index ce5a524d..5d4e16be 100644 --- a/py/ToolChains/Altera/ModelSim.py +++ b/py/ToolChains/Altera/ModelSim.py @@ -33,15 +33,7 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module ToolChains.Altera.ModelSim") - - +# load dependencies from re import compile as RegExpCompile from subprocess import check_output @@ -49,6 +41,13 @@ from ToolChains.Altera.Altera import AlteraException +__api__ = [ + 'ModelSimException', + 'Configuration' +] +__all__ = __api__ + + class ModelSimException(AlteraException): pass diff --git a/py/ToolChains/Altera/Quartus.py b/py/ToolChains/Altera/Quartus.py index 5c596961..c696fb8b 100644 --- a/py/ToolChains/Altera/Quartus.py +++ b/py/ToolChains/Altera/Quartus.py @@ -32,15 +32,7 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module ToolChains.Altera.Quartus") - - +# load dependencies from collections import OrderedDict from subprocess import check_output, STDOUT @@ -53,6 +45,22 @@ from ToolChains.Altera.Altera import AlteraException +__api__ = [ + 'QuartusException', + 'Configuration', + 'QuartusMixIn', + 'Quartus', + 'Map', + 'TclShell', + 'MapFilter', + 'QuartusSession', + 'QuartusProject', + 'QuartusSettings', + 'QuartusProjectFile' +] +__all__ = __api__ + + class QuartusException(AlteraException): pass @@ -211,6 +219,7 @@ def Compile(self) : if self._hasOutput: self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) + class TclShell(Executable, QuartusMixIn): def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): QuartusMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) @@ -233,6 +242,7 @@ class SwitchShell(metaclass=ShortFlagArgument): SwitchShell ) + def MapFilter(gen): iterator = iter(gen) diff --git a/py/ToolChains/GHDL.py b/py/ToolChains/GHDL.py index 8119dc71..cebd6040 100644 --- a/py/ToolChains/GHDL.py +++ b/py/ToolChains/GHDL.py @@ -33,15 +33,7 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module ToolChains.GHDL") - - +# load dependencies from pathlib import Path from re import compile as re_compile from subprocess import check_output, CalledProcessError @@ -57,6 +49,21 @@ from lib.Functions import CallByRefParam +__api__ = [ + 'GHDLException', + 'GHDLReanalyzeException', + 'Configuration', + 'GHDL', + 'GHDLAnalyze', + 'GHDLElaborate', + 'GHDLRun', + 'GHDLAnalyzeFilter', + 'GHDLElaborateFilter', + 'GHDLRunFilter' +] +__all__ = __api__ + + class GHDLException(ToolChainException): pass @@ -389,6 +396,7 @@ def Analyze(self): if self._hasOutput: self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) + class GHDLElaborate(GHDL): def __init__(self, platform, dryrun, binaryDirectoryPath, version, backend, logger=None): super().__init__(platform, dryrun, binaryDirectoryPath, version, backend, logger=logger) @@ -436,6 +444,7 @@ def Elaborate(self): if self._hasOutput: self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) + class GHDLRun(GHDL): def __init__(self, platform, dryrun, binaryDirectoryPath, version, backend, logger=None): super().__init__(platform, dryrun, binaryDirectoryPath, version, backend, logger=logger) diff --git a/py/ToolChains/GNU.py b/py/ToolChains/GNU.py index 3fbabca9..44526e3b 100644 --- a/py/ToolChains/GNU.py +++ b/py/ToolChains/GNU.py @@ -32,14 +32,6 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module ToolChains.GNU") - # load dependencies import re @@ -51,6 +43,16 @@ from lib.Functions import Init, CallByRefParam +__api__ = [ + 'GNUException', + # 'Configuration', + 'Make', + 'GNUMakeQuestaSimFilter', + 'CocotbSimulationResultFilter' +] +__all__ = __api__ + + class GNUException(ToolChainException): pass diff --git a/py/ToolChains/GTKWave.py b/py/ToolChains/GTKWave.py index 4c6b84f2..31f873b1 100644 --- a/py/ToolChains/GTKWave.py +++ b/py/ToolChains/GTKWave.py @@ -33,15 +33,7 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module ToolChains.GTKWave") - - +# load dependencies from pathlib import Path from re import compile as RegExpCompile from subprocess import check_output, CalledProcessError @@ -53,6 +45,16 @@ from Base.ToolChain import ToolChainException +__api__ = [ + 'GTKWaveException', + 'Configuration', + 'GTKWave', + 'GTKWaveFilter' +] +__all__ = __api__ + + + class GTKWaveException(ToolChainException): pass @@ -135,7 +137,6 @@ def __WriteGtkWaveSection(self, binPath): self._host.PoCConfig[self._section]['Version'] = version - class GTKWave(Executable): def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): if (platform == "Windows"): executablePath = binaryDirectoryPath/ "gtkwave.exe" @@ -216,6 +217,7 @@ def View(self): if self._hasOutput: self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) + def GTKWaveFilter(gen): for line in gen: yield LogEntry(line, Severity.Normal) diff --git a/py/ToolChains/Git.py b/py/ToolChains/Git.py index e3dda915..b94600bd 100644 --- a/py/ToolChains/Git.py +++ b/py/ToolChains/Git.py @@ -33,15 +33,7 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module ToolChains.PoC") - - +# load dependencies from pathlib import Path from re import compile as re_compile from subprocess import check_output, CalledProcessError @@ -55,6 +47,20 @@ from Base.ToolChain import ToolChainException +__api__ = [ + 'GitException', + 'Configuration', + 'GitMixIn', + 'Git', + 'GitSCM', + 'GitRevParse', + 'GitRevList', + 'GitDescribe', + 'GitConfig' +] +__all__ = __api__ + + class GitException(ToolChainException): pass diff --git a/py/ToolChains/Lattice/ActiveHDL.py b/py/ToolChains/Lattice/ActiveHDL.py index 7eac20bd..b1383dcc 100644 --- a/py/ToolChains/Lattice/ActiveHDL.py +++ b/py/ToolChains/Lattice/ActiveHDL.py @@ -32,15 +32,7 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module ToolChains.Lattice.ActiveHDL") - - +# load dependencies from subprocess import check_output from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException diff --git a/py/ToolChains/Lattice/Diamond.py b/py/ToolChains/Lattice/Diamond.py index b5b51c3f..79031090 100644 --- a/py/ToolChains/Lattice/Diamond.py +++ b/py/ToolChains/Lattice/Diamond.py @@ -32,17 +32,9 @@ # limitations under the License. # ============================================================================== # -# entry point +# load dependencies import time - -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module ToolChains.Lattice.Diamond") - from pathlib import Path from subprocess import check_output, CalledProcessError, STDOUT @@ -54,6 +46,19 @@ from ToolChains.Lattice.Lattice import LatticeException +__api__ = [ + 'DiamondException', + 'Configuration', + 'DiamondMixIn', + 'Diamond', + 'Synth', + 'SynthesisArgumentFile', + 'MapFilter', + 'CompilerFilter' +] +__all__ = __api__ + + class DiamondException(LatticeException): pass @@ -232,11 +237,6 @@ def Compile(self, logFile): self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) -def MapFilter(gen): - for line in gen: - yield LogEntry(line, Severity.Normal) - - class SynthesisArgumentFile(File): def __init__(self, file): super().__init__(file) @@ -331,6 +331,11 @@ def Write(self, project): fileHandle.write(buffer) +def MapFilter(gen): + for line in gen: + yield LogEntry(line, Severity.Normal) + + def CompilerFilter(gen): for line in gen: if line.startswith("ERROR "): diff --git a/py/ToolChains/Lattice/Lattice.py b/py/ToolChains/Lattice/Lattice.py index 5242f0dc..27a41401 100644 --- a/py/ToolChains/Lattice/Lattice.py +++ b/py/ToolChains/Lattice/Lattice.py @@ -32,20 +32,20 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module ToolChains.Lattice.Diamond") - - +# load dependencies from Base.Configuration import Configuration as BaseConfiguration from Base.Project import ConstraintFile, FileTypes from Base.ToolChain import ToolChainException +__api__ = [ + 'LatticeException', + 'Configuration', + 'LatticeDesignConstraintFile' +] +__all__ = __api__ + + class LatticeException(ToolChainException): pass diff --git a/py/ToolChains/Lattice/Synopsys.py b/py/ToolChains/Lattice/Synplify.py similarity index 81% rename from py/ToolChains/Lattice/Synopsys.py rename to py/ToolChains/Lattice/Synplify.py index b3f22653..5410d382 100644 --- a/py/ToolChains/Lattice/Synopsys.py +++ b/py/ToolChains/Lattice/Synplify.py @@ -31,24 +31,22 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module ToolChains.Lattice.Synopsys") +# load dependencies +from Base.Configuration import Configuration as BaseConfiguration +from Base.ToolChain import ToolChainException -# from collections import OrderedDict -# from pathlib import Path +__api__ = [ + 'SynplifyException', + 'Configuration' +] +__all__ = __api__ -from Base.Configuration import Configuration as BaseConfiguration -from Base.ToolChain import ToolChainException -class SynopsysException(ToolChainException): +class SynplifyException(ToolChainException): pass + class Configuration(BaseConfiguration): def __init__(self, host): super().__init__(host) diff --git a/py/ToolChains/Mentor/Mentor.py b/py/ToolChains/Mentor/Mentor.py index 6365671d..9f74a37f 100644 --- a/py/ToolChains/Mentor/Mentor.py +++ b/py/ToolChains/Mentor/Mentor.py @@ -32,19 +32,18 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module ToolChains.Mentor.QuestaSim") - - +# load dependencies from Base.Configuration import Configuration as BaseConfiguration from Base.ToolChain import ToolChainException +__api__ = [ + 'MentorException', + 'Configuration' +] +__all__ = __api__ + + class MentorException(ToolChainException): pass diff --git a/py/ToolChains/Mentor/QuestaSim.py b/py/ToolChains/Mentor/QuestaSim.py index 7c8cf469..84772a93 100644 --- a/py/ToolChains/Mentor/QuestaSim.py +++ b/py/ToolChains/Mentor/QuestaSim.py @@ -32,15 +32,7 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module ToolChains.Mentor.QuestaSim") - - +# load dependencies from subprocess import check_output from textwrap import dedent @@ -54,6 +46,21 @@ from ToolChains.Mentor.Mentor import MentorException +__api__ = [ + 'QuestaSimException', + 'Configuration', + 'QuestaSimMixIn', + 'QuestaSim', + 'QuestaVHDLCompiler', + 'QuestaSimulator', + 'QuestaVHDLLibraryTool', + 'QuestaVComFilter', + 'QuestaVSimFilter', + 'QuestaVLibFilter' +] +__all__ = __api__ + + class QuestaSimException(MentorException): pass diff --git a/py/ToolChains/PoC.py b/py/ToolChains/PoC.py index 64c9bf03..bd43672d 100644 --- a/py/ToolChains/PoC.py +++ b/py/ToolChains/PoC.py @@ -33,15 +33,7 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module ToolChains.PoC") - - +# load dependencies from os import environ from pathlib import Path from subprocess import check_output, check_call, CalledProcessError @@ -50,6 +42,13 @@ from ToolChains.Git import Git +__api__ = [ + 'Configuration' +] +__all__ = __api__ + + + class Configuration(BaseConfiguration): _vendor = "VLSI-EDA" _toolName = "PoC" diff --git a/py/ToolChains/Synopsys/Synopsys.py b/py/ToolChains/Synopsys/Synopsys.py index 4efdb8da..9a7c50d4 100644 --- a/py/ToolChains/Synopsys/Synopsys.py +++ b/py/ToolChains/Synopsys/Synopsys.py @@ -31,20 +31,20 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module ToolChains.Synopsys.Synopsys") - - +# load dependencies from Base.Configuration import Configuration as BaseConfiguration from Base.Project import ConstraintFile, FileTypes from Base.ToolChain import ToolChainException +__api__ = [ + 'SynopsysException', + 'Configuration', + 'SynopsysDesignConstraintFile' +] +__all__ = __api__ + + class SynopsysException(ToolChainException): pass diff --git a/py/ToolChains/Xilinx/ISE.py b/py/ToolChains/Xilinx/ISE.py index bbb3a661..ba12f6c5 100644 --- a/py/ToolChains/Xilinx/ISE.py +++ b/py/ToolChains/Xilinx/ISE.py @@ -32,15 +32,7 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module ToolChains.Xilinx.ISE") - - +# load dependencies from subprocess import check_output from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException @@ -54,6 +46,27 @@ from lib.Functions import CallByRefParam +__api__ = [ + 'ISEException', + 'Configuration', + 'ISEMixIn', + 'ISE', + 'Fuse', + 'ISESimulator', + 'Xst', + 'CoreGenerator', + 'VhCompFilter', + 'FuseFilter', + 'SimulatorFilter', + 'XstFilter', + 'CoreGeneratorFilter' + 'ISEProject', + 'ISEProjectFile', + 'UserConstraintFile' +] +__all__ = __api__ + + class ISEException(XilinxException): pass diff --git a/py/ToolChains/Xilinx/Vivado.py b/py/ToolChains/Xilinx/Vivado.py index d2e5b0b3..082d633a 100644 --- a/py/ToolChains/Xilinx/Vivado.py +++ b/py/ToolChains/Xilinx/Vivado.py @@ -32,17 +32,9 @@ # limitations under the License. # ============================================================================== # -# entry point +# load dependencies from subprocess import check_output -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module ToolChains.Xilinx.Vivado") - - from lib.Functions import CallByRefParam from Base.Exceptions import PlatformNotSupportedException from Base.Logging import LogEntry, Severity @@ -54,6 +46,24 @@ from ToolChains.Xilinx.Xilinx import XilinxException +__api__ = [ + 'VivadoException', + 'Configuration', + 'VivadoMixIn', + 'Vivado', + 'XElab', + 'XSim', + 'Synth', + 'ElaborationFilter', + 'SimulatorFilter', + 'CompilerFilter', + 'VivadoProject', + 'VivadoProjectFile', + 'XilinxDesignConstraintFile' +] +__all__ = __api__ + + class VivadoException(XilinxException): pass diff --git a/py/ToolChains/Xilinx/Xilinx.py b/py/ToolChains/Xilinx/Xilinx.py index b88ac27d..69893847 100644 --- a/py/ToolChains/Xilinx/Xilinx.py +++ b/py/ToolChains/Xilinx/Xilinx.py @@ -32,15 +32,7 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module ToolChains.Xilinx.Xilinx") - - +# load dependencies from os import environ from pathlib import Path @@ -49,9 +41,18 @@ from Base.ToolChain import ToolChainException +__api__ = [ + 'XilinxException', + 'Configuration', + 'XilinxProjectExportMixIn' +] +__all__ = __api__ + + class XilinxException(ToolChainException): pass + class Configuration(BaseConfiguration): _vendor = "Xilinx" _toolName = None # automatically configure only vendor path diff --git a/py/config.defaults.ini b/py/config.defaults.ini index d77d3d86..23e180be 100644 --- a/py/config.defaults.ini +++ b/py/config.defaults.ini @@ -131,9 +131,12 @@ ghdlWaveformOptionFile = ${SimDir}/${TestbenchModule}.ghdl ghdlWaveformFileFormat = ghw gtkwSaveFile = ${SimDir}/${TestbenchModule}.gtkw # ModelSim / QuestaSim -vSimBatchScript = ${PoC:SimDir}/vSim.batch.tcl -vSimGUIScript = ${PoC:SimDir}/vSim.gui.tcl +vSimBatchScript = ${SimDir}/${TestbenchModule}.vsim.batch.tcl +vSimGUIScript = ${SimDir}/${TestbenchModule}.vsim.gui.tcl vSimWaveScript = ${SimDir}/${TestbenchModule}.wdo +vSimDefaultBatchScript = ${PoC:SimDir}/vSim.batch.tcl +vSimDefaultGUIScript = ${PoC:SimDir}/vSim.gui.tcl +vSimDefaultWaveScript = ${PoC:SimDir}/vSim.default.wdo # Xilinx ISE iSimBatchScript = ${PoC:SimDir}/iSim.batch.tcl iSimGUIScript = ${PoC:SimDir}/iSim.gui.tcl diff --git a/py/lib/CodeDOM.py b/py/lib/CodeDOM.py index 62d52c00..2104d166 100644 --- a/py/lib/CodeDOM.py +++ b/py/lib/CodeDOM.py @@ -29,10 +29,49 @@ # limitations under the License. # ============================================================================== # +# load dependencies from lib.Functions import Init from lib.Parser import MismatchingParserResult, MatchingParserResult, EmptyChoiseParserResult, GreedyMatchingParserResult from lib.Parser import SpaceToken, CharacterToken, StringToken, NumberToken, Tokenizer + +__api__ = [ + 'CodeDOMMeta', + 'CodeDOMObject', + 'Expression', + 'UnaryExpression', + 'NotExpression', + 'BinaryExpression', + 'LogicalExpression', + 'CompareExpression', + 'EqualExpression', + 'UnequalExpression', + 'LessThanExpression', + 'LessThanEqualExpression', + 'GreaterThanExpression', + 'GreaterThanEqualExpression', + 'AndExpression', + 'OrExpression', + 'XorExpression', + 'InExpression', + 'NotInExpression', + 'Function', + 'ListElement', + 'Literal', + 'StringLiteral', + 'IntegerLiteral', + 'Identifier', + 'Statement', + 'BlockStatement', + 'ConditionalBlockStatement', + 'EmptyLine', + 'CommentLine', + 'BlockedStatement', + 'ExpressionChoice' +] +__all__ = __api__ + + DEBUG = False#True # ============================================================================== diff --git a/py/lib/Decorators.py b/py/lib/Decorators.py index 559263e1..b8211a6c 100644 --- a/py/lib/Decorators.py +++ b/py/lib/Decorators.py @@ -1,6 +1,46 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# Thomas B. Preusser +# +# Python functions: Auxillary functions to exit a program and report an error message. +# +# Description: +# ------------------------------------ +# TODO: +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair of VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +# +# load dependencies +import functools -import functools +__api__ = [ + 'ILazyLoadable', + 'LazyLoadTrigger', + 'CachedReadOnlyProperty' +] +__all__ = __api__ + class ILazyLoadable: def __init__(self): @@ -13,6 +53,7 @@ def _LazyLoadable_Load(self): def LazyLoadable_IsLoaded(self): return self.__IsLoaded + class LazyLoadTrigger: def __init__(self, func): self.func = func @@ -25,6 +66,7 @@ def __call__(self, inst, *args, **kwargs): def __repr__(self): return self.func.__doc__ + class CachedReadOnlyProperty: def __init__(self, func): self.func = func diff --git a/py/lib/ExtendedConfigParser/__init__.py b/py/lib/ExtendedConfigParser/__init__.py index 00336355..b9c05521 100644 --- a/py/lib/ExtendedConfigParser/__init__.py +++ b/py/lib/ExtendedConfigParser/__init__.py @@ -32,15 +32,23 @@ # limitations under the License. # ============================================================================== # -import functools -import re -from sys import version_info +# load dependencies +from itertools import chain as itertools_chain +from functools import partial as functools_partial +from re import compile as re_compile, escape as re_escape, VERBOSE as RE_VERBOSE +from sys import version_info from collections import OrderedDict as _default_dict, ChainMap as _ChainMap, MutableMapping from configparser import ConfigParser, SectionProxy, Interpolation, MAX_INTERPOLATION_DEPTH, DEFAULTSECT, _UNSET from configparser import NoSectionError, InterpolationDepthError, InterpolationSyntaxError, NoOptionError, InterpolationMissingOptionError -import itertools + +__api__ = [ + 'ExtendedSectionProxy', + 'ExtendedInterpolation', + 'ExtendedConfigParser' +] +__all__ = __api__ class ExtendedSectionProxy(SectionProxy): @@ -60,7 +68,7 @@ class ConverterMapping(MutableMapping): section proxies to find and use the implementation on the parser class. """ - GETTERCRE = re.compile(r"^get(?P.+)$") + GETTERCRE = re_compile(r"^get(?P.+)$") def __init__(self, parser): self._parser = parser @@ -83,11 +91,11 @@ def __setitem__(self, key, value): if k == 'get': raise ValueError('Incompatible key: cannot use "" as a name') self._data[key] = value - func = functools.partial(self._parser._get_conv, conv=value) + func = functools_partial(self._parser._get_conv, conv=value) func.converter = value setattr(self._parser, k, func) for proxy in self._parser.values(): - getter = functools.partial(proxy.get, _impl=func) + getter = functools_partial(proxy.get, _impl=func) setattr(proxy, k, getter) def __delitem__(self, key): @@ -96,7 +104,7 @@ def __delitem__(self, key): except TypeError: raise KeyError(key) del self._data[key] - for inst in itertools.chain((self._parser,), self._parser.values()): + for inst in itertools_chain((self._parser,), self._parser.values()): try: delattr(inst, k) except AttributeError: @@ -119,8 +127,8 @@ def __len__(self): class ExtendedInterpolation(Interpolation): - _KEYCRE = re.compile(r"\$\{(?P[^}]+)\}") - _KEYCRE2 = re.compile(r"\$\[(?P[^\]]+)\}") + _KEYCRE = re_compile(r"\$\{(?P[^}]+)\}") + _KEYCRE2 = re_compile(r"\$\[(?P[^\]]+)\}") def __init__(self): self._cache = dict() @@ -315,9 +323,9 @@ def __init__(self, defaults=None, dict_type=_default_dict, allow_no_value=False, if delimiters == ('=', ':'): self._optcre = self.OPTCRE_NV if allow_no_value else self.OPTCRE else: - d = "|".join(re.escape(d) for d in delimiters) - if allow_no_value: self._optcre = re.compile(self._OPT_NV_TMPL.format(delim=d), re.VERBOSE) - else: self._optcre = re.compile(self._OPT_TMPL.format(delim=d), re.VERBOSE) + d = "|".join(re_escape(d) for d in delimiters) + if allow_no_value: self._optcre = re_compile(self._OPT_NV_TMPL.format(delim=d), RE_VERBOSE) + else: self._optcre = re_compile(self._OPT_TMPL.format(delim=d), RE_VERBOSE) if (interpolation is None): self._interpolation = Interpolation() elif (interpolation is _UNSET): self._interpolation = ExtendedInterpolation() diff --git a/py/lib/Functions.py b/py/lib/Functions.py index e63008f3..a3850696 100644 --- a/py/lib/Functions.py +++ b/py/lib/Functions.py @@ -30,11 +30,21 @@ # limitations under the License. # ============================================================================== # +# load dependencies from functools import reduce from operator import or_ from sys import version_info +__api__ = [ + 'merge', 'merge_with', + 'CallByRefParam', + 'Init', + 'Exit' +] +__all__ = __api__ + + def merge(*dicts): """Merge 2 or more dictionaries.""" return {k : reduce(lambda d,x: x.get(k, d), dicts, None) for k in reduce(or_, map(lambda x: x.keys(), dicts), set()) } diff --git a/py/lib/Parser.py b/py/lib/Parser.py index 813cf3c3..caae13e8 100644 --- a/py/lib/Parser.py +++ b/py/lib/Parser.py @@ -28,9 +28,31 @@ # limitations under the License. # ============================================================================== # +# load dependencies from enum import Enum +__api__ = [ + 'ParserException', + 'MismatchingParserResult', + 'EmptyChoiseParserResult', + 'MatchingParserResult', + 'GreedyMatchingParserResult', + 'SourceCodePosition', + 'Token', + 'SuperToken', + 'ValuedToken', + 'StartOfDocumentToken', + 'CharacterToken', + 'SpaceToken', + 'DelimiterToken', + 'NumberToken', + 'StringToken', + 'Tokenizer' +] +__all__ = __api__ + + class ParserException(Exception): pass @@ -148,6 +170,7 @@ def __str__(self): return "".format( value=self.Value, pos=self.Start.Absolute, line=self.Start.Row, col=self.Start.Column) + class DelimiterToken(ValuedToken): def __str__(self): return "".format( diff --git a/py/lib/pyAttribute/ArgParseAttributes.py b/py/lib/pyAttribute/ArgParseAttributes.py index a161f2d7..fc99672a 100644 --- a/py/lib/pyAttribute/ArgParseAttributes.py +++ b/py/lib/pyAttribute/ArgParseAttributes.py @@ -36,9 +36,23 @@ # limitations under the License. # ============================================================================ # +# load dependencies from . import Attribute, AttributeHelperMixin +__api__ = [ + 'CommandGroupAttribute', + 'DefaultAttribute', + 'CommandAttribute', + 'ArgumentAttribute', + 'SwitchArgumentAttribute', + 'CommonArgumentAttribute', + 'CommonSwitchArgumentAttribute', + 'ArgParseMixin' +] +__all__ = __api__ + + class CommandGroupAttribute(Attribute): __groupName = "" diff --git a/py/lib/pyAttribute/__init__.py b/py/lib/pyAttribute/__init__.py index aceb75cf..c88a3f1c 100644 --- a/py/lib/pyAttribute/__init__.py +++ b/py/lib/pyAttribute/__init__.py @@ -36,6 +36,13 @@ # limitations under the License. # ============================================================================ # +__api__ = [ + 'Attribute', + 'AttributeHelperMixin' +] +__all__ = __api__ + + class Attribute: __AttributesMemberName__ = "__pyattr__" _debug = False diff --git a/sim/vSim.default.wdo b/sim/vSim.default.wdo index 4ed8a948..05fa26a6 100644 --- a/sim/vSim.default.wdo +++ b/sim/vSim.default.wdo @@ -1 +1 @@ -run -all +add wave * diff --git a/tools/ReadTheDocs/requirements.txt b/tools/ReadTheDocs/requirements.txt index 453cbc7e..1db5d19a 100644 --- a/tools/ReadTheDocs/requirements.txt +++ b/tools/ReadTheDocs/requirements.txt @@ -1,2 +1,3 @@ -r ../../requirements.txt sphinxcontrib-autoprogram>=0.1.3 +autoapi From 4ab5f4d3f8eca7e6bc9bd60d64d88511278c9fa4 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 12 Nov 2016 08:44:14 +0100 Subject: [PATCH 27/97] Added missing file. --- .gitignore | 7 +++++-- docs/PyInfrastructure/.gitempty | 0 docs/PyInfrastructure/index.rst | 31 +++++++++++++++++++++++++++++++ 3 files changed, 36 insertions(+), 2 deletions(-) create mode 100644 docs/PyInfrastructure/.gitempty create mode 100644 docs/PyInfrastructure/index.rst diff --git a/.gitignore b/.gitignore index 77c55071..d5cf93be 100644 --- a/.gitignore +++ b/.gitignore @@ -9,7 +9,11 @@ __pycache__ # ignore build directories -docs/_build/ +/docs/_build/ +/docs/PyInfrastructure/ +!/docs/PyInfrastructure/.gitempty +!/docs/PyInfrastructure/index.rst + # ignore files in netlist/ /netlist/ @@ -94,4 +98,3 @@ other/diamond/.spreadsheet_view.ini !.git* !.publish !README.md -docs/PyInfrastructure/ diff --git a/docs/PyInfrastructure/.gitempty b/docs/PyInfrastructure/.gitempty new file mode 100644 index 00000000..e69de29b diff --git a/docs/PyInfrastructure/index.rst b/docs/PyInfrastructure/index.rst new file mode 100644 index 00000000..3d4735ab --- /dev/null +++ b/docs/PyInfrastructure/index.rst @@ -0,0 +1,31 @@ + +Python Infrastructure +##################### + +Frontend Scripts +**************** + +.. toctree:: + + PoC + + +Packages and Modules +******************** + +.. toctree:: + + Base + Compiler + DataBase + Parser + Simulator + ToolChains + lib + +.. foobar + automodule:: PoC + :members: + :undoc-members: + :inherited-members: + :show-inheritance: From 3ab38d287e3ee8c8fd4acd4ba68b733f9a249052 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 12 Nov 2016 08:58:41 +0100 Subject: [PATCH 28/97] Added autoapi template. --- .gitignore | 2 +- docs/_templates/autoapi/module.rst | 142 +++++++++++++++++++++++++++++ 2 files changed, 143 insertions(+), 1 deletion(-) create mode 100644 docs/_templates/autoapi/module.rst diff --git a/.gitignore b/.gitignore index d5cf93be..0eca46e0 100644 --- a/.gitignore +++ b/.gitignore @@ -10,7 +10,7 @@ __pycache__ # ignore build directories /docs/_build/ -/docs/PyInfrastructure/ +/docs/PyInfrastructure/* !/docs/PyInfrastructure/.gitempty !/docs/PyInfrastructure/index.rst diff --git a/docs/_templates/autoapi/module.rst b/docs/_templates/autoapi/module.rst new file mode 100644 index 00000000..3df27f33 --- /dev/null +++ b/docs/_templates/autoapi/module.rst @@ -0,0 +1,142 @@ + +{{ node.name }} +=={{ '=' * node.name|length }}== + +.. automodule:: {{ node.name }} + + +{##} +{%- block modules -%} +{%- if subnodes %} + +----------------------------------- +{##} +**Submodules** + +.. toctree:: +{% for item in subnodes %} + {{ item.name }} +{%- endfor %} +{##} +{%- endif -%} +{%- endblock -%} +{##} +.. currentmodule:: {{ node.name }} +{##} + +----------------------------------- +{##} +{%- if node.variables %} +**Variables** +{##} +{% for item, obj in node.variables.items() -%} +- :py:data:`{{ item }}` +{% endfor -%} +{%- endif -%} + + +{%- if node.exceptions %} +{##} +**Exceptions** +{##} +{% for item, obj in node.exceptions.items() -%} +- :py:exc:`{{ item }}`: + {{ obj|summary }} + +{% endfor -%} +{%- endif -%} + + +{%- if node.classes %} +{##} +**Classes** +{##} +{% for item, obj in node.classes.items() -%} +- :py:class:`{{ item }}`: + {{ obj|summary }} + +{% endfor -%} +{%- endif -%} + + +{%- if node.functions %} +{##} +**Functions** +{##} +{% for item, obj in node.functions.items() -%} +- :py:func:`{{ item }}`: + {{ obj|summary }} + +{% endfor -%} +{%- endif -%} + + +{%- block variables -%} +{%- if node.variables %} +{% for item, obj in node.variables.items() %} +.. autodata:: {{ item }} + :annotation: + + .. code-block:: guess + + {{ obj|pprint|indent(6) }} +{##} +{%- endfor -%} +{%- endif -%} +{%- endblock -%} + + +{%- block exceptions -%} +{%- if node.exceptions %} + +----------------------------------- + +{% for item in node.exceptions %} +.. autoexception:: {{ item }} + :members: + :undoc-members: + + .. rubric:: Inheritance + .. inheritance-diagram:: {{ item }} + .. rubric:: Members + +{##} +{%- endfor -%} +{%- endif -%} +{%- endblock -%} + + +{%- block classes -%} +{%- if node.classes %} + +----------------------------------- + +{% for item in node.classes %} +.. autoclass:: {{ item }} + :members: + :undoc-members: + :inherited-members: + + .. rubric:: Inheritance + .. inheritance-diagram:: {{ item }} + .. rubric:: Members + +{##} +{%- endfor -%} +{%- endif -%} +{%- endblock -%} + + +{%- block functions -%} +{%- if node.functions %} + +----------------------------------- + +**Functions** + +{% for item in node.functions %} +.. autofunction:: {{ item }} +{##} +{%- endfor -%} +{%- endif -%} +{%- endblock -%} From b30cef1989a3b10f5f376bfb42789c95770091f7 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 12 Nov 2016 09:24:05 +0100 Subject: [PATCH 29/97] Minor changes. --- docs/PoCSphinx.py | 4 +- docs/PyInfrastructure/index.rst | 2 +- docs/_templates/autoapi/script.rst | 142 +++++++++++++++++++++++++++++ docs/conf.py | 16 ++-- py/PoC.py | 4 +- 5 files changed, 155 insertions(+), 13 deletions(-) create mode 100644 docs/_templates/autoapi/script.rst diff --git a/docs/PoCSphinx.py b/docs/PoCSphinx.py index 4600f848..0bdc0e5d 100644 --- a/docs/PoCSphinx.py +++ b/docs/PoCSphinx.py @@ -34,7 +34,7 @@ sys_path.append("../py") -from PoC import PoC +from PoC import PileOfCores # entry point -parser = PoC(False, False, False, True, sphinx=True).MainParser +parser = PileOfCores(False, False, False, True, sphinx=True).MainParser diff --git a/docs/PyInfrastructure/index.rst b/docs/PyInfrastructure/index.rst index 3d4735ab..dd684d4b 100644 --- a/docs/PyInfrastructure/index.rst +++ b/docs/PyInfrastructure/index.rst @@ -7,7 +7,7 @@ Frontend Scripts .. toctree:: - PoC + PoC.py Packages and Modules diff --git a/docs/_templates/autoapi/script.rst b/docs/_templates/autoapi/script.rst new file mode 100644 index 00000000..96efb43e --- /dev/null +++ b/docs/_templates/autoapi/script.rst @@ -0,0 +1,142 @@ + +{{ node.name }}.py +=={{ '=' * node.name|length }}== + +.. automodule:: {{ node.name }} + + +{##} +{%- block modules -%} +{%- if subnodes %} + +----------------------------------- +{##} +**Submodules** + +.. toctree:: +{% for item in subnodes %} + {{ item.name }} +{%- endfor %} +{##} +{%- endif -%} +{%- endblock -%} +{##} +.. currentmodule:: {{ node.name }} +{##} + +----------------------------------- +{##} +{%- if node.variables %} +**Variables** +{##} +{% for item, obj in node.variables.items() -%} +- :py:data:`{{ item }}` +{% endfor -%} +{%- endif -%} + + +{%- if node.exceptions %} +{##} +**Exceptions** +{##} +{% for item, obj in node.exceptions.items() -%} +- :py:exc:`{{ item }}`: + {{ obj|summary }} + +{% endfor -%} +{%- endif -%} + + +{%- if node.classes %} +{##} +**Classes** +{##} +{% for item, obj in node.classes.items() -%} +- :py:class:`{{ item }}`: + {{ obj|summary }} + +{% endfor -%} +{%- endif -%} + + +{%- if node.functions %} +{##} +**Functions** +{##} +{% for item, obj in node.functions.items() -%} +- :py:func:`{{ item }}`: + {{ obj|summary }} + +{% endfor -%} +{%- endif -%} + + +{%- block variables -%} +{%- if node.variables %} +{% for item, obj in node.variables.items() %} +.. autodata:: {{ item }} + :annotation: + + .. code-block:: guess + + {{ obj|pprint|indent(6) }} +{##} +{%- endfor -%} +{%- endif -%} +{%- endblock -%} + + +{%- block exceptions -%} +{%- if node.exceptions %} + +----------------------------------- + +{% for item in node.exceptions %} +.. autoexception:: {{ item }} + :members: + :undoc-members: + + .. rubric:: Inheritance + .. inheritance-diagram:: {{ item }} + .. rubric:: Members + +{##} +{%- endfor -%} +{%- endif -%} +{%- endblock -%} + + +{%- block classes -%} +{%- if node.classes %} + +----------------------------------- + +{% for item in node.classes %} +.. autoclass:: {{ item }} + :members: + :undoc-members: + :inherited-members: + + .. rubric:: Inheritance + .. inheritance-diagram:: {{ item }} + .. rubric:: Members + +{##} +{%- endfor -%} +{%- endif -%} +{%- endblock -%} + + +{%- block functions -%} +{%- if node.functions %} + +----------------------------------- + +**Functions** + +{% for item in node.functions %} +.. autofunction:: {{ item }} +{##} +{%- endfor -%} +{%- endif -%} +{%- endblock -%} diff --git a/docs/conf.py b/docs/conf.py index 8662d695..3de4dc2c 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -51,14 +51,14 @@ # Extract Python documentation and generate ReST files. autoapi_modules = { - 'PoC': {'output': 'PyInfrastructure'}, - 'Base': {'output': 'PyInfrastructure'}, - 'Compiler': {'output': 'PyInfrastructure'}, - 'DataBase': {'output': 'PyInfrastructure'}, - 'Parser': {'output': 'PyInfrastructure'}, - 'Simulator': {'output': 'PyInfrastructure'}, - 'ToolChains': {'output': 'PyInfrastructure'}, - 'lib': {'output': 'PyInfrastructure'} + 'PoC': {'output': "PyInfrastructure", 'template': "script"}, + 'Base': {'output': "PyInfrastructure"}, + 'Compiler': {'output': "PyInfrastructure"}, + 'DataBase': {'output': "PyInfrastructure"}, + 'Parser': {'output': "PyInfrastructure"}, + 'Simulator': {'output': "PyInfrastructure"}, + 'ToolChains': {'output': "PyInfrastructure"}, + 'lib': {'output': "PyInfrastructure"} } # Add any paths that contain templates here, relative to this directory. diff --git a/py/PoC.py b/py/PoC.py index f18330d8..fa895ef1 100644 --- a/py/PoC.py +++ b/py/PoC.py @@ -126,7 +126,7 @@ def __call__(self, func): return func -class PoC(ILogable, ArgParseMixin): +class PileOfCores(ILogable, ArgParseMixin): HeadLine = "The PoC-Library - Service Tool" # configure hard coded variables here @@ -1149,7 +1149,7 @@ def main(): # mccabe:disable=MC0001 try: Init.init() # handover to a class instance - poc = PoC(debug, verbose, quiet, dryRun) + poc = PileOfCores(debug, verbose, quiet, dryRun) poc.Run() Exit.exit() From 0e952856ff94c7082c494691280474ec17113902 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 12 Nov 2016 21:25:35 +0100 Subject: [PATCH 30/97] Raised Landscape strictness. Extract documentation version number from latest Git tag. --- .landscape.yml | 3 ++- docs/PyInfrastructure/index.rst | 2 +- docs/conf.py | 33 +++++++++++++++++++++++++++------ 3 files changed, 30 insertions(+), 8 deletions(-) diff --git a/.landscape.yml b/.landscape.yml index 45d79860..a546f410 100644 --- a/.landscape.yml +++ b/.landscape.yml @@ -5,7 +5,7 @@ python-targets: # - py-flags # doc-warnings: yes test-warnings: no -strictness: medium +strictness: high max-line-length: 180 pylint: disable: @@ -30,6 +30,7 @@ ignore-paths: - sim - src # - tb +- tcl - temp # - tools - ucf diff --git a/docs/PyInfrastructure/index.rst b/docs/PyInfrastructure/index.rst index dd684d4b..3d4735ab 100644 --- a/docs/PyInfrastructure/index.rst +++ b/docs/PyInfrastructure/index.rst @@ -7,7 +7,7 @@ Frontend Scripts .. toctree:: - PoC.py + PoC Packages and Modules diff --git a/docs/conf.py b/docs/conf.py index 3de4dc2c..c23e1d50 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -16,6 +16,8 @@ import sys import os +from subprocess import check_output + # If extensions (or modules to document with autodoc) are in another directory, # add these directories to sys.path here. If the directory is relative to the # documentation root, use os.path.abspath to make it absolute, like shown here. @@ -83,11 +85,29 @@ # The version info for the project you're documenting, acts as replacement for # |version| and |release|, also used in various other places throughout the # built documents. -# -# The short X.Y version. -version = '1.1' -# The full version, including alpha/beta/rc tags. -release = '1.1.0' + +def _IsUnderGitControl(): + return (check_output(["git", "rev-parse", "--is-inside-work-tree"], universal_newlines=True).strip() == "true") + +def _LatestTagHash(): + return check_output(["git", "rev-list", "--tags", "--max-count=1"], universal_newlines=True).strip() + +def _LatestTagName(latestTagHash): + return check_output(["git", "describe", "--tags", latestTagHash], universal_newlines=True).strip() + +version = "1.1" # The short X.Y version. +release = "1.1.0" # The full version, including alpha/beta/rc tags. +try: + if _IsUnderGitControl: + latestTagName = _LatestTagName(_LatestTagHash())[1:] # remove prefix "v" + versionParts = latestTagName.split("-")[0].split(".") + + version = ".".join(versionParts[:2]) + release = latestTagName # ".".join(versionParts[:3]) + print(version) + print(release) +except: + pass # The language for content autogenerated by Sphinx. Refer to documentation # for a list of supported languages. @@ -330,5 +350,6 @@ # Example configuration for intersphinx: refer to the Python standard library. intersphinx_mapping = { - 'python': ('http://docs.python.org/3.5/', None) + 'python': ('http://docs.python.org/3.5/', None), + 'ghdl': ('https://ghdl.readthedocs.io/en/latest/', None) } From 75a9585abef60622251b3aa0652bf59219e80d93 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 13 Nov 2016 03:02:52 +0100 Subject: [PATCH 31/97] Changed Sphinx settings. --- .../Compile-Altera-ps1.rst | 0 .../Compile-Altera-sh.rst | 0 .../Compile-Lattice-ps1.rst | 0 .../Compile-Lattice-sh.rst | 0 .../Compile-OSVVM-ps1.rst | 0 .../Compile-OSVVM-sh.rst | 0 docs/References/CmdRefs/Compile-UVVM-ps1.rst | 30 ++++++++++++ docs/References/CmdRefs/Compile-UVVM-sh.rst | 30 ++++++++++++ .../Compile-Xilinx-ISE-ps1.rst | 0 .../Compile-Xilinx-ISE-sh.rst | 0 .../Compile-Xilinx-Vivado-ps1.rst | 0 .../Compile-Xilinx-Vivado-sh.rst | 0 docs/References/CmdRefs/PoC-py.rst | 5 ++ docs/References/CommandReference.rst | 49 ++++++++++++++----- docs/References/index.rst | 2 - docs/_templates/autoapi/module.rst | 13 ++--- docs/_templates/autoapi/script.rst | 13 ++--- docs/conf.py | 10 ++-- docs/index.rst | 3 +- py/Base/Compiler.py | 10 ++-- py/Base/Shared.py | 21 +++++++- py/Base/Simulator.py | 11 ++++- py/PoC.py | 2 +- py/lib/Parser.py | 4 +- py/lib/pyAttribute/__init__.py | 6 ++- 25 files changed, 165 insertions(+), 44 deletions(-) rename docs/References/{CmdRefs-PreCompile => CmdRefs}/Compile-Altera-ps1.rst (100%) rename docs/References/{CmdRefs-PreCompile => CmdRefs}/Compile-Altera-sh.rst (100%) rename docs/References/{CmdRefs-PreCompile => CmdRefs}/Compile-Lattice-ps1.rst (100%) rename docs/References/{CmdRefs-PreCompile => CmdRefs}/Compile-Lattice-sh.rst (100%) rename docs/References/{CmdRefs-PreCompile => CmdRefs}/Compile-OSVVM-ps1.rst (100%) rename docs/References/{CmdRefs-PreCompile => CmdRefs}/Compile-OSVVM-sh.rst (100%) create mode 100644 docs/References/CmdRefs/Compile-UVVM-ps1.rst create mode 100644 docs/References/CmdRefs/Compile-UVVM-sh.rst rename docs/References/{CmdRefs-PreCompile => CmdRefs}/Compile-Xilinx-ISE-ps1.rst (100%) rename docs/References/{CmdRefs-PreCompile => CmdRefs}/Compile-Xilinx-ISE-sh.rst (100%) rename docs/References/{CmdRefs-PreCompile => CmdRefs}/Compile-Xilinx-Vivado-ps1.rst (100%) rename docs/References/{CmdRefs-PreCompile => CmdRefs}/Compile-Xilinx-Vivado-sh.rst (100%) create mode 100644 docs/References/CmdRefs/PoC-py.rst diff --git a/docs/References/CmdRefs-PreCompile/Compile-Altera-ps1.rst b/docs/References/CmdRefs/Compile-Altera-ps1.rst similarity index 100% rename from docs/References/CmdRefs-PreCompile/Compile-Altera-ps1.rst rename to docs/References/CmdRefs/Compile-Altera-ps1.rst diff --git a/docs/References/CmdRefs-PreCompile/Compile-Altera-sh.rst b/docs/References/CmdRefs/Compile-Altera-sh.rst similarity index 100% rename from docs/References/CmdRefs-PreCompile/Compile-Altera-sh.rst rename to docs/References/CmdRefs/Compile-Altera-sh.rst diff --git a/docs/References/CmdRefs-PreCompile/Compile-Lattice-ps1.rst b/docs/References/CmdRefs/Compile-Lattice-ps1.rst similarity index 100% rename from docs/References/CmdRefs-PreCompile/Compile-Lattice-ps1.rst rename to docs/References/CmdRefs/Compile-Lattice-ps1.rst diff --git a/docs/References/CmdRefs-PreCompile/Compile-Lattice-sh.rst b/docs/References/CmdRefs/Compile-Lattice-sh.rst similarity index 100% rename from docs/References/CmdRefs-PreCompile/Compile-Lattice-sh.rst rename to docs/References/CmdRefs/Compile-Lattice-sh.rst diff --git a/docs/References/CmdRefs-PreCompile/Compile-OSVVM-ps1.rst b/docs/References/CmdRefs/Compile-OSVVM-ps1.rst similarity index 100% rename from docs/References/CmdRefs-PreCompile/Compile-OSVVM-ps1.rst rename to docs/References/CmdRefs/Compile-OSVVM-ps1.rst diff --git a/docs/References/CmdRefs-PreCompile/Compile-OSVVM-sh.rst b/docs/References/CmdRefs/Compile-OSVVM-sh.rst similarity index 100% rename from docs/References/CmdRefs-PreCompile/Compile-OSVVM-sh.rst rename to docs/References/CmdRefs/Compile-OSVVM-sh.rst diff --git a/docs/References/CmdRefs/Compile-UVVM-ps1.rst b/docs/References/CmdRefs/Compile-UVVM-ps1.rst new file mode 100644 index 00000000..6666ee36 --- /dev/null +++ b/docs/References/CmdRefs/Compile-UVVM-ps1.rst @@ -0,0 +1,30 @@ +compile-uvvm.ps1 +---------------- + +.. option:: -Help + + Show the embedded help page(s). + +.. option:: -Clean + + Clean up directory before analyzing. + +.. option:: -All + + Pre-compile all libraries and packages for all simulators. + +.. option:: -GHDL + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: -Questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + +.. option:: -VHDL93 + + Set VHDL Standard to '93. + +.. option:: -VHDL2008 + + Set VHDL Standard to '08. diff --git a/docs/References/CmdRefs/Compile-UVVM-sh.rst b/docs/References/CmdRefs/Compile-UVVM-sh.rst new file mode 100644 index 00000000..35cac02f --- /dev/null +++ b/docs/References/CmdRefs/Compile-UVVM-sh.rst @@ -0,0 +1,30 @@ +compile-uvvm.sh +--------------- + +.. option:: --help + + Show the embedded help page(s). + +.. option:: --clean + + Clean up directory before analyzing. + +.. option:: --all + + Pre-compile all libraries and packages for all simulators. + +.. option:: --ghdl + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: --questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + +.. option:: --vhdl93 + + Set VHDL Standard to '93. + +.. option:: --vhdl2008 + + Set VHDL Standard to '08. diff --git a/docs/References/CmdRefs-PreCompile/Compile-Xilinx-ISE-ps1.rst b/docs/References/CmdRefs/Compile-Xilinx-ISE-ps1.rst similarity index 100% rename from docs/References/CmdRefs-PreCompile/Compile-Xilinx-ISE-ps1.rst rename to docs/References/CmdRefs/Compile-Xilinx-ISE-ps1.rst diff --git a/docs/References/CmdRefs-PreCompile/Compile-Xilinx-ISE-sh.rst b/docs/References/CmdRefs/Compile-Xilinx-ISE-sh.rst similarity index 100% rename from docs/References/CmdRefs-PreCompile/Compile-Xilinx-ISE-sh.rst rename to docs/References/CmdRefs/Compile-Xilinx-ISE-sh.rst diff --git a/docs/References/CmdRefs-PreCompile/Compile-Xilinx-Vivado-ps1.rst b/docs/References/CmdRefs/Compile-Xilinx-Vivado-ps1.rst similarity index 100% rename from docs/References/CmdRefs-PreCompile/Compile-Xilinx-Vivado-ps1.rst rename to docs/References/CmdRefs/Compile-Xilinx-Vivado-ps1.rst diff --git a/docs/References/CmdRefs-PreCompile/Compile-Xilinx-Vivado-sh.rst b/docs/References/CmdRefs/Compile-Xilinx-Vivado-sh.rst similarity index 100% rename from docs/References/CmdRefs-PreCompile/Compile-Xilinx-Vivado-sh.rst rename to docs/References/CmdRefs/Compile-Xilinx-Vivado-sh.rst diff --git a/docs/References/CmdRefs/PoC-py.rst b/docs/References/CmdRefs/PoC-py.rst new file mode 100644 index 00000000..d1f2943e --- /dev/null +++ b/docs/References/CmdRefs/PoC-py.rst @@ -0,0 +1,5 @@ +.. This files requires a Python module called 'PoCSphinx' to be located in the + docs root folder. It expects a variable 'parser' of type ArgumentParser. + +.. autoprogram:: PoCSphinx:parser + :prog: PoC.py diff --git a/docs/References/CommandReference.rst b/docs/References/CommandReference.rst index fd3d0361..e7466e77 100644 --- a/docs/References/CommandReference.rst +++ b/docs/References/CommandReference.rst @@ -4,8 +4,24 @@ Command Reference .. contents:: Contents of this Page -.. autoprogram:: PoCSphinx:parser - :prog: PoC.py +PoC Wrapper Scripts +******************* + +poc.ps1 +======== + + + +poc.sh +====== + + +PoC Main Program +**************** + +.. toctree:: + + CmdRefs/PoC-py Pre-compile Scripts @@ -16,8 +32,8 @@ Pre-compile Altera Libraries .. toctree:: - CmdRefs-PreCompile/Compile-Altera-ps1 - CmdRefs-PreCompile/Compile-Altera-sh + CmdRefs/Compile-Altera-ps1 + CmdRefs/Compile-Altera-sh Pre-compile Lattice Libraries @@ -25,8 +41,8 @@ Pre-compile Lattice Libraries .. toctree:: - CmdRefs-PreCompile/Compile-Lattice-ps1 - CmdRefs-PreCompile/Compile-Lattice-sh + CmdRefs/Compile-Lattice-ps1 + CmdRefs/Compile-Lattice-sh Pre-compile OSVVM Libraries @@ -34,8 +50,17 @@ Pre-compile OSVVM Libraries .. toctree:: - CmdRefs-PreCompile/Compile-OSVVM-ps1 - CmdRefs-PreCompile/Compile-OSVVM-sh + CmdRefs/Compile-OSVVM-ps1 + CmdRefs/Compile-OSVVM-sh + + +Pre-compile UVVM Libraries +========================== + +.. toctree:: + + CmdRefs/Compile-UVVM-ps1 + CmdRefs/Compile-UVVM-sh Pre-compile Xilinx ISE Libraries @@ -44,8 +69,8 @@ Pre-compile Xilinx ISE Libraries .. toctree:: - CmdRefs-PreCompile/Compile-Xilinx-ISE-ps1 - CmdRefs-PreCompile/Compile-Xilinx-ISE-sh + CmdRefs/Compile-Xilinx-ISE-ps1 + CmdRefs/Compile-Xilinx-ISE-sh Pre-compile Xilinx Vivado Libraries @@ -53,5 +78,5 @@ Pre-compile Xilinx Vivado Libraries .. toctree:: - CmdRefs-PreCompile/Compile-Xilinx-Vivado-ps1 - CmdRefs-PreCompile/Compile-Xilinx-Vivado-sh + CmdRefs/Compile-Xilinx-Vivado-ps1 + CmdRefs/Compile-Xilinx-Vivado-sh diff --git a/docs/References/index.rst b/docs/References/index.rst index 66868e83..e31d6fa9 100644 --- a/docs/References/index.rst +++ b/docs/References/index.rst @@ -5,12 +5,10 @@ References .. toctree:: :maxdepth: 1 - Interfaces/index NamingConventions CommandReference Database WrapperScriptHookFiles - PythonInfrastructure FileFormats/index ListOfDevices ListOfBoards diff --git a/docs/_templates/autoapi/module.rst b/docs/_templates/autoapi/module.rst index 3df27f33..7f070eb8 100644 --- a/docs/_templates/autoapi/module.rst +++ b/docs/_templates/autoapi/module.rst @@ -95,11 +95,11 @@ .. autoexception:: {{ item }} :members: :undoc-members: - +{##} .. rubric:: Inheritance .. inheritance-diagram:: {{ item }} - .. rubric:: Members - +{##} + .. rubric:: Members {##} {%- endfor -%} {%- endif -%} @@ -114,13 +114,14 @@ {% for item in node.classes %} .. autoclass:: {{ item }} :members: + :private-members: :undoc-members: :inherited-members: - +{##} .. rubric:: Inheritance .. inheritance-diagram:: {{ item }} - .. rubric:: Members - +{##} + .. rubric:: Members {##} {%- endfor -%} {%- endif -%} diff --git a/docs/_templates/autoapi/script.rst b/docs/_templates/autoapi/script.rst index 96efb43e..4ed46196 100644 --- a/docs/_templates/autoapi/script.rst +++ b/docs/_templates/autoapi/script.rst @@ -95,11 +95,11 @@ .. autoexception:: {{ item }} :members: :undoc-members: - +{##} .. rubric:: Inheritance .. inheritance-diagram:: {{ item }} - .. rubric:: Members - +{##} + .. rubric:: Members {##} {%- endfor -%} {%- endif -%} @@ -114,13 +114,14 @@ {% for item in node.classes %} .. autoclass:: {{ item }} :members: + :private-members: :undoc-members: :inherited-members: - +{##} .. rubric:: Inheritance .. inheritance-diagram:: {{ item }} - .. rubric:: Members - +{##} + .. rubric:: Members {##} {%- endfor -%} {%- endif -%} diff --git a/docs/conf.py b/docs/conf.py index c23e1d50..0e413808 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -35,8 +35,8 @@ # ones. extensions = [ 'sphinx.ext.autodoc', - 'sphinx.ext.inheritance_diagram', 'sphinx.ext.intersphinx', + 'sphinx.ext.inheritance_diagram', 'sphinx.ext.todo', # 'sphinx.ext.coverage', 'sphinx.ext.mathjax', @@ -51,6 +51,8 @@ if (not (tags.has('PoCExternal') or tags.has('PoCInternal'))): tags.add('PoCExternal') +autodoc_member_order = "bysource" + # Extract Python documentation and generate ReST files. autoapi_modules = { 'PoC': {'output': "PyInfrastructure", 'template': "script"}, @@ -104,8 +106,6 @@ def _LatestTagName(latestTagHash): version = ".".join(versionParts[:2]) release = latestTagName # ".".join(versionParts[:3]) - print(version) - print(release) except: pass @@ -350,6 +350,6 @@ def _LatestTagName(latestTagHash): # Example configuration for intersphinx: refer to the Python standard library. intersphinx_mapping = { - 'python': ('http://docs.python.org/3.5/', None), - 'ghdl': ('https://ghdl.readthedocs.io/en/latest/', None) + 'python': ('https://docs.python.org/3.5/', None), + 'ghdl': ('http://ghdl.readthedocs.io/en/latest', None) } diff --git a/docs/index.rst b/docs/index.rst index 9aa83841..81eb808a 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -63,6 +63,7 @@ At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergr sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + Cite the PoC-Library ******************** @@ -87,7 +88,6 @@ following `biblatex `_ entry to cite us: WhatIsPoC/index QuickStart - UsingPoC/index GetInvolved/index References/Licenses/License @@ -95,6 +95,7 @@ following `biblatex `_ entry to cite us: :caption: Main Documentation :hidden: + UsingPoC/index Interfaces/index IPCores/index Miscelaneous/ThirdParty diff --git a/py/Base/Compiler.py b/py/Base/Compiler.py index 65d06794..db23b1a0 100644 --- a/py/Base/Compiler.py +++ b/py/Base/Compiler.py @@ -124,12 +124,12 @@ class Compiler(Shared): """ Base class for all Compiler classes. - :param host: The hosting instance for this instance. - :type host: object - :param dryRun: Enable dry-run mode - :type dryRun: bool + :type host: object + :param host: The hosting instance for this instance. + :type dryRun: bool + :param dryRun: Enable dry-run mode + :type noCleanUp: bool :param noCleanUp: Don't clean up after a run. - :type noCleanUp: bool """ _ENVIRONMENT = Environment.Synthesis diff --git a/py/Base/Shared.py b/py/Base/Shared.py index c56d6081..58e2f486 100644 --- a/py/Base/Shared.py +++ b/py/Base/Shared.py @@ -52,13 +52,32 @@ # local helper function def to_time(seconds): - """Convert n seconds to a str with pattern {min}:{sec:02}.""" + """ + Convert *n* seconds to a :py:class:`str` with this pattern: "{min}:{sec:02}". + + :type seconds: int + :param seconds: Number of seconds to be converted. + :rtype: str + :return: Returns a string formatted as #:##. E.g. "1:05" + """ + minutes = int(seconds / 60) seconds = seconds - (minutes * 60) return "{min}:{sec:02}".format(min=minutes, sec=seconds) class Shared(ILogable): + """ + Base class for Simulator and Compiler. + + :type host: object + :param host: The hosting instance for this instance. + :type dryRun: bool + :param dryRun: Enable dry-run mode + :type noCleanUp: bool + :param noCleanUp: Don't clean up after a run. + """ + _ENVIRONMENT = Environment.Any _TOOL_CHAIN = ToolChain.Any _TOOL = Tool.Any diff --git a/py/Base/Simulator.py b/py/Base/Simulator.py index 3fc38dbf..837c0955 100644 --- a/py/Base/Simulator.py +++ b/py/Base/Simulator.py @@ -96,7 +96,16 @@ class SimulationResult(Enum): class Simulator(Shared): - """Base class for all Simulator classes.""" + """ + Base class for all Simulator classes. + + :type host: object + :param host: The hosting instance for this instance. + :type dryRun: bool + :param dryRun: Enable dry-run mode + :type noCleanUp: bool + :param noCleanUp: Don't clean up after a run. + """ _ENVIRONMENT = Environment.Simulation _vhdlVersion = VHDLVersion.VHDL2008 diff --git a/py/PoC.py b/py/PoC.py index fa895ef1..8543acac 100644 --- a/py/PoC.py +++ b/py/PoC.py @@ -1132,7 +1132,7 @@ def main(): # mccabe:disable=MC0001 """ This is the entry point for PoC.py written as a function. - 1. It extracts common flags from the script's arguments list, before :py:class:`argparse.ArgumentParser` is fully loaded. + 1. It extracts common flags from the script's arguments list, before :py:class:`~argparse.ArgumentParser` is fully loaded. 2. It initializes colorama for colored outputs 3. It creates an instance of PoC and hands over to class based execution. All is wrapped in a big ``try..except`` block to catch every unhandled exception. 4. Shutdown the script and return its exit code. diff --git a/py/lib/Parser.py b/py/lib/Parser.py index caae13e8..c3522b45 100644 --- a/py/lib/Parser.py +++ b/py/lib/Parser.py @@ -194,8 +194,8 @@ class TokenKind(Enum): DelimiterChars = 3 OtherChars = 4 - @classmethod - def GetCharacterTokenizer(cls, iterable): + @staticmethod + def GetCharacterTokenizer(iterable): previousToken = None absolute = 0 column = 0 diff --git a/py/lib/pyAttribute/__init__.py b/py/lib/pyAttribute/__init__.py index c88a3f1c..76973ca0 100644 --- a/py/lib/pyAttribute/__init__.py +++ b/py/lib/pyAttribute/__init__.py @@ -92,14 +92,16 @@ def GetMethods(self): if hasattr(func, '__dict__') }.items() - def HasAttribute(self, method): + @staticmethod + def HasAttribute(method): if (Attribute.__AttributesMemberName__ in method.__dict__): attributeList = method.__dict__[Attribute.__AttributesMemberName__] return (isinstance(attributeList, list) and (len(attributeList) != 0)) else: return False - def GetAttributes(self, method): + @staticmethod + def GetAttributes(method): if (Attribute.__AttributesMemberName__ in method.__dict__): attributeList = method.__dict__[Attribute.__AttributesMemberName__] if isinstance(attributeList, list): From 71586e5ec4326bb36d4b062c437b8e0e13da2391 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 13 Nov 2016 03:42:48 +0100 Subject: [PATCH 32/97] Documented UVVM as a third party library. --- lib/README.md | 47 ++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 38 insertions(+), 9 deletions(-) diff --git a/lib/README.md b/lib/README.md index 844ff8b2..4022ea59 100644 --- a/lib/README.md +++ b/lib/README.md @@ -57,6 +57,35 @@ Source: [https://github.com/JimLewis/OSVVM][21] [21]: https://github.com/JimLewis/OSVVM +## Universal VHDL Verification Methodology (UVVM) + +**Folder:** `\lib\uvvm\` +**Copyright:** Copyright © 2016 by [Bitvis AS](http://bitvis.no/) +**License:** [The MIT License (MIT)](UVVM MIT.md) + +The Open Source **UVVM (Universal VHDL Verification Methodology) - VVC (VHDL +Verification Component) Framework** for making structured VHDL testbenches +for verification of FPGA. UVVM consists currently of: Utility Library, VVC +Framework and Verification IPs (VIP) for various protocols. + +**For what do I need this VVC Framework?** +The VVC Framework is a VHDL Verification Component system that allows multiple +interfaces on a DUT to be stimulated/handled simultaneously in a very +structured manner, and controlled by a very simple to understand software like +a test sequencer. VVC Framework is unique as an open source VHDL approach to +building a structured testbench architecture using Verification components and +a simple protocol to access these. As an example a simple command like +`uart_expect(UART_VVCT, my_data)`, or `axilite_write(AXILITE_VVCT, my_addr, my_data, my_message)` +will automatically tell the respective VVC (for UART or AXI-Lite) to execute the +`uart_receive()` or `axilite_write()` BFM respectively. + +Website: [http://bitvis.no/][30] +Source: [https://github.com/UVVM/UVVM_All][31] + + [30]: http://bitvis.no/ + [31]: https://github.com/UVVM/UVVM_All + + ## VUnit **Folder:** `\lib\vunit\` @@ -69,11 +98,11 @@ needed to realize continuous and automated testing of your VHDL code. VUnit doesn't replace but rather complements traditional testing methodologies by supporting a "test early and often" approach through automation. -Website: [https://vunit.github.io/][30] -Source: [https://github.com/VUnit/vunit][31] +Website: [https://vunit.github.io/][40] +Source: [https://github.com/VUnit/vunit][41] - [30]: https://vunit.github.io/ - [31]: https://github.com/VUnit/vunit + [40]: https://vunit.github.io/ + [41]: https://github.com/VUnit/vunit ## Xillybus @@ -82,13 +111,13 @@ Source: [https://github.com/VUnit/vunit][31] **Copyright:** TODO **License:** TODO, see [local copy](Xillybus License.md) -[xillybus][40] TODO +[xillybus][50] TODO -Documentation: [http://xillybus.com][40] -Source: [http://xillybus.com][41] +Documentation: [http://xillybus.com][50] +Source: [http://xillybus.com][51] - [40]: http://xillybus.com - [41]: http://xillybus.com + [50]: http://xillybus.com + [51]: http://xillybus.com [PAL2.0]: http://www.perlfoundation.org/artistic_license_2_0 From 1e9abcf10bc0fc90b16d86680b3fcba1d971b35b Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 13 Nov 2016 03:59:07 +0100 Subject: [PATCH 33/97] Added license file. --- docs/Miscelaneous/ThirdParty.rst | 33 +++++++++++ .../References/Licenses/BSDLicense_Cocotb.rst | 4 +- docs/References/Licenses/MIT_UVVM.rst | 31 ++++++++++ docs/References/Licenses/index.rst | 1 + lib/README.md | 2 +- lib/UVVM.files | 58 +++++++++++++++++++ 6 files changed, 126 insertions(+), 3 deletions(-) create mode 100644 docs/References/Licenses/MIT_UVVM.rst create mode 100644 lib/UVVM.files diff --git a/docs/Miscelaneous/ThirdParty.rst b/docs/Miscelaneous/ThirdParty.rst index b5b6caf5..100c6429 100644 --- a/docs/Miscelaneous/ThirdParty.rst +++ b/docs/Miscelaneous/ThirdParty.rst @@ -49,6 +49,39 @@ existing testbench or testbench models. +----------------+---------------------------------------------------------------------------------------+ + +UVVM +**** + +The Open Source **UVVM (Universal VHDL Verification Methodology) - VVC (VHDL +Verification Component) Framework** for making structured VHDL testbenches for +verification of FPGA. UVVM consists currently of: Utility Library, VVC +Framework and Verification IPs (VIP) for various protocols. + +**For what do I need this VVC Framework?** |br| +The VVC Framework is a VHDL Verification Component system that allows multiple +interfaces on a DUT to be stimulated/handled simultaneously in a very structured +manner, and controlled by a very simple to understand software like a test +sequencer. VVC Framework is unique as an open source VHDL approach to building +a structured testbench architecture using Verification components and a simple +protocol to access these. As an example a simple command like +``uart_expect(UART_VVCT, my_data)``, or ``axilite_write(AXILITE_VVCT, my_addr, my_data, my_message)`` +will automatically tell the respective VVC (for UART or AXI-Lite) to execute +the ``uart_receive()`` or ``axilite_write()`` BFM respectively. + ++----------------+---------------------------------------------------------------------------------------+ +| **Folder:** | ``\lib\uvvm\`` | ++----------------+---------------------------------------------------------------------------------------+ +| **Copyright:** | Copyright © 2016 by `Bitvis AS `_ | ++----------------+---------------------------------------------------------------------------------------+ +| **License:** | :doc:`The MIT License (local copy) ` | ++----------------+---------------------------------------------------------------------------------------+ +| **Website:** | `http://bitvis.no/ `_ | ++----------------+---------------------------------------------------------------------------------------+ +| **Source:** | `https://github.com/UVVM/UVVM_All `_ | ++----------------+---------------------------------------------------------------------------------------+ + + VUnit ***** diff --git a/docs/References/Licenses/BSDLicense_Cocotb.rst b/docs/References/Licenses/BSDLicense_Cocotb.rst index 17eda5c8..f9c4389c 100644 --- a/docs/References/Licenses/BSDLicense_Cocotb.rst +++ b/docs/References/Licenses/BSDLicense_Cocotb.rst @@ -12,8 +12,8 @@ BSD License for Cocotb Cocotb is licensed under the Revised BSD License. Full license text below. -**Copyright (c) 2013 Potential Ventures Ltd** |br| -**Copyright (c) 2013 SolarFlare Communications Inc** |br| +**Copyright © 2013 Potential Ventures Ltd** |br| +**Copyright © 2013 SolarFlare Communications Inc** |br| **All rights reserved.** Redistribution and use in source and binary forms, with or without diff --git a/docs/References/Licenses/MIT_UVVM.rst b/docs/References/Licenses/MIT_UVVM.rst new file mode 100644 index 00000000..a4ce5d5d --- /dev/null +++ b/docs/References/Licenses/MIT_UVVM.rst @@ -0,0 +1,31 @@ +.. Note:: + This is a local copy of `The MIT License (MIT) `_ + used in the UVVM library. The original can be found in file :file:`LICENSE` in the + UVVM_All source tree. + +.. TODO:: Check link to the lib/uvvm/LICENSE file. + +-------------------------------------------------------------------------------- + +The MIT License (MIT) +##################### + +**Copyright © 2016 by Bitvis AS** + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/docs/References/Licenses/index.rst b/docs/References/Licenses/index.rst index d648002d..4ca99541 100644 --- a/docs/References/Licenses/index.rst +++ b/docs/References/Licenses/index.rst @@ -15,6 +15,7 @@ which contains a link to the orginal license file source. CCLA ArtisticLicense2.0 BSDLicense_Cocotb + MIT_UVVM MozillaPublicLicense2.0 .. rubric:: Footnotes diff --git a/lib/README.md b/lib/README.md index 4022ea59..318597cb 100644 --- a/lib/README.md +++ b/lib/README.md @@ -61,7 +61,7 @@ Source: [https://github.com/JimLewis/OSVVM][21] **Folder:** `\lib\uvvm\` **Copyright:** Copyright © 2016 by [Bitvis AS](http://bitvis.no/) -**License:** [The MIT License (MIT)](UVVM MIT.md) +**License:** [The MIT License (MIT)](MIT UVVM.md) The Open Source **UVVM (Universal VHDL Verification Methodology) - VVC (VHDL Verification Component) Framework** for making structured VHDL testbenches diff --git a/lib/UVVM.files b/lib/UVVM.files new file mode 100644 index 00000000..85912955 --- /dev/null +++ b/lib/UVVM.files @@ -0,0 +1,58 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# ============================================================================== +# Note: all files are relative to PoC root directory +# +path PreCompiled = ${CONFIG.DirectoryNames:PrecompiledFiles} +path UVVM_Directory = "uvvm" + +if (VHDLVersion < 2002) then + report "UVVM requires VHDL-2002." +elseif (VHDLVersion >= 2002) then + if (Tool = "GHDL") then + path GHDLPath = (PreCompiled / ${CONFIG.DirectoryNames:GHDLFiles}) + path UVVM_LibraryPath = (GHDLPath / UVVM_Directory) + if ?{(UVVM_LibraryPath / "uvvm_util/v08/uvvm_util-obj08.cf")} then + library uvvm_util UVVM_LibraryPath + end if + if ?{(UVVM_LibraryPath / "uvvm_vvc_framework/v08/uvvm_vvc_framework-obj08.cf")} then + library uvvm_vvc_framework UVVM_LibraryPath + end if + if ?{(UVVM_LibraryPath / "bitvis_vip_axilite/v08/bitvis_vip_axilite-obj08.cf")} then + library bitvis_vip_axilite UVVM_LibraryPath + end if + if ?{(UVVM_LibraryPath / "bitvis_vip_axistream/v08/bitvis_vip_axistream-obj08.cf")} then + library bitvis_vip_axistream UVVM_LibraryPath + end if + if ?{(UVVM_LibraryPath / "bitvis_vip_i2c/v08/bitvis_vip_i2c-obj08.cf")} then + library bitvis_vip_i2c UVVM_LibraryPath + end if + if ?{(UVVM_LibraryPath / "bitvis_vip_sbi/v08/bitvis_vip_sbi-obj08.cf")} then + library bitvis_vip_sbi UVVM_LibraryPath + end if + if ?{(UVVM_LibraryPath / "bitvis_vip_uart/v08/bitvis_vip_uart-obj08.cf")} then + library bitvis_vip_uart UVVM_LibraryPath + else + report "No precompiled UVVM libraries for GHDL found." + end if + elseif (Tool = "Mentor_vSim") then + path UVVM_LibraryPath = (PreCompiled / (${CONFIG.DirectoryNames:ModelSimFiles} / UVVM_Directory)) + if ?{UVVM_LibraryPath} then + library uvvm_util UVVM_LibraryPath + library uvvm_vvc_framework UVVM_LibraryPath + library bitvis_vip_axilite UVVM_LibraryPath + library bitvis_vip_axistream UVVM_LibraryPath + library bitvis_vip_i2c UVVM_LibraryPath + library bitvis_vip_sbi UVVM_LibraryPath + library bitvis_vip_uart UVVM_LibraryPath + else + report "No precompiled UVVM libraries for QuestaSim/ModelSim found." + end if + else + # TODO self-compile section? + # vhdl uvvm "lib/uvvm/NamePkg.vhd" # UVVM + end if +else + report "VHDL version not supported by UVVM." +end if From 3adcb226e27259e215791226beff6626e19ffea3 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 13 Nov 2016 04:06:41 +0100 Subject: [PATCH 34/97] Added UVVM as a Git submodule in lib/uvvm. --- .gitmodules | 3 +++ lib/uvvm | 1 + 2 files changed, 4 insertions(+) create mode 160000 lib/uvvm diff --git a/.gitmodules b/.gitmodules index 06b72da2..19e704da 100644 --- a/.gitmodules +++ b/.gitmodules @@ -10,3 +10,6 @@ [submodule "docs/_themes/sphinx_rtd_theme"] path = docs/_themes/sphinx_rtd_theme url = https://github.com/VLSI-EDA/sphinx_rtd_theme.git +[submodule "lib/uvvm"] + path = lib/uvvm + url = https://github.com/VLSI-EDA/UVVM_All.git diff --git a/lib/uvvm b/lib/uvvm new file mode 160000 index 00000000..0ce4f8fe --- /dev/null +++ b/lib/uvvm @@ -0,0 +1 @@ +Subproject commit 0ce4f8fe59d14d01ddc50f84fcda2fbb521ae633 From 060ca372600e9e8217508704f9904260ccf94624 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 13 Nov 2016 04:10:14 +0100 Subject: [PATCH 35/97] Fixed linebreaks in lib\README.md. --- lib/README.md | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/lib/README.md b/lib/README.md index 318597cb..b92d0aec 100644 --- a/lib/README.md +++ b/lib/README.md @@ -32,7 +32,7 @@ foreach($dir in (dir -Directory)) { Documentation: [http://cocotb.readthedocs.org/en/latest/index.html][10] Source: [https://github.com/potentialventures/cocotb][11] - [10]: http://cocotb.readthedocs.org/en/latest/index.html + [10]: http://cocotb.readthedocs.org/en/latest/index.html [11]: https://github.com/potentialventures/cocotb @@ -50,7 +50,7 @@ needed. With OSVVM you can add advanced verification methodologies to your current testbench without having to learn a new language or throw out your existing testbench or testbench models. -Website: [http://osvvm.org/][20] +Website: [http://osvvm.org/][20] Source: [https://github.com/JimLewis/OSVVM][21] [20]: http://osvvm.org/ @@ -79,7 +79,7 @@ a simple protocol to access these. As an example a simple command like will automatically tell the respective VVC (for UART or AXI-Lite) to execute the `uart_receive()` or `axilite_write()` BFM respectively. -Website: [http://bitvis.no/][30] +Website: [http://bitvis.no/][30] Source: [https://github.com/UVVM/UVVM_All][31] [30]: http://bitvis.no/ @@ -98,7 +98,7 @@ needed to realize continuous and automated testing of your VHDL code. VUnit doesn't replace but rather complements traditional testing methodologies by supporting a "test early and often" approach through automation. -Website: [https://vunit.github.io/][40] +Website: [https://vunit.github.io/][40] Source: [https://github.com/VUnit/vunit][41] [40]: https://vunit.github.io/ @@ -113,7 +113,7 @@ Source: [https://github.com/VUnit/vunit][41] [xillybus][50] TODO -Documentation: [http://xillybus.com][50] +Documentation: [http://xillybus.com][50] Source: [http://xillybus.com][51] [50]: http://xillybus.com From 1f4c55febb3f50efaad1fda9aa24e394a53c947b Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 13 Nov 2016 04:41:16 +0100 Subject: [PATCH 36/97] Added MIT license file. --- lib/MIT UVVM.md | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 lib/MIT UVVM.md diff --git a/lib/MIT UVVM.md b/lib/MIT UVVM.md new file mode 100644 index 00000000..85f7e4ad --- /dev/null +++ b/lib/MIT UVVM.md @@ -0,0 +1,21 @@ +# The MIT License (MIT) + +**Copyright © 2016 by Bitvis AS** + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. From 47a960019aa52adc0a57f90f77fb06e708bcf54d Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 13 Nov 2016 06:23:20 +0100 Subject: [PATCH 37/97] Added missing UVVM references. --- README.md | 7 +++++-- docs/QuickStart.rst | 2 ++ lib/README.md | 10 +++++----- 3 files changed, 12 insertions(+), 7 deletions(-) diff --git a/README.md b/README.md index ae1263ea..2ef66b28 100644 --- a/README.md +++ b/README.md @@ -85,7 +85,9 @@ Windows. See [Requirements][211] for further details. A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python. - [OS-VVM][2132] Open Source VHDL Verification Methodology. - - [VUnit][2133] + - [UVVM][2133] + Universal VHDL Verification Methodology. + - [VUnit][2134] An unit testing framework for VHDL. All dependencies are available as GitHub repositories and are linked to PoC as Git submodules into the @@ -93,7 +95,8 @@ All dependencies are available as GitHub repositories and are linked to PoC as G [2131]: https://github.com/potentialventures/cocotb [2132]: https://github.com/JimLewis/OSVVM -[2133]: https://github.com/VUnit/vunit +[2133]: https://github.com/UVVM/UVVM_All +[2134]: https://github.com/VUnit/vunit [201]: http://poc-library.readthedocs.io/en/latest/UsingPoC/index.html [202]: http://poc-library.readthedocs.io/ diff --git a/docs/QuickStart.rst b/docs/QuickStart.rst index 12f45cc1..0fbfd28e 100644 --- a/docs/QuickStart.rst +++ b/docs/QuickStart.rst @@ -43,6 +43,8 @@ See :doc:`/UsingPoC/Requirements` for further details. A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python. * `OS-VVM `_ |br| Open Source VHDL Verification Methodology. +* `UVVM `_ |br| + Universal VHDL Verification Methodology. * `VUnit `_ |br| An unit testing framework for VHDL. diff --git a/lib/README.md b/lib/README.md index b92d0aec..318597cb 100644 --- a/lib/README.md +++ b/lib/README.md @@ -32,7 +32,7 @@ foreach($dir in (dir -Directory)) { Documentation: [http://cocotb.readthedocs.org/en/latest/index.html][10] Source: [https://github.com/potentialventures/cocotb][11] - [10]: http://cocotb.readthedocs.org/en/latest/index.html + [10]: http://cocotb.readthedocs.org/en/latest/index.html [11]: https://github.com/potentialventures/cocotb @@ -50,7 +50,7 @@ needed. With OSVVM you can add advanced verification methodologies to your current testbench without having to learn a new language or throw out your existing testbench or testbench models. -Website: [http://osvvm.org/][20] +Website: [http://osvvm.org/][20] Source: [https://github.com/JimLewis/OSVVM][21] [20]: http://osvvm.org/ @@ -79,7 +79,7 @@ a simple protocol to access these. As an example a simple command like will automatically tell the respective VVC (for UART or AXI-Lite) to execute the `uart_receive()` or `axilite_write()` BFM respectively. -Website: [http://bitvis.no/][30] +Website: [http://bitvis.no/][30] Source: [https://github.com/UVVM/UVVM_All][31] [30]: http://bitvis.no/ @@ -98,7 +98,7 @@ needed to realize continuous and automated testing of your VHDL code. VUnit doesn't replace but rather complements traditional testing methodologies by supporting a "test early and often" approach through automation. -Website: [https://vunit.github.io/][40] +Website: [https://vunit.github.io/][40] Source: [https://github.com/VUnit/vunit][41] [40]: https://vunit.github.io/ @@ -113,7 +113,7 @@ Source: [https://github.com/VUnit/vunit][41] [xillybus][50] TODO -Documentation: [http://xillybus.com][50] +Documentation: [http://xillybus.com][50] Source: [http://xillybus.com][51] [50]: http://xillybus.com From 1ed20c83bd424a1fdfc6539d33e4b96400b733b4 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 17 Nov 2016 02:57:19 +0100 Subject: [PATCH 38/97] Changed documentation linking (uses ref instead of doc). Added sidebar with source code links in IP core descriptions. Documented pre-compile scripts. Added railroad diagrams for INI files. --- docs/GetInvolved/index.rst | 2 +- docs/IPCores/alt/index.rst | 5 +- docs/IPCores/arith/arith.pkg.rst | 26 +- docs/IPCores/arith/arith_addw.rst | 18 +- docs/IPCores/arith/arith_bcdcollect.rst | 18 +- docs/IPCores/arith/arith_carrychain_inc.rst | 18 +- docs/IPCores/arith/arith_convert_bin2bcd.rst | 18 +- docs/IPCores/arith/arith_counter_bcd.rst | 18 +- docs/IPCores/arith/arith_counter_free.rst | 18 +- docs/IPCores/arith/arith_counter_gray.rst | 18 +- docs/IPCores/arith/arith_counter_ring.rst | 18 +- docs/IPCores/arith/arith_div.rst | 18 +- docs/IPCores/arith/arith_firstone.rst | 18 +- docs/IPCores/arith/arith_muls_wide.rst | 18 +- docs/IPCores/arith/arith_prefix_and.rst | 18 +- docs/IPCores/arith/arith_prefix_or.rst | 18 +- docs/IPCores/arith/arith_prng.rst | 18 +- docs/IPCores/arith/arith_same.rst | 18 +- docs/IPCores/arith/arith_scaler.rst | 18 +- docs/IPCores/arith/arith_shifter_barrel.rst | 18 +- docs/IPCores/arith/arith_sqrt.rst | 18 +- docs/IPCores/arith/index.rst | 83 +- docs/IPCores/bus/bus_Arbiter.rst | 18 +- docs/IPCores/bus/index.rst | 20 +- docs/IPCores/bus/stream/index.rst | 19 +- docs/IPCores/bus/stream/stream_Buffer.rst | 20 +- docs/IPCores/bus/stream/stream_DeMux.rst | 18 +- .../bus/stream/stream_FrameGenerator.rst | 18 +- docs/IPCores/bus/stream/stream_Mirror.rst | 18 +- docs/IPCores/bus/stream/stream_Mux.rst | 18 +- docs/IPCores/bus/stream/stream_Sink.rst | 18 +- docs/IPCores/bus/stream/stream_Source.rst | 18 +- docs/IPCores/bus/wb/index.rst | 13 +- docs/IPCores/bus/wb/wb_fifo_adapter.rst | 18 +- docs/IPCores/bus/wb/wb_ocram.rst | 18 +- docs/IPCores/bus/wb/wb_uart_wrapper.rst | 22 +- docs/IPCores/cache/cache_par.rst | 18 +- .../cache/cache_replacement_policy.rst | 18 +- docs/IPCores/cache/cache_tagunit_par.rst | 18 +- docs/IPCores/cache/cache_tagunit_seq.rst | 18 +- docs/IPCores/cache/index.rst | 19 +- docs/IPCores/comm/comm_crc.rst | 18 +- docs/IPCores/comm/comm_scramble.rst | 18 +- docs/IPCores/comm/index.rst | 9 +- docs/IPCores/common/index.rst | 1 + docs/IPCores/fifo/fifo.pkg.rst | 17 +- docs/IPCores/fifo/fifo_cc_got.rst | 24 +- docs/IPCores/fifo/fifo_cc_got_tempgot.rst | 18 +- docs/IPCores/fifo/fifo_cc_got_tempput.rst | 18 +- docs/IPCores/fifo/fifo_dc_got_sm.rst | 18 +- docs/IPCores/fifo/fifo_glue.rst | 18 +- docs/IPCores/fifo/fifo_ic_assembly.rst | 18 +- docs/IPCores/fifo/fifo_ic_got.rst | 18 +- docs/IPCores/fifo/fifo_shift.rst | 18 +- docs/IPCores/fifo/index.rst | 44 +- docs/IPCores/index.rst | 31 +- docs/IPCores/io/ddrio/ddrio_in.rst | 18 +- docs/IPCores/io/ddrio/ddrio_inout.rst | 18 +- docs/IPCores/io/ddrio/ddrio_out.rst | 18 +- docs/IPCores/io/ddrio/index.rst | 17 +- docs/IPCores/io/iic/iic_BusController.rst | 20 +- docs/IPCores/io/iic/iic_Controller.rst | 20 +- .../IPCores/io/iic/iic_Controller_SFF8431.rst | 18 +- docs/IPCores/io/iic/iic_Switch_PCA9548A.rst | 18 +- docs/IPCores/io/iic/index.rst | 12 +- docs/IPCores/io/index.rst | 38 +- docs/IPCores/io/io.pkg.rst | 7 +- docs/IPCores/io/io_7SegmentMux_BCD.rst | 18 +- docs/IPCores/io/io_7SegmentMux_HEX.rst | 18 +- docs/IPCores/io/io_Debounce.rst | 18 +- docs/IPCores/io/io_FanControl.rst | 18 +- docs/IPCores/io/io_FrequencyCounter.rst | 18 +- docs/IPCores/io/io_GlitchFilter.rst | 18 +- docs/IPCores/io/io_KeyPadScanner.rst | 18 +- docs/IPCores/io/io_PulseWidthModulation.rst | 18 +- docs/IPCores/io/io_TimingCounter.rst | 18 +- docs/IPCores/io/jtag/index.rst | 6 +- docs/IPCores/io/lcd/index.rst | 14 +- docs/IPCores/io/lcd/lcd_LCDBuffer.rst | 18 +- docs/IPCores/io/lcd/lcd_LCDBusController.rst | 18 +- .../io/lcd/lcd_LCDController_KS0066U.rst | 18 +- docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst | 18 +- docs/IPCores/io/lcd/lcd_dotmatrix.rst | 18 +- docs/IPCores/io/mdio/index.rst | 12 +- docs/IPCores/io/mdio/mdio_Controller.rst | 18 +- docs/IPCores/io/mdio/mdio_IIC_Adapter.rst | 18 +- docs/IPCores/io/ow/index.rst | 10 +- docs/IPCores/io/pio/index.rst | 14 +- docs/IPCores/io/pio/pio_fifo_in.rst | 18 +- docs/IPCores/io/pio/pio_fifo_out.rst | 18 +- docs/IPCores/io/pio/pio_in.rst | 18 +- docs/IPCores/io/pio/pio_out.rst | 18 +- docs/IPCores/io/pmod/index.rst | 17 +- docs/IPCores/io/pmod/pmod_KYPD.rst | 18 +- docs/IPCores/io/pmod/pmod_SSD.rst | 18 +- docs/IPCores/io/pmod/pmod_USBUART.rst | 18 +- docs/IPCores/io/ps2/index.rst | 7 +- docs/IPCores/io/uart/index.rst | 21 +- docs/IPCores/io/uart/uart_bclk.rst | 18 +- docs/IPCores/io/uart/uart_fifo.rst | 18 +- docs/IPCores/io/uart/uart_ft245.rst | 18 +- docs/IPCores/io/uart/uart_rx.rst | 18 +- docs/IPCores/io/uart/uart_tx.rst | 18 +- docs/IPCores/io/vga/index.rst | 12 +- docs/IPCores/io/vga/vga_phy.rst | 18 +- docs/IPCores/io/vga/vga_phy_ch7301c.rst | 18 +- docs/IPCores/io/vga/vga_timing.rst | 18 +- .../ddr2/ddr2_mem2mig_adapter_Spartan6.rst | 22 +- docs/IPCores/mem/ddr2/index.rst | 11 +- .../mem/ddr3/ddr3_mem2mig_adapter_Series7.rst | 22 +- docs/IPCores/mem/ddr3/index.rst | 11 +- docs/IPCores/mem/index.rst | 37 +- docs/IPCores/mem/lut/index.rst | 9 +- docs/IPCores/mem/lut/lut_Sine.rst | 18 +- docs/IPCores/mem/mem.pkg.rst | 7 +- docs/IPCores/mem/ocram/index.rst | 21 +- docs/IPCores/mem/ocram/ocram_esdp.rst | 18 +- docs/IPCores/mem/ocram/ocram_sdp.rst | 18 +- docs/IPCores/mem/ocram/ocram_sp.rst | 18 +- docs/IPCores/mem/ocram/ocram_tdp.rst | 18 +- docs/IPCores/mem/ocrom/index.rst | 13 +- docs/IPCores/mem/ocrom/ocrom_dp.rst | 18 +- docs/IPCores/mem/ocrom/ocrom_sp.rst | 18 +- docs/IPCores/mem/sdram/index.rst | 31 +- docs/IPCores/mem/sdram/sdram_ctrl_de0.rst | 18 +- docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst | 18 +- docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst | 18 +- .../mem/sdram/sdram_ctrl_phy_s3esk.rst | 18 +- docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst | 18 +- docs/IPCores/misc/filter/filter_and.rst | 18 +- docs/IPCores/misc/filter/filter_mean.rst | 18 +- docs/IPCores/misc/filter/filter_or.rst | 18 +- docs/IPCores/misc/filter/index.rst | 17 +- docs/IPCores/misc/gearbox/gearbox_down_cc.rst | 18 +- docs/IPCores/misc/gearbox/gearbox_down_dc.rst | 18 +- docs/IPCores/misc/gearbox/gearbox_up_cc.rst | 18 +- docs/IPCores/misc/gearbox/gearbox_up_dc.rst | 18 +- docs/IPCores/misc/gearbox/index.rst | 21 +- docs/IPCores/misc/index.rst | 57 +- docs/IPCores/misc/misc.pkg.rst | 7 +- docs/IPCores/misc/misc_BitwidthConverter.rst | 18 +- docs/IPCores/misc/misc_ByteAligner.rst | 18 +- docs/IPCores/misc/misc_Delay.rst | 18 +- .../misc/misc_FrequencyMeasurement.rst | 18 +- docs/IPCores/misc/misc_PulseTrain.rst | 18 +- docs/IPCores/misc/misc_Sequencer.rst | 18 +- docs/IPCores/misc/misc_StrobeGenerator.rst | 18 +- docs/IPCores/misc/misc_StrobeLimiter.rst | 18 +- docs/IPCores/misc/misc_bit_lz.rst | 18 +- docs/IPCores/misc/stat/index.rst | 21 +- docs/IPCores/misc/stat/stat_Average.rst | 18 +- docs/IPCores/misc/stat/stat_Histogram.rst | 18 +- docs/IPCores/misc/stat/stat_Maximum.rst | 18 +- docs/IPCores/misc/stat/stat_Minimum.rst | 18 +- docs/IPCores/misc/sync/index.rst | 51 +- docs/IPCores/misc/sync/sync_Bits.rst | 26 +- docs/IPCores/misc/sync/sync_Command.rst | 18 +- docs/IPCores/misc/sync/sync_Pulse.rst | 26 +- docs/IPCores/misc/sync/sync_Reset.rst | 18 +- docs/IPCores/misc/sync/sync_Strobe.rst | 18 +- docs/IPCores/misc/sync/sync_Vector.rst | 18 +- .../net/arp/arp_BroadCast_Receiver.rst | 18 +- .../net/arp/arp_BroadCast_Requester.rst | 18 +- docs/IPCores/net/arp/arp_Cache.rst | 18 +- docs/IPCores/net/arp/arp_IPPool.rst | 18 +- docs/IPCores/net/arp/arp_Tester.rst | 18 +- docs/IPCores/net/arp/arp_UniCast_Receiver.rst | 18 +- .../IPCores/net/arp/arp_UniCast_Responder.rst | 18 +- docs/IPCores/net/arp/arp_Wrapper.rst | 18 +- docs/IPCores/net/arp/index.rst | 21 +- docs/IPCores/net/eth/eth_GEMAC_GMII.rst | 18 +- docs/IPCores/net/eth/eth_GEMAC_RX.rst | 18 +- docs/IPCores/net/eth/eth_GEMAC_TX.rst | 18 +- docs/IPCores/net/eth/eth_PHYController.rst | 18 +- .../eth/eth_PHYController_Marvell_88E1111.rst | 18 +- docs/IPCores/net/eth/eth_Wrapper.rst | 18 +- docs/IPCores/net/eth/index.rst | 17 +- docs/IPCores/net/icmpv4/icmpv4_RX.rst | 18 +- docs/IPCores/net/icmpv4/icmpv4_TX.rst | 18 +- docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst | 18 +- docs/IPCores/net/icmpv4/index.rst | 11 +- docs/IPCores/net/icmpv6/icmpv6_RX.rst | 18 +- docs/IPCores/net/icmpv6/icmpv6_TX.rst | 18 +- docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst | 18 +- docs/IPCores/net/icmpv6/index.rst | 11 +- docs/IPCores/net/index.rst | 58 +- docs/IPCores/net/ipv4/index.rst | 13 +- docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst | 18 +- docs/IPCores/net/ipv4/ipv4_RX.rst | 18 +- docs/IPCores/net/ipv4/ipv4_TX.rst | 18 +- docs/IPCores/net/ipv4/ipv4_Wrapper.rst | 18 +- docs/IPCores/net/ipv6/index.rst | 13 +- docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst | 18 +- docs/IPCores/net/ipv6/ipv6_RX.rst | 18 +- docs/IPCores/net/ipv6/ipv6_TX.rst | 18 +- docs/IPCores/net/ipv6/ipv6_Wrapper.rst | 18 +- docs/IPCores/net/mac/index.rst | 21 +- docs/IPCores/net/mac/mac_FrameLoopback.rst | 18 +- .../IPCores/net/mac/mac_RX_DestMAC_Switch.rst | 18 +- docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst | 18 +- docs/IPCores/net/mac/mac_RX_Type_Switch.rst | 18 +- .../net/mac/mac_TX_DestMAC_Prepender.rst | 18 +- .../net/mac/mac_TX_SrcMAC_Prepender.rst | 18 +- .../IPCores/net/mac/mac_TX_Type_Prepender.rst | 18 +- docs/IPCores/net/mac/mac_Wrapper.rst | 18 +- docs/IPCores/net/ndp/index.rst | 13 +- docs/IPCores/net/ndp/ndp_DestinationCache.rst | 18 +- docs/IPCores/net/ndp/ndp_FSMQuery.rst | 18 +- docs/IPCores/net/ndp/ndp_NeighborCache.rst | 18 +- docs/IPCores/net/ndp/ndp_Wrapper.rst | 18 +- docs/IPCores/net/net_FrameChecksum.rst | 18 +- docs/IPCores/net/net_FrameLoopback.rst | 18 +- .../net/net_FramePerformanceCounter.rst | 18 +- docs/IPCores/net/stack/index.rst | 15 +- docs/IPCores/net/stack/stack_UDPv4.rst | 18 +- docs/IPCores/net/udp/index.rst | 13 +- docs/IPCores/net/udp/udp_FrameLoopback.rst | 18 +- docs/IPCores/net/udp/udp_RX.rst | 18 +- docs/IPCores/net/udp/udp_TX.rst | 18 +- docs/IPCores/net/udp/udp_Wrapper.rst | 18 +- docs/IPCores/sim/index.rst | 1 + docs/IPCores/sort/index.rst | 29 +- docs/IPCores/sort/sort_ExpireList.rst | 18 +- docs/IPCores/sort/sort_InsertSort.rst | 18 +- .../IPCores/sort/sort_LeastFrequentlyUsed.rst | 18 +- docs/IPCores/sort/sort_lru_cache.rst | 18 +- docs/IPCores/sort/sort_lru_list.rst | 18 +- docs/IPCores/sort/sortnet/index.rst | 34 +- .../sort/sortnet/sortnet_BitonicSort.rst | 18 +- .../sortnet/sortnet_MergeSort_Streamed.rst | 18 +- .../sort/sortnet/sortnet_OddEvenMergeSort.rst | 18 +- .../sort/sortnet/sortnet_OddEvenSort.rst | 18 +- .../sort/sortnet/sortnet_Stream_Adapter.rst | 18 +- .../sort/sortnet/sortnet_Stream_Adapter2.rst | 18 +- .../sort/sortnet/sortnet_Transform.rst | 18 +- docs/IPCores/xil/index.rst | 54 +- docs/IPCores/xil/mig/index.rst | 13 +- docs/IPCores/xil/mig/mig_Atlys_1x128.rst | 1 + .../xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rst | 1 + docs/IPCores/xil/reconfig/index.rst | 13 +- .../xil/reconfig/reconfig_icap_fsm.rst | 18 +- .../xil/reconfig/reconfig_icap_wrapper.rst | 18 +- docs/IPCores/xil/xil_BSCAN.rst | 18 +- docs/IPCores/xil/xil_ChipScopeICON.rst | 18 +- docs/IPCores/xil/xil_DRP_BusMux.rst | 18 +- docs/IPCores/xil/xil_DRP_BusSync.rst | 18 +- docs/IPCores/xil/xil_ICAP.rst | 18 +- docs/IPCores/xil/xil_Reconfigurator.rst | 18 +- docs/IPCores/xil/xil_SystemMonitor.rst | 18 +- .../IPCores/xil/xil_SystemMonitor_Series7.rst | 18 +- .../IPCores/xil/xil_SystemMonitor_Virtex6.rst | 18 +- docs/Interfaces/CommandStatusError.rst | 5 +- docs/Interfaces/FIFO.rst | 7 + docs/Interfaces/Memory.rst | 5 +- docs/Interfaces/Stream.rst | 5 +- docs/Interfaces/index.rst | 8 +- docs/Miscelaneous/ThirdParty.rst | 9 +- docs/QuickStart.rst | 25 +- .../References/CmdRefs/Compile-Altera-ps1.rst | 39 +- docs/References/CmdRefs/Compile-Altera-sh.rst | 39 +- .../CmdRefs/Compile-Lattice-ps1.rst | 39 +- .../References/CmdRefs/Compile-Lattice-sh.rst | 39 +- docs/References/CmdRefs/Compile-OSVVM-ps1.rst | 30 +- docs/References/CmdRefs/Compile-OSVVM-sh.rst | 28 +- docs/References/CmdRefs/Compile-UVVM-ps1.rst | 28 +- docs/References/CmdRefs/Compile-UVVM-sh.rst | 28 +- .../CmdRefs/Compile-Xilinx-ISE-ps1.rst | 40 +- .../CmdRefs/Compile-Xilinx-ISE-sh.rst | 41 +- .../CmdRefs/Compile-Xilinx-Vivado-ps1.rst | 42 +- .../CmdRefs/Compile-Xilinx-Vivado-sh.rst | 43 +- docs/References/CmdRefs/Compile.rst | 86 ++ .../CmdRefs/{PoC-py.rst => PoC.rst} | 9 + docs/References/CmdRefs/Wrapper.rst | 59 ++ docs/References/CommandReference.rst | 81 +- docs/References/Database.rst | 212 +++-- docs/References/FileFormats/FilesFormat.rst | 1 + docs/References/FileFormats/IniFormat.rst | 124 +++ docs/References/FileFormats/RulesFormat.rst | 1 + docs/References/FileFormats/index.rst | 2 + .../{CCLA.rst => ApacheLicense2.0_CCLA.rst} | 4 +- .../{ICLA.rst => ApacheLicense2.0_ICLA.rst} | 7 +- ...cense_Cocotb.rst => Cocotb_BSDLicense.rst} | 0 .../Licenses/{MIT_UVVM.rst => UVVM_MIT.rst} | 0 docs/References/Licenses/index.rst | 8 +- docs/References/NamingConventions.rst | 4 +- docs/References/index.rst | 16 - docs/UsingPoC/Simulation.rst | 15 + docs/_static/css/railroad-diagrams.css | 41 + docs/_static/javascript/railroad-diagrams.js | 893 ++++++++++++++++++ docs/conf.py | 35 +- docs/genindex.rst | 1 + docs/index.rst | 6 + docs/poc.py | 36 +- poc.ps1 | 6 +- py/Base/Compiler.py | 29 +- py/Base/Shared.py | 66 +- py/Base/Simulator.py | 90 +- py/PoC.py | 179 ++-- py/Simulator/ActiveHDLSimulator.py | 8 +- py/Simulator/CocotbSimulator.py | 8 +- py/Simulator/GHDLSimulator.py | 24 +- py/Simulator/ISESimulator.py | 8 +- py/Simulator/QuestaSimulator.py | 92 +- py/Simulator/VivadoSimulator.py | 18 +- py/ToolChains/Mentor/QuestaSim.py | 46 +- py/lib/Decorators.py | 9 + py/lib/ExtendedConfigParser/__init__.py | 4 +- sim/vSim.gui.tcl | 4 + src/bus/stream/stream_Buffer.vhdl | 2 +- src/fifo/fifo_cc_got.vhdl | 8 +- .../ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl | 4 +- .../ddr3/ddr3_mem2mig_adapter_Series7.vhdl | 4 +- src/misc/sync/sync_Bits.vhdl | 8 +- src/misc/sync/sync_Pulse.vhdl | 8 +- tools/precompile/precompile.psm1 | 2 +- 315 files changed, 6036 insertions(+), 1370 deletions(-) create mode 100644 docs/Interfaces/FIFO.rst create mode 100644 docs/References/CmdRefs/Compile.rst rename docs/References/CmdRefs/{PoC-py.rst => PoC.rst} (57%) create mode 100644 docs/References/CmdRefs/Wrapper.rst create mode 100644 docs/References/FileFormats/IniFormat.rst rename docs/References/Licenses/{CCLA.rst => ApacheLicense2.0_CCLA.rst} (98%) rename docs/References/Licenses/{ICLA.rst => ApacheLicense2.0_ICLA.rst} (97%) rename docs/References/Licenses/{BSDLicense_Cocotb.rst => Cocotb_BSDLicense.rst} (100%) rename docs/References/Licenses/{MIT_UVVM.rst => UVVM_MIT.rst} (100%) delete mode 100644 docs/References/index.rst create mode 100644 docs/_static/css/railroad-diagrams.css create mode 100644 docs/_static/javascript/railroad-diagrams.js diff --git a/docs/GetInvolved/index.rst b/docs/GetInvolved/index.rst index 8282d047..0eda9dec 100644 --- a/docs/GetInvolved/index.rst +++ b/docs/GetInvolved/index.rst @@ -67,7 +67,7 @@ Contributers License Agreement We require all contributers to sign a Contributor License Agreement (CLA). If you don't know whatfore a CLA is needed and how it prevents legal issues on both sides, read `this short blog `_ post.PoC -uses the :doc:`Apache Contributor License Agreement ` +uses the :doc:`Apache Contributor License Agreement ` to match the :doc:`Apache License 2.0 `. So to get started, `sign the Contributor License Agreement (CLA) `_ diff --git a/docs/IPCores/alt/index.rst b/docs/IPCores/alt/index.rst index a54a3239..c0752f3f 100644 --- a/docs/IPCores/alt/index.rst +++ b/docs/IPCores/alt/index.rst @@ -1,5 +1,6 @@ +.. _NS:alt: -alt -=== +PoC.alt +======== .. TODO:: This namespace is reserved for Altera specific entities. diff --git a/docs/IPCores/arith/arith.pkg.rst b/docs/IPCores/arith/arith.pkg.rst index 72c72851..80cc19ba 100644 --- a/docs/IPCores/arith/arith.pkg.rst +++ b/docs/IPCores/arith/arith.pkg.rst @@ -1,6 +1,7 @@ +.. _PKG:arith: -Package -======== +PoC.arith Package +================= This package holds all component declarations for this namespace. @@ -16,19 +17,18 @@ This package holds all component declarations for this namespace. .. rubric:: Exported Components -* :doc:`PoC.arith.addw ` +* :ref:`PoC.arith.addw ` * PoC.arith.carrychain_inc_xilinx -* :doc:`PoC.arith.counter_bcd ` -* :doc:`PoC.arith.counter_gray ` -* :doc:`PoC.arith.div ` -* :doc:`PoC.arith.firstone ` +* :ref:`PoC.arith.counter_bcd ` +* :ref:`PoC.arith.counter_gray ` +* :ref:`PoC.arith.div ` +* :ref:`PoC.arith.firstone ` * PoC.arith.inc_ovcy_xilinx -* :doc:`PoC.arith.muls_wide ` +* :ref:`PoC.arith.muls_wide ` * PoC.arith.prefix_and_xilinx * PoC.arith.prefix_or_xilinx -* :doc:`PoC.arith.prng ` -* :doc:`PoC.arith.same ` -* :doc:`PoC.arith.sqrt ` - -Source file: `arith/arith.pkg.vhdl `_ +* :ref:`PoC.arith.prng ` +* :ref:`PoC.arith.same ` +* :ref:`PoC.arith.sqrt ` +Source file: :pocsrc:`arith.pkg.vhdl ` diff --git a/docs/IPCores/arith/arith_addw.rst b/docs/IPCores/arith/arith_addw.rst index b96675bc..6642e8f0 100644 --- a/docs/IPCores/arith/arith_addw.rst +++ b/docs/IPCores/arith/arith_addw.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_addw.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_addw_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arith_addw: arith_addw ########## @@ -28,7 +43,6 @@ arith_addw :linenos: :lines: 53-70 -Source file: `arith/arith_addw.vhdl `_ - +Source file: :pocsrc:`arith/arith_addw.vhdl ` diff --git a/docs/IPCores/arith/arith_bcdcollect.rst b/docs/IPCores/arith/arith_bcdcollect.rst index 05298e28..6bb4df6a 100644 --- a/docs/IPCores/arith/arith_bcdcollect.rst +++ b/docs/IPCores/arith/arith_bcdcollect.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_bcdcollect.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_bcdcollect_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arith_bcdcollect: arith_bcdcollect ################ @@ -14,7 +29,6 @@ arith_bcdcollect :linenos: :lines: 37-55 -Source file: `arith/arith_bcdcollect.vhdl `_ - +Source file: :pocsrc:`arith/arith_bcdcollect.vhdl ` diff --git a/docs/IPCores/arith/arith_carrychain_inc.rst b/docs/IPCores/arith/arith_carrychain_inc.rst index c9cbaf9a..2ca932dd 100644 --- a/docs/IPCores/arith/arith_carrychain_inc.rst +++ b/docs/IPCores/arith/arith_carrychain_inc.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_carrychain_inc.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_carrychain_inc_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arith_carrychain_inc: arith_carrychain_inc #################### @@ -16,7 +31,6 @@ arith_carrychain_inc :linenos: :lines: 43-52 -Source file: `arith/arith_carrychain_inc.vhdl `_ - +Source file: :pocsrc:`arith/arith_carrychain_inc.vhdl ` diff --git a/docs/IPCores/arith/arith_convert_bin2bcd.rst b/docs/IPCores/arith/arith_convert_bin2bcd.rst index 01e101cc..622fc3d1 100644 --- a/docs/IPCores/arith/arith_convert_bin2bcd.rst +++ b/docs/IPCores/arith/arith_convert_bin2bcd.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_convert_bin2bcd.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_convert_bin2bcd_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arith_convert_bin2bcd: arith_convert_bin2bcd ##################### @@ -14,7 +29,6 @@ arith_convert_bin2bcd :linenos: :lines: 40-58 -Source file: `arith/arith_convert_bin2bcd.vhdl `_ - +Source file: :pocsrc:`arith/arith_convert_bin2bcd.vhdl ` diff --git a/docs/IPCores/arith/arith_counter_bcd.rst b/docs/IPCores/arith/arith_counter_bcd.rst index c41824ec..09f68656 100644 --- a/docs/IPCores/arith/arith_counter_bcd.rst +++ b/docs/IPCores/arith/arith_counter_bcd.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_counter_bcd.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_counter_bcd_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arith_counter_bcd: arith_counter_bcd ################# @@ -25,7 +40,6 @@ is specified by ``val(3 downto 0)``. :linenos: :lines: 51-61 -Source file: `arith/arith_counter_bcd.vhdl `_ - +Source file: :pocsrc:`arith/arith_counter_bcd.vhdl ` diff --git a/docs/IPCores/arith/arith_counter_free.rst b/docs/IPCores/arith/arith_counter_free.rst index b62a3526..7445fe4c 100644 --- a/docs/IPCores/arith/arith_counter_free.rst +++ b/docs/IPCores/arith/arith_counter_free.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_counter_free.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_counter_free_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arith_counter_free: arith_counter_free ################## @@ -21,7 +36,6 @@ input have been observed. :linenos: :lines: 41-53 -Source file: `arith/arith_counter_free.vhdl `_ - +Source file: :pocsrc:`arith/arith_counter_free.vhdl ` diff --git a/docs/IPCores/arith/arith_counter_gray.rst b/docs/IPCores/arith/arith_counter_gray.rst index af2e3fc5..d1ba293a 100644 --- a/docs/IPCores/arith/arith_counter_gray.rst +++ b/docs/IPCores/arith/arith_counter_gray.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_counter_gray.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_counter_gray_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arith_counter_gray: arith_counter_gray ################## @@ -14,7 +29,6 @@ arith_counter_gray :linenos: :lines: 38-51 -Source file: `arith/arith_counter_gray.vhdl `_ - +Source file: :pocsrc:`arith/arith_counter_gray.vhdl ` diff --git a/docs/IPCores/arith/arith_counter_ring.rst b/docs/IPCores/arith/arith_counter_ring.rst index 0a27c8c6..f036513c 100644 --- a/docs/IPCores/arith/arith_counter_ring.rst +++ b/docs/IPCores/arith/arith_counter_ring.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_counter_ring.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_counter_ring_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arith_counter_ring: arith_counter_ring ################## @@ -17,7 +32,6 @@ enabling ``INVERT_FEEDBACK``. The number of counter bits is configurable with :linenos: :lines: 41-54 -Source file: `arith/arith_counter_ring.vhdl `_ - +Source file: :pocsrc:`arith/arith_counter_ring.vhdl ` diff --git a/docs/IPCores/arith/arith_div.rst b/docs/IPCores/arith/arith_div.rst index aa2a1b0d..15d7da85 100644 --- a/docs/IPCores/arith/arith_div.rst +++ b/docs/IPCores/arith/arith_div.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_div.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_div_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arith_div: arith_div ######### @@ -18,7 +33,6 @@ outputs are undefined in this case. :linenos: :lines: 38-61 -Source file: `arith/arith_div.vhdl `_ - +Source file: :pocsrc:`arith/arith_div.vhdl ` diff --git a/docs/IPCores/arith/arith_firstone.rst b/docs/IPCores/arith/arith_firstone.rst index d5e5a5b3..09fa8dc1 100644 --- a/docs/IPCores/arith/arith_firstone.rst +++ b/docs/IPCores/arith/arith_firstone.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_firstone.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_firstone_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arith_firstone: arith_firstone ############## @@ -27,7 +42,6 @@ This implementation uses carry chains for wider implementations. :linenos: :lines: 50-61 -Source file: `arith/arith_firstone.vhdl `_ - +Source file: :pocsrc:`arith/arith_firstone.vhdl ` diff --git a/docs/IPCores/arith/arith_muls_wide.rst b/docs/IPCores/arith/arith_muls_wide.rst index 80bb5fb7..2e9b227d 100644 --- a/docs/IPCores/arith/arith_muls_wide.rst +++ b/docs/IPCores/arith/arith_muls_wide.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_muls_wide.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_muls_wide_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arith_muls_wide: arith_muls_wide ############### @@ -16,7 +31,6 @@ For detailed documentation see below. :linenos: :lines: 38-49 -Source file: `arith/arith_muls_wide.vhdl `_ - +Source file: :pocsrc:`arith/arith_muls_wide.vhdl ` diff --git a/docs/IPCores/arith/arith_prefix_and.rst b/docs/IPCores/arith/arith_prefix_and.rst index 8e939c2f..3aa6e5b2 100644 --- a/docs/IPCores/arith/arith_prefix_and.rst +++ b/docs/IPCores/arith/arith_prefix_and.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_prefix_and.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_prefix_and_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arith_prefix_and: arith_prefix_and ################ @@ -16,7 +31,6 @@ This implementation uses carry chains for wider implementations. :linenos: :lines: 43-51 -Source file: `arith/arith_prefix_and.vhdl `_ - +Source file: :pocsrc:`arith/arith_prefix_and.vhdl ` diff --git a/docs/IPCores/arith/arith_prefix_or.rst b/docs/IPCores/arith/arith_prefix_or.rst index 3c40904b..15ae0bf7 100644 --- a/docs/IPCores/arith/arith_prefix_or.rst +++ b/docs/IPCores/arith/arith_prefix_or.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_prefix_or.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_prefix_or_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arith_prefix_or: arith_prefix_or ############### @@ -16,7 +31,6 @@ This implementation uses carry chains for wider implementations. :linenos: :lines: 43-51 -Source file: `arith/arith_prefix_or.vhdl `_ - +Source file: :pocsrc:`arith/arith_prefix_or.vhdl ` diff --git a/docs/IPCores/arith/arith_prng.rst b/docs/IPCores/arith/arith_prng.rst index 4c56a7d2..715483e9 100644 --- a/docs/IPCores/arith/arith_prng.rst +++ b/docs/IPCores/arith/arith_prng.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_prng.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_prng_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arith_prng: arith_prng ########## @@ -20,7 +35,6 @@ The generated number sequence includes the value all-zeros, but not all-ones. :linenos: :lines: 46-57 -Source file: `arith/arith_prng.vhdl `_ - +Source file: :pocsrc:`arith/arith_prng.vhdl ` diff --git a/docs/IPCores/arith/arith_same.rst b/docs/IPCores/arith/arith_same.rst index 2a54dbc5..4c05faf9 100644 --- a/docs/IPCores/arith/arith_same.rst +++ b/docs/IPCores/arith/arith_same.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_same.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_same_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arith_same: arith_same ########## @@ -21,7 +36,6 @@ bit position as to avoid an undetected sign change between the slices. :linenos: :lines: 48-57 -Source file: `arith/arith_same.vhdl `_ - +Source file: :pocsrc:`arith/arith_same.vhdl ` diff --git a/docs/IPCores/arith/arith_scaler.rst b/docs/IPCores/arith/arith_scaler.rst index ab1d609d..54cb6370 100644 --- a/docs/IPCores/arith/arith_scaler.rst +++ b/docs/IPCores/arith/arith_scaler.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_scaler.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_scaler_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arith_scaler: arith_scaler ############ @@ -28,7 +43,6 @@ highest scaling ratio to be used in order to avoid a truncation overflow. :linenos: :lines: 52-69 -Source file: `arith/arith_scaler.vhdl `_ - +Source file: :pocsrc:`arith/arith_scaler.vhdl ` diff --git a/docs/IPCores/arith/arith_shifter_barrel.rst b/docs/IPCores/arith/arith_shifter_barrel.rst index 309c3295..85907d3d 100644 --- a/docs/IPCores/arith/arith_shifter_barrel.rst +++ b/docs/IPCores/arith/arith_shifter_barrel.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_shifter_barrel.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_shifter_barrel_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arith_shifter_barrel: arith_shifter_barrel #################### @@ -20,7 +35,6 @@ This is equivalent to the CPU instructions: SLL, SLA, SRL, SRA, RL, RR :linenos: :lines: 45-57 -Source file: `arith/arith_shifter_barrel.vhdl `_ - +Source file: :pocsrc:`arith/arith_shifter_barrel.vhdl ` diff --git a/docs/IPCores/arith/arith_sqrt.rst b/docs/IPCores/arith/arith_sqrt.rst index 8f3d9fb8..df23659e 100644 --- a/docs/IPCores/arith/arith_sqrt.rst +++ b/docs/IPCores/arith/arith_sqrt.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_sqrt.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_sqrt_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arith_sqrt: arith_sqrt ########## @@ -16,7 +31,6 @@ Its computation requires (N+1)/2 steps for an argument bit width of N. :linenos: :lines: 38-55 -Source file: `arith/arith_sqrt.vhdl `_ - +Source file: :pocsrc:`arith/arith_sqrt.vhdl ` diff --git a/docs/IPCores/arith/index.rst b/docs/IPCores/arith/index.rst index 786577f1..11da2e3a 100644 --- a/docs/IPCores/arith/index.rst +++ b/docs/IPCores/arith/index.rst @@ -1,52 +1,57 @@ -arith -===== +.. _NS:arith: + +PoC.arith +========= These are arithmetic entities.... **Package** -:doc:`PoC.arith ` +:ref:`PKG:arith` **Entities** - * :doc:`PoC.arith.addw ` - * :doc:`PoC.arith.carrychain_inc ` - * :doc:`PoC.arith.convert_bin2bcd ` - * :doc:`PoC.arith.counter_bcd ` - * :doc:`PoC.arith.counter_free ` - * :doc:`PoC.arith.counter_gray ` - * :doc:`PoC.arith.counter_ring ` - * :doc:`PoC.arith.div ` - * :doc:`PoC.arith.firstone ` - * :doc:`PoC.arith.muls_wide ` - * :doc:`PoC.arith.prefix_and ` - * :doc:`PoC.arith.prefix_or ` - * :doc:`PoC.arith.prng ` - * :doc:`PoC.arith.same ` - * :doc:`PoC.arith.scaler ` - * :doc:`PoC.arith.shifter_barrel ` - * :doc:`PoC.arith.sqrt ` + * :ref:`IP:arith_addw` + * :ref:`IP:arith_carrychain_inc` + * :ref:`IP:arith_convert_bin2bcd` + * :ref:`IP:arith_counter_bcd` + * :ref:`IP:arith_counter_free` + * :ref:`IP:arith_counter_gray` + * :ref:`IP:arith_counter_ring` + * :ref:`IP:arith_div` + * :ref:`IP:arith_firstone` + * :ref:`IP:arith_muls_wide` + * :ref:`IP:arith_prefix_and` + * :ref:`IP:arith_prefix_or` + * :ref:`IP:arith_prng` + * :ref:`IP:arith_same` + * :ref:`IP:arith_scaler` + * :ref:`IP:arith_shifter_barrel` + * :ref:`IP:arith_sqrt` + + +.. toctree:: + :hidden: + Package .. toctree:: :hidden: - arith.pkg - - arith_addw - arith_carrychain_inc - arith_convert_bin2bcd - arith_counter_bcd - arith_counter_free - arith_counter_gray - arith_counter_ring - arith_div - arith_firstone - arith_muls_wide - arith_prefix_and - arith_prefix_or - arith_prng - arith_same - arith_scaler - arith_shifter_barrel - arith_sqrt + arith_addw + arith_carrychain_inc + arith_convert_bin2bcd + arith_counter_bcd + arith_counter_free + arith_counter_gray + arith_counter_ring + arith_div + arith_firstone + arith_muls_wide + arith_prefix_and + arith_prefix_or + arith_prng + arith_same + arith_scaler + arith_shifter_barrel + arith_sqrt diff --git a/docs/IPCores/bus/bus_Arbiter.rst b/docs/IPCores/bus/bus_Arbiter.rst index 2fbef755..003969f9 100644 --- a/docs/IPCores/bus/bus_Arbiter.rst +++ b/docs/IPCores/bus/bus_Arbiter.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/bus_Arbiter.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/bus_Arbiter_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:bus_Arbiter: bus_Arbiter ########### @@ -17,7 +32,6 @@ following arbitration strategies: :linenos: :lines: 42-60 -Source file: `bus/bus_Arbiter.vhdl `_ - +Source file: :pocsrc:`bus/bus_Arbiter.vhdl ` diff --git a/docs/IPCores/bus/index.rst b/docs/IPCores/bus/index.rst index 911fe07b..ebda5e61 100644 --- a/docs/IPCores/bus/index.rst +++ b/docs/IPCores/bus/index.rst @@ -1,22 +1,26 @@ +.. _NS:bus: -bus -=== +PoC.bus +======== These are bus entities.... **Sub-namespaces** - * :doc:`PoC.bus.stream ` - * :doc:`PoC.bus.wb ` + * :ref:`NS:stream` + * :ref:`NS:wb` **Entities** - * :doc:`PoC.bus.Arbiter ` + * :ref:`IP:bus_Arbiter` .. toctree:: :hidden: - stream/index - wb/index + stream + wb - bus_Arbiter +.. toctree:: + :hidden: + + bus_Arbiter diff --git a/docs/IPCores/bus/stream/index.rst b/docs/IPCores/bus/stream/index.rst index 7d23fbf0..3199bcf7 100644 --- a/docs/IPCores/bus/stream/index.rst +++ b/docs/IPCores/bus/stream/index.rst @@ -1,15 +1,16 @@ +.. _NS:stream: -stream -^^^^^^ +PoC.bus.stream +============== PoC.Stream modules ... .. toctree:: - stream_Buffer - stream_DeMux - stream_Mux - stream_Mirror - stream_Sink - stream_Source - stream_FrameGenerator + stream_Buffer + stream_DeMux + stream_Mux + stream_Mirror + stream_Sink + stream_Source + stream_FrameGenerator diff --git a/docs/IPCores/bus/stream/stream_Buffer.rst b/docs/IPCores/bus/stream/stream_Buffer.rst index 0cab881a..a73a33c0 100644 --- a/docs/IPCores/bus/stream/stream_Buffer.rst +++ b/docs/IPCores/bus/stream/stream_Buffer.rst @@ -1,9 +1,24 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_Buffer.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_Buffer_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:stream_Buffer: stream_Buffer ############# This module implements a generic buffer (FIFO) for the -:doc:`PoC.Stream ` protocol. It is generic in +:doc:`PoC.Stream ` protocol. It is generic in ``DATA_BITS`` and in ``META_BITS`` as well as in FIFO depths for data and meta information. @@ -17,7 +32,6 @@ meta information. :linenos: :lines: 44-74 -Source file: `bus/stream/stream_Buffer.vhdl `_ - +Source file: :pocsrc:`bus/stream/stream_Buffer.vhdl ` diff --git a/docs/IPCores/bus/stream/stream_DeMux.rst b/docs/IPCores/bus/stream/stream_DeMux.rst index 4a75cdc4..4eac6ed5 100644 --- a/docs/IPCores/bus/stream/stream_DeMux.rst +++ b/docs/IPCores/bus/stream/stream_DeMux.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_DeMux.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_DeMux_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:stream_DeMux: stream_DeMux ############ @@ -14,7 +29,6 @@ stream_DeMux :linenos: :lines: 41-70 -Source file: `bus/stream/stream_DeMux.vhdl `_ - +Source file: :pocsrc:`bus/stream/stream_DeMux.vhdl ` diff --git a/docs/IPCores/bus/stream/stream_FrameGenerator.rst b/docs/IPCores/bus/stream/stream_FrameGenerator.rst index 83531c5d..bf090d02 100644 --- a/docs/IPCores/bus/stream/stream_FrameGenerator.rst +++ b/docs/IPCores/bus/stream/stream_FrameGenerator.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_FrameGenerator.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_FrameGenerator_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:stream_FrameGenerator: stream_FrameGenerator ##################### @@ -14,7 +29,6 @@ stream_FrameGenerator :linenos: :lines: 40-66 -Source file: `bus/stream/stream_FrameGenerator.vhdl `_ - +Source file: :pocsrc:`bus/stream/stream_FrameGenerator.vhdl ` diff --git a/docs/IPCores/bus/stream/stream_Mirror.rst b/docs/IPCores/bus/stream/stream_Mirror.rst index 166f44b3..bd7d529d 100644 --- a/docs/IPCores/bus/stream/stream_Mirror.rst +++ b/docs/IPCores/bus/stream/stream_Mirror.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_Mirror.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_Mirror_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:stream_Mirror: stream_Mirror ############# @@ -14,7 +29,6 @@ stream_Mirror :linenos: :lines: 41-70 -Source file: `bus/stream/stream_Mirror.vhdl `_ - +Source file: :pocsrc:`bus/stream/stream_Mirror.vhdl ` diff --git a/docs/IPCores/bus/stream/stream_Mux.rst b/docs/IPCores/bus/stream/stream_Mux.rst index 4f8f069b..3f7e407f 100644 --- a/docs/IPCores/bus/stream/stream_Mux.rst +++ b/docs/IPCores/bus/stream/stream_Mux.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_Mux.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_Mux_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:stream_Mux: stream_Mux ########## @@ -14,7 +29,6 @@ stream_Mux :linenos: :lines: 41-69 -Source file: `bus/stream/stream_Mux.vhdl `_ - +Source file: :pocsrc:`bus/stream/stream_Mux.vhdl ` diff --git a/docs/IPCores/bus/stream/stream_Sink.rst b/docs/IPCores/bus/stream/stream_Sink.rst index 718ef6c0..1188e3c5 100644 --- a/docs/IPCores/bus/stream/stream_Sink.rst +++ b/docs/IPCores/bus/stream/stream_Sink.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_Sink.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_Sink_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:stream_Sink: stream_Sink ########### @@ -14,7 +29,6 @@ stream_Sink :linenos: :lines: 42-59 -Source file: `bus/stream/stream_Sink.vhdl `_ - +Source file: :pocsrc:`bus/stream/stream_Sink.vhdl ` diff --git a/docs/IPCores/bus/stream/stream_Source.rst b/docs/IPCores/bus/stream/stream_Source.rst index 5f182b9b..a95529f5 100644 --- a/docs/IPCores/bus/stream/stream_Source.rst +++ b/docs/IPCores/bus/stream/stream_Source.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_Source.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_Source_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:stream_Source: stream_Source ############# @@ -14,7 +29,6 @@ stream_Source :linenos: :lines: 42-58 -Source file: `bus/stream/stream_Source.vhdl `_ - +Source file: :pocsrc:`bus/stream/stream_Source.vhdl ` diff --git a/docs/IPCores/bus/wb/index.rst b/docs/IPCores/bus/wb/index.rst index 1248d92b..9a68f5d4 100644 --- a/docs/IPCores/bus/wb/index.rst +++ b/docs/IPCores/bus/wb/index.rst @@ -1,12 +1,15 @@ +.. _NS:wb: -wb -^^ +PoC.bus.wb +========== WishBone modules ... **Entities:** .. toctree:: - wb_ocram - wb_fifo_adapter - wb_uart_wrapper + :hidden: + + wb_ocram + wb_fifo_adapter + wb_uart_wrapper diff --git a/docs/IPCores/bus/wb/wb_fifo_adapter.rst b/docs/IPCores/bus/wb/wb_fifo_adapter.rst index bbffb8e4..1b7de9cf 100644 --- a/docs/IPCores/bus/wb/wb_fifo_adapter.rst +++ b/docs/IPCores/bus/wb/wb_fifo_adapter.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/wb/wb_fifo_adapter.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/wb/wb_fifo_adapter_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:wb_fifo_adapter: wb_fifo_adapter ############### @@ -21,7 +36,6 @@ old comments: :linenos: :lines: 80-104 -Source file: `bus/wb/wb_fifo_adapter.vhdl `_ - +Source file: :pocsrc:`bus/wb/wb_fifo_adapter.vhdl ` diff --git a/docs/IPCores/bus/wb/wb_ocram.rst b/docs/IPCores/bus/wb/wb_ocram.rst index 89a2daf7..e9f18f9b 100644 --- a/docs/IPCores/bus/wb/wb_ocram.rst +++ b/docs/IPCores/bus/wb/wb_ocram.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/wb/wb_ocram.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/wb/wb_ocram_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:ocram_wb: ocram_wb ######## @@ -33,7 +48,6 @@ PIPE_STAGES = 2 :linenos: :lines: 54-80 -Source file: `bus/wb/wb_ocram.vhdl `_ - +Source file: :pocsrc:`bus/wb/wb_ocram.vhdl ` diff --git a/docs/IPCores/bus/wb/wb_uart_wrapper.rst b/docs/IPCores/bus/wb/wb_uart_wrapper.rst index 48e5bd7c..35cf954c 100644 --- a/docs/IPCores/bus/wb/wb_uart_wrapper.rst +++ b/docs/IPCores/bus/wb/wb_uart_wrapper.rst @@ -1,9 +1,24 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/wb/wb_uart_wrapper.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/wb/wb_uart_wrapper_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:uart_wb: uart_wb ####### -Wrapper module for :doc:`PoC.io.uart.rx ` and -:doc:`PoC.io.uart.tx ` to support the Wishbone +Wrapper module for :doc:`PoC.io.uart.rx ` and +:doc:`PoC.io.uart.tx ` to support the Wishbone interface. Synchronized reset is used. @@ -16,7 +31,6 @@ interface. Synchronized reset is used. :linenos: :lines: 40-69 -Source file: `bus/wb/wb_uart_wrapper.vhdl `_ - +Source file: :pocsrc:`bus/wb/wb_uart_wrapper.vhdl ` diff --git a/docs/IPCores/cache/cache_par.rst b/docs/IPCores/cache/cache_par.rst index 0ba198f5..d6e25481 100644 --- a/docs/IPCores/cache/cache_par.rst +++ b/docs/IPCores/cache/cache_par.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/cache/cache_par.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_par_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:cache_par: cache_par ######### @@ -49,7 +64,6 @@ both with a latency of one clock cycle. :linenos: :lines: 76-100 -Source file: `cache/cache_par.vhdl `_ - +Source file: :pocsrc:`cache/cache_par.vhdl ` diff --git a/docs/IPCores/cache/cache_replacement_policy.rst b/docs/IPCores/cache/cache_replacement_policy.rst index edd0530d..eb9dd1cd 100644 --- a/docs/IPCores/cache/cache_replacement_policy.rst +++ b/docs/IPCores/cache/cache_replacement_policy.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/cache/cache_replacement_policy.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_replacement_policy_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:cache_replacement_policy: cache_replacement_policy ######################## @@ -56,7 +71,6 @@ cache set (see above). :linenos: :lines: 85-104 -Source file: `cache/cache_replacement_policy.vhdl `_ - +Source file: :pocsrc:`cache/cache_replacement_policy.vhdl ` diff --git a/docs/IPCores/cache/cache_tagunit_par.rst b/docs/IPCores/cache/cache_tagunit_par.rst index 5f31022f..cf364399 100644 --- a/docs/IPCores/cache/cache_tagunit_par.rst +++ b/docs/IPCores/cache/cache_tagunit_par.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/cache/cache_tagunit_par.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_tagunit_par_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:cache_tagunit_par: cache_tagunit_par ################# @@ -49,7 +64,6 @@ must be a power of 2. :linenos: :lines: 75-99 -Source file: `cache/cache_tagunit_par.vhdl `_ - +Source file: :pocsrc:`cache/cache_tagunit_par.vhdl ` diff --git a/docs/IPCores/cache/cache_tagunit_seq.rst b/docs/IPCores/cache/cache_tagunit_seq.rst index 1268786c..7558fb8d 100644 --- a/docs/IPCores/cache/cache_tagunit_seq.rst +++ b/docs/IPCores/cache/cache_tagunit_seq.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/cache/cache_tagunit_seq.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_tagunit_seq_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:cache_tagunit_seq: cache_tagunit_seq ################# @@ -14,7 +29,6 @@ cache_tagunit_seq :linenos: :lines: 39-73 -Source file: `cache/cache_tagunit_seq.vhdl `_ - +Source file: :pocsrc:`cache/cache_tagunit_seq.vhdl ` diff --git a/docs/IPCores/cache/index.rst b/docs/IPCores/cache/index.rst index a49a74df..033ac76e 100644 --- a/docs/IPCores/cache/index.rst +++ b/docs/IPCores/cache/index.rst @@ -1,20 +1,21 @@ +.. _NS:cache: -cache -===== +PoC.cache +========= These are cache entities.... **Entities** - * :doc:`PoC.cache.par ` - * :doc:`PoC.cache.tagunit_par ` - * :doc:`PoC.cache.tagunit_seq ` + * :ref:`IP:cache_par` + * :ref:`IP:cache_tagunit_par` + * :ref:`IP:cache_tagunit_seq` .. toctree:: :hidden: - cache_par - cache_replacement_policy - cache_tagunit_par - cache_tagunit_seq + cache_par + cache_replacement_policy + cache_tagunit_par + cache_tagunit_seq diff --git a/docs/IPCores/comm/comm_crc.rst b/docs/IPCores/comm/comm_crc.rst index f50c7508..aa2d4499 100644 --- a/docs/IPCores/comm/comm_crc.rst +++ b/docs/IPCores/comm/comm_crc.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/comm/comm_crc.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/comm/comm_crc_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:comm_crc: comm_crc ######## @@ -20,7 +35,6 @@ processing width. :linenos: :lines: 45-64 -Source file: `comm/comm_crc.vhdl `_ - +Source file: :pocsrc:`comm/comm_crc.vhdl ` diff --git a/docs/IPCores/comm/comm_scramble.rst b/docs/IPCores/comm/comm_scramble.rst index 1a6d0c3d..b79def24 100644 --- a/docs/IPCores/comm/comm_scramble.rst +++ b/docs/IPCores/comm/comm_scramble.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/comm/comm_scramble.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/comm/comm_scramble_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:comm_scramble: comm_scramble ############# @@ -16,7 +31,6 @@ sequence is independent from the chosen output width. :linenos: :lines: 37-51 -Source file: `comm/comm_scramble.vhdl `_ - +Source file: :pocsrc:`comm/comm_scramble.vhdl ` diff --git a/docs/IPCores/comm/index.rst b/docs/IPCores/comm/index.rst index 5063c228..c6200649 100644 --- a/docs/IPCores/comm/index.rst +++ b/docs/IPCores/comm/index.rst @@ -1,10 +1,11 @@ +.. _NS:comm: -comm -==== +PoC.comm +======== These are communication entities.... .. toctree:: - comm_crc - comm_scramble + comm_crc + comm_scramble diff --git a/docs/IPCores/common/index.rst b/docs/IPCores/common/index.rst index e96eda89..ed575ec4 100644 --- a/docs/IPCores/common/index.rst +++ b/docs/IPCores/common/index.rst @@ -1,3 +1,4 @@ +.. _PKG_Common: Common Packages =============== diff --git a/docs/IPCores/fifo/fifo.pkg.rst b/docs/IPCores/fifo/fifo.pkg.rst index 967ddd16..ca9cb13b 100644 --- a/docs/IPCores/fifo/fifo.pkg.rst +++ b/docs/IPCores/fifo/fifo.pkg.rst @@ -1,7 +1,18 @@ +.. _PKG:fifo: -Package -======== +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo.pkg.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + + +PoC.fifo Package +================ This package holds all component declarations for this namespace. -Source file: `fifo/fifo.pkg.vhdl `_ +Source file: :pocsrc:`fifo.pkg.vhdl ` diff --git a/docs/IPCores/fifo/fifo_cc_got.rst b/docs/IPCores/fifo/fifo_cc_got.rst index da288a1c..ab1274ed 100644 --- a/docs/IPCores/fifo/fifo_cc_got.rst +++ b/docs/IPCores/fifo/fifo_cc_got.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_cc_got.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_cc_got_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:fifo_cc_got: fifo_cc_got ########### @@ -60,16 +75,15 @@ comparator (subtractor) in their path. :linenos: :lines: 98-124 -Source file: `fifo/fifo_cc_got.vhdl `_ +Source file: :pocsrc:`fifo/fifo_cc_got.vhdl ` .. seealso:: - :doc:`PoC.fifo.dc_got ` + :ref:`IP:fifo_dc_got` For a FIFO with dependent clocks. - :doc:`PoC.fifo.ic_got ` + :ref:`IP:fifo_ic_got` For a FIFO with independent clocks (cross-clock FIFO). - :doc:`PoC.fifo.glue ` + :ref:`IP:fifo_glue` For a minimal FIFO / pipeline decoupling. - diff --git a/docs/IPCores/fifo/fifo_cc_got_tempgot.rst b/docs/IPCores/fifo/fifo_cc_got_tempgot.rst index 7596e4a3..b9e0842a 100644 --- a/docs/IPCores/fifo/fifo_cc_got_tempgot.rst +++ b/docs/IPCores/fifo/fifo_cc_got_tempgot.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_cc_got_tempgot.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_cc_got_tempgot_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:fifo_cc_got_tempgot: fifo_cc_got_tempgot ################### @@ -55,7 +70,6 @@ comparator (subtractor) in their path. :linenos: :lines: 85-114 -Source file: `fifo/fifo_cc_got_tempgot.vhdl `_ - +Source file: :pocsrc:`fifo/fifo_cc_got_tempgot.vhdl ` diff --git a/docs/IPCores/fifo/fifo_cc_got_tempput.rst b/docs/IPCores/fifo/fifo_cc_got_tempput.rst index b94c840a..d6a8db8b 100644 --- a/docs/IPCores/fifo/fifo_cc_got_tempput.rst +++ b/docs/IPCores/fifo/fifo_cc_got_tempput.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_cc_got_tempput.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_cc_got_tempput_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:fifo_cc_got_tempput: fifo_cc_got_tempput ################### @@ -55,7 +70,6 @@ comparator (subtractor) in their path. :linenos: :lines: 85-114 -Source file: `fifo/fifo_cc_got_tempput.vhdl `_ - +Source file: :pocsrc:`fifo/fifo_cc_got_tempput.vhdl ` diff --git a/docs/IPCores/fifo/fifo_dc_got_sm.rst b/docs/IPCores/fifo/fifo_dc_got_sm.rst index 573c8d58..6c9a8af1 100644 --- a/docs/IPCores/fifo/fifo_dc_got_sm.rst +++ b/docs/IPCores/fifo/fifo_dc_got_sm.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_dc_got_sm.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_dc_got_sm_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:fifo_dc_got_sm: fifo_dc_got_sm ############## @@ -37,7 +52,6 @@ Synchronous reset is used. Both resets must overlap. :linenos: :lines: 62-85 -Source file: `fifo/fifo_dc_got_sm.vhdl `_ - +Source file: :pocsrc:`fifo/fifo_dc_got_sm.vhdl ` diff --git a/docs/IPCores/fifo/fifo_glue.rst b/docs/IPCores/fifo/fifo_glue.rst index 5ec75bcb..f90e3b89 100644 --- a/docs/IPCores/fifo/fifo_glue.rst +++ b/docs/IPCores/fifo/fifo_glue.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_glue.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_glue_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:fifo_glue: fifo_glue ######### @@ -16,7 +31,6 @@ the ``ful`` and the ``vld`` indicators to be driven by registers. :linenos: :lines: 36-55 -Source file: `fifo/fifo_glue.vhdl `_ - +Source file: :pocsrc:`fifo/fifo_glue.vhdl ` diff --git a/docs/IPCores/fifo/fifo_ic_assembly.rst b/docs/IPCores/fifo/fifo_ic_assembly.rst index 52c30ac4..18692d7b 100644 --- a/docs/IPCores/fifo/fifo_ic_assembly.rst +++ b/docs/IPCores/fifo/fifo_ic_assembly.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_ic_assembly.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_ic_assembly_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:fifo_ic_assembly: fifo_ic_assembly ################ @@ -25,7 +40,6 @@ the transmission of data blocks. This applies to many DMA implementations. :linenos: :lines: 45-78 -Source file: `fifo/fifo_ic_assembly.vhdl `_ - +Source file: :pocsrc:`fifo/fifo_ic_assembly.vhdl ` diff --git a/docs/IPCores/fifo/fifo_ic_got.rst b/docs/IPCores/fifo/fifo_ic_got.rst index 493f7940..dd35c6a1 100644 --- a/docs/IPCores/fifo/fifo_ic_got.rst +++ b/docs/IPCores/fifo/fifo_ic_got.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_ic_got.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_ic_got_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:fifo_ic_got: fifo_ic_got ########### @@ -49,7 +64,6 @@ Examples: :linenos: :lines: 77-103 -Source file: `fifo/fifo_ic_got.vhdl `_ - +Source file: :pocsrc:`fifo/fifo_ic_got.vhdl ` diff --git a/docs/IPCores/fifo/fifo_shift.rst b/docs/IPCores/fifo/fifo_shift.rst index eafbe1cb..52273eeb 100644 --- a/docs/IPCores/fifo/fifo_shift.rst +++ b/docs/IPCores/fifo/fifo_shift.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_shift.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_shift_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:fifo_shift: fifo_shift ########## @@ -20,7 +35,6 @@ The specified depth (``MIN_DEPTH``) is rounded up to the next suitable value. :linenos: :lines: 44-64 -Source file: `fifo/fifo_shift.vhdl `_ - +Source file: :pocsrc:`fifo/fifo_shift.vhdl ` diff --git a/docs/IPCores/fifo/index.rst b/docs/IPCores/fifo/index.rst index b05de404..27ee6f03 100644 --- a/docs/IPCores/fifo/index.rst +++ b/docs/IPCores/fifo/index.rst @@ -1,12 +1,13 @@ +.. _NS:fifo: -fifo -==== +PoC.fifo +======== The namespace `PoC.fifo` offers different :abbr:`FIFO (first-in, first-out)` implementations. **Package** -The package :doc:`PoC.fifo ` holds all component declarations for this namespace. +The package :ref:`NS:fifo` holds all component declarations for this namespace. **Entities** @@ -21,30 +22,33 @@ the current fill-state. The prefixes `cc_` (common clock), `dc_` (dependent clock) and `ic_` (independent clock) refer to the write- and read-side clock relationship. - * :doc:`PoC.fifo.cc_got ` implements a regular FIFO (one common clock, + * :ref:`IP:fifo_cc_got` implements a regular FIFO (one common clock, got-interface) - * :doc:`PoC.fifo.cc_got_tempgot ` implements a regular FIFO (one common - clock, got-interface), extended by a transactional `tempgot`-interface (read-side). - * :doc:`PoC.fifo.cc_got_tempput ` implements a regular FIFO (one common - clock, got-interface), extended by a transactional `tempput`-interface (write-side). - * :doc:`PoC.fifo.dc_got ` implements a cross-clock FIFO (two related clocks, + * :ref:`IP:fifo_cc_got_tempgot` implements a regular FIFO (one common clock, + got-interface), extended by a transactional `tempgot`-interface (read-side). + * :ref:`IP:fifo_cc_got_tempput` implements a regular FIFO (one common clock, + got-interface), extended by a transactional `tempput`-interface (write-side). + * :ref:`IP:fifo_dc_got` implements a cross-clock FIFO (two related clocks, got-interface) - * :doc:`PoC.fifo.ic_got ` implements a cross-clock FIFO (two independent clocks, + * :ref:`IP:fifo_ic_got` implements a cross-clock FIFO (two independent clocks, got-interface) - * :doc:`PoC.fifo.glue ` implements a two-stage FIFO (one common clock, + * :ref:`IP:fifo_glue` implements a two-stage FIFO (one common clock, got-interface) - * :doc:`PoC.fifo.shift ` implements a regular FIFO (one common clock, + * :ref:`IP:fifo_shift` implements a regular FIFO (one common clock, got-interface, optimized for FPGAs with shifter primitives) .. toctree:: :hidden: - fifo.pkg + Package - fifo_cc_got - fifo_cc_got_tempgot - fifo_cc_got_tempput - fifo_glue - fifo_ic_assembly - fifo_ic_got - fifo_shift +.. toctree:: + :hidden: + + fifo_cc_got + fifo_cc_got_tempgot + fifo_cc_got_tempput + fifo_glue + fifo_ic_assembly + fifo_ic_got + fifo_shift diff --git a/docs/IPCores/index.rst b/docs/IPCores/index.rst index 3b8755cf..4ecd9237 100644 --- a/docs/IPCores/index.rst +++ b/docs/IPCores/index.rst @@ -1,3 +1,4 @@ +.. _NS: IP Core Documentations ###################### @@ -6,23 +7,23 @@ Namespace for Packages: .. toctree:: - common/index - sim/index + common + sim Namespaces for Entities: .. toctree:: - alt/index - arith/index - bus/index - cache/index - comm/index - dstruct/index - fifo/index - io/index - mem/index - misc/index - net/index - sort/index - xil/index + alt + arith + bus + cache + comm + dstruct + fifo + io + mem + misc + net + sort + xil diff --git a/docs/IPCores/io/ddrio/ddrio_in.rst b/docs/IPCores/io/ddrio/ddrio_in.rst index 32f3b50b..7452bb86 100644 --- a/docs/IPCores/io/ddrio/ddrio_in.rst +++ b/docs/IPCores/io/ddrio/ddrio_in.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/ddrio/ddrio_in.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/ddrio/ddrio_in_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:ddrio_in: ddrio_in ######## @@ -36,7 +51,6 @@ IOBs. :linenos: :lines: 64-76 -Source file: `io/ddrio/ddrio_in.vhdl `_ - +Source file: :pocsrc:`io/ddrio/ddrio_in.vhdl ` diff --git a/docs/IPCores/io/ddrio/ddrio_inout.rst b/docs/IPCores/io/ddrio/ddrio_inout.rst index 95fd3698..0b215c6e 100644 --- a/docs/IPCores/io/ddrio/ddrio_inout.rst +++ b/docs/IPCores/io/ddrio/ddrio_inout.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/ddrio/ddrio_inout.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/ddrio/ddrio_inout_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:ddrio_inout: ddrio_inout ########### @@ -42,7 +57,6 @@ IOBs. :linenos: :lines: 70-88 -Source file: `io/ddrio/ddrio_inout.vhdl `_ - +Source file: :pocsrc:`io/ddrio/ddrio_inout.vhdl ` diff --git a/docs/IPCores/io/ddrio/ddrio_out.rst b/docs/IPCores/io/ddrio/ddrio_out.rst index 43c9fab6..b13dd7d9 100644 --- a/docs/IPCores/io/ddrio/ddrio_out.rst +++ b/docs/IPCores/io/ddrio/ddrio_out.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/ddrio/ddrio_out.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/ddrio/ddrio_out_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:ddrio_out: ddrio_out ######### @@ -29,7 +44,6 @@ IOBs. :linenos: :lines: 57-71 -Source file: `io/ddrio/ddrio_out.vhdl `_ - +Source file: :pocsrc:`io/ddrio/ddrio_out.vhdl ` diff --git a/docs/IPCores/io/ddrio/index.rst b/docs/IPCores/io/ddrio/index.rst index 0be35a42..d5ae070e 100644 --- a/docs/IPCores/io/ddrio/index.rst +++ b/docs/IPCores/io/ddrio/index.rst @@ -1,19 +1,20 @@ +.. _NS:ddrio: -ddrio -===== +PoC.io.ddrio +============ These are :abbr:`DDR-I/O (Double Data Rate - Input/Output)` entities.... **Entities** - * :doc:`PoC.io.ddrio.in ` - * :doc:`PoC.io.ddrio.inout ` - * :doc:`PoC.io.ddrio.out ` + * :ref:`IP:ddrio_in` + * :ref:`IP:ddrio_inout` + * :ref:`IP:ddrio_out` .. toctree:: :hidden: - ddrio_in - ddrio_inout - ddrio_out + ddrio_in + ddrio_inout + ddrio_out diff --git a/docs/IPCores/io/iic/iic_BusController.rst b/docs/IPCores/io/iic/iic_BusController.rst index 139e99e1..077f90d4 100644 --- a/docs/IPCores/io/iic/iic_BusController.rst +++ b/docs/IPCores/io/iic/iic_BusController.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/iic/iic_BusController.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/iic/iic_BusController_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:iic_BusController: iic_BusController ################# @@ -15,9 +30,8 @@ controller is compatible to the System Management Bus (SMBus). :language: vhdl :tab-width: 2 :linenos: - :lines: 47-70 - -Source file: `io/iic/iic_BusController.vhdl `_ + :lines: 47-65 +Source file: :pocsrc:`io/iic/iic_BusController.vhdl ` diff --git a/docs/IPCores/io/iic/iic_Controller.rst b/docs/IPCores/io/iic/iic_Controller.rst index 25ced5c3..efb868a1 100644 --- a/docs/IPCores/io/iic/iic_Controller.rst +++ b/docs/IPCores/io/iic/iic_Controller.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/iic/iic_Controller.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/iic/iic_Controller_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:iic_Controller: iic_Controller ############## @@ -15,9 +30,8 @@ is compatible to the System Management Bus (SMBus). :language: vhdl :tab-width: 2 :linenos: - :lines: 47-87 - -Source file: `io/iic/iic_Controller.vhdl `_ + :lines: 47-82 +Source file: :pocsrc:`io/iic/iic_Controller.vhdl ` diff --git a/docs/IPCores/io/iic/iic_Controller_SFF8431.rst b/docs/IPCores/io/iic/iic_Controller_SFF8431.rst index 87280961..85e82161 100644 --- a/docs/IPCores/io/iic/iic_Controller_SFF8431.rst +++ b/docs/IPCores/io/iic/iic_Controller_SFF8431.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/iic/iic_Controller_SFF8431.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/iic/iic_Controller_SFF8431_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:IICController_SFF8431: IICController_SFF8431 ##################### @@ -12,7 +27,6 @@ IICController_SFF8431 :linenos: :lines: 15-49 -Source file: `io/iic/iic_Controller_SFF8431.vhdl `_ - +Source file: :pocsrc:`io/iic/iic_Controller_SFF8431.vhdl ` diff --git a/docs/IPCores/io/iic/iic_Switch_PCA9548A.rst b/docs/IPCores/io/iic/iic_Switch_PCA9548A.rst index b4da4a8b..5979dc78 100644 --- a/docs/IPCores/io/iic/iic_Switch_PCA9548A.rst +++ b/docs/IPCores/io/iic/iic_Switch_PCA9548A.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/iic/iic_Switch_PCA9548A.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/iic/iic_Switch_PCA9548A_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:iic_Switch_PCA9548A: iic_Switch_PCA9548A ################### @@ -14,7 +29,6 @@ iic_Switch_PCA9548A :linenos: :lines: 42-90 -Source file: `io/iic/iic_Switch_PCA9548A.vhdl `_ - +Source file: :pocsrc:`io/iic/iic_Switch_PCA9548A.vhdl ` diff --git a/docs/IPCores/io/iic/index.rst b/docs/IPCores/io/iic/index.rst index 04460025..7baaa34d 100644 --- a/docs/IPCores/io/iic/index.rst +++ b/docs/IPCores/io/iic/index.rst @@ -1,11 +1,13 @@ +.. _NS:iic: -iic -===== +PoC.io.iic +========== These are I2C entities.... .. toctree:: + :hidden: - iic_BusController - iic_Controller - iic_Switch_PCA9548A + iic_BusController + iic_Controller + iic_Switch_PCA9548A diff --git a/docs/IPCores/io/index.rst b/docs/IPCores/io/index.rst index 65c21ad4..3723afcf 100644 --- a/docs/IPCores/io/index.rst +++ b/docs/IPCores/io/index.rst @@ -1,6 +1,7 @@ +.. _NS:io: -io -== +PoC.io +====== The namespace ``PoC.io`` offers different general purpose I/O (GPIO) implementations, as well as low-speed bus protocol controllers. @@ -32,22 +33,29 @@ The package :doc:`PoC.io ` holds all enum, function and component declar * :doc:`PoC.io.PulseWidthModulation ` * :doc:`PoC.io.TimingCounter ` + +.. toctree:: + :hidden: + + ddrio + iic + jtag + lcd + mdio + ow + pio + pmod + ps2 + uart + vga + .. toctree:: :hidden: - ddrio/index - iic/index - jtag/index - lcd/index - mdio/index - ow/index - pio/index - pmod/index - ps2/index - uart/index - vga/index - - io.pkg + Package + +.. toctree:: + :hidden: io_7SegmentMux_BCD io_7SegmentMux_HEX diff --git a/docs/IPCores/io/io.pkg.rst b/docs/IPCores/io/io.pkg.rst index 00a8c8a5..80609a05 100644 --- a/docs/IPCores/io/io.pkg.rst +++ b/docs/IPCores/io/io.pkg.rst @@ -1,7 +1,8 @@ +.. _PKG:io: -Package -======== +PoC.io Package +============== This package holds all component declarations for this namespace. -Source file: `io/io.pkg.vhdl `_ +Source file: :pocsrc:`io.pkg.vhdl ` diff --git a/docs/IPCores/io/io_7SegmentMux_BCD.rst b/docs/IPCores/io/io_7SegmentMux_BCD.rst index be066af6..0217b6c4 100644 --- a/docs/IPCores/io/io_7SegmentMux_BCD.rst +++ b/docs/IPCores/io/io_7SegmentMux_BCD.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_7SegmentMux_BCD.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_7SegmentMux_BCD_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:io_7SegmentMux_BCD: io_7SegmentMux_BCD ################## @@ -17,7 +32,6 @@ numbers is supported. :linenos: :lines: 45-60 -Source file: `io/io_7SegmentMux_BCD.vhdl `_ - +Source file: :pocsrc:`io/io_7SegmentMux_BCD.vhdl ` diff --git a/docs/IPCores/io/io_7SegmentMux_HEX.rst b/docs/IPCores/io/io_7SegmentMux_HEX.rst index 4926b941..98fe1f90 100644 --- a/docs/IPCores/io/io_7SegmentMux_HEX.rst +++ b/docs/IPCores/io/io_7SegmentMux_HEX.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_7SegmentMux_HEX.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_7SegmentMux_HEX_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:io_7SegmentMux_HEX: io_7SegmentMux_HEX ################## @@ -16,7 +31,6 @@ are HEX encoded. A dot per digit is optional. :linenos: :lines: 45-60 -Source file: `io/io_7SegmentMux_HEX.vhdl `_ - +Source file: :pocsrc:`io/io_7SegmentMux_HEX.vhdl ` diff --git a/docs/IPCores/io/io_Debounce.rst b/docs/IPCores/io/io_Debounce.rst index 4e0c4b86..4e418c0e 100644 --- a/docs/IPCores/io/io_Debounce.rst +++ b/docs/IPCores/io/io_Debounce.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_Debounce.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_Debounce_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:io_Debounce: io_Debounce ########### @@ -25,7 +40,6 @@ of a two-FF input synchronizer on each input bit. :linenos: :lines: 52-67 -Source file: `io/io_Debounce.vhdl `_ - +Source file: :pocsrc:`io/io_Debounce.vhdl ` diff --git a/docs/IPCores/io/io_FanControl.rst b/docs/IPCores/io/io_FanControl.rst index f91d7bfa..956ab4f2 100644 --- a/docs/IPCores/io/io_FanControl.rst +++ b/docs/IPCores/io/io_FanControl.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_FanControl.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_FanControl_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:io_FanControl: io_FanControl ############# @@ -33,7 +48,6 @@ io_FanControl :linenos: :lines: 63-81 -Source file: `io/io_FanControl.vhdl `_ - +Source file: :pocsrc:`io/io_FanControl.vhdl ` diff --git a/docs/IPCores/io/io_FrequencyCounter.rst b/docs/IPCores/io/io_FrequencyCounter.rst index 80e9bc94..cd53378d 100644 --- a/docs/IPCores/io/io_FrequencyCounter.rst +++ b/docs/IPCores/io/io_FrequencyCounter.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_FrequencyCounter.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_FrequencyCounter_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:io_FrequencyCounter: io_FrequencyCounter ################### @@ -14,7 +29,6 @@ io_FrequencyCounter :linenos: :lines: 40-52 -Source file: `io/io_FrequencyCounter.vhdl `_ - +Source file: :pocsrc:`io/io_FrequencyCounter.vhdl ` diff --git a/docs/IPCores/io/io_GlitchFilter.rst b/docs/IPCores/io/io_GlitchFilter.rst index 48c4f1bf..bde06d95 100644 --- a/docs/IPCores/io/io_GlitchFilter.rst +++ b/docs/IPCores/io/io_GlitchFilter.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_GlitchFilter.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_GlitchFilter_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:io_GlitchFilter: io_GlitchFilter ############### @@ -15,7 +30,6 @@ cycle counts can be configured. :linenos: :lines: 41-51 -Source file: `io/io_GlitchFilter.vhdl `_ - +Source file: :pocsrc:`io/io_GlitchFilter.vhdl ` diff --git a/docs/IPCores/io/io_KeyPadScanner.rst b/docs/IPCores/io/io_KeyPadScanner.rst index b1b06f23..5fff5cfb 100644 --- a/docs/IPCores/io/io_KeyPadScanner.rst +++ b/docs/IPCores/io/io_KeyPadScanner.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_KeyPadScanner.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_KeyPadScanner_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:io_KeyPadScanner: io_KeyPadScanner ################ @@ -18,7 +33,6 @@ matrix is not debounced. :linenos: :lines: 46-63 -Source file: `io/io_KeyPadScanner.vhdl `_ - +Source file: :pocsrc:`io/io_KeyPadScanner.vhdl ` diff --git a/docs/IPCores/io/io_PulseWidthModulation.rst b/docs/IPCores/io/io_PulseWidthModulation.rst index f130f1dc..4555888a 100644 --- a/docs/IPCores/io/io_PulseWidthModulation.rst +++ b/docs/IPCores/io/io_PulseWidthModulation.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_PulseWidthModulation.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_PulseWidthModulation_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:io_PulseWidthModulation: io_PulseWidthModulation ####################### @@ -15,7 +30,6 @@ in frequency (``PWM_FREQ``) and modulation granularity (``PWM_RESOLUTION``). :linenos: :lines: 41-53 -Source file: `io/io_PulseWidthModulation.vhdl `_ - +Source file: :pocsrc:`io/io_PulseWidthModulation.vhdl ` diff --git a/docs/IPCores/io/io_TimingCounter.rst b/docs/IPCores/io/io_TimingCounter.rst index 02862613..85e61084 100644 --- a/docs/IPCores/io/io_TimingCounter.rst +++ b/docs/IPCores/io/io_TimingCounter.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_TimingCounter.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_TimingCounter_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:io_TimingCounter: io_TimingCounter ################ @@ -17,7 +32,6 @@ consisting of ``log2ceilnz(imax(TIMING_TABLE)) + 1`` 6-input LUTs. :linenos: :lines: 43-54 -Source file: `io/io_TimingCounter.vhdl `_ - +Source file: :pocsrc:`io/io_TimingCounter.vhdl ` diff --git a/docs/IPCores/io/jtag/index.rst b/docs/IPCores/io/jtag/index.rst index 0ed83f3e..c5faf6d4 100644 --- a/docs/IPCores/io/jtag/index.rst +++ b/docs/IPCores/io/jtag/index.rst @@ -1,8 +1,10 @@ +.. _NS:jtag: -jtag -==== +PoC.io.jtag +=========== These are JTAG entities.... .. toctree:: + :hidden: diff --git a/docs/IPCores/io/lcd/index.rst b/docs/IPCores/io/lcd/index.rst index 144729aa..f3ca6363 100644 --- a/docs/IPCores/io/lcd/index.rst +++ b/docs/IPCores/io/lcd/index.rst @@ -1,12 +1,14 @@ +.. _NS:lcd: -lcd -=== +PoC.io.lcd +========== These are LCD entities.... .. toctree:: + :hidden: - lcd_LCDBuffer - lcd_LCDBusController - lcd_LCDController_KS0066U - lcd_LCDSynchronizer + lcd_LCDBuffer + lcd_LCDBusController + lcd_LCDController_KS0066U + lcd_LCDSynchronizer diff --git a/docs/IPCores/io/lcd/lcd_LCDBuffer.rst b/docs/IPCores/io/lcd/lcd_LCDBuffer.rst index da24ae53..66fc6ad8 100644 --- a/docs/IPCores/io/lcd/lcd_LCDBuffer.rst +++ b/docs/IPCores/io/lcd/lcd_LCDBuffer.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd_LCDBuffer.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/lcd/lcd_LCDBuffer_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:lcd_LCDBuffer: lcd_LCDBuffer ############# @@ -14,7 +29,6 @@ lcd_LCDBuffer :linenos: :lines: 42-58 -Source file: `io/lcd/lcd_LCDBuffer.vhdl `_ - +Source file: :pocsrc:`io/lcd/lcd_LCDBuffer.vhdl ` diff --git a/docs/IPCores/io/lcd/lcd_LCDBusController.rst b/docs/IPCores/io/lcd/lcd_LCDBusController.rst index 5512701f..e5ead44c 100644 --- a/docs/IPCores/io/lcd/lcd_LCDBusController.rst +++ b/docs/IPCores/io/lcd/lcd_LCDBusController.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd_LCDBusController.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/lcd/lcd_LCDBusController_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:lcd_LCDBusController: lcd_LCDBusController #################### @@ -14,7 +29,6 @@ lcd_LCDBusController :linenos: :lines: 43-67 -Source file: `io/lcd/lcd_LCDBusController.vhdl `_ - +Source file: :pocsrc:`io/lcd/lcd_LCDBusController.vhdl ` diff --git a/docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst b/docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst index 9ca3f647..856d1428 100644 --- a/docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst +++ b/docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd_LCDController_KS0066U.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/lcd/lcd_LCDController_KS0066U_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:lcd_LCDController_KS0066U: lcd_LCDController_KS0066U ######################### @@ -14,7 +29,6 @@ lcd_LCDController_KS0066U :linenos: :lines: 42-64 -Source file: `io/lcd/lcd_LCDController_KS0066U.vhdl `_ - +Source file: :pocsrc:`io/lcd/lcd_LCDController_KS0066U.vhdl ` diff --git a/docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst b/docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst index 1ad67e80..9d711368 100644 --- a/docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst +++ b/docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd_LCDSynchronizer.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/lcd/lcd_LCDSynchronizer_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:lcd_LCDSynchronizer: lcd_LCDSynchronizer ################### @@ -14,7 +29,6 @@ lcd_LCDSynchronizer :linenos: :lines: 42-64 -Source file: `io/lcd/lcd_LCDSynchronizer.vhdl `_ - +Source file: :pocsrc:`io/lcd/lcd_LCDSynchronizer.vhdl ` diff --git a/docs/IPCores/io/lcd/lcd_dotmatrix.rst b/docs/IPCores/io/lcd/lcd_dotmatrix.rst index fe397947..5f31050c 100644 --- a/docs/IPCores/io/lcd/lcd_dotmatrix.rst +++ b/docs/IPCores/io/lcd/lcd_dotmatrix.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd_dotmatrix.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/lcd/lcd_dotmatrix_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:lcd_dotmatrix: lcd_dotmatrix ############# @@ -14,7 +29,6 @@ lcd_dotmatrix :linenos: :lines: 36-67 -Source file: `io/lcd/lcd_dotmatrix.vhdl `_ - +Source file: :pocsrc:`io/lcd/lcd_dotmatrix.vhdl ` diff --git a/docs/IPCores/io/mdio/index.rst b/docs/IPCores/io/mdio/index.rst index 67b40b87..24bb8c4a 100644 --- a/docs/IPCores/io/mdio/index.rst +++ b/docs/IPCores/io/mdio/index.rst @@ -1,11 +1,13 @@ +.. _NS:mdio: -mdio -==== +PoC.io.mdio +=========== These are MDIO entities.... .. toctree:: + :hidden: - mdio_BusController - mdio_Controller - mdio_IIC_Adapter + mdio_BusController + mdio_Controller + mdio_IIC_Adapter diff --git a/docs/IPCores/io/mdio/mdio_Controller.rst b/docs/IPCores/io/mdio/mdio_Controller.rst index f06789d2..210cedd0 100644 --- a/docs/IPCores/io/mdio/mdio_Controller.rst +++ b/docs/IPCores/io/mdio/mdio_Controller.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/mdio/mdio_Controller.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/mdio/mdio_Controller_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:mdio_Controller: mdio_Controller ############### @@ -14,7 +29,6 @@ mdio_Controller :linenos: :lines: 44-73 -Source file: `io/mdio/mdio_Controller.vhdl `_ - +Source file: :pocsrc:`io/mdio/mdio_Controller.vhdl ` diff --git a/docs/IPCores/io/mdio/mdio_IIC_Adapter.rst b/docs/IPCores/io/mdio/mdio_IIC_Adapter.rst index 65373fe9..6bac62e7 100644 --- a/docs/IPCores/io/mdio/mdio_IIC_Adapter.rst +++ b/docs/IPCores/io/mdio/mdio_IIC_Adapter.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/mdio/mdio_IIC_Adapter.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/mdio/mdio_IIC_Adapter_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:mdio_IIC_Adapter: mdio_IIC_Adapter ################ @@ -14,7 +29,6 @@ mdio_IIC_Adapter :linenos: :lines: 44-80 -Source file: `io/mdio/mdio_IIC_Adapter.vhdl `_ - +Source file: :pocsrc:`io/mdio/mdio_IIC_Adapter.vhdl ` diff --git a/docs/IPCores/io/ow/index.rst b/docs/IPCores/io/ow/index.rst index 436fb3f4..21e868f0 100644 --- a/docs/IPCores/io/ow/index.rst +++ b/docs/IPCores/io/ow/index.rst @@ -1,10 +1,12 @@ +.. _NS:ow: -ow -== +PoC.io.ow +========= These are OneWire entities.... .. toctree:: + :hidden: - ow_BusController - ow_Controller + ow_BusController + ow_Controller diff --git a/docs/IPCores/io/pio/index.rst b/docs/IPCores/io/pio/index.rst index 69dd0a40..b66aca7c 100644 --- a/docs/IPCores/io/pio/index.rst +++ b/docs/IPCores/io/pio/index.rst @@ -1,12 +1,14 @@ +.. _NS:pio: -pio -### +PoC.io.pio +========== These are Pmod entities.... .. toctree:: + :hidden: - pio_in - pio_out - pio_fifo_in - pio_fifo_out + pio_in + pio_out + pio_fifo_in + pio_fifo_out diff --git a/docs/IPCores/io/pio/pio_fifo_in.rst b/docs/IPCores/io/pio/pio_fifo_in.rst index f09a6af0..8c0d8df5 100644 --- a/docs/IPCores/io/pio/pio_fifo_in.rst +++ b/docs/IPCores/io/pio/pio_fifo_in.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pio/pio_fifo_in.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pio/pio_fifo_in_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:pio_fifo_in: pio_fifo_in ########### @@ -13,7 +28,6 @@ pio_fifo_in :linenos: :lines: 38-55 -Source file: `io/pio/pio_fifo_in.vhdl `_ - +Source file: :pocsrc:`io/pio/pio_fifo_in.vhdl ` diff --git a/docs/IPCores/io/pio/pio_fifo_out.rst b/docs/IPCores/io/pio/pio_fifo_out.rst index 49fffc17..784a2b1e 100644 --- a/docs/IPCores/io/pio/pio_fifo_out.rst +++ b/docs/IPCores/io/pio/pio_fifo_out.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pio/pio_fifo_out.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pio/pio_fifo_out_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:pio_fifo_out: pio_fifo_out ############ @@ -13,7 +28,6 @@ pio_fifo_out :linenos: :lines: 38-55 -Source file: `io/pio/pio_fifo_out.vhdl `_ - +Source file: :pocsrc:`io/pio/pio_fifo_out.vhdl ` diff --git a/docs/IPCores/io/pio/pio_in.rst b/docs/IPCores/io/pio/pio_in.rst index e7eccec2..f6c1b2de 100644 --- a/docs/IPCores/io/pio/pio_in.rst +++ b/docs/IPCores/io/pio/pio_in.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pio/pio_in.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pio/pio_in_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:pio_in: pio_in ###### @@ -13,7 +28,6 @@ pio_in :linenos: :lines: 40-55 -Source file: `io/pio/pio_in.vhdl `_ - +Source file: :pocsrc:`io/pio/pio_in.vhdl ` diff --git a/docs/IPCores/io/pio/pio_out.rst b/docs/IPCores/io/pio/pio_out.rst index 2e36dd20..ff2dfea5 100644 --- a/docs/IPCores/io/pio/pio_out.rst +++ b/docs/IPCores/io/pio/pio_out.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pio/pio_out.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pio/pio_out_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:pio_out: pio_out ####### @@ -13,7 +28,6 @@ pio_out :linenos: :lines: 40-55 -Source file: `io/pio/pio_out.vhdl `_ - +Source file: :pocsrc:`io/pio/pio_out.vhdl ` diff --git a/docs/IPCores/io/pmod/index.rst b/docs/IPCores/io/pmod/index.rst index adfaf17a..16135599 100644 --- a/docs/IPCores/io/pmod/index.rst +++ b/docs/IPCores/io/pmod/index.rst @@ -1,19 +1,20 @@ +.. _NS:pmod: -pmod -#### +PoC.io.pmod +=========== These are Pmod entities.... **Entities** - * :doc:`PoC.io.pmod.KYPD ` - * :doc:`PoC.io.pmod.SSD ` - * :doc:`PoC.io.pmod.USBUART ` + * :ref:`IP:pmod_KYPD` + * :ref:`IP:pmod_SSD` + * :ref:`IP:pmod_USBUART` .. toctree:: :hidden: - pmod_KYPD - pmod_SSD - pmod_USBUART + pmod_KYPD + pmod_SSD + pmod_USBUART diff --git a/docs/IPCores/io/pmod/pmod_KYPD.rst b/docs/IPCores/io/pmod/pmod_KYPD.rst index b160a86b..60bd0fc9 100644 --- a/docs/IPCores/io/pmod/pmod_KYPD.rst +++ b/docs/IPCores/io/pmod/pmod_KYPD.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pmod/pmod_KYPD.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pmod/pmod_KYPD_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:pmod_KYPD: pmod_KYPD ######### @@ -19,7 +34,6 @@ the button signals. The scan frequency and bounce time can be configured. :linenos: :lines: 46-61 -Source file: `io/pmod/pmod_KYPD.vhdl `_ - +Source file: :pocsrc:`io/pmod/pmod_KYPD.vhdl ` diff --git a/docs/IPCores/io/pmod/pmod_SSD.rst b/docs/IPCores/io/pmod/pmod_SSD.rst index b0482c82..215fdc78 100644 --- a/docs/IPCores/io/pmod/pmod_SSD.rst +++ b/docs/IPCores/io/pmod/pmod_SSD.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pmod/pmod_SSD.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pmod/pmod_SSD_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:pmod_SSD: pmod_SSD ######## @@ -27,7 +42,6 @@ Pmod connector (7 anode bits, 1 cathode bit). :linenos: :lines: 56-69 -Source file: `io/pmod/pmod_SSD.vhdl `_ - +Source file: :pocsrc:`io/pmod/pmod_SSD.vhdl ` diff --git a/docs/IPCores/io/pmod/pmod_USBUART.rst b/docs/IPCores/io/pmod/pmod_USBUART.rst index a5a1c9b4..f34d0080 100644 --- a/docs/IPCores/io/pmod/pmod_USBUART.rst +++ b/docs/IPCores/io/pmod/pmod_USBUART.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pmod/pmod_USBUART.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pmod/pmod_USBUART_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:pmod_USBUART: pmod_USBUART ############ @@ -17,7 +32,6 @@ Hardware flow control (RTS_CTS) is enabled. :linenos: :lines: 43-65 -Source file: `io/pmod/pmod_USBUART.vhdl `_ - +Source file: :pocsrc:`io/pmod/pmod_USBUART.vhdl ` diff --git a/docs/IPCores/io/ps2/index.rst b/docs/IPCores/io/ps2/index.rst index 3638c2f7..9cd1c3a2 100644 --- a/docs/IPCores/io/ps2/index.rst +++ b/docs/IPCores/io/ps2/index.rst @@ -1,8 +1,9 @@ +.. _NS:ps2: -ps2 -=== +PoC.io.ps2 +========== These are PS/2 entities.... .. toctree:: - + :hidden: diff --git a/docs/IPCores/io/uart/index.rst b/docs/IPCores/io/uart/index.rst index f356581c..bb7b3c91 100644 --- a/docs/IPCores/io/uart/index.rst +++ b/docs/IPCores/io/uart/index.rst @@ -1,21 +1,22 @@ +.. _NS:uart: -uart -==== +PoC.io.uart +=========== These are :abbr:`UART (Universal Asynchronous Receiver Transmitter)` entities.... **Entities** - * :doc:`PoC.io.uart.bclk ` - * :doc:`PoC.io.uart.rx ` - * :doc:`PoC.io.uart.tx ` - * :doc:`PoC.io.uart.fifo ` + * :ref:`IP:uart_bclk` + * :ref:`IP:uart_rx` + * :ref:`IP:uart_tx` + * :ref:`IP:uart_fifo` .. toctree:: :hidden: - uart_bclk - uart_rx - uart_tx - uart_fifo + uart_bclk + uart_rx + uart_tx + uart_fifo diff --git a/docs/IPCores/io/uart/uart_bclk.rst b/docs/IPCores/io/uart/uart_bclk.rst index b6fc0837..b0a9e7de 100644 --- a/docs/IPCores/io/uart/uart_bclk.rst +++ b/docs/IPCores/io/uart/uart_bclk.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart_bclk.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/uart/uart_bclk_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:uart_bclk: uart_bclk ######### @@ -20,7 +35,6 @@ old comments: :linenos: :lines: 50-61 -Source file: `io/uart/uart_bclk.vhdl `_ - +Source file: :pocsrc:`io/uart/uart_bclk.vhdl ` diff --git a/docs/IPCores/io/uart/uart_fifo.rst b/docs/IPCores/io/uart/uart_fifo.rst index 283e63bd..cd446978 100644 --- a/docs/IPCores/io/uart/uart_fifo.rst +++ b/docs/IPCores/io/uart/uart_fifo.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart_fifo.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/uart/uart_fifo_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:uart_fifo: uart_fifo ######### @@ -22,7 +37,6 @@ old comments: :linenos: :lines: 52-94 -Source file: `io/uart/uart_fifo.vhdl `_ - +Source file: :pocsrc:`io/uart/uart_fifo.vhdl ` diff --git a/docs/IPCores/io/uart/uart_ft245.rst b/docs/IPCores/io/uart/uart_ft245.rst index 8152cb77..457f2d72 100644 --- a/docs/IPCores/io/uart/uart_ft245.rst +++ b/docs/IPCores/io/uart/uart_ft245.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart_ft245.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/uart/uart_ft245_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:uart_ft245: uart_ft245 ########## @@ -14,7 +29,6 @@ uart_ft245 :linenos: :lines: 37-63 -Source file: `io/uart/uart_ft245.vhdl `_ - +Source file: :pocsrc:`io/uart/uart_ft245.vhdl ` diff --git a/docs/IPCores/io/uart/uart_rx.rst b/docs/IPCores/io/uart/uart_rx.rst index 85f74718..6e0c91c9 100644 --- a/docs/IPCores/io/uart/uart_rx.rst +++ b/docs/IPCores/io/uart/uart_rx.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart_rx.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/uart/uart_rx_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:uart_rx: uart_rx ####### @@ -15,7 +30,6 @@ uart_rx :linenos: :lines: 39-56 -Source file: `io/uart/uart_rx.vhdl `_ - +Source file: :pocsrc:`io/uart/uart_rx.vhdl ` diff --git a/docs/IPCores/io/uart/uart_tx.rst b/docs/IPCores/io/uart/uart_tx.rst index b4c63f15..9d99c7c1 100644 --- a/docs/IPCores/io/uart/uart_tx.rst +++ b/docs/IPCores/io/uart/uart_tx.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart_tx.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/uart/uart_tx_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:uart_tx: uart_tx ####### @@ -15,7 +30,6 @@ uart_tx :linenos: :lines: 35-50 -Source file: `io/uart/uart_tx.vhdl `_ - +Source file: :pocsrc:`io/uart/uart_tx.vhdl ` diff --git a/docs/IPCores/io/vga/index.rst b/docs/IPCores/io/vga/index.rst index 9cdebbc4..d5ba2277 100644 --- a/docs/IPCores/io/vga/index.rst +++ b/docs/IPCores/io/vga/index.rst @@ -1,11 +1,13 @@ +.. _NS:vga: -vga -=== +PoC.io.vga +========== These are VGA entities.... .. toctree:: + :hidden: - vga_phy - vga_phy_ch7301c - vga_timing + vga_phy + vga_phy_ch7301c + vga_timing diff --git a/docs/IPCores/io/vga/vga_phy.rst b/docs/IPCores/io/vga/vga_phy.rst index 8ed5ade8..1ac7b6a4 100644 --- a/docs/IPCores/io/vga/vga_phy.rst +++ b/docs/IPCores/io/vga/vga_phy.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/vga/vga_phy.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/vga/vga_phy_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:vga_phy: vga_phy ####### @@ -18,7 +33,6 @@ vga_phy :linenos: :lines: 43-55 -Source file: `io/vga/vga_phy.vhdl `_ - +Source file: :pocsrc:`io/vga/vga_phy.vhdl ` diff --git a/docs/IPCores/io/vga/vga_phy_ch7301c.rst b/docs/IPCores/io/vga/vga_phy_ch7301c.rst index f1614b64..b0e639ca 100644 --- a/docs/IPCores/io/vga/vga_phy_ch7301c.rst +++ b/docs/IPCores/io/vga/vga_phy_ch7301c.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/vga/vga_phy_ch7301c.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/vga/vga_phy_ch7301c_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:vga_phy_ch7301c: vga_phy_ch7301c ############### @@ -45,7 +60,6 @@ tests/ml505/vga_test_ml505.vhdl for an example. :linenos: :lines: 70-83 -Source file: `io/vga/vga_phy_ch7301c.vhdl `_ - +Source file: :pocsrc:`io/vga/vga_phy_ch7301c.vhdl ` diff --git a/docs/IPCores/io/vga/vga_timing.rst b/docs/IPCores/io/vga/vga_timing.rst index fdde46c5..aa822f74 100644 --- a/docs/IPCores/io/vga/vga_timing.rst +++ b/docs/IPCores/io/vga/vga_timing.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/vga/vga_timing.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/vga/vga_timing_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:vga_timing: vga_timing ########## @@ -53,7 +68,6 @@ differ between SMT and CVT. :linenos: :lines: 80-96 -Source file: `io/vga/vga_timing.vhdl `_ - +Source file: :pocsrc:`io/vga/vga_timing.vhdl ` diff --git a/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst b/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst index ff96714a..aff9727b 100644 --- a/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst +++ b/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst @@ -1,8 +1,23 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ddr2/ddr2_mem2mig_adapter_Spartan6_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:ddr2_mem2mig_adapter_Spartan6: ddr2_mem2mig_adapter_Spartan6 ############################# -Adapter between the :doc:`PoC.Mem ` +Adapter between the :doc:`PoC.Mem ` interface and the User Interface of the Xilinx MIG IP core for the Spartan-6 FPGA Memory Controller Block (MCB). The MCB can be configured to have multiple ports. One instance of this adapter is required for every @@ -13,7 +28,7 @@ Simplifies the User Interface ("user") of the Xilinx MIG IP core (UG388). The PoC.Mem interface provides single-cycle fully pipelined read/write access to the memory. All accesses are word-aligned. Always all bytes of a word are written to the memory. More details can be found -:doc:`here `. +:doc:`here `. Generic parameters: @@ -36,7 +51,6 @@ Containts only combinational logic. :linenos: :lines: 61-95 -Source file: `mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl `_ - +Source file: :pocsrc:`mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl ` diff --git a/docs/IPCores/mem/ddr2/index.rst b/docs/IPCores/mem/ddr2/index.rst index a65f9d39..1f98bb54 100644 --- a/docs/IPCores/mem/ddr2/index.rst +++ b/docs/IPCores/mem/ddr2/index.rst @@ -1,5 +1,7 @@ -ddr2 -==== +.. _NS:ddr2: + +PoC.mem.ddr2 +============ The namespace ``PoC.mem.ddr2`` is designated for own implementations of DDR2 memory controllers as well as for adapters for vendor-specific @@ -10,12 +12,11 @@ provide the same simple memory interface to the user application. **Entities** - * :doc:`PoC.mem.ddr2.mem2mig_adapter_Spartan6 - ` - Adapter for the Xilinx MIG core + * :ref:`IP:ddr2_mem2mig_adapter_Spartan6` - Adapter for the Xilinx MIG core for Spartan-6 FPGAs .. toctree:: :hidden: - ddr2_mem2mig_adapter_Spartan6 + ddr2_mem2mig_adapter_Spartan6 diff --git a/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst b/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst index cf988c31..8de9d117 100644 --- a/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst +++ b/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst @@ -1,8 +1,23 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ddr3/ddr3_mem2mig_adapter_Series7_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:ddr3_mem2mig_adapter_Series7: ddr3_mem2mig_adapter_Series7 ############################ -Adapter between the :doc:`PoC.Mem ` +Adapter between the :doc:`PoC.Mem ` interface and the application interface ("app") of the Xilinx MIG IP core for 7-Series FPGAs. @@ -10,7 +25,7 @@ Simplifies the application interface ("app") of the Xilinx MIG IP core. The PoC.Mem interface provides single-cycle fully pipelined read/write access to the memory. All accesses are word-aligned. Always all bytes of a word are written to the memory. More details can be found -:doc:`here `. +:doc:`here `. Generic parameters: @@ -36,7 +51,6 @@ Containts only combinational logic. :linenos: :lines: 61-96 -Source file: `mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl `_ - +Source file: :pocsrc:`mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl ` diff --git a/docs/IPCores/mem/ddr3/index.rst b/docs/IPCores/mem/ddr3/index.rst index 99902c1a..f6232571 100644 --- a/docs/IPCores/mem/ddr3/index.rst +++ b/docs/IPCores/mem/ddr3/index.rst @@ -1,5 +1,7 @@ -ddr3 -==== +.. _NS:ddr3: + +PoC.mem.ddr3 +============ The namespace ``PoC.mem.ddr3`` is designated for own implementations of DDR3 memory controllers as well as for adapters for vendor-specific @@ -10,12 +12,11 @@ provide the same simple memory interface to the user application. **Entities** - * :doc:`PoC.mem.ddr3.mem2mig_adapter_Series7 - ` - Adapter for the Xilinx MIG core + * :ref:`IP:ddr3_mem2mig_adapter_Series7` - Adapter for the Xilinx MIG core for 7-Series FPGAs .. toctree:: :hidden: - ddr3_mem2mig_adapter_Series7 + ddr3_mem2mig_adapter_Series7 diff --git a/docs/IPCores/mem/index.rst b/docs/IPCores/mem/index.rst index c9bdd898..21fc27c8 100644 --- a/docs/IPCores/mem/index.rst +++ b/docs/IPCores/mem/index.rst @@ -1,6 +1,7 @@ +.. _NS:mem: -mem -=== +PoC.mem +======== The namespace ``PoC.mem`` offers different on-chip and off-chip memory and memory-controller implementations. @@ -8,26 +9,30 @@ implementations. **Sub-Namespaces** - * :doc:`PoC.mem.ddr3 ` - DDR3 memory controllers - * :doc:`PoC.mem.ddr2 ` - DDR2 memory controllers - * :doc:`PoC.mem.lut ` - Lookup-Table (LUT) implementations - * :doc:`PoC.mem.ocram ` - On-Chip RAM abstraction layer - * :doc:`PoC.mem.ocrom ` - On-Chip ROM abstraction layer - * :doc:`PoC.mem.sdram ` - SDRAM controllers + * :ref:`NS:ddr3` - DDR3 memory controllers + * :ref:`NS:ddr2` - DDR2 memory controllers + * :ref:`NS:lut` - Lookup-Table (LUT) implementations + * :ref:`NS:ocram` - On-Chip RAM abstraction layer + * :ref:`NS:ocrom` - On-Chip ROM abstraction layer + * :ref:`NS:sdram` - SDRAM controllers **Package** -:doc:`PoC.mem ` +:ref:`PoC.mem ` .. toctree:: :hidden: - ddr3/index - ddr2/index - lut/index - ocram/index - ocrom/index - sdram/index + Package + +.. toctree:: + :hidden: + + ddr3 + ddr2 + lut + ocram + ocrom + sdram - mem.pkg diff --git a/docs/IPCores/mem/lut/index.rst b/docs/IPCores/mem/lut/index.rst index 6336bbb7..c714731c 100644 --- a/docs/IPCores/mem/lut/index.rst +++ b/docs/IPCores/mem/lut/index.rst @@ -1,15 +1,16 @@ +.. _NS:lut: -lut -=== +PoC.mem.lut +=========== The namespace ``PoC.mem.lut`` offers different lookup-tables (LUTs). **Entities** - * :doc:`lut_Sine ` - a Sine implementation with 1,2 or 4 quadrants. + * :ref:`IP:lut_Sine` - a Sine implementation with 1,2 or 4 quadrants. .. toctree:: :hidden: - lut_Sine + lut_Sine diff --git a/docs/IPCores/mem/lut/lut_Sine.rst b/docs/IPCores/mem/lut/lut_Sine.rst index ea7d1b82..fa9dd8a5 100644 --- a/docs/IPCores/mem/lut/lut_Sine.rst +++ b/docs/IPCores/mem/lut/lut_Sine.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/lut/lut_Sine.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/lut/lut_Sine_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:lut_Sine: lut_Sine ######## @@ -14,7 +29,6 @@ lut_Sine :linenos: :lines: 41-54 -Source file: `mem/lut/lut_Sine.vhdl `_ - +Source file: :pocsrc:`mem/lut/lut_Sine.vhdl ` diff --git a/docs/IPCores/mem/mem.pkg.rst b/docs/IPCores/mem/mem.pkg.rst index cb5820d1..963c1dca 100644 --- a/docs/IPCores/mem/mem.pkg.rst +++ b/docs/IPCores/mem/mem.pkg.rst @@ -1,7 +1,8 @@ +.. _PKG:mem: -Package -======== +PoC.mem Package +=============== This package holds all component declarations for this namespace. -Source file: `mem/mem.pkg.vhdl `_ +Source file: :pocsrc:`mem.pkg.vhdl ` diff --git a/docs/IPCores/mem/ocram/index.rst b/docs/IPCores/mem/ocram/index.rst index 68beb118..b2c5c31e 100644 --- a/docs/IPCores/mem/ocram/index.rst +++ b/docs/IPCores/mem/ocram/index.rst @@ -1,6 +1,7 @@ +.. _NS:ocram: -ocram -===== +PoC.mem.ocram +============= The namespace ``PoC.mem.ocram`` offers different on-chip RAM abstractions. @@ -16,18 +17,18 @@ The package PoC.mem.ocram holds all component declarations for this namespace. **Entities** - * :doc:`PoC.mem.ocram.sp ` - An on-chip RAM with a single port interface. - * :doc:`PoC.mem.ocram.sdp ` - An on-chip RAM with a simple dual port interface. - * :doc:`PoC.mem.ocram.tdp ` - An on-chip RAM with a true dual port interface. + * :ref:`IP:ocram_sp` - An on-chip RAM with a single port interface. + * :ref:`IP:ocram_sdp` - An on-chip RAM with a simple dual port interface. + * :ref:`IP:ocram_tdp` - An on-chip RAM with a true dual port interface. **Deprecated Entities** - * :doc:`PoC.mem.ocram.esdp ` - An on-chip RAM with an extended simple dual port interface. + * :ref:`IP:ocram_esdp` - An on-chip RAM with an extended simple dual port interface. .. toctree:: :hidden: - ocram_sp - ocram_esdp - ocram_sdp - ocram_tdp + ocram_sp + ocram_esdp + ocram_sdp + ocram_tdp diff --git a/docs/IPCores/mem/ocram/ocram_esdp.rst b/docs/IPCores/mem/ocram/ocram_esdp.rst index 3c181384..76d40a9d 100644 --- a/docs/IPCores/mem/ocram/ocram_esdp.rst +++ b/docs/IPCores/mem/ocram/ocram_esdp.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram_esdp.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocram/ocram_esdp_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:ocram_esdp: ocram_esdp ########## @@ -68,7 +83,6 @@ Mixed-Port Read-During-Write :linenos: :lines: 101-119 -Source file: `mem/ocram/ocram_esdp.vhdl `_ - +Source file: :pocsrc:`mem/ocram/ocram_esdp.vhdl ` diff --git a/docs/IPCores/mem/ocram/ocram_sdp.rst b/docs/IPCores/mem/ocram/ocram_sdp.rst index eec1100e..2169056a 100644 --- a/docs/IPCores/mem/ocram/ocram_sdp.rst +++ b/docs/IPCores/mem/ocram/ocram_sdp.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram_sdp.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocram/ocram_sdp_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:ocram_sdp: ocram_sdp ######### @@ -34,7 +49,6 @@ Mixed-Port Read-During-Write :linenos: :lines: 65-82 -Source file: `mem/ocram/ocram_sdp.vhdl `_ - +Source file: :pocsrc:`mem/ocram/ocram_sdp.vhdl ` diff --git a/docs/IPCores/mem/ocram/ocram_sp.rst b/docs/IPCores/mem/ocram/ocram_sp.rst index 131c4b5f..86322a29 100644 --- a/docs/IPCores/mem/ocram/ocram_sp.rst +++ b/docs/IPCores/mem/ocram/ocram_sp.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram_sp.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocram/ocram_sp_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:ocram_sp: ocram_sp ######## @@ -37,7 +52,6 @@ also applies to Altera M20K memory blocks as described in the Altera: :linenos: :lines: 68-82 -Source file: `mem/ocram/ocram_sp.vhdl `_ - +Source file: :pocsrc:`mem/ocram/ocram_sp.vhdl ` diff --git a/docs/IPCores/mem/ocram/ocram_tdp.rst b/docs/IPCores/mem/ocram/ocram_tdp.rst index 8690b8fc..ef13a067 100644 --- a/docs/IPCores/mem/ocram/ocram_tdp.rst +++ b/docs/IPCores/mem/ocram/ocram_tdp.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram_tdp.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocram/ocram_tdp_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:ocram_tdp: ocram_tdp ######### @@ -53,7 +68,6 @@ Mixed-Port Read-During-Write :linenos: :lines: 84-104 -Source file: `mem/ocram/ocram_tdp.vhdl `_ - +Source file: :pocsrc:`mem/ocram/ocram_tdp.vhdl ` diff --git a/docs/IPCores/mem/ocrom/index.rst b/docs/IPCores/mem/ocrom/index.rst index f899db1f..0d80cf8b 100644 --- a/docs/IPCores/mem/ocrom/index.rst +++ b/docs/IPCores/mem/ocrom/index.rst @@ -1,6 +1,7 @@ +.. _NS:ocrom: -ocrom -===== +PoC.mem.ocrom +============= The namespace ``PoC.mem.ocrom`` offers different on-chip ROM abstractions. @@ -16,12 +17,12 @@ The package PoC.mem.ocrom holds all component declarations for this namespace. **Entities** - - :doc:`ocrom_sp ` is a on-chip RAM with a single port interface. - - :doc:`ocrom_dp ` is a on-chip RAM with a dual port interface. + - :ref:`ocrom_sp ` is a on-chip RAM with a single port interface. + - :ref:`ocrom_dp ` is a on-chip RAM with a dual port interface. .. toctree:: :hidden: - ocrom_sp - ocrom_dp + ocrom_sp + ocrom_dp diff --git a/docs/IPCores/mem/ocrom/ocrom_dp.rst b/docs/IPCores/mem/ocrom/ocrom_dp.rst index c889d0ec..fcbc610d 100644 --- a/docs/IPCores/mem/ocrom/ocrom_dp.rst +++ b/docs/IPCores/mem/ocrom/ocrom_dp.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocrom/ocrom_dp.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocrom/ocrom_dp_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:ocrom_dp: ocrom_dp ######## @@ -25,7 +40,6 @@ TODO: implement correct behavior for RT-level simulation :linenos: :lines: 60-76 -Source file: `mem/ocrom/ocrom_dp.vhdl `_ - +Source file: :pocsrc:`mem/ocrom/ocrom_dp.vhdl ` diff --git a/docs/IPCores/mem/ocrom/ocrom_sp.rst b/docs/IPCores/mem/ocrom/ocrom_sp.rst index 6bf43afa..d2b7583d 100644 --- a/docs/IPCores/mem/ocrom/ocrom_sp.rst +++ b/docs/IPCores/mem/ocrom/ocrom_sp.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocrom/ocrom_sp.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocrom/ocrom_sp_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:ocrom_sp: ocrom_sp ######## @@ -18,7 +33,6 @@ Inferring / instantiating single-port read-only memory :linenos: :lines: 53-65 -Source file: `mem/ocrom/ocrom_sp.vhdl `_ - +Source file: :pocsrc:`mem/ocrom/ocrom_sp.vhdl ` diff --git a/docs/IPCores/mem/sdram/index.rst b/docs/IPCores/mem/sdram/index.rst index 5c50a4fe..fafe582b 100644 --- a/docs/IPCores/mem/sdram/index.rst +++ b/docs/IPCores/mem/sdram/index.rst @@ -1,6 +1,7 @@ +.. _NS:sdram: -sdram -===== +PoC.mem.sdram +============= The namespace ``PoC.mem.sdram`` offers components for the access of external SDRAMs. A common finite state-machine is used to address the memory via banks, rows and @@ -10,24 +11,24 @@ module required by the FPGA board. .. rubric:: SDRAM Controller for the Altera DE0 Board -The module :doc:`sdram_ctrl_de0 ` combines the finite state machine -:doc:`sdram_ctrl_fsm ` and the DE0 specific physical layer -:doc:`sdram_ctrl_phy_de0 `. It has been tested with the +The module :ref:`sdram_ctrl_de0 ` combines the finite state machine +:ref:`sdram_ctrl_fsm ` and the DE0 specific physical layer +:ref:`sdram_ctrl_phy_de0 `. It has been tested with the IS42S16400F SDR memory at a frequency of 133 MHz. A usage example is given in PoC-Examples_. .. rubric:: SDRAM Controller for the Xilinx Spartan-3E Starter Kit (S3ESK) -The module :doc:`sdram_ctrl_s3esk ` combines the finite state -machine :doc:`sdram_ctrl_fsm ` and the S3ESK specific physical layer -:doc:`sdram_ctrl_phy_s3esk `. It has been tested with the +The module :ref:`sdram_ctrl_s3esk ` combines the finite state +machine :ref:`sdram_ctrl_fsm ` and the S3ESK specific physical layer +:ref:`sdram_ctrl_phy_s3esk `. It has been tested with the MT46V32M16-6T DDR memory at a frequency of 100 MHz (DDR-200). A usage example is given in PoC-Examples_. .. Note:: - See also :doc:`PoC.xil.mig ` for board specific memory controller - implementations created by Xilinx's Memory Interface Generator (MIG). + See also :ref:`NS:mig` for board specific memory controller implementations + created by Xilinx's Memory Interface Generator (MIG). @@ -36,8 +37,8 @@ example is given in PoC-Examples_. .. toctree:: :hidden: - sdram_ctrl_fsm - sdram_ctrl_de0 - sdram_ctrl_phy_de0 - sdram_ctrl_s3esk - sdram_ctrl_phy_s3esk + sdram_ctrl_fsm + sdram_ctrl_de0 + sdram_ctrl_phy_de0 + sdram_ctrl_s3esk + sdram_ctrl_phy_s3esk diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst b/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst index 05e2bdca..803211ae 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/sdram/sdram_ctrl_de0.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/sdram/sdram_ctrl_de0_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:sdram_ctrl_de0: sdram_ctrl_de0 ############## @@ -44,7 +59,6 @@ Synchronous resets are used. :linenos: :lines: 88-120 -Source file: `mem/sdram/sdram_ctrl_de0.vhdl `_ - +Source file: :pocsrc:`mem/sdram/sdram_ctrl_de0.vhdl ` diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst b/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst index ff3bd7e9..d838ac5f 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/sdram/sdram_ctrl_fsm.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/sdram/sdram_ctrl_fsm_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:sdram_ctrl_fsm: sdram_ctrl_fsm ############## @@ -80,7 +95,6 @@ The write data must directly connected to the physical layer. :linenos: :lines: 124-168 -Source file: `mem/sdram/sdram_ctrl_fsm.vhdl `_ - +Source file: :pocsrc:`mem/sdram/sdram_ctrl_fsm.vhdl ` diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst b/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst index d1c05adb..bffa9e26 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/sdram/sdram_ctrl_phy_de0.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/sdram/sdram_ctrl_phy_de0_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:sdram_ctrl_phy_de0: sdram_ctrl_phy_de0 ################## @@ -46,7 +61,6 @@ Synchronous resets are used. Reset must be hold for at least two cycles. :linenos: :lines: 89-122 -Source file: `mem/sdram/sdram_ctrl_phy_de0.vhdl `_ - +Source file: :pocsrc:`mem/sdram/sdram_ctrl_phy_de0.vhdl ` diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst b/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst index 65ebdfdc..f11e6440 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/sdram/sdram_ctrl_phy_s3esk_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:sdram_ctrl_phy_s3esk: sdram_ctrl_phy_s3esk #################### @@ -84,7 +99,6 @@ Synchronous resets are used. Reset must be hold for at least two cycles. :linenos: :lines: 127-171 -Source file: `mem/sdram/sdram_ctrl_phy_s3esk.vhdl `_ - +Source file: :pocsrc:`mem/sdram/sdram_ctrl_phy_s3esk.vhdl ` diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst b/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst index f4bee22a..d5d6bd54 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/sdram/sdram_ctrl_s3esk.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/sdram/sdram_ctrl_s3esk_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:sdram_ctrl_s3esk: sdram_ctrl_s3esk ################ @@ -45,7 +60,6 @@ Synchronous resets are used. :linenos: :lines: 89-132 -Source file: `mem/sdram/sdram_ctrl_s3esk.vhdl `_ - +Source file: :pocsrc:`mem/sdram/sdram_ctrl_s3esk.vhdl ` diff --git a/docs/IPCores/misc/filter/filter_and.rst b/docs/IPCores/misc/filter/filter_and.rst index b5b9508d..8d47f49a 100644 --- a/docs/IPCores/misc/filter/filter_and.rst +++ b/docs/IPCores/misc/filter/filter_and.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/filter/filter_and.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/filter/filter_and_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:filter_and: filter_and ########## @@ -14,7 +29,6 @@ filter_and :linenos: :lines: 37-48 -Source file: `misc/filter/filter_and.vhdl `_ - +Source file: :pocsrc:`misc/filter/filter_and.vhdl ` diff --git a/docs/IPCores/misc/filter/filter_mean.rst b/docs/IPCores/misc/filter/filter_mean.rst index 09812062..13cc8e97 100644 --- a/docs/IPCores/misc/filter/filter_mean.rst +++ b/docs/IPCores/misc/filter/filter_mean.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/filter/filter_mean.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/filter/filter_mean_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:filter_mean: filter_mean ########### @@ -14,7 +29,6 @@ filter_mean :linenos: :lines: 37-48 -Source file: `misc/filter/filter_mean.vhdl `_ - +Source file: :pocsrc:`misc/filter/filter_mean.vhdl ` diff --git a/docs/IPCores/misc/filter/filter_or.rst b/docs/IPCores/misc/filter/filter_or.rst index 18f5377e..2d8d9bf7 100644 --- a/docs/IPCores/misc/filter/filter_or.rst +++ b/docs/IPCores/misc/filter/filter_or.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/filter/filter_or.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/filter/filter_or_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:filter_or: filter_or ######### @@ -14,7 +29,6 @@ filter_or :linenos: :lines: 37-48 -Source file: `misc/filter/filter_or.vhdl `_ - +Source file: :pocsrc:`misc/filter/filter_or.vhdl ` diff --git a/docs/IPCores/misc/filter/index.rst b/docs/IPCores/misc/filter/index.rst index 3e6e224d..a6bc70d6 100644 --- a/docs/IPCores/misc/filter/index.rst +++ b/docs/IPCores/misc/filter/index.rst @@ -1,18 +1,19 @@ +.. _NS:filter: -filter -====== +PoC.misc.filter +=============== These are filter entities.... **Entities** - * :doc:`PoC.misc.filter.and ` - * :doc:`PoC.misc.filter.mean ` - * :doc:`PoC.misc.filter.or ` + * :ref:`IP:filter_and` + * :ref:`IP:filter_mean` + * :ref:`IP:filter_or` .. toctree:: :hidden: - filter_and - filter_mean - filter_or + filter_and + filter_mean + filter_or diff --git a/docs/IPCores/misc/gearbox/gearbox_down_cc.rst b/docs/IPCores/misc/gearbox/gearbox_down_cc.rst index 73f094b0..6cdf8fca 100644 --- a/docs/IPCores/misc/gearbox/gearbox_down_cc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_down_cc.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/gearbox/gearbox_down_cc.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/gearbox/gearbox_down_cc_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:gearbox_down_cc: gearbox_down_cc ############### @@ -18,7 +33,6 @@ gearbox_down_cc :linenos: :lines: 46-70 -Source file: `misc/gearbox/gearbox_down_cc.vhdl `_ - +Source file: :pocsrc:`misc/gearbox/gearbox_down_cc.vhdl ` diff --git a/docs/IPCores/misc/gearbox/gearbox_down_dc.rst b/docs/IPCores/misc/gearbox/gearbox_down_dc.rst index 6e26413f..5c2972c4 100644 --- a/docs/IPCores/misc/gearbox/gearbox_down_dc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_down_dc.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/gearbox/gearbox_down_dc.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/gearbox/gearbox_down_dc_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:gearbox_down_dc: gearbox_down_dc ############### @@ -23,7 +38,6 @@ Assertions: :linenos: :lines: 50-64 -Source file: `misc/gearbox/gearbox_down_dc.vhdl `_ - +Source file: :pocsrc:`misc/gearbox/gearbox_down_dc.vhdl ` diff --git a/docs/IPCores/misc/gearbox/gearbox_up_cc.rst b/docs/IPCores/misc/gearbox/gearbox_up_cc.rst index 86042b81..fce085ad 100644 --- a/docs/IPCores/misc/gearbox/gearbox_up_cc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_up_cc.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/gearbox/gearbox_up_cc.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/gearbox/gearbox_up_cc_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:gearbox_up_cc: gearbox_up_cc ############# @@ -18,7 +33,6 @@ gearbox_up_cc :linenos: :lines: 46-69 -Source file: `misc/gearbox/gearbox_up_cc.vhdl `_ - +Source file: :pocsrc:`misc/gearbox/gearbox_up_cc.vhdl ` diff --git a/docs/IPCores/misc/gearbox/gearbox_up_dc.rst b/docs/IPCores/misc/gearbox/gearbox_up_dc.rst index 8d90a465..ecb9a9a6 100644 --- a/docs/IPCores/misc/gearbox/gearbox_up_dc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_up_dc.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/gearbox/gearbox_up_dc.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/gearbox/gearbox_up_dc_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:gearbox_up_dc: gearbox_up_dc ############# @@ -24,7 +39,6 @@ Assertions: :linenos: :lines: 51-66 -Source file: `misc/gearbox/gearbox_up_dc.vhdl `_ - +Source file: :pocsrc:`misc/gearbox/gearbox_up_dc.vhdl ` diff --git a/docs/IPCores/misc/gearbox/index.rst b/docs/IPCores/misc/gearbox/index.rst index 765ae347..b66ca2fe 100644 --- a/docs/IPCores/misc/gearbox/index.rst +++ b/docs/IPCores/misc/gearbox/index.rst @@ -1,20 +1,21 @@ +.. _NS:gearbox: -gearbox -======== +PoC.misc.gearbox +================ These are gearbox entities.... **Entities** - * :doc:`PoC.misc.gearbox.down_cc ` - * :doc:`PoC.misc.gearbox.down_dc ` - * :doc:`PoC.misc.gearbox.up_cc ` - * :doc:`PoC.misc.gearbox.up_dc ` + * :ref:`IP:gearbox_down_cc` + * :ref:`IP:gearbox_down_dc` + * :ref:`IP:gearbox_up_cc` + * :ref:`IP:gearbox_up_dc` .. toctree:: :hidden: - gearbox_down_cc - gearbox_down_dc - gearbox_up_cc - gearbox_up_dc + gearbox_down_cc + gearbox_down_dc + gearbox_up_cc + gearbox_up_dc diff --git a/docs/IPCores/misc/index.rst b/docs/IPCores/misc/index.rst index 7651ed65..d8920515 100644 --- a/docs/IPCores/misc/index.rst +++ b/docs/IPCores/misc/index.rst @@ -1,43 +1,50 @@ +.. _NS:misc: -misc -==== +PoC.misc +======== The namespace ``PoC.misc`` offers different yet uncathegorized entities. **Sub-Namespaces** - * :doc:`PoC.misc.filter ` contains 1-bit filter algorithms. - * :doc:`PoC.misc.stat ` contains statistic modules. - * :doc:`PoC.misc.sync ` offers clock-domain-crossing (CDC) modules. + * :ref:`NS:filter` contains 1-bit filter algorithms. + * :ref:`NS:stat` contains statistic modules. + * :ref:`NS:sync` offers clock-domain-crossing (CDC) modules. **Package** -The package :doc:`PoC.misc ` holds all component declarations for this namespace. +The package :ref:`PoC.misc ` holds all component declarations for this namespace. **Entities** - * :doc:`PoC.misc.Delay ` - * :doc:`PoC.misc.FrequencyMeasurement ` - * :doc:`PoC.misc.PulseTrain ` - * :doc:`PoC.misc.Sequencer ` - * :doc:`PoC.misc.StrobeGenerator ` - * :doc:`PoC.misc.StrobeLimiter ` - * :doc:`PoC.misc.WordAligner ` + * :ref:`IP:misc_Delay` + * :ref:`IP:misc_FrequencyMeasurement` + * :ref:`IP:misc_PulseTrain` + * :ref:`IP:misc_Sequencer` + * :ref:`IP:misc_StrobeGenerator` + * :ref:`IP:misc_StrobeLimiter` + * :ref:`IP:misc_WordAligner` .. toctree:: :hidden: - filter/index - gearbox/index - stat/index - sync/index + filter + gearbox + stat + sync - misc.pkg +.. toctree:: + :hidden: + + Package + +.. toctree:: + :hidden: - misc_Delay - misc_FrequencyMeasurement - misc_PulseTrain - misc_Sequencer - misc_StrobeGenerator - misc_StrobeLimiter - misc_WordAligner + misc_Delay + misc_FrequencyMeasurement + misc_PulseTrain + misc_Sequencer + misc_StrobeGenerator + misc_StrobeLimiter + misc_WordAligner diff --git a/docs/IPCores/misc/misc.pkg.rst b/docs/IPCores/misc/misc.pkg.rst index 7ea587d9..1b5f56f3 100644 --- a/docs/IPCores/misc/misc.pkg.rst +++ b/docs/IPCores/misc/misc.pkg.rst @@ -1,7 +1,8 @@ +.. _PKG:misc: -Package -======== +PoC.misc Package +================ This package holds all component declarations for this namespace. -Source file: `misc/misc.pkg.vhdl `_ +Source file: :pocsrc:`misc.pkg.vhdl ` diff --git a/docs/IPCores/misc/misc_BitwidthConverter.rst b/docs/IPCores/misc/misc_BitwidthConverter.rst index 2b78114f..dc1b1cad 100644 --- a/docs/IPCores/misc/misc_BitwidthConverter.rst +++ b/docs/IPCores/misc/misc_BitwidthConverter.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_BitwidthConverter.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_BitwidthConverter_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:misc_BitwidthConverter: misc_BitwidthConverter ###################### @@ -12,7 +27,6 @@ misc_BitwidthConverter :linenos: :lines: 32-45 -Source file: `misc/misc_BitwidthConverter.vhdl `_ - +Source file: :pocsrc:`misc/misc_BitwidthConverter.vhdl ` diff --git a/docs/IPCores/misc/misc_ByteAligner.rst b/docs/IPCores/misc/misc_ByteAligner.rst index b7024d4f..6c821706 100644 --- a/docs/IPCores/misc/misc_ByteAligner.rst +++ b/docs/IPCores/misc/misc_ByteAligner.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_ByteAligner.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_ByteAligner_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:misc_ByteAligner: misc_ByteAligner ################ @@ -14,7 +29,6 @@ misc_ByteAligner :linenos: :lines: 40-53 -Source file: `misc/misc_ByteAligner.vhdl `_ - +Source file: :pocsrc:`misc/misc_ByteAligner.vhdl ` diff --git a/docs/IPCores/misc/misc_Delay.rst b/docs/IPCores/misc/misc_Delay.rst index edd17178..b266b9a8 100644 --- a/docs/IPCores/misc/misc_Delay.rst +++ b/docs/IPCores/misc/misc_Delay.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_Delay.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_Delay_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:misc_Delay: misc_Delay ########## @@ -14,7 +29,6 @@ misc_Delay :linenos: :lines: 38-50 -Source file: `misc/misc_Delay.vhdl `_ - +Source file: :pocsrc:`misc/misc_Delay.vhdl ` diff --git a/docs/IPCores/misc/misc_FrequencyMeasurement.rst b/docs/IPCores/misc/misc_FrequencyMeasurement.rst index c8d13954..a933bde1 100644 --- a/docs/IPCores/misc/misc_FrequencyMeasurement.rst +++ b/docs/IPCores/misc/misc_FrequencyMeasurement.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_FrequencyMeasurement.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_FrequencyMeasurement_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:misc_FrequencyMeasurement: misc_FrequencyMeasurement ######################### @@ -16,7 +31,6 @@ value is the measured frequency in Hz. :linenos: :lines: 44-56 -Source file: `misc/misc_FrequencyMeasurement.vhdl `_ - +Source file: :pocsrc:`misc/misc_FrequencyMeasurement.vhdl ` diff --git a/docs/IPCores/misc/misc_PulseTrain.rst b/docs/IPCores/misc/misc_PulseTrain.rst index d0a88636..e43344e7 100644 --- a/docs/IPCores/misc/misc_PulseTrain.rst +++ b/docs/IPCores/misc/misc_PulseTrain.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_PulseTrain.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_PulseTrain_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:misc_PulseTrain: misc_PulseTrain ############### @@ -15,7 +30,6 @@ misc_PulseTrain :linenos: :lines: 41-51 -Source file: `misc/misc_PulseTrain.vhdl `_ - +Source file: :pocsrc:`misc/misc_PulseTrain.vhdl ` diff --git a/docs/IPCores/misc/misc_Sequencer.rst b/docs/IPCores/misc/misc_Sequencer.rst index 73209bb0..9e5bac82 100644 --- a/docs/IPCores/misc/misc_Sequencer.rst +++ b/docs/IPCores/misc/misc_Sequencer.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_Sequencer.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_Sequencer_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:misc_Sequencer: misc_Sequencer ############## @@ -14,7 +29,6 @@ misc_Sequencer :linenos: :lines: 40-56 -Source file: `misc/misc_Sequencer.vhdl `_ - +Source file: :pocsrc:`misc/misc_Sequencer.vhdl ` diff --git a/docs/IPCores/misc/misc_StrobeGenerator.rst b/docs/IPCores/misc/misc_StrobeGenerator.rst index 8471f24f..dba1a0a9 100644 --- a/docs/IPCores/misc/misc_StrobeGenerator.rst +++ b/docs/IPCores/misc/misc_StrobeGenerator.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_StrobeGenerator.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_StrobeGenerator_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:misc_StrobeGenerator: misc_StrobeGenerator #################### @@ -14,7 +29,6 @@ misc_StrobeGenerator :linenos: :lines: 40-49 -Source file: `misc/misc_StrobeGenerator.vhdl `_ - +Source file: :pocsrc:`misc/misc_StrobeGenerator.vhdl ` diff --git a/docs/IPCores/misc/misc_StrobeLimiter.rst b/docs/IPCores/misc/misc_StrobeLimiter.rst index 7eea3f38..3badfdf1 100644 --- a/docs/IPCores/misc/misc_StrobeLimiter.rst +++ b/docs/IPCores/misc/misc_StrobeLimiter.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_StrobeLimiter.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_StrobeLimiter_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:misc_StrobeLimiter: misc_StrobeLimiter ################## @@ -14,7 +29,6 @@ misc_StrobeLimiter :linenos: :lines: 39-51 -Source file: `misc/misc_StrobeLimiter.vhdl `_ - +Source file: :pocsrc:`misc/misc_StrobeLimiter.vhdl ` diff --git a/docs/IPCores/misc/misc_bit_lz.rst b/docs/IPCores/misc/misc_bit_lz.rst index 10b20231..5224d825 100644 --- a/docs/IPCores/misc/misc_bit_lz.rst +++ b/docs/IPCores/misc/misc_bit_lz.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_bit_lz.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_bit_lz_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:misc_bit_lz: misc_bit_lz ########### @@ -50,7 +65,6 @@ misc_bit_lz :linenos: :lines: 69-91 -Source file: `misc/misc_bit_lz.vhdl `_ - +Source file: :pocsrc:`misc/misc_bit_lz.vhdl ` diff --git a/docs/IPCores/misc/stat/index.rst b/docs/IPCores/misc/stat/index.rst index 542f6f0c..72d74210 100644 --- a/docs/IPCores/misc/stat/index.rst +++ b/docs/IPCores/misc/stat/index.rst @@ -1,21 +1,22 @@ +.. _NS:stat: -stat -==== +PoC.misc.stat +============= These are stat entities.... **Entities** - * :doc:`PoC.misc.stat.Average ` - * :doc:`PoC.misc.stat.Histogram ` - * :doc:`PoC.misc.stat.Maximum ` - * :doc:`PoC.misc.stat.Minimum ` + * :ref:`IP:stat_Average` + * :ref:`IP:stat_Histogram` + * :ref:`IP:stat_Maximum` + * :ref:`IP:stat_Minimum` .. toctree:: :hidden: - stat_Average - stat_Histogram - stat_Maximum - stat_Minimum + stat_Average + stat_Histogram + stat_Maximum + stat_Minimum diff --git a/docs/IPCores/misc/stat/stat_Average.rst b/docs/IPCores/misc/stat/stat_Average.rst index 6d149fd1..aedc5de9 100644 --- a/docs/IPCores/misc/stat/stat_Average.rst +++ b/docs/IPCores/misc/stat/stat_Average.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/stat/stat_Average.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/stat/stat_Average_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:stat_Average: stat_Average ############ @@ -14,7 +29,6 @@ stat_Average :linenos: :lines: 41-58 -Source file: `misc/stat/stat_Average.vhdl `_ - +Source file: :pocsrc:`misc/stat/stat_Average.vhdl ` diff --git a/docs/IPCores/misc/stat/stat_Histogram.rst b/docs/IPCores/misc/stat/stat_Histogram.rst index 3fa0400f..69ae2c40 100644 --- a/docs/IPCores/misc/stat/stat_Histogram.rst +++ b/docs/IPCores/misc/stat/stat_Histogram.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/stat/stat_Histogram.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/stat/stat_Histogram_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:stat_Histogram: stat_Histogram ############## @@ -14,7 +29,6 @@ stat_Histogram :linenos: :lines: 40-54 -Source file: `misc/stat/stat_Histogram.vhdl `_ - +Source file: :pocsrc:`misc/stat/stat_Histogram.vhdl ` diff --git a/docs/IPCores/misc/stat/stat_Maximum.rst b/docs/IPCores/misc/stat/stat_Maximum.rst index 36f9adeb..65a9b785 100644 --- a/docs/IPCores/misc/stat/stat_Maximum.rst +++ b/docs/IPCores/misc/stat/stat_Maximum.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/stat/stat_Maximum.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/stat/stat_Maximum_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:stat_Maximum: stat_Maximum ############ @@ -14,7 +29,6 @@ stat_Maximum :linenos: :lines: 40-57 -Source file: `misc/stat/stat_Maximum.vhdl `_ - +Source file: :pocsrc:`misc/stat/stat_Maximum.vhdl ` diff --git a/docs/IPCores/misc/stat/stat_Minimum.rst b/docs/IPCores/misc/stat/stat_Minimum.rst index e98f7545..00c43b3a 100644 --- a/docs/IPCores/misc/stat/stat_Minimum.rst +++ b/docs/IPCores/misc/stat/stat_Minimum.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/stat/stat_Minimum.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/stat/stat_Minimum_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:stat_Minimum: stat_Minimum ############ @@ -14,7 +29,6 @@ stat_Minimum :linenos: :lines: 40-57 -Source file: `misc/stat/stat_Minimum.vhdl `_ - +Source file: :pocsrc:`misc/stat/stat_Minimum.vhdl ` diff --git a/docs/IPCores/misc/sync/index.rst b/docs/IPCores/misc/sync/index.rst index 8c7caf2f..026c89cd 100644 --- a/docs/IPCores/misc/sync/index.rst +++ b/docs/IPCores/misc/sync/index.rst @@ -1,36 +1,38 @@ -sync -==== +.. _NS:sync: + +PoC.misc.sync +============= The namespace ``PoC.misc.sync`` offers different clock-domain-crossing (CDC) synchronizer circuits. All synchronizers are based on the basic 2 flip-flop -synchonizer called :doc:`sync_Bits `. PoC has two +synchonizer called :ref:`sync_Bits `. PoC has two platform specific implementations for Altera and Xilinx, which are choosen, if the appropriate ``MY_DEVICE`` constant is configured in ``my_config.vhdl``. **Decision Table:** -+----------+-------------------------------------------------+---------------------------------------------------+--------------------+-----------------------------------------------+-----------------------------------------------+ -| Behavior | Flag [#f1]_ | Strobe [#f2]_ | Continuous Data | Reset [#f4]_ | Pulse [#f3]_ | -+==========+=================================================+===================================================+====================+===============================================+===============================================+ -| 1 Bit | :doc:`sync_Bits ` | :doc:`sync_Strobe ` | fifo_ic_got [#f5]_ | :doc:`sync_Reset ` | :doc:`sync_Pulse ` | -+----------+-------------------------------------------------+---------------------------------------------------+--------------------+-----------------------------------------------+-----------------------------------------------+ -| n Bit | :doc:`sync_Vector ` | :doc:`sync_Command ` | fifo_ic_got [#f5]_ | | | -+----------+-------------------------------------------------+---------------------------------------------------+--------------------+-----------------------------------------------+-----------------------------------------------+ ++----------+-------------------------------------+---------------------------------------+--------------------+-----------------------------------+-----------------------------------+ +| Behavior | Flag [#f1]_ | Strobe [#f2]_ | Continuous Data | Reset [#f4]_ | Pulse [#f3]_ | ++==========+=====================================+=======================================+====================+===================================+===================================+ +| 1 Bit | :ref:`sync_Bits ` | :ref:`sync_Strobe ` | fifo_ic_got [#f5]_ | :ref:`sync_Reset ` | :ref:`sync_Pulse ` | ++----------+-------------------------------------+---------------------------------------+--------------------+-----------------------------------+-----------------------------------+ +| n Bit | :ref:`sync_Vector ` | :ref:`sync_Command ` | fifo_ic_got [#f5]_ | | | ++----------+-------------------------------------+---------------------------------------+--------------------+-----------------------------------+-----------------------------------+ .. rubric:: Basic 2 Flip-Flop Synchronizer -The basic 2 flip-flop synchronizer is called :doc:`sync_Bits `. It's +The basic 2 flip-flop synchronizer is called :ref:`sync_Bits `. It's possible to configure the bit count of indivital bits. If a vector shall be synchronized, use one of the special synchronizers like `sync_Vector`. The vendor specific implementations are named ``sync_Bits_Altera`` and ``sync_Bits_Xilinx`` respectivily. -A second variant of the 2-FF synchronizer is called :doc:`sync_Reset `. +A second variant of the 2-FF synchronizer is called :ref:`sync_Reset `. It's for ``Reset``-signals, implementing asynchronous assertion and synchronous deassertion. The vendor specific implementations are named ``sync_Reset_Altera`` and ``sync_Reset_Xilinx`` respectivily. -A third variant of a 2-FF synchronizer is called :doc:`sync_Pulse `. +A third variant of a 2-FF synchronizer is called :ref:`sync_Pulse `. It's for very short ``Pulsed``-signals. It uses an addition asynchronous capture FF to latch the very short pulse. The vendor specific implementations are named ``sync_Pulse_Altera`` and ``sync_Pulse_Xilinx`` respectivily. @@ -39,15 +41,15 @@ very short pulse. The vendor specific implementations are named ``sync_Pulse_Alt Based on the 2-FF synchronizer, several "high-level" synchronizers are build. -* :doc:`sync_Strobe ` synchronizer ``strobe``-signals +* :ref:`sync_Strobe ` synchronizer ``strobe``-signals across clock-domain-boundaries. A busy signal indicates the synchronization status and can be used as a internal gate-signal to disallow new incoming strobes. A ``strobe``-signal is only for one clock period active. -* :doc:`sync_Command ` like ``sync_Strobe``, it synchronizes +* :ref:`sync_Command ` like ``sync_Strobe``, it synchronizes a one clock period active signal across the clock-domain-boundary, but the input has multiple bits. After the multi bit strobe (Command) was transfered, the output goes to its idle value. -* :doc:`sync_Vector ` synchronizes a complete vector +* :ref:`sync_Vector ` synchronizes a complete vector across the clock-domain-boundary. A changed detection on the input vector causes a register to latch the current state. The changed event is transfered to the new clock-domain and triggers a register to store the latched content, @@ -55,7 +57,7 @@ Based on the 2-FF synchronizer, several "high-level" synchronizers are build. .. seealso:: - :doc:`PoC.fifo.ic_got ` + :ref:`IP:fifo_ic_got` For a cross-clock capable FIFO. .. rubric:: Footnotes @@ -63,15 +65,16 @@ Based on the 2-FF synchronizer, several "high-level" synchronizers are build. .. [#f1] A *flag* or *status* signal is a continuous, long time stable signal. .. [#f2] A *strobe* signal is active for only one cycle. .. [#f3] A *pulse* signal is a very short event. -.. [#f4] To be documented +.. [#f4] To be refumented .. [#f5] See the ``PoC.fifo`` namespace for cross-clock capable FIFOs. + .. toctree:: :hidden: - sync_Bits - sync_Command - sync_Pulse - sync_Reset - sync_Strobe - sync_Vector + sync_Bits + sync_Command + sync_Pulse + sync_Reset + sync_Strobe + sync_Vector diff --git a/docs/IPCores/misc/sync/sync_Bits.rst b/docs/IPCores/misc/sync/sync_Bits.rst index 51c5225d..19c9ccff 100644 --- a/docs/IPCores/misc/sync/sync_Bits.rst +++ b/docs/IPCores/misc/sync/sync_Bits.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Bits.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Bits_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:sync_Bits: sync_Bits ######### @@ -32,18 +47,17 @@ Constraints: :linenos: :lines: 68-79 -Source file: `misc/sync/sync_Bits.vhdl `_ +Source file: :pocsrc:`misc/sync/sync_Bits.vhdl ` .. seealso:: - :doc:`PoC.misc.sync.Reset ` + :doc:`PoC.misc.sync.Reset ` For a special 2 D-FF synchronizer for *reset*-signals. - :doc:`PoC.misc.sync.Pulse ` + :doc:`PoC.misc.sync.Pulse ` For a special 1+2 D-FF synchronizer for *pulse*-signals. - :doc:`PoC.misc.sync.Strobe ` + :doc:`PoC.misc.sync.Strobe ` For a synchronizer for *strobe*-signals. - :doc:`PoC.misc.sync.Vector ` + :doc:`PoC.misc.sync.Vector ` For a multiple bits capable synchronizer. - diff --git a/docs/IPCores/misc/sync/sync_Command.rst b/docs/IPCores/misc/sync/sync_Command.rst index 8224d838..aaf13394 100644 --- a/docs/IPCores/misc/sync/sync_Command.rst +++ b/docs/IPCores/misc/sync/sync_Command.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Command.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Command_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:sync_Command: sync_Command ############ @@ -24,7 +39,6 @@ Constraints: :linenos: :lines: 50-63 -Source file: `misc/sync/sync_Command.vhdl `_ - +Source file: :pocsrc:`misc/sync/sync_Command.vhdl ` diff --git a/docs/IPCores/misc/sync/sync_Pulse.rst b/docs/IPCores/misc/sync/sync_Pulse.rst index 7667bf73..b74f65d2 100644 --- a/docs/IPCores/misc/sync/sync_Pulse.rst +++ b/docs/IPCores/misc/sync/sync_Pulse.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Pulse.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Pulse_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:sync_Pulse: sync_Pulse ########## @@ -32,18 +47,17 @@ Constraints: :linenos: :lines: 68-78 -Source file: `misc/sync/sync_Pulse.vhdl `_ +Source file: :pocsrc:`misc/sync/sync_Pulse.vhdl ` .. seealso:: - :doc:`PoC.misc.sync.Bits ` + :doc:`PoC.misc.sync.Bits ` For a common 2 D-FF synchronizer for *flag*-signals. - :doc:`PoC.misc.sync.Reset ` + :doc:`PoC.misc.sync.Reset ` For a special 2 D-FF synchronizer for *reset*-signals. - :doc:`PoC.misc.sync.Strobe ` + :doc:`PoC.misc.sync.Strobe ` For a synchronizer for *strobe*-signals. - :doc:`PoC.misc.sync.Vector ` + :doc:`PoC.misc.sync.Vector ` For a multiple bits capable synchronizer. - diff --git a/docs/IPCores/misc/sync/sync_Reset.rst b/docs/IPCores/misc/sync/sync_Reset.rst index 191a0f65..b89017f6 100644 --- a/docs/IPCores/misc/sync/sync_Reset.rst +++ b/docs/IPCores/misc/sync/sync_Reset.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Reset.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Reset_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:sync_Reset: sync_Reset ########## @@ -34,7 +49,6 @@ Constraints: :linenos: :lines: 60-69 -Source file: `misc/sync/sync_Reset.vhdl `_ - +Source file: :pocsrc:`misc/sync/sync_Reset.vhdl ` diff --git a/docs/IPCores/misc/sync/sync_Strobe.rst b/docs/IPCores/misc/sync/sync_Strobe.rst index a59b2d2a..4f68fc44 100644 --- a/docs/IPCores/misc/sync/sync_Strobe.rst +++ b/docs/IPCores/misc/sync/sync_Strobe.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Strobe.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Strobe_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:sync_Strobe: sync_Strobe ########### @@ -29,7 +44,6 @@ Constraints: :linenos: :lines: 54-66 -Source file: `misc/sync/sync_Strobe.vhdl `_ - +Source file: :pocsrc:`misc/sync/sync_Strobe.vhdl ` diff --git a/docs/IPCores/misc/sync/sync_Vector.rst b/docs/IPCores/misc/sync/sync_Vector.rst index c2ace981..c959e08f 100644 --- a/docs/IPCores/misc/sync/sync_Vector.rst +++ b/docs/IPCores/misc/sync/sync_Vector.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Vector.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Vector_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:sync_Vector: sync_Vector ########### @@ -23,7 +38,6 @@ Constraints: :linenos: :lines: 49-63 -Source file: `misc/sync/sync_Vector.vhdl `_ - +Source file: :pocsrc:`misc/sync/sync_Vector.vhdl ` diff --git a/docs/IPCores/net/arp/arp_BroadCast_Receiver.rst b/docs/IPCores/net/arp/arp_BroadCast_Receiver.rst index 9aeca321..25def10c 100644 --- a/docs/IPCores/net/arp/arp_BroadCast_Receiver.rst +++ b/docs/IPCores/net/arp/arp_BroadCast_Receiver.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_BroadCast_Receiver.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_BroadCast_Receiver_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arp_BroadCast_Receiver: arp_BroadCast_Receiver ###################### @@ -14,7 +29,6 @@ arp_BroadCast_Receiver :linenos: :lines: 42-74 -Source file: `net/arp/arp_BroadCast_Receiver.vhdl `_ - +Source file: :pocsrc:`net/arp/arp_BroadCast_Receiver.vhdl ` diff --git a/docs/IPCores/net/arp/arp_BroadCast_Requester.rst b/docs/IPCores/net/arp/arp_BroadCast_Requester.rst index 45f11821..01e5d526 100644 --- a/docs/IPCores/net/arp/arp_BroadCast_Requester.rst +++ b/docs/IPCores/net/arp/arp_BroadCast_Requester.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_BroadCast_Requester.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_BroadCast_Requester_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arp_BroadCast_Requester: arp_BroadCast_Requester ####################### @@ -14,7 +29,6 @@ arp_BroadCast_Requester :linenos: :lines: 42-73 -Source file: `net/arp/arp_BroadCast_Requester.vhdl `_ - +Source file: :pocsrc:`net/arp/arp_BroadCast_Requester.vhdl ` diff --git a/docs/IPCores/net/arp/arp_Cache.rst b/docs/IPCores/net/arp/arp_Cache.rst index 5007fdb0..8103a188 100644 --- a/docs/IPCores/net/arp/arp_Cache.rst +++ b/docs/IPCores/net/arp/arp_Cache.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_Cache.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_Cache_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arp_Cache: arp_Cache ######### @@ -14,7 +29,6 @@ arp_Cache :linenos: :lines: 44-75 -Source file: `net/arp/arp_Cache.vhdl `_ - +Source file: :pocsrc:`net/arp/arp_Cache.vhdl ` diff --git a/docs/IPCores/net/arp/arp_IPPool.rst b/docs/IPCores/net/arp/arp_IPPool.rst index dceffcdf..27a28095 100644 --- a/docs/IPCores/net/arp/arp_IPPool.rst +++ b/docs/IPCores/net/arp/arp_IPPool.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_IPPool.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_IPPool_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arp_IPPool: arp_IPPool ########## @@ -14,7 +29,6 @@ arp_IPPool :linenos: :lines: 43-63 -Source file: `net/arp/arp_IPPool.vhdl `_ - +Source file: :pocsrc:`net/arp/arp_IPPool.vhdl ` diff --git a/docs/IPCores/net/arp/arp_Tester.rst b/docs/IPCores/net/arp/arp_Tester.rst index 39ce6b01..09e9a8cd 100644 --- a/docs/IPCores/net/arp/arp_Tester.rst +++ b/docs/IPCores/net/arp/arp_Tester.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_Tester.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_Tester_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arp_Tester: arp_Tester ########## @@ -14,7 +29,6 @@ arp_Tester :linenos: :lines: 43-65 -Source file: `net/arp/arp_Tester.vhdl `_ - +Source file: :pocsrc:`net/arp/arp_Tester.vhdl ` diff --git a/docs/IPCores/net/arp/arp_UniCast_Receiver.rst b/docs/IPCores/net/arp/arp_UniCast_Receiver.rst index 518ba0ea..dcd72188 100644 --- a/docs/IPCores/net/arp/arp_UniCast_Receiver.rst +++ b/docs/IPCores/net/arp/arp_UniCast_Receiver.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_UniCast_Receiver.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_UniCast_Receiver_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arp_UniCast_Receiver: arp_UniCast_Receiver #################### @@ -14,7 +29,6 @@ arp_UniCast_Receiver :linenos: :lines: 42-76 -Source file: `net/arp/arp_UniCast_Receiver.vhdl `_ - +Source file: :pocsrc:`net/arp/arp_UniCast_Receiver.vhdl ` diff --git a/docs/IPCores/net/arp/arp_UniCast_Responder.rst b/docs/IPCores/net/arp/arp_UniCast_Responder.rst index 6cb4e232..9dc59855 100644 --- a/docs/IPCores/net/arp/arp_UniCast_Responder.rst +++ b/docs/IPCores/net/arp/arp_UniCast_Responder.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_UniCast_Responder.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_UniCast_Responder_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arp_UniCast_Responder: arp_UniCast_Responder ##################### @@ -14,7 +29,6 @@ arp_UniCast_Responder :linenos: :lines: 42-73 -Source file: `net/arp/arp_UniCast_Responder.vhdl `_ - +Source file: :pocsrc:`net/arp/arp_UniCast_Responder.vhdl ` diff --git a/docs/IPCores/net/arp/arp_Wrapper.rst b/docs/IPCores/net/arp/arp_Wrapper.rst index 5a480ad7..44214616 100644 --- a/docs/IPCores/net/arp/arp_Wrapper.rst +++ b/docs/IPCores/net/arp/arp_Wrapper.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_Wrapper.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_Wrapper_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:arp_Wrapper: arp_Wrapper ########### @@ -14,7 +29,6 @@ arp_Wrapper :linenos: :lines: 44-100 -Source file: `net/arp/arp_Wrapper.vhdl `_ - +Source file: :pocsrc:`net/arp/arp_Wrapper.vhdl ` diff --git a/docs/IPCores/net/arp/index.rst b/docs/IPCores/net/arp/index.rst index f4dd1fe2..05bd2b95 100644 --- a/docs/IPCores/net/arp/index.rst +++ b/docs/IPCores/net/arp/index.rst @@ -1,16 +1,17 @@ +.. _NS:arp: -arp -=== +PoC.net.arp +=========== These are ARP entities.... .. toctree:: - arp_BroadCast_Receiver - arp_BroadCast_Requester - arp_Cache - arp_IPPool - arp_Tester - arp_UniCast_Receiver - arp_UniCast_Responder - arp_Wrapper + arp_BroadCast_Receiver + arp_BroadCast_Requester + arp_Cache + arp_IPPool + arp_Tester + arp_UniCast_Receiver + arp_UniCast_Responder + arp_Wrapper diff --git a/docs/IPCores/net/eth/eth_GEMAC_GMII.rst b/docs/IPCores/net/eth/eth_GEMAC_GMII.rst index 75094c88..b0ef49bf 100644 --- a/docs/IPCores/net/eth/eth_GEMAC_GMII.rst +++ b/docs/IPCores/net/eth/eth_GEMAC_GMII.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_GEMAC_GMII.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_GEMAC_GMII_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:eth_GEMAC_GMII: eth_GEMAC_GMII ############## @@ -14,7 +29,6 @@ eth_GEMAC_GMII :linenos: :lines: 42-101 -Source file: `net/eth/eth_GEMAC_GMII.vhdl `_ - +Source file: :pocsrc:`net/eth/eth_GEMAC_GMII.vhdl ` diff --git a/docs/IPCores/net/eth/eth_GEMAC_RX.rst b/docs/IPCores/net/eth/eth_GEMAC_RX.rst index 24745ee6..bfba9622 100644 --- a/docs/IPCores/net/eth/eth_GEMAC_RX.rst +++ b/docs/IPCores/net/eth/eth_GEMAC_RX.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_GEMAC_RX.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_GEMAC_RX_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:Eth_GEMAC_RX: Eth_GEMAC_RX ############ @@ -14,7 +29,6 @@ Eth_GEMAC_RX :linenos: :lines: 42-62 -Source file: `net/eth/eth_GEMAC_RX.vhdl `_ - +Source file: :pocsrc:`net/eth/eth_GEMAC_RX.vhdl ` diff --git a/docs/IPCores/net/eth/eth_GEMAC_TX.rst b/docs/IPCores/net/eth/eth_GEMAC_TX.rst index 6cbfea27..5273b154 100644 --- a/docs/IPCores/net/eth/eth_GEMAC_TX.rst +++ b/docs/IPCores/net/eth/eth_GEMAC_TX.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_GEMAC_TX.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_GEMAC_TX_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:Eth_GEMAC_TX: Eth_GEMAC_TX ############ @@ -14,7 +29,6 @@ Eth_GEMAC_TX :linenos: :lines: 42-65 -Source file: `net/eth/eth_GEMAC_TX.vhdl `_ - +Source file: :pocsrc:`net/eth/eth_GEMAC_TX.vhdl ` diff --git a/docs/IPCores/net/eth/eth_PHYController.rst b/docs/IPCores/net/eth/eth_PHYController.rst index dd91ac10..07e53335 100644 --- a/docs/IPCores/net/eth/eth_PHYController.rst +++ b/docs/IPCores/net/eth/eth_PHYController.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_PHYController.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_PHYController_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:Eth_PHYController: Eth_PHYController ################# @@ -14,7 +29,6 @@ Eth_PHYController :linenos: :lines: 45-68 -Source file: `net/eth/eth_PHYController.vhdl `_ - +Source file: :pocsrc:`net/eth/eth_PHYController.vhdl ` diff --git a/docs/IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst b/docs/IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst index 8be2545e..10a48e8f 100644 --- a/docs/IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst +++ b/docs/IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_PHYController_Marvell_88E1111.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_PHYController_Marvell_88E1111_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:Eth_PHYController_Marvell_88E1111: Eth_PHYController_Marvell_88E1111 ################################# @@ -14,7 +29,6 @@ Eth_PHYController_Marvell_88E1111 :linenos: :lines: 44-71 -Source file: `net/eth/eth_PHYController_Marvell_88E1111.vhdl `_ - +Source file: :pocsrc:`net/eth/eth_PHYController_Marvell_88E1111.vhdl ` diff --git a/docs/IPCores/net/eth/eth_Wrapper.rst b/docs/IPCores/net/eth/eth_Wrapper.rst index f54362b9..af4644a4 100644 --- a/docs/IPCores/net/eth/eth_Wrapper.rst +++ b/docs/IPCores/net/eth/eth_Wrapper.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_Wrapper.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_Wrapper_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:Eth_Wrapper: Eth_Wrapper ########### @@ -14,7 +29,6 @@ Eth_Wrapper :linenos: :lines: 68-112 -Source file: `net/eth/eth_Wrapper.vhdl `_ - +Source file: :pocsrc:`net/eth/eth_Wrapper.vhdl ` diff --git a/docs/IPCores/net/eth/index.rst b/docs/IPCores/net/eth/index.rst index 555d552e..d3d74f8e 100644 --- a/docs/IPCores/net/eth/index.rst +++ b/docs/IPCores/net/eth/index.rst @@ -1,14 +1,15 @@ +.. _NS:eth: -eth -=== +PoC.net.eth +=========== These are eth entities.... .. toctree:: - eth_GEMAC_GMII - eth_GEMAC_RX - eth_GEMAC_TX - eth_PHYController - eth_PHYController_Marvell_88E1111 - eth_Wrapper + eth_GEMAC_GMII + eth_GEMAC_RX + eth_GEMAC_TX + eth_PHYController + eth_PHYController_Marvell_88E1111 + eth_Wrapper diff --git a/docs/IPCores/net/icmpv4/icmpv4_RX.rst b/docs/IPCores/net/icmpv4/icmpv4_RX.rst index 32d296c8..f9d08143 100644 --- a/docs/IPCores/net/icmpv4/icmpv4_RX.rst +++ b/docs/IPCores/net/icmpv4/icmpv4_RX.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv4/icmpv4_RX.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv4/icmpv4_RX_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:icmpv4_RX: icmpv4_RX ######### @@ -14,7 +29,6 @@ icmpv4_RX :linenos: :lines: 42-88 -Source file: `net/icmpv4/icmpv4_RX.vhdl `_ - +Source file: :pocsrc:`net/icmpv4/icmpv4_RX.vhdl ` diff --git a/docs/IPCores/net/icmpv4/icmpv4_TX.rst b/docs/IPCores/net/icmpv4/icmpv4_TX.rst index 67986f7c..893bc63f 100644 --- a/docs/IPCores/net/icmpv4/icmpv4_TX.rst +++ b/docs/IPCores/net/icmpv4/icmpv4_TX.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv4/icmpv4_TX.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv4/icmpv4_TX_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:icmpv4_TX: icmpv4_TX ######### @@ -14,7 +29,6 @@ icmpv4_TX :linenos: :lines: 42-78 -Source file: `net/icmpv4/icmpv4_TX.vhdl `_ - +Source file: :pocsrc:`net/icmpv4/icmpv4_TX.vhdl ` diff --git a/docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst b/docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst index c08141e8..72e1c648 100644 --- a/docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst +++ b/docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv4/icmpv4_Wrapper.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv4/icmpv4_Wrapper_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:icmpv4_Wrapper: icmpv4_Wrapper ############## @@ -14,7 +29,6 @@ icmpv4_Wrapper :linenos: :lines: 42-91 -Source file: `net/icmpv4/icmpv4_Wrapper.vhdl `_ - +Source file: :pocsrc:`net/icmpv4/icmpv4_Wrapper.vhdl ` diff --git a/docs/IPCores/net/icmpv4/index.rst b/docs/IPCores/net/icmpv4/index.rst index e8276ba9..ab12b94e 100644 --- a/docs/IPCores/net/icmpv4/index.rst +++ b/docs/IPCores/net/icmpv4/index.rst @@ -1,11 +1,12 @@ +.. _NS:icmpv4: -icmpv4 -====== +PoC.net.icmpv4 +============== These are icmpv4 entities.... .. toctree:: - icmpv4_RX - icmpv4_TX - icmpv4_Wrapper + icmpv4_RX + icmpv4_TX + icmpv4_Wrapper diff --git a/docs/IPCores/net/icmpv6/icmpv6_RX.rst b/docs/IPCores/net/icmpv6/icmpv6_RX.rst index 9a57ab9f..8ea87cea 100644 --- a/docs/IPCores/net/icmpv6/icmpv6_RX.rst +++ b/docs/IPCores/net/icmpv6/icmpv6_RX.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv6/icmpv6_RX.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv6/icmpv6_RX_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:icmpv6_RX: icmpv6_RX ######### @@ -14,7 +29,6 @@ icmpv6_RX :linenos: :lines: 42-57 -Source file: `net/icmpv6/icmpv6_RX.vhdl `_ - +Source file: :pocsrc:`net/icmpv6/icmpv6_RX.vhdl ` diff --git a/docs/IPCores/net/icmpv6/icmpv6_TX.rst b/docs/IPCores/net/icmpv6/icmpv6_TX.rst index 24e6dee4..50305e8a 100644 --- a/docs/IPCores/net/icmpv6/icmpv6_TX.rst +++ b/docs/IPCores/net/icmpv6/icmpv6_TX.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv6/icmpv6_TX.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv6/icmpv6_TX_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:icmpv6_TX: icmpv6_TX ######### @@ -14,7 +29,6 @@ icmpv6_TX :linenos: :lines: 42-56 -Source file: `net/icmpv6/icmpv6_TX.vhdl `_ - +Source file: :pocsrc:`net/icmpv6/icmpv6_TX.vhdl ` diff --git a/docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst b/docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst index 23718664..8247e1b2 100644 --- a/docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst +++ b/docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv6/icmpv6_Wrapper.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv6/icmpv6_Wrapper_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:icmpv6_Wrapper: icmpv6_Wrapper ############## @@ -14,7 +29,6 @@ icmpv6_Wrapper :linenos: :lines: 42-67 -Source file: `net/icmpv6/icmpv6_Wrapper.vhdl `_ - +Source file: :pocsrc:`net/icmpv6/icmpv6_Wrapper.vhdl ` diff --git a/docs/IPCores/net/icmpv6/index.rst b/docs/IPCores/net/icmpv6/index.rst index 2586053b..452d9eea 100644 --- a/docs/IPCores/net/icmpv6/index.rst +++ b/docs/IPCores/net/icmpv6/index.rst @@ -1,11 +1,12 @@ +.. _NS:icmpv6: -icmpv6 -====== +PoC.net.icmpv6 +============== These are icmpv6 entities.... .. toctree:: - icmpv6_RX - icmpv6_TX - icmpv6_Wrapper + icmpv6_RX + icmpv6_TX + icmpv6_Wrapper diff --git a/docs/IPCores/net/index.rst b/docs/IPCores/net/index.rst index 728d253f..259af559 100644 --- a/docs/IPCores/net/index.rst +++ b/docs/IPCores/net/index.rst @@ -1,43 +1,49 @@ +.. _NS:net: -net -=== +PoC.net +======== These are bus entities.... **Sub-Namespaces** - * :doc:`PoC.net.arp ` - * :doc:`PoC.net.eth ` - * :doc:`PoC.net.icmpv4 ` - * :doc:`PoC.net.icmpv6 ` - * :doc:`PoC.net.ipv4 ` - * :doc:`PoC.net.ipv6 ` - * :doc:`PoC.net.mac ` - * :doc:`PoC.net.ndp ` - * :doc:`PoC.net.stack ` - * :doc:`PoC.net.udp ` + * :ref:`NS:arp` + * :ref:`NS:eth` + * :ref:`NS:icmpv4` + * :ref:`NS:icmpv6` + * :ref:`NS:ipv4` + * :ref:`NS:ipv6` + * :ref:`NS:mac` + * :ref:`NS:ndp` + * :ref:`NS:stack` + * :ref:`NS:udp` **Entities** - * :doc:`PoC.net.FrameChecksum ` - * :doc:`PoC.net.FrameLoopback ` + * :ref:`IP:net_FrameChecksum` + * :ref:`IP:net_FrameLoopback` .. toctree:: :hidden: - arp/index - eth/index - icmpv4/index - icmpv6/index - ipv4/index - ipv6/index - mac/index - ndp/index - stack/index - udp/index + arp + eth + icmpv4 + icmpv6 + ipv4 + ipv6 + mac + ndp + stack + udp .. toctree:: :hidden: - net_FrameChecksum - net_FrameLoopback + Package + +.. toctree:: + :hidden: + + net_FrameChecksum + net_FrameLoopback diff --git a/docs/IPCores/net/ipv4/index.rst b/docs/IPCores/net/ipv4/index.rst index abd71311..0aaec125 100644 --- a/docs/IPCores/net/ipv4/index.rst +++ b/docs/IPCores/net/ipv4/index.rst @@ -1,12 +1,13 @@ +.. _NS:ipv4: -ipv4 -==== +PoC.net.ipv4 +============ These are ipv4 entities.... .. toctree:: - ipv4_RX - ipv4_TX - ipv4_FrameLoopback - ipv4_Wrapper + ipv4_RX + ipv4_TX + ipv4_FrameLoopback + ipv4_Wrapper diff --git a/docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst b/docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst index d551fa49..07212aee 100644 --- a/docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst +++ b/docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv4/ipv4_FrameLoopback.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv4/ipv4_FrameLoopback_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:ipv4_FrameLoopback: ipv4_FrameLoopback ################## @@ -14,7 +29,6 @@ ipv4_FrameLoopback :linenos: :lines: 42-74 -Source file: `net/ipv4/ipv4_FrameLoopback.vhdl `_ - +Source file: :pocsrc:`net/ipv4/ipv4_FrameLoopback.vhdl ` diff --git a/docs/IPCores/net/ipv4/ipv4_RX.rst b/docs/IPCores/net/ipv4/ipv4_RX.rst index 71f65197..635c8c7e 100644 --- a/docs/IPCores/net/ipv4/ipv4_RX.rst +++ b/docs/IPCores/net/ipv4/ipv4_RX.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv4/ipv4_RX.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv4/ipv4_RX_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:ipv4_RX: ipv4_RX ####### @@ -14,7 +29,6 @@ ipv4_RX :linenos: :lines: 42-82 -Source file: `net/ipv4/ipv4_RX.vhdl `_ - +Source file: :pocsrc:`net/ipv4/ipv4_RX.vhdl ` diff --git a/docs/IPCores/net/ipv4/ipv4_TX.rst b/docs/IPCores/net/ipv4/ipv4_TX.rst index c7143b05..74c27035 100644 --- a/docs/IPCores/net/ipv4/ipv4_TX.rst +++ b/docs/IPCores/net/ipv4/ipv4_TX.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv4/ipv4_TX.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv4/ipv4_TX_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:ipv4_TX: ipv4_TX ####### @@ -14,7 +29,6 @@ ipv4_TX :linenos: :lines: 42-81 -Source file: `net/ipv4/ipv4_TX.vhdl `_ - +Source file: :pocsrc:`net/ipv4/ipv4_TX.vhdl ` diff --git a/docs/IPCores/net/ipv4/ipv4_Wrapper.rst b/docs/IPCores/net/ipv4/ipv4_Wrapper.rst index 587c5e1e..2255d2e0 100644 --- a/docs/IPCores/net/ipv4/ipv4_Wrapper.rst +++ b/docs/IPCores/net/ipv4/ipv4_Wrapper.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv4/ipv4_Wrapper.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv4/ipv4_Wrapper_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:ipv4_Wrapper: ipv4_Wrapper ############ @@ -14,7 +29,6 @@ ipv4_Wrapper :linenos: :lines: 42-112 -Source file: `net/ipv4/ipv4_Wrapper.vhdl `_ - +Source file: :pocsrc:`net/ipv4/ipv4_Wrapper.vhdl ` diff --git a/docs/IPCores/net/ipv6/index.rst b/docs/IPCores/net/ipv6/index.rst index ca51fd7e..205edfb8 100644 --- a/docs/IPCores/net/ipv6/index.rst +++ b/docs/IPCores/net/ipv6/index.rst @@ -1,12 +1,13 @@ +.. _NS:ipv6: -ipv6 -==== +PoC.net.ipv6 +============ These are ipv6 entities.... .. toctree:: - ipv6_RX - ipv6_TX - ipv6_FrameLoopback - ipv6_Wrapper + ipv6_RX + ipv6_TX + ipv6_FrameLoopback + ipv6_Wrapper diff --git a/docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst b/docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst index 8262fcc3..5a0daced 100644 --- a/docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst +++ b/docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv6/ipv6_FrameLoopback.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv6/ipv6_FrameLoopback_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:ipv6_FrameLoopback: ipv6_FrameLoopback ################## @@ -14,7 +29,6 @@ ipv6_FrameLoopback :linenos: :lines: 42-74 -Source file: `net/ipv6/ipv6_FrameLoopback.vhdl `_ - +Source file: :pocsrc:`net/ipv6/ipv6_FrameLoopback.vhdl ` diff --git a/docs/IPCores/net/ipv6/ipv6_RX.rst b/docs/IPCores/net/ipv6/ipv6_RX.rst index c364261b..8a3da845 100644 --- a/docs/IPCores/net/ipv6/ipv6_RX.rst +++ b/docs/IPCores/net/ipv6/ipv6_RX.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv6/ipv6_RX.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv6/ipv6_RX_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:ipv6_RX: ipv6_RX ####### @@ -14,7 +29,6 @@ ipv6_RX :linenos: :lines: 42-84 -Source file: `net/ipv6/ipv6_RX.vhdl `_ - +Source file: :pocsrc:`net/ipv6/ipv6_RX.vhdl ` diff --git a/docs/IPCores/net/ipv6/ipv6_TX.rst b/docs/IPCores/net/ipv6/ipv6_TX.rst index 48dfb6ff..4014f33f 100644 --- a/docs/IPCores/net/ipv6/ipv6_TX.rst +++ b/docs/IPCores/net/ipv6/ipv6_TX.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv6/ipv6_TX.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv6/ipv6_TX_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:ipv6_TX: ipv6_TX ####### @@ -14,7 +29,6 @@ ipv6_TX :linenos: :lines: 42-84 -Source file: `net/ipv6/ipv6_TX.vhdl `_ - +Source file: :pocsrc:`net/ipv6/ipv6_TX.vhdl ` diff --git a/docs/IPCores/net/ipv6/ipv6_Wrapper.rst b/docs/IPCores/net/ipv6/ipv6_Wrapper.rst index 20470586..c7ed9000 100644 --- a/docs/IPCores/net/ipv6/ipv6_Wrapper.rst +++ b/docs/IPCores/net/ipv6/ipv6_Wrapper.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv6/ipv6_Wrapper.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv6/ipv6_Wrapper_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:ipv6_Wrapper: ipv6_Wrapper ############ @@ -14,7 +29,6 @@ ipv6_Wrapper :linenos: :lines: 42-116 -Source file: `net/ipv6/ipv6_Wrapper.vhdl `_ - +Source file: :pocsrc:`net/ipv6/ipv6_Wrapper.vhdl ` diff --git a/docs/IPCores/net/mac/index.rst b/docs/IPCores/net/mac/index.rst index 88884649..e4cf7704 100644 --- a/docs/IPCores/net/mac/index.rst +++ b/docs/IPCores/net/mac/index.rst @@ -1,16 +1,17 @@ +.. _NS:mac: -mac -=== +PoC.net.mac +=========== These are mac entities.... .. toctree:: - mac_RX_DestMAC_Switch - mac_RX_SrcMAC_Filter - mac_RX_Type_Switch - mac_TX_SrcMAC_Prepender - mac_TX_DestMAC_Prepender - mac_TX_Type_Prepender - mac_FrameLoopback - mac_Wrapper + mac_RX_DestMAC_Switch + mac_RX_SrcMAC_Filter + mac_RX_Type_Switch + mac_TX_SrcMAC_Prepender + mac_TX_DestMAC_Prepender + mac_TX_Type_Prepender + mac_FrameLoopback + mac_Wrapper diff --git a/docs/IPCores/net/mac/mac_FrameLoopback.rst b/docs/IPCores/net/mac/mac_FrameLoopback.rst index 9306aa6e..5d0c016b 100644 --- a/docs/IPCores/net/mac/mac_FrameLoopback.rst +++ b/docs/IPCores/net/mac/mac_FrameLoopback.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_FrameLoopback.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_FrameLoopback_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:mac_FrameLoopback: mac_FrameLoopback ################# @@ -14,7 +29,6 @@ mac_FrameLoopback :linenos: :lines: 42-72 -Source file: `net/mac/mac_FrameLoopback.vhdl `_ - +Source file: :pocsrc:`net/mac/mac_FrameLoopback.vhdl ` diff --git a/docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst b/docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst index f030f20b..7af23c2c 100644 --- a/docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst +++ b/docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_RX_DestMAC_Switch.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_RX_DestMAC_Switch_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:mac_RX_DestMAC_Switch: mac_RX_DestMAC_Switch ##################### @@ -14,7 +29,6 @@ mac_RX_DestMAC_Switch :linenos: :lines: 42-67 -Source file: `net/mac/mac_RX_DestMAC_Switch.vhdl `_ - +Source file: :pocsrc:`net/mac/mac_RX_DestMAC_Switch.vhdl ` diff --git a/docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst b/docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst index 5a167feb..ecb00675 100644 --- a/docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst +++ b/docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_RX_SrcMAC_Filter.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_RX_SrcMAC_Filter_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:mac_RX_SrcMAC_Filter: mac_RX_SrcMAC_Filter #################### @@ -14,7 +29,6 @@ mac_RX_SrcMAC_Filter :linenos: :lines: 42-72 -Source file: `net/mac/mac_RX_SrcMAC_Filter.vhdl `_ - +Source file: :pocsrc:`net/mac/mac_RX_SrcMAC_Filter.vhdl ` diff --git a/docs/IPCores/net/mac/mac_RX_Type_Switch.rst b/docs/IPCores/net/mac/mac_RX_Type_Switch.rst index 895056a6..46417d5d 100644 --- a/docs/IPCores/net/mac/mac_RX_Type_Switch.rst +++ b/docs/IPCores/net/mac/mac_RX_Type_Switch.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_RX_Type_Switch.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_RX_Type_Switch_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:mac_RX_Type_Switch: mac_RX_Type_Switch ################## @@ -14,7 +29,6 @@ mac_RX_Type_Switch :linenos: :lines: 42-74 -Source file: `net/mac/mac_RX_Type_Switch.vhdl `_ - +Source file: :pocsrc:`net/mac/mac_RX_Type_Switch.vhdl ` diff --git a/docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst b/docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst index 84ae9d79..905376b9 100644 --- a/docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst +++ b/docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_TX_DestMAC_Prepender.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_TX_DestMAC_Prepender_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:mac_TX_DestMAC_Prepender: mac_TX_DestMAC_Prepender ######################## @@ -14,7 +29,6 @@ mac_TX_DestMAC_Prepender :linenos: :lines: 42-65 -Source file: `net/mac/mac_TX_DestMAC_Prepender.vhdl `_ - +Source file: :pocsrc:`net/mac/mac_TX_DestMAC_Prepender.vhdl ` diff --git a/docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst b/docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst index c2dcf82c..56749127 100644 --- a/docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst +++ b/docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_TX_SrcMAC_Prepender.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_TX_SrcMAC_Prepender_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:mac_TX_SrcMAC_Prepender: mac_TX_SrcMAC_Prepender ####################### @@ -14,7 +29,6 @@ mac_TX_SrcMAC_Prepender :linenos: :lines: 42-69 -Source file: `net/mac/mac_TX_SrcMAC_Prepender.vhdl `_ - +Source file: :pocsrc:`net/mac/mac_TX_SrcMAC_Prepender.vhdl ` diff --git a/docs/IPCores/net/mac/mac_TX_Type_Prepender.rst b/docs/IPCores/net/mac/mac_TX_Type_Prepender.rst index fcb6f29e..184b7132 100644 --- a/docs/IPCores/net/mac/mac_TX_Type_Prepender.rst +++ b/docs/IPCores/net/mac/mac_TX_Type_Prepender.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_TX_Type_Prepender.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_TX_Type_Prepender_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:mac_TX_Type_Prepender: mac_TX_Type_Prepender ##################### @@ -14,7 +29,6 @@ mac_TX_Type_Prepender :linenos: :lines: 42-69 -Source file: `net/mac/mac_TX_Type_Prepender.vhdl `_ - +Source file: :pocsrc:`net/mac/mac_TX_Type_Prepender.vhdl ` diff --git a/docs/IPCores/net/mac/mac_Wrapper.rst b/docs/IPCores/net/mac/mac_Wrapper.rst index 16be2b8a..bf728d43 100644 --- a/docs/IPCores/net/mac/mac_Wrapper.rst +++ b/docs/IPCores/net/mac/mac_Wrapper.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_Wrapper.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_Wrapper_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:mac_Wrapper: mac_Wrapper ########### @@ -14,7 +29,6 @@ mac_Wrapper :linenos: :lines: 42-84 -Source file: `net/mac/mac_Wrapper.vhdl `_ - +Source file: :pocsrc:`net/mac/mac_Wrapper.vhdl ` diff --git a/docs/IPCores/net/ndp/index.rst b/docs/IPCores/net/ndp/index.rst index f054b692..5d718eae 100644 --- a/docs/IPCores/net/ndp/index.rst +++ b/docs/IPCores/net/ndp/index.rst @@ -1,12 +1,13 @@ +.. _NS:ndp: -ndp -=== +PoC.net.ndp +=========== These are ndp entities.... .. toctree:: - ndp_DestinationCache - ndp_FSMQuery - ndp_NeighborCache - ndp_Wrapper + ndp_DestinationCache + ndp_FSMQuery + ndp_NeighborCache + ndp_Wrapper diff --git a/docs/IPCores/net/ndp/ndp_DestinationCache.rst b/docs/IPCores/net/ndp/ndp_DestinationCache.rst index b1ef4627..90721a73 100644 --- a/docs/IPCores/net/ndp/ndp_DestinationCache.rst +++ b/docs/IPCores/net/ndp/ndp_DestinationCache.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ndp/ndp_DestinationCache.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ndp/ndp_DestinationCache_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:ndp_DestinationCache: ndp_DestinationCache #################### @@ -14,7 +29,6 @@ ndp_DestinationCache :linenos: :lines: 42-65 -Source file: `net/ndp/ndp_DestinationCache.vhdl `_ - +Source file: :pocsrc:`net/ndp/ndp_DestinationCache.vhdl ` diff --git a/docs/IPCores/net/ndp/ndp_FSMQuery.rst b/docs/IPCores/net/ndp/ndp_FSMQuery.rst index 842125a4..ec3d5aa5 100644 --- a/docs/IPCores/net/ndp/ndp_FSMQuery.rst +++ b/docs/IPCores/net/ndp/ndp_FSMQuery.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ndp/ndp_FSMQuery.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ndp/ndp_FSMQuery_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:ndp_FSMQuery: ndp_FSMQuery ############ @@ -14,7 +29,6 @@ ndp_FSMQuery :linenos: :lines: 42-79 -Source file: `net/ndp/ndp_FSMQuery.vhdl `_ - +Source file: :pocsrc:`net/ndp/ndp_FSMQuery.vhdl ` diff --git a/docs/IPCores/net/ndp/ndp_NeighborCache.rst b/docs/IPCores/net/ndp/ndp_NeighborCache.rst index 7b5647c5..30d792e6 100644 --- a/docs/IPCores/net/ndp/ndp_NeighborCache.rst +++ b/docs/IPCores/net/ndp/ndp_NeighborCache.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ndp/ndp_NeighborCache.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ndp/ndp_NeighborCache_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:ndp_NeighborCache: ndp_NeighborCache ################# @@ -14,7 +29,6 @@ ndp_NeighborCache :linenos: :lines: 42-65 -Source file: `net/ndp/ndp_NeighborCache.vhdl `_ - +Source file: :pocsrc:`net/ndp/ndp_NeighborCache.vhdl ` diff --git a/docs/IPCores/net/ndp/ndp_Wrapper.rst b/docs/IPCores/net/ndp/ndp_Wrapper.rst index b7e5a34b..06ae73fb 100644 --- a/docs/IPCores/net/ndp/ndp_Wrapper.rst +++ b/docs/IPCores/net/ndp/ndp_Wrapper.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ndp/ndp_Wrapper.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ndp/ndp_Wrapper_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:NDP_Wrapper: NDP_Wrapper ########### @@ -14,7 +29,6 @@ NDP_Wrapper :linenos: :lines: 43-65 -Source file: `net/ndp/ndp_Wrapper.vhdl `_ - +Source file: :pocsrc:`net/ndp/ndp_Wrapper.vhdl ` diff --git a/docs/IPCores/net/net_FrameChecksum.rst b/docs/IPCores/net/net_FrameChecksum.rst index ed1530a3..f4ceb14f 100644 --- a/docs/IPCores/net/net_FrameChecksum.rst +++ b/docs/IPCores/net/net_FrameChecksum.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/net_FrameChecksum.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/net_FrameChecksum_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:net_FrameChecksum: net_FrameChecksum ################# @@ -14,7 +29,6 @@ net_FrameChecksum :linenos: :lines: 41-72 -Source file: `net/net_FrameChecksum.vhdl `_ - +Source file: :pocsrc:`net/net_FrameChecksum.vhdl ` diff --git a/docs/IPCores/net/net_FrameLoopback.rst b/docs/IPCores/net/net_FrameLoopback.rst index 71e0148a..c3e4be93 100644 --- a/docs/IPCores/net/net_FrameLoopback.rst +++ b/docs/IPCores/net/net_FrameLoopback.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/net_FrameLoopback.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/net_FrameLoopback_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:FrameLoopback: FrameLoopback ############# @@ -14,7 +29,6 @@ FrameLoopback :linenos: :lines: 41-65 -Source file: `net/net_FrameLoopback.vhdl `_ - +Source file: :pocsrc:`net/net_FrameLoopback.vhdl ` diff --git a/docs/IPCores/net/net_FramePerformanceCounter.rst b/docs/IPCores/net/net_FramePerformanceCounter.rst index 0ed18f58..cbb9f29b 100644 --- a/docs/IPCores/net/net_FramePerformanceCounter.rst +++ b/docs/IPCores/net/net_FramePerformanceCounter.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/net_FramePerformanceCounter.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/net_FramePerformanceCounter_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:LocalLink_PerformanceCounter: LocalLink_PerformanceCounter ############################ @@ -12,7 +27,6 @@ LocalLink_PerformanceCounter :linenos: :lines: 11-35 -Source file: `net/net_FramePerformanceCounter.vhdl `_ - +Source file: :pocsrc:`net/net_FramePerformanceCounter.vhdl ` diff --git a/docs/IPCores/net/stack/index.rst b/docs/IPCores/net/stack/index.rst index 21b64c1f..2513173d 100644 --- a/docs/IPCores/net/stack/index.rst +++ b/docs/IPCores/net/stack/index.rst @@ -1,13 +1,14 @@ +.. _NS:stack: -stack -===== +PoC.net.stack +============= These are udp entities.... .. toctree:: - stack_IPv4 - stack_IPv6 - stack_UDPv4 - stack_UDPv6 - stack_MAC + stack_IPv4 + stack_IPv6 + stack_UDPv4 + stack_UDPv6 + stack_MAC diff --git a/docs/IPCores/net/stack/stack_UDPv4.rst b/docs/IPCores/net/stack/stack_UDPv4.rst index fbaf061d..afc9b2e8 100644 --- a/docs/IPCores/net/stack/stack_UDPv4.rst +++ b/docs/IPCores/net/stack/stack_UDPv4.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/stack/stack_UDPv4.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/stack/stack_UDPv4_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:stack_UDPv4: stack_UDPv4 ########### @@ -14,7 +29,6 @@ stack_UDPv4 :linenos: :lines: 44-111 -Source file: `net/stack/stack_UDPv4.vhdl `_ - +Source file: :pocsrc:`net/stack/stack_UDPv4.vhdl ` diff --git a/docs/IPCores/net/udp/index.rst b/docs/IPCores/net/udp/index.rst index e58e8535..bbc99c00 100644 --- a/docs/IPCores/net/udp/index.rst +++ b/docs/IPCores/net/udp/index.rst @@ -1,12 +1,13 @@ +.. _NS:udp: -udp -=== +PoC.net.udp +=========== These are udp entities.... .. toctree:: - udp_RX - udp_TX - udp_FrameLoopback - udp_Wrapper + udp_RX + udp_TX + udp_FrameLoopback + udp_Wrapper diff --git a/docs/IPCores/net/udp/udp_FrameLoopback.rst b/docs/IPCores/net/udp/udp_FrameLoopback.rst index eb379923..6cd1292c 100644 --- a/docs/IPCores/net/udp/udp_FrameLoopback.rst +++ b/docs/IPCores/net/udp/udp_FrameLoopback.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/udp/udp_FrameLoopback.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/udp/udp_FrameLoopback_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:udp_FrameLoopback: udp_FrameLoopback ################# @@ -14,7 +29,6 @@ udp_FrameLoopback :linenos: :lines: 42-77 -Source file: `net/udp/udp_FrameLoopback.vhdl `_ - +Source file: :pocsrc:`net/udp/udp_FrameLoopback.vhdl ` diff --git a/docs/IPCores/net/udp/udp_RX.rst b/docs/IPCores/net/udp/udp_RX.rst index 80d4854a..e79611ea 100644 --- a/docs/IPCores/net/udp/udp_RX.rst +++ b/docs/IPCores/net/udp/udp_RX.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/udp/udp_RX.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/udp/udp_RX_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:udp_RX: udp_RX ###### @@ -14,7 +29,6 @@ udp_RX :linenos: :lines: 42-95 -Source file: `net/udp/udp_RX.vhdl `_ - +Source file: :pocsrc:`net/udp/udp_RX.vhdl ` diff --git a/docs/IPCores/net/udp/udp_TX.rst b/docs/IPCores/net/udp/udp_TX.rst index 9c8cdb84..e6745093 100644 --- a/docs/IPCores/net/udp/udp_TX.rst +++ b/docs/IPCores/net/udp/udp_TX.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/udp/udp_TX.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/udp/udp_TX_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:udp_TX: udp_TX ###### @@ -14,7 +29,6 @@ udp_TX :linenos: :lines: 42-78 -Source file: `net/udp/udp_TX.vhdl `_ - +Source file: :pocsrc:`net/udp/udp_TX.vhdl ` diff --git a/docs/IPCores/net/udp/udp_Wrapper.rst b/docs/IPCores/net/udp/udp_Wrapper.rst index 01d8c187..9f375442 100644 --- a/docs/IPCores/net/udp/udp_Wrapper.rst +++ b/docs/IPCores/net/udp/udp_Wrapper.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/udp/udp_Wrapper.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/udp/udp_Wrapper_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:udp_Wrapper: udp_Wrapper ########### @@ -14,7 +29,6 @@ udp_Wrapper :linenos: :lines: 42-120 -Source file: `net/udp/udp_Wrapper.vhdl `_ - +Source file: :pocsrc:`net/udp/udp_Wrapper.vhdl ` diff --git a/docs/IPCores/sim/index.rst b/docs/IPCores/sim/index.rst index 4eb0873b..680789e1 100644 --- a/docs/IPCores/sim/index.rst +++ b/docs/IPCores/sim/index.rst @@ -1,3 +1,4 @@ +.. _PKG_Sim: Simulation Packages ################### diff --git a/docs/IPCores/sort/index.rst b/docs/IPCores/sort/index.rst index c9993826..11139acc 100644 --- a/docs/IPCores/sort/index.rst +++ b/docs/IPCores/sort/index.rst @@ -1,31 +1,32 @@ +.. _NS:sort: -sort -==== +PoC.sort +======== These are sorting entities.... **Sub-Namespaces** - * :doc:`PoC.sort.sortnet ` + * :ref:`NS:sortnet` **Entities** - * :doc:`PoC.sort.ExpireList ` - * :doc:`PoC.sort.InsertSort ` - * :doc:`PoC.sort.LeastFrequentlyUsed ` - * :doc:`PoC.sort.lru_cache ` - * :doc:`PoC.sort.lru_list ` + * :ref:`IP:sort_ExpireList` + * :ref:`IP:sort_InsertSort` + * :ref:`IP:sort_LeastFrequentlyUsed` + * :ref:`IP:sort_lru_cache` + * :ref:`IP:sort_lru_list` .. toctree:: :hidden: - sortnet/index + sortnet .. toctree:: :hidden: - sort_ExpireList - sort_InsertSort - sort_LeastFrequentlyUsed - sort_lru_cache - sort_lru_list + sort_ExpireList + sort_InsertSort + sort_LeastFrequentlyUsed + sort_lru_cache + sort_lru_list diff --git a/docs/IPCores/sort/sort_ExpireList.rst b/docs/IPCores/sort/sort_ExpireList.rst index f73f680c..c69703b9 100644 --- a/docs/IPCores/sort/sort_ExpireList.rst +++ b/docs/IPCores/sort/sort_ExpireList.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sort_ExpireList.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sort_ExpireList_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:list_expire: list_expire ########### @@ -14,7 +29,6 @@ list_expire :linenos: :lines: 42-61 -Source file: `sort/sort_ExpireList.vhdl `_ - +Source file: :pocsrc:`sort/sort_ExpireList.vhdl ` diff --git a/docs/IPCores/sort/sort_InsertSort.rst b/docs/IPCores/sort/sort_InsertSort.rst index 8bcb56f4..2c77a188 100644 --- a/docs/IPCores/sort/sort_InsertSort.rst +++ b/docs/IPCores/sort/sort_InsertSort.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sort_InsertSort.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sort_InsertSort_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:list_lru_systolic: list_lru_systolic ################# @@ -14,7 +29,6 @@ list_lru_systolic :linenos: :lines: 44-64 -Source file: `sort/sort_InsertSort.vhdl `_ - +Source file: :pocsrc:`sort/sort_InsertSort.vhdl ` diff --git a/docs/IPCores/sort/sort_LeastFrequentlyUsed.rst b/docs/IPCores/sort/sort_LeastFrequentlyUsed.rst index ac1d9ea8..58059f94 100644 --- a/docs/IPCores/sort/sort_LeastFrequentlyUsed.rst +++ b/docs/IPCores/sort/sort_LeastFrequentlyUsed.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sort_LeastFrequentlyUsed.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sort_LeastFrequentlyUsed_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:sort_LeastFrequentlyUsed: sort_LeastFrequentlyUsed ######################## @@ -14,7 +29,6 @@ sort_LeastFrequentlyUsed :linenos: :lines: 36-53 -Source file: `sort/sort_LeastFrequentlyUsed.vhdl `_ - +Source file: :pocsrc:`sort/sort_LeastFrequentlyUsed.vhdl ` diff --git a/docs/IPCores/sort/sort_lru_cache.rst b/docs/IPCores/sort/sort_lru_cache.rst index 870aaf75..59feed50 100644 --- a/docs/IPCores/sort/sort_lru_cache.rst +++ b/docs/IPCores/sort/sort_lru_cache.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sort_lru_cache.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sort_lru_cache_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:sort_lru_cache: sort_lru_cache ############## @@ -28,7 +43,6 @@ Supported operations: :linenos: :lines: 56-70 -Source file: `sort/sort_lru_cache.vhdl `_ - +Source file: :pocsrc:`sort/sort_lru_cache.vhdl ` diff --git a/docs/IPCores/sort/sort_lru_list.rst b/docs/IPCores/sort/sort_lru_list.rst index 8a199844..d595a965 100644 --- a/docs/IPCores/sort/sort_lru_list.rst +++ b/docs/IPCores/sort/sort_lru_list.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sort_lru_list.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sort_lru_list_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:sort_lru_list: sort_lru_list ############# @@ -26,7 +41,6 @@ Supported operations: :linenos: :lines: 55-74 -Source file: `sort/sort_lru_list.vhdl `_ - +Source file: :pocsrc:`sort/sort_lru_list.vhdl ` diff --git a/docs/IPCores/sort/sortnet/index.rst b/docs/IPCores/sort/sortnet/index.rst index e62cee53..444581a0 100644 --- a/docs/IPCores/sort/sortnet/index.rst +++ b/docs/IPCores/sort/sortnet/index.rst @@ -1,26 +1,28 @@ +.. _NS:sortnet: -sortnet -======== +PoC.sort.sortnet +================ This sub-namespace contains sorting network implementations. **Entities** - * :doc:`PoC.sort.sortnet.BitonicSort ` - * :doc:`PoC.sort.sortnet.MergeSort_Streamed ` - * :doc:`PoC.sort.sortnet.OddEvenMergeSort ` - * :doc:`PoC.sort.sortnet.OddEvenSort ` - * :doc:`PoC.sort.sortnet.Stream_Adapter ` - * :doc:`PoC.sort.sortnet.Stream_Adapter2 ` - * :doc:`PoC.sort.sortnet.Transform ` + * :ref:`IP:sortnet_BitonicSort` + * :ref:`IP:sortnet_MergeSort_Streamed` + * :ref:`IP:sortnet_OddEvenMergeSort` + * :ref:`IP:sortnet_OddEvenSort` + * :ref:`IP:sortnet_Stream_Adapter` + * :ref:`IP:sortnet_Stream_Adapter2` + * :ref:`IP:sortnet_Transform` + .. toctree:: :hidden: - sortnet_BitonicSort - sortnet_MergeSort_Streamed - sortnet_OddEvenMergeSort - sortnet_OddEvenSort - sortnet_Stream_Adapter - sortnet_Stream_Adapter2 - sortnet_Transform + sortnet_BitonicSort + sortnet_MergeSort_Streamed + sortnet_OddEvenMergeSort + sortnet_OddEvenSort + sortnet_Stream_Adapter + sortnet_Stream_Adapter2 + sortnet_Transform diff --git a/docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst b/docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst index 9addb1d6..48e2095a 100644 --- a/docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst +++ b/docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_BitonicSort.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:sortnet_BitonicSort: sortnet_BitonicSort ################### @@ -17,7 +32,6 @@ This sorting network uses the *bitonic sort* algorithm. :linenos: :lines: 46-72 -Source file: `sort/sortnet/sortnet_BitonicSort.vhdl `_ - +Source file: :pocsrc:`sort/sortnet/sortnet_BitonicSort.vhdl ` diff --git a/docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst b/docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst index 88d64260..1a50a964 100644 --- a/docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst +++ b/docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_MergeSort_Streamed.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_MergeSort_Streamed_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:sortnet_MergeSort_Streamed: sortnet_MergeSort_Streamed ########################## @@ -14,7 +29,6 @@ sortnet_MergeSort_Streamed :linenos: :lines: 41-68 -Source file: `sort/sortnet/sortnet_MergeSort_Streamed.vhdl `_ - +Source file: :pocsrc:`sort/sortnet/sortnet_MergeSort_Streamed.vhdl ` diff --git a/docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst b/docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst index 88007f23..db8e2923 100644 --- a/docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst +++ b/docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_OddEvenMergeSort.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:sortnet_OddEvenMergeSort: sortnet_OddEvenMergeSort ######################## @@ -14,7 +29,6 @@ sortnet_OddEvenMergeSort :linenos: :lines: 43-69 -Source file: `sort/sortnet/sortnet_OddEvenMergeSort.vhdl `_ - +Source file: :pocsrc:`sort/sortnet/sortnet_OddEvenMergeSort.vhdl ` diff --git a/docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst b/docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst index 32a53603..758fd9e3 100644 --- a/docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst +++ b/docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_OddEvenSort.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:sortnet_OddEvenSort: sortnet_OddEvenSort ################### @@ -14,7 +29,6 @@ sortnet_OddEvenSort :linenos: :lines: 42-68 -Source file: `sort/sortnet/sortnet_OddEvenSort.vhdl `_ - +Source file: :pocsrc:`sort/sortnet/sortnet_OddEvenSort.vhdl ` diff --git a/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst index 21e0f97a..55d6c869 100644 --- a/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst +++ b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_Stream_Adapter.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_Stream_Adapter_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:sortnet_Stream_Adapter: sortnet_Stream_Adapter ###################### @@ -14,7 +29,6 @@ sortnet_Stream_Adapter :linenos: :lines: 42-68 -Source file: `sort/sortnet/sortnet_Stream_Adapter.vhdl `_ - +Source file: :pocsrc:`sort/sortnet/sortnet_Stream_Adapter.vhdl ` diff --git a/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst index 6d893c7e..b81d5f56 100644 --- a/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst +++ b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_Stream_Adapter2.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_Stream_Adapter2_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:sortnet_Stream_Adapter2: sortnet_Stream_Adapter2 ####################### @@ -14,7 +29,6 @@ sortnet_Stream_Adapter2 :linenos: :lines: 42-76 -Source file: `sort/sortnet/sortnet_Stream_Adapter2.vhdl `_ - +Source file: :pocsrc:`sort/sortnet/sortnet_Stream_Adapter2.vhdl ` diff --git a/docs/IPCores/sort/sortnet/sortnet_Transform.rst b/docs/IPCores/sort/sortnet/sortnet_Transform.rst index 503e4450..f1d59223 100644 --- a/docs/IPCores/sort/sortnet/sortnet_Transform.rst +++ b/docs/IPCores/sort/sortnet/sortnet_Transform.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_Transform.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_Transform_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:sortnet_Transform: sortnet_Transform ################# @@ -14,7 +29,6 @@ sortnet_Transform :linenos: :lines: 41-61 -Source file: `sort/sortnet/sortnet_Transform.vhdl `_ - +Source file: :pocsrc:`sort/sortnet/sortnet_Transform.vhdl ` diff --git a/docs/IPCores/xil/index.rst b/docs/IPCores/xil/index.rst index 9d89b376..b5420586 100644 --- a/docs/IPCores/xil/index.rst +++ b/docs/IPCores/xil/index.rst @@ -1,42 +1,48 @@ +.. _NS:xil: -xil -=== +PoC.xil +======== This namespace is for Xilinx specific modules. **Sub-Namespaces** - * :doc:`PoC.xil.mig ` - * :doc:`PoC.xil.reconfig ` + * :ref:`NS:mig` + * :ref:`NS:reconfig` **Entities** - * :doc:`PoC.xil.BSCAN ` - * :doc:`PoC.xil.ChipScopeICON ` - * :doc:`PoC.xil.DRP_BusMux ` - * :doc:`PoC.xil.DRP_BusSync ` - * :doc:`PoC.xil.ICAP ` - * :doc:`PoC.xil.Reconfigurator ` - * :doc:`PoC.xil.SystemMonitor ` - * :doc:`PoC.xil.SystemMonitor_Virtex6 ` - * :doc:`PoC.xil.SystemMonitor_Series7 ` + * :ref:`IP:xil_BSCAN` + * :ref:`IP:xil_ChipScopeICON` + * :ref:`IP:xil_DRP_BusMux` + * :ref:`IP:xil_DRP_BusSync` + * :ref:`IP:xil_ICAP` + * :ref:`IP:xil_Reconfigurator` + * :ref:`IP:xil_SystemMonitor` + * :ref:`IP:xil_SystemMonitor_Virtex6` + * :ref:`IP:xil_SystemMonitor_Series7` .. toctree:: :hidden: - mig/index - reconfig/index + mig + reconfig .. toctree:: :hidden: - xil_BSCAN - xil_ChipScopeICON - xil_DRP_BusMux - xil_DRP_BusSync - xil_ICAP - xil_Reconfigurator - xil_SystemMonitor - xil_SystemMonitor_Virtex6 - xil_SystemMonitor_Series7 + Package + +.. toctree:: + :hidden: + + xil_BSCAN + xil_ChipScopeICON + xil_DRP_BusMux + xil_DRP_BusSync + xil_ICAP + xil_Reconfigurator + xil_SystemMonitor + xil_SystemMonitor_Virtex6 + xil_SystemMonitor_Series7 diff --git a/docs/IPCores/xil/mig/index.rst b/docs/IPCores/xil/mig/index.rst index 001fd816..bd2d9961 100644 --- a/docs/IPCores/xil/mig/index.rst +++ b/docs/IPCores/xil/mig/index.rst @@ -1,17 +1,18 @@ +.. _NS:mig: -mig -=== +PoC.xil.mig +=========== The namespace ``PoC.xil.mig`` offers pre-configured memory controllers generated with Xilinx's Memory Interface Generator (MIG). * **for Spartan-6 boards:** - * :doc:`mig_Atlys_1x128 ` - A DDR2 memory controller for the Digilent Atlys board. + * :ref:`mig_Atlys_1x128 ` - A DDR2 memory controller for the Digilent Atlys board. * **for Kintex-7 boards:** - * :doc:`mig_KC705_MT8JTF12864HZ_1G6 ` - A DDR3 memory controller for the Xilinx KC705 board. + * :ref:`mig_KC705_MT8JTF12864HZ_1G6 ` - A DDR3 memory controller for the Xilinx KC705 board. * **for Virtex-7 boards:** @@ -19,5 +20,5 @@ with Xilinx's Memory Interface Generator (MIG). .. toctree:: :hidden: - mig_Atlys_1x128 - mig_KC705_MT8JTF12864HZ_1G6 + mig_Atlys_1x128 + mig_KC705_MT8JTF12864HZ_1G6 diff --git a/docs/IPCores/xil/mig/mig_Atlys_1x128.rst b/docs/IPCores/xil/mig/mig_Atlys_1x128.rst index 337b1f3a..5acdcb4e 100644 --- a/docs/IPCores/xil/mig/mig_Atlys_1x128.rst +++ b/docs/IPCores/xil/mig/mig_Atlys_1x128.rst @@ -1,3 +1,4 @@ +.. _IP:mig_Atlys_1x128: mig_Atlys_1x128 ############### diff --git a/docs/IPCores/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rst b/docs/IPCores/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rst index 5e66ef52..75f7caf4 100644 --- a/docs/IPCores/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rst +++ b/docs/IPCores/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rst @@ -1,3 +1,4 @@ +.. _IP:mig_KC705_MT8JTF12864HZ_1G6: mig_KC705_MT8JTF12864HZ_1G6 ########################### diff --git a/docs/IPCores/xil/reconfig/index.rst b/docs/IPCores/xil/reconfig/index.rst index 0f84f4d5..079beba3 100644 --- a/docs/IPCores/xil/reconfig/index.rst +++ b/docs/IPCores/xil/reconfig/index.rst @@ -1,16 +1,17 @@ +.. _NS:reconfig: -reconfig -======== +PoC.xil.reconfig +================ These are reconfig entities.... **Entities** - * :doc:`PoC.xil.reconfig.icap_fsm ` - * :doc:`PoC.xil.reconfig.icap_wrapper ` + * :ref:`IP:reconfig_icap_fsm` + * :ref:`IP:reconfig_icap_wrapper` .. toctree:: :hidden: - reconfig_icap_fsm - reconfig_icap_wrapper + reconfig_icap_fsm + reconfig_icap_wrapper diff --git a/docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst b/docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst index 3a53c1b4..82937980 100644 --- a/docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst +++ b/docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/reconfig/reconfig_icap_fsm.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/reconfig/reconfig_icap_fsm_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:reconfig_icap_fsm: reconfig_icap_fsm ################# @@ -18,7 +33,6 @@ primitives to generate control signals. Tested on: :linenos: :lines: 42-63 -Source file: `xil/reconfig/reconfig_icap_fsm.vhdl `_ - +Source file: :pocsrc:`xil/reconfig/reconfig_icap_fsm.vhdl ` diff --git a/docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst b/docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst index baabe148..4caa2e01 100644 --- a/docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst +++ b/docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/reconfig/reconfig_icap_wrapper.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/reconfig/reconfig_icap_wrapper_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:reconfig_icap_wrapper: reconfig_icap_wrapper ##################### @@ -17,7 +32,6 @@ tbd :linenos: :lines: 43-68 -Source file: `xil/reconfig/reconfig_icap_wrapper.vhdl `_ - +Source file: :pocsrc:`xil/reconfig/reconfig_icap_wrapper.vhdl ` diff --git a/docs/IPCores/xil/xil_BSCAN.rst b/docs/IPCores/xil/xil_BSCAN.rst index 2eb45615..ac44d30f 100644 --- a/docs/IPCores/xil/xil_BSCAN.rst +++ b/docs/IPCores/xil/xil_BSCAN.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_BSCAN.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_BSCAN_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:xil_BSCAN: xil_BSCAN ######### @@ -19,7 +34,6 @@ Supported devices are: :linenos: :lines: 47-65 -Source file: `xil/xil_BSCAN.vhdl `_ - +Source file: :pocsrc:`xil/xil_BSCAN.vhdl ` diff --git a/docs/IPCores/xil/xil_ChipScopeICON.rst b/docs/IPCores/xil/xil_ChipScopeICON.rst index ee254a98..381740a0 100644 --- a/docs/IPCores/xil/xil_ChipScopeICON.rst +++ b/docs/IPCores/xil/xil_ChipScopeICON.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_ChipScopeICON.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_ChipScopeICON_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:xil_ChipScopeICON: xil_ChipScopeICON ################# @@ -27,7 +42,7 @@ the needed source and netlist files on your local machine. :linenos: :lines: 56-63 -Source file: `xil/xil_ChipScopeICON.vhdl `_ +Source file: :pocsrc:`xil/xil_ChipScopeICON.vhdl ` .. seealso:: @@ -35,4 +50,3 @@ Source file: `xil/xil_ChipScopeICON.vhdl ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:xil_DRP_BusMux: xil_DRP_BusMux ############## @@ -14,7 +29,6 @@ xil_DRP_BusMux :linenos: :lines: 42-65 -Source file: `xil/xil_DRP_BusMux.vhdl `_ - +Source file: :pocsrc:`xil/xil_DRP_BusMux.vhdl ` diff --git a/docs/IPCores/xil/xil_DRP_BusSync.rst b/docs/IPCores/xil/xil_DRP_BusSync.rst index 31baf6b0..c398d6e1 100644 --- a/docs/IPCores/xil/xil_DRP_BusSync.rst +++ b/docs/IPCores/xil/xil_DRP_BusSync.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_DRP_BusSync.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_DRP_BusSync_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:xil_DRP_BusSync: xil_DRP_BusSync ############### @@ -14,7 +29,6 @@ xil_DRP_BusSync :linenos: :lines: 40-58 -Source file: `xil/xil_DRP_BusSync.vhdl `_ - +Source file: :pocsrc:`xil/xil_DRP_BusSync.vhdl ` diff --git a/docs/IPCores/xil/xil_ICAP.rst b/docs/IPCores/xil/xil_ICAP.rst index b445d6a9..ab2b8468 100644 --- a/docs/IPCores/xil/xil_ICAP.rst +++ b/docs/IPCores/xil/xil_ICAP.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_ICAP.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_ICAP_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:xil_ICAP: xil_ICAP ######## @@ -19,7 +34,6 @@ Supported devices are: :linenos: :lines: 47-66 -Source file: `xil/xil_ICAP.vhdl `_ - +Source file: :pocsrc:`xil/xil_ICAP.vhdl ` diff --git a/docs/IPCores/xil/xil_Reconfigurator.rst b/docs/IPCores/xil/xil_Reconfigurator.rst index 99f35b93..1efa9174 100644 --- a/docs/IPCores/xil/xil_Reconfigurator.rst +++ b/docs/IPCores/xil/xil_Reconfigurator.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_Reconfigurator.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_Reconfigurator_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:xil_Reconfigurator: xil_Reconfigurator ################## @@ -22,7 +37,6 @@ completes with another strobe on ``ReconfigDone``. :linenos: :lines: 51-72 -Source file: `xil/xil_Reconfigurator.vhdl `_ - +Source file: :pocsrc:`xil/xil_Reconfigurator.vhdl ` diff --git a/docs/IPCores/xil/xil_SystemMonitor.rst b/docs/IPCores/xil/xil_SystemMonitor.rst index 43a64195..5fb4952a 100644 --- a/docs/IPCores/xil/xil_SystemMonitor.rst +++ b/docs/IPCores/xil/xil_SystemMonitor.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_SystemMonitor.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_SystemMonitor_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:xil_SystemMonitor: xil_SystemMonitor ################# @@ -32,7 +47,6 @@ monitors (normal, user temperature, over temperature). :linenos: :lines: 62-73 -Source file: `xil/xil_SystemMonitor.vhdl `_ - +Source file: :pocsrc:`xil/xil_SystemMonitor.vhdl ` diff --git a/docs/IPCores/xil/xil_SystemMonitor_Series7.rst b/docs/IPCores/xil/xil_SystemMonitor_Series7.rst index 23d050ce..4c1c1f32 100644 --- a/docs/IPCores/xil/xil_SystemMonitor_Series7.rst +++ b/docs/IPCores/xil/xil_SystemMonitor_Series7.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_SystemMonitor_Series7.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_SystemMonitor_Series7_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:xil_SystemMonitor_Series7: xil_SystemMonitor_Series7 ######################### @@ -31,7 +46,6 @@ are overrun. The XADC was formerly known as "System Monitor". :linenos: :lines: 56-66 -Source file: `xil/xil_SystemMonitor_Series7.vhdl `_ - +Source file: :pocsrc:`xil/xil_SystemMonitor_Series7.vhdl ` diff --git a/docs/IPCores/xil/xil_SystemMonitor_Virtex6.rst b/docs/IPCores/xil/xil_SystemMonitor_Virtex6.rst index a56624dc..ec135982 100644 --- a/docs/IPCores/xil/xil_SystemMonitor_Virtex6.rst +++ b/docs/IPCores/xil/xil_SystemMonitor_Virtex6.rst @@ -1,3 +1,18 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_SystemMonitor_Virtex6.vhdl + :alt: Source Code on GitHub +.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_SystemMonitor_Virtex6_tb.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. _IP:xil_SystemMonitor_Virtex6: xil_SystemMonitor_Virtex6 ######################### @@ -31,7 +46,6 @@ temperature values are overrun. :linenos: :lines: 56-66 -Source file: `xil/xil_SystemMonitor_Virtex6.vhdl `_ - +Source file: :pocsrc:`xil/xil_SystemMonitor_Virtex6.vhdl ` diff --git a/docs/Interfaces/CommandStatusError.rst b/docs/Interfaces/CommandStatusError.rst index d7207f10..0e5582f9 100644 --- a/docs/Interfaces/CommandStatusError.rst +++ b/docs/Interfaces/CommandStatusError.rst @@ -1,6 +1,7 @@ +.. _Int:PoC.CSE: -PoC.CSE -####### +Command-Status-Error (PoC.CSE) Interface +######################################## .. TODO:: Define the PoC.CSE (Command-Status-Error) interface used in ... diff --git a/docs/Interfaces/FIFO.rst b/docs/Interfaces/FIFO.rst new file mode 100644 index 00000000..9ab680c5 --- /dev/null +++ b/docs/Interfaces/FIFO.rst @@ -0,0 +1,7 @@ +.. _Int:PoC.FIFO: + +PoC.FIFO Interface +################## + +.. TODO:: + Define the PoC.FIFO interface (writer and reader) used in ``PoC.fifo.*`` ... diff --git a/docs/Interfaces/Memory.rst b/docs/Interfaces/Memory.rst index 76eae7bf..752b3b67 100644 --- a/docs/Interfaces/Memory.rst +++ b/docs/Interfaces/Memory.rst @@ -1,6 +1,7 @@ +.. _Int:PoC.Mem: -PoC.Mem -####### +PoC.Mem Interface +################# PoC.Mem is a single-cycle, pipelined memory interface used by various memory controllers and related components like caches. Memory accesses diff --git a/docs/Interfaces/Stream.rst b/docs/Interfaces/Stream.rst index 38ef2d0f..3fd04d7b 100644 --- a/docs/Interfaces/Stream.rst +++ b/docs/Interfaces/Stream.rst @@ -1,6 +1,7 @@ +.. _Int:PoC.Stream: -PoC.Stream -########## +PoC.Stream Interface +#################### .. TODO:: Define the PoC.Stream interface used in PoC.net.* and ``PoC.bus.stream.*`` ... diff --git a/docs/Interfaces/index.rst b/docs/Interfaces/index.rst index 7d67c720..1ab58f20 100644 --- a/docs/Interfaces/index.rst +++ b/docs/Interfaces/index.rst @@ -1,3 +1,4 @@ +.. _Int: IP Core Interfaces ################## @@ -5,7 +6,8 @@ IP Core Interfaces .. toctree:: :maxdepth: 1 - CommandStatusError - Memory - Stream + PoC.CSE + PoC.FIFO + PoC.Mem + PoC.Stream diff --git a/docs/Miscelaneous/ThirdParty.rst b/docs/Miscelaneous/ThirdParty.rst index 100c6429..d772867f 100644 --- a/docs/Miscelaneous/ThirdParty.rst +++ b/docs/Miscelaneous/ThirdParty.rst @@ -5,6 +5,7 @@ The PoC-Library is shiped with different third party libraries, which are located in the ``/lib/`` folder. This document lists all these libraries, their websites and licenses. +.. _ThirdParty:Cocotb: Cocotb ****** @@ -17,13 +18,14 @@ library for writing VHDL and Verilog testbenches in Python. +--------------------+-----------------------------------------------------------------------------------------------------------+ | **Copyright:** | Copyright © 2013, `Potential Ventures Ltd. `_, SolarFlare Communications Inc. | +--------------------+-----------------------------------------------------------------------------------------------------------+ -| **License:** | :doc:`Revised BSD License (local copy) ` | +| **License:** | :doc:`Revised BSD License (local copy) ` | +--------------------+-----------------------------------------------------------------------------------------------------------+ | **Documentation:** | `http://cocotb.readthedocs.org/ `_ | +--------------------+-----------------------------------------------------------------------------------------------------------+ | **Source:** | `https://github.com/potentialventures/cocotb `_ | +--------------------+-----------------------------------------------------------------------------------------------------------+ +.. _ThirdParty:OSVVM: OSVVM ***** @@ -48,7 +50,7 @@ existing testbench or testbench models. | **Source:** | `https://github.com/JimLewis/OSVVM `_ | +----------------+---------------------------------------------------------------------------------------+ - +.. _ThirdParty:UVVM: UVVM **** @@ -74,13 +76,14 @@ the ``uart_receive()`` or ``axilite_write()`` BFM respectively. +----------------+---------------------------------------------------------------------------------------+ | **Copyright:** | Copyright © 2016 by `Bitvis AS `_ | +----------------+---------------------------------------------------------------------------------------+ -| **License:** | :doc:`The MIT License (local copy) ` | +| **License:** | :doc:`The MIT License (local copy) ` | +----------------+---------------------------------------------------------------------------------------+ | **Website:** | `http://bitvis.no/ `_ | +----------------+---------------------------------------------------------------------------------------+ | **Source:** | `https://github.com/UVVM/UVVM_All `_ | +----------------+---------------------------------------------------------------------------------------+ +.. _ThirdParty:VUnit: VUnit ***** diff --git a/docs/QuickStart.rst b/docs/QuickStart.rst index 0fbfd28e..58efbe27 100644 --- a/docs/QuickStart.rst +++ b/docs/QuickStart.rst @@ -39,15 +39,32 @@ See :doc:`/UsingPoC/Requirements` for further details. .. rubric:: PoC depends on third part libraries: -* `Cocotb `_ |br| +* :ref:`ThirdParty:Cocotb` |gh-cocotb| |br| A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python. -* `OS-VVM `_ |br| +* :ref:`ThirdParty:OSVVM` |gh-osvvm| |br| Open Source VHDL Verification Methodology. -* `UVVM `_ |br| +* :ref:`ThirdParty:UVVM` |gh-uvvm| |br| Universal VHDL Verification Methodology. -* `VUnit `_ |br| +* :ref:`ThirdParty:VUnit` |gh-vunit| |br| An unit testing framework for VHDL. +.. |gh-cocotb| image:: _static/logos/GitHub-Mark-32px.png + :scale: 50 + :target: https://github.com/potentialventures/cocotb + :alt: Source Code on GitHub +.. |gh-osvvm| image:: _static/logos/GitHub-Mark-32px.png + :scale: 50 + :target: https://github.com/JimLewis/OSVVM + :alt: Source Code on GitHub +.. |gh-uvvm| image:: _static/logos/GitHub-Mark-32px.png + :scale: 50 + :target: https://github.com/UVVM/UVVM_All + :alt: Source Code on GitHub +.. |gh-vunit| image:: _static/logos/GitHub-Mark-32px.png + :scale: 50 + :target: https://github.com/VUnit/vunit + :alt: Source Code on GitHub + All dependencies are available as GitHub repositories and are linked to PoC as Git submodules into the `PoCRoot\\lib `_ directory. See :doc:`Third Party Libraries ` for more details on these libraries. diff --git a/docs/References/CmdRefs/Compile-Altera-ps1.rst b/docs/References/CmdRefs/Compile-Altera-ps1.rst index d9d0f88b..f15e9560 100644 --- a/docs/References/CmdRefs/Compile-Altera-ps1.rst +++ b/docs/References/CmdRefs/Compile-Altera-ps1.rst @@ -1,6 +1,27 @@ compile-altera.ps1 ------------------ +.. program:: compile-altera.ps1 + +This script pre-compiles the Altera primitives. This script will generate all +outputs into a :file:`altera` directory. + + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + + +.. rubric:: Command Line Options + .. option:: -Help Show the embedded help page(s). @@ -21,10 +42,24 @@ compile-altera.ps1 Pre-compile the Altera Quartus libraries for QuestaSim. + +.. rubric:: Additional Options for GHDL + .. option:: -VHDL93 - Set VHDL Standard to '93. + For GHDL only: Set VHDL Standard to '93. .. option:: -VHDL2008 - Set VHDL Standard to '08. + For GHDL only: Set VHDL Standard to '08. + + +.. rubric:: GHDL Notes + +Not all primitives and macros are available as plain VHDL source code. Encrypted +primitives and netlists cannot be pre-compiled by GHDL. + + +.. rubric:: QuestaSim Notes + +The pre-compilation for QuestaSim uses a build in program from Altera. diff --git a/docs/References/CmdRefs/Compile-Altera-sh.rst b/docs/References/CmdRefs/Compile-Altera-sh.rst index 9b0ea31c..72b37394 100644 --- a/docs/References/CmdRefs/Compile-Altera-sh.rst +++ b/docs/References/CmdRefs/Compile-Altera-sh.rst @@ -1,6 +1,27 @@ compile-altera.sh ----------------- +.. program:: compile-altera.sh + +This script pre-compiles the Altera primitives. This script will generate all +outputs into a :file:`altera` directory. + + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + + +.. rubric:: Command Line Options + .. option:: --help Show the embedded help page(s). @@ -21,10 +42,24 @@ compile-altera.sh Pre-compile the Altera Quartus libraries for QuestaSim. + +.. rubric:: Additional Options for GHDL + .. option:: --vhdl93 - Set VHDL Standard to '93. + For GHDL only: Set VHDL Standard to '93. .. option:: --vhdl2008 - Set VHDL Standard to '08. + For GHDL only: Set VHDL Standard to '08. + + +.. rubric:: GHDL Notes + +Not all primitives and macros are available as plain VHDL source code. Encrypted +primitives and netlists cannot be pre-compiled by GHDL. + + +.. rubric:: QuestaSim Notes + +The pre-compilation for QuestaSim uses a build in program from Altera. diff --git a/docs/References/CmdRefs/Compile-Lattice-ps1.rst b/docs/References/CmdRefs/Compile-Lattice-ps1.rst index 87955ead..228c5470 100644 --- a/docs/References/CmdRefs/Compile-Lattice-ps1.rst +++ b/docs/References/CmdRefs/Compile-Lattice-ps1.rst @@ -1,6 +1,27 @@ compile-lattice.ps1 ------------------- +.. program:: compile-lattice.ps1 + +This script pre-compiles the Lattice primitives. This script will generate all +outputs into a :file:`lattice` directory. + + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + + +.. rubric:: Command Line Options + .. option:: -Help Show the embedded help page(s). @@ -21,10 +42,24 @@ compile-lattice.ps1 Pre-compile the Altera Quartus libraries for QuestaSim. + +.. rubric:: Additional Options for GHDL + .. option:: -VHDL93 - Set VHDL Standard to '93. + For GHDL only: Set VHDL Standard to '93. .. option:: -VHDL2008 - Set VHDL Standard to '08. + For GHDL only: Set VHDL Standard to '08. + + +.. rubric:: GHDL Notes + +Not all primitives and macros are available as plain VHDL source code. Encrypted +primitives and netlists cannot be pre-compiled by GHDL. + + +.. rubric:: QuestaSim Notes + +The pre-compilation for QuestaSim uses a build in program from Lattice. diff --git a/docs/References/CmdRefs/Compile-Lattice-sh.rst b/docs/References/CmdRefs/Compile-Lattice-sh.rst index d19189ec..6f8df6b9 100644 --- a/docs/References/CmdRefs/Compile-Lattice-sh.rst +++ b/docs/References/CmdRefs/Compile-Lattice-sh.rst @@ -1,6 +1,27 @@ compile-lattice.sh ------------------ +.. program:: compile-lattice.sh + +This script pre-compiles the Lattice primitives. This script will generate all +outputs into a :file:`lattice` directory. + + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + + +.. rubric:: Command Line Options + .. option:: --help Show the embedded help page(s). @@ -21,10 +42,24 @@ compile-lattice.sh Pre-compile the Altera Quartus libraries for QuestaSim. + +.. rubric:: Additional Options for GHDL + .. option:: --vhdl93 - Set VHDL Standard to '93. + For GHDL only: Set VHDL Standard to '93. .. option:: --vhdl2008 - Set VHDL Standard to '08. + For GHDL only: Set VHDL Standard to '08. + + +.. rubric:: GHDL Notes + +Not all primitives and macros are available as plain VHDL source code. Encrypted +primitives and netlists cannot be pre-compiled by GHDL. + + +.. rubric:: QuestaSim Notes + +The pre-compilation for QuestaSim uses a build in program from Lattice. diff --git a/docs/References/CmdRefs/Compile-OSVVM-ps1.rst b/docs/References/CmdRefs/Compile-OSVVM-ps1.rst index 9a241e42..2eda7260 100644 --- a/docs/References/CmdRefs/Compile-OSVVM-ps1.rst +++ b/docs/References/CmdRefs/Compile-OSVVM-ps1.rst @@ -1,5 +1,26 @@ compile-osvvm.ps1 ------------------- +----------------- + +.. program:: compile-osvvm.ps1 + +This script pre-compiles the OSVVM packages. This script will generate all +outputs into a :file:`osvvm` directory. + + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + + +.. rubric:: Command Line Options .. option:: -Help @@ -21,10 +42,13 @@ compile-osvvm.ps1 Pre-compile the Altera Quartus libraries for QuestaSim. + +.. rubric:: Additional Options for GHDL + .. option:: -VHDL93 - Set VHDL Standard to '93. + For GHDL only: Set VHDL Standard to '93. .. option:: -VHDL2008 - Set VHDL Standard to '08. + For GHDL only: Set VHDL Standard to '08. diff --git a/docs/References/CmdRefs/Compile-OSVVM-sh.rst b/docs/References/CmdRefs/Compile-OSVVM-sh.rst index 1081b79e..8b9f1334 100644 --- a/docs/References/CmdRefs/Compile-OSVVM-sh.rst +++ b/docs/References/CmdRefs/Compile-OSVVM-sh.rst @@ -1,6 +1,27 @@ compile-osvvm.sh ---------------- +.. program:: compile-osvvm.sh + +This script pre-compiles the OSVVM packages. This script will generate all +outputs into a :file:`osvvm` directory. + + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + + +.. rubric:: Command Line Options + .. option:: --help Show the embedded help page(s). @@ -21,10 +42,13 @@ compile-osvvm.sh Pre-compile the Altera Quartus libraries for QuestaSim. + +.. rubric:: Additional Options for GHDL + .. option:: --vhdl93 - Set VHDL Standard to '93. + For GHDL only: Set VHDL Standard to '93. .. option:: --vhdl2008 - Set VHDL Standard to '08. + For GHDL only: Set VHDL Standard to '08. diff --git a/docs/References/CmdRefs/Compile-UVVM-ps1.rst b/docs/References/CmdRefs/Compile-UVVM-ps1.rst index 6666ee36..41c34f50 100644 --- a/docs/References/CmdRefs/Compile-UVVM-ps1.rst +++ b/docs/References/CmdRefs/Compile-UVVM-ps1.rst @@ -1,6 +1,27 @@ compile-uvvm.ps1 ---------------- +.. program:: compile-uvvm.ps1 + +This script pre-compiles the UVVM framework. This script will generate all +outputs into a :file:`uvvm` directory. + + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + + +.. rubric:: Command Line Options + .. option:: -Help Show the embedded help page(s). @@ -21,10 +42,13 @@ compile-uvvm.ps1 Pre-compile the Altera Quartus libraries for QuestaSim. + +.. rubric:: Additional Options for GHDL + .. option:: -VHDL93 - Set VHDL Standard to '93. + For GHDL only: Set VHDL Standard to '93. .. option:: -VHDL2008 - Set VHDL Standard to '08. + For GHDL only: Set VHDL Standard to '08. diff --git a/docs/References/CmdRefs/Compile-UVVM-sh.rst b/docs/References/CmdRefs/Compile-UVVM-sh.rst index 35cac02f..0a3fd45f 100644 --- a/docs/References/CmdRefs/Compile-UVVM-sh.rst +++ b/docs/References/CmdRefs/Compile-UVVM-sh.rst @@ -1,6 +1,27 @@ compile-uvvm.sh --------------- +.. program:: compile-uvvm.sh + +This script pre-compiles the UVVM framework. This script will generate all +outputs into a :file:`uvvm` directory. + + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + + +.. rubric:: Command Line Options + .. option:: --help Show the embedded help page(s). @@ -21,10 +42,13 @@ compile-uvvm.sh Pre-compile the Altera Quartus libraries for QuestaSim. + +.. rubric:: Additional Options for GHDL + .. option:: --vhdl93 - Set VHDL Standard to '93. + For GHDL only: Set VHDL Standard to '93. .. option:: --vhdl2008 - Set VHDL Standard to '08. + For GHDL only: Set VHDL Standard to '08. diff --git a/docs/References/CmdRefs/Compile-Xilinx-ISE-ps1.rst b/docs/References/CmdRefs/Compile-Xilinx-ISE-ps1.rst index e756cf74..9b993b4d 100644 --- a/docs/References/CmdRefs/Compile-Xilinx-ISE-ps1.rst +++ b/docs/References/CmdRefs/Compile-Xilinx-ISE-ps1.rst @@ -1,6 +1,28 @@ compile-xilinx-ise.ps1 ---------------------- +.. program:: compile-xilinx-ise.ps1 + +This script pre-compiles the Xilinx primitives. Because Xilinx offers two tool +chains (ISE, Vivado), this script will generate all outputs into a +:file:`xilinx-ise` directory and a symlink to :file:`xilinx` will be created. +This eases the coexistence of pre-compiled primitives from ISE and Vivado. The +symlink can be changed by the user or via :option:`-ReLink`. + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + +.. rubric:: Command Line Options + .. option:: -Help Show the embedded help page(s). @@ -25,10 +47,24 @@ compile-xilinx-ise.ps1 Change the 'xilinx' symlink to 'xilinx-ise'. + +.. rubric:: Additional Options for GHDL + .. option:: -VHDL93 - Set VHDL Standard to '93. + For GHDL only: Set VHDL Standard to '93. .. option:: -VHDL2008 - Set VHDL Standard to '08. + For GHDL only: Set VHDL Standard to '08. + + +.. rubric:: GHDL Notes + +Not all primitives and macros are available as plain VHDL source code. Encrypted +SecureIP primitives and netlists cannot be pre-compiled by GHDL. + + +.. rubric:: QuestaSim Notes + +The pre-compilation for QuestaSim uses a build in program from Xilinx. diff --git a/docs/References/CmdRefs/Compile-Xilinx-ISE-sh.rst b/docs/References/CmdRefs/Compile-Xilinx-ISE-sh.rst index c8269385..36de7540 100644 --- a/docs/References/CmdRefs/Compile-Xilinx-ISE-sh.rst +++ b/docs/References/CmdRefs/Compile-Xilinx-ISE-sh.rst @@ -1,6 +1,29 @@ compile-xilinx-ise.sh --------------------- +.. program:: compile-xilinx-ise.sh + +This script pre-compiles the Xilinx primitives. Because Xilinx offers two tool +chains (ISE, Vivado), this script will generate all outputs into a +:file:`xilinx-ise` directory and a symlink to :file:`xilinx` will be created. +This eases the coexistence of pre-compiled primitives from ISE and Vivado. + +.. The symlink can be changed by the user or via :option:`--relink`. + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + +.. rubric:: Command Line Options + .. option:: --help Show the embedded help page(s). @@ -21,10 +44,24 @@ compile-xilinx-ise.sh Pre-compile the Altera Quartus libraries for QuestaSim. + +.. rubric:: Additional Options for GHDL + .. option:: --vhdl93 - Set VHDL Standard to '93. + For GHDL only: Set VHDL Standard to '93. .. option:: --vhdl2008 - Set VHDL Standard to '08. + For GHDL only: Set VHDL Standard to '08. + + +.. rubric:: GHDL Notes + +Not all primitives and macros are available as plain VHDL source code. Encrypted +SecureIP primitives and netlists cannot be pre-compiled by GHDL. + + +.. rubric:: QuestaSim Notes + +The pre-compilation for QuestaSim uses a build in program from Xilinx. diff --git a/docs/References/CmdRefs/Compile-Xilinx-Vivado-ps1.rst b/docs/References/CmdRefs/Compile-Xilinx-Vivado-ps1.rst index e48613b3..59a3aee7 100644 --- a/docs/References/CmdRefs/Compile-Xilinx-Vivado-ps1.rst +++ b/docs/References/CmdRefs/Compile-Xilinx-Vivado-ps1.rst @@ -1,6 +1,30 @@ compile-xilinx-vivado.ps1 ------------------------- +.. program:: compile-xilinx-vivado.ps1 + +This script pre-compiles the Xilinx primitives. Because Xilinx offers two tool +chains (ISE, Vivado), this script will generate all outputs into a +:file:`xilinx-vivado` directory and a symlink to :file:`xilinx` will be created. +This eases the coexistence of pre-compiled primitives from ISE and Vivado. The +symlink can be changed by the user or via :option:`-ReLink`. + + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + + +.. rubric:: Command Line Options + .. option:: -Help Show the embedded help page(s). @@ -25,10 +49,24 @@ compile-xilinx-vivado.ps1 Change the 'xilinx' symlink to 'xilinx-vivado'. + +.. rubric:: Additional Options for GHDL + .. option:: -VHDL93 - Set VHDL Standard to '93. + For GHDL only: Set VHDL Standard to '93. .. option:: -VHDL2008 - Set VHDL Standard to '08. + For GHDL only: Set VHDL Standard to '08. + + +.. rubric:: GHDL Notes + +Not all primitives and macros are available as plain VHDL source code. Encrypted +SecureIP primitives and netlists cannot be pre-compiled by GHDL. + + +.. rubric:: QuestaSim Notes + +The pre-compilation for QuestaSim uses a build in program from Xilinx. diff --git a/docs/References/CmdRefs/Compile-Xilinx-Vivado-sh.rst b/docs/References/CmdRefs/Compile-Xilinx-Vivado-sh.rst index 5ea1d216..73d32f49 100644 --- a/docs/References/CmdRefs/Compile-Xilinx-Vivado-sh.rst +++ b/docs/References/CmdRefs/Compile-Xilinx-Vivado-sh.rst @@ -1,6 +1,31 @@ compile-xilinx-vivado.sh ------------------------ +.. program:: compile-xilinx-vivado.sh + +This script pre-compiles the Xilinx primitives. Because Xilinx offers two tool +chains (ISE, Vivado), this script will generate all outputs into a +:file:`xilinx-vivado` directory and a symlink to :file:`xilinx` will be created. +This eases the coexistence of pre-compiled primitives from ISE and Vivado. + +.. The symlink can be changed by the user or via :option:`--relink`. + + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + + +.. rubric:: Command Line Options + .. option:: --help Show the embedded help page(s). @@ -21,10 +46,24 @@ compile-xilinx-vivado.sh Pre-compile the Altera Quartus libraries for QuestaSim. + +.. rubric:: Additional Options for GHDL + .. option:: --vhdl93 - Set VHDL Standard to '93. + For GHDL only: Set VHDL Standard to '93. .. option:: --vhdl2008 - Set VHDL Standard to '08. + For GHDL only: Set VHDL Standard to '08. + + +.. rubric:: GHDL Notes + +Not all primitives and macros are available as plain VHDL source code. Encrypted +SecureIP primitives and netlists cannot be pre-compiled by GHDL. + + +.. rubric:: QuestaSim Notes + +The pre-compilation for QuestaSim uses a build in program from Xilinx. diff --git a/docs/References/CmdRefs/Compile.rst b/docs/References/CmdRefs/Compile.rst new file mode 100644 index 00000000..a94aa06d --- /dev/null +++ b/docs/References/CmdRefs/Compile.rst @@ -0,0 +1,86 @@ +.. _CmdRef:PreCompile: + +Pre-compile Scripts +################### + +The following scripts can be used to pre-compile vendor's primitives or third +party libraries. Pre-compile vendor primitives are required for vendor specific +simulations or if no generic IP core implementation is available. Third party +libraries are usually used as simulation helpers and thus needed by many +testbenches. + +The pre-compiled packages and libraries are stored in the directory :file:`/temp/precompiled/`. +Per simulator, one :file:`/` sub-directory is created. Each simulator +directory in turn contains library directories, which may be grouped by the +library vendor's name: :file:`[/]/`. + +So for example: :ref:`ThirdParty:OSVVM` pre-compiled with GHDL is stored in +:file:`/temp/precompiled/ghdl/osvvm/`. Note OSVVM is a single library and thus +no vendor directory is used to group the generated files. GHDL will also create +VHDL language revision sub-directories like :file:`v93/` or :file:`v08/`. + +Currently the provided scripts support 2 simulator targets and one combined +target: + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + +The GHDL simulator distinguishes various VHDL language revisions and thus can +pre-compile the source for these language revisions into separate output +directories. The command line switch ``-All``/``--all`` will build the libraries +for all major VHDL revisions (93, 2008). + + +.. rubric:: Pre-compile Altera Libraries + +.. toctree:: + + Compile-Altera-ps1 + Compile-Altera-sh + + +.. rubric:: Pre-compile Lattice Libraries + +.. toctree:: + + Compile-Lattice-ps1 + Compile-Lattice-sh + + +.. rubric:: Pre-compile OSVVM Libraries + +.. toctree:: + + Compile-OSVVM-ps1 + Compile-OSVVM-sh + + +.. rubric:: Pre-compile UVVM Libraries + +.. toctree:: + + Compile-UVVM-ps1 + Compile-UVVM-sh + + +.. rubric:: Pre-compile Xilinx ISE Libraries + +.. toctree:: + + Compile-Xilinx-ISE-ps1 + Compile-Xilinx-ISE-sh + + +.. rubric:: Pre-compile Xilinx Vivado Libraries + +.. toctree:: + + Compile-Xilinx-Vivado-ps1 + Compile-Xilinx-Vivado-sh diff --git a/docs/References/CmdRefs/PoC-py.rst b/docs/References/CmdRefs/PoC.rst similarity index 57% rename from docs/References/CmdRefs/PoC-py.rst rename to docs/References/CmdRefs/PoC.rst index d1f2943e..1889563f 100644 --- a/docs/References/CmdRefs/PoC-py.rst +++ b/docs/References/CmdRefs/PoC.rst @@ -1,5 +1,14 @@ .. This files requires a Python module called 'PoCSphinx' to be located in the docs root folder. It expects a variable 'parser' of type ArgumentParser. +.. _CmdRef:PoC: + +Main Programs +############# + +The main program :program:`PoC.py` expects the environment variable :envvar:`PoCRootDirectory` +to be set. + + .. autoprogram:: PoCSphinx:parser :prog: PoC.py diff --git a/docs/References/CmdRefs/Wrapper.rst b/docs/References/CmdRefs/Wrapper.rst new file mode 100644 index 00000000..705d9069 --- /dev/null +++ b/docs/References/CmdRefs/Wrapper.rst @@ -0,0 +1,59 @@ +.. _CmdRef:Wrapper: + +PoC Wrapper Scripts +################### + +The PoC main program :program:`PoC.py` requires a prepared environment, which +needs to be setup by platform specific wrapper scripts written as shell +scripts language (PowerShell/Bash). Moreover, the main program requires a +supported Python version, so the wrapper script will search the best matching +language environment. + +The wrapper script offers the ability to hook in user-defined scripts to prepared +(before) and clean up the environment (after) a PoC execution. E.g. it's possible +to load the environment variable :envvar:`LM_LICENSE_FILE` for the FlexLM license +manager. + + +.. rubric:: Created Environment Variables + +.. envvar:: PoCRootDirectory + + The path to PoC's root directory. + +--------------------------------- + +poc.ps1 +======== + +.. program:: poc.ps1 + +:file:`PoC.ps1` is the wrapper for the Windows platform using a PowerShell script. +It can be debugged by adding the command line switch :option:`-D`. All parameters +are passed to :file:`PoC.py`. + +.. option:: -D + + Enabled debug mode in the wrapper script. + +.. describe:: Other arguments + + All remaining arguments are passed to :file:`PoC.py`. + + +poc.sh +====== + +.. program:: poc.sh + +:file:`PoC.sh` is the wrapper for Linux and Unix platforms using a Bash script. +It can be debugged by adding the command line switch :option:`-D`. All parameters +are passed to :file:`PoC.py`. + +.. option:: -D + + Enabled debug mode in the wrapper script. + +.. describe:: Other arguments + + All remaining arguments are passed to :file:`PoC.py`. diff --git a/docs/References/CommandReference.rst b/docs/References/CommandReference.rst index e7466e77..9ca2eded 100644 --- a/docs/References/CommandReference.rst +++ b/docs/References/CommandReference.rst @@ -1,82 +1,13 @@ +.. _CmdRef: Command Reference ################# -.. contents:: Contents of this Page - -PoC Wrapper Scripts -******************* - -poc.ps1 -======== - - - -poc.sh -====== - - -PoC Main Program -**************** - -.. toctree:: - - CmdRefs/PoC-py - - -Pre-compile Scripts -******************* - -Pre-compile Altera Libraries -============================ - -.. toctree:: - - CmdRefs/Compile-Altera-ps1 - CmdRefs/Compile-Altera-sh - - -Pre-compile Lattice Libraries -============================= - -.. toctree:: - - CmdRefs/Compile-Lattice-ps1 - CmdRefs/Compile-Lattice-sh - - -Pre-compile OSVVM Libraries -=========================== - -.. toctree:: - - CmdRefs/Compile-OSVVM-ps1 - CmdRefs/Compile-OSVVM-sh - - -Pre-compile UVVM Libraries -========================== - -.. toctree:: - - CmdRefs/Compile-UVVM-ps1 - CmdRefs/Compile-UVVM-sh - - -Pre-compile Xilinx ISE Libraries -================================ - - -.. toctree:: - - CmdRefs/Compile-Xilinx-ISE-ps1 - CmdRefs/Compile-Xilinx-ISE-sh - - -Pre-compile Xilinx Vivado Libraries -=================================== +This is the command line option reference for all provided scripts +(Bash, PowerShell, Perl) and programs (Python) shipped with PoC. .. toctree:: - CmdRefs/Compile-Xilinx-Vivado-ps1 - CmdRefs/Compile-Xilinx-Vivado-sh + CmdRefs/Wrapper + CmdRefs/PoC + CmdRefs/Compile diff --git a/docs/References/Database.rst b/docs/References/Database.rst index fdaedc98..21ef4b76 100644 --- a/docs/References/Database.rst +++ b/docs/References/Database.rst @@ -1,3 +1,4 @@ +.. _IPDB: IP Core Database ################ @@ -9,49 +10,53 @@ Overview ******** PoC internal IP core database uses INI files and advanced interpolation rules -provided by ExtendedConfigParser_. -The database consists of 5 *.ini files which are in-memory merge to a single -configuration database: +provided by ExtendedConfigParser_. The database consists of 5 *.ini files: -* ``py\config.boards.ini`` +* :file:`py\config.boards.ini` This files contains all known :doc:`FPGA boards ` and :doc:`FPGA devices `. -* ``py\config.defaults.ini`` - This files contains all default options and values for all supported nodes +* :file:`py\config.defaults.ini` + This files contains all default options and values for all supported node types. -* ``py\config.entity.ini`` +* :file:`py\config.entity.ini` This file contains all IP cores (entities) and theirs corresponding testbench or netlist settings. -* ``py\config.private.ini`` - This files is created by ``.\poc.ps1 configure`` and contains settings for these +* :file:`py\config.private.ini` + This files is created by ``.\poc.ps1 configure`` and contains settings for the local PoC installation. This files must not be shared with other PoC instances. See :doc:`Configuring PoC's Infrastructure ` on how to configure PoC on a local system. -* ``py\config.structure.ini`` - Nodes in these file describe PoC's namespace tree and which IP cores are +* :file:`py\config.structure.ini` + Nodes in this file describe PoC's namespace tree and which IP cores are assigned to which namespace. -Additionally, the database refers to *.files and *.rules files. The first file -type describes in an imperative langauge, which files are needed to compile a -simulation or to run a synthesis. the latter file type comprises patch -instructions per IP core. See :doc:`Files Format ` and -:doc:`Rules Format ` for more details. +Additionally, the database refers to :ref:`*.files ` +and :ref:`*.rules ` files. The first file type describes, in +an imperative language, which files are needed to compile a simulation or to +run a synthesis. The latter file type contains patch instructions per IP core. +See :ref:`Files Formats ` for more details. .. _ExtendedConfigParser: https://github.com/Paebbels/ExtendedConfigParser + +.. _IPDB:Structure: + Database Structure ****************** -The database is stored in *.ini files, which define an associative array of -`sections` and option lines. The content itself is an associative array of -`options` and values. Section names are inclosed in square brackets ``[...]`` -and allow simple strings as names. A section name is case-sensitive. It is -followed by its section content, which consists of option lines. +The database is stored in multiple :ref:`INI files `, +which are merged in memory to a single configuration database. Each INI file +defines an associative array of *sections* and option lines. The content itself +is an associative array of *options* and values. Section names are inclosed in +square brackets ``[...]`` and allow simple case-sensitive strings as names. A +section name is followed by its section content, which consists of option lines. -One option is stored per line. An option name is a case-sensitive simple string -separated by an equal sign ``=`` from its value. The value is string, starts -after the first non-whitespace character and end before the newline character at -the line end. The content can be of any character string. +One option is stored per option line and consists of an option name and a value +separated by an equal sign ``=``. The option name is also a case-sensitive +simple string. The value is string, starts after the first non-whitespace +character and end before the newline character at the end of the line. The +content can be of any string, except for the newline characters. Support for +escape sequences depends on the option usage. Values containing ``${...}`` and ``%{...}`` are raw values, which need to be interpolated by the ExtendedConfigParser. See `Value Interpolation`_ and @@ -61,26 +66,6 @@ Sections can have a default section called ``DEFAULT``. Options not found in a normal section are looked up in the default section. If found, the value of the matching option name is the lookup result. -.. productionlist:: - Document: `DocumentLine`* - DocumentLine: `SpecialSection` | `Section` | `CommentLine` | `EmptyLine` - CommentLine: "#" `CommentText` `LineBreak` - EmptyLine: `WhiteSpace`* `LineBreak` - SpecialSection: "[" `SimpleString` "]" - : (`OptionLine`)* - Section: "[" `FQSectionName` "]" - : (`OptionLine`)* - OptionLine: `Reference` | `Option` | `UserDefVariable` - Reference: `ReferenceName` `WhiteSpace`* "=" `WhiteSpace`* `Keyword` - Option: `OptionName` `WhiteSpace`* "=" `WhiteSpace`* `OptionValue` - UserDefVariable: `VariableName` `WhiteSpace`* "=" `WhiteSpace`* `VariableValue` - FQSectionName: `Prefix` "." `SectionName` - SectionName: `SectionNamePart` ("." `SectionNamePart`)* - SectionNamePart: `SimpleString` - ReferenceName: `SimpleString` - OptionName: `SimpleString` - VariableName: `SimpleString` - .. rubric:: Example .. code-block:: ini @@ -93,10 +78,56 @@ matching option name is the lookup result. option1 = ${section1:option1} opt2 = ${option1} -.. topic:: **foo bar** - | wichtige hinweise - | 2 leerzeichen +Option lines can be of three kinds: An option, a reference, or a user defined +variable. While the syntax is always the same, the meaning is infered from the +context. + ++---------------------------+-----------------------------------------------------------------+ +| Option Line Kind | Distinguishing Characteristic | ++===========================+=================================================================+ +| **Reference** | The option name is called a (node) reference, if the value\ | +| | of an option is a predefined keyword for the current node\ | +| | class. Because the option's value is a keyword, it can not\ | +| | be an interpolated value. | ++---------------------------+-----------------------------------------------------------------+ +| **Option** | The option uses a defined option name valid for the current\ | +| | node class. The value can be a fixed or interpolated string. | ++---------------------------+-----------------------------------------------------------------+ +| **User Defined Variable** | Otherwise an option line is a user defined variable. It can\ | +| | have fixed or interpolated string values. | ++---------------------------+-----------------------------------------------------------------+ + +.. code-block:: ini + + [PoC] + Name = + Prefix = + arith = Namespace + bus = Namespace + + [PoC.arith] + addw = Entity + prng = Entity + + [PoC.bus] + stream = Namespace + wb = Namespace + Arbiter = Entity + + [PoC.bus.stream] + Buffer = Entity + DeMux = Entity + Mirror = Entity + Mux = Entity + + [PoC.bus.wb] + fifo_adapter = Entity + ocram_adapter = Entity + uart_wrapper = Entity + + +.. _IPDB:Nodes: Nodes ===== @@ -174,54 +205,8 @@ hierarchical database. The parent node is ``PoC.bus`` and its grandparent is ``PoC``. (Note this is a special section. See the special sections table from above.) -Option lines can be of three kinds: - -+---------------------------+-----------------------------------------------------------------+ -| Option Line Kind | Distinguishing Characteristic | -+===========================+=================================================================+ -| **Reference** | The option name is called a (node) reference, if the value\ | -| | of an option is a predefined keyword for the current node\ | -| | class. Because the option's value is a keyword, it can not\ | -| | be an interpolated value. | -+---------------------------+-----------------------------------------------------------------+ -| **Option** | The option uses a defined option name valid for the current\ | -| | node class. The value can be a fixed or interpolated string. | -+---------------------------+-----------------------------------------------------------------+ -| **User Defined Variable** | Otherwise an option line is a user defined variable. It can\ | -| | have fixed or interpolated string values. | -+---------------------------+-----------------------------------------------------------------+ - -.. code-block:: ini - - [PoC] - Name = - Prefix = - arith = Namespace - bus = Namespace - - [PoC.arith] - addw = Entity - prng = Entity - - [PoC.bus] - stream = Namespace - wb = Namespace - Arbiter = Entity - - [PoC.bus.stream] - Buffer = Entity - DeMux = Entity - Mirror = Entity - Mux = Entity - - [PoC.bus.wb] - fifo_adapter = Entity - ocram_adapter = Entity - uart_wrapper = Entity - - - +.. _IPDB:Refs: References ========== @@ -231,18 +216,32 @@ References :Whatever: this is handy to create new field +.. _IPDB:Options: + Options ======== + +.. _IPDB:Values: + Values ====== + +.. _IPDB:ValueInterpol: + Value Interpolation =================== + +.. _IPDB:NodeInterpol: + Node Interpolation ================== + +.. _IPDB:Roots: + Root Nodes ========== @@ -254,21 +253,42 @@ Supported Options See ``py\config.defaults.ini`` for predefined default values (options) and predefined variables, which can be used as a shortcut. + +.. _IPDB:Files: + Files in detail *************** + + +.. _IPDB:File:Structure: + config.structure.ini ==================== + + +.. _IPDB:File:Entity: + config.entity.ini ================= + + +.. _IPDB:File:Boards: + config.boards.ini ================= + + +.. _IPDB:File:Private: + config.private.ini ================== +.. _IPDB:UserDefVar: + User Defined Variables ********************** @@ -276,4 +296,4 @@ User Defined Variables .. |date| date:: %d.%m.%Y .. |time| date:: %H:%M -This document was generated on |date| at |time|. + diff --git a/docs/References/FileFormats/FilesFormat.rst b/docs/References/FileFormats/FilesFormat.rst index e724121b..5187a0a2 100644 --- a/docs/References/FileFormats/FilesFormat.rst +++ b/docs/References/FileFormats/FilesFormat.rst @@ -1,3 +1,4 @@ +.. _FileFormat:files: *.files Format ############## diff --git a/docs/References/FileFormats/IniFormat.rst b/docs/References/FileFormats/IniFormat.rst new file mode 100644 index 00000000..f41b787f --- /dev/null +++ b/docs/References/FileFormats/IniFormat.rst @@ -0,0 +1,124 @@ +.. _FileFormat:ini: + +.. raw:: html + + + + + +*.ini Format +############ + +.. contents:: Contents of this Page + :local: + +**Document rule:** + +.. raw:: html + +
+ +
+ +**DocumentLine rule:** + +.. raw:: html + +
+ +
+ +**Section rule:** + +.. raw:: html + +
+ +
+ +**OptionLine rule:** + +.. raw:: html + +
+ +
+ +**FQSectionName rule:** + +.. raw:: html + +
+ +
+ + +.. + productionlist:: + Document: `DocumentLine`* + DocumentLine: `SpecialSection` | `Section` | `CommentLine` | `EmptyLine` + CommentLine: "#" `CommentText` `LineBreak` + EmptyLine: `WhiteSpace`* `LineBreak` + SpecialSection: "[" `SimpleString` "]" + : (`OptionLine`)* + Section: "[" `FQSectionName` "]" + : (`OptionLine`)* + OptionLine: `Reference` | `Option` | `UserDefVariable` + Reference: `ReferenceName` `WhiteSpace`* "=" `WhiteSpace`* `Keyword` + Option: `OptionName` `WhiteSpace`* "=" `WhiteSpace`* `OptionValue` + UserDefVariable: `VariableName` `WhiteSpace`* "=" `WhiteSpace`* `VariableValue` + FQSectionName: `Prefix` "." `SectionName` + SectionName: `SectionNamePart` ("." `SectionNamePart`)* + SectionNamePart: `SimpleString` + ReferenceName: `SimpleString` + OptionName: `SimpleString` + VariableName: `SimpleString` diff --git a/docs/References/FileFormats/RulesFormat.rst b/docs/References/FileFormats/RulesFormat.rst index 617ca121..887683b6 100644 --- a/docs/References/FileFormats/RulesFormat.rst +++ b/docs/References/FileFormats/RulesFormat.rst @@ -1,3 +1,4 @@ +.. _FileFormat:rules: *.rules Format ############## diff --git a/docs/References/FileFormats/index.rst b/docs/References/FileFormats/index.rst index a379df4e..b35d451d 100644 --- a/docs/References/FileFormats/index.rst +++ b/docs/References/FileFormats/index.rst @@ -1,3 +1,4 @@ +.. _FileFormats: File Formats ############ @@ -5,5 +6,6 @@ File Formats .. toctree:: :maxdepth: 1 + IniFormat FilesFormat RulesFormat diff --git a/docs/References/Licenses/CCLA.rst b/docs/References/Licenses/ApacheLicense2.0_CCLA.rst similarity index 98% rename from docs/References/Licenses/CCLA.rst rename to docs/References/Licenses/ApacheLicense2.0_CCLA.rst index 47f53e83..4147668f 100644 --- a/docs/References/Licenses/CCLA.rst +++ b/docs/References/Licenses/ApacheLicense2.0_CCLA.rst @@ -1,7 +1,9 @@ -.. image:: /_static/images/logo_tud.jpg +.. image:: /_static/logos/tu-dresden.jpg :scale: 10 :alt: Logo: Technische Universität Dresden +----------------------------------- + Modified Apache Corporate Contributor License Agreement v2.0 ############################################################ diff --git a/docs/References/Licenses/ICLA.rst b/docs/References/Licenses/ApacheLicense2.0_ICLA.rst similarity index 97% rename from docs/References/Licenses/ICLA.rst rename to docs/References/Licenses/ApacheLicense2.0_ICLA.rst index acf5b704..314020d2 100644 --- a/docs/References/Licenses/ICLA.rst +++ b/docs/References/Licenses/ApacheLicense2.0_ICLA.rst @@ -1,7 +1,9 @@ -.. image:: /_static/images/logo_tud.jpg +.. image:: /_static/logos/tu-dresden.jpg :scale: 10 :alt: Logo: Technische Universität Dresden +----------------------------------- + Modified Apache Contributor License Agreement v2.0 ################################################## @@ -86,7 +88,8 @@ and interest in and to Your Contributions. that you have received permission to make Contributions on behalf of that employer, that your employer has waived such rights for your Contributions to the Chair, or that your employer has - executed a separate :doc:`Corporate CLA ` with the Chair. + executed a separate :doc:`Corporate CLA ` + with the Chair. 5. You represent that each of Your Contributions is Your original creation (see section 7 for submissions on behalf of others). You diff --git a/docs/References/Licenses/BSDLicense_Cocotb.rst b/docs/References/Licenses/Cocotb_BSDLicense.rst similarity index 100% rename from docs/References/Licenses/BSDLicense_Cocotb.rst rename to docs/References/Licenses/Cocotb_BSDLicense.rst diff --git a/docs/References/Licenses/MIT_UVVM.rst b/docs/References/Licenses/UVVM_MIT.rst similarity index 100% rename from docs/References/Licenses/MIT_UVVM.rst rename to docs/References/Licenses/UVVM_MIT.rst diff --git a/docs/References/Licenses/index.rst b/docs/References/Licenses/index.rst index 4ca99541..1018632f 100644 --- a/docs/References/Licenses/index.rst +++ b/docs/References/Licenses/index.rst @@ -11,11 +11,11 @@ which contains a link to the orginal license file source. :maxdepth: 1 ApacheLicense2.0 - ICLA - CCLA + Apache License 2.0 - ICLA + Apache License 2.0 - CCLA ArtisticLicense2.0 - BSDLicense_Cocotb - MIT_UVVM + Cocotb - BSD License + UVVM - MIT License MozillaPublicLicense2.0 .. rubric:: Footnotes diff --git a/docs/References/NamingConventions.rst b/docs/References/NamingConventions.rst index 875e205d..cf6a715c 100644 --- a/docs/References/NamingConventions.rst +++ b/docs/References/NamingConventions.rst @@ -11,7 +11,7 @@ Root Directory Overview (PoCRoot) The PoC-Library is structured into several sub-directories, naming the purpose of the directory like ``src`` for sources files or ``tb`` for testbench files. The structure within these directories is most likely the same and based on -PoC's :doc:`sub-namespace tree `. PoC's installation directory is +PoC's :doc:`sub-namespace tree `. PoC's installation directory is also referred to as ``PoCRoot``. * ``lib`` @@ -40,7 +40,7 @@ also referred to as ``PoCRoot``. * ``src`` The source files of PoC's IP cores are stored in this directory. The IP cores are grouped by their sub-namespace into sub-directories according to - the :doc:`sub-namespace tree `. See the paragraph below, for + the :doc:`sub-namespace tree `. See the paragraph below, for how IP cores are named and how PoC core names map to the sub-namespace hierachy and the resulting sub-namespace directory structure. * ``tb`` diff --git a/docs/References/index.rst b/docs/References/index.rst deleted file mode 100644 index e31d6fa9..00000000 --- a/docs/References/index.rst +++ /dev/null @@ -1,16 +0,0 @@ - -References -########## - -.. toctree:: - :maxdepth: 1 - - NamingConventions - CommandReference - Database - WrapperScriptHookFiles - FileFormats/index - ListOfDevices - ListOfBoards - KnownIssues - Licenses/index diff --git a/docs/UsingPoC/Simulation.rst b/docs/UsingPoC/Simulation.rst index c48e1519..48407de8 100644 --- a/docs/UsingPoC/Simulation.rst +++ b/docs/UsingPoC/Simulation.rst @@ -287,6 +287,21 @@ QuestaSim: cd PoCRoot .\poc.ps1 vsim PoC.arith.prng --board=DE4 --gui +If QuestaSim is started in GUI mode (:option:`--gui`), PoC will provide several +Tcl files (:file:`*.do`) in the simulator's working directory to recompile, +restart or rerun the current simulation. The rerun command is based on the saved +IP core's run script, which may default to ``run -all``. + ++--------------------------+---------------------------------------------------------+ +| Tcl Script | Performed Tasks | ++==========================+=========================================================+ +| :file:`recompile.do` | recompile and restart | ++--------------------------+---------------------------------------------------------+ +| :file:`relaunch.do` | recompile, restart and rerun | ++--------------------------+---------------------------------------------------------+ +| :file:`saveWaveform.do` | save the current waveform viewer settings | ++--------------------------+---------------------------------------------------------+ + Xilinx ISE Simulator ==================== diff --git a/docs/_static/css/railroad-diagrams.css b/docs/_static/css/railroad-diagrams.css new file mode 100644 index 00000000..24db32fd --- /dev/null +++ b/docs/_static/css/railroad-diagrams.css @@ -0,0 +1,41 @@ +svg.railroad-diagram { + background-color: hsl(30,20%,95%); +} +svg.railroad-diagram path { + stroke-width: 3; + stroke: black; + fill: rgba(0,0,0,0); +} +svg.railroad-diagram text { + font: bold 14px monospace; + text-anchor: middle; +} +svg.railroad-diagram text.diagram-text { + font-size: 12px; +} +svg.railroad-diagram text.diagram-arrow { + font-size: 16px; +} +svg.railroad-diagram text.label { + text-anchor: start; +} +svg.railroad-diagram text.comment { + font: italic 12px monospace; +} +svg.railroad-diagram g.non-terminal text { + /*font-style: italic;*/ +} +svg.railroad-diagram rect { + stroke-width: 3; + stroke: black; + fill: hsl(120,100%,90%); +} +svg.railroad-diagram path.diagram-text { + stroke-width: 3; + stroke: black; + fill: white; + cursor: help; +} +svg.railroad-diagram g.diagram-text:hover path.diagram-text { + fill: #eee; +} diff --git a/docs/_static/javascript/railroad-diagrams.js b/docs/_static/javascript/railroad-diagrams.js new file mode 100644 index 00000000..f45f99e8 --- /dev/null +++ b/docs/_static/javascript/railroad-diagrams.js @@ -0,0 +1,893 @@ +"use strict"; +/* +Railroad Diagrams +by Tab Atkins Jr. (and others) +http://xanthir.com +http://twitter.com/tabatkins +http://github.com/tabatkins/railroad-diagrams + +This document and all associated files in the github project are licensed under CC0: http://creativecommons.org/publicdomain/zero/1.0/ +This means you can reuse, remix, or otherwise appropriate this project for your own use WITHOUT RESTRICTION. +(The actual legal meaning can be found at the above link.) +Don't ask me for permission to use any part of this project, JUST USE IT. +I would appreciate attribution, but that is not required by the license. +*/ + +/* +This file uses a module pattern to avoid leaking names into the global scope. +The only accidental leakage is the name "temp". +The exported names can be found at the bottom of this file; +simply change the names in the array of strings to change what they are called in your application. + +As well, several configuration constants are passed into the module function at the bottom of this file. +At runtime, these constants can be found on the Diagram class. +*/ + +(function(options) { + function subclassOf(baseClass, superClass) { + baseClass.prototype = Object.create(superClass.prototype); + baseClass.prototype.$super = superClass.prototype; + } + + function unnull(/* children */) { + return [].slice.call(arguments).reduce(function(sofar, x) { return sofar !== undefined ? sofar : x; }); + } + + function determineGaps(outer, inner) { + var diff = outer - inner; + switch(Diagram.INTERNAL_ALIGNMENT) { + case 'left': return [0, diff]; break; + case 'right': return [diff, 0]; break; + case 'center': + default: return [diff/2, diff/2]; break; + } + } + + function wrapString(value) { + return ((typeof value) == 'string') ? new Terminal(value) : value; + } + + function sum(iter, func) { + if(!func) func = function(x) { return x; }; + return iter.map(func).reduce(function(a,b){return a+b}, 0); + } + + function max(iter, func) { + if(!func) func = function(x) { return x; }; + return Math.max.apply(null, iter.map(func)); + } + + function SVG(name, attrs, text) { + attrs = attrs || {}; + text = text || ''; + var el = document.createElementNS("http://www.w3.org/2000/svg",name); + for(var attr in attrs) { + if(attr === 'xlink:href') + el.setAttributeNS("http://www.w3.org/1999/xlink", 'href', attrs[attr]); + else + el.setAttribute(attr, attrs[attr]); + } + el.textContent = text; + return el; + } + + function FakeSVG(tagName, attrs, text){ + if(!(this instanceof FakeSVG)) return new FakeSVG(tagName, attrs, text); + if(text) this.children = text; + else this.children = []; + this.tagName = tagName; + this.attrs = unnull(attrs, {}); + return this; + }; + FakeSVG.prototype.format = function(x, y, width) { + // Virtual + }; + FakeSVG.prototype.addTo = function(parent) { + if(parent instanceof FakeSVG) { + parent.children.push(this); + return this; + } else { + var svg = this.toSVG(); + parent.appendChild(svg); + return svg; + } + }; + FakeSVG.prototype.escapeString = function(string) { + // Escape markdown and HTML special characters + return string.replace(/[*_\`\[\]<&]/g, function(charString) { + return '&#' + charString.charCodeAt(0) + ';'; + }); + }; + FakeSVG.prototype.toSVG = function() { + var el = SVG(this.tagName, this.attrs); + if(typeof this.children == 'string') { + el.textContent = this.children; + } else { + this.children.forEach(function(e) { + el.appendChild(e.toSVG()); + }); + } + return el; + }; + FakeSVG.prototype.toString = function() { + var str = '<' + this.tagName; + var group = this.tagName == "g" || this.tagName == "svg"; + for(var attr in this.attrs) { + str += ' ' + attr + '="' + (this.attrs[attr]+'').replace(/&/g, '&').replace(/"/g, '"') + '"'; + } + str += '>'; + if(group) str += "\n"; + if(typeof this.children == 'string') { + str += FakeSVG.prototype.escapeString(this.children); + } else { + this.children.forEach(function(e) { + str += e; + }); + } + str += '\n'; + return str; + } + + function Path(x,y) { + if(!(this instanceof Path)) return new Path(x,y); + FakeSVG.call(this, 'path'); + this.attrs.d = "M"+x+' '+y; + } + subclassOf(Path, FakeSVG); + Path.prototype.m = function(x,y) { + this.attrs.d += 'm'+x+' '+y; + return this; + } + Path.prototype.h = function(val) { + this.attrs.d += 'h'+val; + return this; + } + Path.prototype.right = Path.prototype.h; + Path.prototype.left = function(val) { return this.h(-val); } + Path.prototype.v = function(val) { + this.attrs.d += 'v'+val; + return this; + } + Path.prototype.down = Path.prototype.v; + Path.prototype.up = function(val) { return this.v(-val); } + Path.prototype.arc = function(sweep){ + var x = Diagram.ARC_RADIUS; + var y = Diagram.ARC_RADIUS; + if(sweep[0] == 'e' || sweep[1] == 'w') { + x *= -1; + } + if(sweep[0] == 's' || sweep[1] == 'n') { + y *= -1; + } + if(sweep == 'ne' || sweep == 'es' || sweep == 'sw' || sweep == 'wn') { + var cw = 1; + } else { + var cw = 0; + } + this.attrs.d += "a"+Diagram.ARC_RADIUS+" "+Diagram.ARC_RADIUS+" 0 0 "+cw+' '+x+' '+y; + return this; + } + Path.prototype.format = function() { + // All paths in this library start/end horizontally. + // The extra .5 ensures a minor overlap, so there's no seams in bad rasterizers. + this.attrs.d += 'h.5'; + return this; + } + + function Diagram(items) { + if(!(this instanceof Diagram)) return new Diagram([].slice.call(arguments)); + FakeSVG.call(this, 'svg', {class: Diagram.DIAGRAM_CLASS}); + this.items = items.map(wrapString); + this.items.unshift(new Start); + this.items.push(new End); + this.up = this.down = this.height = this.width = 0; + for(var i = 0; i < this.items.length; i++) { + var item = this.items[i]; + this.width += item.width + (item.needsSpace?20:0); + this.up = Math.max(this.up, item.up - this.height); + this.height += item.height; + this.down = Math.max(this.down - item.height, item.down); + } + this.formatted = false; + } + subclassOf(Diagram, FakeSVG); + for(var option in options) { + Diagram[option] = options[option]; + } + Diagram.prototype.format = function(paddingt, paddingr, paddingb, paddingl) { + paddingt = unnull(paddingt, 20); + paddingr = unnull(paddingr, paddingt, 20); + paddingb = unnull(paddingb, paddingt, 20); + paddingl = unnull(paddingl, paddingr, 20); + var x = paddingl; + var y = paddingt; + y += this.up; + var g = FakeSVG('g', Diagram.STROKE_ODD_PIXEL_LENGTH ? {transform:'translate(.5 .5)'} : {}); + for(var i = 0; i < this.items.length; i++) { + var item = this.items[i]; + if(item.needsSpace) { + Path(x,y).h(10).addTo(g); + x += 10; + } + item.format(x, y, item.width).addTo(g); + x += item.width; + y += item.height; + if(item.needsSpace) { + Path(x,y).h(10).addTo(g); + x += 10; + } + } + this.attrs.width = this.width + paddingl + paddingr; + this.attrs.height = this.up + this.height + this.down + paddingt + paddingb; + this.attrs.viewBox = "0 0 " + this.attrs.width + " " + this.attrs.height; + g.addTo(this); + this.formatted = true; + return this; + } + Diagram.prototype.addTo = function(parent) { + if(!parent) { + var scriptTag = document.getElementsByTagName('script'); + scriptTag = scriptTag[scriptTag.length - 1]; + parent = scriptTag.parentNode; + } + return this.$super.addTo.call(this, parent); + } + Diagram.prototype.toSVG = function() { + if (!this.formatted) { + this.format(); + } + return this.$super.toSVG.call(this); + } + Diagram.prototype.toString = function() { + if (!this.formatted) { + this.format(); + } + return this.$super.toString.call(this); + } + + function ComplexDiagram() { + var diagram = new Diagram([].slice.call(arguments)); + var items = diagram.items; + items.shift(); + items.pop(); + items.unshift(new Start("complex")); + items.push(new End("complex")); + diagram.items = items; + return diagram; + } + + function Sequence(items) { + if(!(this instanceof Sequence)) return new Sequence([].slice.call(arguments)); + FakeSVG.call(this, 'g'); + this.items = items.map(wrapString); + var numberOfItems = this.items.length; + this.needsSpace = true; + this.up = this.down = this.height = this.width = 0; + for(var i = 0; i < this.items.length; i++) { + var item = this.items[i]; + this.width += item.width + (item.needsSpace?20:0); + this.up = Math.max(this.up, item.up - this.height); + this.height += item.height; + this.down = Math.max(this.down - item.height, item.down); + } + if(this.items[0].needsSpace) this.width -= 10; + if(this.items[this.items.length-1].needsSpace) this.width -= 10; + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "sequence" + } + } + subclassOf(Sequence, FakeSVG); + Sequence.prototype.format = function(x,y,width) { + // Hook up the two sides if this is narrower than its stated width. + var gaps = determineGaps(width, this.width); + Path(x,y).h(gaps[0]).addTo(this); + Path(x+gaps[0]+this.width,y+this.height).h(gaps[1]).addTo(this); + x += gaps[0]; + + for(var i = 0; i < this.items.length; i++) { + var item = this.items[i]; + if(item.needsSpace && i > 0) { + Path(x,y).h(10).addTo(this); + x += 10; + } + item.format(x, y, item.width).addTo(this); + x += item.width; + y += item.height; + if(item.needsSpace && i < this.items.length-1) { + Path(x,y).h(10).addTo(this); + x += 10; + } + } + return this; + } + + function Stack(items) { + if(!(this instanceof Stack)) return new Stack([].slice.call(arguments)); + FakeSVG.call(this, 'g'); + if( items.length === 0 ) { + throw new RangeError("Stack() must have at least one child."); + } + this.items = items.map(wrapString); + this.width = Math.max.apply(null, this.items.map(function(e) { return e.width + (e.needsSpace?20:0); })); + if(this.items[0].needsSpace) this.width -= 10; + if(this.items[this.items.length-1].needsSpace) this.width -= 10; + if(this.items.length > 1){ + this.width += Diagram.ARC_RADIUS*2; + } + this.needsSpace = true; + this.up = this.items[0].up; + this.down = this.items[this.items.length-1].down; + + this.height = 0; + for(var i = 0; i < this.items.length; i++) { + this.height += this.items[i].height; + if(i !== this.items.length-1) { + this.height += Math.max(this.items[i].down + Diagram.VERTICAL_SEPARATION, Diagram.ARC_RADIUS*2) + Math.max(this.items[i+1].up + Diagram.VERTICAL_SEPARATION, Diagram.ARC_RADIUS*2); + } + } + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "stack" + } + } + subclassOf(Stack, FakeSVG); + Stack.prototype.format = function(x,y,width) { + var gaps = determineGaps(width, this.width); + Path(x,y).h(gaps[0]).addTo(this); + x += gaps[0]; + var xInitial = x; + if(this.items.length > 1) { + Path(x, y).h(Diagram.ARC_RADIUS).addTo(this); + x += Diagram.ARC_RADIUS; + } + + for(var i = 0; i < this.items.length; i++) { + var item = this.items[i]; + var innerWidth = this.width - (this.items.length>1 ? Diagram.ARC_RADIUS*2 : 0); + item.format(x, y, innerWidth).addTo(this); + x += innerWidth; + y += item.height; + + if(i !== this.items.length-1) { + Path(x, y) + .arc('ne').down(Math.max(0, item.down + Diagram.VERTICAL_SEPARATION - Diagram.ARC_RADIUS*2)) + .arc('es').left(innerWidth) + .arc('nw').down(Math.max(0, this.items[i+1].up + Diagram.VERTICAL_SEPARATION - Diagram.ARC_RADIUS*2)) + .arc('ws').addTo(this); + y += Math.max(item.down + Diagram.VERTICAL_SEPARATION, Diagram.ARC_RADIUS*2) + Math.max(this.items[i+1].up + Diagram.VERTICAL_SEPARATION, Diagram.ARC_RADIUS*2); + //y += Math.max(Diagram.ARC_RADIUS*4, item.down + Diagram.VERTICAL_SEPARATION*2 + this.items[i+1].up) + x = xInitial+Diagram.ARC_RADIUS; + } + + } + + if(this.items.length > 1) { + Path(x,y).h(Diagram.ARC_RADIUS).addTo(this); + x += Diagram.ARC_RADIUS; + } + Path(x,y).h(gaps[1]).addTo(this); + + return this; + } + + function OptionalSequence(items) { + if(!(this instanceof OptionalSequence)) return new OptionalSequence([].slice.call(arguments)); + FakeSVG.call(this, 'g'); + if( items.length === 0 ) { + throw new RangeError("OptionalSequence() must have at least one child."); + } + this.items = items.map(wrapString); + this.needsSpace = false; + this.width = Diagram.ARC_RADIUS *4; + this.up = 0; + this.height = sum(this.items, function(x){return x.height}); + this.down = this.items[0].down; + var heightSoFar = 0; + for(var i = 0; i < this.items.length; i++) { + var item = this.items[i]; + this.up = Math.max(this.up, Math.max(Diagram.ARC_RADIUS*2, item.up + Diagram.VERTICAL_SEPARATION) - heightSoFar); + heightSoFar += item.height; + if(i > 0) { + this.down = Math.max(this.height + this.down, heightSoFar + Math.max(Diagram.ARC_RADIUS*2, item.down + Diagram.VERTICAL_SEPARATION)) - this.height; + } + this.width += Math.max(Diagram.ARC_RADIUS*2, item.width + (item.needsSpace?20:0)); + if(i == 0) this.width += Diagram.ARC_RADIUS; + else if(i == 1) this.width += Diagram.ARC_RADIUS*2; + else if(i < this.items.length - 1) this.width += Diagram.ARC_RADIUS*3; + } + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "optseq" + } + } + subclassOf(OptionalSequence, FakeSVG); + OptionalSequence.prototype.format = function(x, y, width) { + var gaps = determineGaps(width, this.width) + Path(x, y).h(gaps[0]).addTo(this) + Path(x + gaps[0] + this.width, y + this.height).h(gaps[1]).addTo(this) + x += gaps[0] + var upperLineY = y - this.up; + var last = this.items.length - 1; + Path(x,y) + .arc('se') + .up(Math.max(0, this.up - Diagram.ARC_RADIUS*2)) + .arc('wn') + .right(this.width - Diagram.ARC_RADIUS*5 - this.items[last].width - (this.items[last].needsSpace?20:0)) + .arc('ne') + .down(Math.max(0, this.up + this.height - this.items[last].height - Diagram.ARC_RADIUS*2)) + .arc('ws') + .addTo(this); + for(var i = 0; i < this.items.length; i++) { + var item = this.items[i]; + var itemWidth = item.width + (item.needsSpace?20:0); + if(i == 0) var spaceSize = Diagram.ARC_RADIUS; + else if(i == 1) var spaceSize = Diagram.ARC_RADIUS*2; + else var spaceSize = Diagram.ARC_RADIUS*3; + if(i > 0) { + if(i < last) { + Path(x + spaceSize - Diagram.ARC_RADIUS*2, upperLineY) + .arc('ne') + .down(Math.abs(upperLineY - y) - Diagram.ARC_RADIUS*2) + .arc('ws') + .addTo(this); + } + Path(x + spaceSize - Diagram.ARC_RADIUS*2, y) + .arc('ne') + .down(item.height + Math.max(0, item.down + Diagram.VERTICAL_SEPARATION - Diagram.ARC_RADIUS*2)) + .arc('ws') + .right(itemWidth - Diagram.ARC_RADIUS) + .arc('se') + .up(Math.max(0, item.down + Diagram.VERTICAL_SEPARATION - Diagram.ARC_RADIUS*2)) + .arc('wn') + .addTo(this); + } + Path(x, y).right(spaceSize).addTo(this); + x += spaceSize; + item.format(x, y, itemWidth).addTo(this); + x += itemWidth; + y += item.height; + } + Path(x, y).right(Diagram.ARC_RADIUS*2).addTo(this); + return this; + }; + + function Choice(normal, items) { + if(!(this instanceof Choice)) return new Choice(normal, [].slice.call(arguments,1)); + FakeSVG.call(this, 'g'); + if( typeof normal !== "number" || normal !== Math.floor(normal) ) { + throw new TypeError("The first argument of Choice() must be an integer."); + } else if(normal < 0 || normal >= items.length) { + throw new RangeError("The first argument of Choice() must be an index for one of the items."); + } else { + this.normal = normal; + } + var first = 0; + var last = items.length - 1; + this.items = items.map(wrapString); + this.width = Math.max.apply(null, this.items.map(function(el){return el.width})) + Diagram.ARC_RADIUS*4; + this.height = this.items[normal].height; + this.up = this.items[first].up; + for(var i = first; i < normal; i++) { + if(i == normal-1) var arcs = Diagram.ARC_RADIUS*2; + else var arcs = Diagram.ARC_RADIUS; + this.up += Math.max(arcs, this.items[i].height + this.items[i].down + Diagram.VERTICAL_SEPARATION + this.items[i+1].up); + } + this.down = this.items[last].down; + for(var i = normal+1; i <= last; i++) { + if(i == normal+1) var arcs = Diagram.ARC_RADIUS*2; + else var arcs = Diagram.ARC_RADIUS; + this.down += Math.max(arcs, this.items[i-1].height + this.items[i-1].down + Diagram.VERTICAL_SEPARATION + this.items[i].up); + } + this.down -= this.items[normal].height; // already counted in Choice.height + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "choice" + } + } + subclassOf(Choice, FakeSVG); + Choice.prototype.format = function(x,y,width) { + // Hook up the two sides if this is narrower than its stated width. + var gaps = determineGaps(width, this.width); + Path(x,y).h(gaps[0]).addTo(this); + Path(x+gaps[0]+this.width,y+this.height).h(gaps[1]).addTo(this); + x += gaps[0]; + + var last = this.items.length -1; + var innerWidth = this.width - Diagram.ARC_RADIUS*4; + + // Do the elements that curve above + for(var i = this.normal - 1; i >= 0; i--) { + var item = this.items[i]; + if( i == this.normal - 1 ) { + var distanceFromY = Math.max(Diagram.ARC_RADIUS*2, this.items[this.normal].up + Diagram.VERTICAL_SEPARATION + item.down + item.height); + } + Path(x,y) + .arc('se') + .up(distanceFromY - Diagram.ARC_RADIUS*2) + .arc('wn').addTo(this); + item.format(x+Diagram.ARC_RADIUS*2,y - distanceFromY,innerWidth).addTo(this); + Path(x+Diagram.ARC_RADIUS*2+innerWidth, y-distanceFromY+item.height) + .arc('ne') + .down(distanceFromY - item.height + this.height - Diagram.ARC_RADIUS*2) + .arc('ws').addTo(this); + distanceFromY += Math.max(Diagram.ARC_RADIUS, item.up + Diagram.VERTICAL_SEPARATION + (i == 0 ? 0 : this.items[i-1].down+this.items[i-1].height)); + } + + // Do the straight-line path. + Path(x,y).right(Diagram.ARC_RADIUS*2).addTo(this); + this.items[this.normal].format(x+Diagram.ARC_RADIUS*2, y, innerWidth).addTo(this); + Path(x+Diagram.ARC_RADIUS*2+innerWidth, y+this.height).right(Diagram.ARC_RADIUS*2).addTo(this); + + // Do the elements that curve below + for(var i = this.normal+1; i <= last; i++) { + var item = this.items[i]; + if( i == this.normal + 1 ) { + var distanceFromY = Math.max(Diagram.ARC_RADIUS*2, this.height + this.items[this.normal].down + Diagram.VERTICAL_SEPARATION + item.up); + } + Path(x,y) + .arc('ne') + .down(distanceFromY - Diagram.ARC_RADIUS*2) + .arc('ws').addTo(this); + item.format(x+Diagram.ARC_RADIUS*2, y+distanceFromY, innerWidth).addTo(this); + Path(x+Diagram.ARC_RADIUS*2+innerWidth, y+distanceFromY+item.height) + .arc('se') + .up(distanceFromY - Diagram.ARC_RADIUS*2 + item.height - this.height) + .arc('wn').addTo(this); + distanceFromY += Math.max(Diagram.ARC_RADIUS, item.height + item.down + Diagram.VERTICAL_SEPARATION + (i == last ? 0 : this.items[i+1].up)); + } + + return this; + } + + function MultipleChoice(normal, type, items) { + if(!(this instanceof MultipleChoice)) return new MultipleChoice(normal, type, [].slice.call(arguments,2)); + FakeSVG.call(this, 'g'); + if( typeof normal !== "number" || normal !== Math.floor(normal) ) { + throw new TypeError("The first argument of MultipleChoice() must be an integer."); + } else if(normal < 0 || normal >= items.length) { + throw new RangeError("The first argument of MultipleChoice() must be an index for one of the items."); + } else { + this.normal = normal; + } + if( type != "any" && type != "all" ) { + throw new SyntaxError("The second argument of MultipleChoice must be 'any' or 'all'."); + } else { + this.type = type; + } + this.needsSpace = true; + this.items = items.map(wrapString); + this.innerWidth = max(this.items, function(x){return x.width}); + this.width = 30 + Diagram.ARC_RADIUS + this.innerWidth + Diagram.ARC_RADIUS + 20; + this.up = this.items[0].up; + this.down = this.items[this.items.length-1].down; + this.height = this.items[normal].height; + for(var i = 0; i < this.items.length; i++) { + var item = this.items[i]; + if(i == normal - 1 || i == normal + 1) var minimum = 10 + Diagram.ARC_RADIUS; + else var minimum = Diagram.ARC_RADIUS; + if(i < normal) { + this.up += Math.max(minimum, item.height + item.down + Diagram.VERTICAL_SEPARATION + this.items[i+1].up); + } else if(i > normal) { + this.down += Math.max(minimum, item.up + Diagram.VERTICAL_SEPARATION + this.items[i-1].down + this.items[i-1].height); + } + } + this.down -= this.items[normal].height; // already counted in this.height + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "multiplechoice" + } + } + subclassOf(MultipleChoice, FakeSVG); + MultipleChoice.prototype.format = function(x, y, width) { + var gaps = determineGaps(width, this.width); + Path(x, y).right(gaps[0]).addTo(this); + Path(x + gaps[0] + this.width, y + this.height).right(gaps[1]).addTo(this); + x += gaps[0]; + + var normal = this.items[this.normal]; + + // Do the elements that curve above + for(var i = this.normal - 1; i >= 0; i--) { + var item = this.items[i]; + if( i == this.normal - 1 ) { + var distanceFromY = Math.max(10 + Diagram.ARC_RADIUS, normal.up + Diagram.VERTICAL_SEPARATION + item.down + item.height); + } + Path(x + 30,y) + .up(distanceFromY - Diagram.ARC_RADIUS) + .arc('wn').addTo(this); + item.format(x + 30 + Diagram.ARC_RADIUS, y - distanceFromY, this.innerWidth).addTo(this); + Path(x + 30 + Diagram.ARC_RADIUS + this.innerWidth, y - distanceFromY + item.height) + .arc('ne') + .down(distanceFromY - item.height + this.height - Diagram.ARC_RADIUS - 10) + .addTo(this); + if(i != 0) { + distanceFromY += Math.max(Diagram.ARC_RADIUS, item.up + Diagram.VERTICAL_SEPARATION + this.items[i-1].down + this.items[i-1].height); + } + } + + Path(x + 30, y).right(Diagram.ARC_RADIUS).addTo(this); + normal.format(x + 30 + Diagram.ARC_RADIUS, y, this.innerWidth).addTo(this); + Path(x + 30 + Diagram.ARC_RADIUS + this.innerWidth, y + this.height).right(Diagram.ARC_RADIUS).addTo(this); + + for(var i = this.normal+1; i < this.items.length; i++) { + var item = this.items[i]; + if(i == this.normal + 1) { + var distanceFromY = Math.max(10+Diagram.ARC_RADIUS, normal.height + normal.down + Diagram.VERTICAL_SEPARATION + item.up); + } + Path(x + 30, y) + .down(distanceFromY - Diagram.ARC_RADIUS) + .arc('ws') + .addTo(this); + item.format(x + 30 + Diagram.ARC_RADIUS, y + distanceFromY, this.innerWidth).addTo(this) + Path(x + 30 + Diagram.ARC_RADIUS + this.innerWidth, y + distanceFromY + item.height) + .arc('se') + .up(distanceFromY - Diagram.ARC_RADIUS + item.height - normal.height) + .addTo(this); + if(i != this.items.length - 1) { + distanceFromY += Math.max(Diagram.ARC_RADIUS, item.height + item.down + Diagram.VERTICAL_SEPARATION + this.items[i+1].up); + } + } + var text = FakeSVG('g', {"class": "diagram-text"}).addTo(this) + FakeSVG('title', {}, (this.type=="any"?"take one or more branches, once each, in any order":"take all branches, once each, in any order")).addTo(text) + FakeSVG('path', { + "d": "M "+(x+30)+" "+(y-10)+" h -26 a 4 4 0 0 0 -4 4 v 12 a 4 4 0 0 0 4 4 h 26 z", + "class": "diagram-text" + }).addTo(text) + FakeSVG('text', { + "x": x + 15, + "y": y + 4, + "class": "diagram-text" + }, (this.type=="any"?"1+":"all")).addTo(text) + FakeSVG('path', { + "d": "M "+(x+this.width-20)+" "+(y-10)+" h 16 a 4 4 0 0 1 4 4 v 12 a 4 4 0 0 1 -4 4 h -16 z", + "class": "diagram-text" + }).addTo(text) + FakeSVG('path', { + "d": "M "+(x+this.width-13)+" "+(y-2)+" a 4 4 0 1 0 6 -1 m 2.75 -1 h -4 v 4 m 0 -3 h 2", + "style": "stroke-width: 1.75" + }).addTo(text) + return this; + }; + + function Optional(item, skip) { + if( skip === undefined ) + return Choice(1, Skip(), item); + else if ( skip === "skip" ) + return Choice(0, Skip(), item); + else + throw "Unknown value for Optional()'s 'skip' argument."; + } + + function OneOrMore(item, rep) { + if(!(this instanceof OneOrMore)) return new OneOrMore(item, rep); + FakeSVG.call(this, 'g'); + rep = rep || (new Skip); + this.item = wrapString(item); + this.rep = wrapString(rep); + this.width = Math.max(this.item.width, this.rep.width) + Diagram.ARC_RADIUS*2; + this.height = this.item.height; + this.up = this.item.up; + this.down = Math.max(Diagram.ARC_RADIUS*2, this.item.down + Diagram.VERTICAL_SEPARATION + this.rep.up + this.rep.height + this.rep.down); + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "oneormore" + } + } + subclassOf(OneOrMore, FakeSVG); + OneOrMore.prototype.needsSpace = true; + OneOrMore.prototype.format = function(x,y,width) { + // Hook up the two sides if this is narrower than its stated width. + var gaps = determineGaps(width, this.width); + Path(x,y).h(gaps[0]).addTo(this); + Path(x+gaps[0]+this.width,y+this.height).h(gaps[1]).addTo(this); + x += gaps[0]; + + // Draw item + Path(x,y).right(Diagram.ARC_RADIUS).addTo(this); + this.item.format(x+Diagram.ARC_RADIUS,y,this.width-Diagram.ARC_RADIUS*2).addTo(this); + Path(x+this.width-Diagram.ARC_RADIUS,y+this.height).right(Diagram.ARC_RADIUS).addTo(this); + + // Draw repeat arc + var distanceFromY = Math.max(Diagram.ARC_RADIUS*2, this.item.height+this.item.down+Diagram.VERTICAL_SEPARATION+this.rep.up); + Path(x+Diagram.ARC_RADIUS,y).arc('nw').down(distanceFromY-Diagram.ARC_RADIUS*2).arc('ws').addTo(this); + this.rep.format(x+Diagram.ARC_RADIUS, y+distanceFromY, this.width - Diagram.ARC_RADIUS*2).addTo(this); + Path(x+this.width-Diagram.ARC_RADIUS, y+distanceFromY+this.rep.height).arc('se').up(distanceFromY-Diagram.ARC_RADIUS*2+this.rep.height-this.item.height).arc('en').addTo(this); + + return this; + } + + function ZeroOrMore(item, rep, skip) { + return Optional(OneOrMore(item, rep), skip); + } + + function Start(type) { + if(!(this instanceof Start)) return new Start(); + FakeSVG.call(this, 'path'); + this.width = 20; + this.height = 0; + this.up = 10; + this.down = 10; + this.type = type || "simple"; + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "start" + } + } + subclassOf(Start, FakeSVG); + Start.prototype.format = function(x,y) { + if (this.type === "complex") { + this.attrs.d = 'M '+x+' '+(y-10)+' v 20 m 0 -10 h 20.5'; + } else { + this.attrs.d = 'M '+x+' '+(y-10)+' v 20 m 10 -20 v 20 m -10 -10 h 20.5'; + } + return this; + } + + function End(type) { + if(!(this instanceof End)) return new End(); + FakeSVG.call(this, 'path'); + this.width = 20; + this.height = 0; + this.up = 10; + this.down = 10; + this.type = type || "simple"; + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "end" + } + } + subclassOf(End, FakeSVG); + End.prototype.format = function(x,y) { + if (this.type === "complex") { + this.attrs.d = 'M '+x+' '+y+' h 20 m 0 -10 v 20'; + } else { + this.attrs.d = 'M '+x+' '+y+' h 20 m -10 -10 v 20 m 10 -20 v 20'; + } + return this; + } + + function Terminal(text, href) { + if(!(this instanceof Terminal)) return new Terminal(text, href); + FakeSVG.call(this, 'g', {'class': 'terminal'}); + this.text = text; + this.href = href; + this.width = text.length * 8 + 20; /* Assume that each char is .5em, and that the em is 16px */ + this.height = 0; + this.up = 11; + this.down = 11; + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "terminal" + } + } + subclassOf(Terminal, FakeSVG); + Terminal.prototype.needsSpace = true; + Terminal.prototype.format = function(x, y, width) { + // Hook up the two sides if this is narrower than its stated width. + var gaps = determineGaps(width, this.width); + Path(x,y).h(gaps[0]).addTo(this); + Path(x+gaps[0]+this.width,y).h(gaps[1]).addTo(this); + x += gaps[0]; + + FakeSVG('rect', {x:x, y:y-11, width:this.width, height:this.up+this.down, rx:10, ry:10}).addTo(this); + var text = FakeSVG('text', {x:x+this.width/2, y:y+4}, this.text); + if(this.href) + FakeSVG('a', {'xlink:href': this.href}, [text]).addTo(this); + else + text.addTo(this); + return this; + } + + function NonTerminal(text, href) { + if(!(this instanceof NonTerminal)) return new NonTerminal(text, href); + FakeSVG.call(this, 'g', {'class': 'non-terminal'}); + this.text = text; + this.href = href; + this.width = text.length * 8 + 20; + this.height = 0; + this.up = 11; + this.down = 11; + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "nonterminal" + } + } + subclassOf(NonTerminal, FakeSVG); + NonTerminal.prototype.needsSpace = true; + NonTerminal.prototype.format = function(x, y, width) { + // Hook up the two sides if this is narrower than its stated width. + var gaps = determineGaps(width, this.width); + Path(x,y).h(gaps[0]).addTo(this); + Path(x+gaps[0]+this.width,y).h(gaps[1]).addTo(this); + x += gaps[0]; + + FakeSVG('rect', {x:x, y:y-11, width:this.width, height:this.up+this.down}).addTo(this); + var text = FakeSVG('text', {x:x+this.width/2, y:y+4}, this.text); + if(this.href) + FakeSVG('a', {'xlink:href': this.href}, [text]).addTo(this); + else + text.addTo(this); + return this; + } + + function Comment(text, href) { + if(!(this instanceof Comment)) return new Comment(text, href); + FakeSVG.call(this, 'g'); + this.text = text; + this.href = href; + this.width = text.length * 7 + 10; + this.height = 0; + this.up = 11; + this.down = 11; + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "comment" + } + } + subclassOf(Comment, FakeSVG); + Comment.prototype.needsSpace = true; + Comment.prototype.format = function(x, y, width) { + // Hook up the two sides if this is narrower than its stated width. + var gaps = determineGaps(width, this.width); + Path(x,y).h(gaps[0]).addTo(this); + Path(x+gaps[0]+this.width,y+this.height).h(gaps[1]).addTo(this); + x += gaps[0]; + + var text = FakeSVG('text', {x:x+this.width/2, y:y+5, class:'comment'}, this.text); + if(this.href) + FakeSVG('a', {'xlink:href': this.href}, [text]).addTo(this); + else + text.addTo(this); + return this; + } + + function Skip() { + if(!(this instanceof Skip)) return new Skip(); + FakeSVG.call(this, 'g'); + this.width = 0; + this.height = 0; + this.up = 0; + this.down = 0; + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "skip" + } + } + subclassOf(Skip, FakeSVG); + Skip.prototype.format = function(x, y, width) { + Path(x,y).right(width).addTo(this); + return this; + } + + var root; + if (typeof define === 'function' && define.amd) { + // AMD. Register as an anonymous module. + root = {}; + define([], function() { + return root; + }); + } else if (typeof exports === 'object') { + // CommonJS for node + root = exports; + } else { + // Browser globals (root is window) + root = this; + } + + var temp = [Diagram, ComplexDiagram, Sequence, Stack, OptionalSequence, Choice, MultipleChoice, Optional, OneOrMore, ZeroOrMore, Terminal, NonTerminal, Comment, Skip]; + /* + These are the names that the internal classes are exported as. + If you would like different names, adjust them here. + */ + ['Diagram', 'ComplexDiagram', 'Sequence', 'Stack', 'OptionalSequence', 'Choice', 'MultipleChoice', 'Optional', 'OneOrMore', 'ZeroOrMore', 'Terminal', 'NonTerminal', 'Comment', 'Skip'] + .forEach(function(e,i) { root[e] = temp[i]; }); +}).call(this, + { + VERTICAL_SEPARATION: 8, + ARC_RADIUS: 10, + DIAGRAM_CLASS: 'railroad-diagram', + STROKE_ODD_PIXEL_LENGTH: true, + INTERNAL_ALIGNMENT: 'center', + } +); diff --git a/docs/conf.py b/docs/conf.py index 0e413808..4319d4ac 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -34,18 +34,20 @@ # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom # ones. extensions = [ - 'sphinx.ext.autodoc', - 'sphinx.ext.intersphinx', - 'sphinx.ext.inheritance_diagram', - 'sphinx.ext.todo', - # 'sphinx.ext.coverage', - 'sphinx.ext.mathjax', - 'sphinx.ext.ifconfig', - 'sphinx.ext.viewcode', - # 'sphinx.ext.githubpages', - 'sphinxcontrib.autoprogram', - 'autoapi.sphinx', - 'poc' + 'sphinx.ext.autodoc', + 'sphinx.ext.extlinks', + 'sphinx.ext.intersphinx', + 'sphinx.ext.inheritance_diagram', + 'sphinx.ext.todo', + # 'sphinx.ext.coverage', + 'sphinx.ext.graphviz', + 'sphinx.ext.mathjax', + 'sphinx.ext.ifconfig', + 'sphinx.ext.viewcode', + # 'sphinx.ext.githubpages', + 'sphinxcontrib.autoprogram', + 'autoapi.sphinx', + 'poc' ] if (not (tags.has('PoCExternal') or tags.has('PoCInternal'))): @@ -353,3 +355,12 @@ def _LatestTagName(latestTagHash): 'python': ('https://docs.python.org/3.5/', None), 'ghdl': ('http://ghdl.readthedocs.io/en/latest', None) } + +extlinks = { + 'pocissue': ('https://github.com/VLSI-EDA/PoC/issues/%s', 'issue #'), + 'pocpull': ('https://github.com/VLSI-EDA/PoC/pull/%s', 'pull request #'), + 'pocsrc': ('https://github.com/VLSI-EDA/PoC/blob/master/src/%s?ts=2', None), + 'poctb': ('https://github.com/VLSI-EDA/PoC/blob/master/tb/%s?ts=2', None) +} + +graphviz_output_format = "svg" diff --git a/docs/genindex.rst b/docs/genindex.rst index 7c6a7dd4..c07da40d 100644 --- a/docs/genindex.rst +++ b/docs/genindex.rst @@ -1,3 +1,4 @@ +.. This file is a placeholder and will be replaced Index ##### diff --git a/docs/index.rst b/docs/index.rst index 81eb808a..d17792d1 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -82,6 +82,12 @@ following `biblatex `_ entry to cite us: urldate={2016-10-28}, } +------------------------------------ + +.. |docdate| date:: %b %d, %Y - %H:%M + +This document was generated on |docdate|. + .. toctree:: :caption: Introduction :hidden: diff --git a/docs/poc.py b/docs/poc.py index e02adf07..7dc13022 100644 --- a/docs/poc.py +++ b/docs/poc.py @@ -43,6 +43,7 @@ def __init__(self, file, startRow, endRow): self.StartRow = startRow self.EndRow = endRow + class SourceFile: def __init__(self, entitySourceCodeRange): #, entityName, entitySourceCodeRange, summary, description, seeAlso): self.File = entitySourceCodeRange.SourceFile @@ -56,9 +57,10 @@ def __init__(self, entitySourceCodeRange): #, entityName, entitySourceCodeRan class Extract: def __init__(self): - self.sourceDirectory = Path("../src") - self.outputDirectory = Path("IPCores") - self.relSourceDirectory = Path("../../src") + self.sourceDirectory = Path("../src") + self.outputDirectory = Path("IPCores") + self.relSourceDirectory = Path("../../src") + self.relTestbenchDirectory = Path("../../tb") self.templateFile = Path("Entity.template") self.templateContent = "" @@ -100,9 +102,11 @@ def recursion2(self, result): self.writeReST(item) def writeReST(self, sourceFile): - relPath = sourceFile.File.relative_to(self.sourceDirectory) - outputFile = self.outputDirectory / relPath.with_suffix(".rst") - relSourceFile = ("../" * (len(relPath.parents) - 1)) / self.relSourceDirectory / relPath + sourceRelPath = sourceFile.File.relative_to(self.sourceDirectory) + outputFile = self.outputDirectory / sourceRelPath.with_suffix(".rst") + relSourceFile = ("../" * (len(sourceRelPath.parents) - 1)) / self.relSourceDirectory / sourceRelPath + + testbenchRelPath = Path(sourceRelPath.with_name(sourceRelPath.stem + "_tb.vhdl")) print("Writing reST file '{0!s}'.".format(outputFile)) @@ -123,7 +127,8 @@ def writeReST(self, sourceFile): EntityDescription=sourceFile.Description, EntityFilePath=relSourceFile.as_posix(), EntityDeclarationFromTo="{0}-{1}".format(sourceFile.EntitySourceCodeRange.StartRow, sourceFile.EntitySourceCodeRange.EndRow), - GitHubSourceFile="`{relPath} `_".format(relPath=relPath.as_posix()), + SourceRelPath=sourceRelPath.as_posix(), + TestbenchRelPath=testbenchRelPath.as_posix(), SeeAlsoBox=seeAlsoBox ) @@ -133,14 +138,15 @@ def writeReST(self, sourceFile): def ExtractComments(self, sourceFile): """ Extracts the documentation from the header of a PoC VHDL source. - - The documentation header starts with a separator line matching /^--\s*={16,}$/. - - The documentation header continues through all immediately following comment lines. - - The contained information is added to the currently active section. - - A specific section is opened by a line matching /^--\s*(?P
\w+):/ with -
as one of Authors|Entity|Description|SeeAlso|License. - - An underline /^-- -+$/ immediately following a section opening is ignored. - - After the documentation header, the entity name is extracted from the entity declaration. - """ + + * The documentation header starts with a separator line matching /^--\s*={16,}$/. + * The documentation header continues through all immediately following comment lines. + * The contained information is added to the currently active section. + * A specific section is opened by a line matching /^--\s*(?P
\w+):/ with +
as one of Authors|Entity|Description|SeeAlso|License. + * An underline /^-- -+$/ immediately following a section opening is ignored. + * After the documentation header, the entity name is extracted from the entity declaration. + """ class State(Enum): BeforeDocHeader = 0 InDocHeader = 1 diff --git a/poc.ps1 b/poc.ps1 index 49e7f67a..0d5d54f2 100644 --- a/poc.ps1 +++ b/poc.ps1 @@ -59,7 +59,7 @@ if ($Debug -eq $true ) { Write-Host "This is the PoC-Library script wrapper operating in debug mode." -ForegroundColor Yellow Write-Host "" Write-Host "Directories:" -ForegroundColor Yellow - Write-Host " PoC Root $PoC_RootDir" -ForegroundColor Yellow + Write-Host " PoC Root $PoCRootDir" -ForegroundColor Yellow Write-Host " Working $PyWrapper_WorkingDir" -ForegroundColor Yellow Write-Host "Script:" -ForegroundColor Yellow Write-Host " Filename $PoC_ScriptPy" -ForegroundColor Yellow @@ -74,9 +74,9 @@ if ($Debug -eq $true ) { # execute script with appropriate Python interpreter and all given parameters if ($PoC_Solution -eq "") -{ $Command = "$Python_Interpreter $Python_Parameters $PoC_RootDir\$PoC_ScriptPy $args" } +{ $Command = "$Python_Interpreter $Python_Parameters $PoCRootDir\$PoC_ScriptPy $args" } else -{ $Command = "$Python_Interpreter $Python_Parameters $PoC_RootDir\$PoC_ScriptPy --sln=$PoC_Solution $args" } +{ $Command = "$Python_Interpreter $Python_Parameters $PoCRootDir\$PoC_ScriptPy --sln=$PoC_Solution $args" } # execute script with appropriate Python interpreter and all given parameters if ($Debug -eq $true) { Write-Host "launching: '$Command'" -ForegroundColor Yellow } diff --git a/py/Base/Compiler.py b/py/Base/Compiler.py index db23b1a0..92d8357d 100644 --- a/py/Base/Compiler.py +++ b/py/Base/Compiler.py @@ -38,6 +38,8 @@ from re import compile as re_compile, subn as re_subn, DOTALL as RE_DOTALL, MULTILINE as RE_MULTILINE, IGNORECASE as RE_IGNORECASE from shutil import copy as shutil_copy +from flags import Flags + from lib.Functions import Init from lib.Parser import ParserException from Base.Exceptions import ExceptionBase, SkipableException @@ -72,26 +74,42 @@ class SkipableCompilerException(CompilerException, SkipableException): pass class CopyTask(CopyRuleMixIn): - """This class represents a 'copy task' and inherits the partial class :ref:`CopyRuleMixIn`.""" + """This class represents a 'copy task' and inherits the partial class :class:`Parser.RulesParser.CopyRuleMixIn`.""" pass class DeleteTask(DeleteRuleMixIn): - """This class represents a 'delete task' and inherits the partial class :ref:`DeleteRuleMixIn`.""" + """This class represents a 'delete task' and inherits the partial class :class:`Parser.RulesParser.DeleteRuleMixIn`.""" pass class ReplaceTask(ReplaceRuleMixIn): - """This class represents a 'replace task' and inherits the partial class :ref:`ReplaceRuleMixIn`.""" + """This class represents a 'replace task' and inherits the partial class :class:`Parser.RulesParser.ReplaceRuleMixIn`.""" pass class AppendLineTask(AppendLineRuleMixIn): - """This class represents a 'append line task' and inherits the partial class :ref:`AppendLineRuleMixIn`.""" + """This class represents a 'append line task' and inherits the partial class :class:`Parser.RulesParser.AppendLineRuleMixIn`.""" pass +@unique +class CompilerSteps(Flags): + """Compiler step enumeration.""" + Prepare = 1 << 0 + CleanUpBefore = 1 << 1 + CleanUpAfter = 1 << 2 + Synthesize = 1 << 5 + Merge = 1 << 6 + AnalyzeTiming = 1 << 7 + Place = 1 << 8 + Route = 1 << 9 + WriteBitfile = 1 << 10 + ShowReport = 1 << 15 + # Recompile = 1 << 25 + # Resimulate = 1 << 26 + # Review = 1 << 27 + @unique class CompileState(Enum): """Compile state enumeration.""" - Prepare = 0 PreCopy = 10 PrePatch = 11 @@ -113,7 +131,6 @@ class CompileState(Enum): @unique class CompileResult(Enum): """Compilation result enumeration.""" - NotRun = 0 Error = 1 Failed = 2 diff --git a/py/Base/Shared.py b/py/Base/Shared.py index 58e2f486..7fd9b35e 100644 --- a/py/Base/Shared.py +++ b/py/Base/Shared.py @@ -36,6 +36,7 @@ from datetime import datetime from os import chdir +from lib.Functions import Init from lib.Parser import ParserException from Base.Exceptions import CommonException, SkipableCommonException from Base.Logging import ILogable @@ -124,30 +125,57 @@ def _GetTimeDeltaSinceLastEvent(self): self._lastEvent = now return result - def _Prepare(self): - self.LogNormal("Preparing {0}.".format(self._TOOL.LongName)) - def _PrepareEnvironment(self): # create fresh temporary directory self.LogVerbose("Creating fresh temporary directory.") if (self.Directories.Working.exists()): - self.LogDebug("Purging temporary directory: {0!s}".format(self.Directories.Working)) - for item in self.Directories.Working.iterdir(): - try: - if item.is_dir(): - shutil.rmtree(str(item)) - elif item.is_file(): - item.unlink() - except OSError as ex: - raise CommonException("Error while deleting '{0!s}'.".format(item)) from ex + self._PrepareEnvironment_PurgeDirectory() + # self.LogDebug("Purging temporary directory: {0!s}".format(self.Directories.Working)) + # for item in self.Directories.Working.iterdir(): + # try: + # if item.is_dir(): + # shutil.rmtree(str(item)) + # elif item.is_file(): + # item.unlink() + # except OSError as ex: + # raise CommonException("Error while deleting '{0!s}'.".format(item)) from ex else: - self.LogDebug("Creating temporary directory: {0!s}".format(self.Directories.Working)) + self._PrepareEnvironment_CreatingDirectory() + # self.LogDebug("Creating temporary directory: {0!s}".format(self.Directories.Working)) + # try: + # self.Directories.Working.mkdir(parents=True) + # except OSError as ex: + # raise CommonException("Error while creating '{0!s}'.".format(self.Directories.Working)) from ex + + self._PrepareEnvironment_ChangeDirectory() + # change working directory to temporary path + # self.LogVerbose("Changing working directory to temporary directory.") + # self.LogDebug("cd \"{0!s}\"".format(self.Directories.Working)) + # try: + # chdir(str(self.Directories.Working)) + # except OSError as ex: + # raise CommonException("Error while changing to '{0!s}'.".format(self.Directories.Working)) from ex + + def _PrepareEnvironment_PurgeDirectory(self): + self.LogDebug("Purging temporary directory: {0!s}".format(self.Directories.Working)) + for item in self.Directories.Working.iterdir(): try: - self.Directories.Working.mkdir(parents=True) + if item.is_dir(): + shutil.rmtree(str(item)) + elif item.is_file(): + item.unlink() except OSError as ex: - raise CommonException("Error while creating '{0!s}'.".format(self.Directories.Working)) from ex + raise CommonException("Error while deleting '{0!s}'.".format(item)) from ex - # change working directory to temporary path + def _PrepareEnvironment_CreatingDirectory(self): + self.LogDebug("Creating temporary directory: {0!s}".format(self.Directories.Working)) + try: + self.Directories.Working.mkdir(parents=True) + except OSError as ex: + raise CommonException("Error while creating '{0!s}'.".format(self.Directories.Working)) from ex + + def _PrepareEnvironment_ChangeDirectory(self): + """Change working directory to temporary path 'temp/'.""" self.LogVerbose("Changing working directory to temporary directory.") self.LogDebug("cd \"{0!s}\"".format(self.Directories.Working)) try: @@ -155,6 +183,9 @@ def _PrepareEnvironment(self): except OSError as ex: raise CommonException("Error while changing to '{0!s}'.".format(self.Directories.Working)) from ex + def _Prepare(self): + self.LogNormal("Preparing {0}.".format(self._TOOL.LongName)) + def _CreatePoCProject(self, projectName, board): # create a PoCProject and read all needed files self.LogVerbose("Creating PoC project '{0}'".format(projectName)) @@ -186,7 +217,8 @@ def _AddFileListFile(self, fileListFilePath): self.LogDebug("=" * 78) self.LogDebug("Pretty printing the PoCProject...") - self.LogDebug(self._pocProject.pprint(2)) + self.LogDebug("{DARK_RED}Disabled{NOCOLOR}".format(**Init.Foreground)) + # self.LogDebug(self._pocProject.pprint(2)) self.LogDebug("=" * 78) if (len(fileListFile.Warnings) > 0): for warn in fileListFile.Warnings: diff --git a/py/Base/Simulator.py b/py/Base/Simulator.py index 837c0955..10f84814 100644 --- a/py/Base/Simulator.py +++ b/py/Base/Simulator.py @@ -36,6 +36,9 @@ from datetime import datetime from enum import Enum, unique +from flags import Flags + +from lib.Decorators import MethodAlias from lib.Functions import Init from Base.Exceptions import ExceptionBase, SkipableException from Base.Logging import LogEntry @@ -50,6 +53,7 @@ 'SimulatorException', 'SkipableSimulatorException', 'PoCSimulationResultNotFoundException', + 'SimulationSteps', 'SimulationState', 'SimulationResult', 'Simulator', @@ -74,6 +78,29 @@ class PoCSimulationResultNotFoundException(SkipableSimulatorException): pass +@unique +class SimulationSteps(Flags): + """Simulation step enumeration.""" + Prepare = 1 << 0 + CleanUpBefore = 1 << 1 + CleanUpAfter = 1 << 2 + Analyze = 1 << 5 + Elaborate = 1 << 6 + # Compile = 1 << 7 + # Optimize = 1 << 8 + Simulate = 1 << 9 + ShowWaveform = 1 << 10 + ShowReport = 1 << 15 + Recompile = 1 << 25 + Resimulate = 1 << 26 + # Review = 1 << 27 + + def __and__(self, other): + if isinstance(other, bool): + return self if other else self.__class__.no_flags + else: + return super().__and__(other) + @unique class SimulationState(Enum): """Simulation state enumeration.""" @@ -113,29 +140,33 @@ class Simulator(Shared): class __Directories__(Shared.__Directories__): PreCompiled = None - def __init__(self, host, dryRun, guiMode): + def __init__(self, host, dryRun, simulationSteps : SimulationSteps): super().__init__(host, dryRun) - self._guiMode = guiMode + self._simulationSteps = simulationSteps self._testSuite = TestSuite() # TODO: This includes not the read ini files phases ... self._state = SimulationState.Prepare self._analyzeTime = None self._elaborationTime = None self._simulationTime = None - # class properties # ============================================================================ @property def TestSuite(self): return self._testSuite - def _PrepareSimulator(self): - self._Prepare() - def _PrepareSimulationEnvironment(self): self.LogNormal("Preparing simulation environment...") self._PrepareEnvironment() + def _PrepareEnvironment_PurgeDirectory(self): + if (SimulationSteps.CleanUpBefore in self._simulationSteps): + super()._PrepareEnvironment_PurgeDirectory() + + @MethodAlias(Shared._Prepare) + def _PrepareSimulator(self): + pass + def RunAll(self, fqnList, *args, **kwargs): """Run a list of testbenches. Expand wildcards to all selected testbenches.""" self._testSuite.StartTimer() @@ -155,7 +186,8 @@ def RunAll(self, fqnList, *args, **kwargs): finally: self._testSuite.StopTimer() - self.PrintOverallSimulationReport() + if (SimulationSteps.ShowReport in self._simulationSteps): + self.PrintOverallSimulationReport() return self._testSuite.IsAllPassed @@ -165,7 +197,7 @@ def TryRun(self, testbench, *args, **kwargs): SimulationState.Prepare: SimulationStatus.InternalError, SimulationState.Analyze: SimulationStatus.AnalyzeError, SimulationState.Elaborate: SimulationStatus.ElaborationError, - SimulationState.Optimize: SimulationStatus.ElaborationError, + # SimulationState.Optimize: SimulationStatus.ElaborationError, SimulationState.Simulate: SimulationStatus.SimulationError } @@ -195,10 +227,12 @@ def TryRun(self, testbench, *args, **kwargs): finally: testCase.StopTimer() - def Run(self, testbench, board, vhdlVersion, vhdlGenerics=None, guiMode=False): + def Run(self, testbench, board, vhdlVersion, vhdlGenerics=None): """Write the Testbench message line, create a PoCProject and add the first *.files file to it.""" self.LogQuiet("{CYAN}Testbench: {0!s}{NOCOLOR}".format(testbench.Parent, **Init.Foreground)) + testbench.Result = SimulationResult.NotRun + self._vhdlVersion = vhdlVersion self._vhdlGenerics = vhdlGenerics @@ -208,22 +242,34 @@ def Run(self, testbench, board, vhdlVersion, vhdlGenerics=None, guiMode=False): self._prepareTime = self._GetTimeDeltaSinceLastEvent() - self.LogNormal("Running analysis for every vhdl file...") - self._state = SimulationState.Analyze - self._RunAnalysis(testbench) - self._analyzeTime = self._GetTimeDeltaSinceLastEvent() + if self._simulationSteps.CleanUpBefore: + pass + + if self._simulationSteps.Prepare: + pass + + if self._simulationSteps.Analyze: + self.LogNormal("Running analysis for every vhdl file...") + self._state = SimulationState.Analyze + self._RunAnalysis(testbench) + self._analyzeTime = self._GetTimeDeltaSinceLastEvent() + + if self._simulationSteps.Elaborate: + self.LogNormal("Running elaboration...") + self._state = SimulationState.Elaborate + self._RunElaboration(testbench) + self._elaborationTime = self._GetTimeDeltaSinceLastEvent() - self.LogNormal("Running elaboration...") - self._state = SimulationState.Elaborate - self._RunElaboration(testbench) - self._elaborationTime = self._GetTimeDeltaSinceLastEvent() + # if self._simulationSteps.Optimize: + # pass - self.LogNormal("Running simulation...") - self._state = SimulationState.Simulate - self._RunSimulation(testbench) - self._simulationTime = self._GetTimeDeltaSinceLastEvent() + if self._simulationSteps.Simulate: + self.LogNormal("Running simulation...") + self._state = SimulationState.Simulate + self._RunSimulation(testbench) + self._simulationTime = self._GetTimeDeltaSinceLastEvent() - if (self._guiMode is True): + if self._simulationSteps.ShowWaveform: self.LogNormal("Executing waveform viewer...") self._state = SimulationState.View self._RunView(testbench) diff --git a/py/PoC.py b/py/PoC.py index 8543acac..bd005bc8 100644 --- a/py/PoC.py +++ b/py/PoC.py @@ -48,7 +48,7 @@ from Base.Exceptions import ExceptionBase, CommonException, PlatformNotSupportedException, EnvironmentException, NotConfiguredException from Base.Logging import ILogable, Logger, Severity from Base.Project import VHDLVersion -from Base.Simulator import SimulatorException, Simulator as BaseSimulator +from Base.Simulator import SimulatorException, Simulator as BaseSimulator, SimulationSteps from Base.ToolChain import ToolChainException from Compiler.LSECompiler import Compiler as LSECompiler from Compiler.QuartusCompiler import Compiler as MapCompiler @@ -91,8 +91,9 @@ 'BoardDeviceAttributeGroup', 'VHDLVersionAttribute', 'GUIModeAttribute', - 'NoCleanUpAttribute', - 'PoC', + 'SimulationStepsAttribute', + 'CompileStepsAttribute', + 'PileOfCores', 'main' ] __all__ = __api__ @@ -115,14 +116,31 @@ def __call__(self, func): self._AppendAttribute(func, ArgumentAttribute("--std", metavar="VHDLVersion", dest="VHDLVersion", help="Simulate with VHDL-??")) return func -class GUIModeAttribute(Attribute): +class SimulationStepsAttribute(Attribute): def __call__(self, func): - self._AppendAttribute(func, SwitchArgumentAttribute("-g", "--gui", dest="GUIMode", help="show waveform in a GUI window.")) + self._AppendAttribute(func, SwitchArgumentAttribute("-g", "--gui", dest="GUIMode", help="Run all steps (prepare, analysis, elaboration, optimization, simulation) and finally display the waveform in a GUI window.")) + self._AppendAttribute(func, SwitchArgumentAttribute("-a", "--analyze", dest="Analyze", help="Run only the prepare and analysis step.")) + self._AppendAttribute(func, SwitchArgumentAttribute("-e", "--elaborate", dest="Elaborate", help="Run only the prepare and elaboration step.")) + # self._AppendAttribute(func, SwitchArgumentAttribute("-c", "--compile", dest="Compile", help="Run only the prepare and compile step.")) + # self._AppendAttribute(func, SwitchArgumentAttribute("-o", "--optimize", dest="Optimize", help="Run only the prepare and optimization step.")) + self._AppendAttribute(func, SwitchArgumentAttribute("-C", "--recompile", dest="Recompile", help="Run all compile steps (prepare, analysis, elaboration, optimization).")) + self._AppendAttribute(func, SwitchArgumentAttribute("-s", "--simulate", dest="Simulate", help="Run only the prepare and simulation step.")) + self._AppendAttribute(func, SwitchArgumentAttribute("-w", "--showwave", dest="ShowWave", help="Run only the prepare step and display the waveform in a GUI window.")) + self._AppendAttribute(func, SwitchArgumentAttribute("-W", "--review", dest="Review", help="Run only display the waveform in a GUI window.")) + self._AppendAttribute(func, SwitchArgumentAttribute("-S", "--resimulate", dest="Resimulate", help="Run all simulation steps (prepare, simulation) and finally display the waveform in a GUI window.")) + self._AppendAttribute(func, SwitchArgumentAttribute("-r", "--showreport", dest="ShowReport", help="Show a simulation report.")) + # self._AppendAttribute(func, SwitchArgumentAttribute( "--cleanup-after", dest="CleanUpAfter", help="Don't delete intermediate files. Skip post-delete rules.")) return func -class NoCleanUpAttribute(Attribute): +class CompileStepsAttribute(Attribute): def __call__(self, func): - self._AppendAttribute(func, SwitchArgumentAttribute("--no-cleanup", dest="NoCleanUp", help="Don't delete intermediate files. Skip post-delete rules.")) + # synthesize + # merge + # place + # route + # bitfile + self._AppendAttribute(func, SwitchArgumentAttribute("-r", "--showreport", dest="ShowReport", help="Show a simulation report.")) + self._AppendAttribute(func, SwitchArgumentAttribute( "--no-cleanup", dest="NoCleanUp", help="Don't delete intermediate files. Skip post-delete rules.")) return func @@ -316,13 +334,13 @@ def __PrepareForSynthesis(self): # ============================================================================ # common arguments valid for all commands # ---------------------------------------------------------------------------- - @CommonSwitchArgumentAttribute("-D", dest="DEBUG", help="enable script wrapper debug mode") - @CommonSwitchArgumentAttribute( "--dryrun", dest="DryRun", help="enable script wrapper debug mode") - @CommonSwitchArgumentAttribute("-d", "--debug", dest="debug", help="enable debug mode") - @CommonSwitchArgumentAttribute("-v", "--verbose", dest="verbose", help="print out detailed messages") - @CommonSwitchArgumentAttribute("-q", "--quiet", dest="quiet", help="reduce messages to a minimum") - @CommonArgumentAttribute("--sln", metavar="SolutionID", dest="SolutionID", help="Solution name") - @CommonArgumentAttribute("--prj", metavar="ProjectID", dest="ProjectID", help="Solution name") + @CommonSwitchArgumentAttribute("-D", dest="DEBUG", help="Enable script wrapper debug mode. See also :option:`poc.ps1 -D`.") + @CommonSwitchArgumentAttribute( "--dryrun", dest="DryRun", help="Don't execute external programs.") + @CommonSwitchArgumentAttribute("-d", "--debug", dest="debug", help="Enable debug mode.") + @CommonSwitchArgumentAttribute("-v", "--verbose", dest="verbose", help="Print out detailed messages.") + @CommonSwitchArgumentAttribute("-q", "--quiet", dest="quiet", help="Reduce messages to a minimum.") + @CommonArgumentAttribute("--sln", metavar="SolutionID", dest="SolutionID", help="Solution name.") + @CommonArgumentAttribute("--prj", metavar="ProjectID", dest="ProjectID", help="Project name.") def Run(self): ArgParseMixin.Run(self) @@ -704,6 +722,39 @@ def _CheckISEEnvironment(self): if (len(self.PoCConfig.options("INSTALL.Xilinx.ISE")) == 0): raise NotConfiguredException("Xilinx ISE is not configured on this system.") if (environ.get('XILINX') is None): raise EnvironmentException("Xilinx ISE environment is not loaded in this shell environment.") + @staticmethod + def _ExtractSimulationSteps(guiMode, analyze, elaborate, optimize, recompile, simulate, showWaveform, resimulate, showReport, cleanUp): + simulationSteps = SimulationSteps.no_flags + if (not (analyze or elaborate or optimize or recompile or simulate or resimulate or showWaveform)): + simulationSteps |= SimulationSteps.Prepare | SimulationSteps.CleanUpBefore + simulationSteps |= SimulationSteps.Analyze | SimulationSteps.Elaborate #| SimulationSteps.Optimize + simulationSteps |= SimulationSteps.Simulate + simulationSteps |= SimulationSteps.ShowWaveform & guiMode + simulationSteps |= SimulationSteps.ShowReport + simulationSteps |= SimulationSteps.CleanUpAfter & cleanUp + elif (not (analyze or elaborate or optimize or simulate or resimulate or showWaveform or guiMode) and recompile): + simulationSteps |= SimulationSteps.Analyze | SimulationSteps.Elaborate #| SimulationSteps.Optimize + simulationSteps |= SimulationSteps.Recompile + simulationSteps |= SimulationSteps.ShowReport & showReport + simulationSteps |= SimulationSteps.CleanUpAfter & cleanUp + elif (not (analyze or elaborate or optimize or recompile or simulate or showWaveform) and resimulate): + simulationSteps |= SimulationSteps.Simulate + simulationSteps |= SimulationSteps.ShowWaveform & guiMode + simulationSteps |= SimulationSteps.ShowReport & showReport + simulationSteps |= SimulationSteps.CleanUpAfter & cleanUp + elif (recompile or resimulate): + raise SimulatorException("Combination of command line options is not allowed.") + else: + # simulationSteps |= SimulationSteps.CleanUpBefore & True #cleanup + simulationSteps |= SimulationSteps.Prepare & True #prepare + simulationSteps |= SimulationSteps.Analyze & analyze + simulationSteps |= SimulationSteps.Elaborate & elaborate + # simulationSteps |= SimulationSteps.Optimize & optimize + simulationSteps |= SimulationSteps.Simulate & simulate + simulationSteps |= SimulationSteps.ShowWaveform & (showWaveform or guiMode) + simulationSteps |= SimulationSteps.ShowReport & showReport + return simulationSteps + # ---------------------------------------------------------------------------- # create the sub-parser for the "list-testbench" command # ---------------------------------------------------------------------------- @@ -794,20 +845,21 @@ def HandleListTestbenches(self, args): @PoCEntityAttribute() @BoardDeviceAttributeGroup() @VHDLVersionAttribute() - @GUIModeAttribute() + @SimulationStepsAttribute() def HandleActiveHDLSimulation(self, args): self.PrintHeadline() self.__PrepareForSimulation() - fqnList = self._ExtractFQNs(args.FQN) - board = self._ExtractBoard(args.BoardName, args.DeviceName) - vhdlVersion = self._ExtractVHDLVersion(args.VHDLVersion) + fqnList = self._ExtractFQNs(args.FQN) + board = self._ExtractBoard(args.BoardName, args.DeviceName) + vhdlVersion = self._ExtractVHDLVersion(args.VHDLVersion) + simulationSteps = self._ExtractSimulationSteps(args.GUIMode, args.Analyze, args.Elaborate, False, args.Recompile, args.Simulate, args.ShowWave, args.Resimulate, args.ShowReport, False) # create a GHDLSimulator instance and prepare it - simulator = ActiveHDLSimulator(self, self.DryRun, args.GUIMode) - allPassed = simulator.RunAll(fqnList, board=board, vhdlVersion=vhdlVersion) # , vhdlGenerics=None) + simulator = ActiveHDLSimulator(self, self.DryRun, simulationSteps) + allPassed = simulator.RunAll(fqnList, board=board, vhdlVersion=vhdlVersion) - Exit.exit(0 if allPassed else 1) + Exit.exit(1 if ((SimulationSteps.Simulate in simulationSteps) and not allPassed) else 0) # ---------------------------------------------------------------------------- @@ -818,7 +870,7 @@ def HandleActiveHDLSimulation(self, args): @PoCEntityAttribute() @BoardDeviceAttributeGroup() @VHDLVersionAttribute() - @GUIModeAttribute() + @SimulationStepsAttribute() @ArgumentAttribute("--reproducer", metavar="Name", dest="CreateReproducer", help="Create a bug reproducer") def HandleGHDLSimulation(self, args): self.PrintHeadline() @@ -828,14 +880,15 @@ def HandleGHDLSimulation(self, args): if (not config.IsSupportedPlatform()): raise PlatformNotSupportedException() if (not config.IsConfigured()): raise NotConfiguredException("GHDL is not configured on this system.") - fqnList = self._ExtractFQNs(args.FQN) - board = self._ExtractBoard(args.BoardName, args.DeviceName) - vhdlVersion = self._ExtractVHDLVersion(args.VHDLVersion) + fqnList = self._ExtractFQNs(args.FQN) + board = self._ExtractBoard(args.BoardName, args.DeviceName) + vhdlVersion = self._ExtractVHDLVersion(args.VHDLVersion) + simulationSteps = self._ExtractSimulationSteps(args.GUIMode, args.Analyze, args.Elaborate, False, args.Recompile, args.Simulate, args.ShowWave, args.Resimulate, args.ShowReport, False) - simulator = GHDLSimulator(self, self.DryRun, args.GUIMode) - allPassed = simulator.RunAll(fqnList, board=board, vhdlVersion=vhdlVersion) #, vhdlGenerics=None) + simulator = GHDLSimulator(self, self.DryRun, simulationSteps) + allPassed = simulator.RunAll(fqnList, board=board, vhdlVersion=vhdlVersion) - Exit.exit(0 if allPassed else 1) + Exit.exit(1 if ((SimulationSteps.Simulate in simulationSteps) and not allPassed) else 0) # ---------------------------------------------------------------------------- @@ -845,19 +898,20 @@ def HandleGHDLSimulation(self, args): @CommandAttribute("isim", help="Simulate a PoC Entity with Xilinx ISE Simulator (iSim)") @PoCEntityAttribute() @BoardDeviceAttributeGroup() - @GUIModeAttribute() + @SimulationStepsAttribute() def HandleISESimulation(self, args): self.PrintHeadline() self.__PrepareForSimulation() self._CheckISEEnvironment() - fqnList = self._ExtractFQNs(args.FQN) - board = self._ExtractBoard(args.BoardName, args.DeviceName) + fqnList = self._ExtractFQNs(args.FQN) + board = self._ExtractBoard(args.BoardName, args.DeviceName) + simulationSteps = self._ExtractSimulationSteps(args.GUIMode, args.Analyze, args.Elaborate, False, args.Recompile, args.Simulate, args.ShowWave, args.Resimulate, args.ShowReport, False) - simulator = ISESimulator(self, self.DryRun, args.GUIMode) - allPassed = simulator.RunAll(fqnList, board=board, vhdlVersion=VHDLVersion.VHDL93) #, vhdlGenerics=None) + simulator = ISESimulator(self, self.DryRun, simulationSteps) + allPassed = simulator.RunAll(fqnList, board=board, vhdlVersion=VHDLVersion.VHDL93) - Exit.exit(0 if allPassed else 1) + Exit.exit(1 if ((SimulationSteps.Simulate in simulationSteps) and not allPassed) else 0) # ---------------------------------------------------------------------------- @@ -868,19 +922,22 @@ def HandleISESimulation(self, args): @PoCEntityAttribute() @BoardDeviceAttributeGroup() @VHDLVersionAttribute() - @GUIModeAttribute() + @SimulationStepsAttribute() def HandleQuestaSimulation(self, args): self.PrintHeadline() self.__PrepareForSimulation() - fqnList = self._ExtractFQNs(args.FQN) - board = self._ExtractBoard(args.BoardName, args.DeviceName) - vhdlVersion = self._ExtractVHDLVersion(args.VHDLVersion) + fqnList = self._ExtractFQNs(args.FQN) + board = self._ExtractBoard(args.BoardName, args.DeviceName) + vhdlVersion = self._ExtractVHDLVersion(args.VHDLVersion) + simulationSteps = self._ExtractSimulationSteps(args.GUIMode, args.Analyze, args.Elaborate, False, args.Recompile, args.Simulate, args.ShowWave, args.Resimulate, args.ShowReport, False) + + print(simulationSteps) - simulator = QuestaSimulator(self, self.DryRun, args.GUIMode) - allPassed = simulator.RunAll(fqnList, board=board, vhdlVersion=vhdlVersion) # , vhdlGenerics=None) + simulator = QuestaSimulator(self, self.DryRun, simulationSteps) + allPassed = simulator.RunAll(fqnList, board=board, vhdlVersion=vhdlVersion) - Exit.exit(0 if allPassed else 1) + Exit.exit(1 if ((SimulationSteps.Simulate in simulationSteps) and not allPassed) else 0) # ---------------------------------------------------------------------------- @@ -891,22 +948,23 @@ def HandleQuestaSimulation(self, args): @PoCEntityAttribute() @BoardDeviceAttributeGroup() @VHDLVersionAttribute() - @GUIModeAttribute() + @SimulationStepsAttribute() def HandleVivadoSimulation(self, args): self.PrintHeadline() self.__PrepareForSimulation() self._CheckVivadoEnvironment() - fqnList = self._ExtractFQNs(args.FQN) - board = self._ExtractBoard(args.BoardName, args.DeviceName) + fqnList = self._ExtractFQNs(args.FQN) + board = self._ExtractBoard(args.BoardName, args.DeviceName) # FIXME: VHDL-2008 is broken in Vivado 2016.1 -> use VHDL-93 by default - vhdlVersion = self._ExtractVHDLVersion(args.VHDLVersion, defaultVersion=VHDLVersion.VHDL93) + vhdlVersion = self._ExtractVHDLVersion(args.VHDLVersion, defaultVersion=VHDLVersion.VHDL93) + simulationSteps = self._ExtractSimulationSteps(args.GUIMode, args.Analyze, args.Elaborate, False, args.Recompile, args.Simulate, args.ShowWave, args.Resimulate, args.ShowReport, False) - simulator = VivadoSimulator(self, self.DryRun, args.GUIMode) - allPassed = simulator.RunAll(fqnList, board=board, vhdlVersion=vhdlVersion) # , vhdlGenerics=None) + simulator = VivadoSimulator(self, self.DryRun, simulationSteps) + allPassed = simulator.RunAll(fqnList, board=board, vhdlVersion=vhdlVersion) - Exit.exit(0 if allPassed else 1) + Exit.exit(1 if ((SimulationSteps.Simulate in simulationSteps) and not allPassed) else 0) # ---------------------------------------------------------------------------- @@ -916,7 +974,7 @@ def HandleVivadoSimulation(self, args): @CommandAttribute("cocotb", help="Simulate a PoC Entity with Cocotb and Questa Simulator") @PoCEntityAttribute() @BoardDeviceAttributeGroup() - @GUIModeAttribute() + @SimulationStepsAttribute() def HandleCocotbSimulation(self, args): self.PrintHeadline() self.__PrepareForSimulation() @@ -926,14 +984,15 @@ def HandleCocotbSimulation(self, args): if (len(self.PoCConfig.options("INSTALL.Altera.ModelSim")) == 0): raise NotConfiguredException("Neither Mentor QuestaSim nor Altera ModelSim is not configured on this system.") - fqnList = self._ExtractFQNs(args.FQN) - board = self._ExtractBoard(args.BoardName, args.DeviceName) + fqnList = self._ExtractFQNs(args.FQN) + board = self._ExtractBoard(args.BoardName, args.DeviceName) + simulationSteps = self._ExtractSimulationSteps(args.GUIMode, args.Analyze, args.Elaborate, False, args.Recompile, args.Simulate, args.ShowWave, args.Resimulate, args.ShowReport, False) # create a CocotbSimulator instance and prepare it - simulator = CocotbSimulator(self, self.DryRun, args.GUIMode) + simulator = CocotbSimulator(self, self.DryRun, simulationSteps) allPassed = simulator.RunAll(fqnList, board=board, vhdlVersion=VHDLVersion.VHDL2008) - Exit.exit(0 if allPassed else 1) + Exit.exit(1 if ((SimulationSteps.Simulate in simulationSteps) and not allPassed) else 0) # ============================================================================ @@ -980,7 +1039,7 @@ def HandleListNetlist(self, args): @CommandAttribute("ise", help="Generate any IP core for the Xilinx ISE tool chain") @PoCEntityAttribute() @BoardDeviceAttributeGroup() - @NoCleanUpAttribute() + @CompileStepsAttribute() def HandleISECompilation(self, args): self.PrintHeadline() self.__PrepareForSynthesis() @@ -1001,7 +1060,7 @@ def HandleISECompilation(self, args): @CommandAttribute("coregen", help="Generate an IP core with Xilinx ISE Core Generator") @PoCEntityAttribute() @BoardDeviceAttributeGroup() - @NoCleanUpAttribute() + @CompileStepsAttribute() def HandleCoreGeneratorCompilation(self, args): self.PrintHeadline() self.__PrepareForSynthesis() @@ -1022,7 +1081,7 @@ def HandleCoreGeneratorCompilation(self, args): @CommandAttribute("xst", help="Compile a PoC IP core with Xilinx ISE XST to a netlist") @PoCEntityAttribute() @BoardDeviceAttributeGroup() - @NoCleanUpAttribute() + @CompileStepsAttribute() def HandleXstCompilation(self, args): self.PrintHeadline() self.__PrepareForSynthesis() @@ -1043,7 +1102,7 @@ def HandleXstCompilation(self, args): @CommandAttribute("xci", help="Generate an IP core from Xilinx Vivado IP Catalog") @PoCEntityAttribute() @BoardDeviceAttributeGroup() - @NoCleanUpAttribute() + @CompileStepsAttribute() def HandleIpCatalogCompilation(self, args): self.PrintHeadline() self.__PrepareForSynthesis() @@ -1064,7 +1123,7 @@ def HandleIpCatalogCompilation(self, args): @CommandAttribute("vivado", help="Compile a PoC IP core with Xilinx Vivado Synth to a design checkpoint") @PoCEntityAttribute() @BoardDeviceAttributeGroup() - @NoCleanUpAttribute() + @CompileStepsAttribute() def HandleVivadoCompilation(self, args): self.PrintHeadline() self.__PrepareForSynthesis() @@ -1086,7 +1145,7 @@ def HandleVivadoCompilation(self, args): @CommandAttribute("quartus", help="Compile a PoC IP core with Altera Quartus II Map to a netlist") @PoCEntityAttribute() @BoardDeviceAttributeGroup() - @NoCleanUpAttribute() + @CompileStepsAttribute() def HandleQuartusCompilation(self, args): self.PrintHeadline() self.__PrepareForSynthesis() @@ -1110,7 +1169,7 @@ def HandleQuartusCompilation(self, args): @CommandAttribute("lse", help="Compile a PoC IP core with Lattice Diamond LSE to a netlist") @PoCEntityAttribute() @BoardDeviceAttributeGroup() - @NoCleanUpAttribute() + @CompileStepsAttribute() def HandleLSECompilation(self, args): self.PrintHeadline() self.__PrepareForSynthesis() diff --git a/py/Simulator/ActiveHDLSimulator.py b/py/Simulator/ActiveHDLSimulator.py index 3d78c156..4213f480 100644 --- a/py/Simulator/ActiveHDLSimulator.py +++ b/py/Simulator/ActiveHDLSimulator.py @@ -35,7 +35,7 @@ from Base.Exceptions import NotConfiguredException from Base.Project import FileTypes, ToolChain, Tool -from Base.Simulator import SimulatorException, Simulator as BaseSimulator, VHDL_TESTBENCH_LIBRARY_NAME, SkipableSimulatorException +from Base.Simulator import SimulatorException, Simulator as BaseSimulator, VHDL_TESTBENCH_LIBRARY_NAME, SkipableSimulatorException, SimulationSteps from ToolChains.Aldec.ActiveHDL import ActiveHDL, ActiveHDLException @@ -49,8 +49,8 @@ class Simulator(BaseSimulator): _TOOL_CHAIN = ToolChain.Aldec_ActiveHDL _TOOL = Tool.Aldec_aSim - def __init__(self, host, dryRun, guiMode): - super().__init__(host, dryRun, guiMode) + def __init__(self, host, dryRun, simulationSteps): + super().__init__(host, dryRun, simulationSteps) self._vhdlVersion = None self._vhdlGenerics = None @@ -109,7 +109,7 @@ def _RunAnalysis(self, _): raise SkipableSimulatorException("Error while compiling '{0!s}'.".format(file.Path)) def _RunSimulation(self, testbench): - if self._guiMode: + if (SimulationSteps.ShowWaveform in self._simulationSteps): return self._RunSimulationWithGUI(testbench) # tclBatchFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['aSimBatchScript'] diff --git a/py/Simulator/CocotbSimulator.py b/py/Simulator/CocotbSimulator.py index 8f21a00a..3b30db5a 100644 --- a/py/Simulator/CocotbSimulator.py +++ b/py/Simulator/CocotbSimulator.py @@ -37,7 +37,7 @@ from textwrap import dedent from Base.Project import FileTypes, ToolChain, Tool -from Base.Simulator import SimulatorException, Simulator as BaseSimulator +from Base.Simulator import SimulatorException, Simulator as BaseSimulator, SimulationSteps from DataBase.Config import Vendors from DataBase.Entity import WildCard from ToolChains.GNU import Make @@ -54,8 +54,8 @@ class Simulator(BaseSimulator): _TOOL = Tool.Cocotb_QuestaSim _COCOTB_SIMBUILD_DIRECTORY = "sim_build" - def __init__(self, host, dryRun, guiMode): - super().__init__(host, dryRun, guiMode) + def __init__(self, host, dryRun, simulationSteps): + super().__init__(host, dryRun, simulationSteps) configSection = host.PoCConfig['CONFIG.DirectoryNames'] self.Directories.Working = host.Directories.Temp / configSection['CocotbFiles'] @@ -174,5 +174,5 @@ def _RunSimulation(self, testbench): # mccabe:disable=MC0001 # execute make make = Make(self.Host.Platform, self.DryRun, logger=self.Logger) - if self._guiMode: make.Parameters[Make.SwitchGui] = 1 + if (SimulationSteps.ShowWaveform in self._simulationSteps): make.Parameters[Make.SwitchGui] = 1 testbench.Result = make.RunCocotb() diff --git a/py/Simulator/GHDLSimulator.py b/py/Simulator/GHDLSimulator.py index 97c8cea4..48eb8ba6 100644 --- a/py/Simulator/GHDLSimulator.py +++ b/py/Simulator/GHDLSimulator.py @@ -38,7 +38,7 @@ from Base.Exceptions import NotConfiguredException from Base.Logging import Severity from Base.Project import FileTypes, VHDLVersion, ToolChain, Tool -from Base.Simulator import SimulatorException, Simulator as BaseSimulator, VHDL_TESTBENCH_LIBRARY_NAME, SkipableSimulatorException +from Base.Simulator import SimulatorException, Simulator as BaseSimulator, VHDL_TESTBENCH_LIBRARY_NAME, SkipableSimulatorException, SimulationSteps from ToolChains.GHDL import GHDL, GHDLException, GHDLReanalyzeException from ToolChains.GTKWave import GTKWave @@ -58,9 +58,9 @@ class Simulator(BaseSimulator): class __Directories__(BaseSimulator.__Directories__): GTKWBinary = None - def __init__(self, host, dryRun, guiMode): + def __init__(self, host, dryRun, simulationSteps): """Constructor""" - super().__init__(host, dryRun, guiMode) + super().__init__(host, dryRun, simulationSteps) self._vhdlGenerics = None self._toolChain = None @@ -69,7 +69,14 @@ def __init__(self, host, dryRun, guiMode): self.Directories.Working = host.Directories.Temp / ghdlFilesDirectoryName self.Directories.PreCompiled = host.Directories.PreCompiled / ghdlFilesDirectoryName - if (self._guiMode is True): + self._PrepareSimulationEnvironment() + self._PrepareSimulator() + + if (self._toolChain.Backend == "mcode"): + # A separate elaboration step is not implemented in GHDL (mcode) + self._simulationSteps &= ~SimulationSteps.Elaborate + + if (SimulationSteps.ShowWaveform in self._simulationSteps): # prepare paths for GTKWave, if configured sectionName = 'INSTALL.GTKWave' if (len(host.PoCConfig.options(sectionName)) != 0): @@ -77,13 +84,8 @@ def __init__(self, host, dryRun, guiMode): else: raise NotConfiguredException("No GHDL compatible waveform viewer is configured on this system.") - self._PrepareSimulationEnvironment() - self._PrepareSimulator() - def _PrepareSimulator(self): - """""" - - # create the GHDL executable factory + """Create the GHDL executable factory instance.""" self.LogVerbose("Preparing GHDL simulator.") ghdlSection = self.Host.PoCConfig['INSTALL.GHDL'] binaryPath = Path(ghdlSection['BinaryDirectory']) @@ -191,7 +193,7 @@ def _RunSimulation(self, testbench): # configure RUNOPTS ghdl.RunOptions[ghdl.SwitchIEEEAsserts] = "disable-at-0" # enable, disable, disable-at-0 # set dump format to save simulation results to *.vcd file - if (self._guiMode): + if (SimulationSteps.ShowWaveform in self._simulationSteps): configSection = self.Host.PoCConfig[testbench.ConfigSectionName] testbench.WaveformOptionFile = Path(configSection['ghdlWaveformOptionFile']) testbench.WaveformFileFormat = configSection['ghdlWaveformFileFormat'] diff --git a/py/Simulator/ISESimulator.py b/py/Simulator/ISESimulator.py index d9559436..d90d1305 100644 --- a/py/Simulator/ISESimulator.py +++ b/py/Simulator/ISESimulator.py @@ -36,7 +36,7 @@ from pathlib import Path from Base.Project import ToolChain, Tool -from Base.Simulator import SimulatorException, Simulator as BaseSimulator, VHDL_TESTBENCH_LIBRARY_NAME, SkipableSimulatorException +from Base.Simulator import SimulatorException, Simulator as BaseSimulator, VHDL_TESTBENCH_LIBRARY_NAME, SkipableSimulatorException, SimulationSteps from ToolChains.Xilinx.Xilinx import XilinxProjectExportMixIn from ToolChains.Xilinx.ISE import ISE, ISESimulator, ISEException @@ -51,8 +51,8 @@ class Simulator(BaseSimulator, XilinxProjectExportMixIn): _TOOL_CHAIN = ToolChain.Xilinx_ISE _TOOL = Tool.Xilinx_iSim - def __init__(self, host, dryRun, guiMode): - super().__init__(host, dryRun, guiMode) + def __init__(self, host, dryRun, simulationSteps): + super().__init__(host, dryRun, simulationSteps) XilinxProjectExportMixIn.__init__(self) self._vhdlGenerics = None @@ -106,7 +106,7 @@ def _RunSimulation(self, testbench): iSim = ISESimulator(self._host.Platform, self._host.DryRun, exeFilePath, logger=self.Logger) iSim.Parameters[iSim.SwitchLogFile] = str(iSimLogFilePath) - if (not self._guiMode): + if (SimulationSteps.ShowWaveform not in self._simulationSteps): iSim.Parameters[iSim.SwitchTclBatchFile] = str(tclBatchFilePath) else: iSim.Parameters[iSim.SwitchTclBatchFile] = str(tclGUIFilePath) diff --git a/py/Simulator/QuestaSimulator.py b/py/Simulator/QuestaSimulator.py index 1bc5e5b2..7094c980 100644 --- a/py/Simulator/QuestaSimulator.py +++ b/py/Simulator/QuestaSimulator.py @@ -31,12 +31,16 @@ # ============================================================================== # # load dependencies +from datetime import datetime from pathlib import Path +from textwrap import dedent +from lib.Functions import Init from Base.Exceptions import NotConfiguredException from Base.Project import FileTypes, ToolChain, Tool -from Base.Simulator import SimulatorException, Simulator as BaseSimulator, VHDL_TESTBENCH_LIBRARY_NAME, SkipableSimulatorException -from DataBase.Config import Vendors +from Base.Simulator import SimulatorException, Simulator as BaseSimulator, VHDL_TESTBENCH_LIBRARY_NAME, SkipableSimulatorException, SimulationState, SimulationResult, \ + SimulationSteps +from DataBase.Config import Vendors from ToolChains.Mentor.QuestaSim import QuestaSim, QuestaSimException @@ -50,8 +54,10 @@ class Simulator(BaseSimulator): _TOOL_CHAIN = ToolChain.Mentor_QuestaSim _TOOL = Tool.Mentor_vSim - def __init__(self, host, dryRun, guiMode): - super().__init__(host, dryRun, guiMode) + def __init__(self, host, dryRun, simulationSteps): + # A separate elaboration step is not implemented in QuestaSim + simulationSteps &= ~SimulationSteps.Elaborate + super().__init__(host, dryRun, simulationSteps) self._vhdlVersion = None self._vhdlGenerics = None @@ -61,8 +67,12 @@ def __init__(self, host, dryRun, guiMode): self.Directories.Working = host.Directories.Temp / vSimSimulatorFiles self.Directories.PreCompiled = host.Directories.PreCompiled / vSimSimulatorFiles - self._PrepareSimulationEnvironment() - self._PrepareSimulator() + if (SimulationSteps.CleanUpBefore in self._simulationSteps): + pass + + if (SimulationSteps.Prepare in self._simulationSteps): + self._PrepareSimulationEnvironment() + self._PrepareSimulator() def _PrepareSimulator(self): # create the QuestaSim executable factory @@ -79,7 +89,7 @@ def _PrepareSimulator(self): version = questaSection['Version'] self._toolChain = QuestaSim(self.Host.Platform, self.DryRun, binaryPath, version, logger=self.Logger) - def Run(self, testbench, board, vhdlVersion, vhdlGenerics=None, guiMode=False): + def Run(self, testbench, board, vhdlVersion, vhdlGenerics=None): # TODO: refactor into a ModelSim module, shared by QuestaSim and Cocotb (-> MixIn class)? # select modelsim.ini self._modelsimIniPath = self.Directories.PreCompiled @@ -95,7 +105,7 @@ def Run(self, testbench, board, vhdlVersion, vhdlGenerics=None, guiMode=False): raise SimulatorException("Modelsim ini file '{0!s}' not found.".format(self._modelsimIniPath)) \ from FileNotFoundError(str(self._modelsimIniPath)) - super().Run(testbench, board, vhdlVersion, vhdlGenerics, guiMode) + super().Run(testbench, board, vhdlVersion, vhdlGenerics) def _RunAnalysis(self, _): # create a QuestaVHDLCompiler instance @@ -112,6 +122,10 @@ def _RunAnalysis(self, _): vcom.Parameters[vcom.SwitchModelSimIniFile] = self._modelsimIniPath.as_posix() vcom.Parameters[vcom.SwitchVHDLVersion] = repr(self._vhdlVersion) + recompileScriptContent = dedent("""\ + puts "Recompiling..." + """) + # run vcom compile for each VHDL file for file in self._pocProject.Files(fileType=FileTypes.VHDLSourceFile): if (not file.Path.exists()): raise SimulatorException("Cannot analyse '{0!s}'.".format(file.Path)) from FileNotFoundError(str(file.Path)) @@ -135,8 +149,30 @@ def _RunAnalysis(self, _): except OSError as ex: raise SimulatorException("Error while deleting '{0!s}'.".format(vcomLogFile)) from ex + # collecting all compile commands in a buffer + recompileScriptContent += dedent("""\ + puts " Compiling '{file}'..." + {tcl} + """).format( + file=file.Path.as_posix(), + tcl=vcom.GetTclCommand() + ) + + recompileScriptContent += dedent("""\ + puts "Recompilation done" + puts "Restarting simulation..." + restart -force + puts "Simulation is restarted." + """) + recompileScriptContent = recompileScriptContent.replace("\\", "/") # WORKAROUND: to convert all paths to Tcl compatible paths. + + recompileScriptPath = self.Directories.Working / "recompile.do" + self.LogDebug("Writing recompile script to '{0!s}'".format(recompileScriptPath)) + with recompileScriptPath.open('w') as fileHandle: + fileHandle.write(recompileScriptContent) + def _RunSimulation(self, testbench): - if self._guiMode: + if (SimulationSteps.ShowWaveform in self._simulationSteps): return self._RunSimulationWithGUI(testbench) tclBatchFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['vSimBatchScript'] @@ -214,16 +250,50 @@ def _RunSimulationWithGUI(self, testbench): vsimBatchCommand = "{0};".format(vsimDefaultWaveCommands) # find a Tcl batch script for the GUI mode + vsimRunScript = "" if (tclGUIFilePath.exists()): self.LogDebug("Found Tcl script for GUI mode: '{0!s}'".format(tclGUIFilePath)) - vsimBatchCommand += "do {0};".format(tclGUIFilePath.as_posix()) + vsimRunScript = tclGUIFilePath.as_posix() + vsimBatchCommand += "do {0};".format(vsimRunScript) elif (tclDefaultGUIFilePath.exists()): self.LogDebug("Falling back to default Tcl script for GUI mode: '{0!s}'".format(tclDefaultGUIFilePath)) - vsimBatchCommand += "do {0};".format(tclDefaultGUIFilePath.as_posix()) + vsimRunScript = tclDefaultGUIFilePath.as_posix() + vsimBatchCommand += "do {0};".format(vsimRunScript) else: raise QuestaSimException("No Tcl batch script for GUI mode found.") \ from FileNotFoundError(str(tclDefaultGUIFilePath)) vsim.Parameters[vsim.SwitchBatchCommand] = vsimBatchCommand + # writing a relaunch file + recompileScriptPath = self.Directories.Working / "recompile.do" + relaunchScriptPath = self.Directories.Working / "relaunch.do" + saveWaveformScriptPath = self.Directories.Working / "saveWaveform.do" + + relaunchScriptContent = dedent("""\ + puts "Loading recompile script '{recompileScript}'..." + do {recompileScript} + puts "Loading run script '{runScript}'..." + do {runScript} + """).format( + recompileScript=recompileScriptPath.as_posix(), + runScript=vsimRunScript + ) + + self.LogDebug("Writing relaunch script to '{0!s}'".format(relaunchScriptPath)) + with relaunchScriptPath.open('w') as fileHandle: + fileHandle.write(relaunchScriptContent) + + # writing a saveWaveform file + saveWaveformScriptContent = dedent("""\ + puts "Saving waveform settings to '{waveformFile}'..." + write format wave -window .main_pane.wave.interior.cs.body.pw.wf {waveformFile} + """).format( + waveformFile=tclWaveFilePath.as_posix() + ) + + self.LogDebug("Writing saveWaveform script to '{0!s}'".format(saveWaveformScriptPath)) + with saveWaveformScriptPath.open('w') as fileHandle: + fileHandle.write(saveWaveformScriptContent) + testbench.Result = vsim.Simulate() diff --git a/py/Simulator/VivadoSimulator.py b/py/Simulator/VivadoSimulator.py index a14fcf0f..0f41c283 100644 --- a/py/Simulator/VivadoSimulator.py +++ b/py/Simulator/VivadoSimulator.py @@ -36,7 +36,7 @@ from pathlib import Path from Base.Project import ToolChain, Tool -from Base.Simulator import SimulatorException, Simulator as BaseSimulator, VHDL_TESTBENCH_LIBRARY_NAME, SkipableSimulatorException +from Base.Simulator import SimulatorException, Simulator as BaseSimulator, VHDL_TESTBENCH_LIBRARY_NAME, SkipableSimulatorException, SimulationSteps from Base.Logging import Severity from ToolChains.Xilinx.Xilinx import XilinxProjectExportMixIn from ToolChains.Xilinx.Vivado import Vivado, VivadoException @@ -52,8 +52,8 @@ class Simulator(BaseSimulator, XilinxProjectExportMixIn): _TOOL_CHAIN = ToolChain.Xilinx_Vivado _TOOL = Tool.Xilinx_xSim - def __init__(self, host, dryRun, guiMode): - super().__init__(host, dryRun, guiMode) + def __init__(self, host, dryRun, simulationSteps): + super().__init__(host, dryRun, simulationSteps) XilinxProjectExportMixIn.__init__(self) self._vhdlVersion = None @@ -110,18 +110,18 @@ def _RunSimulation(self, testbench): # create a VivadoSimulator instance xSim = self._toolChain.GetSimulator() - xSim.Parameters[xSim.SwitchLogFile] = str(xSimLogFilePath) + xSim.Parameters[xSim.SwitchLogFile] = str(xSimLogFilePath) - if (not self._guiMode): - xSim.Parameters[xSim.SwitchTclBatchFile] = str(tclBatchFilePath) + if (SimulationSteps.ShowWaveform not in self._simulationSteps): + xSim.Parameters[xSim.SwitchTclBatchFile] = tclBatchFilePath.as_posix() else: - xSim.Parameters[xSim.SwitchTclBatchFile] = str(tclGUIFilePath) - xSim.Parameters[xSim.FlagGuiMode] = True + xSim.Parameters[xSim.SwitchTclBatchFile] = tclGUIFilePath.as_posix() + xSim.Parameters[xSim.FlagGuiMode] = True # if xSim save file exists, load it's settings if wcfgFilePath.exists(): self.LogDebug("Found waveform config file: '{0!s}'".format(wcfgFilePath)) - xSim.Parameters[xSim.SwitchWaveformFile] = str(wcfgFilePath) + xSim.Parameters[xSim.SwitchWaveformFile] = str(wcfgFilePath) else: self.LogDebug("Didn't find waveform config file: '{0!s}'".format(wcfgFilePath)) diff --git a/py/ToolChains/Mentor/QuestaSim.py b/py/ToolChains/Mentor/QuestaSim.py index 84772a93..30319aa3 100644 --- a/py/ToolChains/Mentor/QuestaSim.py +++ b/py/ToolChains/Mentor/QuestaSim.py @@ -36,7 +36,7 @@ from subprocess import check_output from textwrap import dedent -from lib.Functions import CallByRefParam +from lib.Functions import CallByRefParam, Init from Base.Exceptions import PlatformNotSupportedException from Base.Logging import LogEntry, Severity from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException @@ -186,42 +186,42 @@ def HasErrors(self): return self._hasErrors class Executable(metaclass=ExecutableArgument): - _value = None + _value = None class FlagTime(metaclass=ShortFlagArgument): - _name = "time" # Print the compilation wall clock time - _value = None + _name = "time" # Print the compilation wall clock time + _value = None class FlagExplicit(metaclass=ShortFlagArgument): - _name = "explicit" - _value = None + _name = "explicit" + _value = None class FlagQuietMode(metaclass=ShortFlagArgument): - _name = "quiet" # Do not report 'Loading...' messages" - _value = None + _name = "quiet" # Do not report 'Loading...' messages" + _value = None class SwitchModelSimIniFile(metaclass=ShortTupleArgument): - _name = "modelsimini" - _value = None + _name = "modelsimini" + _value = None class FlagRangeCheck(metaclass=ShortFlagArgument): - _name = "rangecheck" - _value = None + _name = "rangecheck" + _value = None class SwitchVHDLVersion(metaclass=StringArgument): _pattern = "-{0}" _value = None class ArgLogFile(metaclass=ShortTupleArgument): - _name = "l" # what's the difference to -logfile ? - _value = None + _name = "l" # what's the difference to -logfile ? + _value = None class SwitchVHDLLibrary(metaclass=ShortTupleArgument): - _name = "work" - _value = None + _name = "work" + _value = None class ArgSourceFile(metaclass=PathArgument): - _value = None + _value = None Parameters = CommandLineArgumentList( Executable, @@ -276,6 +276,11 @@ def Compile(self): if self._hasOutput: self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) + def GetTclCommand(self): + parameterList = self.Parameters.ToArgumentList() + return "vcom " + " ".join(parameterList[1:]) + + class QuestaSimulator(Executable, QuestaSimMixIn): def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): QuestaSimMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) @@ -519,7 +524,12 @@ def QuestaVSimFilter(gen): yield LogEntry(line, Severity.Error) elif line.startswith("** Fatal: "): yield LogEntry(line, Severity.Error) - elif line.startswith("# "): + elif line.startswith("# %%"): + if ("ERROR" in line): + yield LogEntry("{DARK_RED}{line}{NOCOLOR}".format(line=line[2:], **Init.Foreground), Severity.Error) + else: + yield LogEntry("{DARK_CYAN}{line}{NOCOLOR}".format(line=line[2:], **Init.Foreground), Severity.Normal) + elif line.startswith("# "): if (not PoCOutputFound): yield LogEntry(line, Severity.Verbose) else: diff --git a/py/lib/Decorators.py b/py/lib/Decorators.py index b8211a6c..14c69221 100644 --- a/py/lib/Decorators.py +++ b/py/lib/Decorators.py @@ -35,6 +35,7 @@ __api__ = [ + 'MethodAlias', 'ILazyLoadable', 'LazyLoadTrigger', 'CachedReadOnlyProperty' @@ -42,6 +43,14 @@ __all__ = __api__ +class MethodAlias: + def __init__(self, method): + self.method = method + + def __call__(self, func): + return self.method + + class ILazyLoadable: def __init__(self): self.__IsLoaded = False diff --git a/py/lib/ExtendedConfigParser/__init__.py b/py/lib/ExtendedConfigParser/__init__.py index b9c05521..53dcf847 100644 --- a/py/lib/ExtendedConfigParser/__init__.py +++ b/py/lib/ExtendedConfigParser/__init__.py @@ -365,8 +365,8 @@ def _unify_values(self, section, variables): def has_option(self, section, option): """Check for the existence of a given option in a given section. - If the specified `section' is None or an empty string, DEFAULT is - assumed. If the specified `section' does not exist, returns False.""" + If the specified `section` is None or an empty string, DEFAULT is + assumed. If the specified `section` does not exist, returns False.""" option = self.optionxform(option) if ((not section) or (section == self.default_section)): sect = self._defaults diff --git a/sim/vSim.gui.tcl b/sim/vSim.gui.tcl index 668a24df..d694be4f 100644 --- a/sim/vSim.gui.tcl +++ b/sim/vSim.gui.tcl @@ -1,2 +1,6 @@ run -all wave zoom full +puts "Provided files:" +puts "- 'do recompile.do' compile all sources from scratch and restart the simulation" +puts "- 'do relaunch.do' recompile, restart and rerun the simulation" +puts "- 'do saveWaveform.do' save current waveform selection to a *.wdo file" diff --git a/src/bus/stream/stream_Buffer.vhdl b/src/bus/stream/stream_Buffer.vhdl index be66668c..df1f38ab 100644 --- a/src/bus/stream/stream_Buffer.vhdl +++ b/src/bus/stream/stream_Buffer.vhdl @@ -9,7 +9,7 @@ -- Description: -- ------------------------------------- -- This module implements a generic buffer (FIFO) for the --- :doc:`PoC.Stream ` protocol. It is generic in +-- :doc:`PoC.Stream ` protocol. It is generic in -- ``DATA_BITS`` and in ``META_BITS`` as well as in FIFO depths for data and -- meta information. -- diff --git a/src/fifo/fifo_cc_got.vhdl b/src/fifo/fifo_cc_got.vhdl index 9c72d7ac..145f2768 100644 --- a/src/fifo/fifo_cc_got.vhdl +++ b/src/fifo/fifo_cc_got.vhdl @@ -60,16 +60,16 @@ -- +-----------+----------------------+ -- -- SeeAlso: --- :doc:`PoC.fifo.dc_got ` +-- :ref:`IP:fifo_dc_got` -- For a FIFO with dependent clocks. --- :doc:`PoC.fifo.ic_got ` +-- :ref:`IP:fifo_ic_got` -- For a FIFO with independent clocks (cross-clock FIFO). --- :doc:`PoC.fifo.glue ` +-- :ref:`IP:fifo_glue` -- For a minimal FIFO / pipeline decoupling. -- -- License: -- ============================================================================= --- Copyright 2007-2015 Technische Universitaet Dresden - Germany, +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl b/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl index 6e62941c..bac83d84 100644 --- a/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl +++ b/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl @@ -9,7 +9,7 @@ -- -- Description: -- ------------------------------------ --- Adapter between the :doc:`PoC.Mem ` +-- Adapter between the :doc:`PoC.Mem ` -- interface and the User Interface of the Xilinx MIG IP core for the -- Spartan-6 FPGA Memory Controller Block (MCB). The MCB can be configured to -- have multiple ports. One instance of this adapter is required for every @@ -20,7 +20,7 @@ -- The PoC.Mem interface provides single-cycle fully pipelined read/write access -- to the memory. All accesses are word-aligned. Always all bytes of a word are -- written to the memory. More details can be found --- :doc:`here `. +-- :doc:`here `. -- -- Generic parameters: -- diff --git a/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl b/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl index f2539019..13730862 100644 --- a/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl +++ b/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl @@ -9,7 +9,7 @@ -- -- Description: -- ------------------------------------ --- Adapter between the :doc:`PoC.Mem ` +-- Adapter between the :doc:`PoC.Mem ` -- interface and the application interface ("app") -- of the Xilinx MIG IP core for 7-Series FPGAs. -- @@ -17,7 +17,7 @@ -- The PoC.Mem interface provides single-cycle fully pipelined read/write access -- to the memory. All accesses are word-aligned. Always all bytes of a word are -- written to the memory. More details can be found --- :doc:`here `. +-- :doc:`here `. -- -- Generic parameters: -- diff --git a/src/misc/sync/sync_Bits.vhdl b/src/misc/sync/sync_Bits.vhdl index 05f5e167..6a3da367 100644 --- a/src/misc/sync/sync_Bits.vhdl +++ b/src/misc/sync/sync_Bits.vhdl @@ -29,13 +29,13 @@ -- TODO -- -- SeeAlso: --- :doc:`PoC.misc.sync.Reset ` +-- :doc:`PoC.misc.sync.Reset ` -- For a special 2 D-FF synchronizer for *reset*-signals. --- :doc:`PoC.misc.sync.Pulse ` +-- :doc:`PoC.misc.sync.Pulse ` -- For a special 1+2 D-FF synchronizer for *pulse*-signals. --- :doc:`PoC.misc.sync.Strobe ` +-- :doc:`PoC.misc.sync.Strobe ` -- For a synchronizer for *strobe*-signals. --- :doc:`PoC.misc.sync.Vector ` +-- :doc:`PoC.misc.sync.Vector ` -- For a multiple bits capable synchronizer. -- -- License: diff --git a/src/misc/sync/sync_Pulse.vhdl b/src/misc/sync/sync_Pulse.vhdl index eb6f9189..536ba161 100644 --- a/src/misc/sync/sync_Pulse.vhdl +++ b/src/misc/sync/sync_Pulse.vhdl @@ -29,13 +29,13 @@ -- TODO -- -- SeeAlso: --- :doc:`PoC.misc.sync.Bits ` +-- :doc:`PoC.misc.sync.Bits ` -- For a common 2 D-FF synchronizer for *flag*-signals. --- :doc:`PoC.misc.sync.Reset ` +-- :doc:`PoC.misc.sync.Reset ` -- For a special 2 D-FF synchronizer for *reset*-signals. --- :doc:`PoC.misc.sync.Strobe ` +-- :doc:`PoC.misc.sync.Strobe ` -- For a synchronizer for *strobe*-signals. --- :doc:`PoC.misc.sync.Vector ` +-- :doc:`PoC.misc.sync.Vector ` -- For a multiple bits capable synchronizer. -- -- License: diff --git a/tools/precompile/precompile.psm1 b/tools/precompile/precompile.psm1 index 640a51e7..c9ae750e 100644 --- a/tools/precompile/precompile.psm1 +++ b/tools/precompile/precompile.psm1 @@ -40,7 +40,7 @@ param( $Module_WorkingDir = $WorkingDir function Exit-PrecompileScript -{ <# +{ <# .SYNOPSIS Undocumented From 04c4beb62558d123a716f00718a41d2e85bf7d2a Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 17 Nov 2016 03:18:38 +0100 Subject: [PATCH 39/97] Changed Landscape.io settings back (part 1). --- .landscape.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.landscape.yml b/.landscape.yml index a546f410..3f8858a6 100644 --- a/.landscape.yml +++ b/.landscape.yml @@ -5,7 +5,7 @@ python-targets: # - py-flags # doc-warnings: yes test-warnings: no -strictness: high +strictness: medium max-line-length: 180 pylint: disable: From 402babec7d361eb2b18192b3bd85ae8ea6fd25a7 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Nov 2016 13:59:24 +0100 Subject: [PATCH 40/97] Major documentation update. New linking strategy in documentation. Fixed configuration routines for ModelSim. Improved MixIn classes for Executable classes. Removed PSCX dependency. --- .gitignore | 3 + docs/ChangeLog/index.rst | 13 + docs/ChangeLog/template.rst | 30 + docs/ConstraintFiles/index.rst | 23 +- docs/GetInvolved/Authors.rst | 2 +- docs/IPCores/arith/arith.pkg.rst | 9 + docs/IPCores/bus/stream/index.rst | 6 + docs/IPCores/bus/stream/stream.pkg.rst | 16 + docs/IPCores/bus/wb/index.rst | 5 + docs/IPCores/bus/wb/wb.pkg.rst | 16 + docs/IPCores/comm/comm.pkg.rst | 15 + docs/IPCores/comm/index.rst | 6 + docs/IPCores/fifo/fifo.pkg.rst | 3 +- docs/IPCores/io/ddrio/ddrio.pkg.rst | 16 + docs/IPCores/io/ddrio/ddrio_in.rst | 16 +- docs/IPCores/io/ddrio/index.rst | 5 + docs/IPCores/io/iic/iic.pkg.rst | 16 + docs/IPCores/io/iic/index.rst | 5 + docs/IPCores/io/io.pkg.rst | 9 + docs/IPCores/io/lcd/index.rst | 5 + docs/IPCores/io/lcd/lcd.pkg.rst | 16 + docs/IPCores/io/pmod/index.rst | 5 + docs/IPCores/io/pmod/pmod.pkg.rst | 16 + docs/IPCores/io/uart/index.rst | 5 + docs/IPCores/io/uart/uart.pkg.rst | 16 + docs/IPCores/io/vga/index.rst | 5 + docs/IPCores/io/vga/vga.pkg.rst | 16 + .../ddr2/ddr2_mem2mig_adapter_Spartan6.rst | 4 +- .../mem/ddr3/ddr3_mem2mig_adapter_Series7.rst | 9 +- docs/IPCores/mem/index.rst | 4 +- docs/IPCores/mem/mem.pkg.rst | 9 + docs/IPCores/mem/ocram/index.rst | 6 + docs/IPCores/mem/ocram/ocram.pkg.rst | 16 + docs/IPCores/mem/ocram/ocram_esdp.rst | 8 +- docs/IPCores/mem/ocrom/index.rst | 5 + docs/IPCores/mem/ocrom/ocrom.pkg.rst | 16 + docs/IPCores/mem/sdram/sdram_ctrl_de0.rst | 4 +- docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst | 2 +- docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst | 2 +- .../mem/sdram/sdram_ctrl_phy_s3esk.rst | 4 +- docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst | 2 +- docs/IPCores/misc/misc.pkg.rst | 9 + docs/IPCores/misc/sync/index.rst | 5 + docs/IPCores/misc/sync/sync.pkg.rst | 16 + docs/IPCores/net/net.pkg.rst | 15 + docs/IPCores/sort/sortnet/index.rst | 5 + docs/IPCores/sort/sortnet/sortnet.pkg.rst | 36 + docs/IPCores/xil/xil.pkg.rst | 17 + docs/Interfaces/CommandStatusError.rst | 2 +- docs/Interfaces/FIFO.rst | 2 +- docs/Interfaces/Memory.rst | 2 +- docs/Interfaces/Stream.rst | 2 +- docs/Interfaces/index.rst | 5 +- docs/Miscelaneous/ChangeLog.rst | 514 ------------ docs/Miscelaneous/ThirdParty.rst | 37 +- docs/QuickStart.rst | 105 ++- docs/References/CmdRefs/Compile.rst | 14 +- docs/References/CmdRefs/PoC.rst | 168 +++- docs/References/CommandReference.rst | 2 +- docs/UsingPoC/AddingIPCores.rst | 1 + docs/UsingPoC/Download.rst | 37 +- docs/UsingPoC/Integration.rst | 4 +- docs/UsingPoC/PoCConfiguration.rst | 73 +- docs/UsingPoC/PrecompilingVendorLibraries.rst | 755 ++++++++++++------ docs/UsingPoC/ProjectManagement.rst | 1 + docs/UsingPoC/Requirements.rst | 133 +-- docs/UsingPoC/Simulation.rst | 27 +- docs/UsingPoC/Synthesis.rst | 237 +++--- docs/UsingPoC/VHDLConfiguration.rst | 6 + docs/UsingPoC/index.rst | 15 +- docs/WhatIsPoC/SupportedToolChains.rst | 20 +- docs/_extensions/DocumentMember.py | 55 ++ docs/_extensions/autoprogram.py | 407 ++++++++++ docs/_static/css/custom.css | 3 + docs/_templates/autoapi/module.rst | 18 +- docs/_templates/autoapi/script.rst | 16 +- docs/conf.py | 114 ++- docs/index.rst | 14 +- docs/poc.py | 5 +- lib/Altera.files | 2 +- lib/OSVVM.files | 2 +- lib/UVVM.files | 2 +- lib/Xilinx.files | 2 +- py/Base/Compiler.py | 60 +- py/Base/Configuration.py | 18 +- py/Base/Exceptions.py | 36 +- py/Base/Project.py | 2 + py/Base/Simulator.py | 39 +- py/PoC.py | 92 ++- py/Simulator/QuestaSimulator.py | 11 +- py/ToolChains/Aldec/ActiveHDL.py | 74 +- py/ToolChains/Aldec/Aldec.py | 2 +- py/ToolChains/Altera/ModelSim.py | 13 +- py/ToolChains/Altera/Quartus.py | 53 +- py/ToolChains/Git.py | 66 +- py/ToolChains/Lattice/Diamond.py | 34 +- py/ToolChains/Mentor/QuestaSim.py | 66 +- py/ToolChains/PoC.py | 2 +- py/ToolChains/Xilinx/ISE.py | 73 +- py/ToolChains/Xilinx/Vivado.py | 68 +- py/ToolChains/__init__.py | 16 +- py/Wrapper/PoC.psm1 | 21 + py/Wrapper/Xilinx.ISE.psm1 | 7 - py/Wrapper/Xilinx.Vivado.psm1 | 7 - py/Wrapper/wrapper.sh | 9 +- py/config.defaults.ini | 1 - py/lib/Decorators.py | 8 + py/lib/pyAttribute/ArgParseAttributes.py | 6 +- py/lib/pyAttribute/__init__.py | 8 +- sim/sort/sortnet/sortnet_BitonicSort_tb.wdo | 40 + src/io/ddrio/ddrio_in.vhdl | 16 +- .../ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl | 4 +- .../ddr3/ddr3_mem2mig_adapter_Series7.vhdl | 7 +- src/mem/ocram/ocram_esdp.vhdl | 8 +- src/mem/sdram/sdram_ctrl_de0.vhdl | 24 +- src/mem/sdram/sdram_ctrl_fsm.vhdl | 20 - src/mem/sdram/sdram_ctrl_phy_de0.vhdl | 4 +- src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl | 24 +- src/mem/sdram/sdram_ctrl_s3esk.vhdl | 22 +- tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl | 106 ++- tools/ReadTheDocs/requirements.txt | 6 + tools/precompile/compile-osvvm.ps1 | 13 +- tools/precompile/compile-osvvm.sh | 2 + 123 files changed, 2852 insertions(+), 1530 deletions(-) create mode 100644 docs/ChangeLog/index.rst create mode 100644 docs/ChangeLog/template.rst create mode 100644 docs/IPCores/bus/stream/stream.pkg.rst create mode 100644 docs/IPCores/bus/wb/wb.pkg.rst create mode 100644 docs/IPCores/comm/comm.pkg.rst create mode 100644 docs/IPCores/io/ddrio/ddrio.pkg.rst create mode 100644 docs/IPCores/io/iic/iic.pkg.rst create mode 100644 docs/IPCores/io/lcd/lcd.pkg.rst create mode 100644 docs/IPCores/io/pmod/pmod.pkg.rst create mode 100644 docs/IPCores/io/uart/uart.pkg.rst create mode 100644 docs/IPCores/io/vga/vga.pkg.rst create mode 100644 docs/IPCores/mem/ocram/ocram.pkg.rst create mode 100644 docs/IPCores/mem/ocrom/ocrom.pkg.rst create mode 100644 docs/IPCores/misc/sync/sync.pkg.rst create mode 100644 docs/IPCores/net/net.pkg.rst create mode 100644 docs/IPCores/sort/sortnet/sortnet.pkg.rst create mode 100644 docs/IPCores/xil/xil.pkg.rst delete mode 100644 docs/Miscelaneous/ChangeLog.rst create mode 100644 docs/_extensions/DocumentMember.py create mode 100644 docs/_extensions/autoprogram.py create mode 100644 docs/_static/css/custom.css diff --git a/.gitignore b/.gitignore index 0eca46e0..40fb9426 100644 --- a/.gitignore +++ b/.gitignore @@ -12,6 +12,8 @@ __pycache__ /docs/_build/ /docs/PyInfrastructure/* !/docs/PyInfrastructure/.gitempty +!/docs/PyInfrastructure/.publish +!/docs/PyInfrastructure/README.md !/docs/PyInfrastructure/index.rst @@ -98,3 +100,4 @@ other/diamond/.spreadsheet_view.ini !.git* !.publish !README.md +other/PrecisionRTL/ diff --git a/docs/ChangeLog/index.rst b/docs/ChangeLog/index.rst new file mode 100644 index 00000000..89ae8038 --- /dev/null +++ b/docs/ChangeLog/index.rst @@ -0,0 +1,13 @@ +.. _CHANGE: + +Change Log +########## + + +.. toctree:: + + 2016/index + 2015/index + 2014/index + +.. # 2017/index diff --git a/docs/ChangeLog/template.rst b/docs/ChangeLog/template.rst new file mode 100644 index 00000000..d658b010 --- /dev/null +++ b/docs/ChangeLog/template.rst @@ -0,0 +1,30 @@ +.. # This file is a template for new release notes. It's marked as orphan to suppress warnings. + +:orphan: + +New in 1.x (upcomming) +======================= + +Already documented changes are available on the ``release`` branch at GitHub. + +* Python Infrastructure + * Common changes + * All Simulators + * Aldec Active-HDL + * GHDL + * Mentor QuestaSim + * Xilinx ISE Simulator + * Xilinx Vivado Simulator + * All Compilers + * Altera Quartus Synthesis + * Lattice Diamond (LSE) + * Xilinx ISE (XST) + * Xilinx ISE Core Generator + * Xilinx Vivado Synthesis +* Documentation +* VHDL common packages +* VHDL Simulation helpers +* New Entities +* New Testbenches +* New Constraints +* Shipped Tool and Helper Scripts diff --git a/docs/ConstraintFiles/index.rst b/docs/ConstraintFiles/index.rst index 294ef1e9..9a2e28b1 100644 --- a/docs/ConstraintFiles/index.rst +++ b/docs/ConstraintFiles/index.rst @@ -1,9 +1,10 @@ +.. _CONST: Constraint Files ################ -IP Core Contraint Files -*********************** +IP Core Constraint Files +************************ * fifo * misc @@ -11,12 +12,6 @@ IP Core Contraint Files * net * eth -.. only:: PoCInternal - - * sata - * xilinx - -.. #PoCInternal .. toctree:: :hidden: @@ -25,17 +20,9 @@ IP Core Contraint Files misc/index net/index -.. only:: PoCInternal - - .. toctree:: - :hidden: - - sata/index -.. #PoCInternal - -Board Contraint Files -********************* +Board Constraint Files +********************** * Altera Boards * Cyclone III diff --git a/docs/GetInvolved/Authors.rst b/docs/GetInvolved/Authors.rst index 672eda18..611c545e 100644 --- a/docs/GetInvolved/Authors.rst +++ b/docs/GetInvolved/Authors.rst @@ -1,4 +1,4 @@ -.. This file is included. So it needs to marked as orphan to suppress warnings. +.. # This file is included. So it needs to be marked as orphan to suppress warnings. :orphan: diff --git a/docs/IPCores/arith/arith.pkg.rst b/docs/IPCores/arith/arith.pkg.rst index 80cc19ba..adaa993f 100644 --- a/docs/IPCores/arith/arith.pkg.rst +++ b/docs/IPCores/arith/arith.pkg.rst @@ -1,3 +1,12 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith.pkg.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + .. _PKG:arith: PoC.arith Package diff --git a/docs/IPCores/bus/stream/index.rst b/docs/IPCores/bus/stream/index.rst index 3199bcf7..a39eaf75 100644 --- a/docs/IPCores/bus/stream/index.rst +++ b/docs/IPCores/bus/stream/index.rst @@ -6,6 +6,12 @@ PoC.bus.stream PoC.Stream modules ... .. toctree:: + :hidden: + + Package + +.. toctree:: + :hidden: stream_Buffer stream_DeMux diff --git a/docs/IPCores/bus/stream/stream.pkg.rst b/docs/IPCores/bus/stream/stream.pkg.rst new file mode 100644 index 00000000..c4fca429 --- /dev/null +++ b/docs/IPCores/bus/stream/stream.pkg.rst @@ -0,0 +1,16 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream.pkg.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:stream: + +PoC.bus.stream Package +====================== + +Source file: :pocsrc:`stream.pkg.vhdl ` + diff --git a/docs/IPCores/bus/wb/index.rst b/docs/IPCores/bus/wb/index.rst index 9a68f5d4..d3cf6e0d 100644 --- a/docs/IPCores/bus/wb/index.rst +++ b/docs/IPCores/bus/wb/index.rst @@ -7,6 +7,11 @@ WishBone modules ... **Entities:** +.. toctree:: + :hidden: + + Package + .. toctree:: :hidden: diff --git a/docs/IPCores/bus/wb/wb.pkg.rst b/docs/IPCores/bus/wb/wb.pkg.rst new file mode 100644 index 00000000..8a3a6106 --- /dev/null +++ b/docs/IPCores/bus/wb/wb.pkg.rst @@ -0,0 +1,16 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/wb/wb.pkg.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:wb: + +PoC.bus.wb Package +====================== + +Source file: :pocsrc:`wb.pkg.vhdl ` + diff --git a/docs/IPCores/comm/comm.pkg.rst b/docs/IPCores/comm/comm.pkg.rst new file mode 100644 index 00000000..199f5cd7 --- /dev/null +++ b/docs/IPCores/comm/comm.pkg.rst @@ -0,0 +1,15 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/comm/comm.pkg.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:comm: + +PoC.comm Package +================ + +Source file: :pocsrc:`comm.pkg.vhdl ` diff --git a/docs/IPCores/comm/index.rst b/docs/IPCores/comm/index.rst index c6200649..12fb724f 100644 --- a/docs/IPCores/comm/index.rst +++ b/docs/IPCores/comm/index.rst @@ -6,6 +6,12 @@ PoC.comm These are communication entities.... .. toctree:: + :hidden: + + Package + +.. toctree:: + :hidden: comm_crc comm_scramble diff --git a/docs/IPCores/fifo/fifo.pkg.rst b/docs/IPCores/fifo/fifo.pkg.rst index ca9cb13b..0ce9d086 100644 --- a/docs/IPCores/fifo/fifo.pkg.rst +++ b/docs/IPCores/fifo/fifo.pkg.rst @@ -1,5 +1,3 @@ -.. _PKG:fifo: - .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png :scale: 40 :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo.pkg.vhdl @@ -9,6 +7,7 @@ |gh-src| :pocsrc:`Sourcecode ` +.. _PKG:fifo: PoC.fifo Package ================ diff --git a/docs/IPCores/io/ddrio/ddrio.pkg.rst b/docs/IPCores/io/ddrio/ddrio.pkg.rst new file mode 100644 index 00000000..f3c899cd --- /dev/null +++ b/docs/IPCores/io/ddrio/ddrio.pkg.rst @@ -0,0 +1,16 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/ddrio/ddrio.pkg.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:ddrio: + +PoC.io.ddrio Package +==================== + +Source file: :pocsrc:`ddrio.pkg.vhdl ` + diff --git a/docs/IPCores/io/ddrio/ddrio_in.rst b/docs/IPCores/io/ddrio/ddrio_in.rst index 7452bb86..266d5468 100644 --- a/docs/IPCores/io/ddrio/ddrio_in.rst +++ b/docs/IPCores/io/ddrio/ddrio_in.rst @@ -25,6 +25,20 @@ sampled with the same rising edge. ``DataIn_low`` is the value sampled with the falling edge directly before this rising edge. Thus sampling starts with the falling edge of the clock as depicted in the following waveform. +.. wavedrom:: + + { signal: [ + {name: 'clk', wave: 'H.L.H.L.H.L.H.L.H'}, + {name: 'pad', wave: 'x2.3.4.5.2.3.x...', data: ['0', '1', '2', '3', '4', '5'], node: '..a.b.c.d.e.f..'}, + ['DataIn', + {name: 'DataIn_low', wave: 'x...2...4...2...x', data: ['0', '2', '4'], node: '.....k...m...o.'}, + {name: 'DataIn_high', wave: 'x...3...5...3...x', data: ['1', '3', '5'], node: '.....l...n...p.'}, + ], + ], + edge: ['a~k', 'b~l', 'c~m', 'd~n', 'e~o', 'f~p'], + foot: {text: 'PoC.io.ddrio.in'} + } + .. code-block:: none __ ____ ____ __ @@ -49,7 +63,7 @@ IOBs. :language: vhdl :tab-width: 2 :linenos: - :lines: 64-76 + :lines: 78-90 Source file: :pocsrc:`io/ddrio/ddrio_in.vhdl ` diff --git a/docs/IPCores/io/ddrio/index.rst b/docs/IPCores/io/ddrio/index.rst index d5ae070e..0960d607 100644 --- a/docs/IPCores/io/ddrio/index.rst +++ b/docs/IPCores/io/ddrio/index.rst @@ -12,6 +12,11 @@ These are :abbr:`DDR-I/O (Double Data Rate - Input/Output)` entities.... * :ref:`IP:ddrio_out` +.. toctree:: + :hidden: + + Package + .. toctree:: :hidden: diff --git a/docs/IPCores/io/iic/iic.pkg.rst b/docs/IPCores/io/iic/iic.pkg.rst new file mode 100644 index 00000000..787e0094 --- /dev/null +++ b/docs/IPCores/io/iic/iic.pkg.rst @@ -0,0 +1,16 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/iic/iic.pkg.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:iic: + +PoC.io.iic Package +================== + +Source file: :pocsrc:`iic.pkg.vhdl ` + diff --git a/docs/IPCores/io/iic/index.rst b/docs/IPCores/io/iic/index.rst index 7baaa34d..d0c7e20b 100644 --- a/docs/IPCores/io/iic/index.rst +++ b/docs/IPCores/io/iic/index.rst @@ -5,6 +5,11 @@ PoC.io.iic These are I2C entities.... +.. toctree:: + :hidden: + + Package + .. toctree:: :hidden: diff --git a/docs/IPCores/io/io.pkg.rst b/docs/IPCores/io/io.pkg.rst index 80609a05..fb421f25 100644 --- a/docs/IPCores/io/io.pkg.rst +++ b/docs/IPCores/io/io.pkg.rst @@ -1,3 +1,12 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io.pkg.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + .. _PKG:io: PoC.io Package diff --git a/docs/IPCores/io/lcd/index.rst b/docs/IPCores/io/lcd/index.rst index f3ca6363..6c4ac133 100644 --- a/docs/IPCores/io/lcd/index.rst +++ b/docs/IPCores/io/lcd/index.rst @@ -5,6 +5,11 @@ PoC.io.lcd These are LCD entities.... +.. toctree:: + :hidden: + + Package + .. toctree:: :hidden: diff --git a/docs/IPCores/io/lcd/lcd.pkg.rst b/docs/IPCores/io/lcd/lcd.pkg.rst new file mode 100644 index 00000000..63792d60 --- /dev/null +++ b/docs/IPCores/io/lcd/lcd.pkg.rst @@ -0,0 +1,16 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd.pkg.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:lcd: + +PoC.io.lcd Package +================== + +Source file: :pocsrc:`lcd.pkg.vhdl ` + diff --git a/docs/IPCores/io/pmod/index.rst b/docs/IPCores/io/pmod/index.rst index 16135599..16a0ce73 100644 --- a/docs/IPCores/io/pmod/index.rst +++ b/docs/IPCores/io/pmod/index.rst @@ -12,6 +12,11 @@ These are Pmod entities.... * :ref:`IP:pmod_USBUART` +.. toctree:: + :hidden: + + Package + .. toctree:: :hidden: diff --git a/docs/IPCores/io/pmod/pmod.pkg.rst b/docs/IPCores/io/pmod/pmod.pkg.rst new file mode 100644 index 00000000..0a42ad0a --- /dev/null +++ b/docs/IPCores/io/pmod/pmod.pkg.rst @@ -0,0 +1,16 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pmod/pmod.pkg.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:pmod: + +PoC.io.pmod Package +=================== + +Source file: :pocsrc:`pmod.pkg.vhdl ` + diff --git a/docs/IPCores/io/uart/index.rst b/docs/IPCores/io/uart/index.rst index bb7b3c91..45ed08f6 100644 --- a/docs/IPCores/io/uart/index.rst +++ b/docs/IPCores/io/uart/index.rst @@ -13,6 +13,11 @@ These are :abbr:`UART (Universal Asynchronous Receiver Transmitter)` entities... * :ref:`IP:uart_fifo` +.. toctree:: + :hidden: + + Package + .. toctree:: :hidden: diff --git a/docs/IPCores/io/uart/uart.pkg.rst b/docs/IPCores/io/uart/uart.pkg.rst new file mode 100644 index 00000000..9fecad90 --- /dev/null +++ b/docs/IPCores/io/uart/uart.pkg.rst @@ -0,0 +1,16 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart.pkg.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:uart: + +PoC.io.uart Package +=================== + +Source file: :pocsrc:`uart.pkg.vhdl ` + diff --git a/docs/IPCores/io/vga/index.rst b/docs/IPCores/io/vga/index.rst index d5ba2277..49c6c421 100644 --- a/docs/IPCores/io/vga/index.rst +++ b/docs/IPCores/io/vga/index.rst @@ -5,6 +5,11 @@ PoC.io.vga These are VGA entities.... +.. toctree:: + :hidden: + + Package + .. toctree:: :hidden: diff --git a/docs/IPCores/io/vga/vga.pkg.rst b/docs/IPCores/io/vga/vga.pkg.rst new file mode 100644 index 00000000..ae03e623 --- /dev/null +++ b/docs/IPCores/io/vga/vga.pkg.rst @@ -0,0 +1,16 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/vga/vga.pkg.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:vga: + +PoC.io.vga Package +================== + +Source file: :pocsrc:`vga.pkg.vhdl ` + diff --git a/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst b/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst index aff9727b..d9afec35 100644 --- a/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst +++ b/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst @@ -17,7 +17,7 @@ ddr2_mem2mig_adapter_Spartan6 ############################# -Adapter between the :doc:`PoC.Mem ` +Adapter between the :ref:`PoC.Mem ` interface and the User Interface of the Xilinx MIG IP core for the Spartan-6 FPGA Memory Controller Block (MCB). The MCB can be configured to have multiple ports. One instance of this adapter is required for every @@ -28,7 +28,7 @@ Simplifies the User Interface ("user") of the Xilinx MIG IP core (UG388). The PoC.Mem interface provides single-cycle fully pipelined read/write access to the memory. All accesses are word-aligned. Always all bytes of a word are written to the memory. More details can be found -:doc:`here `. +:ref:`here `. Generic parameters: diff --git a/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst b/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst index 8de9d117..4977ca1a 100644 --- a/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst +++ b/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst @@ -17,15 +17,14 @@ ddr3_mem2mig_adapter_Series7 ############################ -Adapter between the :doc:`PoC.Mem ` -interface and the application interface ("app") -of the Xilinx MIG IP core for 7-Series FPGAs. +Adapter between the :ref:`PoC.Mem ` interface and the +application interface ("app") of the Xilinx MIG IP core for 7-Series FPGAs. Simplifies the application interface ("app") of the Xilinx MIG IP core. The PoC.Mem interface provides single-cycle fully pipelined read/write access to the memory. All accesses are word-aligned. Always all bytes of a word are written to the memory. More details can be found -:doc:`here `. +:ref:`here `. Generic parameters: @@ -49,7 +48,7 @@ Containts only combinational logic. :language: vhdl :tab-width: 2 :linenos: - :lines: 61-96 + :lines: 60-95 Source file: :pocsrc:`mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl ` diff --git a/docs/IPCores/mem/index.rst b/docs/IPCores/mem/index.rst index 21fc27c8..05a166f8 100644 --- a/docs/IPCores/mem/index.rst +++ b/docs/IPCores/mem/index.rst @@ -9,8 +9,8 @@ implementations. **Sub-Namespaces** - * :ref:`NS:ddr3` - DDR3 memory controllers * :ref:`NS:ddr2` - DDR2 memory controllers + * :ref:`NS:ddr3` - DDR3 memory controllers * :ref:`NS:lut` - Lookup-Table (LUT) implementations * :ref:`NS:ocram` - On-Chip RAM abstraction layer * :ref:`NS:ocrom` - On-Chip ROM abstraction layer @@ -29,8 +29,8 @@ implementations. .. toctree:: :hidden: - ddr3 ddr2 + ddr3 lut ocram ocrom diff --git a/docs/IPCores/mem/mem.pkg.rst b/docs/IPCores/mem/mem.pkg.rst index 963c1dca..5f0fc3a1 100644 --- a/docs/IPCores/mem/mem.pkg.rst +++ b/docs/IPCores/mem/mem.pkg.rst @@ -1,3 +1,12 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/mem.pkg.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + .. _PKG:mem: PoC.mem Package diff --git a/docs/IPCores/mem/ocram/index.rst b/docs/IPCores/mem/ocram/index.rst index b2c5c31e..dc07fbe9 100644 --- a/docs/IPCores/mem/ocram/index.rst +++ b/docs/IPCores/mem/ocram/index.rst @@ -25,6 +25,12 @@ The package PoC.mem.ocram holds all component declarations for this namespace. * :ref:`IP:ocram_esdp` - An on-chip RAM with an extended simple dual port interface. + +.. toctree:: + :hidden: + + Package + .. toctree:: :hidden: diff --git a/docs/IPCores/mem/ocram/ocram.pkg.rst b/docs/IPCores/mem/ocram/ocram.pkg.rst new file mode 100644 index 00000000..f3a0e805 --- /dev/null +++ b/docs/IPCores/mem/ocram/ocram.pkg.rst @@ -0,0 +1,16 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram.pkg.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:ocram: + +PoC.mem.ocram Package +===================== + +Source file: :pocsrc:`ocram.pkg.vhdl ` + diff --git a/docs/IPCores/mem/ocram/ocram_esdp.rst b/docs/IPCores/mem/ocram/ocram_esdp.rst index 76d40a9d..59a0c643 100644 --- a/docs/IPCores/mem/ocram/ocram_esdp.rst +++ b/docs/IPCores/mem/ocram/ocram_esdp.rst @@ -22,11 +22,11 @@ Inferring / instantiating enhanced simple dual-port memory, with: * dual clock, clock enable, * 1 read/write port (1st port) plus 1 read port (2nd port). -.. NOTE:: - This component is **deprecated**. - Please use :doc:`PoC.mem.ocram.tdp ` for new designs. +.. deprecated:: 1.1 + + :color:`Please use ` :ref:`IP:ocram_tdp` :color:`for new designs. This component has been provided because older FPGA compilers where not - able to infer true dual-port memory from an RTL description. + able to infer true dual-port memory from an RTL description. ` Command truth table for port 1: diff --git a/docs/IPCores/mem/ocrom/index.rst b/docs/IPCores/mem/ocrom/index.rst index 0d80cf8b..f9453dae 100644 --- a/docs/IPCores/mem/ocrom/index.rst +++ b/docs/IPCores/mem/ocrom/index.rst @@ -21,6 +21,11 @@ The package PoC.mem.ocrom holds all component declarations for this namespace. - :ref:`ocrom_dp ` is a on-chip RAM with a dual port interface. +.. toctree:: + :hidden: + + Package + .. toctree:: :hidden: diff --git a/docs/IPCores/mem/ocrom/ocrom.pkg.rst b/docs/IPCores/mem/ocrom/ocrom.pkg.rst new file mode 100644 index 00000000..df23511e --- /dev/null +++ b/docs/IPCores/mem/ocrom/ocrom.pkg.rst @@ -0,0 +1,16 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocrom/ocrom.pkg.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:ocrom: + +PoC.mem.ocrom Package +===================== + +Source file: :pocsrc:`ocrom.pkg.vhdl ` + diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst b/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst index 803211ae..6685e72e 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst @@ -45,7 +45,7 @@ Command, address and write data is sampled with ``clk``. Read data is also aligned with ``clk``. For description on ``clkout`` see -:doc:`sdram_ctrl_phy_de0 `. +:ref:`sdram_ctrl_phy_de0 `. Synchronous resets are used. @@ -57,7 +57,7 @@ Synchronous resets are used. :language: vhdl :tab-width: 2 :linenos: - :lines: 88-120 + :lines: 68-100 Source file: :pocsrc:`mem/sdram/sdram_ctrl_de0.vhdl ` diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst b/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst index d838ac5f..5f3764af 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst @@ -93,7 +93,7 @@ The write data must directly connected to the physical layer. :language: vhdl :tab-width: 2 :linenos: - :lines: 124-168 + :lines: 104-148 Source file: :pocsrc:`mem/sdram/sdram_ctrl_fsm.vhdl ` diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst b/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst index bffa9e26..5f1c946c 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst @@ -17,7 +17,7 @@ sdram_ctrl_phy_de0 ################## -Physical layer used by module :doc:`sdram_ctrl_de0 `. +Physical layer used by module :ref:`sdram_ctrl_de0 `. Instantiates input and output buffer components and adjusts the timing for the Altera DE0 board. diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst b/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst index f11e6440..9ac446a9 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst @@ -17,7 +17,7 @@ sdram_ctrl_phy_s3esk #################### -Physical layer used by module :doc:`sdram_ctrl_s3esk `. +Physical layer used by module :ref:`sdram_ctrl_s3esk `. Instantiates input and output buffer components and adjusts the timing for the Spartan-3E Starter Kit Board. @@ -97,7 +97,7 @@ Synchronous resets are used. Reset must be hold for at least two cycles. :language: vhdl :tab-width: 2 :linenos: - :lines: 127-171 + :lines: 107-151 Source file: :pocsrc:`mem/sdram/sdram_ctrl_phy_s3esk.vhdl ` diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst b/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst index d5d6bd54..19499987 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst @@ -58,7 +58,7 @@ Synchronous resets are used. :language: vhdl :tab-width: 2 :linenos: - :lines: 89-132 + :lines: 69-112 Source file: :pocsrc:`mem/sdram/sdram_ctrl_s3esk.vhdl ` diff --git a/docs/IPCores/misc/misc.pkg.rst b/docs/IPCores/misc/misc.pkg.rst index 1b5f56f3..63f01d03 100644 --- a/docs/IPCores/misc/misc.pkg.rst +++ b/docs/IPCores/misc/misc.pkg.rst @@ -1,3 +1,12 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc.pkg.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + .. _PKG:misc: PoC.misc Package diff --git a/docs/IPCores/misc/sync/index.rst b/docs/IPCores/misc/sync/index.rst index 026c89cd..06b7e8ff 100644 --- a/docs/IPCores/misc/sync/index.rst +++ b/docs/IPCores/misc/sync/index.rst @@ -69,6 +69,11 @@ Based on the 2-FF synchronizer, several "high-level" synchronizers are build. .. [#f5] See the ``PoC.fifo`` namespace for cross-clock capable FIFOs. +.. toctree:: + :hidden: + + Package + .. toctree:: :hidden: diff --git a/docs/IPCores/misc/sync/sync.pkg.rst b/docs/IPCores/misc/sync/sync.pkg.rst new file mode 100644 index 00000000..5a3e19b8 --- /dev/null +++ b/docs/IPCores/misc/sync/sync.pkg.rst @@ -0,0 +1,16 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync.pkg.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:sync: + +PoC.misc.sync Package +===================== + +Source file: :pocsrc:`sync.pkg.vhdl ` + diff --git a/docs/IPCores/net/net.pkg.rst b/docs/IPCores/net/net.pkg.rst new file mode 100644 index 00000000..5a64d231 --- /dev/null +++ b/docs/IPCores/net/net.pkg.rst @@ -0,0 +1,15 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/net.pkg.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:net: + +PoC.net Package +=============== + +Source file: :pocsrc:`net.pkg.vhdl ` diff --git a/docs/IPCores/sort/sortnet/index.rst b/docs/IPCores/sort/sortnet/index.rst index 444581a0..5b25deb3 100644 --- a/docs/IPCores/sort/sortnet/index.rst +++ b/docs/IPCores/sort/sortnet/index.rst @@ -16,6 +16,11 @@ This sub-namespace contains sorting network implementations. * :ref:`IP:sortnet_Transform` +.. toctree:: + :hidden: + + Package + .. toctree:: :hidden: diff --git a/docs/IPCores/sort/sortnet/sortnet.pkg.rst b/docs/IPCores/sort/sortnet/sortnet.pkg.rst new file mode 100644 index 00000000..a63cffc1 --- /dev/null +++ b/docs/IPCores/sort/sortnet/sortnet.pkg.rst @@ -0,0 +1,36 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet.pkg.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:sortnet: + +PoC.sort.sortnet Package +======================== + +.. code-block:: VHDL + + type T_SORTNET_IMPL is ( + SORT_SORTNET_IMPL_ODDEVEN_SORT, + SORT_SORTNET_IMPL_ODDEVEN_MERGESORT, + SORT_SORTNET_IMPL_BITONIC_SORT + ); + +.. c:type:: T_SORTNET_IMPL + + SORT_SORTNET_IMPL_ODDEVEN_SORT + Instantiate a :ref:`IP:sortnet_OddEvenSort` sorting network. + + SORT_SORTNET_IMPL_ODDEVEN_MERGESORT + Instantiate a :ref:`IP:sortnet_OddEvenMergeSort` sorting network. + + SORT_SORTNET_IMPL_BITONIC_SORT + Instantiate a :ref:`IP:sortnet_BitonicSort` sorting network. + + +Source file: :pocsrc:`sortnet.pkg.vhdl ` + diff --git a/docs/IPCores/xil/xil.pkg.rst b/docs/IPCores/xil/xil.pkg.rst new file mode 100644 index 00000000..356a78ee --- /dev/null +++ b/docs/IPCores/xil/xil.pkg.rst @@ -0,0 +1,17 @@ +.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil.pkg.vhdl + :alt: Source Code on GitHub + +.. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:xil: + +PoC.xil Package +================ + +This package holds all component declarations for this namespace. + +Source file: :pocsrc:`xil.pkg.vhdl ` diff --git a/docs/Interfaces/CommandStatusError.rst b/docs/Interfaces/CommandStatusError.rst index 0e5582f9..c34b596d 100644 --- a/docs/Interfaces/CommandStatusError.rst +++ b/docs/Interfaces/CommandStatusError.rst @@ -1,4 +1,4 @@ -.. _Int:PoC.CSE: +.. _INT:PoC.CSE: Command-Status-Error (PoC.CSE) Interface ######################################## diff --git a/docs/Interfaces/FIFO.rst b/docs/Interfaces/FIFO.rst index 9ab680c5..7475a127 100644 --- a/docs/Interfaces/FIFO.rst +++ b/docs/Interfaces/FIFO.rst @@ -1,4 +1,4 @@ -.. _Int:PoC.FIFO: +.. _INT:PoC.FIFO: PoC.FIFO Interface ################## diff --git a/docs/Interfaces/Memory.rst b/docs/Interfaces/Memory.rst index 752b3b67..2d2d9ede 100644 --- a/docs/Interfaces/Memory.rst +++ b/docs/Interfaces/Memory.rst @@ -1,4 +1,4 @@ -.. _Int:PoC.Mem: +.. _INT:PoC.Mem: PoC.Mem Interface ################# diff --git a/docs/Interfaces/Stream.rst b/docs/Interfaces/Stream.rst index 3fd04d7b..d6df1e10 100644 --- a/docs/Interfaces/Stream.rst +++ b/docs/Interfaces/Stream.rst @@ -1,4 +1,4 @@ -.. _Int:PoC.Stream: +.. _INT:PoC.Stream: PoC.Stream Interface #################### diff --git a/docs/Interfaces/index.rst b/docs/Interfaces/index.rst index 1ab58f20..240ebca0 100644 --- a/docs/Interfaces/index.rst +++ b/docs/Interfaces/index.rst @@ -1,8 +1,10 @@ -.. _Int: +.. _INT: IP Core Interfaces ################## +PoC defines a set of on-chip interfaces described in the next sections. + .. toctree:: :maxdepth: 1 @@ -10,4 +12,3 @@ IP Core Interfaces PoC.FIFO PoC.Mem PoC.Stream - diff --git a/docs/Miscelaneous/ChangeLog.rst b/docs/Miscelaneous/ChangeLog.rst deleted file mode 100644 index f07b88bd..00000000 --- a/docs/Miscelaneous/ChangeLog.rst +++ /dev/null @@ -1,514 +0,0 @@ -Change Log -########## - -.. contents:: Content of this page - :local: - -**************************************************************************************************************************************************************** -2016 -**************************************************************************************************************************************************************** - -.. This is a comment block. Copy this block for a new release version. - - New in 1.x (upcomming) - ======================= - - Already documented changes are available on the ``release`` branch at GitHub. - - * Python Infrastructure - * Common changes - * All Simulators - * Aldec Active-HDL - * GHDL - * Mentor QuestaSim - * Xilinx ISE Simulator - * Xilinx Vivado Simulator - * All Compilers - * Altera Quartus Synthesis - * Lattice Diamond (LSE) - * Xilinx ISE (XST) - * Xilinx ISE Core Generator - * Xilinx Vivado Synthesis - * Documentation - * VHDL common packages - * VHDL Simulation helpers - * New Entities - * New Testbenches - * New Constraints - * Shipped Tool and Helper Scripts - - -New in 1.x (upcomming) -======================= - -Already documented changes are available on the ``release`` branch at GitHub. - -* Python Infrastructure - - * Common changes - - * The classes ``Simulator`` and ``Compiler`` now share common methods in base class called ``Shared``. - - * ``*.files`` Parser - - * Implemented path expressions: sub-directory expression, concatenate expression - * Implemented InterpolateLiteral: access database keys in ``*.files`` files - * New Path statement, which defines a path constant calculated from a path expression - * Replaced string arguments in statements with path expressions if the desired string was a path - * Replaced simple StringToken matches with Identifier expressions - - * All Simulators - - * - - * All Compilers - - * - - * GHDL - - * Reduced ``-P`` parameters: Removed doublings - -* Documentation - - * - -* VHDL common packages - - * - -* VHDL Simulation helpers - - * Mark a testbench as failed if (registered) processes are active while finilize is called - -* New Entities - - * - -* New Testbenches - - * - -* New Constraints - - * - -* Shipped Tool and Helper Scripts - - * Updated and new Notepad++ syntax files - - -New in 1.0 (13.05.2016) -================================================================================================================================================================ - -* Python Infrastructure (Completely Reworked) - - * New Requirements - - * Python 3.5 - * py-flags - - * New command line interface - - * Synopsis: ``poc.sh|ps1 [common options] [options]`` - * Removed task specific wrapper scripts: ``testbench.sh|ps1``, ``netlist.sh|ps1``, ... - * Updated ``wrapper.ps1`` and ``wrapper.sh`` files - - * New ini-file database - - * - * Added a new config.boards.ini file to list known boards (real and virtual ones) - - * New parser for ``*.files`` files - - * conditional compiling (if-then-elseif-else) - * include statement - include other ``*.files`` files - * library statement - reference external VHDL libraries - * prepared for Cocotb testbenches - - * New parser for ``*.rules`` files - - * - - * All Tool Flows - - * Unbuffered outputs from vendor tools (realtime output to stdout from subprocess) - * Output filtering from vendor tools - - * verbose message suppression - * error and warning message highlighting - * abort flow on vendor tool errors - - * All Simulators - - * Run testbenches for different board or device configurations (see ``--board`` and ``--device`` command line options) - - * New Simulators - - * Aldec Active-HDL support (no GUI support) - - * Tested with Active-HDL from Lattice Diamond - * Tested with Active-HDL Student Edition - - * Cocotb (with QuestaSim backend on Linux) - - * New Synthesizers - - * Altera Quartus II and Quartus Prime - - * Command: ``quartus`` - - * Lattice Synthesis Engine (LSE) from Diamond - - * Command: ``lse`` - - * Xilinx Vivado - - * Command: ``vivado`` - - * GHDL - - * GHDLSimulator can distinguish different backends (mcode, gcc, llvm) - * Pre-compiled library support for GHDL - - * QuestaSim / ModelSim Altera Edition - - * Pre-compiled library support for GHDL - - * Vivado Simulator - - * Tested Vivado Simulator 2016.1 (xSim) with PoC -> still produces errors or false results - -* New Entities - - * - -* New Testbenches - - * - -* New Constraints - - * - -* New dependencies - - * Embedded Cocotb in ``/lib/cocotb`` - -* Shipped Tool and Helper Scripts - - * Updated and new Notepad++ syntax files - * Pre-compiled vendor library support - - * Added a new ``/temp/precompiled`` folder for precompiled vendor libraries - * QuestaSim supports Altera QuartusII, Xilinx ISE and Xilinx Vivado libraries - * GHDL supports Altera QuartusII, Xilinx ISE and Xilinx Vivado libraries - - -New in 0.21 (17.02.2016) -================================================================================================================================================================ - - -New in 0.20 (16.01.2016) -================================================================================================================================================================ - - -New in 0.19 (16.01.2016) -================================================================================================================================================================ - -**************************************************************************************************************************************************************** -2015 -**************************************************************************************************************************************************************** - -New in 0.18 (16.12.2015) -================================================================================================================================================================ - - -New in 0.17 (08.12.2015) -================================================================================================================================================================ - - -New in 0.16 (01.12.2015) -================================================================================================================================================================ - - -New in 0.15 (13.11.2015) -================================================================================================================================================================ - - -New in 0.14 (28.09.2015) -================================================================================================================================================================ - - -New in 0.13 (04.09.2015) -================================================================================================================================================================ - - -New in 0.12 (25.08.2015) -================================================================================================================================================================ - - -New in 0.11 (07.08.2015) -================================================================================================================================================================ - - -New in 0.10 (23.07.2015) -================================================================================================================================================================ - - -New in 0.9 (21.07.2015) -================================================================================================================================================================ - - -New in 0.8 (03.07.2015) -================================================================================================================================================================ - - -New in 0.7 (27.06.2015) -================================================================================================================================================================ - - -New in 0.6 (09.06.2015) -================================================================================================================================================================ - - -New in 0.5 (27.05.2015) -================================================================================================================================================================ - -* Updated Python infrastructure -* New testbenches: - - * sync_Reset_tb - * sync_Flag_tb - * sync_Strobe_tb - * sync_Vector_tb - * sync_Command_tb - -* Updated modules: - - * sync_Vector - * sync_Command - -* Updated packages: - - * physical - * utils - * vectors - * xil - -New in 0.4 (29.04.2015) -================================================================================================================================================================ - -* New Python infrastructure - - * Added simulators for: - - * GHDL + GTKWave - * Mentor Graphic QuestaSim - * Xilinx ISE Simulator - * Xilinx Vivado Simulator - -* New packages: - - * simulation - -* New modules: - - * PoC.comm - communication modules - - * comm_crc - - * PoC.comm.remote - remote communication modules - - * remote_terminal_control - -* New testbenches: - - * arith_addw_tb - * arith_counter_bcd_tb - * arith_prefix_and_tb - * arith_prefix_or_tb - * arith_prng_tb - -* Updated packages: - - * board - * config - * physical - * strings - * utils - -* Updated modules: - - * io_Debounce - * misc_FrequencyMeasurement - * sync_Bits - * sync_Reset - -New in 0.3 (31.03.20015) -================================================================================================================================================================ - -* Added Python infrastructure - - * Added platform wrapper scripts (\*.sh, \*.ps1) - * Added IP-core compiler scripts Netlist.py - -* Added Tools - - * Notepad++ syntax file for Xilinx UCF/XCF files - * Git configuration script to register global aliases - -* New packages: - - * components - hardware described as functions - * physical - physical types like frequency, memory and baudrate - * io - -* New modules: - - * PoC.misc - - * misc_FrequencyMeasurement - - * PoC.io - Low-speed I/O interfaces - - * io_7SegmentMux_BCD - * io_7SegmentMux_HEX - * io_FanControl - * io_PulseWidthModulation - * io_TimingCounter - * io_Debounce - * io_GlitchFilter - -* New IP-cores: - - * PoC.xil - Xilinx specific modules - - * xil_ChipScopeICON_1 - * xil_ChipScopeICON_2 - * xil_ChipScopeICON_3 - * xil_ChipScopeICON_4 - * xil_ChipScopeICON_6 - * xil_ChipScopeICON_7 - * xil_ChipScopeICON_8 - * xil_ChipScopeICON_9 - * xil_ChipScopeICON_10 - * xil_ChipScopeICON_11 - * xil_ChipScopeICON_12 - * xil_ChipScopeICON_13 - * xil_ChipScopeICON_14 - * xil_ChipScopeICON_15 - -* New constraint files: - - * ML605 - * KC705 - * VC707 - * MetaStability - * xil_Sync - -* Updated packages: - - * board - * config - -* Updated modules: - - * xil_BSCAN - -New in 0.2 (09.03.2015) -================================================================================================================================================================ - -* New packages: - - * xil - * stream - -* New modules: - - * PoC.bus - Modules for busses - - * bus_Arbiter - - * PoC.bus.stream - Modules for the PoC.Stream protocol - - * stream_Buffer - * stream_DeMux - * stream_FrameGenerator - * stream_Mirror - * stream_Mux - * stream_Source - - * PoC.misc.sync - Cross-Clock Synchronizers - - * sync_Reset - * sync_Flag - * sync_Strobe - * sync_Vector - * sync_Command - - * PoC.xil - Xilinx specific modules - - * xil_SyncBits - * xil_SyncReset - * xil_BSCAN - * xil_Reconfigurator - * xil_SystemMonitor_Virtex6 - * xil_SystemMonitor_Series7 - -* Updated packages: - - * utils - * arith - -New in 0.1 (19.02.2015) -================================================================================================================================================================ - -* New packages: - - * board - common development board configurations - * config - extract configuration parameters from device names - * utils - common utility functions - * strings - a helper package for string handling - * vectors - a helper package for std_logic_vector and std_logic_matrix - * arith - * fifo - -* New modules - - * PoC.arith - arithmetic modules - - * arith_counter_gray - * arith_counter_ring - * arith_div - * arith_prefix_and - * arith_prefix_or - * arith_prng - * arith_scaler - * arith_sqrt - - * PoC.fifo - FIFOs - - * fifo_cc_got - * fifo_cc_got_tempgot - * fifo_cc_got_tempput - * fifo_ic_got - * fifo_glue - * fifo_shift - - * PoC.mem.ocram - On-Chip RAMs - - * ocram_sp - * ocram_sdp - * ocram_esdp - * ocram_tdp - * ocram_wb - -**************************************************************************************************************************************************************** -2014 -**************************************************************************************************************************************************************** - -New in 0.0 (16.12.2014) -================================================================================================================================================================ - -* Initial commit diff --git a/docs/Miscelaneous/ThirdParty.rst b/docs/Miscelaneous/ThirdParty.rst index d772867f..787a2363 100644 --- a/docs/Miscelaneous/ThirdParty.rst +++ b/docs/Miscelaneous/ThirdParty.rst @@ -1,3 +1,8 @@ +.. index:: + single: Third-Party Libraries + +.. _THIRD: + Third Party Libraries ##################### @@ -5,7 +10,13 @@ The PoC-Library is shiped with different third party libraries, which are located in the ``/lib/`` folder. This document lists all these libraries, their websites and licenses. -.. _ThirdParty:Cocotb: + +.. # =========================================================================================================================================================== + +.. index:: + pair: Third-Party Libraries; Cocotb + +.. _THIRD:Cocotb: Cocotb ****** @@ -25,7 +36,13 @@ library for writing VHDL and Verilog testbenches in Python. | **Source:** | `https://github.com/potentialventures/cocotb `_ | +--------------------+-----------------------------------------------------------------------------------------------------------+ -.. _ThirdParty:OSVVM: + +.. # =========================================================================================================================================================== + +.. index:: + pair: Third-Party Libraries; OSVVM + +.. _THIRD:OSVVM: OSVVM ***** @@ -50,7 +67,13 @@ existing testbench or testbench models. | **Source:** | `https://github.com/JimLewis/OSVVM `_ | +----------------+---------------------------------------------------------------------------------------+ -.. _ThirdParty:UVVM: + +.. # =========================================================================================================================================================== + +.. index:: + pair: Third-Party Libraries; UVVM + +.. _THIRD:UVVM: UVVM **** @@ -83,7 +106,13 @@ the ``uart_receive()`` or ``axilite_write()`` BFM respectively. | **Source:** | `https://github.com/UVVM/UVVM_All `_ | +----------------+---------------------------------------------------------------------------------------+ -.. _ThirdParty:VUnit: + +.. # =========================================================================================================================================================== + +.. index:: + pair: Third-Party Libraries; VUnit + +.. _THIRD:VUnit: VUnit ***** diff --git a/docs/QuickStart.rst b/docs/QuickStart.rst index 58efbe27..1ea4990e 100644 --- a/docs/QuickStart.rst +++ b/docs/QuickStart.rst @@ -1,15 +1,55 @@ +.. _QUICK: + +.. raw:: html + + + +.. |kbd-Y| raw:: html + + Y + +.. |kbd-N| raw:: html + + N + +.. |kbd-P| raw:: html + + P + +.. |kbd-Return| raw:: html + + Return Quick Start Guide ################# -This **quick start guide** gives a fast and simple introduction into PoC. All -topics can be found in the :doc:`Using PoC ` section with much -more details and examples. +This **Quick Start Guide** gives a fast and simple introduction into PoC. All +topics can be found in the :ref:`Using PoC ` section with much more +details and examples. .. contents:: Contents of this Page :local: +.. _QUICK:Requirements: + Requirements and Dependencies ***************************** @@ -17,13 +57,13 @@ The PoC-Library comes with some scripts to ease most of the common tasks, like running testbenches or generating IP cores. PoC uses Python 3 as a platform independent scripting environment. All Python scripts are wrapped in Bash or PowerShell scripts, to hide some platform specifics of Darwin, Linux or Windows. -See :doc:`/UsingPoC/Requirements` for further details. +See :ref:`USING:Require` for further details. .. rubric:: PoC requires: -* A :doc:`supported synthesis tool chain `, if you want to synthezise IP cores. -* A :doc:`supported simulator too chain `, if you want to simulate IP cores. +* A :ref:`supported synthesis tool chain `, if you want to synthezise IP cores. +* A :ref:`supported simulator too chain `, if you want to simulate IP cores. * The **Python 3** programming language and runtime, if you want to use PoC's infrastructure. * A shell to execute shell scripts: @@ -33,50 +73,53 @@ See :doc:`/UsingPoC/Requirements` for further details. .. rubric:: PoC optionally requires: -* **Git command line** tools or +* **Git** command line tools or * **Git User Interface**, if you want to check out the latest 'master' or 'release' branch. .. rubric:: PoC depends on third part libraries: -* :ref:`ThirdParty:Cocotb` |gh-cocotb| |br| - A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python. -* :ref:`ThirdParty:OSVVM` |gh-osvvm| |br| - Open Source VHDL Verification Methodology. -* :ref:`ThirdParty:UVVM` |gh-uvvm| |br| - Universal VHDL Verification Methodology. -* :ref:`ThirdParty:VUnit` |gh-vunit| |br| - An unit testing framework for VHDL. - .. |gh-cocotb| image:: _static/logos/GitHub-Mark-32px.png - :scale: 50 + :scale: 40 :target: https://github.com/potentialventures/cocotb :alt: Source Code on GitHub .. |gh-osvvm| image:: _static/logos/GitHub-Mark-32px.png - :scale: 50 + :scale: 40 :target: https://github.com/JimLewis/OSVVM :alt: Source Code on GitHub .. |gh-uvvm| image:: _static/logos/GitHub-Mark-32px.png - :scale: 50 + :scale: 40 :target: https://github.com/UVVM/UVVM_All :alt: Source Code on GitHub .. |gh-vunit| image:: _static/logos/GitHub-Mark-32px.png - :scale: 50 + :scale: 40 :target: https://github.com/VUnit/vunit :alt: Source Code on GitHub +* :ref:`THIRD:Cocotb` |gh-cocotb| |br| + A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python. +* :ref:`THIRD:OSVVM` |gh-osvvm| |br| + Open Source VHDL Verification Methodology. +* :ref:`THIRD:UVVM` |gh-uvvm| |br| + Universal VHDL Verification Methodology. +* :ref:`THIRD:VUnit` |gh-vunit| |br| + An unit testing framework for VHDL. + All dependencies are available as GitHub repositories and are linked to PoC as Git submodules into the `PoCRoot\\lib `_ -directory. See :doc:`Third Party Libraries ` for more details on these libraries. +directory. See :ref:`Third Party Libraries ` for more details on these +libraries. +.. _QUICK:Download: + Download ******** The PoC-Library can be downloaded as a `zip-file `_ (latest 'master' branch), cloned with ``git clone`` or embedded with ``git submodule add`` from GitHub. GitHub offers HTTPS and SSH as transfer -protocols. See the :doc:`Download ` page for further +protocols. See the :ref:`Download ` page for further details. The installation directory is referred to as ``PoCRoot``. +----------+---------------------------------------------------------------------+ @@ -88,6 +131,8 @@ details. The installation directory is referred to as ``PoCRoot``. +----------+---------------------------------------------------------------------+ +.. _QUICK:Configuration: + Configuring PoC on a Local System ********************************* @@ -95,7 +140,7 @@ To explore PoC's full potential, it's required to configure some paths and synthesis or simulation tool chains. The following commands start a guided configuration process. Please follow the instructions on screen. It's possible to relaunch the process at any time, for example to register new tools or to -update tool versions. See :doc:`Configuration ` for +update tool versions. See :ref:`Configuration ` for more details. Run the following command line instructions to configure PoC on your local system: @@ -104,9 +149,13 @@ your local system: cd PoCRoot .\poc.ps1 configure -Use the keyboard buttons: :kbd:`Y` to accept, :kbd:`N` to decline, :kbd:`P` to -skip/pass a step and :kbd:`Return` to accept a default value displayed in brackets. +Use the keyboard buttons: |kbd-Y| to accept, |kbd-N| to decline, |kbd-P| to +skip/pass a step and |kbd-Return| to accept a default value displayed in +brackets. + + +.. _QUICK:Integration: Integration *********** @@ -205,6 +254,8 @@ and if needed patch these IP cores. See :doc:`Synthesis ` for more details. +.. _QUICK:RunSimulation: + Run a Simulation **************** @@ -241,6 +292,8 @@ status (``... ERROR``, ``FAILED``, ``NO ASSERTS`` or ``PASSED``). See :doc:`Simulation ` for more details. +.. _QUICK:RunSynthesis: + Run a Synthesis *************** @@ -268,6 +321,8 @@ synthesized to a netlist. :alt: PowerShell console output after running PoC.arith.prng with XST. +.. _QUICK:Updating: + Updating ******** diff --git a/docs/References/CmdRefs/Compile.rst b/docs/References/CmdRefs/Compile.rst index a94aa06d..e6af334e 100644 --- a/docs/References/CmdRefs/Compile.rst +++ b/docs/References/CmdRefs/Compile.rst @@ -14,7 +14,7 @@ Per simulator, one :file:`/` sub-directory is created. Each simulator directory in turn contains library directories, which may be grouped by the library vendor's name: :file:`[/]/`. -So for example: :ref:`ThirdParty:OSVVM` pre-compiled with GHDL is stored in +So for example: :ref:`THIRD:OSVVM` pre-compiled with GHDL is stored in :file:`/temp/precompiled/ghdl/osvvm/`. Note OSVVM is a single library and thus no vendor directory is used to group the generated files. GHDL will also create VHDL language revision sub-directories like :file:`v93/` or :file:`v08/`. @@ -42,45 +42,45 @@ for all major VHDL revisions (93, 2008). .. toctree:: - Compile-Altera-ps1 Compile-Altera-sh + Compile-Altera-ps1 .. rubric:: Pre-compile Lattice Libraries .. toctree:: - Compile-Lattice-ps1 Compile-Lattice-sh + Compile-Lattice-ps1 .. rubric:: Pre-compile OSVVM Libraries .. toctree:: - Compile-OSVVM-ps1 Compile-OSVVM-sh + Compile-OSVVM-ps1 .. rubric:: Pre-compile UVVM Libraries .. toctree:: - Compile-UVVM-ps1 Compile-UVVM-sh + Compile-UVVM-ps1 .. rubric:: Pre-compile Xilinx ISE Libraries .. toctree:: - Compile-Xilinx-ISE-ps1 Compile-Xilinx-ISE-sh + Compile-Xilinx-ISE-ps1 .. rubric:: Pre-compile Xilinx Vivado Libraries .. toctree:: - Compile-Xilinx-Vivado-ps1 Compile-Xilinx-Vivado-sh + Compile-Xilinx-Vivado-ps1 diff --git a/docs/References/CmdRefs/PoC.rst b/docs/References/CmdRefs/PoC.rst index 1889563f..99c9be03 100644 --- a/docs/References/CmdRefs/PoC.rst +++ b/docs/References/CmdRefs/PoC.rst @@ -1,14 +1,172 @@ .. This files requires a Python module called 'PoCSphinx' to be located in the docs root folder. It expects a variable 'parser' of type ArgumentParser. -.. _CmdRef:PoC: +.. _CMDREF:PoC: -Main Programs -############# +Main Program (:file:`PoC.py`) +############################# -The main program :program:`PoC.py` expects the environment variable :envvar:`PoCRootDirectory` -to be set. +The main program :file:`PoC.py` expects the environment variable +:envvar:`PoCRootDirectory` to be set. .. autoprogram:: PoCSphinx:parser :prog: PoC.py + :label: CMDREF: + + +.. foo :maxdepth: 1 + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :start_command: add-solution + :label: CmdRef:poc-add-solution + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :start_command: asim + :prog: PoC.py + :label: CmdRef:poc-asim + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :start_command: cocotb + :prog: PoC.py foo + :label: CmdRef:poc-cocotb + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: configure + :label: CmdRef:poc-configure + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: coregen + :label: CmdRef:poc-coregen + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: ghdl + :label: CmdRef:poc-ghdl + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: help + :label: CmdRef:poc-help + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: ise + :label: CmdRef:poc-ise + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: isim + :label: CmdRef:poc-isim + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: list-netlist + :label: CmdRef:poc-list-netlist + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: list-project + :label: CmdRef:poc-list-project + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: list-solution + :label: CmdRef:poc-list-solution + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: list-testbench + :label: CmdRef:poc-list-testbench + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: lse + :label: CmdRef:poc-lse + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: quartus + :label: CmdRef:poc-quartus + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: query + :label: CmdRef:poc-query + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: remove-solution + :label: CmdRef:poc-remove-solution + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: vivado + :label: CmdRef:poc-vivado + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: vsim + :label: CmdRef:poc-vsim + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: xci + :label: CmdRef:poc-xci + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: xsim + :label: CmdRef:poc-xsim + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: xst + :label: CmdRef:poc-xst + diff --git a/docs/References/CommandReference.rst b/docs/References/CommandReference.rst index 9ca2eded..c3f7ec09 100644 --- a/docs/References/CommandReference.rst +++ b/docs/References/CommandReference.rst @@ -9,5 +9,5 @@ This is the command line option reference for all provided scripts .. toctree:: CmdRefs/Wrapper - CmdRefs/PoC + Main Program CmdRefs/Compile diff --git a/docs/UsingPoC/AddingIPCores.rst b/docs/UsingPoC/AddingIPCores.rst index ee96bc4c..45a3ae66 100644 --- a/docs/UsingPoC/AddingIPCores.rst +++ b/docs/UsingPoC/AddingIPCores.rst @@ -1,3 +1,4 @@ +.. _USING:AddIP: Adding IP Cores to a Project ############################ diff --git a/docs/UsingPoC/Download.rst b/docs/UsingPoC/Download.rst index 64bbfbd6..4f4d9c31 100644 --- a/docs/UsingPoC/Download.rst +++ b/docs/UsingPoC/Download.rst @@ -1,3 +1,4 @@ +.. _USING:Download: Downloading PoC ############### @@ -5,21 +6,35 @@ Downloading PoC .. contents:: Contents of this Page :local: + +.. _USING:Zip: + Downloading from GitHub *********************** The PoC-Library can be downloaded as a zip-file from GitHub. See the following table, to choose your desired git branch. -+----------+--------------------------------------------------------------------+ -| Branch | download link | -+==========+====================================================================+ -| master | `zip-file `_ | -+----------+--------------------------------------------------------------------+ -| release | `zip-file `_ | -+----------+--------------------------------------------------------------------+ +.. |zip-master| image:: /_static/icons/ZIP.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/archive/master.zip + :alt: Source Code from GitHub - 'master' branch. +.. |zip-release| image:: /_static/icons/ZIP.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/archive/release.zip + :alt: Source Code from GitHub - 'release' branch. + ++----------+------------------------+ +| Branch | Download Link | ++==========+========================+ +| master | zip-file |zip-master| | ++----------+------------------------+ +| release | zip-file |zip-release| | ++----------+------------------------+ +.. _USING:GitClone: + Downloading via ``git clone`` ***************************** @@ -28,7 +43,7 @@ GitHub offers the transfer protocols HTTPS and SSH. You should use SSH if you have a GitHub account and have already uploaded an OpenSSH public key to GitHub, otherwise use HTTPS if you have no account or you want to use login credentials. -The created folder :file:`\PoC` is used as :file:`` in later +The created folder :file:`\\PoC` is used as :file:`` in later instructions or on other pages in this documentation. +----------+----------------------------------------+ @@ -78,7 +93,7 @@ On Windows All Windows command line instructions are intended for :program:`Windows PowerShell`, if not marked otherwise. So executing the following instructions in Windows Command Prompt (:program:`cmd.exe`) won't function or result in errors! See - the :doc:`Requirements section ` on where to + the :ref:`Requirements section ` on where to download or update PowerShell. Command line instructions to clone the PoC-Library onto a Windows machine with @@ -109,6 +124,8 @@ SSH protocol: needed anymore. +.. _USING:GitSubmodule: + Downloading via ``git submodule add`` ************************************* @@ -165,7 +182,7 @@ On Windows All Windows command line instructions are intended for :program:`Windows PowerShell`, if not marked otherwise. So executing the following instructions in Windows Command Prompt (:program:`cmd.exe`) won't function or result in errors! See - the :doc:`Requirements section ` on where to + the :ref:`Requirements section ` on where to download or update PowerShell. Command line instructions to clone the PoC-Library onto a Windows machine with diff --git a/docs/UsingPoC/Integration.rst b/docs/UsingPoC/Integration.rst index ab106804..b5f9089e 100644 --- a/docs/UsingPoC/Integration.rst +++ b/docs/UsingPoC/Integration.rst @@ -1,3 +1,4 @@ +.. _USING:Integration: Integrating PoC into Projects ############################# @@ -7,6 +8,8 @@ Integrating PoC into Projects :depth: 2 +.. _USING:Integration:GitSubmodule: + As a Git submodule ****************** @@ -176,4 +179,3 @@ On Windows } ``` - diff --git a/docs/UsingPoC/PoCConfiguration.rst b/docs/UsingPoC/PoCConfiguration.rst index 66e08875..7c09d8cf 100644 --- a/docs/UsingPoC/PoCConfiguration.rst +++ b/docs/UsingPoC/PoCConfiguration.rst @@ -1,3 +1,41 @@ +.. _USING:PoCConfig: + +.. raw:: html + + + +.. |kbd-Y| raw:: html + + Y + +.. |kbd-N| raw:: html + + N + +.. |kbd-P| raw:: html + + P + +.. |kbd-Return| raw:: html + + Return Configuring PoC's Infrastructure ################################ @@ -11,13 +49,15 @@ at any time, for example to register new tools or to update tool versions. :depth: 2 +.. _USING:PoCConf:Over: + Overview ======== The setup process is started by invoking PoC's frontend script with the command ``configure``. Please follow the instructions on screen. Use the keyboard -buttons: :kbd:`Y` to accept, :kbd:`N` to decline, :kbd:`P` to skip/pass a step -and :kbd:`Return` to accept a default value displayed in brackets. +buttons: |kbd-Y| to accept, |kbd-N| to decline, |kbd-P| to skip/pass a step and +|kbd-Return| to accept a default value displayed in brackets. Optionally, a vendor or tool chain name can be passed to the configuration process to launch only its configuration routines. @@ -73,6 +113,8 @@ Please see the Linux instructions. Installation directory: D:\git\PoC (found in environment variable) +.. _USING:PoCConf:PoC: + The PoC-Library =============== PoC itself has a fully automated configuration routine. It detects if PoC is @@ -86,6 +128,9 @@ by ``PoC.ps1`` or ``poc.sh``. PoC version: v1.0.1 (found in git) Installation directory: D:\git\PoC (found in environment variable) + +.. _USING:PoCConf:Git: + Git === .. NOTE:: @@ -103,6 +148,9 @@ Git Installing Git hooks... Setting 'pre-commit' hook for PoC... + +.. _USING:PoCConf:Aldec: + Aldec ===== Configure the installation directory for all Aldec tools. @@ -122,6 +170,9 @@ Active-HDL Aldec Active-HDL version [10.3]: Aldec Active-HDL installation directory [C:\Aldec\Active-HDL]: C:\Aldec\Active-HDL-Student-Edition + +.. _USING:PoCConf:Altera: + Altera ====== Configure the installation directory for all Altera tools. @@ -149,6 +200,9 @@ ModelSim Altera Edition Is ModelSim Altera Edition installed on your system? [Y/n/p]: Y ModelSim Altera Edition installation directory [C:\Altera\15.0\modelsim_ae]: C:\Altera\16.0\modelsim_ase + +.. _USING:PoCConf:Lattice: + Lattice ======== Configure the installation directory for all Lattice Semiconductor tools. @@ -177,6 +231,9 @@ Active-HDL Lattice Edition Active-HDL Lattice Edition version [10.2]: Active-HDL Lattice Edition installation directory [D:\Lattice\Diamond\3.7_x64\active-hdl]: + +.. _USING:PoCConf:Mentor: + Mentor Graphics =============== Configure the installation directory for all mentor Graphics tools. @@ -196,6 +253,9 @@ QuestaSim Mentor QuestaSim version [10.4d]: 10.4c Mentor QuestaSim installation directory [C:\Mentor\QuestaSim\10.4c]: C:\Mentor\QuestaSim64\10.4c + +.. _USING:PoCConf:Xilinx: + Xilinx ====== Configure the installation directory for all Xilinx tools. @@ -233,6 +293,9 @@ answer the following questions: Xilinx Vivado version [2016.2]: Xilinx Vivado installation directory [C:\Xilinx\Vivado\2016.2]: + +.. _USING:PoCConf:GHDL: + GHDL ==== .. code-block:: none @@ -241,6 +304,9 @@ GHDL Is GHDL installed on your system? [Y/n/p]: Y GHDL installation directory [C:\Tools\GHDL\0.34dev]: + +.. _USING:PoCConf:GTKWave: + GTKWave ======== .. code-block:: none @@ -249,6 +315,9 @@ GTKWave Is GTKWave installed on your system? [Y/n/p]: Y GTKWave installation directory [C:\Tools\GTKWave\3.3.71]: + +.. _USING:PoCConf:HookFiles: + Hook Files ========== diff --git a/docs/UsingPoC/PrecompilingVendorLibraries.rst b/docs/UsingPoC/PrecompilingVendorLibraries.rst index d5512571..b4e4f776 100644 --- a/docs/UsingPoC/PrecompilingVendorLibraries.rst +++ b/docs/UsingPoC/PrecompilingVendorLibraries.rst @@ -1,3 +1,4 @@ +.. _USING:PreCompile: Pre-Compiling Vendor Libraries ############################## @@ -7,9 +8,12 @@ Pre-Compiling Vendor Libraries :depth: 2 :backlinks: entry + .. index:: single: Pre-compilation +.. _USING:PreCompile:Over: + Overview ******** @@ -29,45 +33,53 @@ are located in ``\tools\precompile\`` and the output is stored in .. index:: pair: Pre-compilation; Supported Simulators +.. _USING:PreCompile:Simulators: + Supported Simulators ******************** The current set of pre-compile scripts support these simulators: -+------------+------------------------------+--------------+--------------+---------------+--------------------+ -| Vendor | Simulator and Edition | Altera | Lattice | Xilinx (ISE) | Xilinx (Vivado) | -+============+==============================+==============+==============+===============+====================+ -| T. Gingold | GHDL with ``--std=93c`` |br| | yes |br| | yes |br| | yes |br| | yes |br| | -| | GHDL with ``--std=08`` | yes | yes | yes | yes | -+------------+------------------------------+--------------+--------------+---------------+--------------------+ -| Aldec | Active-HDL |br| | planned |br| | planned |br| | planned |br| | planned |br| | -| | Active-HDL Lattice Ed. |br| | planned |br| | shipped |br| | planned |br| | planned |br| | -| | Reviera-PRO | planned | planned | planned | planned | -+------------+------------------------------+--------------+--------------+---------------+--------------------+ -| Mentor | ModelSim |br| | yes |br| | yes |br| | yes |br| | yes |br| | -| | ModelSim Altera Ed. |br| | shipped |br| | yes |br| | yes |br| | yes |br| | -| | QuestaSim | yes | yes | yes | yes | -+------------+------------------------------+--------------+--------------+---------------+--------------------+ -| Xilinx | ISE Simulator |br| | | | shipped |br| | not supported |br| | -| | Vivado Simulator | | | not supported | shipped | -+------------+------------------------------+--------------+--------------+---------------+--------------------+ ++------------------+--------------------------------------+--------------+--------------+-----------------+----------------------+ +| Vendor | Simulator and Edition | Altera | Lattice | Xilinx (ISE) | Xilinx (Vivado) | ++==================+======================================+==============+==============+=================+======================+ +| T. Gingold |br| | GHDL with ``--std=93c`` |br| | yes |br| | yes |br| | yes |br| | yes |br| | +| | GHDL with ``--std=08`` | yes | yes | yes | yes | ++------------------+--------------------------------------+--------------+--------------+-----------------+----------------------+ +| Aldec |br| | Active-HDL (or Stududent Ed.) |br| | planned |br| | planned |br| | planned |br| | planned |br| | +| |br| | Active-HDL Lattice Ed. |br| | planned |br| | shipped |br| | planned |br| | planned |br| | +| | Reviera-PRO | planned | planned | planned | planned | ++------------------+--------------------------------------+--------------+--------------+-----------------+----------------------+ +| Mentor |br| | ModelSim PE (or Stududent Ed.) |br| | yes |br| | yes |br| | yes |br| | yes |br| | +| |br| | ModelSim SE |br| | yes |br| | yes |br| | yes |br| | yes |br| | +| |br| | ModelSim Altera Ed. |br| | shipped |br| | yes |br| | yes |br| | yes |br| | +| | QuestaSim | yes | yes | yes | yes | ++------------------+--------------------------------------+--------------+--------------+-----------------+----------------------+ +| Xilinx |br| | ISE Simulator |br| | | | shipped |br| | not supported |br| | +| | Vivado Simulator | | | not supported | shipped | ++------------------+--------------------------------------+--------------+--------------+-----------------+----------------------+ .. index:: pair: Pre-compilation; Vendor Primitives +.. _USING:PreCompile:Primitives: + FPGA Vendor's Primitive Libraries -********************************* +**************************************************************************************************************************************************************** +.. # =========================================================================================================================================================== .. index:: pair: Pre-compilation; Altera +.. _USING:PreCompile:Primitives:Altera: + Altera ====== .. note:: The Altera Quartus tool chain needs to be configured in PoC. |br| - See :doc:`Configuring PoC's Infrastruture ` for further details. + See :ref:`Configuring PoC's Infrastruture ` for further details. On Linux -------- @@ -81,23 +93,34 @@ On Linux **List of command line arguments:** -+------------------+-------------------------------+ -| Common Option | Description | -+=====+============+===============================+ -| -h | --help | Print embedded help page(s) | -+-----+------------+-------------------------------+ -| -c | --clean | Clean-up directories | -+-----+------------+-------------------------------+ -| -a | --all | Compile for all simulators | -+-----+------------+-------------------------------+ -| | --ghdl | Compile for GHDL | -+-----+------------+-------------------------------+ -| | --questa | Compile for QuestaSim | -+-----+------------+-------------------------------+ -| | --vhdl93 | Compile only for VHDL-93 | -+-----+------------+-------------------------------+ -| | --vhdl2008 | Compile only for VHDL-2008 | -+-----+------------+-------------------------------+ +.. |c-altera-sh-h| replace:: :option:`-h ` +.. |c-altera-sh-c| replace:: :option:`-c ` +.. |c-altera-sh-a| replace:: :option:`-a ` +.. |c-altera-sh-help| replace:: :option:`--help ` +.. |c-altera-sh-clean| replace:: :option:`--clean ` +.. |c-altera-sh-all| replace:: :option:`--all ` +.. |c-altera-sh-ghdl| replace:: :option:`--ghdl ` +.. |c-altera-sh-questa| replace:: :option:`--questa ` +.. |c-altera-sh-vhdl93| replace:: :option:`--vhdl93 ` +.. |c-altera-sh-vhdl08| replace:: :option:`--vhdl2008 ` + ++------------------------------------------+---------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++==================+=======================+===========================================================================+ +| |c-altera-sh-h| | |c-altera-sh-help| | Print embedded help page(s). | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| |c-altera-sh-c| | |c-altera-sh-clean| | Clean-up directories. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| |c-altera-sh-a| | |c-altera-sh-all| | Compile for all simulators. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-altera-sh-ghdl| | Compile for GHDL. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-altera-sh-questa| | Compile for QuestaSim. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-altera-sh-vhdl93| | GHDL only: Compile only for VHDL-93. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-altera-sh-vhdl08| | GHDL only: Compile only for VHDL-2008. | ++------------------+-----------------------+---------------------------------------------------------------------------+ On Windows @@ -112,34 +135,47 @@ On Windows **List of command line arguments:** -+-----------------+-------------------------------+ -| Common Option | Description | -+=====+===========+===============================+ -| -h | -Help | Print embedded help page(s) | -+-----+-----------+-------------------------------+ -| -c | -Clean | Clean-up directories | -+-----+-----------+-------------------------------+ -| -a | -All | Compile for all simulators | -+-----+-----------+-------------------------------+ -| | -GHDL | Compile for GHDL | -+-----+-----------+-------------------------------+ -| | -Questa | Compile for QuestaSim | -+-----+-----------+-------------------------------+ -| | -VHDL93 | Compile only for VHDL-93 | -+-----+-----------+-------------------------------+ -| | -VHDL2008 | Compile only for VHDL-2008 | -+-----+-----------+-------------------------------+ - - +.. |c-altera-ps-h| replace:: ``-h`` +.. |c-altera-ps-c| replace:: ``-c`` +.. |c-altera-ps-a| replace:: ``-a`` +.. |c-altera-ps-help| replace:: :option:`-Help ` +.. |c-altera-ps-clean| replace:: :option:`-Clean ` +.. |c-altera-ps-all| replace:: :option:`-All ` +.. |c-altera-ps-ghdl| replace:: :option:`-GHDL ` +.. |c-altera-ps-questa| replace:: :option:`-Questa ` +.. |c-altera-ps-vhdl93| replace:: :option:`-VHDL93 ` +.. |c-altera-ps-vhdl08| replace:: :option:`-VHDL2008 ` + ++------------------------------------------+---------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++==================+=======================+===========================================================================+ +| |c-altera-ps-h| | |c-altera-ps-help| | Print embedded help page(s). | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| |c-altera-ps-c| | |c-altera-ps-clean| | Clean-up directories. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| |c-altera-ps-a| | |c-altera-ps-all| | Compile for all simulators. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-altera-ps-ghdl| | Compile for GHDL. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-altera-ps-questa| | Compile for QuestaSim. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-altera-ps-vhdl93| | GHDL only: Compile only for VHDL-93. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-altera-ps-vhdl08| | GHDL only: Compile only for VHDL-2008. | ++------------------+-----------------------+---------------------------------------------------------------------------+ + +.. # =========================================================================================================================================================== .. index:: pair: Pre-compilation; Lattice +.. _USING:PreCompile:Primitives:Lattice: + Lattice ======== .. note:: The Lattice Diamond tool chain needs to be configured in PoC. |br| - See :doc:`Configuring PoC's Infrastruture ` for further details. + See :ref:`Configuring PoC's Infrastruture ` for further details. On Linux -------- @@ -153,23 +189,34 @@ On Linux **List of command line arguments:** -+------------------+-------------------------------+ -| Common Option | Description | -+=====+============+===============================+ -| -h | --help | Print embedded help page(s) | -+-----+------------+-------------------------------+ -| -c | --clean | Clean-up directories | -+-----+------------+-------------------------------+ -| -a | --all | Compile for all simulators | -+-----+------------+-------------------------------+ -| | --ghdl | Compile for GHDL | -+-----+------------+-------------------------------+ -| | --questa | Compile for QuestaSim | -+-----+------------+-------------------------------+ -| | --vhdl93 | Compile only for VHDL-93 | -+-----+------------+-------------------------------+ -| | --vhdl2008 | Compile only for VHDL-2008 | -+-----+------------+-------------------------------+ +.. |c-lattice-sh-h| replace:: :option:`-h ` +.. |c-lattice-sh-c| replace:: :option:`-c ` +.. |c-lattice-sh-a| replace:: :option:`-a ` +.. |c-lattice-sh-help| replace:: :option:`--help ` +.. |c-lattice-sh-clean| replace:: :option:`--clean ` +.. |c-lattice-sh-all| replace:: :option:`--all ` +.. |c-lattice-sh-ghdl| replace:: :option:`--ghdl ` +.. |c-lattice-sh-questa| replace:: :option:`--questa ` +.. |c-lattice-sh-vhdl93| replace:: :option:`--vhdl93 ` +.. |c-lattice-sh-vhdl08| replace:: :option:`--vhdl2008 ` + ++--------------------------------------------+-------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++===================+========================+=========================================================================+ +| |c-lattice-sh-h| | |c-lattice-sh-help| | Print embedded help page(s). | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| |c-lattice-sh-c| | |c-lattice-sh-clean| | Clean-up directories. | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| |c-lattice-sh-a| | |c-lattice-sh-all| | Compile for all simulators. | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| | |c-lattice-sh-ghdl| | Compile for GHDL. | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| | |c-lattice-sh-questa| | Compile for QuestaSim. | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| | |c-lattice-sh-vhdl93| | GHDL only: Compile only for VHDL-93. | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| | |c-lattice-sh-vhdl08| | GHDL only: Compile only for VHDL-2008. | ++-------------------+------------------------+-------------------------------------------------------------------------+ On Windows @@ -184,34 +231,47 @@ On Windows **List of command line arguments:** -+-----------------+-------------------------------+ -| Common Option | Description | -+=====+===========+===============================+ -| -h | -Help | Print embedded help page(s) | -+-----+-----------+-------------------------------+ -| -c | -Clean | Clean-up directories | -+-----+-----------+-------------------------------+ -| -a | -All | Compile for all simulators | -+-----+-----------+-------------------------------+ -| | -GHDL | Compile for GHDL | -+-----+-----------+-------------------------------+ -| | -Questa | Compile for QuestaSim | -+-----+-----------+-------------------------------+ -| | -VHDL93 | Compile only for VHDL-93 | -+-----+-----------+-------------------------------+ -| | -VHDL2008 | Compile only for VHDL-2008 | -+-----+-----------+-------------------------------+ - - +.. |c-lattice-ps-h| replace:: ``-h`` +.. |c-lattice-ps-c| replace:: ``-c`` +.. |c-lattice-ps-a| replace:: ``-a`` +.. |c-lattice-ps-help| replace:: :option:`-Help ` +.. |c-lattice-ps-clean| replace:: :option:`-Clean ` +.. |c-lattice-ps-all| replace:: :option:`-All ` +.. |c-lattice-ps-ghdl| replace:: :option:`-GHDL ` +.. |c-lattice-ps-questa| replace:: :option:`-Questa ` +.. |c-lattice-ps-vhdl93| replace:: :option:`-VHDL93 ` +.. |c-lattice-ps-vhdl08| replace:: :option:`-VHDL2008 ` + ++--------------------------------------------+-------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++===================+========================+=========================================================================+ +| |c-lattice-ps-h| | |c-lattice-ps-help| | Print embedded help page(s). | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| |c-lattice-ps-c| | |c-lattice-ps-clean| | Clean-up directories. | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| |c-lattice-ps-a| | |c-lattice-ps-all| | Compile for all simulators. | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| | |c-lattice-ps-ghdl| | Compile for GHDL. | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| | |c-lattice-ps-questa| | Compile for QuestaSim. | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| | |c-lattice-ps-vhdl93| | GHDL only: Compile only for VHDL-93. | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| | |c-lattice-ps-vhdl08| | GHDL only: Compile only for VHDL-2008. | ++-------------------+------------------------+-------------------------------------------------------------------------+ + +.. # =========================================================================================================================================================== .. index:: pair: Pre-compilation; Xilinx ISE +.. _USING:PreCompile:Primitives:XilinxISE: + Xilinx ISE ========== .. note:: The Xilinx ISE tool chain needs to be configured in PoC. |br| - See :doc:`Configuring PoC's Infrastruture ` for further details. + See :ref:`Configuring PoC's Infrastruture ` for further details. On Linux -------- @@ -225,23 +285,34 @@ On Linux **List of command line arguments:** -+------------------+-------------------------------+ -| Common Option | Description | -+=====+============+===============================+ -| -h | --help | Print embedded help page(s) | -+-----+------------+-------------------------------+ -| -c | --clean | Clean-up directories | -+-----+------------+-------------------------------+ -| -a | --all | Compile for all simulators | -+-----+------------+-------------------------------+ -| | --ghdl | Compile for GHDL | -+-----+------------+-------------------------------+ -| | --questa | Compile for QuestaSim | -+-----+------------+-------------------------------+ -| | --vhdl93 | Compile only for VHDL-93 | -+-----+------------+-------------------------------+ -| | --vhdl2008 | Compile only for VHDL-2008 | -+-----+------------+-------------------------------+ +.. |c-ise-sh-h| replace:: :option:`-h ` +.. |c-ise-sh-c| replace:: :option:`-c ` +.. |c-ise-sh-a| replace:: :option:`-a ` +.. |c-ise-sh-help| replace:: :option:`--help ` +.. |c-ise-sh-clean| replace:: :option:`--clean ` +.. |c-ise-sh-all| replace:: :option:`--all ` +.. |c-ise-sh-ghdl| replace:: :option:`--ghdl ` +.. |c-ise-sh-questa| replace:: :option:`--questa ` +.. |c-ise-sh-vhdl93| replace:: :option:`--vhdl93 ` +.. |c-ise-sh-vhdl08| replace:: :option:`--vhdl2008 ` + ++------------------------------------+---------------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++===============+====================+=================================================================================+ +| |c-ise-sh-h| | |c-ise-sh-help| | Print embedded help page(s). | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| |c-ise-sh-c| | |c-ise-sh-clean| | Clean-up directories. | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| |c-ise-sh-a| | |c-ise-sh-all| | Compile for all simulators. | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| | |c-ise-sh-ghdl| | Compile for GHDL. | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| | |c-ise-sh-questa| | Compile for QuestaSim. | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| | |c-ise-sh-vhdl93| | GHDL only: Compile only for VHDL-93. | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| | |c-ise-sh-vhdl08| | GHDL only: Compile only for VHDL-2008. | ++---------------+--------------------+---------------------------------------------------------------------------------+ On Windows @@ -256,34 +327,47 @@ On Windows **List of command line arguments:** -+-----------------+-------------------------------+ -| Common Option | Description | -+=====+===========+===============================+ -| -h | -Help | Print embedded help page(s) | -+-----+-----------+-------------------------------+ -| -c | -Clean | Clean-up directories | -+-----+-----------+-------------------------------+ -| -a | -All | Compile for all simulators | -+-----+-----------+-------------------------------+ -| | -GHDL | Compile for GHDL | -+-----+-----------+-------------------------------+ -| | -Questa | Compile for QuestaSim | -+-----+-----------+-------------------------------+ -| | -VHDL93 | Compile only for VHDL-93 | -+-----+-----------+-------------------------------+ -| | -VHDL2008 | Compile only for VHDL-2008 | -+-----+-----------+-------------------------------+ - - +.. |c-ise-ps-h| replace:: ``-h`` +.. |c-ise-ps-c| replace:: ``-c`` +.. |c-ise-ps-a| replace:: ``-a`` +.. |c-ise-ps-help| replace:: :option:`-Help ` +.. |c-ise-ps-clean| replace:: :option:`-Clean ` +.. |c-ise-ps-all| replace:: :option:`-All ` +.. |c-ise-ps-ghdl| replace:: :option:`-GHDL ` +.. |c-ise-ps-questa| replace:: :option:`-Questa ` +.. |c-ise-ps-vhdl93| replace:: :option:`-VHDL93 ` +.. |c-ise-ps-vhdl08| replace:: :option:`-VHDL2008 ` + ++------------------------------------+---------------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++===============+====================+=================================================================================+ +| |c-ise-ps-h| | |c-ise-ps-help| | Print embedded help page(s). | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| |c-ise-ps-c| | |c-ise-ps-clean| | Clean-up directories. | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| |c-ise-ps-a| | |c-ise-ps-all| | Compile for all simulators. | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| | |c-ise-ps-ghdl| | Compile for GHDL. | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| | |c-ise-ps-questa| | Compile for QuestaSim. | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| | |c-ise-ps-vhdl93| | GHDL only: Compile only for VHDL-93. | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| | |c-ise-ps-vhdl08| | GHDL only: Compile only for VHDL-2008. | ++---------------+--------------------+---------------------------------------------------------------------------------+ + +.. # =========================================================================================================================================================== .. index:: pair: Pre-compilation; Xilinx Vivado +.. _USING:PreCompile:Primitives:XilinxVivado + Xilinx Vivado ============= .. note:: The Xilinx Vivado tool chain needs to be configured in PoC. |br| - See :doc:`Configuring PoC's Infrastruture ` for further details. + See :ref:`Configuring PoC's Infrastruture ` for further details. On Linux -------- @@ -297,23 +381,34 @@ On Linux **List of command line arguments:** -+------------------+-------------------------------+ -| Common Option | Description | -+=====+============+===============================+ -| -h | --help | Print embedded help page(s) | -+-----+------------+-------------------------------+ -| -c | --clean | Clean-up directories | -+-----+------------+-------------------------------+ -| -a | --all | Compile for all simulators | -+-----+------------+-------------------------------+ -| | --ghdl | Compile for GHDL | -+-----+------------+-------------------------------+ -| | --questa | Compile for QuestaSim | -+-----+------------+-------------------------------+ -| | --vhdl93 | Compile only for VHDL-93 | -+-----+------------+-------------------------------+ -| | --vhdl2008 | Compile only for VHDL-2008 | -+-----+------------+-------------------------------+ +.. |c-vivado-sh-h| replace:: :option:`-h ` +.. |c-vivado-sh-c| replace:: :option:`-c ` +.. |c-vivado-sh-a| replace:: :option:`-a ` +.. |c-vivado-sh-help| replace:: :option:`--help ` +.. |c-vivado-sh-clean| replace:: :option:`--clean ` +.. |c-vivado-sh-all| replace:: :option:`--all ` +.. |c-vivado-sh-ghdl| replace:: :option:`--ghdl ` +.. |c-vivado-sh-questa| replace:: :option:`--questa ` +.. |c-vivado-sh-vhdl93| replace:: :option:`--vhdl93 ` +.. |c-vivado-sh-vhdl08| replace:: :option:`--vhdl2008 ` + ++------------------------------------------+---------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++==================+=======================+===========================================================================+ +| |c-vivado-sh-h| | |c-vivado-sh-help| | Print embedded help page(s). | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| |c-vivado-sh-c| | |c-vivado-sh-clean| | Clean-up directories. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| |c-vivado-sh-a| | |c-vivado-sh-all| | Compile for all simulators. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-vivado-sh-ghdl| | Compile for GHDL. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-vivado-sh-questa| | Compile for QuestaSim. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-vivado-sh-vhdl93| | GHDL only: Compile only for VHDL-93. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-vivado-sh-vhdl08| | GHDL only: Compile only for VHDL-2008. | ++------------------+-----------------------+---------------------------------------------------------------------------+ On Windows @@ -328,34 +423,50 @@ On Windows **List of command line arguments:** -+-----------------+-------------------------------+ -| Common Option | Description | -+=====+===========+===============================+ -| -h | -Help | Print embedded help page(s) | -+-----+-----------+-------------------------------+ -| -c | -Clean | Clean-up directories | -+-----+-----------+-------------------------------+ -| -a | -All | Compile for all simulators | -+-----+-----------+-------------------------------+ -| | -GHDL | Compile for GHDL | -+-----+-----------+-------------------------------+ -| | -Questa | Compile for QuestaSim | -+-----+-----------+-------------------------------+ -| | -VHDL93 | Compile only for VHDL-93 | -+-----+-----------+-------------------------------+ -| | -VHDL2008 | Compile only for VHDL-2008 | -+-----+-----------+-------------------------------+ - - +.. |c-vivado-ps-h| replace:: ``-h`` +.. |c-vivado-ps-c| replace:: ``-c`` +.. |c-vivado-ps-a| replace:: ``-a`` +.. |c-vivado-ps-help| replace:: :option:`-Help ` +.. |c-vivado-ps-clean| replace:: :option:`-Clean ` +.. |c-vivado-ps-all| replace:: :option:`-All ` +.. |c-vivado-ps-ghdl| replace:: :option:`-GHDL ` +.. |c-vivado-ps-questa| replace:: :option:`-Questa ` +.. |c-vivado-ps-vhdl93| replace:: :option:`-VHDL93 ` +.. |c-vivado-ps-vhdl08| replace:: :option:`-VHDL2008 ` + ++------------------------------------------+---------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++==================+=======================+===========================================================================+ +| |c-vivado-ps-h| | |c-vivado-ps-help| | Print embedded help page(s). | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| |c-vivado-ps-c| | |c-vivado-ps-clean| | Clean-up directories. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| |c-vivado-ps-a| | |c-vivado-ps-all| | Compile for all simulators. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-vivado-ps-ghdl| | Compile for GHDL. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-vivado-ps-questa| | Compile for QuestaSim. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-vivado-ps-vhdl93| | GHDL only: Compile only for VHDL-93. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-vivado-ps-vhdl08| | GHDL only: Compile only for VHDL-2008. | ++------------------+-----------------------+---------------------------------------------------------------------------+ + +.. # =========================================================================================================================================================== .. index:: pair: Pre-compilation; Third-Party Libraries +.. _USING:PreCompile:ThirdParty: + Third-Party Libraries -********************* +**************************************************************************************************************************************************************** +.. # =========================================================================================================================================================== .. index:: pair: Pre-compilation; OSVVM +.. _USING:PreCompile:ThirdParty:OSVVM: + OSVVM ===== @@ -371,19 +482,28 @@ On Linux **List of command line arguments:** -+------------------+-------------------------------+ -| Common Option | Description | -+=====+============+===============================+ -| -h | --help | Print embedded help page(s) | -+-----+------------+-------------------------------+ -| -c | --clean | Clean-up directories | -+-----+------------+-------------------------------+ -| -a | --all | Compile for all simulators | -+-----+------------+-------------------------------+ -| | --ghdl | Compile for GHDL | -+-----+------------+-------------------------------+ -| | --questa | Compile for QuestaSim | -+-----+------------+-------------------------------+ +.. |c-osvvm-sh-h| replace:: :option:`-h ` +.. |c-osvvm-sh-c| replace:: :option:`-c ` +.. |c-osvvm-sh-a| replace:: :option:`-a ` +.. |c-osvvm-sh-help| replace:: :option:`--help ` +.. |c-osvvm-sh-clean| replace:: :option:`--clean ` +.. |c-osvvm-sh-all| replace:: :option:`--all ` +.. |c-osvvm-sh-ghdl| replace:: :option:`--ghdl ` +.. |c-osvvm-sh-questa| replace:: :option:`--questa ` + ++----------------------------------------+-----------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++=================+======================+=============================================================================+ +| |c-osvvm-sh-h| | |c-osvvm-sh-help| | Print embedded help page(s). | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| |c-osvvm-sh-c| | |c-osvvm-sh-clean| | Clean-up directories. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| |c-osvvm-sh-a| | |c-osvvm-sh-all| | Compile for all simulators. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| | |c-osvvm-sh-ghdl| | Compile for GHDL. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| | |c-osvvm-sh-questa| | Compile for QuestaSim. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ On Windows @@ -398,24 +518,35 @@ On Windows **List of command line arguments:** -+-----------------+-------------------------------+ -| Common Option | Description | -+=====+===========+===============================+ -| -h | -Help | Print embedded help page(s) | -+-----+-----------+-------------------------------+ -| -c | -Clean | Clean-up directories | -+-----+-----------+-------------------------------+ -| -a | -All | Compile for all simulators | -+-----+-----------+-------------------------------+ -| | -GHDL | Compile for GHDL | -+-----+-----------+-------------------------------+ -| | -Questa | Compile for QuestaSim | -+-----+-----------+-------------------------------+ - - +.. |c-osvvm-ps-h| replace:: ``-h`` +.. |c-osvvm-ps-c| replace:: ``-c`` +.. |c-osvvm-ps-a| replace:: ``-a`` +.. |c-osvvm-ps-help| replace:: :option:`-Help ` +.. |c-osvvm-ps-clean| replace:: :option:`-Clean ` +.. |c-osvvm-ps-all| replace:: :option:`-All ` +.. |c-osvvm-ps-ghdl| replace:: :option:`-GHDL ` +.. |c-osvvm-ps-questa| replace:: :option:`-Questa ` + ++----------------------------------------+-----------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++=================+======================+=============================================================================+ +| |c-osvvm-ps-h| | |c-osvvm-ps-help| | Print embedded help page(s). | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| |c-osvvm-ps-c| | |c-osvvm-ps-clean| | Clean-up directories. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| |c-osvvm-ps-a| | |c-osvvm-ps-all| | Compile for all simulators. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| | |c-osvvm-ps-ghdl| | Compile for GHDL. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| | |c-osvvm-ps-questa| | Compile for QuestaSim. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ + +.. # =========================================================================================================================================================== .. index:: pair: Pre-compilation; UVVM +.. _USING:PreCompile:ThirdParty:UVVM: + UVVM ==== @@ -431,19 +562,28 @@ On Linux **List of command line arguments:** -+------------------+-------------------------------+ -| Common Option | Description | -+=====+============+===============================+ -| -h | --help | Print embedded help page(s) | -+-----+------------+-------------------------------+ -| -c | --clean | Clean-up directories | -+-----+------------+-------------------------------+ -| -a | --all | Compile for all simulators | -+-----+------------+-------------------------------+ -| | --ghdl | Compile for GHDL | -+-----+------------+-------------------------------+ -| | --questa | Compile for QuestaSim | -+-----+------------+-------------------------------+ +.. |c-uvvm-sh-h| replace:: :option:`-h ` +.. |c-uvvm-sh-c| replace:: :option:`-c ` +.. |c-uvvm-sh-a| replace:: :option:`-a ` +.. |c-uvvm-sh-help| replace:: :option:`--help ` +.. |c-uvvm-sh-clean| replace:: :option:`--clean ` +.. |c-uvvm-sh-all| replace:: :option:`--all ` +.. |c-uvvm-sh-ghdl| replace:: :option:`--ghdl ` +.. |c-uvvm-sh-questa| replace:: :option:`--questa ` + ++--------------------------------------+-------------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++================+=====================+===============================================================================+ +| |c-uvvm-sh-h| | |c-uvvm-sh-help| | Print embedded help page(s). | ++----------------+---------------------+-------------------------------------------------------------------------------+ +| |c-uvvm-sh-c| | |c-uvvm-sh-clean| | Clean-up directories. | ++----------------+---------------------+-------------------------------------------------------------------------------+ +| |c-uvvm-sh-a| | |c-uvvm-sh-all| | Compile for all simulators. | ++----------------+---------------------+-------------------------------------------------------------------------------+ +| | |c-uvvm-sh-ghdl| | Compile for GHDL. | ++----------------+---------------------+-------------------------------------------------------------------------------+ +| | |c-uvvm-sh-questa| | Compile for QuestaSim. | ++----------------+---------------------+-------------------------------------------------------------------------------+ On Windows @@ -458,30 +598,123 @@ On Windows **List of command line arguments:** -+-----------------+-------------------------------+ -| Common Option | Description | -+=====+===========+===============================+ -| -h | -Help | Print embedded help page(s) | -+-----+-----------+-------------------------------+ -| -c | -Clean | Clean-up directories | -+-----+-----------+-------------------------------+ -| -a | -All | Compile for all simulators | -+-----+-----------+-------------------------------+ -| | -GHDL | Compile for GHDL | -+-----+-----------+-------------------------------+ -| | -Questa | Compile for QuestaSim | -+-----+-----------+-------------------------------+ - - +.. |c-uvvm-ps-h| replace:: ``-h`` +.. |c-uvvm-ps-c| replace:: ``-c`` +.. |c-uvvm-ps-a| replace:: ``-a`` +.. |c-uvvm-ps-help| replace:: :option:`-Help ` +.. |c-uvvm-ps-clean| replace:: :option:`-Clean ` +.. |c-uvvm-ps-all| replace:: :option:`-All ` +.. |c-uvvm-ps-ghdl| replace:: :option:`-GHDL ` +.. |c-uvvm-ps-questa| replace:: :option:`-Questa ` + ++--------------------------------------+-------------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++================+=====================+===============================================================================+ +| |c-uvvm-ps-h| | |c-uvvm-ps-help| | Print embedded help page(s). | ++----------------+---------------------+-------------------------------------------------------------------------------+ +| |c-uvvm-ps-c| | |c-uvvm-ps-clean| | Clean-up directories. | ++----------------+---------------------+-------------------------------------------------------------------------------+ +| |c-uvvm-ps-a| | |c-uvvm-ps-all| | Compile for all simulators. | ++----------------+---------------------+-------------------------------------------------------------------------------+ +| | |c-uvvm-ps-ghdl| | Compile for GHDL. | ++----------------+---------------------+-------------------------------------------------------------------------------+ +| | |c-uvvm-ps-questa| | Compile for QuestaSim. | ++----------------+---------------------+-------------------------------------------------------------------------------+ + +.. # =========================================================================================================================================================== + .. index:: + pair: Pre-compilation; VUnit + + .. _USING:PreCompile:ThirdParty:VUnit: + + VUnit + ===== + + On Linux + -------- + + .. code-block:: Bash + + # Example 1 - Compile for all Simulators + ./tools/precompile/compile-vunit.sh --all + # Example 2 - Compile only for GHDL + ./tools/precompile/compile-vunit.sh --ghdl + + **List of command line arguments:** + + .. |c-vunit-sh-h| replace:: :option:`-h ` + .. |c-vunit-sh-c| replace:: :option:`-c ` + .. |c-vunit-sh-a| replace:: :option:`-a ` + .. |c-vunit-sh-help| replace:: :option:`--help ` + .. |c-vunit-sh-clean| replace:: :option:`--clean ` + .. |c-vunit-sh-all| replace:: :option:`--all ` + .. |c-vunit-sh-ghdl| replace:: :option:`--ghdl ` + .. |c-vunit-sh-questa| replace:: :option:`--questa ` + + +----------------------------------------+-----------------------------------------------------------------------------+ + | Common Option | Parameter Description | + +=================+======================+=============================================================================+ + | |c-vunit-sh-h| | |c-vunit-sh-help| | Print embedded help page(s). | + +-----------------+----------------------+-----------------------------------------------------------------------------+ + | |c-vunit-sh-c| | |c-vunit-sh-clean| | Clean-up directories. | + +-----------------+----------------------+-----------------------------------------------------------------------------+ + | |c-vunit-sh-a| | |c-vunit-sh-all| | Compile for all simulators. | + +-----------------+----------------------+-----------------------------------------------------------------------------+ + | | |c-vunit-sh-ghdl| | Compile for GHDL. | + +-----------------+----------------------+-----------------------------------------------------------------------------+ + | | |c-vunit-sh-questa| | Compile for QuestaSim. | + +-----------------+----------------------+-----------------------------------------------------------------------------+ + + + On Windows + ---------- + + .. code-block:: PowerShell + + # Example 1 - Compile for all Simulators + .\tools\precompile\compile-vunit.ps1 -All + # Example 2 - Compile only for GHDL + .\tools\precompile\compile-vunit.ps1 -GHDL + + **List of command line arguments:** + + .. |c-vunit-ps-h| replace:: ``-h`` + .. |c-vunit-ps-c| replace:: ``-c`` + .. |c-vunit-ps-a| replace:: ``-a`` + .. |c-vunit-ps-help| replace:: :option:`-Help ` + .. |c-vunit-ps-clean| replace:: :option:`-Clean ` + .. |c-vunit-ps-all| replace:: :option:`-All ` + .. |c-vunit-ps-ghdl| replace:: :option:`-GHDL ` + .. |c-vunit-ps-questa| replace:: :option:`-Questa ` + + +----------------------------------------+-------------------------------------------------------------------------------+ + | Common Option | Parameter Description | + +=================+======================+===============================================================================+ + | |c-vunit-ps-h| | |c-vunit-ps-help| | Print embedded help page(s). | + +-----------------+----------------------+-------------------------------------------------------------------------------+ + | |c-vunit-ps-c| | |c-vunit-ps-clean| | Clean-up directories. | + +-----------------+----------------------+-------------------------------------------------------------------------------+ + | |c-vunit-ps-a| | |c-vunit-ps-all| | Compile for all simulators. | + +-----------------+----------------------+-------------------------------------------------------------------------------+ + | | |c-vunit-ps-ghdl| | Compile for GHDL. | + +-----------------+----------------------+-------------------------------------------------------------------------------+ + | | |c-vunit-ps-questa| | Compile for QuestaSim. | + +-----------------+----------------------+-------------------------------------------------------------------------------+ + +.. # =========================================================================================================================================================== .. index:: pair: Pre-compilation; Simulator Adapters +.. _USING:PreCompile:Adapter: + Simulator Adapters -****************** +**************************************************************************************************************************************************************** .. index:: pair: Pre-compilation; Cocotb +.. _USING:PreCompile:Adapter:Cocotb: + Cocotb ====== @@ -500,19 +733,28 @@ On Linux **List of command line arguments:** -+------------------+-------------------------------+ -| Common Option | Description | -+=====+============+===============================+ -| -h | --help | Print embedded help page(s) | -+-----+------------+-------------------------------+ -| -c | --clean | Clean-up directories | -+-----+------------+-------------------------------+ -| -a | --all | Compile for all simulators | -+-----+------------+-------------------------------+ -| | --ghdl | Compile for GHDL | -+-----+------------+-------------------------------+ -| | --questa | Compile for QuestaSim | -+-----+------------+-------------------------------+ +.. |c-cocotb-sh-h| replace:: :option:`-h ` +.. |c-cocotb-sh-c| replace:: :option:`-c ` +.. |c-cocotb-sh-a| replace:: :option:`-a ` +.. |c-cocotb-sh-help| replace:: :option:`--help ` +.. |c-cocotb-sh-clean| replace:: :option:`--clean ` +.. |c-cocotb-sh-all| replace:: :option:`--all ` +.. |c-cocotb-sh-ghdl| replace:: :option:`--ghdl ` +.. |c-cocotb-sh-questa| replace:: :option:`--questa ` + ++----------------------------------------+-----------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++=================+======================+=============================================================================+ +| |c-cocotb-sh-h| | |c-cocotb-sh-help| | Print embedded help page(s). | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| |c-cocotb-sh-c| | |c-cocotb-sh-clean| | Clean-up directories. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| |c-cocotb-sh-a| | |c-cocotb-sh-all| | Compile for all simulators. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| | |c-cocotb-sh-ghdl| | Compile for GHDL. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| | |c-cocotb-sh-questa| | Compile for QuestaSim. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ On Windows @@ -530,21 +772,30 @@ On Windows **List of command line arguments:** -+-----------------+-------------------------------+ -| Common Option | Description | -+=====+===========+===============================+ -| -h | -Help | Print embedded help page(s) | -+-----+-----------+-------------------------------+ -| -c | -Clean | Clean-up directories | -+-----+-----------+-------------------------------+ -| -a | -All | Compile for all simulators | -+-----+-----------+-------------------------------+ -| | -GHDL | Compile for GHDL | -+-----+-----------+-------------------------------+ -| | -Questa | Compile for QuestaSim | -+-----+-----------+-------------------------------+ - -.. comment +.. |c-cocotb-ps-h| replace:: ``-h`` +.. |c-cocotb-ps-c| replace:: ``-c`` +.. |c-cocotb-ps-a| replace:: ``-a`` +.. |c-cocotb-ps-help| replace:: :option:`-Help ` +.. |c-cocotb-ps-clean| replace:: :option:`-Clean ` +.. |c-cocotb-ps-all| replace:: :option:`-All ` +.. |c-cocotb-ps-ghdl| replace:: :option:`-GHDL ` +.. |c-cocotb-ps-questa| replace:: :option:`-Questa ` + ++----------------------------------------+-----------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++=================+======================+=============================================================================+ +| |c-cocotb-ps-h| | |c-cocotb-ps-help| | Print embedded help page(s). | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| |c-cocotb-ps-c| | |c-cocotb-ps-clean| | Clean-up directories. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| |c-cocotb-ps-a| | |c-cocotb-ps-all| | Compile for all simulators. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| | |c-cocotb-ps-ghdl| | Compile for GHDL. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| | |c-cocotb-ps-questa| | Compile for QuestaSim. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ + +.. # Supported Simulators: diff --git a/docs/UsingPoC/ProjectManagement.rst b/docs/UsingPoC/ProjectManagement.rst index 0343913e..bff3930a 100644 --- a/docs/UsingPoC/ProjectManagement.rst +++ b/docs/UsingPoC/ProjectManagement.rst @@ -1,3 +1,4 @@ +.. _USING:Project: Project Management ################## diff --git a/docs/UsingPoC/Requirements.rst b/docs/UsingPoC/Requirements.rst index be08a693..ddfc41ec 100644 --- a/docs/UsingPoC/Requirements.rst +++ b/docs/UsingPoC/Requirements.rst @@ -4,6 +4,8 @@ .. include:: +.. _USING:Require: + Requirements ############ @@ -16,11 +18,12 @@ platform independent scripting environment. All Python scripts are wrapped in Bash or PowerShell scripts, to hide some platform specifics of Darwin, Linux or Windows. +.. _USING:Require:Common: + Common requirements: ******************** -* Programming Languages and Runtime Environments: - +Programming Languages and Runtime Environments: * `Python 3 `_ (|geq| 3.5): * `colorama `_ @@ -28,104 +31,118 @@ Common requirements: All Python requirements are listed in `requirements.txt `_ and can be installed via: |br| ``sudo python3.5 -m pip install -r requirements.txt`` - -* Synthesis tool chains: - - * Altera Quartus |geq| 13.0 or - * Lattice Diamond or +Synthesis tool chains: + * Altera Quartus II |geq| 13.0 or + * Altera Quartus Prime |geq| 15.1 or + * Intel Quartus Prime |geq| 16.1 or + * Lattice Diamond |geq| 3.6 or * Xilinx ISE 14.7 [#f1]_ or - * Xilinx Vivado [#f2]_ - -* Simulation tool chains - - * Aldec Active-HDL or + * Xilinx Vivado |geq| 2016.3 [#f2]_ +Simulation tool chains + * Aldec Active-HDL (or Student Edition) or + * Aldec Active-HDL Lattice Edition or + * Mentor Graphics ModelSim PE (or Student Edition) or + * Mentor Graphics ModelSim SE or * Mentor Graphics ModelSim Altera Edition or * Mentor Graphics QuestaSim or * Xilinx ISE Simulator 14.7 or - * Xilinx Vivado Simulator |geq| 2016.1 [#f3]_ or + * Xilinx Vivado Simulator |geq| 2016.3 [#f3]_ or * `GHDL `_ |geq| 0.34dev and `GTKWave `_ |geq| 3.3.70 +.. _USING:Require:Linux: + Linux specific requirements: **************************** -* Debian and Ubuntu specific: - - * bash is configured as :file:`/bin/sh` (`read more `_) |br| +Debian and Ubuntu specific: + * ``bash`` is configured as :file:`/bin/sh` (`read more `_) |br| ``dpkg-reconfigure dash`` Optional Tools on Linux: ======================== -* Git - The command line tools to manage Git repositories. It's possible to extend - the shell prompt with Git information. +Git + The command line tools to manage Git repositories. It's possible to extend + the shell prompt with Git information. +SmartGit + A Git client to handle complex Git flows in a GUI. +`Generic Colouriser `_ (grc) |geq| 1.9 + Colorizes outputs of foreign scripts and programs. GRC is hosted on `GitHub `_ + The latest *.deb installation packages can be downloaded `here `_. -* SmartGit - A Git client to handle complex Git flows in a GUI. - -* `Generic Colouriser `_ (grc) |geq| 1.9 - Colorizes outputs of foreign scripts and programs. GRC is hosted on `GitHub `_ - The latest *.deb installation packages can be downloaded `here `_. +.. _USING:Require:MacOS: Mac OS specific requirements: ***************************** -* Bash |geq| 4.3 - Mac OS is shipped with Bash 3.2. Use Homebrew to install an up-to-date Bash |br| - ``brew install bash`` - -* coreutils - Mac OS' ``readlink`` program has a different behavior than the Linux version. - The ``coreutils`` package installs a GNU readlink clone called ``greadlink``. |br| - ``brew install coreutils`` +Bash |geq| 4.3 + Mac OS is shipped with Bash 3.2. Use Homebrew to install an up-to-date Bash |br| + ``brew install bash`` +coreutils + Mac OS' ``readlink`` program has a different behavior than the Linux version. + The ``coreutils`` package installs a GNU readlink clone called ``greadlink``. |br| + ``brew install coreutils`` Optional Tools on Mac OS: ========================= -* Git - The command line tools to manage Git repositories. It's possible to extend - the shell prompt with Git information. +Git + The command line tools to manage Git repositories. It's possible to extend + the shell prompt with Git information. +SmartGit or SourceTree + A Git client to handle complex Git flows in a GUI. +`Generic Colouriser `_ (grc) |geq| 1.9 + Colorizes outputs of foreign scripts and programs. GRC is hosted on `GitHub `_ |br| + ``brew install Grc`` -* SmartGit or SourceTree - A Git client to handle complex Git flows in a GUI. - -* `Generic Colouriser `_ (grc) |geq| 1.9 - Colorizes outputs of foreign scripts and programs. GRC is hosted on `GitHub `_ |br| - ``brew install Grc`` +.. _USING:Require:Windows: Windows specific requirements: ****************************** -* PowerShell |geq| 4.0 - PowerShell shipped with Windows since Vista. It is a part if the Windows - Management Framework. If the required version not already included in - Windows, it can be downloaded from microsoft.com: `WMF 4.0 `_, - `WMF 5.0 `_ (recommended). +PowerShell + * **Allow local script execution** (`read more `_) |br| + ``PS> Set-ExecutionPolicy RemoteSigned`` + + * **PowerShell** |geq| **5.0 (recommended)** |br| + PowerShell 5.0 is shipped since Windows 10. It is a part if the `Windows Management Framework 5.0 `_ + (WMF). Windows 7 and 8/8.1 can be updated to WMF 5.0. The package does not + include **PSReadLine**, which is included in the Windows 10 + PowerShell environment. Install PSReadLine manually: |br| + ``PS> Install-Module PSReadline``. - * Allow local script execution (`read more `_) |br| - ``Set-ExecutionPolicy RemoteSigned`` - * PowerShell Community Extensions (PSCX) |geq| 3.2 |br| - The latest PSCX can be downloaded from `PowerShellGallery `_ + * **PowerShell 4.0** |br| + PowerShell is shipped with Windows since Vista. If the required version + not already included in Windows, it can be downloaded from Microsoft.com: + `WMF 4.0 `_ Optional Tools on Windows: ========================== -* Git (MSys-Git) - The command line tools to manage Git repositories. +PowerShell |geq| 4.0 + * **PSReadLine** replaces the command line editing experience in PowerShell for versions 3 and up. + * **PowerShell Community Extensions (PSCX)** |geq| **3.2** |br| + The latest PSCX can be downloaded from `PowerShellGallery `_ |br| + ``PS> Install-Module Pscx`` |br| + Note: PSCX |geq| 3.2.1 is required for PowerShell |geq| 5.0. + +Git (MSys-Git) + The command line tools to manage Git repositories. -* SmartGit or SourceTree - A Git client to handle complex Git flows in a GUI. +SmartGit or SourceTree + A Git client to handle complex Git flows in a GUI. -* `posh-git `_ - PowerShell integration for Git |br| - Installing posh-git with `PsGet `_ package manager: ``Install-Module posh-git`` +`posh-git `_ + PowerShell integration for Git |br| + ``PS> Install-Module posh-git`` +.. # Installing posh-git with `PsGet `_ package manager: |br| ------------------------------------------ diff --git a/docs/UsingPoC/Simulation.rst b/docs/UsingPoC/Simulation.rst index 48407de8..9a1c1fcf 100644 --- a/docs/UsingPoC/Simulation.rst +++ b/docs/UsingPoC/Simulation.rst @@ -1,3 +1,4 @@ +.. _USING:Sim: Simulation ########## @@ -6,6 +7,8 @@ Simulation :local: +.. _USING:Sim:Over: + Overview ******** @@ -34,6 +37,8 @@ frontend script: See the Intruction page for a list of supported simulators. +.. _USING:Sim:Quick: + Quick Example ************* @@ -86,6 +91,8 @@ The opened waveform viewer and displayed waveform should look like this: :alt: GTKWave waveform view of PoC.arith.prng. +.. _USING:Sim:Vendor: + Vendor Specific Testbenches *************************** @@ -128,6 +135,9 @@ A vendor specific testbench can be launched by passing either ``--board=xxx`` or and common storage for all supported vendor's pre-compile procedures. See :doc:`Pre-Compiling Vendor Libraries `. + +.. _USING:Sim:Single: + Running a Single Testbench ************************** @@ -180,6 +190,8 @@ PoC runs multiple testbenches at once, all finished testbenches are reported wit there testbench result. The aborted testbench will be listed as errored. +.. _USING:Sim:Aldec-ActiveHDL: + Aldec Active-HDL ================ @@ -207,6 +219,8 @@ PoC entities. The following options are supported for Active-HDL: .\poc.ps1 asim PoC.arith.prng --std=93 +.. _USING:Sim:Cocotb: + Cocotb with QuestaSim backend ============================= @@ -235,6 +249,8 @@ by a list of PoC entities. The following options are supported for Cocotb: .\poc.ps1 cocotb PoC.cache.par +.. _USING:Sim:GHDL: + GHDL (plus GTKwave) =================== @@ -261,6 +277,8 @@ PoC entities. The following options are supported for GHDL: .\poc.ps1 ghdl PoC.arith.prng --board=Atlys -g +.. _USING:Sim:Mentor-QuestaSim: + Mentor Graphics QuestaSim ========================= @@ -303,6 +321,8 @@ IP core's run script, which may default to ``run -all``. +--------------------------+---------------------------------------------------------+ +.. _USING:Sim:Xilinx-iSim: + Xilinx ISE Simulator ==================== @@ -328,6 +348,8 @@ ISE Simulator: .\poc.ps1 isim PoC.arith.prng --board=Atlys -g +.. _USING:Sim:Xilinx-xSim: + Xilinx Vivado Simulator ======================= @@ -355,6 +377,8 @@ Vivado Simulator: .\poc.ps1 xsim PoC.arith.prng --board=Atlys -g +.. _USING:Sim:Group: + Running a Group of Testbenches ****************************** @@ -393,6 +417,8 @@ current namespace and all sub-namespaces. :alt: Report after running multiple testbenches in Active-HDL. +.. _USING:Sim:CI: + Continuous Integration (CI) *************************** @@ -432,4 +458,3 @@ Terrasic DE4 board: `Latest Travis-CI Report `_ Browse the list of branches at Travis-CI.org. - diff --git a/docs/UsingPoC/Synthesis.rst b/docs/UsingPoC/Synthesis.rst index 7c533070..527cb89c 100644 --- a/docs/UsingPoC/Synthesis.rst +++ b/docs/UsingPoC/Synthesis.rst @@ -1,3 +1,4 @@ +.. _USING:Synth: Synthesis ######### @@ -6,6 +7,8 @@ Synthesis :local: +.. _USING:Synth:Over: + Overview ******** @@ -25,10 +28,10 @@ one of PoC's frontend script: .. seealso:: - :doc:`PoC Configuration ` + :ref:`PoC Configuration ` See the Configuration page on how to configure PoC and your installed synthesis tool chains. This is required to invoke the compilers. - :doc:`Supported Compiler ` + :ref:`Supported Compiler ` See the Intruction page for a list of supported compilers. @@ -38,6 +41,9 @@ one of PoC's frontend script: :doc:`List of Supported Development Boards ` See this list to find a supported and well known development board. + +.. _USING:Synth:Quick: + Quick Example ************* @@ -65,65 +71,93 @@ synthesized to a netlist. :alt: PowerShell console output after running PoC.arith.prng with XST. +.. _USING:Synth:Single: + Running a single Synthesis ************************** -A synthesis run is supervised by PoC's ``PoCRoot\py\PoC.py`` service tool, -which offers a consistent interface to all synthesizers. Unfortunately, every -platform has it's specialties, so a wrapper script is needed as abstraction from -the host's operating system. Depending on the choosen tool chain, the wrapper -script will source or invoke the vendor tool's environment scripts to pre-load -the needed environment variables, paths or license file settings. +A synthesis run is supervised by PoC's :ref:`PoCRoot\\py\\PoC.py ` +service tool, which offers a consistent interface to all synthesizers. +Unfortunately, every platform has it's specialties, so a wrapper script is +needed as abstraction from the host's operating system. Depending on the choosen +tool chain, the wrapper script will source or invoke the vendor tool's +environment scripts to pre-load the needed environment variables, paths or +license file settings. The order of options to the frontend script is as following: -`` `` +`` [] `` The frontend offers several common options: -+-----------------+-------------------------------+ -| Common Option | Description | -+=====+===========+===============================+ -| -q | --quiet | Quiet-mode (print nothing) | -+-----+-----------+-------------------------------+ -| -v | --verbose | Print more messages | -+-----+-----------+-------------------------------+ -| -d | --debug | Debug mode (print everything) | -+-----+-----------+-------------------------------+ -| | --dryrun | Run in dry-run mode | -+-----+-----------+-------------------------------+ +.. |-q| replace:: :option:`-q ` +.. |-v| replace:: :option:`-v ` +.. |-d| replace:: :option:`-d ` +.. |--quiet| replace:: :option:`--quiet ` +.. |--verbose| replace:: :option:`--verbose ` +.. |--debug| replace:: :option:`--debug ` +.. |--dryrun| replace:: :option:`--dryrun ` + ++--------------------+---------------------------------------------------------+ +| Common Option | Description | ++======+=============+=========================================================+ +| |-q| | |--quiet| | Quiet-mode (print nothing) | ++------+-------------+---------------------------------------------------------+ +| |-v| | |--verbose| | Print more messages | ++------+-------------+---------------------------------------------------------+ +| |-d| | |--debug| | Debug mode (print everything) | ++------+-------------+---------------------------------------------------------+ +| | |--dryrun| | Run in dry-run mode | ++------+-------------+---------------------------------------------------------+ + One of the following supported synthesizers can be choosen, if installed and configured in PoC: -+-----------+--------------------------------------------------+ -| Simulator | Description | -+===========+==================================================+ -| quartus | Altera Quartus II or Quartus Prime | -+-----------+--------------------------------------------------+ -| lse | Lattice Diamond - Lattice Synthesis Engine (LSE) | -+-----------+--------------------------------------------------+ -| xst | Xilinx ISE Systhesis Tool (XST) | -+-----------+--------------------------------------------------+ -| coregen | Xilinx ISE Core Generator (CoreGen) | -+-----------+--------------------------------------------------+ -| vivado | Xilinx Vivado Synthesis | -+-----------+--------------------------------------------------+ - - -Altera Quartus -============== - -The command to invoke a synthesis using Altera Quartus II or Quartus Prime is -``quartus`` followed by a list of PoC entities. The following options are +.. |l-quartus| replace:: :ref:`Altera Quartus II or Intel Quartus Prime ` +.. |r-quartus| replace:: :ref:`PoC.py quartus ` +.. |l-lse| replace:: :ref:`Lattice (Diamond) Synthesis Engine (LSE) ` +.. |r-lse| replace:: :ref:`PoC.py lse ` +.. |l-xst| replace:: :ref:`Xilinx ISE Systhesis Tool (XST) ` +.. |r-xst| replace:: :ref:`PoC.py xst ` +.. |l-coregen| replace:: :ref:`Xilinx ISE Core Generator (CoreGen) ` +.. |r-coregen| replace:: :ref:`PoC.py coregen ` +.. |l-vivado| replace:: :ref:`Xilinx Vivado Synthesis ` +.. |r-vivado| replace:: :ref:`PoC.py vivado ` + ++---------------------------------+--------------------------------------------+ +| Synthesizer | Command Reference | ++=================================+============================================+ +| |l-quartus| | |r-quartus| | ++---------------------------------+--------------------------------------------+ +| |l-lse| | |r-lse| | ++---------------------------------+--------------------------------------------+ +| |l-xst| | |r-xst| | ++---------------------------------+--------------------------------------------+ +| |l-coregen| | |r-coregen| | ++---------------------------------+--------------------------------------------+ +| |l-vivado| | |r-vivado| | ++---------------------------------+--------------------------------------------+ + + +.. _USING:Synth:Altera-Quartus: + +Altera / Intel Quartus +====================== + +The command to invoke a synthesis using Altera Quartus II or Intel Quartus Prime is +:ref:`quartus ` followed by a list of PoC entities. The following options are supported for Quartus: -+--------------------------+---------------------------------------------------------+ -| Simulator Option | Description | -+====+=====================+=========================================================+ -| | --board= | Specify a target board. | -+----+---------------------+---------------------------------------------------------+ -| | --device= | Specify a target device. | -+----+---------------------+---------------------------------------------------------+ +.. |quartus--board| replace:: :option:`--board=\ ` +.. |quartus--device| replace:: :option:`--device=\ ` + ++--------------------------+---------------------------------------------------+ +| Simulator Option | Description | ++====+=====================+===================================================+ +| | |quartus--board| | Specify a target board. | ++----+---------------------+---------------------------------------------------+ +| | |quartus--device| | Specify a target device. | ++----+---------------------+---------------------------------------------------+ .. rubric:: Example: @@ -133,95 +167,116 @@ supported for Quartus: .\poc.ps1 quartus PoC.arith.prng --board=DE4 +.. _USING:Synth:Lattice-Diamond: + Lattice Diamond =============== -The command to invoke a synthesis using Altera Quartus II or Quartus Prime is -``quartus`` followed by a list of PoC entities. The following options are -supported for Quartus: +The command to invoke a synthesis using Lattice Diamond is :ref:`lse ` followed by +a list of PoC entities. The following options are supported for the Lattice +Synthesis Engine (LSE): + +.. |lse--board| replace:: :option:`--board=\ ` +.. |lse--device| replace:: :option:`--device=\ ` -+--------------------------+---------------------------------------------------------+ -| Simulator Option | Description | -+====+=====================+=========================================================+ -| | --board= | Specify a target board. | -+----+---------------------+---------------------------------------------------------+ -| | --device= | Specify a target device. | -+----+---------------------+---------------------------------------------------------+ ++--------------------+---------------------------------------------------------+ +| Simulator Option | Description | ++====+===============+=========================================================+ +| | |lse--board| | Specify a target board. | ++----+---------------+---------------------------------------------------------+ +| | |lse--device| | Specify a target device. | ++----+---------------+---------------------------------------------------------+ .. rubric:: Example: .. code-block:: PowerShell cd PoCRoot - .\poc.ps1 quartus PoC.arith.prng --board=DE4 + .\poc.ps1 lse PoC.arith.prng --board=ECP5Versa + +.. _USING:Synth:Xilinx-ISE: Xilinx ISE Synthesis Tool (XST) =============================== -The command to invoke a synthesis using Altera Quartus II or Quartus Prime is -``quartus`` followed by a list of PoC entities. The following options are -supported for Quartus: +The command to invoke a synthesis using Xilinx ISE Synthesis is :ref:`xst ` followed +by a list of PoC entities. The following options are supported for the Xilinx +Synthesis Tool (XST): -+--------------------------+---------------------------------------------------------+ -| Simulator Option | Description | -+====+=====================+=========================================================+ -| | --board= | Specify a target board. | -+----+---------------------+---------------------------------------------------------+ -| | --device= | Specify a target device. | -+----+---------------------+---------------------------------------------------------+ +.. |xst--board| replace:: :option:`--board=\ ` +.. |xst--device| replace:: :option:`--device=\ ` + ++--------------------+---------------------------------------------------------+ +| Simulator Option | Description | ++====+===============+=========================================================+ +| | |xst--board| | Specify a target board. | ++----+---------------+---------------------------------------------------------+ +| | |xst--device| | Specify a target device. | ++----+---------------+---------------------------------------------------------+ .. rubric:: Example: .. code-block:: PowerShell cd PoCRoot - .\poc.ps1 quartus PoC.arith.prng --board=DE4 + .\poc.ps1 xst PoC.arith.prng --board=KC705 +.. _USING:Synth:Xilinx-CoreGen: + Xilinx ISE Core Generator ========================= -The command to invoke a synthesis using Altera Quartus II or Quartus Prime is -``quartus`` followed by a list of PoC entities. The following options are -supported for Quartus: +The command to invoke an IP core generation using Xilinx Core Generator is +:ref:`coregen ` followed by a list of PoC entities. The following options are +supported for Core Generator (CG): + +.. |cg--board| replace:: :option:`--board=\ ` +.. |cg--device| replace:: :option:`--device=\ ` -+--------------------------+---------------------------------------------------------+ -| Simulator Option | Description | -+====+=====================+=========================================================+ -| | --board= | Specify a target board. | -+----+---------------------+---------------------------------------------------------+ -| | --device= | Specify a target device. | -+----+---------------------+---------------------------------------------------------+ ++-------------------+----------------------------------------------------------+ +| Simulator Option | Description | ++====+==============+==========================================================+ +| | |cg--board| | Specify a target board. | ++----+--------------+----------------------------------------------------------+ +| | |cg--device| | Specify a target device. | ++----+--------------+----------------------------------------------------------+ .. rubric:: Example: .. code-block:: PowerShell cd PoCRoot - .\poc.ps1 quartus PoC.arith.prng --board=DE4 + .\poc.ps1 coregen PoC.xil.mig.Atlys_1x128 --board=Atlys + + +.. _USING:Synth:Xilinx-Vivado: Xilinx Vivado Synthesis ======================= -The command to invoke a synthesis using Altera Quartus II or Quartus Prime is -``quartus`` followed by a list of PoC entities. The following options are -supported for Quartus: +The command to invoke a synthesis using Xilinx Vivado Synthesis is :ref:`vivado ` +followed by a list of PoC entities. The following options are supported for +Vivado Synthesis (Synth): + +.. |vivado--board| replace:: :option:`--board=\ ` +.. |vivado--device| replace:: :option:`--device=\ ` -+--------------------------+---------------------------------------------------------+ -| Simulator Option | Description | -+====+=====================+=========================================================+ -| | --board= | Specify a target board. | -+----+---------------------+---------------------------------------------------------+ -| | --device= | Specify a target device. | -+----+---------------------+---------------------------------------------------------+ ++-----------------------+------------------------------------------------------+ +| Simulator Option | Description | ++====+==================+======================================================+ +| | |vivado--board| | Specify a target board. | ++----+------------------+------------------------------------------------------+ +| | |vivado--device| | Specify a target device. | ++----+------------------+------------------------------------------------------+ .. rubric:: Example: .. code-block:: PowerShell cd PoCRoot - .\poc.ps1 quartus PoC.arith.prng --board=DE4 + .\poc.ps1 vivado PoC.arith.prng --board=KC705 diff --git a/docs/UsingPoC/VHDLConfiguration.rst b/docs/UsingPoC/VHDLConfiguration.rst index 84abc147..5c133c4e 100644 --- a/docs/UsingPoC/VHDLConfiguration.rst +++ b/docs/UsingPoC/VHDLConfiguration.rst @@ -1,3 +1,4 @@ +.. _USING:VHDLConf: Creating my_config/my_project.vhdl ################################## @@ -7,6 +8,9 @@ used to determine the most suitable implementation depending on the provided platform information. These files are also used to select appropiate work arounds. + +.. _USING:VHDLConf:myconfig: + Create my_config.vhdl ********************* @@ -46,6 +50,8 @@ If the requested board is not known to PoC or it's custom made, then set constant MY_DEVICE : string := "XC6SLX45-3CSG324"; +.. _USING:VHDLConf:myproject: + Create my_project.vhdl ********************** diff --git a/docs/UsingPoC/index.rst b/docs/UsingPoC/index.rst index 4e0c6206..9d8f8142 100644 --- a/docs/UsingPoC/index.rst +++ b/docs/UsingPoC/index.rst @@ -1,8 +1,9 @@ +.. _USING: Using PoC ######### -PoC can be used in several ways, if all :doc:`Requirements ` +PoC can be used in several ways, if all :ref:`Requirements ` are fulfilled. Chose one of the following integration kinds: * Stand-Alone IP Core Library: @@ -25,8 +26,8 @@ are fulfilled. Chose one of the following integration kinds: * No possibility to contribute bugfixes and extensions via Git pull requests. **Next steps:** |br| - 1. See :doc:`Downloads ` for how to download a stand-alone version (*.zip-file) of the PoC-Library. |br| - 2. See :doc:`Configuration ` for how to configure PoC on a local system. + 1. See :ref:`Downloads ` for how to download a stand-alone version (*.zip-file) of the PoC-Library. |br| + 2. See :ref:`Configuration ` for how to configure PoC on a local system. * Stand-Alone IP Core Library cloned from Git: Download PoC via ``git clone`` from GitHub as latest branch copy. IP cores @@ -48,8 +49,8 @@ are fulfilled. Chose one of the following integration kinds: * Using different PoC versions in different projects is not possible **Next steps:** |br| - 1. See :doc:`Downloads ` for how to clone a stand-alone version of the PoC-Library. |br| - 2. See :doc:`Configuration ` for how to configure PoC on a local system. + 1. See :ref:`Downloads ` for how to clone a stand-alone version of the PoC-Library. |br| + 2. See :ref:`Configuration ` for how to configure PoC on a local system. * Embedded IP Core Library as Git Submodule: Integrate PoC as a Git submodule into the destination projects Git repository. @@ -67,8 +68,8 @@ are fulfilled. Chose one of the following integration kinds: * Version linking between hosting Git and PoC. **Next steps:** |br| - 1. See :doc:`Integration ` for how to integrate PoC as a Git submodule into an existing Git. |br| - 2. See :doc:`Configuration ` for how to configure PoC on a local system. + 1. See :ref:`Integration ` for how to integrate PoC as a Git submodule into an existing Git. |br| + 2. See :ref:`Configuration ` for how to configure PoC on a local system. .. toctree:: diff --git a/docs/WhatIsPoC/SupportedToolChains.rst b/docs/WhatIsPoC/SupportedToolChains.rst index 1798587e..7d91c8c7 100644 --- a/docs/WhatIsPoC/SupportedToolChains.rst +++ b/docs/WhatIsPoC/SupportedToolChains.rst @@ -1,6 +1,7 @@ - .. include:: +.. _INTRO:ToolChains: + Which Tool Chains are supported? ################################ @@ -12,6 +13,9 @@ The PoC-Library and its Python-based infrastructure currently supports the follo Tested with Quartus-II |geq| 13.0. |br| Tested with Quartus Prime |geq| 15.1. + * **Intel Quartus** |br| + Tested with Quartus Prime |geq| 16.1. + * **Lattice Diamond** |br| Tested with Diamond |geq| 3.6. @@ -29,22 +33,26 @@ The PoC-Library and its Python-based infrastructure currently supports the follo * Simulation Tool Chains: * **Aldec Active-HDL** |br| - Tested with Active-HDL Student-Edition 10.3 |br| - Tested with Active-HDL Lattice Edition 10.2 + Tested with Active-HDL (or Student-Edition) |geq| 10.3 |br| + Tested with Active-HDL Lattice Edition |geq| 10.2 * **Cocotb with Mentor QuestaSim backend** |br| Tested with Mentor QuestaSim 10.4d + * **Mentor Graphics ModelSim** |br| + Tested with ModelSim PE (or Student Edition) |geq| 10.5c |br| + Tested with ModelSim SE |geq| 10.5c |br| + Tested with ModelSim Altera Edition 10.3d (or Starter Edition) + * **Mentor Graphics QuestaSim/ModelSim** |br| - Tested with ModelSim Altera Edition 10.3d and ModelSim Altera Starter Edition 10.3d |br| - Tested with Mentor QuestaSim 10.4d + Tested with Mentor QuestaSim |geq| 10.4d * **Xilinx ISE Simulator** |br| Tested with ISE Simulator (iSim) 14.7. |br| The Python infrastructure supports isim, but PoC's simulation helper packages and testbenches rely on VHDL-2008 features, which are not supported by isim. * **Xilinx Vivado Simulator** |br| - Tested with Vivado Simulator (xsim) |geq| 2016.1. |br| + Tested with Vivado Simulator (xsim) |geq| 2016.3. |br| The Python infrastructure supports xsim, but PoC's simulation helper packages and testbenches rely on VHDL-2008 features, which are not fully supported by xsim, yet. * **GHDL** + **GTKWave** |br| diff --git a/docs/_extensions/DocumentMember.py b/docs/_extensions/DocumentMember.py new file mode 100644 index 00000000..6070158b --- /dev/null +++ b/docs/_extensions/DocumentMember.py @@ -0,0 +1,55 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# Python Module: +# +# Description: +# ------------------------------------ +# - TODO +# +# License: +# ============================================================================== +# Copyright 2007-2016 Patrick Lehmann - Dresden, Germany +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +# +from lib.SphinxExtensions import DocumentMemberAttribute + + +def skip_member_handler(app, what, name, obj, skip, options): + # try: + # print("skip_member_handler: ", obj) + # except: + # print("skip_member_handler: ERROR") + + try: + attributes = DocumentMemberAttribute.GetAttributes(obj) + if (len(attributes) > 0): + # print("*#"*20) + # try: + # print("skip_member_handler: ", obj) + # except: + # print("skip_member_handler: ERROR") + + return not attributes[0].value + except: + pass + return None + +def setup(app): + app.connect('autodoc-skip-member', skip_member_handler) diff --git a/docs/_extensions/autoprogram.py b/docs/_extensions/autoprogram.py new file mode 100644 index 00000000..cfb98409 --- /dev/null +++ b/docs/_extensions/autoprogram.py @@ -0,0 +1,407 @@ +""" + sphinxcontrib.autoprogram + ~~~~~~~~~~~~~~~~~~~~~~~~~ + + Documenting CLI programs. + + :copyright: Copyright 2014 by Hong Minhee + :license: BSD, see LICENSE for details. + +""" +# pylint: disable=protected-access,missing-docstring +import argparse +import collections +try: + import builtins +except ImportError: + import __builtin__ as builtins +import functools +import os +import re +import six +import textwrap +import unittest + +from docutils import nodes +from docutils.parsers.rst.directives import unchanged +from docutils.statemachine import ViewList +from sphinx.util.compat import Directive +from sphinx.util.nodes import nested_parse_with_titles +from sphinx.domains import std + +__all__ = ('BOOLEAN_OPTIONS', 'AutoprogramDirective', 'ScannerTestCase', + 'import_object', 'scan_programs', 'setup', 'suite') + + +def get_subparser_action(parser): + neg1_action = parser._actions[-1] + + if isinstance(neg1_action, argparse._SubParsersAction): + return neg1_action + + for a in parser._actions: + if isinstance(a, argparse._SubParsersAction): + return a + + +def scan_programs(parser, command=[], maxdepth=0, depth=0): + if maxdepth and depth >= maxdepth: + return + + options = [] + for arg in parser._actions: + if not (arg.option_strings or + isinstance(arg, argparse._SubParsersAction)): + name = (arg.metavar or arg.dest).lower() + desc = (arg.help or '') % {'default': arg.default} + options.append(([name], desc)) + + for arg in parser._actions: + if arg.option_strings and arg.help is not argparse.SUPPRESS: + if isinstance(arg, (argparse._StoreAction, + argparse._AppendAction)): + if arg.choices is None: + metavar = arg.metavar or arg.dest + + if isinstance(metavar, tuple): + names = [ + '{0} <{1}>'.format( + option_string, '> <'.join(metavar).lower() + ) + for option_string in arg.option_strings + ] + else: + names = [ + '{0} <{1}>'.format(option_string, metavar.lower()) + for option_string in arg.option_strings + ] + else: + choices = '{0}'.format(','.join(arg.choices)) + names = ['{0} {{{1}}}'.format(option_string, choices) + for option_string in arg.option_strings] + else: + names = list(arg.option_strings) + desc = (arg.help or '') % {'default': arg.default} + options.append((names, desc)) + + yield command, options, parser + + if parser._subparsers: + choices = () + + subp_action = get_subparser_action(parser) + + if subp_action: + choices = subp_action.choices.items() + + if not (hasattr(collections, 'OrderedDict') and + isinstance(choices, collections.OrderedDict)): + choices = sorted(choices, key=lambda pair: pair[0]) + + for cmd, sub in choices: + if isinstance(sub, argparse.ArgumentParser): + for program in scan_programs( + sub, command + [cmd], maxdepth, depth + 1 + ): + yield program + + +def import_object(import_name): + module_name, expr = import_name.split(':', 1) + try: + mod = __import__(module_name) + except ImportError: + # This happens if the file is a script with no .py extension. Here we + # trick autoprogram to load a module in memory with the contents of + # the script, if there is a script named module_name. Otherwise, raise + # an ImportError as it did before. + import glob + import sys + import os + import imp + + for p in sys.path: + f = glob.glob(os.path.join(p, module_name)) + if len(f) > 0: + with open(f[0]) as fobj: + codestring = fobj.read() + foo = imp.new_module("foo") + six.exec_(codestring, foo.__dict__) + + sys.modules["foo"] = foo + mod = __import__("foo") + break + else: + raise ImportError("No module named {}".format(module_name)) + + reduce_ = getattr(functools, 'reduce', None) or reduce + mod = reduce_(getattr, module_name.split('.')[1:], mod) + globals_ = builtins + if not isinstance(globals_, dict): + globals_ = globals_.__dict__ + return eval(expr, globals_, mod.__dict__) + + +class AutoprogramDirective(Directive): + + has_content = False + required_arguments = 1 + option_spec = { + 'prog': unchanged, + 'maxdepth': unchanged, + 'start_command': unchanged, + 'strip_usage': unchanged, + 'no_usage_codeblock': unchanged, + 'label': unchanged, + } + + def make_rst(self): + import_name, = self.arguments + parser = import_object(import_name or '__undefined__') + prog = self.options.get('prog') + if prog: + original_prog = parser.prog + parser.prog = prog + start_command = self.options.get('start_command', '').split(' ') + strip_usage = 'strip_usage' in self.options + usage_codeblock = 'no_usage_codeblock' not in self.options + + if start_command[0] == '': + start_command.pop(0) + + if start_command: + def get_start_cmd_parser(p): + looking_for = start_command.pop(0) + action = get_subparser_action(p) + + if not action: + raise ValueError('No actions for command ' + looking_for) + + subp = action.choices[looking_for] + + if start_command: + return get_start_cmd_parser(subp) + + return subp + + parser = get_start_cmd_parser(parser) + if prog and parser.prog.startswith(original_prog): + parser.prog = parser.prog.replace(original_prog, prog, 1) + + for commands, options, cmd_parser in scan_programs( + parser, maxdepth=int(self.options.get('maxdepth', 0)) + ): + if prog and cmd_parser.prog.startswith(original_prog): + cmd_parser.prog = cmd_parser.prog.replace( + original_prog, prog, 1) + title = cmd_parser.prog.rstrip() + usage = cmd_parser.format_usage() + + if strip_usage: + to_strip = title.rsplit(' ', 1)[0] + len_to_strip = len(to_strip) - 4 + usage_lines = usage.splitlines() + + usage = os.linesep.join([ + usage_lines[0].replace(to_strip, '...'), + ] + [ + l[len_to_strip:] for l in usage_lines[1:] + ]) + + yield '' + yield '.. program:: ' + title + + if 'label' in self.options: + yield '' + yield '.. _%s:' % (self.options.get('label') + title).replace(" ", "-") + + yield '' + yield title + yield ('!' if commands else '?') * len(title) + yield '' + for line in (cmd_parser.description or '').splitlines(): + yield line + yield '' + + if usage_codeblock: + yield '.. code-block:: console' + yield '' + yield textwrap.indent(usage, ' ') + else: + yield usage + + yield '' + + for option_strings, help_ in options: + yield '.. option:: {0}'.format(', '.join(option_strings)) + yield '' + yield ' ' + help_.replace('\n', ' \n') + yield '' + yield '' + for line in (cmd_parser.epilog or '').splitlines(): + yield line or '' + + yield '' + yield '-' * 20 + yield '' + + def run(self): + node = nodes.section() + node.document = self.state.document + result = ViewList() + for line in self.make_rst(): + result.append(line, '') + nested_parse_with_titles(self.state, result, node) + return node.children + + +def patch_option_role_to_allow_argument_form(): + """Before Sphinx 1.2.2, :rst:dir:`.. option::` directive hadn't + allowed to not start with a dash or slash, so it hadn't been possible + to represent positional arguments (not options). + + https://bitbucket.org/birkenfeld/sphinx/issue/1357/ + + It monkeypatches the :rst:dir:`.. option::` directive's behavior. + + """ + std.option_desc_re = re.compile(r'((?:/|-|--)?[-_a-zA-Z0-9]+)(\s*.*)') + + +def setup(app): + app.add_directive('autoprogram', AutoprogramDirective) + patch_option_role_to_allow_argument_form() + + +class ScannerTestCase(unittest.TestCase): + + def test_simple_parser(self): + parser = argparse.ArgumentParser(description='Process some integers.') + parser.add_argument('integers', metavar='N', type=int, nargs='*', + help='an integer for the accumulator') + parser.add_argument('-i', '--identity', type=int, default=0, + help='the default result for no arguments ' + '(default: 0)') + parser.add_argument('--sum', dest='accumulate', action='store_const', + const=sum, default=max, + help='sum the integers (default: find the max)') + parser.add_argument('--key-value', metavar=('KEY', 'VALUE'), nargs=2) + parser.add_argument('--max', help=argparse.SUPPRESS) # must be opt-out + + programs = scan_programs(parser) + programs = list(programs) + self.assertEqual(1, len(programs)) + parser_info, = programs + program, options, cmd_parser = parser_info + self.assertEqual([], program) + self.assertEqual('Process some integers.', cmd_parser.description) + self.assertEqual(5, len(options)) + self.assertEqual( + (['n'], 'an integer for the accumulator'), + options[0] + ) + self.assertEqual( + (['-h', '--help'], 'show this help message and exit'), + options[1] + ) + self.assertEqual( + (['-i ', '--identity '], + 'the default result for no arguments (default: 0)'), + options[2] + ) + self.assertEqual( + (['--sum'], 'sum the integers (default: find the max)'), + options[3] + ) + self.assertEqual( + (['--key-value ', ], ''), + options[4] + ) + + def test_subcommands(self): + parser = argparse.ArgumentParser(description='Process some integers.') + subparsers = parser.add_subparsers() + max_parser = subparsers.add_parser('max', description='Find the max.') + max_parser.set_defaults(accumulate=max) + max_parser.add_argument('integers', metavar='N', type=int, nargs='+', + help='An integer for the accumulator.') + sum_parser = subparsers.add_parser('sum', + description='Sum the integers.') + sum_parser.set_defaults(accumulate=sum) + sum_parser.add_argument('integers', metavar='N', type=int, nargs='+', + help='An integer for the accumulator.') + programs = scan_programs(parser) + programs = list(programs) + self.assertEqual(3, len(programs)) + # main + program, options, cmd_parser = programs[0] + self.assertEqual([], program) + self.assertEqual('Process some integers.', cmd_parser.description) + self.assertEqual(1, len(options)) + self.assertEqual( + (['-h', '--help'], + 'show this help message and exit'), + options[0] + ) + # max + program, options, cmd_parser = programs[1] + self.assertEqual(['max'], program) + self.assertEqual('Find the max.', cmd_parser.description) + self.assertEqual(2, len(options)) + self.assertEqual((['n'], 'An integer for the accumulator.'), + options[0]) + self.assertEqual( + (['-h', '--help'], + 'show this help message and exit'), + options[1] + ) + # sum + program, options, cmd_parser = programs[2] + self.assertEqual(['sum'], program) + self.assertEqual('Sum the integers.', cmd_parser.description) + self.assertEqual(2, len(options)) + self.assertEqual((['n'], 'An integer for the accumulator.'), + options[0]) + + def test_choices(self): + parser = argparse.ArgumentParser() + parser.add_argument("--awesomeness", choices=["meh", "awesome"]) + program, options, cmd_parser = list(scan_programs(parser))[0] + log_option = options[1] + self.assertEqual((["--awesomeness {meh,awesome}"], ''), log_option) + + def test_parse_epilog(self): + parser = argparse.ArgumentParser( + description='Process some integers.', + epilog='The integers will be processed.' + ) + programs = scan_programs(parser) + programs = list(programs) + self.assertEqual(1, len(programs)) + parser_data, = programs + program, options, cmd_parser = parser_data + self.assertEqual('The integers will be processed.', cmd_parser.epilog) + + +class UtilTestCase(unittest.TestCase): + + def test_import_object(self): + cls = import_object('sphinxcontrib.autoprogram:UtilTestCase') + self.assertTrue(cls is UtilTestCase) + instance = import_object( + 'sphinxcontrib.autoprogram:UtilTestCase("test_import_object")' + ) + self.assertIsInstance(instance, UtilTestCase) + + if not hasattr(unittest.TestCase, 'assertIsInstance'): + def assertIsInstance(self, instance, cls): + self.assertTrue(isinstance(instance, cls), + '{0!r} is not an instance of {1.__module__}.' + '{1.__name__}'.format(instance, cls)) + + +suite = unittest.TestSuite() +suite.addTests( + unittest.defaultTestLoader.loadTestsFromTestCase(ScannerTestCase) +) +suite.addTests(unittest.defaultTestLoader.loadTestsFromTestCase(UtilTestCase)) diff --git a/docs/_static/css/custom.css b/docs/_static/css/custom.css new file mode 100644 index 00000000..59b5412a --- /dev/null +++ b/docs/_static/css/custom.css @@ -0,0 +1,3 @@ +.wy-table-responsive table td { + white-space: normal; +} diff --git a/docs/_templates/autoapi/module.rst b/docs/_templates/autoapi/module.rst index 7f070eb8..f4d129f4 100644 --- a/docs/_templates/autoapi/module.rst +++ b/docs/_templates/autoapi/module.rst @@ -3,13 +3,13 @@ =={{ '=' * node.name|length }}== .. automodule:: {{ node.name }} - + :noindex: {##} {%- block modules -%} {%- if subnodes %} ------------------------------------ +.. #----------------------------------- {##} **Submodules** @@ -24,7 +24,7 @@ .. currentmodule:: {{ node.name }} {##} ------------------------------------ +.. #----------------------------------- {##} {%- if node.variables %} **Variables** @@ -75,6 +75,7 @@ {%- if node.variables %} {% for item, obj in node.variables.items() %} .. autodata:: {{ item }} + :noindex: :annotation: .. code-block:: guess @@ -89,11 +90,14 @@ {%- block exceptions -%} {%- if node.exceptions %} ------------------------------------ +.. #----------------------------------- {% for item in node.exceptions %} .. autoexception:: {{ item }} :members: + :noindex: + :private-members: + :inherited-members: :undoc-members: {##} .. rubric:: Inheritance @@ -109,11 +113,12 @@ {%- block classes -%} {%- if node.classes %} ------------------------------------ +.. #----------------------------------- {% for item in node.classes %} .. autoclass:: {{ item }} :members: + :noindex: :private-members: :undoc-members: :inherited-members: @@ -131,12 +136,13 @@ {%- block functions -%} {%- if node.functions %} ------------------------------------ +.. #----------------------------------- **Functions** {% for item in node.functions %} .. autofunction:: {{ item }} + :noindex: {##} {%- endfor -%} {%- endif -%} diff --git a/docs/_templates/autoapi/script.rst b/docs/_templates/autoapi/script.rst index 4ed46196..57c41c20 100644 --- a/docs/_templates/autoapi/script.rst +++ b/docs/_templates/autoapi/script.rst @@ -9,7 +9,7 @@ {%- block modules -%} {%- if subnodes %} ------------------------------------ +.. #----------------------------------- {##} **Submodules** @@ -24,7 +24,7 @@ .. currentmodule:: {{ node.name }} {##} ------------------------------------ +.. #----------------------------------- {##} {%- if node.variables %} **Variables** @@ -75,6 +75,7 @@ {%- if node.variables %} {% for item, obj in node.variables.items() %} .. autodata:: {{ item }} + :noindex: :annotation: .. code-block:: guess @@ -89,11 +90,14 @@ {%- block exceptions -%} {%- if node.exceptions %} ------------------------------------ +.. #----------------------------------- {% for item in node.exceptions %} .. autoexception:: {{ item }} :members: + :noindex: + :private-members: + :inherited-members: :undoc-members: {##} .. rubric:: Inheritance @@ -109,11 +113,12 @@ {%- block classes -%} {%- if node.classes %} ------------------------------------ +.. #----------------------------------- {% for item in node.classes %} .. autoclass:: {{ item }} :members: + :noindex: :private-members: :undoc-members: :inherited-members: @@ -131,12 +136,13 @@ {%- block functions -%} {%- if node.functions %} ------------------------------------ +.. #----------------------------------- **Functions** {% for item in node.functions %} .. autofunction:: {{ item }} + :noindex: {##} {%- endfor -%} {%- endif -%} diff --git a/docs/conf.py b/docs/conf.py index 4319d4ac..83542d64 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -23,6 +23,7 @@ # documentation root, use os.path.abspath to make it absolute, like shown here. sys.path.insert(0, os.path.abspath('.')) sys.path.insert(0, os.path.abspath('../py')) +sys.path.insert(0, os.path.abspath('_extensions')) # -- General configuration ------------------------------------------------ @@ -34,6 +35,7 @@ # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom # ones. extensions = [ +# Standard Sphinx extensions 'sphinx.ext.autodoc', 'sphinx.ext.extlinks', 'sphinx.ext.intersphinx', @@ -45,13 +47,26 @@ 'sphinx.ext.ifconfig', 'sphinx.ext.viewcode', # 'sphinx.ext.githubpages', - 'sphinxcontrib.autoprogram', +# SphinxContrib extensions + # 'sphinxcontrib.actdiag', + # 'sphinxcontrib.seqdiag', + 'sphinxcontrib.wavedrom', + 'sphinxcontrib.textstyle', + # 'sphinxcontrib.spelling', 'autoapi.sphinx', + # 'changelog', +# local extensions (patched) + 'autoprogram', #'sphinxcontrib.autoprogram', +# local extensions + 'DocumentMember', 'poc' ] -if (not (tags.has('PoCExternal') or tags.has('PoCInternal'))): - tags.add('PoCExternal') +for tag in tags: + print(tag) + +# if (not (tags.has('PoCExternal') or tags.has('PoCInternal'))): + # tags.add('PoCExternal') autodoc_member_order = "bysource" @@ -349,13 +364,17 @@ def _LatestTagName(latestTagHash): # If true, do not generate a @detailmenu in the "Top" node's menu. #texinfo_no_detailmenu = False - -# Example configuration for intersphinx: refer to the Python standard library. +# ============================================================================== +# Sphinx.Ext.InterSphinx +# ============================================================================== intersphinx_mapping = { 'python': ('https://docs.python.org/3.5/', None), 'ghdl': ('http://ghdl.readthedocs.io/en/latest', None) } +# ============================================================================== +# Sphinx.Ext.ExtLinks +# ============================================================================== extlinks = { 'pocissue': ('https://github.com/VLSI-EDA/PoC/issues/%s', 'issue #'), 'pocpull': ('https://github.com/VLSI-EDA/PoC/pull/%s', 'pull request #'), @@ -363,4 +382,89 @@ def _LatestTagName(latestTagHash): 'poctb': ('https://github.com/VLSI-EDA/PoC/blob/master/tb/%s?ts=2', None) } + +# ============================================================================== +# Sphinx.Ext.Graphviz +# ============================================================================== graphviz_output_format = "svg" + + +# ============================================================================== +# Changelog +# ============================================================================== +# section names - optional +changelog_sections = ["general", "rendering", "tests"] + +# tags to sort on inside of sections - also optional +changelog_inner_tag_sort = ["feature", "bug"] + +# how to render changelog links - these are plain +# python string templates, ticket/pullreq/changeset number goes +# in "%s" +changelog_render_ticket = "http://bitbucket.org/myusername/myproject/issue/%s" +changelog_render_pullreq = "http://bitbucket.org/myusername/myproject/pullrequest/%s" +changelog_render_changeset = "http://bitbucket.org/myusername/myproject/changeset/%s" + + +# ============================================================================== +# SphinxContrib.Spelling +# ============================================================================== +# # String specifying the language, as understood by PyEnchant and enchant. +# # Defaults to en_US for US English. +# spelling_lang='en_US' +# +# # String specifying a file containing a list of words known to be spelled +# # correctly but that do not appear in the language dictionary selected by +# # spelling_lang. The file should contain one word per line. +# # Refer to the PyEnchant tutorial for details. +# #spelling_word_list_filename='spelling_wordlist.txt' +# +# # Boolean controlling whether suggestions for misspelled words are printed. +# # Defaults to False. +# spelling_show_suggestions=True +# +# # Boolean controlling whether words that look like package names from PyPI are +# # treated as spelled properly. When True, the current list of package names is +# # downloaded at the start of the build and used to extend the list of known +# # words in the dictionary. +# # Defaults to False. +# spelling_ignore_pypi_package_names=False +# +# # Boolean controlling whether words that follow the CamelCase conventions used +# # for page names in wikis should be treated as spelled properly. +# # Defaults to True. +# spelling_ignore_wiki_words=True +# +# # Boolean controlling treatment of words that appear in all capital letters, or +# # all capital letters followed by a lower case s. When True, acronyms are +# # assumed to be spelled properly. +# # Defaults to True. +# spelling_ignore_acronyms=True +# +# # Boolean controlling whether names built in to Python should be treated as +# # spelled properly. +# # Defaults to True. +# spelling_ignore_python_builtins=True +# +# # Boolean controlling whether words that are names of modules found on +# # sys.path are treated as spelled properly. +# # Defaults to True. +# spelling_ignore_importable_modules=True +# +# # List of filter classes to be added to the tokenizer that produces words to be +# # checked. The classes should be derived from enchant.tokenize.Filter. Refer to +# # the PyEnchant tutorial for examples. +# spelling_filters=[] + + +# ============================================================================== +# Custom changes +# ============================================================================== +def setup(app): + app.add_stylesheet('css/custom.css') + if tags.has('PoCInternal'): + app.add_config_value('visibility', 'PoCInternal', True) + print("="* 40) + else: + app.add_config_value('visibility', 'PoCExternal', True) + print("-"* 40) diff --git a/docs/index.rst b/docs/index.rst index d17792d1..49263291 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -3,13 +3,13 @@ and Architecture** - Faculty of Computer Science, Technische Universität Dresde Germany |br| `https://tu-dresden.de/ing/informatik/ti/vlsi `_ -.. image:: _static/logos/tu-dresden.jpg +.. image:: /_static/logos/tu-dresden.jpg :scale: 10 :alt: Technische Universität Dresden -------------------------------------------------------------------------------- -.. image:: _static/logos/GitHub-Mark-32px.png +.. image:: /_static/logos/GitHub-Mark-32px.png :scale: 60 :target: https://www.github.com/VLSI-EDA/PoC :alt: Source Code on GitHub @@ -120,5 +120,13 @@ This document was generated on |docdate|. :caption: Appendix :hidden: - Miscelaneous/ChangeLog + ChangeLog/index genindex + +.. ifconfig:: visibility in ('PoCInternal') + + .. toctree:: + :caption: Internal + :hidden: + + Internal/Sphinx diff --git a/docs/poc.py b/docs/poc.py index 7dc13022..96ca0510 100644 --- a/docs/poc.py +++ b/docs/poc.py @@ -115,9 +115,10 @@ def writeReST(self, sourceFile): # print(" Entity '{0}' at {1}..{2}.".format(sourceFile.EntityName, sourceFile.EntitySourceCodeRange.StartRow, sourceFile.EntitySourceCodeRange.EndRow)) if (sourceFile.SeeAlso != ""): - seeAlsoBox = ".. seealso::\n \n" + seeAlsoBox = ".. seealso::\n\n" for line in sourceFile.SeeAlso.splitlines(): - seeAlsoBox += " {line}\n".format(line=line) + if line == "": seeAlsoBox += "\n" + else: seeAlsoBox += " {line}\n".format(line=line) else: seeAlsoBox = "" diff --git a/lib/Altera.files b/lib/Altera.files index b143cd9b..178ee4cc 100644 --- a/lib/Altera.files +++ b/lib/Altera.files @@ -55,7 +55,7 @@ if (Tool = "GHDL") then report "No precompiled Altera primitives for GHDL found." end if elseif (Tool in ["Mentor_vSim", "Cocotb_QuestaSim"]) then - path Altera_Directory = (PreCompiled / (${CONFIG.DirectoryNames:ModelSimFiles} / ${CONFIG.DirectoryNames:AlteraSpecificFiles})) + path Altera_Directory = (PreCompiled / (${CONFIG.DirectoryNames:QuestaSimFiles} / ${CONFIG.DirectoryNames:AlteraSpecificFiles})) if ?{Altera_Directory} then library lpm Altera_Directory library sgate Altera_Directory diff --git a/lib/OSVVM.files b/lib/OSVVM.files index 6e398a8e..e7da9117 100644 --- a/lib/OSVVM.files +++ b/lib/OSVVM.files @@ -18,7 +18,7 @@ elseif (VHDLVersion = 2008) then report "No precompiled OSVVM library for GHDL found." end if elseif (Tool = "Mentor_vSim") then - path OSVVM_LibraryPath = (PreCompiled / (${CONFIG.DirectoryNames:ModelSimFiles} / OSVVM_Directory)) + path OSVVM_LibraryPath = (PreCompiled / (${CONFIG.DirectoryNames:QuestaSimFiles} / OSVVM_Directory)) if ?{OSVVM_LibraryPath} then library osvvm OSVVM_LibraryPath else diff --git a/lib/UVVM.files b/lib/UVVM.files index 85912955..2a74df50 100644 --- a/lib/UVVM.files +++ b/lib/UVVM.files @@ -37,7 +37,7 @@ elseif (VHDLVersion >= 2002) then report "No precompiled UVVM libraries for GHDL found." end if elseif (Tool = "Mentor_vSim") then - path UVVM_LibraryPath = (PreCompiled / (${CONFIG.DirectoryNames:ModelSimFiles} / UVVM_Directory)) + path UVVM_LibraryPath = (PreCompiled / (${CONFIG.DirectoryNames:QuestaSimFiles} / UVVM_Directory)) if ?{UVVM_LibraryPath} then library uvvm_util UVVM_LibraryPath library uvvm_vvc_framework UVVM_LibraryPath diff --git a/lib/Xilinx.files b/lib/Xilinx.files index a5e0008c..bd48ef83 100644 --- a/lib/Xilinx.files +++ b/lib/Xilinx.files @@ -47,7 +47,7 @@ if (Tool = "GHDL") then report "No precompiled Xilinx primitives for GHDL found." end if elseif (Tool in ["Mentor_vSim", "Cocotb_QuestaSim"]) then - path Xilinx_Directory = (PreCompiled / (${CONFIG.DirectoryNames:ModelSimFiles} / ${CONFIG.DirectoryNames:XilinxSpecificFiles})) + path Xilinx_Directory = (PreCompiled / (${CONFIG.DirectoryNames:QuestaSimFiles} / ${CONFIG.DirectoryNames:XilinxSpecificFiles})) if ?{Xilinx_Directory} then library unisim Xilinx_Directory library unimacro Xilinx_Directory diff --git a/py/Base/Compiler.py b/py/Base/Compiler.py index 92d8357d..3c9ba9f1 100644 --- a/py/Base/Compiler.py +++ b/py/Base/Compiler.py @@ -51,6 +51,9 @@ # required for autoapi.sphinx +from lib.SphinxExtensions import DocumentMemberAttribute + + __api__ = [ 'CompilerException', 'SkipableCompilerException', @@ -66,28 +69,34 @@ class CompilerException(ExceptionBase): - """Base exception for all CompilerExceptions.""" - pass + """Base class for all CompilerException classes. It is raised while running + compiler (synthesis) tasks in PoC. + """ class SkipableCompilerException(CompilerException, SkipableException): - """Base class for all skipable CompilerException.""" - pass + """``SkipableCompilerException`` is a :py:exc:`CompilerException`, which + can be skipped. + """ class CopyTask(CopyRuleMixIn): - """This class represents a 'copy task' and inherits the partial class :class:`Parser.RulesParser.CopyRuleMixIn`.""" - pass + """This class represents a 'copy task' and inherits the partial class + :class:`CopyRuleMixIn `. + """ class DeleteTask(DeleteRuleMixIn): - """This class represents a 'delete task' and inherits the partial class :class:`Parser.RulesParser.DeleteRuleMixIn`.""" - pass + """This class represents a 'delete task' and inherits the partial class + :class:`DeleteRuleMixIn `. + """ class ReplaceTask(ReplaceRuleMixIn): - """This class represents a 'replace task' and inherits the partial class :class:`Parser.RulesParser.ReplaceRuleMixIn`.""" - pass + """This class represents a 'replace task' and inherits the partial class + :class:`ReplaceRuleMixIn `. + """ class AppendLineTask(AppendLineRuleMixIn): - """This class represents a 'append line task' and inherits the partial class :class:`Parser.RulesParser.AppendLineRuleMixIn`.""" - pass + """This class represents a 'append line task' and inherits the partial class + :class:`AppendLineRuleMixIn `. + """ @unique @@ -138,16 +147,7 @@ class CompileResult(Enum): class Compiler(Shared): - """ - Base class for all Compiler classes. - - :type host: object - :param host: The hosting instance for this instance. - :type dryRun: bool - :param dryRun: Enable dry-run mode - :type noCleanUp: bool - :param noCleanUp: Don't clean up after a run. - """ + """Base class for all Compiler classes.""" _ENVIRONMENT = Environment.Synthesis _vhdlVersion = VHDLVersion.VHDL93 @@ -157,8 +157,17 @@ class __Directories__(Shared.__Directories__): Source = None Destination = None + @DocumentMemberAttribute() def __init__(self, host, dryRun, noCleanUp): - """Constructur""" + """Class initializer + + :type host: object + :param host: The hosting instance for this instance. + :type dryRun: bool + :param dryRun: Enable dry-run mode + :type noCleanUp: bool + :param noCleanUp: Don't clean up after a run. + """ super().__init__(host, dryRun) self._noCleanUp = noCleanUp @@ -173,8 +182,9 @@ def __init__(self, host, dryRun, noCleanUp): def NoCleanUp(self): return self._noCleanUp def _PrepareCompiler(self): - """Prepare for compilation. This method forwards to :py:meth:`Base.Compiler.Compiler._Prepare`, which is un herited from:py:class:`Base.Shared.Shared`.""" - self._Prepare() + """Prepare for compilation. This method forwards to :py:meth:`Base.Compiler.Compiler._Prepare`, + which is inherited from :py:class:`Base.Shared.Shared`. + """ def TryRun(self, netlist, *args, **kwargs): """Try to run a testbench. Skip skipable exceptions by printing the error and its cause.""" diff --git a/py/Base/Configuration.py b/py/Base/Configuration.py index a05dc9f2..333fcbde 100644 --- a/py/Base/Configuration.py +++ b/py/Base/Configuration.py @@ -46,10 +46,17 @@ class ConfigurationException(ExceptionBase): - pass + """``ConfigurationException`` is raise while running configuration or database + tasks in PoC + """ class SkipConfigurationException(ExceptionBase): - pass + """``SkipConfigurationException`` is a :py:exc:`ConfigurationException`, + which can be skipped. + """ + + + # class RegisterSubClassesMeta(type): # def __new__(mcs, name, bases, members): @@ -77,6 +84,7 @@ class SkipConfigurationException(ExceptionBase): # return self._subclasses class Configuration: #(ISubClassRegistration): + """base class for all Configuration classes.""" _vendor = "Unknown" _toolName = "Unknown" _section = "ERROR" @@ -229,7 +237,9 @@ def _GetDefaultVersion(self): return self._template[self._host.Platform][self._section]['Version'] def _ConfigureBinaryDirectory(self): - """Updates section with value from _template and returns directory as Path object.""" + """Updates section with value from :attr:`_template` and returns directory + as :class:`Path ` object. + """ unresolved = self._template[self._host.Platform][self._section]['BinaryDirectory'] self._host.PoCConfig[self._section]['BinaryDirectory'] = unresolved # create entry defaultPath = Path(self._host.PoCConfig[self._section]['BinaryDirectory']) # resolve entry @@ -243,5 +253,5 @@ def _ConfigureBinaryDirectory(self): return binPath def RunPostConfigurationTasks(self): - """Virtual method. Overwrite to execute post-configuration tasks""" + """Virtual method. Overwrite to execute post-configuration tasks.""" pass diff --git a/py/Base/Exceptions.py b/py/Base/Exceptions.py index 1a1d8bef..623371f4 100644 --- a/py/Base/Exceptions.py +++ b/py/Base/Exceptions.py @@ -31,6 +31,9 @@ # limitations under the License. # ============================================================================== # +from lib.SphinxExtensions import DocumentMemberAttribute + + __api__ = [ 'ExceptionBase', 'EnvironmentException', @@ -44,27 +47,50 @@ class ExceptionBase(Exception): + """Base exception derived from :py:exc:`Exception` for all + custom exceptions in PoC. + """ + @DocumentMemberAttribute() def __init__(self, message=""): + """Exception initializer + + :type message: str + :param message: The exception message. + """ super().__init__() self.message = message + @DocumentMemberAttribute() def __str__(self): + """Returns the exception's message text.""" return self.message + # @DocumentMemberAttribute(False) + # @MethodAlias(Exception.with_traceback) + # def with_traceback(self): pass + class EnvironmentException(ExceptionBase): - pass + """``EnvironmentException`` is raised when an expected environment variable is + missing for PoC. + """ class PlatformNotSupportedException(ExceptionBase): - pass + """``PlatformNotSupportedException`` is raise if the platform is not supported + by PoC, or the selected tool flow is not supported on the host system by PoC. + """ class NotConfiguredException(ExceptionBase): - pass + """``NotConfiguredException`` is raise if PoC or the requested tool chain + setting is not configured in PoC. + """ class SkipableException(ExceptionBase): - pass + """Base class for all skipable exceptions.""" class CommonException(ExceptionBase): pass class SkipableCommonException(CommonException, SkipableException): - pass + """``SkipableCommonException`` is a :py:exc:`CommonException`, which can be + skipped. + """ diff --git a/py/Base/Project.py b/py/Base/Project.py index e2ce7d23..bdd6f701 100644 --- a/py/Base/Project.py +++ b/py/Base/Project.py @@ -127,11 +127,13 @@ class Tool(Enum): # ID Short Name Long Name Any = 0 Aldec_aSim = ("ASIM", "Aldec Active-HDL", "Aldec Active-HDL") Altera_Quartus_Map = ("QMAP", "Quartus Map", "Altera Quartus Map (quartus_map)") + # ModelSim Altera Edition? Cocotb_QuestaSim = ("COCO", "Cocotb", "Coroutine Cosimulation Testbench (Cocotb)") GHDL = ("GHDL", "GHDL", "GHDL") GTKwave = ("GTKW", "GTKWave", "GTKWave") Lattice_LSE = ("LSE", "Lattice LSE", "Lattice Synthesis Engine (LSE)") Mentor_vSim = ("VSIM", "Mentor QuestaSim", "Mentor Graphics QuestaSim (vSim)") + # Mentor ModelSim? Xilinx_iSim = ("XSIM", "Xilinx iSim", "Xilinx ISE Simulator (iSim)") Xilinx_XST = ("XST", "Xilinx XST", "Xilinx Synthesis Tool (XST)") Xilinx_CoreGen = ("CG", "Xilinx CoreGen", "Xilinx Core Generator Tool (CoreGen)") diff --git a/py/Base/Simulator.py b/py/Base/Simulator.py index 10f84814..1095515f 100644 --- a/py/Base/Simulator.py +++ b/py/Base/Simulator.py @@ -49,6 +49,9 @@ # required for autoapi.sphinx +from lib.SphinxExtensions import DocumentMemberAttribute + + __api__ = [ 'SimulatorException', 'SkipableSimulatorException', @@ -66,16 +69,19 @@ class SimulatorException(ExceptionBase): - """Base class for all SimulatorExceptions.""" - pass + """Base class for all SimulatorException classes. It is raised while running + simulation tasks in PoC. + """ class SkipableSimulatorException(SimulatorException, SkipableException): - """Base class for all skipable SimulatorExceptions.""" - pass + """``SkipableSimulatorException`` is a :py:exc:`SimulatorException`, which + can be skipped. + """ class PoCSimulationResultNotFoundException(SkipableSimulatorException): - """This exception is raised if the expected PoC simulation result string was not found in the simulator's output.""" - pass + """This exception is raised if the expected PoC simulation result string was + not found in the simulator's output. + """ @unique @@ -123,16 +129,7 @@ class SimulationResult(Enum): class Simulator(Shared): - """ - Base class for all Simulator classes. - - :type host: object - :param host: The hosting instance for this instance. - :type dryRun: bool - :param dryRun: Enable dry-run mode - :type noCleanUp: bool - :param noCleanUp: Don't clean up after a run. - """ + """Base class for all Simulator classes.""" _ENVIRONMENT = Environment.Simulation _vhdlVersion = VHDLVersion.VHDL2008 @@ -140,7 +137,17 @@ class Simulator(Shared): class __Directories__(Shared.__Directories__): PreCompiled = None + @DocumentMemberAttribute() def __init__(self, host, dryRun, simulationSteps : SimulationSteps): + """Class initializer + + :type host: object + :param host: The hosting instance for this instance. + :type dryRun: bool + :param dryRun: Enable dry-run mode + :type simulationSteps: SimulationSteps + :param simulationSteps: A set of simulation step to precess. + """ super().__init__(host, dryRun) self._simulationSteps = simulationSteps diff --git a/py/PoC.py b/py/PoC.py index bd005bc8..ba0f4737 100644 --- a/py/PoC.py +++ b/py/PoC.py @@ -90,7 +90,6 @@ 'PoCEntityAttribute', 'BoardDeviceAttributeGroup', 'VHDLVersionAttribute', - 'GUIModeAttribute', 'SimulationStepsAttribute', 'CompileStepsAttribute', 'PileOfCores', @@ -99,7 +98,6 @@ __all__ = __api__ - class PoCEntityAttribute(Attribute): def __call__(self, func): self._AppendAttribute(func, ArgumentAttribute(metavar="PoC Entity", dest="FQN", type=str, nargs='+', help="A space separated list of PoC entities.")) @@ -446,8 +444,6 @@ def HandleConfiguration(self, args): nxt = True except SkipConfigurationException: break - except ConfigurationException: - raise except ExceptionBase as ex: print(" {RED}FAULT:{NOCOLOR} {0}".format(ex.message, **Init.Foreground)) @@ -468,7 +464,7 @@ def _InitializeConfiguration(self): self.__pocConfig[sectionName] = OrderedDict() def __UpdateConfiguration(self): - pocSections = set([sectionName for sectionName in self.__pocConfig]) + pocSections = set([sectionName for sectionName in self.__pocConfig]) configSections = set([sectionName for config in Configurations for sectionName in config.GetSections(self.Platform)]) addSections = configSections.difference(pocSections) @@ -488,7 +484,9 @@ def __UpdateConfiguration(self): # create the sub-parser for the "add-solution" command # ---------------------------------------------------------------------------- @CommandGroupAttribute("Configuration commands") - @CommandAttribute("add-solution", help="Add a solution to PoC.") + @CommandAttribute("add-solution", help="Add a solution to PoC.", description=dedent("""\ + Add a solution to PoC. + """)) def HandleAddSolution(self, _): #args self.PrintHeadline() self.__PrepareForConfiguration() @@ -499,7 +497,7 @@ def HandleAddSolution(self, _): #args solutionID = input(" Solution id: ") if (solutionID == ""): raise ConfigurationException("Empty input. Aborting!") - if (solutionID in self.__repo): raise ConfigurationException("Solution ID is already used.") + if (solutionID in self.__repo): raise ConfigurationException("Solution ID is already used.") solutionRootPath = input(" Solution path: ") if (solutionRootPath == ""): raise ConfigurationException("Empty input. Aborting!") @@ -527,7 +525,9 @@ def HandleAddSolution(self, _): #args # create the sub-parser for the "list-solution" command # ---------------------------------------------------------------------------- @CommandGroupAttribute("Configuration commands") - @CommandAttribute("list-solution", help="List all solutions registered in PoC.") + @CommandAttribute("list-solution", help="List all solutions registered in PoC.", description=dedent("""\ + List all solutions registered in PoC. + """)) def HandleListSolution(self, _): #args self.PrintHeadline() self.__PrepareForConfiguration() @@ -548,7 +548,9 @@ def HandleListSolution(self, _): #args # create the sub-parser for the "remove-solution" command # ---------------------------------------------------------------------------- @CommandGroupAttribute("Configuration commands") - @CommandAttribute("remove-solution", help="Add a solution to PoC.") + @CommandAttribute("remove-solution", help="Remove a solution from PoC.", description=dedent("""\ + Remove a solution from PoC. + """)) @ArgumentAttribute(metavar="SolutionID", dest="SolutionID", type=str, help="Solution name.") def HandleRemoveSolution(self, args): self.PrintHeadline() @@ -583,7 +585,9 @@ def HandleRemoveSolution(self, args): # create the sub-parser for the "list-project" command # ---------------------------------------------------------------------------- @CommandGroupAttribute("Configuration commands") - @CommandAttribute("list-project", help="List all projects registered in PoC.") + @CommandAttribute("list-project", help="List all projects registered in PoC.", description=dedent("""\ + List all projects registered in PoC. + """)) def HandleListProject(self, args): self.PrintHeadline() self.__PrepareForConfiguration() @@ -668,7 +672,9 @@ def HandleListProject(self, args): # create the sub-parser for the "query" command # ---------------------------------------------------------------------------- @CommandGroupAttribute("Configuration commands") - @CommandAttribute("query", help="Simulate a PoC Entity with Aldec Active-HDL") + @CommandAttribute("query", help="Query PoC's database.", description=dedent("""\ + Query PoC's database. + """)) @ArgumentAttribute(metavar="Query", dest="Query", type=str, help="todo help") def HandleQueryConfiguration(self, args): self.__PrepareForConfiguration() @@ -759,7 +765,9 @@ def _ExtractSimulationSteps(guiMode, analyze, elaborate, optimize, recompile, si # create the sub-parser for the "list-testbench" command # ---------------------------------------------------------------------------- @CommandGroupAttribute("Simulation commands") # mccabe:disable=MC0001 - @CommandAttribute("list-testbench", help="List all testbenches") + @CommandAttribute("list-testbench", help="List all testbenches.", description=dedent("""\ + List all testbenches. + """)) @PoCEntityAttribute() @ArgumentAttribute("--kind", metavar="Kind", dest="TestbenchKind", help="Testbench kind: VHDL | COCOTB") def HandleListTestbenches(self, args): @@ -841,7 +849,9 @@ def HandleListTestbenches(self, args): # create the sub-parser for the "asim" command # ---------------------------------------------------------------------------- @CommandGroupAttribute("Simulation commands") - @CommandAttribute("asim", help="Simulate a PoC Entity with Aldec Active-HDL") + @CommandAttribute("asim", help="Simulate a PoC Entity with Aldec Active-HDL.", description=dedent("""\ + Simulate a PoC Entity with Aldec Active-HDL. + """)) @PoCEntityAttribute() @BoardDeviceAttributeGroup() @VHDLVersionAttribute() @@ -866,7 +876,9 @@ def HandleActiveHDLSimulation(self, args): # create the sub-parser for the "ghdl" command # ---------------------------------------------------------------------------- @CommandGroupAttribute("Simulation commands") - @CommandAttribute("ghdl", help="Simulate a PoC Entity with GHDL") + @CommandAttribute("ghdl", help="Simulate a PoC Entity with GHDL.", description=dedent("""\ + Simulate a PoC Entity with GHDL. + """)) @PoCEntityAttribute() @BoardDeviceAttributeGroup() @VHDLVersionAttribute() @@ -895,7 +907,9 @@ def HandleGHDLSimulation(self, args): # create the sub-parser for the "isim" command # ---------------------------------------------------------------------------- @CommandGroupAttribute("Simulation commands") - @CommandAttribute("isim", help="Simulate a PoC Entity with Xilinx ISE Simulator (iSim)") + @CommandAttribute("isim", help="Simulate a PoC Entity with Xilinx ISE Simulator (iSim).", description=dedent("""\ + Simulate a PoC Entity with Xilinx ISE Simulator (iSim). + """)) @PoCEntityAttribute() @BoardDeviceAttributeGroup() @SimulationStepsAttribute() @@ -918,7 +932,9 @@ def HandleISESimulation(self, args): # create the sub-parser for the "vsim" command # ---------------------------------------------------------------------------- @CommandGroupAttribute("Simulation commands") - @CommandAttribute("vsim", help="Simulate a PoC Entity with Mentor QuestaSim or ModelSim (vsim)") + @CommandAttribute("vsim", help="Simulate a PoC Entity with Mentor QuestaSim or ModelSim (vsim).", description=dedent("""\ + Simulate a PoC Entity with Mentor QuestaSim or ModelSim (vsim). + """)) @PoCEntityAttribute() @BoardDeviceAttributeGroup() @VHDLVersionAttribute() @@ -944,7 +960,9 @@ def HandleQuestaSimulation(self, args): # create the sub-parser for the "xsim" command # ---------------------------------------------------------------------------- @CommandGroupAttribute("Simulation commands") - @CommandAttribute("xsim", help="Simulate a PoC Entity with Xilinx Vivado Simulator (xSim)") + @CommandAttribute("xsim", help="Simulate a PoC Entity with Xilinx Vivado Simulator (xSim).", description=dedent("""\ + Simulate a PoC Entity with Xilinx Vivado Simulator (xSim). + """)) @PoCEntityAttribute() @BoardDeviceAttributeGroup() @VHDLVersionAttribute() @@ -971,7 +989,9 @@ def HandleVivadoSimulation(self, args): # create the sub-parser for the "cocotb" command # ---------------------------------------------------------------------------- @CommandGroupAttribute("Simulation commands") - @CommandAttribute("cocotb", help="Simulate a PoC Entity with Cocotb and Questa Simulator") + @CommandAttribute("cocotb", help="Simulate a PoC Entity with Cocotb and QuestaSim.", description=dedent("""\ + Simulate a PoC Entity with Cocotb and QuestaSim. + """)) @PoCEntityAttribute() @BoardDeviceAttributeGroup() @SimulationStepsAttribute() @@ -982,7 +1002,7 @@ def HandleCocotbSimulation(self, args): # check if QuestaSim is configured if (len(self.PoCConfig.options("INSTALL.Mentor.QuestaSim")) == 0): if (len(self.PoCConfig.options("INSTALL.Altera.ModelSim")) == 0): - raise NotConfiguredException("Neither Mentor QuestaSim nor Altera ModelSim is not configured on this system.") + raise NotConfiguredException("Neither Mentor QuestaSim, Mentor ModelSimPE nor ModelSim Altera Edition are configured on this system.") fqnList = self._ExtractFQNs(args.FQN) board = self._ExtractBoard(args.BoardName, args.DeviceName) @@ -1001,7 +1021,9 @@ def HandleCocotbSimulation(self, args): # create the sub-parser for the "list-netlist" command # ---------------------------------------------------------------------------- @CommandGroupAttribute("Simulation commands") - @CommandAttribute("list-netlist", help="List all netlists") + @CommandAttribute("list-netlist", help="List all netlists.", description=dedent("""\ + List all netlists. + """)) @PoCEntityAttribute() @ArgumentAttribute("--kind", metavar="Kind", dest="NetlistKind", help="Netlist kind: Lattice | Quartus | XST | CoreGen") def HandleListNetlist(self, args): @@ -1036,7 +1058,9 @@ def HandleListNetlist(self, args): # create the sub-parser for the "ise" command # ---------------------------------------------------------------------------- @CommandGroupAttribute("Synthesis commands") - @CommandAttribute("ise", help="Generate any IP core for the Xilinx ISE tool chain") + @CommandAttribute("ise", help="Generate any IP core for the Xilinx ISE tool chain.", description=dedent("""\ + Generate any IP core for the Xilinx ISE tool chain. + """)) @PoCEntityAttribute() @BoardDeviceAttributeGroup() @CompileStepsAttribute() @@ -1057,7 +1081,9 @@ def HandleISECompilation(self, args): # create the sub-parser for the "coregen" command # ---------------------------------------------------------------------------- @CommandGroupAttribute("Synthesis commands") - @CommandAttribute("coregen", help="Generate an IP core with Xilinx ISE Core Generator") + @CommandAttribute("coregen", help="Generate an IP core with Xilinx ISE Core Generator.", description=dedent("""\ + Generate an IP core with Xilinx ISE Core Generator. + """)) @PoCEntityAttribute() @BoardDeviceAttributeGroup() @CompileStepsAttribute() @@ -1078,7 +1104,11 @@ def HandleCoreGeneratorCompilation(self, args): # create the sub-parser for the "xst" command # ---------------------------------------------------------------------------- @CommandGroupAttribute("Synthesis commands") - @CommandAttribute("xst", help="Compile a PoC IP core with Xilinx ISE XST to a netlist") + @CommandAttribute("xst", help="Compile a PoC IP core with Xilinx ISE XST to a netlist.", description=dedent("""\ + Compile a PoC IP core with Xilinx ISE XST to a netlist. + :ref:`IP:PoC.Mem` + foooo baaarr. + """)) @PoCEntityAttribute() @BoardDeviceAttributeGroup() @CompileStepsAttribute() @@ -1099,7 +1129,9 @@ def HandleXstCompilation(self, args): # create the sub-parser for the "xci" command # ---------------------------------------------------------------------------- @CommandGroupAttribute("Synthesis commands") - @CommandAttribute("xci", help="Generate an IP core from Xilinx Vivado IP Catalog") + @CommandAttribute("xci", help="Generate an IP core from Xilinx Vivado IP Catalog.", description=dedent("""\ + Generate an IP core from Xilinx Vivado IP Catalog. + """)) @PoCEntityAttribute() @BoardDeviceAttributeGroup() @CompileStepsAttribute() @@ -1120,7 +1152,9 @@ def HandleIpCatalogCompilation(self, args): # create the sub-parser for the "vivado" command # ---------------------------------------------------------------------------- @CommandGroupAttribute("Synthesis commands") - @CommandAttribute("vivado", help="Compile a PoC IP core with Xilinx Vivado Synth to a design checkpoint") + @CommandAttribute("vivado", help="Compile a PoC IP core with Xilinx Vivado Synth to a design checkpoint.", description=dedent("""\ + Compile a PoC IP core with Xilinx Vivado Synth to a design checkpoint. + """)) @PoCEntityAttribute() @BoardDeviceAttributeGroup() @CompileStepsAttribute() @@ -1142,7 +1176,9 @@ def HandleVivadoCompilation(self, args): # create the sub-parser for the "quartus" command # ---------------------------------------------------------------------------- @CommandGroupAttribute("Synthesis commands") - @CommandAttribute("quartus", help="Compile a PoC IP core with Altera Quartus II Map to a netlist") + @CommandAttribute("quartus", help="Compile a PoC IP core with Altera Quartus II Map to a netlist.", description=dedent("""\ + Compile a PoC IP core with Altera Quartus II Map to a netlist. + """)) @PoCEntityAttribute() @BoardDeviceAttributeGroup() @CompileStepsAttribute() @@ -1166,7 +1202,9 @@ def HandleQuartusCompilation(self, args): # create the sub-parser for the "lattice" command # ---------------------------------------------------------------------------- @CommandGroupAttribute("Synthesis commands") - @CommandAttribute("lse", help="Compile a PoC IP core with Lattice Diamond LSE to a netlist") + @CommandAttribute("lse", help="Compile a PoC IP core with Lattice Diamond LSE to a netlist.", description=dedent("""\ + Compile a PoC IP core with Lattice Diamond LSE to a netlist. + """)) @PoCEntityAttribute() @BoardDeviceAttributeGroup() @CompileStepsAttribute() diff --git a/py/Simulator/QuestaSimulator.py b/py/Simulator/QuestaSimulator.py index 7094c980..0f19f039 100644 --- a/py/Simulator/QuestaSimulator.py +++ b/py/Simulator/QuestaSimulator.py @@ -31,15 +31,12 @@ # ============================================================================== # # load dependencies -from datetime import datetime from pathlib import Path from textwrap import dedent -from lib.Functions import Init from Base.Exceptions import NotConfiguredException from Base.Project import FileTypes, ToolChain, Tool -from Base.Simulator import SimulatorException, Simulator as BaseSimulator, VHDL_TESTBENCH_LIBRARY_NAME, SkipableSimulatorException, SimulationState, SimulationResult, \ - SimulationSteps +from Base.Simulator import SimulatorException, Simulator as BaseSimulator, VHDL_TESTBENCH_LIBRARY_NAME, SkipableSimulatorException, SimulationSteps from DataBase.Config import Vendors from ToolChains.Mentor.QuestaSim import QuestaSim, QuestaSimException @@ -77,12 +74,12 @@ def __init__(self, host, dryRun, simulationSteps): def _PrepareSimulator(self): # create the QuestaSim executable factory self.LogVerbose("Preparing Mentor simulator.") - for sectionName in ['INSTALL.Mentor.QuestaSim', 'INSTALL.Altera.ModelSim']: + for sectionName in ['INSTALL.Mentor.QuestaSim', 'INSTALL.Mentor.ModelSimPE', 'INSTALL.Altera.ModelSim']: if (len(self.Host.PoCConfig.options(sectionName)) != 0): break else: raise NotConfiguredException( - "Neither Mentor Graphics QuestaSim nor ModelSim Altera-Edition are configured on this system.") + "Neither Mentor Graphics QuestaSim, ModelSim PE nor ModelSim Altera-Edition are configured on this system.") questaSection = self.Host.PoCConfig[sectionName] binaryPath = Path(questaSection['BinaryDirectory']) @@ -276,7 +273,7 @@ def _RunSimulationWithGUI(self, testbench): puts "Loading run script '{runScript}'..." do {runScript} """).format( - recompileScript=recompileScriptPath.as_posix(), + recompileScript=recompileScriptPath.as_posix(), runScript=vsimRunScript ) diff --git a/py/ToolChains/Aldec/ActiveHDL.py b/py/ToolChains/Aldec/ActiveHDL.py index eb9a1af4..f65241b6 100644 --- a/py/ToolChains/Aldec/ActiveHDL.py +++ b/py/ToolChains/Aldec/ActiveHDL.py @@ -35,6 +35,7 @@ # entry point from subprocess import check_output +from ToolChains import ToolMixIn from lib.Functions import CallByRefParam from Base.Exceptions import PlatformNotSupportedException from Base.Logging import LogEntry, Severity @@ -49,7 +50,6 @@ __api__ = [ 'ActiveHDLException', 'Configuration', - 'ActiveHDLMixIn', 'ActiveHDL', 'VHDLCompiler', 'StandaloneSimulator', @@ -119,36 +119,26 @@ def __CheckActiveHDLVersion(self, binPath, version): raise ConfigurationException("Active-HDL version mismatch. Expected version {0}.".format(version)) -class ActiveHDLMixIn: - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - self._platform = platform - self._dryrun = dryrun - self._binaryDirectoryPath = binaryDirectoryPath - self._version = version - self._Logger = logger - - -class ActiveHDL(ActiveHDLMixIn): - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - ActiveHDLMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) - +class ActiveHDL(ToolMixIn): def GetVHDLLibraryTool(self): - return ActiveHDLVHDLLibraryTool(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) + return ActiveHDLVHDLLibraryTool(self) def GetVHDLCompiler(self): - return VHDLCompiler(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) + return VHDLCompiler(self) def GetSimulator(self): - return StandaloneSimulator(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) + return StandaloneSimulator(self) -class VHDLCompiler(Executable, ActiveHDLMixIn): - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - ActiveHDLMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger=logger) - if (self._platform == "Windows"): executablePath = binaryDirectoryPath / "vcom.exe" - # elif (self._platform == "Linux"): executablePath = binaryDirectoryPath / "vcom" - else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, dryrun, executablePath, logger=logger) +class VHDLCompiler(Executable, ToolMixIn): + def __init__(self, toolchain : ToolMixIn): + ToolMixIn.__init__( + self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, + toolchain._Logger) + + if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "vcom.exe" + else: raise PlatformNotSupportedException(self._platform) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) self._hasOutput = False self._hasWarnings = False @@ -239,13 +229,15 @@ def Compile(self): self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) -class StandaloneSimulator(Executable, ActiveHDLMixIn): - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - ActiveHDLMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger=logger) - if (self._platform == "Windows"): executablePath = binaryDirectoryPath / "vsimsa.exe" - # elif (self._platform == "Linux"): executablePath = binaryDirectoryPath / "vsimsa" - else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, dryrun, executablePath, logger=logger) +class StandaloneSimulator(Executable, ToolMixIn): + def __init__(self, toolchain : ToolMixIn): + ToolMixIn.__init__( + self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, + toolchain._Logger) + + if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "vsimsa.exe" + else: raise PlatformNotSupportedException(self._platform) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) self._hasOutput = False self._hasWarnings = False @@ -312,9 +304,9 @@ def Simulate(self): return simulationResult.value -class Simulator(Executable, ActiveHDLMixIn): +class Simulator(Executable, ToolMixIn): def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - ActiveHDLMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger=logger) + ToolMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger=logger) if (self._platform == "Windows"): executablePath = binaryDirectoryPath / "vsimsa.exe" # elif (self._platform == "Linux"): executablePath = binaryDirectoryPath / "vsimsa" else: raise PlatformNotSupportedException(self._platform) @@ -378,13 +370,15 @@ def Simulate(self): print(_indent + "-" * 80) -class ActiveHDLVHDLLibraryTool(Executable, ActiveHDLMixIn): - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - ActiveHDLMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger=logger) - if (self._platform == "Windows"): executablePath = binaryDirectoryPath / "vlib.exe" - # elif (self._platform == "Linux"): executablePath = binaryDirectoryPath / "vlib" - else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, dryrun, executablePath, logger=logger) +class ActiveHDLVHDLLibraryTool(Executable, ToolMixIn): + def __init__(self, toolchain : ToolMixIn): + ToolMixIn.__init__( + self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, + toolchain._Logger) + + if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "vlib.exe" + else: raise PlatformNotSupportedException(self._platform) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) self._hasOutput = False self._hasWarnings = False diff --git a/py/ToolChains/Aldec/Aldec.py b/py/ToolChains/Aldec/Aldec.py index 50fb7e0b..22147bf0 100644 --- a/py/ToolChains/Aldec/Aldec.py +++ b/py/ToolChains/Aldec/Aldec.py @@ -60,7 +60,7 @@ class Configuration(BaseConfiguration): }, "Linux": { _section: { - # "InstallationDirectory": "/opt/Aldec" + "InstallationDirectory": "/opt/Aldec" } } } diff --git a/py/ToolChains/Altera/ModelSim.py b/py/ToolChains/Altera/ModelSim.py index 5d4e16be..283bd02c 100644 --- a/py/ToolChains/Altera/ModelSim.py +++ b/py/ToolChains/Altera/ModelSim.py @@ -34,11 +34,12 @@ # ============================================================================== # # load dependencies -from re import compile as RegExpCompile -from subprocess import check_output +from re import compile as RegExpCompile +from subprocess import check_output -from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException -from ToolChains.Altera.Altera import AlteraException +from Base.Configuration import ConfigurationException +from ToolChains.Mentor.ModelSimPE import Configuration as ModelSimPE_Configuration +from ToolChains.Altera.Altera import AlteraException __api__ = [ @@ -52,10 +53,10 @@ class ModelSimException(AlteraException): pass -class Configuration(BaseConfiguration): +class Configuration(ModelSimPE_Configuration): _vendor = "Altera" _toolName = "ModelSim Altera Edition" - _section = "INSTALL.Altera.ModelSim" + _section = "INSTALL.Altera.ModelSim" _template = { "Windows": { _section: { diff --git a/py/ToolChains/Altera/Quartus.py b/py/ToolChains/Altera/Quartus.py index c696fb8b..e647c786 100644 --- a/py/ToolChains/Altera/Quartus.py +++ b/py/ToolChains/Altera/Quartus.py @@ -42,13 +42,14 @@ from Base.Executable import Executable, CommandLineArgumentList from Base.Executable import ExecutableArgument, ShortValuedFlagArgument, LongValuedFlagArgument, StringArgument, ShortFlagArgument from Base.Project import Project as BaseProject, ProjectFile, FileTypes, SettingsFile +from ToolChains import ToolMixIn from ToolChains.Altera.Altera import AlteraException __api__ = [ 'QuartusException', 'Configuration', - 'QuartusMixIn', + 'ToolMixIn', 'Quartus', 'Map', 'TclShell', @@ -118,34 +119,24 @@ def __CheckQuartusVersion(self, binPath, version): raise ConfigurationException("Quartus version mismatch. Expected version {0}.".format(version)) -class QuartusMixIn: - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - self._platform = platform - self._dryrun = dryrun - self._binaryDirectoryPath = binaryDirectoryPath - self._version = version - self._Logger = logger - - -class Quartus(QuartusMixIn): - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - QuartusMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) - +class Quartus(ToolMixIn): def GetMap(self): - return Map(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) + return Map(self) def GetTclShell(self): - return TclShell(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) + return TclShell(self) -class Map(Executable, QuartusMixIn): - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - QuartusMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) +class Map(Executable, ToolMixIn): + def __init__(self, toolchain : ToolMixIn): + ToolMixIn.__init__( + self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, + toolchain._Logger) - if (platform == "Windows") : executablePath = binaryDirectoryPath / "quartus_map.exe" - elif (platform == "Linux") : executablePath = binaryDirectoryPath / "quartus_map" - else : raise PlatformNotSupportedException(platform) - Executable.__init__(self, platform, dryrun, executablePath, logger=logger) + if (self._platform == "Windows") : executablePath = self._binaryDirectoryPath / "quartus_map.exe" + elif (self._platform == "Linux") : executablePath = self._binaryDirectoryPath / "quartus_map" + else : raise PlatformNotSupportedException(self._platform) + Executable.__init__(self, self._platform, self._dryrun, executablePath, logger=self._Logger) self.Parameters[self.Executable] = executablePath @@ -220,14 +211,16 @@ def Compile(self) : self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) -class TclShell(Executable, QuartusMixIn): - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - QuartusMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) +class TclShell(Executable, ToolMixIn): + def __init__(self, toolchain : ToolMixIn): + ToolMixIn.__init__( + self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, + toolchain._Logger) - if (platform == "Windows") : executablePath = binaryDirectoryPath / "quartus_sh.exe" - elif (platform == "Linux") : executablePath = binaryDirectoryPath / "quartus_sh" - else : raise PlatformNotSupportedException(platform) - super().__init__(platform, dryrun, executablePath, logger=logger) + if (self._platform == "Windows") : executablePath = self._binaryDirectoryPath / "quartus_sh.exe" + elif (self._platform == "Linux") : executablePath = self._binaryDirectoryPath / "quartus_sh" + else : raise PlatformNotSupportedException(self._platform) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) self.Parameters[self.Executable] = executablePath diff --git a/py/ToolChains/Git.py b/py/ToolChains/Git.py index b94600bd..2512f47e 100644 --- a/py/ToolChains/Git.py +++ b/py/ToolChains/Git.py @@ -45,6 +45,33 @@ from Base.Executable import Executable, ExecutableArgument, CommandLineArgumentList, CommandArgument, LongFlagArgument, ValuedFlagArgument, StringArgument, \ LongValuedFlagArgument, LongTupleArgument from Base.ToolChain import ToolChainException +from ToolChains import ToolMixIn + +__api__ = [ + 'GitException', + 'Configuration', + 'Git', + 'GitSCM', + 'GitRevParse', + 'GitRevList', + 'GitDescribe', + 'GitConfig' +] +__all__ = __api__ + + +__api__ = [ + 'GitException', + 'Configuration', + 'GitMixIn', + 'Git', + 'GitSCM', + 'GitRevParse', + 'GitRevList', + 'GitDescribe', + 'GitConfig' +] +__all__ = __api__ __api__ = [ @@ -110,7 +137,7 @@ def ConfigureForAll(self): try: binaryDirectoryPath = binPath - self._git = Git(self._host.Platform, self._host.DryRun, binaryDirectoryPath, logger=self._host.Logger) + self._git = Git(self._host.Platform, self._host.DryRun, binaryDirectoryPath, "", logger=self._host.Logger) except Exception as ex: self._host.LogWarning(str(ex)) @@ -318,54 +345,47 @@ def __GetGitDirectory(self): return gitDirectoryPath -class GitMixIn: - def __init__(self, platform, dryrun, binaryDirectoryPath, logger=None): - self._platform = platform - self._dryrun = dryrun - self._binaryDirectoryPath = binaryDirectoryPath - # self._version = version - self._Logger = logger - - -class Git(GitMixIn): +class Git(ToolMixIn): def GetGitRevParse(self): - git = GitRevParse(self._platform, self._dryrun, self._binaryDirectoryPath, logger=self._Logger) + git = GitRevParse(self) git.Clear() git.RevParseParameters[GitRevParse.Command] = True return git def GetGitRevList(self): - git = GitRevList(self._platform, self._dryrun, self._binaryDirectoryPath, logger=self._Logger) + git = GitRevList(self) git.Clear() git.RevListParameters[GitRevList.Command] = True return git def GetGitDescribe(self): - git = GitDescribe(self._platform, self._dryrun, self._binaryDirectoryPath, logger=self._Logger) + git = GitDescribe(self) git.Clear() git.DescribeParameters[GitDescribe.Command] = True return git def GetGitConfig(self): - git = GitConfig(self._platform, self._dryrun, self._binaryDirectoryPath, logger=self._Logger) + git = GitConfig(self) git.Clear() git.ConfigParameters[GitConfig.Command] = True return git -class GitSCM(Executable, GitMixIn): - def __init__(self, platform, dryrun, binaryDirectoryPath, logger=None): - GitMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, logger=logger) +class GitSCM(Executable, ToolMixIn): + def __init__(self, toolchain : ToolMixIn): + ToolMixIn.__init__( + self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, + toolchain._Logger) - if (platform == "Windows"): executablePath = binaryDirectoryPath / "git.exe" - elif (platform == "Linux"): executablePath = binaryDirectoryPath / "git" - elif (platform == "Darwin"): executablePath = binaryDirectoryPath / "git" - else: raise PlatformNotSupportedException(platform) - super().__init__(platform, dryrun, executablePath, logger=logger) + if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "git.exe" + elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "git" + elif (self._platform == "Darwin"): executablePath = self._binaryDirectoryPath / "git" + else: raise PlatformNotSupportedException(self._platform) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) self.Parameters[self.Executable] = executablePath diff --git a/py/ToolChains/Lattice/Diamond.py b/py/ToolChains/Lattice/Diamond.py index 79031090..f425800d 100644 --- a/py/ToolChains/Lattice/Diamond.py +++ b/py/ToolChains/Lattice/Diamond.py @@ -43,13 +43,13 @@ from Base.Executable import Executable, CommandLineArgumentList, ExecutableArgument, ShortTupleArgument from Base.Logging import Severity, LogEntry from Base.Project import File, FileTypes, VHDLVersion +from ToolChains import ToolMixIn from ToolChains.Lattice.Lattice import LatticeException __api__ = [ 'DiamondException', 'Configuration', - 'DiamondMixIn', 'Diamond', 'Synth', 'SynthesisArgumentFile', @@ -140,31 +140,21 @@ def _ConfigureBinaryDirectory(self): return binPath -class DiamondMixIn: - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - self._platform = platform - self._dryrun = dryrun - self._binaryDirectoryPath = binaryDirectoryPath - self._version = version - self._Logger = logger - - -class Diamond(DiamondMixIn): - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - DiamondMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) - +class Diamond(ToolMixIn): def GetSynthesizer(self): - return Synth(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) + return Synth(self) -class Synth(Executable, DiamondMixIn): - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - DiamondMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) +class Synth(Executable, ToolMixIn): + def __init__(self, toolchain : ToolMixIn): + ToolMixIn.__init__( + self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, + toolchain._Logger) - if (platform == "Windows"): executablePath = binaryDirectoryPath / "synthesis.exe" - elif (platform == "Linux"): executablePath = binaryDirectoryPath / "synthesis" - else: raise PlatformNotSupportedException(platform) - super().__init__(platform, dryrun, executablePath, logger=logger) + if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "synthesis.exe" + elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "synthesis" + else: raise PlatformNotSupportedException(self._platform) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) self.Parameters[self.Executable] = executablePath diff --git a/py/ToolChains/Mentor/QuestaSim.py b/py/ToolChains/Mentor/QuestaSim.py index 30319aa3..45c9b482 100644 --- a/py/ToolChains/Mentor/QuestaSim.py +++ b/py/ToolChains/Mentor/QuestaSim.py @@ -43,13 +43,13 @@ from Base.Simulator import SimulationResult, PoCSimulationResultFilter, PoCSimulationResultNotFoundException from Base.Executable import Executable from Base.Executable import ExecutableArgument, ShortFlagArgument, ShortTupleArgument, PathArgument, StringArgument, CommandLineArgumentList +from ToolChains import ToolMixIn from ToolChains.Mentor.Mentor import MentorException __api__ = [ 'QuestaSimException', 'Configuration', - 'QuestaSimMixIn', 'QuestaSim', 'QuestaVHDLCompiler', 'QuestaSimulator', @@ -139,37 +139,27 @@ def RunPostConfigurationTasks(self): fileHandle.write(fileContent) -class QuestaSimMixIn: - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - self._platform = platform - self._dryrun = dryrun - self._binaryDirectoryPath = binaryDirectoryPath - self._version = version - self._Logger = logger - - -class QuestaSim(QuestaSimMixIn): - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - QuestaSimMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) - +class QuestaSim(ToolMixIn): def GetVHDLCompiler(self): - return QuestaVHDLCompiler(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) + return QuestaVHDLCompiler(self) def GetSimulator(self): - return QuestaSimulator(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) + return QuestaSimulator(self) def GetVHDLLibraryTool(self): - return QuestaVHDLLibraryTool(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) + return QuestaVHDLLibraryTool(self) -class QuestaVHDLCompiler(Executable, QuestaSimMixIn): - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - QuestaSimMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) +class QuestaVHDLCompiler(Executable, ToolMixIn): + def __init__(self, toolchain : ToolMixIn): + ToolMixIn.__init__( + self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, + toolchain._Logger) - if (self._platform == "Windows"): executablePath = binaryDirectoryPath / "vcom.exe" - elif (self._platform == "Linux"): executablePath = binaryDirectoryPath / "vcom" + if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "vcom.exe" + elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "vcom" else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, dryrun, executablePath, logger=logger) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) self.Parameters[self.Executable] = executablePath @@ -281,14 +271,16 @@ def GetTclCommand(self): return "vcom " + " ".join(parameterList[1:]) -class QuestaSimulator(Executable, QuestaSimMixIn): - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - QuestaSimMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) +class QuestaSimulator(Executable, ToolMixIn): + def __init__(self, toolchain : ToolMixIn): + ToolMixIn.__init__( + self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, + toolchain._Logger) - if (self._platform == "Windows"): executablePath = binaryDirectoryPath / "vsim.exe" - elif (self._platform == "Linux"): executablePath = binaryDirectoryPath / "vsim" + if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "vsim.exe" + elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "vsim" else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, dryrun, executablePath, logger=logger) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) self.Parameters[self.Executable] = executablePath @@ -422,14 +414,16 @@ def Simulate(self): return simulationResult.value -class QuestaVHDLLibraryTool(Executable, QuestaSimMixIn): - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - QuestaSimMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) +class QuestaVHDLLibraryTool(Executable, ToolMixIn): + def __init__(self, toolchain : ToolMixIn): + ToolMixIn.__init__( + self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, + toolchain._Logger) - if (self._platform == "Windows"): executablePath = binaryDirectoryPath / "vlib.exe" - elif (self._platform == "Linux"): executablePath = binaryDirectoryPath / "vlib" + if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "vlib.exe" + elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "vlib" else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, dryrun, executablePath, logger=logger) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) self.Parameters[self.Executable] = executablePath @@ -529,7 +523,7 @@ def QuestaVSimFilter(gen): yield LogEntry("{DARK_RED}{line}{NOCOLOR}".format(line=line[2:], **Init.Foreground), Severity.Error) else: yield LogEntry("{DARK_CYAN}{line}{NOCOLOR}".format(line=line[2:], **Init.Foreground), Severity.Normal) - elif line.startswith("# "): + elif line.startswith("# "): if (not PoCOutputFound): yield LogEntry(line, Severity.Verbose) else: diff --git a/py/ToolChains/PoC.py b/py/ToolChains/PoC.py index bd43672d..b5056710 100644 --- a/py/ToolChains/PoC.py +++ b/py/ToolChains/PoC.py @@ -67,7 +67,7 @@ def ConfigureForAll(self): if (len(self._host.PoCConfig['INSTALL.Git']) != 0): try: binaryDirectoryPath = Path(self._host.PoCConfig['INSTALL.Git']['BinaryDirectory']) - git = Git(self._host.Platform, self._host.DryRun, binaryDirectoryPath, logger=self._host.Logger) + git = Git(self._host.Platform, self._host.DryRun, binaryDirectoryPath, "", logger=self._host.Logger) gitRevList = git.GetGitRevList() gitRevList.RevListParameters[gitRevList.SwitchTags] = True gitRevList.RevListParameters[gitRevList.SwitchMaxCount] = 1 diff --git a/py/ToolChains/Xilinx/ISE.py b/py/ToolChains/Xilinx/ISE.py index ba12f6c5..83c3727a 100644 --- a/py/ToolChains/Xilinx/ISE.py +++ b/py/ToolChains/Xilinx/ISE.py @@ -42,6 +42,7 @@ from Base.Logging import LogEntry, Severity from Base.Project import Project as BaseProject, ProjectFile, ConstraintFile, FileTypes from Base.Simulator import SimulationResult, PoCSimulationResultFilter +from ToolChains import ToolMixIn from ToolChains.Xilinx.Xilinx import XilinxException from lib.Functions import CallByRefParam @@ -49,7 +50,6 @@ __api__ = [ 'ISEException', 'Configuration', - 'ISEMixIn', 'ISE', 'Fuse', 'ISESimulator', @@ -59,7 +59,7 @@ 'FuseFilter', 'SimulatorFilter', 'XstFilter', - 'CoreGeneratorFilter' + 'CoreGeneratorFilter', 'ISEProject', 'ISEProjectFile', 'UserConstraintFile' @@ -124,40 +124,31 @@ def __CheckISEVersion(self, binPath): raise ConfigurationException("ISE version mismatch. Expected version 14.7 (P.20131013).") -class ISEMixIn: - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - self._platform = platform - self._dryrun = dryrun - self._binaryDirectoryPath = binaryDirectoryPath - self._version = version - self._Logger = logger - - -class ISE(ISEMixIn): - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - ISEMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) - +class ISE(ToolMixIn): def GetVHDLCompiler(self): raise NotImplementedError("ISE.GetVHDLCompiler") # return ISEVHDLCompiler(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) def GetFuse(self): - return Fuse(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) + return Fuse(self) def GetXst(self): - return Xst(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) + return Xst(self) def GetCoreGenerator(self): - return CoreGenerator(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) + return CoreGenerator(self) + +class Fuse(Executable, ToolMixIn): + def __init__(self, toolchain : ToolMixIn): + ToolMixIn.__init__( + self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, + toolchain._Logger) -class Fuse(Executable, ISEMixIn): - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - ISEMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger=logger) - if (platform == "Windows"): executablePath = binaryDirectoryPath / "fuse.exe" - elif (platform == "Linux"): executablePath = binaryDirectoryPath / "fuse" + if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "fuse.exe" + elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "fuse" else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, dryrun, executablePath, logger=logger) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) self.Parameters[self.Executable] = executablePath @@ -329,13 +320,16 @@ def Simulate(self): return simulationResult.value -class Xst(Executable, ISEMixIn): - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - ISEMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger=logger) - if (platform == "Windows"): executablePath = binaryDirectoryPath / "xst.exe" - elif (platform == "Linux"): executablePath = binaryDirectoryPath / "xst" - else: raise PlatformNotSupportedException(platform) - Executable.__init__(self, platform, dryrun, executablePath, logger=logger) +class Xst(Executable, ToolMixIn): + def __init__(self, toolchain : ToolMixIn): + ToolMixIn.__init__( + self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, + toolchain._Logger) + + if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "xst.exe" + elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "xst" + else: raise PlatformNotSupportedException(self._platform) + Executable.__init__(self, self._platform, self._dryrun, executablePath, logger=self._Logger) self.Parameters[self.Executable] = executablePath @@ -409,13 +403,16 @@ def Compile(self): self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) -class CoreGenerator(Executable, ISEMixIn): - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - ISEMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger=logger) - if (platform == "Windows"): executablePath = binaryDirectoryPath / "coregen.exe" - elif (platform == "Linux"): executablePath = binaryDirectoryPath / "coregen" - else: raise PlatformNotSupportedException(platform) - super().__init__(platform, dryrun, executablePath, logger=logger) +class CoreGenerator(Executable, ToolMixIn): + def __init__(self, toolchain : ToolMixIn): + ToolMixIn.__init__( + self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, + toolchain._Logger) + + if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "coregen.exe" + elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "coregen" + else: raise PlatformNotSupportedException(self._platform) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) self.Parameters[self.Executable] = executablePath diff --git a/py/ToolChains/Xilinx/Vivado.py b/py/ToolChains/Xilinx/Vivado.py index 082d633a..30d35cbf 100644 --- a/py/ToolChains/Xilinx/Vivado.py +++ b/py/ToolChains/Xilinx/Vivado.py @@ -35,6 +35,7 @@ # load dependencies from subprocess import check_output +from ToolChains import ToolMixIn from lib.Functions import CallByRefParam from Base.Exceptions import PlatformNotSupportedException from Base.Logging import LogEntry, Severity @@ -49,7 +50,7 @@ __api__ = [ 'VivadoException', 'Configuration', - 'VivadoMixIn', + 'ToolMixIn', 'Vivado', 'XElab', 'XSim', @@ -120,36 +121,27 @@ def __CheckVivadoVersion(self, binPath, version): raise ConfigurationException("Vivado version mismatch. Expected version {0}.".format(version)) -class VivadoMixIn: - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - self._platform = platform - self._dryrun = dryrun - self._binaryDirectoryPath = binaryDirectoryPath - self._version = version - self._Logger = logger - - -class Vivado(VivadoMixIn): - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - VivadoMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) - +class Vivado(ToolMixIn): def GetElaborator(self): - return XElab(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) + return XElab(self) def GetSimulator(self): - return XSim(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) + return XSim(self) def GetSynthesizer(self): - return Synth(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) + return Synth(self) -class XElab(Executable, VivadoMixIn): - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - VivadoMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) - if (self._platform == "Windows"): executablePath = binaryDirectoryPath / "xelab.bat" - elif (self._platform == "Linux"): executablePath = binaryDirectoryPath / "xelab" +class XElab(Executable, ToolMixIn): + def __init__(self, toolchain : ToolMixIn): + ToolMixIn.__init__( + self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, + toolchain._Logger) + + if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "xelab.bat" + elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "xelab" else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, dryrun, executablePath, logger=logger) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) self.Parameters[self.Executable] = executablePath @@ -270,13 +262,16 @@ def Link(self): self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) -class XSim(Executable, VivadoMixIn): - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - VivadoMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) - if (self._platform == "Windows"): executablePath = binaryDirectoryPath / "xsim.bat" - elif (self._platform == "Linux"): executablePath = binaryDirectoryPath / "xsim" +class XSim(Executable, ToolMixIn): + def __init__(self, toolchain : ToolMixIn): + ToolMixIn.__init__( + self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, + toolchain._Logger) + + if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "xsim.bat" + elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "xsim" else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, dryrun, executablePath, logger=logger) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) self.Parameters[self.Executable] = executablePath @@ -365,13 +360,16 @@ def Simulate(self): return simulationResult.value -class Synth(Executable, VivadoMixIn): - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - VivadoMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) - if (self._platform == "Windows"): executablePath = binaryDirectoryPath / "vivado.bat" - elif (self._platform == "Linux"): executablePath = binaryDirectoryPath / "vivado" +class Synth(Executable, ToolMixIn): + def __init__(self, toolchain : ToolMixIn): + ToolMixIn.__init__( + self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, + toolchain._Logger) + + if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "vivado.bat" + elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "vivado" else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, dryrun, executablePath, logger=logger) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) self.Parameters[self.Executable] = executablePath diff --git a/py/ToolChains/__init__.py b/py/ToolChains/__init__.py index 4785d091..1cfae690 100644 --- a/py/ToolChains/__init__.py +++ b/py/ToolChains/__init__.py @@ -31,13 +31,13 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Repository Service Tool") +class ToolMixIn: + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + self._platform = platform + self._dryrun = dryrun + self._binaryDirectoryPath = binaryDirectoryPath + self._version = version + self._Logger = logger from .PoC import Configuration as PoC_Configuration @@ -55,6 +55,7 @@ # from .Lattice.Symplify import Configuration as LatticeSymplify_Configuration from .Mentor.Mentor import Configuration as Mentor_Configuration from .Mentor.QuestaSim import Configuration as Questa_Configuration +from .Mentor.ModelSimPE import Configuration as ModelSimPE_Configuration # from .Mentor.PrecisionRTL import Configuration as PrecisionRTL_Configuration # from .Synopsys.Synopsys import Configuration as Synopsys_Configuration # from .Synopsys.Symplify import Configuration as Symplify_Configuration @@ -80,6 +81,7 @@ # Mentor products Mentor_Configuration, Questa_Configuration, + ModelSimPE_Configuration, # Xilinx products Xilinx_Configuration, ISE_Configuration, diff --git a/py/Wrapper/PoC.psm1 b/py/Wrapper/PoC.psm1 index ae73157e..6336b5a3 100644 --- a/py/Wrapper/PoC.psm1 +++ b/py/Wrapper/PoC.psm1 @@ -154,6 +154,12 @@ $PoC_Environments = @{ "PSModule" = "Mentor.PrecisionRTL.psm1"; "PreHookFile" = "Mentor.PrecisionRTL.pre.ps1"; "PostHookFile" = "Mentor.PrecisionRTL.post.ps1"}; + "ModelSimPE" = @{ + "Load" = $false; + "Commands" = @("vsim", "msim"); + "PSModule" = "Mentor.ModelSimPE.psm1"; + "PreHookFile" = "Mentor.ModelSimPE.pre.ps1"; + "PostHookFile" = "Mentor.ModelSimPE.post.ps1"}; "QuestaSim" = @{ "Load" = $false; "Commands" = @("vsim", "qsim"); @@ -205,7 +211,22 @@ $PoC_Environments = @{ } # Tools } # Xilinx } +# ============================================================================== +function Invoke-BatchFile +{ param( + [string]$Path, + [string]$Parameters + ) + $environmentVariables = cmd.exe /c " `"$Path`" $Parameters && set " + foreach ($line in $environmentVariables) + { if ($_ -match "^(.*?)=(.*)$") + { Set-Content "env:\$($matches[1])" $matches[2] } + else + { $_ } + } +} +# ============================================================================== function Get-PoCEnvironmentArray { <# .SYNOPSIS diff --git a/py/Wrapper/Xilinx.ISE.psm1 b/py/Wrapper/Xilinx.ISE.psm1 index c0b274d5..1bb2b786 100644 --- a/py/Wrapper/Xilinx.ISE.psm1 +++ b/py/Wrapper/Xilinx.ISE.psm1 @@ -59,14 +59,7 @@ function Open-Environment } Write-Host "Loading Xilinx ISE environment '$ISE_SettingsFile'" -ForegroundColor Yellow - if (-not (Get-Module -ListAvailable PSCX)) - { Write-Host "[ERROR]: PowerShell Community Extensions (PSCX) is not installed." -ForegroundColor Red - return 1 - } - Import-Module PSCX - Push-EnvironmentBlock -Description "Before loading Xilinx ISE." - Invoke-BatchFile -path $ISE_SettingsFile return 0 } diff --git a/py/Wrapper/Xilinx.Vivado.psm1 b/py/Wrapper/Xilinx.Vivado.psm1 index 4dd0178e..0423825f 100644 --- a/py/Wrapper/Xilinx.Vivado.psm1 +++ b/py/Wrapper/Xilinx.Vivado.psm1 @@ -57,14 +57,7 @@ function Open-Environment } Write-Host "Loading Xilinx Vivado environment '$Vivado_SettingsFile'" -ForegroundColor Yellow - if (-not (Get-Module -ListAvailable PSCX)) - { Write-Host "[ERROR]: PowerShell Community Extensions (PSCX) is not installed." -ForegroundColor Red - return 1 - } - Import-Module PSCX - Push-EnvironmentBlock -Description "Before loading Xilinx Vivado." - Invoke-BatchFile -path $Vivado_SettingsFile return 0 } diff --git a/py/Wrapper/wrapper.sh b/py/Wrapper/wrapper.sh index a7130fbc..1eaaab05 100644 --- a/py/Wrapper/wrapper.sh +++ b/py/Wrapper/wrapper.sh @@ -126,7 +126,7 @@ declare -A Env_Lattice_ActiveHDL=( declare -A Env_Mentor=( ["PreHookFile"]="Mentor.pre.sh" ["PostHookFile"]="Mentor.post.sh" - ["Tools"]="PrecisionRTL QuestaSim" + ["Tools"]="PrecisionRTL ModelSimPE QuestaSim" ) declare -A Env_Mentor_PrecisionRTL=( ["Load"]=0 @@ -135,6 +135,13 @@ declare -A Env_Mentor_PrecisionRTL=( ["PreHookFile"]="Mentor.PrecisionRTL.pre.sh" ["PostHookFile"]="Mentor.PrecisionRTL.post.sh" ) +declare -A Env_Mentor_ModelSimPE=( + ["Load"]=0 + ["Commands"]="vsim" + ["BashModule"]="Mentor.ModelSimPE.sh" + ["PreHookFile"]="Mentor.ModelSimPE.pre.sh" + ["PostHookFile"]="Mentor.ModelSimPE.post.sh" +) declare -A Env_Mentor_QuestaSim=( ["Load"]=0 ["Commands"]="vsim" diff --git a/py/config.defaults.ini b/py/config.defaults.ini index 23e180be..94f9c0bd 100644 --- a/py/config.defaults.ini +++ b/py/config.defaults.ini @@ -59,7 +59,6 @@ LatticeSpecificFiles = lattice LatticeSynthesisFiles = lse # Mentor files -ModelSimFiles = vsim QuestaSimFiles = vsim # Synopsys files diff --git a/py/lib/Decorators.py b/py/lib/Decorators.py index 14c69221..2e0ad17c 100644 --- a/py/lib/Decorators.py +++ b/py/lib/Decorators.py @@ -33,6 +33,8 @@ # load dependencies import functools +from lib.SphinxExtensions import DocumentMemberAttribute + __api__ = [ 'MethodAlias', @@ -44,9 +46,15 @@ class MethodAlias: + """``MethodAlias`` creates a local method, which is an alias to another method + local or inherited method. + """ + + @DocumentMemberAttribute() def __init__(self, method): self.method = method + @DocumentMemberAttribute() def __call__(self, func): return self.method diff --git a/py/lib/pyAttribute/ArgParseAttributes.py b/py/lib/pyAttribute/ArgParseAttributes.py index fc99672a..715319af 100644 --- a/py/lib/pyAttribute/ArgParseAttributes.py +++ b/py/lib/pyAttribute/ArgParseAttributes.py @@ -84,11 +84,11 @@ class CommandAttribute(Attribute): def __init__(self, command, **kwargs): super().__init__() - self.__command = command - self.__kwargs = kwargs + self.__command = command + self.__kwargs = kwargs def __call__(self, func): - self.__handler = func + self.__handler = func return super().__call__(func) @property diff --git a/py/lib/pyAttribute/__init__.py b/py/lib/pyAttribute/__init__.py index 76973ca0..0d8019a7 100644 --- a/py/lib/pyAttribute/__init__.py +++ b/py/lib/pyAttribute/__init__.py @@ -42,6 +42,10 @@ ] __all__ = __api__ +# TODO: implement class, method, function attributes +# TODO: implement unique attributes +# TODO: add an attacheHelper methods option +# TODO: implement a static HasAttribute method class Attribute: __AttributesMemberName__ = "__pyattr__" @@ -93,7 +97,7 @@ def GetMethods(self): }.items() @staticmethod - def HasAttribute(method): + def HasAttribute(method): # TODO: add a tuple based type filer if (Attribute.__AttributesMemberName__ in method.__dict__): attributeList = method.__dict__[Attribute.__AttributesMemberName__] return (isinstance(attributeList, list) and (len(attributeList) != 0)) @@ -101,7 +105,7 @@ def HasAttribute(method): return False @staticmethod - def GetAttributes(method): + def GetAttributes(method): # TODO: add a tuple based type filer if (Attribute.__AttributesMemberName__ in method.__dict__): attributeList = method.__dict__[Attribute.__AttributesMemberName__] if isinstance(attributeList, list): diff --git a/sim/sort/sortnet/sortnet_BitonicSort_tb.wdo b/sim/sort/sortnet/sortnet_BitonicSort_tb.wdo index b0cdf998..e51499c2 100644 --- a/sim/sort/sortnet/sortnet_BitonicSort_tb.wdo +++ b/sim/sort/sortnet/sortnet_BitonicSort_tb.wdo @@ -1,3 +1,43 @@ +proc _poc_reanalyze {} { + set returnCode [exec -ignorestderr py -3 ../../py/PoC.py -d vsim PoC.sort.sortnet.BitonicSort --analyze --elaborate] + puts "ReturnCode: $returnCode" +} + +proc poc_recompile {} { + _poc_reanalyze + restart -force + puts "DONE" +} + +proc poc_rerun {} { + restart -force + # if xxx exists + # do ../../sim/sort/sortnet/sortnet_BitonicSort_tb.do + # else + do ../../sim/vSim.gui.tcl + puts "DONE" +} + +proc poc_relaunch {} { + _poc_reanalyze + poc_rerun +} + +proc poc_reload_waveform {} { + puts "Not implemented!" + # if xxx exists + # do ../../sim/sort/sortnet/sortnet_BitonicSort_tb.wdo + # else + # do ../../sim/vSim.default.wdo + puts "DONE" +} + +proc poc_save_waveform {} { + puts "Saving waveform settings to 'D:/git/PoC/sim/sort/sortnet/sortnet_BitonicSort_tb.wdo'..." + write format wave -window .main_pane.wave.interior.cs.body.pw.wf D:/git/PoC/sim/sort/sortnet/sortnet_BitonicSort_tb.wdo + puts "DONE" +} + onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate /sortnet_bitonicsort_tb/Clock diff --git a/src/io/ddrio/ddrio_in.vhdl b/src/io/ddrio/ddrio_in.vhdl index 6d349520..acc228f4 100644 --- a/src/io/ddrio/ddrio_in.vhdl +++ b/src/io/ddrio/ddrio_in.vhdl @@ -17,6 +17,20 @@ -- the falling edge directly before this rising edge. Thus sampling starts with -- the falling edge of the clock as depicted in the following waveform. -- +-- .. wavedrom:: +-- +-- { signal: [ +-- {name: 'clk', wave: 'H.L.H.L.H.L.H.L.H'}, +-- {name: 'pad', wave: 'x2.3.4.5.2.3.x...', data: ['0', '1', '2', '3', '4', '5'], node: '..a.b.c.d.e.f..'}, +-- ['DataIn', +-- {name: 'DataIn_low', wave: 'x...2...4...2...x', data: ['0', '2', '4'], node: '.....k...m...o.'}, +-- {name: 'DataIn_high', wave: 'x...3...5...3...x', data: ['1', '3', '5'], node: '.....l...n...p.'}, +-- ], +-- ], +-- edge: ['a~k', 'b~l', 'c~m', 'd~n', 'e~o', 'f~p'], +-- foot: {text: 'PoC.io.ddrio.in'} +-- } +-- -- .. code-block:: none -- -- __ ____ ____ __ @@ -35,7 +49,7 @@ -- -- License: -- ============================================================================= --- Copyright 2007-2015 Technische Universitaet Dresden - Germany, +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl b/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl index bac83d84..8f1e1dd0 100644 --- a/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl +++ b/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl @@ -9,7 +9,7 @@ -- -- Description: -- ------------------------------------ --- Adapter between the :doc:`PoC.Mem ` +-- Adapter between the :ref:`PoC.Mem ` -- interface and the User Interface of the Xilinx MIG IP core for the -- Spartan-6 FPGA Memory Controller Block (MCB). The MCB can be configured to -- have multiple ports. One instance of this adapter is required for every @@ -20,7 +20,7 @@ -- The PoC.Mem interface provides single-cycle fully pipelined read/write access -- to the memory. All accesses are word-aligned. Always all bytes of a word are -- written to the memory. More details can be found --- :doc:`here `. +-- :ref:`here `. -- -- Generic parameters: -- diff --git a/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl b/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl index 13730862..cb8b6d5a 100644 --- a/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl +++ b/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl @@ -9,15 +9,14 @@ -- -- Description: -- ------------------------------------ --- Adapter between the :doc:`PoC.Mem ` --- interface and the application interface ("app") --- of the Xilinx MIG IP core for 7-Series FPGAs. +-- Adapter between the :ref:`PoC.Mem ` interface and the +-- application interface ("app") of the Xilinx MIG IP core for 7-Series FPGAs. -- -- Simplifies the application interface ("app") of the Xilinx MIG IP core. -- The PoC.Mem interface provides single-cycle fully pipelined read/write access -- to the memory. All accesses are word-aligned. Always all bytes of a word are -- written to the memory. More details can be found --- :doc:`here `. +-- :ref:`here `. -- -- Generic parameters: -- diff --git a/src/mem/ocram/ocram_esdp.vhdl b/src/mem/ocram/ocram_esdp.vhdl index 82d4615d..09583151 100644 --- a/src/mem/ocram/ocram_esdp.vhdl +++ b/src/mem/ocram/ocram_esdp.vhdl @@ -14,11 +14,11 @@ -- * dual clock, clock enable, -- * 1 read/write port (1st port) plus 1 read port (2nd port). -- --- .. NOTE:: --- This component is **deprecated**. --- Please use :doc:`PoC.mem.ocram.tdp ` for new designs. +-- .. deprecated:: 1.1 +-- +-- :color:`Please use ` :ref:`IP:ocram_tdp` :color:`for new designs. -- This component has been provided because older FPGA compilers where not --- able to infer true dual-port memory from an RTL description. +-- able to infer true dual-port memory from an RTL description. ` -- -- Command truth table for port 1: -- diff --git a/src/mem/sdram/sdram_ctrl_de0.vhdl b/src/mem/sdram/sdram_ctrl_de0.vhdl index a5990ec3..3eef14a2 100644 --- a/src/mem/sdram/sdram_ctrl_de0.vhdl +++ b/src/mem/sdram/sdram_ctrl_de0.vhdl @@ -36,13 +36,13 @@ -- Read data is also aligned with ``clk``. -- -- For description on ``clkout`` see --- :doc:`sdram_ctrl_phy_de0 `. +-- :ref:`sdram_ctrl_phy_de0 `. -- -- Synchronous resets are used. -- -- License: -- ============================================================================= --- Copyright 2007-2015 Technische Universitaet Dresden - Germany, +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); @@ -57,27 +57,7 @@ -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= - -------------------------------------------------------------------------------- --- Naming Conventions: --- (Based on: Keating and Bricaud: "Reuse Methodology Manual") -- --- active low signals: "*_n" --- clock signals: "clk", "clk_div#", "clk_#x" --- reset signals: "rst", "rst_n" --- generics: all UPPERCASE --- user defined types: "*_TYPE" --- state machine next state: "*_ns" --- state machine current state: "*_cs" --- output of a register: "*_r" --- asynchronous signal: "*_a" --- pipelined or register delay signals: "*_p#" --- data before being registered into register with the same name: "*_nxt" --- clock enable signals: "*_ce" --- internal version of output port: "*_i" --- tristate internal signal "*_z" -------------------------------------------------------------------------------- - library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; diff --git a/src/mem/sdram/sdram_ctrl_fsm.vhdl b/src/mem/sdram/sdram_ctrl_fsm.vhdl index 2d196089..7d70ea94 100644 --- a/src/mem/sdram/sdram_ctrl_fsm.vhdl +++ b/src/mem/sdram/sdram_ctrl_fsm.vhdl @@ -93,27 +93,7 @@ -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= - -------------------------------------------------------------------------------- --- Naming Conventions: --- (Based on: Keating and Bricaud: "Reuse Methodology Manual") -- --- active low signals: "*_n" --- clock signals: "clk", "clk_div#", "clk_#x" --- reset signals: "rst", "rst_n" --- generics: all UPPERCASE --- user defined types: "*_TYPE" --- state machine next state: "*_ns" --- state machine current state: "*_cs" --- output of a register: "*_r" --- asynchronous signal: "*_a" --- pipelined or register delay signals: "*_p#" --- data before being registered into register with the same name: "*_nxt" --- clock enable signals: "*_ce" --- internal version of output port: "*_i" --- tristate internal signal "*_z" -------------------------------------------------------------------------------- - library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; diff --git a/src/mem/sdram/sdram_ctrl_phy_de0.vhdl b/src/mem/sdram/sdram_ctrl_phy_de0.vhdl index d699c236..20e03823 100644 --- a/src/mem/sdram/sdram_ctrl_phy_de0.vhdl +++ b/src/mem/sdram/sdram_ctrl_phy_de0.vhdl @@ -8,7 +8,7 @@ -- -- Description: -- ------------------------------------- --- Physical layer used by module :doc:`sdram_ctrl_de0 `. +-- Physical layer used by module :ref:`sdram_ctrl_de0 `. -- -- Instantiates input and output buffer components and adjusts the timing for -- the Altera DE0 board. @@ -44,7 +44,7 @@ -- -- License: -- ============================================================================= --- Copyright 2007-2015 Technische Universitaet Dresden - Germany, +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl b/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl index 4cd652c2..0a76bece 100644 --- a/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl +++ b/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl @@ -8,7 +8,7 @@ -- -- Description: -- ------------------------------------- --- Physical layer used by module :doc:`sdram_ctrl_s3esk `. +-- Physical layer used by module :ref:`sdram_ctrl_s3esk `. -- -- Instantiates input and output buffer components and adjusts the timing for -- the Spartan-3E Starter Kit Board. @@ -82,7 +82,7 @@ -- -- License: -- ============================================================================= --- Copyright 2007-2015 Technische Universitaet Dresden - Germany, +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); @@ -97,27 +97,7 @@ -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= - -------------------------------------------------------------------------------- --- Naming Conventions: --- (Based on: Keating and Bricaud: "Reuse Methodology Manual") -- --- active low signals: "*_n" --- clock signals: "clk", "clk_div#", "clk_#x" --- reset signals: "rst", "rst_n" --- generics: all UPPERCASE --- user defined types: "*_TYPE" --- state machine next state: "*_ns" --- state machine current state: "*_cs" --- output of a register: "*_r" --- asynchronous signal: "*_a" --- pipelined or register delay signals: "*_p#" --- data before being registered into register with the same name: "*_nxt" --- clock enable signals: "*_ce" --- internal version of output port: "*_i" --- tristate internal signal "*_z" -------------------------------------------------------------------------------- - library ieee; use ieee.std_logic_1164.all; diff --git a/src/mem/sdram/sdram_ctrl_s3esk.vhdl b/src/mem/sdram/sdram_ctrl_s3esk.vhdl index 27bd1aff..ea107d00 100644 --- a/src/mem/sdram/sdram_ctrl_s3esk.vhdl +++ b/src/mem/sdram/sdram_ctrl_s3esk.vhdl @@ -43,7 +43,7 @@ -- -- License: -- ============================================================================= --- Copyright 2007-2015 Technische Universitaet Dresden - Germany, +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); @@ -58,27 +58,7 @@ -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= - -------------------------------------------------------------------------------- --- Naming Conventions: --- (Based on: Keating and Bricaud: "Reuse Methodology Manual") -- --- active low signals: "*_n" --- clock signals: "clk", "clk_div#", "clk_#x" --- reset signals: "rst", "rst_n" --- generics: all UPPERCASE --- user defined types: "*_TYPE" --- state machine next state: "*_ns" --- state machine current state: "*_cs" --- output of a register: "*_r" --- asynchronous signal: "*_a" --- pipelined or register delay signals: "*_p#" --- data before being registered into register with the same name: "*_nxt" --- clock enable signals: "*_ce" --- internal version of output port: "*_i" --- tristate internal signal "*_z" -------------------------------------------------------------------------------- - library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; diff --git a/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl b/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl index dde6af29..6ddeb525 100644 --- a/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl +++ b/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl @@ -72,6 +72,37 @@ architecture tb of sortnet_BitonicSort_tb is subtype T_DATA is std_logic_vector(DATA_BITS - 1 downto 0); type T_DATA_VECTOR is array(natural range <>) of T_DATA; + type T_SB_KEY_VECTOR is array(natural range <>) of std_logic_vector(KEY_BITS - 1 downto 0); + type T_SB_DATA_VECTOR is array(natural range <>) of std_logic_vector((DATA_BITS - KEY_BITS) - 1 downto 0); + + type T_SCOREBOARD_DATA is record + IsKey : std_logic; + Meta : std_logic_vector(META_BITS - 1 downto 0); + Key : T_SB_KEY_VECTOR(INPUTS - 1 downto 0); + Data : T_SB_DATA_VECTOR(INPUTS - 1 downto 0); + end record; + + function match(expected : T_SCOREBOARD_DATA; actual : T_SCOREBOARD_DATA) return boolean is + begin + report "checking: "; -- & to_string(expected.Meta) severity note; + return TRUE; + end function; + + function to_string(vector : T_SCOREBOARD_DATA) return string is + begin + return "to_string"; + end function; + + package P_Scoreboard is new osvvm.ScoreboardGenericPkg + generic map ( + ExpectedType => T_SCOREBOARD_DATA, + ActualType => T_SCOREBOARD_DATA, + Match => match, + expected_to_string => to_string, --[T_SCOREBOARD_DATA return string], + actual_to_string => to_string + ); + alias T_SCOREBOARD is P_Scoreboard.ScoreBoardPType; + function to_dv(slm : T_SLM) return T_DATA_VECTOR is variable Result : T_DATA_VECTOR(slm'range(1)); begin @@ -94,21 +125,23 @@ architecture tb of sortnet_BitonicSort_tb is return Result; end function; - constant CLOCK_FREQ : FREQ := 100 MHz; - signal Clock : std_logic := '1'; + constant CLOCK_FREQ : FREQ := 100 MHz; + signal Clock : std_logic := '1'; + + signal Generator_Valid : std_logic := '0'; + signal Generator_IsKey : std_logic := '0'; + signal Generator_Data : T_DATA_VECTOR(INPUTS - 1 downto 0) := (others => (others => '0')); + signal Generator_Meta : std_logic_vector(META_BITS - 1 downto 0) := (others => '0'); - signal Generator_Valid : std_logic; - signal Generator_IsKey : std_logic; - signal Generator_Data : T_DATA_VECTOR(INPUTS - 1 downto 0); - signal Generator_Meta : std_logic_vector(META_BITS - 1 downto 0); + signal Sort_Valid : std_logic; + signal Sort_IsKey : std_logic; + signal Sort_Data : T_DATA_VECTOR(INPUTS - 1 downto 0); + signal Sort_Meta : std_logic_vector(META_BITS - 1 downto 0); - signal Sort_Valid : std_logic; - signal Sort_IsKey : std_logic; - signal Sort_Data : T_DATA_VECTOR(INPUTS - 1 downto 0); - signal Sort_Meta : std_logic_vector(META_BITS - 1 downto 0); + signal DataInputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0); + signal DataOutputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0); - signal DataInputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0); - signal DataOutputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0); + shared variable ScoreBoard : T_SCOREBOARD; begin -- initialize global simulation status @@ -123,13 +156,14 @@ begin simGenerateClock(Clock, CLOCK_FREQ); procGenerator : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Generator"); - variable RandomVar : RandomPType; -- protected type from RandomPkg + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Generator"); + variable RandomVar : RandomPType; -- protected type from RandomPkg - variable KeyInput : std_logic_vector(KEY_BITS - 1 downto 0); - variable DataInput : std_logic_vector(DATA_BITS - KEY_BITS - 1 downto 0); - variable TagInput : std_logic_vector(TAG_BITS - 1 downto 0); + variable KeyInput : std_logic_vector(KEY_BITS - 1 downto 0); + variable DataInput : std_logic_vector(DATA_BITS - KEY_BITS - 1 downto 0); + variable TagInput : std_logic_vector(TAG_BITS - 1 downto 0); + variable ScoreBoardData : T_SCOREBOARD_DATA; begin RandomVar.InitSeed(RandomVar'instance_name); -- Generate initial seeds @@ -141,15 +175,22 @@ begin Generator_Valid <= '1'; for i in 0 to LOOP_COUNT - 1 loop - Generator_IsKey <= to_sl(i mod DATA_COLUMNS = 0); + TagInput := RandomVar.RandSlv(TAG_BITS); + + ScoreBoardData.IsKey := to_sl(i mod DATA_COLUMNS = 0); + ScoreBoardData.Meta := resize(TagInput, META_BITS); for j in 0 to INPUTS - 1 loop - KeyInput := RandomVar.RandSlv(KEY_BITS); - DataInput := RandomVar.RandSlv(DATA_BITS - KEY_BITS); - TagInput := RandomVar.RandSlv(TAG_BITS); + KeyInput := RandomVar.RandSlv(KEY_BITS); + DataInput := RandomVar.RandSlv(DATA_BITS - KEY_BITS); - Generator_Data(j) <= DataInput & KeyInput; - Generator_Meta <= resize(TagInput, META_BITS); + ScoreBoardData.Key(j) := KeyInput; + ScoreBoardData.Data(j) := DataInput; + Generator_Data(j) <= DataInput & KeyInput; end loop; + ScoreBoard.Push(ScoreBoardData); + + Generator_IsKey <= ScoreBoardData.IsKey; + Generator_Meta <= ScoreBoardData.Meta; wait until rising_edge(Clock); end loop; @@ -189,10 +230,12 @@ begin Sort_Data <= to_dv(DataOutputMatrix); procChecker : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Checker"); - variable Check : boolean; - variable CurValue : unsigned(KEY_BITS - 1 downto 0); - variable LastValue : unsigned(KEY_BITS - 1 downto 0); + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Checker"); + variable Check : boolean; + variable CurValue : unsigned(KEY_BITS - 1 downto 0); + variable LastValue : unsigned(KEY_BITS - 1 downto 0); + + variable ScoreBoardData : T_SCOREBOARD_DATA; begin wait until rising_edge(Sort_Valid); @@ -200,6 +243,13 @@ begin wait until falling_edge(Clock); Check := TRUE; + ScoreBoardData.IsKey := Sort_IsKey; + ScoreBoardData.Meta := Sort_Meta; + for j in 0 to INPUTS - 1 loop + ScoreBoardData.Key(j) := Sort_Data(j)(KEY_BITS - 1 downto 0); + ScoreBoardData.Data(j) := Sort_Data(j)(DATA_BITS - 1 downto KEY_BITS); + end loop; + if (Sort_IsKey = '1') then LastValue := (others => '0'); for j in 0 to INPUTS - 1 loop @@ -211,6 +261,8 @@ begin else -- no routine implemented to check if sorting network is switched as in the previous cycles end if; + + ScoreBoard.Check(ScoreBoardData); end loop; -- This process is finished diff --git a/tools/ReadTheDocs/requirements.txt b/tools/ReadTheDocs/requirements.txt index 1db5d19a..dce1a4db 100644 --- a/tools/ReadTheDocs/requirements.txt +++ b/tools/ReadTheDocs/requirements.txt @@ -1,3 +1,9 @@ -r ../../requirements.txt sphinxcontrib-autoprogram>=0.1.3 +#sphinxcontrib-actdiag>=0.8.5 +#sphinxcontrib-seqdiag>=0.8.5 +sphinxcontrib-wavedrom>=1.2.0 +sphinxcontrib-textstyle>=0.2.1 +# sphinxcontrib-spelling>=2.2.0 autoapi +# changelog>=0.3.5 diff --git a/tools/precompile/compile-osvvm.ps1 b/tools/precompile/compile-osvvm.ps1 index 128b1cc2..7bd374fb 100644 --- a/tools/precompile/compile-osvvm.ps1 +++ b/tools/precompile/compile-osvvm.ps1 @@ -155,22 +155,27 @@ if ($Questa) "RandomBasePkg.vhd", "RandomPkg.vhd", "CoveragePkg.vhd", + "ScoreboardGenericPkg.vhd", + "ScoreboardPkg.vhd", "OsvvmContext.vhd" ) $SourceFiles = $Files | % { "$SourceDirectory\$_" } # Compile libraries with vcom, executed in destination directory Write-Host "Creating library '$Library' with vlib/vmap..." -ForegroundColor Yellow - & "$VSimBinDir\vlib.exe" $Library - & "$VSimBinDir\vmap.exe" -del $Library - & "$VSimBinDir\vmap.exe" $Library "$DestDir" + $InvokeExpr = "$VSimBinDir\vlib.exe " + $Library + " 2>&1" + $ErrorRecordFound = Invoke-Expression $InvokeExpr | Restore-NativeCommandStream | Write-ColoredQuestaVLibLine $SuppressWarnings " " -Verbose:$EnableVerbose -Debug:$EnableDebug + $InvokeExpr = "$VSimBinDir\vmap.exe -del " + $Library + " 2>&1" + $ErrorRecordFound = Invoke-Expression $InvokeExpr | Restore-NativeCommandStream | Write-ColoredQuestaVMapLine $SuppressWarnings " " -Verbose:$EnableVerbose -Debug:$EnableDebug + $InvokeExpr = "$VSimBinDir\vmap.exe " + $Library + " $DestDir\$Library 2>&1" + $ErrorRecordFound = Invoke-Expression $InvokeExpr | Restore-NativeCommandStream | Write-ColoredQuestaVMapLine $SuppressWarnings " " -Verbose:$EnableVerbose -Debug:$EnableDebug Write-Host "Compiling library '$Library' with vcom..." -ForegroundColor Yellow $ErrorCount += 0 foreach ($File in $SourceFiles) { Write-Host "Compiling '$File'..." -ForegroundColor DarkCyan $InvokeExpr = "$VSimBinDir\vcom.exe -suppress 1246 -2008 -work $Library " + $File + " 2>&1" - $ErrorRecordFound = Invoke-Expression $InvokeExpr | Restore-NativeCommandStream | Write-ColoredQuestaLine $SuppressWarnings " " -Verbose:$EnableVerbose -Debug:$EnableDebug + $ErrorRecordFound = Invoke-Expression $InvokeExpr | Restore-NativeCommandStream | Write-ColoredQuestaVComLine $SuppressWarnings " " -Verbose:$EnableVerbose -Debug:$EnableDebug if ($LastExitCode -ne 0) { $ErrorCount += 1 if ($HaltOnError) diff --git a/tools/precompile/compile-osvvm.sh b/tools/precompile/compile-osvvm.sh index f5129651..fe9b7ffd 100755 --- a/tools/precompile/compile-osvvm.sh +++ b/tools/precompile/compile-osvvm.sh @@ -210,6 +210,8 @@ if [ "$COMPILE_FOR_VSIM" == "TRUE" ]; then RandomBasePkg.vhd RandomPkg.vhd CoveragePkg.vhd + ScoreboardGenericPkg.vhd + ScoreboardPkg.vhd OsvvmContext.vhd ) From 7ff1525cdad4d57de7dc16aa9add8cd7fc921d0f Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Nov 2016 14:17:47 +0100 Subject: [PATCH 41/97] Debugging RTFD - step 1 --- docs/conf.py | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/conf.py b/docs/conf.py index 83542d64..5dea6efe 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -25,6 +25,7 @@ sys.path.insert(0, os.path.abspath('../py')) sys.path.insert(0, os.path.abspath('_extensions')) +print(sys.path) # -- General configuration ------------------------------------------------ From 0e509faff0b9cd78e057c9971a91ef0390d71f1b Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Nov 2016 14:20:56 +0100 Subject: [PATCH 42/97] Require Sphinx >=1.4.8. --- docs/conf.py | 2 +- tools/ReadTheDocs/requirements.txt | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/docs/conf.py b/docs/conf.py index 5dea6efe..65ed8ad1 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -30,7 +30,7 @@ # -- General configuration ------------------------------------------------ # If your documentation needs a minimal Sphinx version, state it here. -#needs_sphinx = '1.0' +needs_sphinx = '1.4.9' # Add any Sphinx extension module names here, as strings. They can be # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom diff --git a/tools/ReadTheDocs/requirements.txt b/tools/ReadTheDocs/requirements.txt index dce1a4db..a45043ce 100644 --- a/tools/ReadTheDocs/requirements.txt +++ b/tools/ReadTheDocs/requirements.txt @@ -1,4 +1,5 @@ -r ../../requirements.txt +sphinx>=1.4.8 sphinxcontrib-autoprogram>=0.1.3 #sphinxcontrib-actdiag>=0.8.5 #sphinxcontrib-seqdiag>=0.8.5 From 52b0f6e935bccbca1727a4670684c3220ac30e8f Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Nov 2016 14:23:20 +0100 Subject: [PATCH 43/97] Fixed typo in version number. --- docs/conf.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/conf.py b/docs/conf.py index 65ed8ad1..78410844 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -30,7 +30,7 @@ # -- General configuration ------------------------------------------------ # If your documentation needs a minimal Sphinx version, state it here. -needs_sphinx = '1.4.9' +needs_sphinx = '1.4.8' # Add any Sphinx extension module names here, as strings. They can be # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom From 3ed2530659827e27252e478b1b4d7496c1ccd4f0 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Nov 2016 14:31:49 +0100 Subject: [PATCH 44/97] Added missing lib.SphinxExtensions package. --- py/lib/SphinxExtensions/__init__.py | 43 +++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 py/lib/SphinxExtensions/__init__.py diff --git a/py/lib/SphinxExtensions/__init__.py b/py/lib/SphinxExtensions/__init__.py new file mode 100644 index 00000000..9c065ea9 --- /dev/null +++ b/py/lib/SphinxExtensions/__init__.py @@ -0,0 +1,43 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# Python Module: +# +# Description: +# ------------------------------------ +# - TODO +# +# License: +# ============================================================================== +# Copyright 2007-2016 Patrick Lehmann - Dresden, Germany +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +# +from lib.pyAttribute import Attribute + + +__api__ = [ + 'DocumentMemberAttribute' +] +__all__ = __api__ + + +class DocumentMemberAttribute(Attribute): + def __init__(self, value=True): + super().__init__() + self.value = value From 914b2df875c1ac11ab79cb57e6d9cc6eab55dc0d Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Nov 2016 14:33:36 +0100 Subject: [PATCH 45/97] Added missing ModelSimPE.py file. --- docs/conf.py | 1 - py/ToolChains/Mentor/ModelSimPE.py | 121 +++++++++++++++++++++++++++++ 2 files changed, 121 insertions(+), 1 deletion(-) create mode 100644 py/ToolChains/Mentor/ModelSimPE.py diff --git a/docs/conf.py b/docs/conf.py index 78410844..5a49b1cd 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -25,7 +25,6 @@ sys.path.insert(0, os.path.abspath('../py')) sys.path.insert(0, os.path.abspath('_extensions')) -print(sys.path) # -- General configuration ------------------------------------------------ diff --git a/py/ToolChains/Mentor/ModelSimPE.py b/py/ToolChains/Mentor/ModelSimPE.py new file mode 100644 index 00000000..15ea1eab --- /dev/null +++ b/py/ToolChains/Mentor/ModelSimPE.py @@ -0,0 +1,121 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# Martin Zabel +# Thomas B. Preusser +# +# Python Class: Mentor Graphics ModelSim specific classes +# +# Description: +# ------------------------------------ +# TODO: +# - +# - +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair of VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +# +# load dependencies +from re import compile as RegExpCompile +from subprocess import check_output + +from Base.Configuration import ConfigurationException +from ToolChains.Mentor.Mentor import MentorException +from ToolChains.Mentor.QuestaSim import Configuration as QuestaSim_Configuration + + +__api__ = [ + 'ModelSimException', + 'Configuration' +] +__all__ = __api__ + + +class ModelSimException(MentorException): + pass + + +class Configuration(QuestaSim_Configuration): + _vendor = "Mentor" + _toolName = "ModelSim PE" + _section = "INSTALL.Mentor.ModelSimPE" + _template = { + "Windows": { + _section: { + "Version": "10.4a", + "InstallationDirectory": "${INSTALL.Mentor:InstallationDirectory}/ModelSim PE/${Version}", + "BinaryDirectory": "${InstallationDirectory}/win32pe_edu" + } + }, + "Linux": { + _section: { + "Version": "10.4a", + "InstallationDirectory": "${INSTALL.Mentor:InstallationDirectory}/ModelSim PE/${Version}", + "BinaryDirectory": "${InstallationDirectory}/linux32pe" + } + } + } + + def CheckDependency(self): + # return True if Mentor is configured + return (len(self._host.PoCConfig['INSTALL.Mentor']) != 0) + + def ConfigureForAll(self): + try: + if (not self._AskInstalled("Is Mentor ModelSim PE installed on your system?")): + self.ClearSection() + else: + version = self._ConfigureVersion() + self._ConfigureInstallationDirectory() + binPath = self._ConfigureBinaryDirectory() + self.__CheckQuestaSimVersion(binPath, version) + except ConfigurationException: + self.ClearSection() + raise + + def __GetModelSimVersion(self, binPath): + if (self._host.Platform == "Windows"): + vsimPath = binPath / "vsim.exe" + else: + vsimPath = binPath / "vsim" + + if not vsimPath.exists(): + raise ConfigurationException("Executable '{0!s}' not found.".format(vsimPath)) from FileNotFoundError( + str(vsimPath)) + + # get version and backend + try: + output = check_output([str(vsimPath), "-version"], universal_newlines=True) + except OSError as ex: + raise ConfigurationException("Error while accessing '{0!s}'.".format(vsimPath)) from ex + + version = None + versionRegExpStr = r"^.* vsim (.+?) " + versionRegExp = RegExpCompile(versionRegExpStr) + for line in output.split('\n'): + if version is None: + match = versionRegExp.match(line) + if match is not None: + version = match.group(1) + + print(self._section, version) + + self._host.PoCConfig[self._section]['Version'] = version From 87023bc47537228087eea4babf2000d1a7d3e5aa Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Nov 2016 14:44:46 +0100 Subject: [PATCH 46/97] Disabled PDF rendering until SphinxContrib.TextStyle gets fixed. --- .readthedocs.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.readthedocs.yml b/.readthedocs.yml index 8b91f62b..cd8a4d65 100644 --- a/.readthedocs.yml +++ b/.readthedocs.yml @@ -1,5 +1,5 @@ -formats: - - pdf +#formats: +# - pdf requirements_file: tools/ReadTheDocs/requirements.txt python: version: 3 From 38572202cb4866f7190ce33e7ebed104e4687d1a Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Nov 2016 15:10:27 +0100 Subject: [PATCH 47/97] Fixes for Landscape.io. --- py/Base/Compiler.py | 4 ++-- py/Base/Shared.py | 26 +++++++++++++------------- py/Base/Simulator.py | 4 ++-- py/Compiler/ISECompiler.py | 4 ++-- py/Compiler/LSECompiler.py | 4 ++-- py/Compiler/QuartusCompiler.py | 4 ++-- py/Compiler/VivadoCompiler.py | 4 ++-- py/Compiler/XCICompiler.py | 4 ++-- py/Compiler/XCOCompiler.py | 4 ++-- py/Compiler/XSTCompiler.py | 4 ++-- py/Simulator/ActiveHDLSimulator.py | 4 ++-- py/Simulator/CocotbSimulator.py | 8 ++++---- py/Simulator/GHDLSimulator.py | 4 ++-- py/Simulator/ISESimulator.py | 4 ++-- py/Simulator/QuestaSimulator.py | 4 ++-- py/Simulator/VivadoSimulator.py | 4 ++-- 16 files changed, 45 insertions(+), 45 deletions(-) diff --git a/py/Base/Compiler.py b/py/Base/Compiler.py index 3c9ba9f1..347170b0 100644 --- a/py/Base/Compiler.py +++ b/py/Base/Compiler.py @@ -149,8 +149,8 @@ class CompileResult(Enum): class Compiler(Shared): """Base class for all Compiler classes.""" - _ENVIRONMENT = Environment.Synthesis - _vhdlVersion = VHDLVersion.VHDL93 + ENVIRONMENT = Environment.Synthesis + VHDL_VERSION = VHDLVersion.VHDL93 class __Directories__(Shared.__Directories__): Netlist = None diff --git a/py/Base/Shared.py b/py/Base/Shared.py index 7fd9b35e..0d230d05 100644 --- a/py/Base/Shared.py +++ b/py/Base/Shared.py @@ -36,12 +36,12 @@ from datetime import datetime from os import chdir -from lib.Functions import Init +from lib.Functions import Init from lib.Parser import ParserException from Base.Exceptions import CommonException, SkipableCommonException from Base.Logging import ILogable from Base.Project import ToolChain, Tool, VHDLVersion, Environment -from DataBase.Solution import VirtualProject, FileListFile +from DataBase.Solution import VirtualProject, FileListFile __api__ = [ @@ -79,10 +79,10 @@ class Shared(ILogable): :param noCleanUp: Don't clean up after a run. """ - _ENVIRONMENT = Environment.Any - _TOOL_CHAIN = ToolChain.Any - _TOOL = Tool.Any - _vhdlVersion = VHDLVersion.VHDL2008 + ENVIRONMENT = Environment.Any + TOOL_CHAIN = ToolChain.Any + TOOL = Tool.Any + VHDL_VERSION = VHDLVersion.VHDL2008 class __Directories__: Working = None @@ -113,7 +113,7 @@ def Host(self): return self._host @property def DryRun(self): return self._dryRun @property - def VHDLVersion(self): return self._vhdlVersion + def VHDLVersion(self): return self.VHDL_VERSION @property def PoCProject(self): return self._pocProject @property @@ -184,7 +184,7 @@ def _PrepareEnvironment_ChangeDirectory(self): raise CommonException("Error while changing to '{0!s}'.".format(self.Directories.Working)) from ex def _Prepare(self): - self.LogNormal("Preparing {0}.".format(self._TOOL.LongName)) + self.LogNormal("Preparing {0}.".format(self.TOOL.LongName)) def _CreatePoCProject(self, projectName, board): # create a PoCProject and read all needed files @@ -193,10 +193,10 @@ def _CreatePoCProject(self, projectName, board): # configure the project pocProject.RootDirectory = self.Host.Directories.Root - pocProject.Environment = self._ENVIRONMENT - pocProject.ToolChain = self._TOOL_CHAIN - pocProject.Tool = self._TOOL - pocProject.VHDLVersion = self._vhdlVersion + pocProject.Environment = self.ENVIRONMENT + pocProject.ToolChain = self.TOOL_CHAIN + pocProject.Tool = self.TOOL + pocProject.VHDLVersion = self.VHDL_VERSION pocProject.Board = board self._pocProject = pocProject @@ -233,7 +233,7 @@ def _GetHDLParameters(self, configSectionName): for keyValuePair in hdlParameters.split(";"): try: key,value = keyValuePair.split("=") - except ValueError as ex: + except ValueError: raise CommonException("Syntax error in option 'HDLParameters' within section {section}.".format(section=configSectionName)) result[key.strip()] = value.strip() return result diff --git a/py/Base/Simulator.py b/py/Base/Simulator.py index 1095515f..9e27ad78 100644 --- a/py/Base/Simulator.py +++ b/py/Base/Simulator.py @@ -131,8 +131,8 @@ class SimulationResult(Enum): class Simulator(Shared): """Base class for all Simulator classes.""" - _ENVIRONMENT = Environment.Simulation - _vhdlVersion = VHDLVersion.VHDL2008 + ENVIRONMENT = Environment.Simulation + VHDL_VERSION = VHDLVersion.VHDL2008 class __Directories__(Shared.__Directories__): PreCompiled = None diff --git a/py/Compiler/ISECompiler.py b/py/Compiler/ISECompiler.py index 33d12e5d..10de1847 100644 --- a/py/Compiler/ISECompiler.py +++ b/py/Compiler/ISECompiler.py @@ -45,8 +45,8 @@ __all__ = __api__ class Compiler(BaseCompiler): - _TOOL_CHAIN = ToolChain.Xilinx_ISE - _TOOL = Tool.Any + TOOL_CHAIN = ToolChain.Xilinx_ISE + TOOL = Tool.Any def __init__(self, host, dryRun, noCleanUp): super().__init__(host, dryRun, noCleanUp) diff --git a/py/Compiler/LSECompiler.py b/py/Compiler/LSECompiler.py index ee8ad2e9..f3e03096 100644 --- a/py/Compiler/LSECompiler.py +++ b/py/Compiler/LSECompiler.py @@ -51,8 +51,8 @@ class Compiler(BaseCompiler): - _TOOL_CHAIN = ToolChain.Lattice_Diamond - _TOOL = Tool.Lattice_LSE + TOOL_CHAIN = ToolChain.Lattice_Diamond + TOOL = Tool.Lattice_LSE def __init__(self, host, dryRun, noCleanUp): super().__init__(host, dryRun, noCleanUp) diff --git a/py/Compiler/QuartusCompiler.py b/py/Compiler/QuartusCompiler.py index 87f8f9ab..3428117c 100644 --- a/py/Compiler/QuartusCompiler.py +++ b/py/Compiler/QuartusCompiler.py @@ -49,8 +49,8 @@ class Compiler(BaseCompiler): - _TOOL_CHAIN = ToolChain.Altera_Quartus - _TOOL = Tool.Altera_Quartus_Map + TOOL_CHAIN = ToolChain.Altera_Quartus + TOOL = Tool.Altera_Quartus_Map def __init__(self, host, dryRun, noCleanUp): super().__init__(host, dryRun, noCleanUp) diff --git a/py/Compiler/VivadoCompiler.py b/py/Compiler/VivadoCompiler.py index 3c53ce67..d269a0c2 100644 --- a/py/Compiler/VivadoCompiler.py +++ b/py/Compiler/VivadoCompiler.py @@ -48,8 +48,8 @@ class Compiler(BaseCompiler): - _TOOL_CHAIN = ToolChain.Xilinx_Vivado - _TOOL = Tool.Xilinx_Synth + TOOL_CHAIN = ToolChain.Xilinx_Vivado + TOOL = Tool.Xilinx_Synth def __init__(self, host, dryRun, noCleanUp): super().__init__(host, dryRun, noCleanUp) diff --git a/py/Compiler/XCICompiler.py b/py/Compiler/XCICompiler.py index f318ee65..05f42b2c 100644 --- a/py/Compiler/XCICompiler.py +++ b/py/Compiler/XCICompiler.py @@ -51,8 +51,8 @@ class Compiler(BaseCompiler): - _TOOL_CHAIN = ToolChain.Xilinx_Vivado - _TOOL = Tool.Xilinx_IPCatalog + TOOL_CHAIN = ToolChain.Xilinx_Vivado + TOOL = Tool.Xilinx_IPCatalog def __init__(self, host, dryRun, noCleanUp): super().__init__(host, dryRun, noCleanUp) diff --git a/py/Compiler/XCOCompiler.py b/py/Compiler/XCOCompiler.py index 6c99253a..43fae3cf 100644 --- a/py/Compiler/XCOCompiler.py +++ b/py/Compiler/XCOCompiler.py @@ -52,8 +52,8 @@ class Compiler(BaseCompiler): - _TOOL_CHAIN = ToolChain.Xilinx_ISE - _TOOL = Tool.Xilinx_CoreGen + TOOL_CHAIN = ToolChain.Xilinx_ISE + TOOL = Tool.Xilinx_CoreGen def __init__(self, host, dryRun, noCleanUp): super().__init__(host, dryRun, noCleanUp) diff --git a/py/Compiler/XSTCompiler.py b/py/Compiler/XSTCompiler.py index 70debbb8..7aae42ef 100644 --- a/py/Compiler/XSTCompiler.py +++ b/py/Compiler/XSTCompiler.py @@ -50,8 +50,8 @@ class Compiler(BaseCompiler, XilinxProjectExportMixIn): - _TOOL_CHAIN = ToolChain.Xilinx_ISE - _TOOL = Tool.Xilinx_XST + TOOL_CHAIN = ToolChain.Xilinx_ISE + TOOL = Tool.Xilinx_XST class __Directories__(BaseCompiler.__Directories__): XSTFiles = None diff --git a/py/Simulator/ActiveHDLSimulator.py b/py/Simulator/ActiveHDLSimulator.py index 4213f480..1799cf9c 100644 --- a/py/Simulator/ActiveHDLSimulator.py +++ b/py/Simulator/ActiveHDLSimulator.py @@ -46,8 +46,8 @@ class Simulator(BaseSimulator): - _TOOL_CHAIN = ToolChain.Aldec_ActiveHDL - _TOOL = Tool.Aldec_aSim + TOOL_CHAIN = ToolChain.Aldec_ActiveHDL + TOOL = Tool.Aldec_aSim def __init__(self, host, dryRun, simulationSteps): super().__init__(host, dryRun, simulationSteps) diff --git a/py/Simulator/CocotbSimulator.py b/py/Simulator/CocotbSimulator.py index 3b30db5a..a73526ea 100644 --- a/py/Simulator/CocotbSimulator.py +++ b/py/Simulator/CocotbSimulator.py @@ -50,9 +50,9 @@ class Simulator(BaseSimulator): - _TOOL_CHAIN = ToolChain.Cocotb - _TOOL = Tool.Cocotb_QuestaSim - _COCOTB_SIMBUILD_DIRECTORY = "sim_build" + TOOL_CHAIN = ToolChain.Cocotb + TOOL = Tool.Cocotb_QuestaSim + COCOTB_SIMBUILD_DIRECTORY = "sim_build" def __init__(self, host, dryRun, simulationSteps): super().__init__(host, dryRun, simulationSteps) @@ -104,7 +104,7 @@ def _RunSimulation(self, testbench): # mccabe:disable=MC0001 raise SimulatorException("Modelsim ini file '{0!s}' not found.".format(precompiledModelsimIniPath)) \ from FileNotFoundError(str(precompiledModelsimIniPath)) - simBuildPath = self.Directories.Working / self._COCOTB_SIMBUILD_DIRECTORY + simBuildPath = self.Directories.Working / self.COCOTB_SIMBUILD_DIRECTORY # create temporary directory for Cocotb if not existent if (not (simBuildPath).exists()): self.LogVerbose("Creating build directory for simulator files.") diff --git a/py/Simulator/GHDLSimulator.py b/py/Simulator/GHDLSimulator.py index 48eb8ba6..1d6e5e15 100644 --- a/py/Simulator/GHDLSimulator.py +++ b/py/Simulator/GHDLSimulator.py @@ -52,8 +52,8 @@ class Simulator(BaseSimulator): """This class encapsulates the GHDL simulator.""" - _TOOL_CHAIN = ToolChain.GHDL_GTKWave - _TOOL = Tool.GHDL + TOOL_CHAIN = ToolChain.GHDL_GTKWave + TOOL = Tool.GHDL class __Directories__(BaseSimulator.__Directories__): GTKWBinary = None diff --git a/py/Simulator/ISESimulator.py b/py/Simulator/ISESimulator.py index d90d1305..49a6073e 100644 --- a/py/Simulator/ISESimulator.py +++ b/py/Simulator/ISESimulator.py @@ -48,8 +48,8 @@ class Simulator(BaseSimulator, XilinxProjectExportMixIn): - _TOOL_CHAIN = ToolChain.Xilinx_ISE - _TOOL = Tool.Xilinx_iSim + TOOL_CHAIN = ToolChain.Xilinx_ISE + TOOL = Tool.Xilinx_iSim def __init__(self, host, dryRun, simulationSteps): super().__init__(host, dryRun, simulationSteps) diff --git a/py/Simulator/QuestaSimulator.py b/py/Simulator/QuestaSimulator.py index 0f19f039..cc9a52a0 100644 --- a/py/Simulator/QuestaSimulator.py +++ b/py/Simulator/QuestaSimulator.py @@ -48,8 +48,8 @@ class Simulator(BaseSimulator): - _TOOL_CHAIN = ToolChain.Mentor_QuestaSim - _TOOL = Tool.Mentor_vSim + TOOL_CHAIN = ToolChain.Mentor_QuestaSim + TOOL = Tool.Mentor_vSim def __init__(self, host, dryRun, simulationSteps): # A separate elaboration step is not implemented in QuestaSim diff --git a/py/Simulator/VivadoSimulator.py b/py/Simulator/VivadoSimulator.py index 0f41c283..6a3ecc5c 100644 --- a/py/Simulator/VivadoSimulator.py +++ b/py/Simulator/VivadoSimulator.py @@ -49,8 +49,8 @@ class Simulator(BaseSimulator, XilinxProjectExportMixIn): - _TOOL_CHAIN = ToolChain.Xilinx_Vivado - _TOOL = Tool.Xilinx_xSim + TOOL_CHAIN = ToolChain.Xilinx_Vivado + TOOL = Tool.Xilinx_xSim def __init__(self, host, dryRun, simulationSteps): super().__init__(host, dryRun, simulationSteps) From 41df09ba7a333e24d9fade36c2f7f5b0afe3dd3d Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Nov 2016 15:22:15 +0100 Subject: [PATCH 48/97] Why does RTFD use other image paths? --- docs/UsingPoC/Download.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/UsingPoC/Download.rst b/docs/UsingPoC/Download.rst index 4f4d9c31..724f6873 100644 --- a/docs/UsingPoC/Download.rst +++ b/docs/UsingPoC/Download.rst @@ -15,11 +15,11 @@ Downloading from GitHub The PoC-Library can be downloaded as a zip-file from GitHub. See the following table, to choose your desired git branch. -.. |zip-master| image:: /_static/icons/ZIP.png +.. |zip-master| image:: _static/icons/ZIP.png :scale: 40 :target: https://github.com/VLSI-EDA/PoC/archive/master.zip :alt: Source Code from GitHub - 'master' branch. -.. |zip-release| image:: /_static/icons/ZIP.png +.. |zip-release| image:: _static/icons/ZIP.png :scale: 40 :target: https://github.com/VLSI-EDA/PoC/archive/release.zip :alt: Source Code from GitHub - 'release' branch. From c18126be44492882489764e4d857ea220d116aea Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Nov 2016 15:24:42 +0100 Subject: [PATCH 49/97] Removed color role. --- src/mem/ocram/ocram_esdp.vhdl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mem/ocram/ocram_esdp.vhdl b/src/mem/ocram/ocram_esdp.vhdl index 09583151..b6a70ed2 100644 --- a/src/mem/ocram/ocram_esdp.vhdl +++ b/src/mem/ocram/ocram_esdp.vhdl @@ -16,9 +16,9 @@ -- -- .. deprecated:: 1.1 -- --- :color:`Please use ` :ref:`IP:ocram_tdp` :color:`for new designs. +-- **Please use** :ref:`IP:ocram_tdp` **for new designs. -- This component has been provided because older FPGA compilers where not --- able to infer true dual-port memory from an RTL description. ` +-- able to infer true dual-port memory from an RTL description.** -- -- Command truth table for port 1: -- From 776c981bb32ace8f346b24643471ecf281776467 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Nov 2016 15:29:34 +0100 Subject: [PATCH 50/97] Reverted image paths for ZIP file icon. --- docs/UsingPoC/Download.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/UsingPoC/Download.rst b/docs/UsingPoC/Download.rst index 724f6873..4f4d9c31 100644 --- a/docs/UsingPoC/Download.rst +++ b/docs/UsingPoC/Download.rst @@ -15,11 +15,11 @@ Downloading from GitHub The PoC-Library can be downloaded as a zip-file from GitHub. See the following table, to choose your desired git branch. -.. |zip-master| image:: _static/icons/ZIP.png +.. |zip-master| image:: /_static/icons/ZIP.png :scale: 40 :target: https://github.com/VLSI-EDA/PoC/archive/master.zip :alt: Source Code from GitHub - 'master' branch. -.. |zip-release| image:: _static/icons/ZIP.png +.. |zip-release| image:: /_static/icons/ZIP.png :scale: 40 :target: https://github.com/VLSI-EDA/PoC/archive/release.zip :alt: Source Code from GitHub - 'release' branch. From 0b2c5f77a5cc5ef76dac9da3943e6be9f628be6c Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Nov 2016 15:52:53 +0100 Subject: [PATCH 51/97] Added missing images. --- docs/_static/icons/ZIP.png | Bin 0 -> 597 bytes docs/_static/io/iic_Controller_Usage.graphml | 111 +++++++++++++++++++ docs/_static/io/iic_Controller_Usage.png | Bin 0 -> 9219 bytes 3 files changed, 111 insertions(+) create mode 100644 docs/_static/icons/ZIP.png create mode 100644 docs/_static/io/iic_Controller_Usage.graphml create mode 100644 docs/_static/io/iic_Controller_Usage.png diff --git a/docs/_static/icons/ZIP.png b/docs/_static/icons/ZIP.png new file mode 100644 index 0000000000000000000000000000000000000000..9d2a8589e66d8834fd6a23ee7d106014aee2b201 GIT binary patch literal 597 zcmV-b0;>IqP)$kFx~iS) z?$@tBcV|re%qDI>9YAXatqg1fSHLcy->W?Dz#O;$^gDSh0A%nBusJ5I^7AiXZw!P5 zz&&tO**L4X2jDn$*#h9Rf%m=53Zb1+06&oc3uvo{hwf$Rvlx>lu*7or-z~huYhL#Q{Z;p078A= zZab4PT6kn&iUBdV5BM2hOekE(PE`g%WoN)0AXc<)>R12_-C26%A3~SP0k6m#Aup=z z`E@e|Krt_tE?pk^uxrAAc2zCjV&EjOz>>teF2Kqe0UA5iL+HkZ&5#FE0F<;_E^kzY ztS#&(L00000NkvXXu0mjf*jEIJ literal 0 HcmV?d00001 diff --git a/docs/_static/io/iic_Controller_Usage.graphml b/docs/_static/io/iic_Controller_Usage.graphml new file mode 100644 index 00000000..63bf666c --- /dev/null +++ b/docs/_static/io/iic_Controller_Usage.graphml @@ -0,0 +1,111 @@ + + + + + + + + + + + + + + + + + + + + + + + + iic_Controller + + + + + + + + + + + + iic_BusController + + + + + + + + + + + + pb_IIC_Adapter + + + + + + + + + + + + iic_Switch_PCA95a8A + + + + + + + + + + + + wb_IIC_Adapter + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/docs/_static/io/iic_Controller_Usage.png b/docs/_static/io/iic_Controller_Usage.png new file mode 100644 index 0000000000000000000000000000000000000000..37b03b8157a9d609cd81260629b5ef9d0ef232a5 GIT binary patch literal 9219 zcmch7c{G%5`2QefN#3{38=;lnL~qt2Ar-POr7%=>V@Sh{B}=8e5s7SL%^G71gE5Sx zh>U%#Ge(xN4lh}<_PZano%8#h^E>Bz&bL1_Gtd3p&vjqdbzj%#^SPg=dOB)6T>M-x z7>q|l{gMF;#+D2|GdNhmUu9yR91M1}UgMIAk$Vp_-uF`c+PB(Tt+1FgQc^LoR!)Q{ zT3C$u9$L4eRLPkYtFUJc4O%tGMc$YLF;-zOtR%aSg=-|Yims$8h}50gqY-v2Oe17+ zWp$yTWP&6=B5#~wF%qXJo)M^!JR998-u`#_DZpC zn+=4qz?#jHqF?;HR~f(kP~PZSuv*EzVF$NyC<6nOQL4=y9UZN$l2TIP?}-b9Z;gi97a%{WCT*PQeWoS7u~n3=53wEzeC&P0i2G`;`vNXZMp* zO6-nWl)ImimL4)q^O@^Y{pe)PbHQt2k{l~1CMKq_Xf3aE(lt)-Kn2F~**tscqZw9Z z5yaHz>VSEPh@xYCX+8T<`Z@ zba!{RfSl8$`SEm<9oyVzhcp!F6w0tyoV2i#&zyBqsn_CEB>#+)#@D&C=*b)RdM!*$ z%9g$z-@kY7sZ*y)JN+kbvUscAODZWXp_jRR$_c!ZvV&J>PBzyk{%#>&VjXE>qf=d}`O7yKzadCOW6J@fmU~PTf zNA9D86_t&AjoV=dnHB{@AP_hlZaAG(tC2!&+W{xtClnSI5{bn0^qPD2ckljl|7f2$ zXQEJVJGHmOdBQN^yvGq1JhDT!i~Hh2wjb$e(?7?(m*?zJsKRb7Rnxk$ScC|@bJQPCoQP6qht2V7a7m8huA+NR1uead4hk5!c6r<;! zbvQ`v=i|%l=-sI&k_vZF>t5+h_a*&0o+c9EH7Sy4ML(5lQ)%G<0=N%IgZXhUX6*5+6BG-Il+?(ho5gZq} zx@_iM7${d$BcMJgBa}_>QZi#x&a%rrH#%7RoEBF<)|NpVwL~BnK7q{BcF%G;Pj;*H zLZi{17J1v{60QGw{`fIF!s^bQBd1R{i6l~cs;a7vs)cl=k6Rn(na?{o85)L9+gi}C z)KGb4$+xVmt-Bi{7o!xAPcok)GLn}>53;80g+`|xujg2LPZP^zEWpZtcb~x(4>W(z!j);hm{d}^GVmaO2z(Ttk>FA{q{PEV@*Q!T5 z4wnRMxJD~v%&%+-E~lC&=UF*u@90{W*V5|Q#?UG9IK<<0UKzD$UAo<`z11w3b=fCd zr7AG^%SBV%;cA~gMHE9T8U-7$&n5Zx+9hX2&RuA|o4ucln|uCiUAQPC#VIF#1k{`K zys^_3q$1(l$VX98Q6Tqa-WB8V^NWjg0!j@h?Ic3wb*O)@&Tfv7$?y5g#MBgro=e4q z)c3r&|1p}zTW>T0&*~Uyj4!NC9V&X?JfnS9CM|`bc-x3llAdnk;BXZuFE2mWfJbza zoXqB}PnX_bDj-jq1kWKOPAfi?YdEsThI zq-3$CPRG6+k=5~(G1hg+k&g9DU-Y&Q3|8;(gEnj(yTT2;^m48_G5-=57w;Bhid~Ji5E2y?y+)zFuhc#j z{QSAtnO(>vBagY!7YR*ub#E@mj(uBOq{}%+Oc%ZL<0-uQZL(X+t51h}7fQ#WL9^Lt zOj~=S)L6ziG7fX$Aq54~6`b3s2yH9L7qSLXONzXg<}~F1*j8lf)9I78*QeS0(HCE} znFUAerc2p2mRgYSV+EX*+yib!Y+JErcF9df6h~#pW2XCF5s2^{e7LIlw6Nb*QeYf; z=gkjz%bb*(Mn z8s~q`=AylA%U|^ey@KZXEoOV`=n_ko4!HvAdt`-lQHzMp%_ApY`lkA1cn)RJ##BK` z$r({mdHzYKnPTx(#>#>j*dxxp+S=NjDX(*LFZ{txbpP;VdUDcnak-}EN(SL%nXFgF z6=^$?&zff;qo$WPR;DB=DQTGQzSwnrT3ZFLlWfxK8loV$Fj2!h%Bf`S?tY`deZ2ke z>2OdZ@7Db{JFKago0Vl?5D^s>8)x65Ai6gjID$cJdl*mQH%GDMs_J$@OJ9VK(^~9| z&P_74?-@?Roy9{J78d-Rtk+uL?-#zYMULPszcOD9re3Voh_;LkusDz}XsB@X#MvJ! z-YTUI_PIorbZy_V)62!hpwI1(jg75vi1ugnP@|t{%8A*ywOqBiTbM;cU$sUekpVk! z1#WI`S*3l`ix!pfdUjX@UzkPd-70}hUDP0R2k|BO$t@zgfsRhdwYA5O9|!OXJ4iW( zaFJ<+4os3O!PhD@Dhl)o_>nL%w(h;}EOh|bB+Zw%z=GGr581A9trwf=ASsBvIsl?Hw8S`6cu`Ecj^P#v zq{OZ~rl?Nbze{<=<)s3{S!H5!)amFcV{Yq^#g(vqw_b%EK;iC>{h5E8m_evg6w{*X ze=b3x=7;srhzyBRg`A!XE!=yt@Konm!RDOyBzRF)rDqgPwX<<2XQ85NoYBNtPBmwR zmdh8igg$!$Jm>t*E;nxvQb_%g0B>pAJJQaLk|&l}*qWyDo=o$ZkBdbduP>41B=6(b zy4FD586!j`VorbN5Oefzg)zO%Bf8?H)6rCp*ZN&P&(I@`o_+S{kf`l9d;eJ>i@7V= z@kS3!EKw*F0^!{BaTNzTJn{i!${OGCrumFpc%J;gZ6`zL&TztM*?|CIpZqp09%7vz zY22O9Tj`E_$@?fF7J*_ftN^v}-JGC!$g^jq-!#&9^!bk9c9v+;XiDlRZ`mYMa${qU zq6^Pu2PxwBme?=~H#Q!b>PyS|EG>O|c12#l;emA03=E*T&-^e0O;k>zu8z+3Rm~aQ z#0$sQcxx@Qo?MXF{nWqG(#btCDr%5MH9l;oOkaJ)xu`15PZ6LY`ExR#K7A@k6*Za| zVr^GxdBE{SyDq@U(a!F~(9@@!B~?*Ez1{h1%$uIh<)%wMOS6}~98rz66W6PzlLu4n zq3y=+6MnWz-bS=1vu4p9R28Fks(7&4^kDy*nx4i^6tTteFN1FgMT-1<;V7|(F)a?U z0vJ7rk(-@;@ZU#^tbI8Jn&e~x{TjZn_SAB2@d0ugATg@s>5a4YO5J@qq3m6HblIFxi0&@jCQv|m_QnD6>hz+QIwT`a6v zZaWDq_W`$UOfGVvZPTuuJ3|4%I;^aWVj*8f9Zr$%%#WeDV~|H7dgTYr7{oBhX){0t zgB^B`(ID|R7sQvO`I^n7qa5OEu!xtDkyp_bQpD5~%`QJIa_d3l>YJHO+MqS`A!8<= zgcOyOloSFTZsi2^>P8x&AnTpSV-f-D}h28f#-4B3#T}4aD z1lmeBnP4ZeI>BLcta5cWXggVH{p+K>?59Fuw`<*ohU&sSNjTi6#k2NTH8tg)4*_2B zatW#Azc@`72E3+s_LXV?KshD!*~!VtU;(+I^tuY#k7=z)41PWdvqP6zxQ{7!xd>+F zqK)t}b54DahN~d-)~6xuy!|&ShTCGv(#wEh#R}dMxMM2e@R}$fr-An8oL(V(@tU>gs)h zGvFq2$sIg3H8te|Hi@|4rJm?gu zM&$ChOVvIXmaA4kPe$)g!xS$}(TFDH9$(VM`$}D^O*uk@6dk1SyPc4J31gF!b3W9D zhG%=!G7DqrGVR#di^WYjuV3e*-vi!xyxXEudzc@TQ_m~7$q(i#ymm^;C~Icl9`V`P zSq6hKX?;eC9m>RN8RL}HD?6r&U?AW8z1yj%kw$xct}Yr)yh^4``)mdR8yg?*?fxh( z?x1+WS(oI>N;)p~jEwP>*R@J(b8Q*AiII_!SvcJB_{g`GmX_BKiHL{{co%6eGDb!) zuC5;ok9U}4=j6=$U7EwyKNUy`C@hWw&%}VNqQW zjLe*vkh)Aljp*3gW-JyuM%=Yk`1&t|;zS1uP{b=_g`iachfPfl4O2eQeOAc(y+;^W zzYE^W(pD=o(#HCu4_@{pU{I}q)o=Mn3Q|2Tsc!$q&NF&;8%JgmVY;uPFmb+Q`EOGA z{!~A(WZ9V|us_IHMA?{*$$usV&-Bu&(w#HX(!M9eJDPq1Kd@%<*;(7MNo58^poCIuEE`}+E#6CW~?38D5_AT!*g=U)zl zO4Ds$na=c+%uClSJv`2Fl4U06+Hl5s@-$Z`<7?N3DbzfHj6X)}gnhnNIlO=YgzUd&@by5BO8qV{|;Svod;U!Fx}F(0T>r%#>wnyVlF z2SQ)iHmC|K#?IS8?OzzQck=bE6dD>D>blA0aES%&>Ka{|0_?fFZL=0Hn4l_sVr?S= zX+YwTP*ZRj@ErpnFLgPZ;J3X<_-+P! zugx0L(Xpr(I5OfxxVuTd91f&E0iPLS=ef^9*mSc+*3z=#{?obq#;`y4!T0VxC7Q00cx#rr<~^ zrwl0I#<33jac>7X?aCL}q%lrTjYQpCGr~Y_vMQ*4{aZ5IWNgT#lorr}{liO5tpP@) zRo|8}k&%=vC@$WQVlFQ)4-Huz+dZ?6V?QlvIjuzC5Y9Y*p~1sdqbTo2k-*?(e~@9y zkiu7fM7hgW@C7^R`J=UO{~XGLc_QK41;q%4foyz8~2+E-CK`pUW zLoK;wRPW%EfPn70p?yEJyu)y}Z7?!>-~kp^;2+S~JRUPxKRnyZ4(WVk_MfiX>Y{iN zWtjY~q@#8cNgH$j(o#A8_$UUoz>i|md?$c_IJ6JytI)F!su=9uytdIEwf$g2`viAD zUHZG!2u-=sm%mT)|6@}v3)F9)T-7d5J*%uLTthvCrzJA@S)_iP=(TkD3q z`Cx)9A5W0o3VLZY?ah$FT(^D1J!>@+C4K|LHW3`RU&vcbym8D`7nd2|^)JHT9|CN$ z*=yUBa2fKGG#?Z|IaL0qmgJTbn<>W9Y<4KGHS_hhhW>k;{99{KHg{1yqpSvm?2Tu= zY^M$k+*w!L_G5`Dgw;Ze4c~)Nl2=ihSFiSwyaj@nA1h%1E{a(hPSV~?)_4f3bn3#a(7v?nxK&Pcd;D-+% z089enb6{X#Sy|cG*qAt8>Fn9A0+n~hj{7My|-p{>FK=zk|WdBM7;jAb);hwcZfGrxmP!lY0I~%)o zI0BUv?+mO01cNC9OJ7DTob}Ai92>K)-R7U3p2ql`S^;W2rI*5i)!aBufo@1EV}N-z z%=!5EkS=z1>Oo(=d?`LFFQ4@RaLo*Y@P+$!NF;M~^adPGOJ@L1H{qh8@ziSutlh_l zL@jys>afnrRhy04h}*#e)j(qymmTUdLeA zC`NX5&t-X$0ro38d+waQr|0^rhnyGChXoi$GnqgRKf`gr1b1(OnHY}3T$Jb>~w6?acsHgzq@XP2j zq`A3yV`F3F$}ie*U{Fwnz~3G~A!3e?O9pfZP;^vO9thD%-n}}9BC`>RqcI>L_>_@( z2*LD*7@5|X!Qt9lZ5Qfsi#jM{V`E-qK8dtG+H$nwkf>UI{{px(w9pP|vL#Bs>#Gwr2lJ;d7V!#S=-OXq$lhQbk41c9=I-iY>k&0^ zo9sF>eWh%VsF@*Ph9nf~_?qk+WRO#!r?vG5{9vqQdbIvle_ETfIu(Q#ej!RHNSG-X2>)o=LT)j#6A zo2lSA<4ajtCpj%VJP71MhZY50`iw386---4LB|0 zeg6*ruLz<24jNtTrDmt{jLmPlu!=dhl_g?Cn!pa+kfl zyp&__Arx8wDKD;m6oY`n=1dvl$QnK zvsxh_U<#TlUbBGS_3T!NVj~~l0Af%DTQEd@_z=WbVPGdIn(AWyCA>*v4=yXKL9*J> z+K*9xomtMI4^Fj=F`P)PyRousaq;oY6=$okd()5Y(8M!!2sbx;k2FS(>}I2M42xZwd+|ofYgPexN

*(%7rB~Oav5bju8Uv?T7c|PCYSK%cq#qZah>e#!u3OH}Y z$V!&r$i%%-2q-s^@nWr$IvhYeF1~GOXy|lw7~gu+BEN?%{i|oIQ@VnjoTvcWR{OO# zMqluk`o}C}I6VdG)l#~CN!@q!%jr=|6@OD+esFr76nN+U{rg`6Jm-xB7~Hb_!Q=4d z353I)J9lg`+)#glfE`Hdl2>}gix+nFecKahATDZEYkM0yzTQHg*Rb|epesB$TM8~a zh^G*Y5XvadKcFTh$I@cwdSX{~b#-RRdm> zrSGtKavOAFUaa==<;&GCO-jFtKObKowJUj`0QlkCx3FL2B0hjFcw)PQF@>_w5j}+9 zAU;Qt7nkY$x-^n#**FP~>3?WZnH~1oge&&;nO2<&g_;{Qa}%ehnPgNj_(30ZvWfad z)LL1)KJjcQ%EAY<#HGRKO6vM=S;6{2U1~9tmTN1$`#H< z4@FDI`w7aFGgcm7_7G*Y{ESV5u_zBB456A#bCZzH2eKf z&MrQ&n*!T!WqDbBLk8RQXy{?J{M6L;W`yRAh5uGK{CI9 zkj*|))PG}!C{#%v-YNId%WhF@3?xBKUbT17AdSm9mvS%OdiZ|;`ZS!n literal 0 HcmV?d00001 From e659fbc02125f06758b4b4be6079df244bb9a48d Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Nov 2016 16:22:51 +0100 Subject: [PATCH 52/97] Deactivated textstyle extenstion in Sphinx. --- docs/conf.py | 2 +- tools/ReadTheDocs/requirements.txt | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/conf.py b/docs/conf.py index 5a49b1cd..a90739dd 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -51,7 +51,7 @@ # 'sphinxcontrib.actdiag', # 'sphinxcontrib.seqdiag', 'sphinxcontrib.wavedrom', - 'sphinxcontrib.textstyle', + # 'sphinxcontrib.textstyle', # 'sphinxcontrib.spelling', 'autoapi.sphinx', # 'changelog', diff --git a/tools/ReadTheDocs/requirements.txt b/tools/ReadTheDocs/requirements.txt index a45043ce..c69a1670 100644 --- a/tools/ReadTheDocs/requirements.txt +++ b/tools/ReadTheDocs/requirements.txt @@ -4,7 +4,7 @@ sphinxcontrib-autoprogram>=0.1.3 #sphinxcontrib-actdiag>=0.8.5 #sphinxcontrib-seqdiag>=0.8.5 sphinxcontrib-wavedrom>=1.2.0 -sphinxcontrib-textstyle>=0.2.1 +# sphinxcontrib-textstyle>=0.2.1 # sphinxcontrib-spelling>=2.2.0 autoapi # changelog>=0.3.5 From b47d1c5434653a8c160130f8a6427d29da6ac1ff Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Nov 2016 17:15:44 +0100 Subject: [PATCH 53/97] Minor fixes. --- docs/GetInvolved/Authors.rst | 22 ---------------------- docs/GetInvolved/index.rst | 20 ++++++++++++++++++-- docs/IPCores/mem/ocram/ocram_esdp.rst | 4 ++-- py/Base/Shared.py | 8 +++++--- py/Base/Simulator.py | 4 ++++ py/Compiler/LSECompiler.py | 3 +-- py/Compiler/QuartusCompiler.py | 2 -- py/Compiler/VivadoCompiler.py | 3 --- py/Compiler/XCICompiler.py | 2 -- py/Compiler/XCOCompiler.py | 2 -- py/Compiler/XSTCompiler.py | 6 ++---- py/PoC.py | 2 +- py/Simulator/ActiveHDLSimulator.py | 4 ---- py/Simulator/GHDLSimulator.py | 3 --- py/Simulator/ISESimulator.py | 3 --- py/Simulator/QuestaSimulator.py | 4 ---- py/Simulator/VivadoSimulator.py | 4 ---- 17 files changed, 33 insertions(+), 63 deletions(-) delete mode 100644 docs/GetInvolved/Authors.rst diff --git a/docs/GetInvolved/Authors.rst b/docs/GetInvolved/Authors.rst deleted file mode 100644 index 611c545e..00000000 --- a/docs/GetInvolved/Authors.rst +++ /dev/null @@ -1,22 +0,0 @@ -.. # This file is included. So it needs to be marked as orphan to suppress warnings. - -:orphan: - -========================= ============================================================ -Contributor [#f1]_ Contact E-Mail -========================= ============================================================ -Genßler, Paul paul.genssler@tu-dresden.de -Köhler, Steffen steffen.koehler@tu-dresden.de -Lehmann, Patrick [#f2]_ patrick.lehmann@tu-dresden.de; paebbels@gmail.com -Preußer, Thomas B. [#f2]_ thomas.preusser@tu-dresden.de; thomas.preusser@utexas.edu -Reichel, Peter peter.reichel@eas.iis.fraunhofer.de; peter@peterreichel.info -Schirok, Jan janschirok@gmx.net -Voß, Jens jens.voss@mailbox.tu-dresden.de -Zabel, Martin [#f2]_ martin.zabel@tu-dresden.de -========================= ============================================================ - - -.. rubric:: Footnotes - -.. [#f1] In alphabetical order. -.. [#f2] Maintainer. diff --git a/docs/GetInvolved/index.rst b/docs/GetInvolved/index.rst index 0eda9dec..ca4d7589 100644 --- a/docs/GetInvolved/index.rst +++ b/docs/GetInvolved/index.rst @@ -233,5 +233,21 @@ story on how you use PoC. List of Contributers ******************** -.. include:: ./Authors.rst - +========================= ============================================================ +Contributor [#f1]_ Contact E-Mail +========================= ============================================================ +Genßler, Paul paul.genssler@tu-dresden.de +Köhler, Steffen steffen.koehler@tu-dresden.de +Lehmann, Patrick [#f2]_ patrick.lehmann@tu-dresden.de; paebbels@gmail.com +Preußer, Thomas B. [#f2]_ thomas.preusser@tu-dresden.de; thomas.preusser@utexas.edu +Reichel, Peter peter.reichel@eas.iis.fraunhofer.de; peter@peterreichel.info +Schirok, Jan janschirok@gmx.net +Voß, Jens jens.voss@mailbox.tu-dresden.de +Zabel, Martin [#f2]_ martin.zabel@tu-dresden.de +========================= ============================================================ + + +.. rubric:: Footnotes + +.. [#f1] In alphabetical order. +.. [#f2] Maintainer. diff --git a/docs/IPCores/mem/ocram/ocram_esdp.rst b/docs/IPCores/mem/ocram/ocram_esdp.rst index 59a0c643..ac2be841 100644 --- a/docs/IPCores/mem/ocram/ocram_esdp.rst +++ b/docs/IPCores/mem/ocram/ocram_esdp.rst @@ -24,9 +24,9 @@ Inferring / instantiating enhanced simple dual-port memory, with: .. deprecated:: 1.1 - :color:`Please use ` :ref:`IP:ocram_tdp` :color:`for new designs. + **Please use** :ref:`IP:ocram_tdp` **for new designs. This component has been provided because older FPGA compilers where not - able to infer true dual-port memory from an RTL description. ` + able to infer true dual-port memory from an RTL description.** Command truth table for port 1: diff --git a/py/Base/Shared.py b/py/Base/Shared.py index 0d230d05..c82cbbec 100644 --- a/py/Base/Shared.py +++ b/py/Base/Shared.py @@ -96,9 +96,11 @@ def __init__(self, host, dryRun): self._host = host self._dryRun = dryRun - self._pocProject = None self._directories = self.__Directories__() + self._toolChain = None + self._vhdlVersion = self.VHDL_VERSION + self._vhdlGenerics = None self._testSuite = None self._startAt = datetime.now() @@ -113,7 +115,7 @@ def Host(self): return self._host @property def DryRun(self): return self._dryRun @property - def VHDLVersion(self): return self.VHDL_VERSION + def VHDLVersion(self): return self._vhdlVersion @property def PoCProject(self): return self._pocProject @property @@ -196,7 +198,7 @@ def _CreatePoCProject(self, projectName, board): pocProject.Environment = self.ENVIRONMENT pocProject.ToolChain = self.TOOL_CHAIN pocProject.Tool = self.TOOL - pocProject.VHDLVersion = self.VHDL_VERSION + pocProject.VHDLVersion = self._vhdlVersion pocProject.Board = board self._pocProject = pocProject diff --git a/py/Base/Simulator.py b/py/Base/Simulator.py index 9e27ad78..df7a6cc6 100644 --- a/py/Base/Simulator.py +++ b/py/Base/Simulator.py @@ -150,6 +150,10 @@ def __init__(self, host, dryRun, simulationSteps : SimulationSteps): """ super().__init__(host, dryRun) + self._vhdlVersion = None + self._vhdlGenerics = None + self._toolChain = None + self._simulationSteps = simulationSteps self._testSuite = TestSuite() # TODO: This includes not the read ini files phases ... self._state = SimulationState.Prepare diff --git a/py/Compiler/LSECompiler.py b/py/Compiler/LSECompiler.py index f3e03096..e39c11e2 100644 --- a/py/Compiler/LSECompiler.py +++ b/py/Compiler/LSECompiler.py @@ -57,8 +57,7 @@ class Compiler(BaseCompiler): def __init__(self, host, dryRun, noCleanUp): super().__init__(host, dryRun, noCleanUp) - self._toolChain = None - self._vhdlVersion = VHDLVersion.VHDL2008 + self._vhdlVersion = VHDLVersion.VHDL2008 configSection = host.PoCConfig['CONFIG.DirectoryNames'] self.Directories.Working = host.Directories.Temp / configSection['LatticeSynthesisFiles'] diff --git a/py/Compiler/QuartusCompiler.py b/py/Compiler/QuartusCompiler.py index 3428117c..a9615704 100644 --- a/py/Compiler/QuartusCompiler.py +++ b/py/Compiler/QuartusCompiler.py @@ -55,8 +55,6 @@ class Compiler(BaseCompiler): def __init__(self, host, dryRun, noCleanUp): super().__init__(host, dryRun, noCleanUp) - self._toolChain = None - configSection = host.PoCConfig['CONFIG.DirectoryNames'] self.Directories.Working = host.Directories.Temp / configSection['QuartusSynthesisFiles'] self.Directories.Netlist = host.Directories.Root / configSection['NetlistFiles'] diff --git a/py/Compiler/VivadoCompiler.py b/py/Compiler/VivadoCompiler.py index d269a0c2..062da16d 100644 --- a/py/Compiler/VivadoCompiler.py +++ b/py/Compiler/VivadoCompiler.py @@ -54,9 +54,6 @@ class Compiler(BaseCompiler): def __init__(self, host, dryRun, noCleanUp): super().__init__(host, dryRun, noCleanUp) - self._device = None - self._toolChain = None - configSection = host.PoCConfig['CONFIG.DirectoryNames'] self.Directories.Working = host.Directories.Temp / configSection['VivadoSynthesisFiles'] self.Directories.XSTFiles = host.Directories.Root / configSection['VivadoSynthesisFiles'] diff --git a/py/Compiler/XCICompiler.py b/py/Compiler/XCICompiler.py index 05f42b2c..7fb864fe 100644 --- a/py/Compiler/XCICompiler.py +++ b/py/Compiler/XCICompiler.py @@ -57,8 +57,6 @@ class Compiler(BaseCompiler): def __init__(self, host, dryRun, noCleanUp): super().__init__(host, dryRun, noCleanUp) - self._toolChain = None - configSection = host.PoCConfig['CONFIG.DirectoryNames'] self.Directories.Working = host.Directories.Temp / configSection['VivadoIPCatalogFiles'] self.Directories.Netlist = host.Directories.Root / configSection['NetlistFiles'] diff --git a/py/Compiler/XCOCompiler.py b/py/Compiler/XCOCompiler.py index 43fae3cf..4df12c15 100644 --- a/py/Compiler/XCOCompiler.py +++ b/py/Compiler/XCOCompiler.py @@ -58,8 +58,6 @@ class Compiler(BaseCompiler): def __init__(self, host, dryRun, noCleanUp): super().__init__(host, dryRun, noCleanUp) - self._toolChain = None - configSection = host.PoCConfig['CONFIG.DirectoryNames'] self.Directories.Working = host.Directories.Temp / configSection['ISECoreGeneratorFiles'] self.Directories.Netlist = host.Directories.Root / configSection['NetlistFiles'] diff --git a/py/Compiler/XSTCompiler.py b/py/Compiler/XSTCompiler.py index 7aae42ef..78b193b6 100644 --- a/py/Compiler/XSTCompiler.py +++ b/py/Compiler/XSTCompiler.py @@ -60,12 +60,10 @@ def __init__(self, host, dryRun, noCleanUp): super().__init__(host, dryRun, noCleanUp) XilinxProjectExportMixIn.__init__(self) - self._toolChain = None - configSection = host.PoCConfig['CONFIG.DirectoryNames'] - self.Directories.Working = host.Directories.Temp / configSection['ISESynthesisFiles'] + self.Directories.Working = host.Directories.Temp / configSection['ISESynthesisFiles'] self.Directories.XSTFiles = host.Directories.Root / configSection['ISESynthesisFiles'] - self.Directories.Netlist = host.Directories.Root / configSection['NetlistFiles'] + self.Directories.Netlist = host.Directories.Root / configSection['NetlistFiles'] self._PrepareCompiler() diff --git a/py/PoC.py b/py/PoC.py index ba0f4737..b57fad15 100644 --- a/py/PoC.py +++ b/py/PoC.py @@ -216,7 +216,7 @@ def __init__(self, *args, **kwargs): self.__repo = None self.__directories = {} - self.__SimulationDefaultVHDLVersion = BaseSimulator._vhdlVersion + self.__SimulationDefaultVHDLVersion = BaseSimulator.VHDL_VERSION self.__SimulationDefaultBoard = None self._directories = self.__Directories__() diff --git a/py/Simulator/ActiveHDLSimulator.py b/py/Simulator/ActiveHDLSimulator.py index 1799cf9c..afd4906a 100644 --- a/py/Simulator/ActiveHDLSimulator.py +++ b/py/Simulator/ActiveHDLSimulator.py @@ -52,10 +52,6 @@ class Simulator(BaseSimulator): def __init__(self, host, dryRun, simulationSteps): super().__init__(host, dryRun, simulationSteps) - self._vhdlVersion = None - self._vhdlGenerics = None - self._toolChain = None - activeHDLFilesDirectoryName = host.PoCConfig['CONFIG.DirectoryNames']['ActiveHDLFiles'] self.Directories.Working = host.Directories.Temp / activeHDLFilesDirectoryName self.Directories.PreCompiled = host.Directories.PreCompiled / activeHDLFilesDirectoryName diff --git a/py/Simulator/GHDLSimulator.py b/py/Simulator/GHDLSimulator.py index 1d6e5e15..4ffb9eab 100644 --- a/py/Simulator/GHDLSimulator.py +++ b/py/Simulator/GHDLSimulator.py @@ -62,9 +62,6 @@ def __init__(self, host, dryRun, simulationSteps): """Constructor""" super().__init__(host, dryRun, simulationSteps) - self._vhdlGenerics = None - self._toolChain = None - ghdlFilesDirectoryName = host.PoCConfig['CONFIG.DirectoryNames']['GHDLFiles'] self.Directories.Working = host.Directories.Temp / ghdlFilesDirectoryName self.Directories.PreCompiled = host.Directories.PreCompiled / ghdlFilesDirectoryName diff --git a/py/Simulator/ISESimulator.py b/py/Simulator/ISESimulator.py index 49a6073e..43f7c3e2 100644 --- a/py/Simulator/ISESimulator.py +++ b/py/Simulator/ISESimulator.py @@ -55,9 +55,6 @@ def __init__(self, host, dryRun, simulationSteps): super().__init__(host, dryRun, simulationSteps) XilinxProjectExportMixIn.__init__(self) - self._vhdlGenerics = None - self._toolChain = None - iseFilesDirectoryName = host.PoCConfig['CONFIG.DirectoryNames']['ISESimulatorFiles'] self.Directories.Working = host.Directories.Temp / iseFilesDirectoryName self.Directories.PreCompiled = host.Directories.PreCompiled / iseFilesDirectoryName diff --git a/py/Simulator/QuestaSimulator.py b/py/Simulator/QuestaSimulator.py index cc9a52a0..31ba51f8 100644 --- a/py/Simulator/QuestaSimulator.py +++ b/py/Simulator/QuestaSimulator.py @@ -56,10 +56,6 @@ def __init__(self, host, dryRun, simulationSteps): simulationSteps &= ~SimulationSteps.Elaborate super().__init__(host, dryRun, simulationSteps) - self._vhdlVersion = None - self._vhdlGenerics = None - self._toolChain = None - vSimSimulatorFiles = host.PoCConfig['CONFIG.DirectoryNames']['QuestaSimFiles'] self.Directories.Working = host.Directories.Temp / vSimSimulatorFiles self.Directories.PreCompiled = host.Directories.PreCompiled / vSimSimulatorFiles diff --git a/py/Simulator/VivadoSimulator.py b/py/Simulator/VivadoSimulator.py index 6a3ecc5c..4d466181 100644 --- a/py/Simulator/VivadoSimulator.py +++ b/py/Simulator/VivadoSimulator.py @@ -56,10 +56,6 @@ def __init__(self, host, dryRun, simulationSteps): super().__init__(host, dryRun, simulationSteps) XilinxProjectExportMixIn.__init__(self) - self._vhdlVersion = None - self._vhdlGenerics = None - self._toolChain = None - vivadoFilesDirectoryName = host.PoCConfig['CONFIG.DirectoryNames']['VivadoSimulatorFiles'] self.Directories.Working = host.Directories.Temp / vivadoFilesDirectoryName self.Directories.PreCompiled = host.Directories.PreCompiled / vivadoFilesDirectoryName From bfd1997e5455845b380d85f04cb844c364350c95 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Nov 2016 18:02:52 +0100 Subject: [PATCH 54/97] Added missing ChangeLog files. --- docs/ChangeLog/2014/index.rst | 11 ++++ docs/ChangeLog/2014/v0.0.0.rst | 6 ++ docs/ChangeLog/2015/index.rst | 28 +++++++++ docs/ChangeLog/2015/v0.1.0.rst | 44 +++++++++++++ docs/ChangeLog/2015/v0.10.0.rst | 4 ++ docs/ChangeLog/2015/v0.11.0.rst | 4 ++ docs/ChangeLog/2015/v0.12.0.rst | 4 ++ docs/ChangeLog/2015/v0.13.0.rst | 4 ++ docs/ChangeLog/2015/v0.14.0.rst | 4 ++ docs/ChangeLog/2015/v0.15.0.rst | 4 ++ docs/ChangeLog/2015/v0.16.0.rst | 4 ++ docs/ChangeLog/2015/v0.17.0.rst | 4 ++ docs/ChangeLog/2015/v0.18.0.rst | 4 ++ docs/ChangeLog/2015/v0.2.0.rst | 46 ++++++++++++++ docs/ChangeLog/2015/v0.3.0.rst | 72 +++++++++++++++++++++ docs/ChangeLog/2015/v0.4.0.rst | 50 +++++++++++++++ docs/ChangeLog/2015/v0.5.0.rst | 25 ++++++++ docs/ChangeLog/2015/v0.6.0.rst | 4 ++ docs/ChangeLog/2015/v0.7.0.rst | 4 ++ docs/ChangeLog/2015/v0.8.0.rst | 4 ++ docs/ChangeLog/2015/v0.9.0.rst | 4 ++ docs/ChangeLog/2016/index.rst | 18 ++++++ docs/ChangeLog/2016/v0.19.0.rst | 4 ++ docs/ChangeLog/2016/v0.20.0.rst | 4 ++ docs/ChangeLog/2016/v0.21.0.rst | 4 ++ docs/ChangeLog/2016/v1.0.0.rst | 107 ++++++++++++++++++++++++++++++++ docs/ChangeLog/2016/v1.0.1.rst | 63 +++++++++++++++++++ docs/ChangeLog/2016/v1.1.0.rst | 62 ++++++++++++++++++ docs/ChangeLog/2016/v1.x.rst | 6 ++ 29 files changed, 602 insertions(+) create mode 100644 docs/ChangeLog/2014/index.rst create mode 100644 docs/ChangeLog/2014/v0.0.0.rst create mode 100644 docs/ChangeLog/2015/index.rst create mode 100644 docs/ChangeLog/2015/v0.1.0.rst create mode 100644 docs/ChangeLog/2015/v0.10.0.rst create mode 100644 docs/ChangeLog/2015/v0.11.0.rst create mode 100644 docs/ChangeLog/2015/v0.12.0.rst create mode 100644 docs/ChangeLog/2015/v0.13.0.rst create mode 100644 docs/ChangeLog/2015/v0.14.0.rst create mode 100644 docs/ChangeLog/2015/v0.15.0.rst create mode 100644 docs/ChangeLog/2015/v0.16.0.rst create mode 100644 docs/ChangeLog/2015/v0.17.0.rst create mode 100644 docs/ChangeLog/2015/v0.18.0.rst create mode 100644 docs/ChangeLog/2015/v0.2.0.rst create mode 100644 docs/ChangeLog/2015/v0.3.0.rst create mode 100644 docs/ChangeLog/2015/v0.4.0.rst create mode 100644 docs/ChangeLog/2015/v0.5.0.rst create mode 100644 docs/ChangeLog/2015/v0.6.0.rst create mode 100644 docs/ChangeLog/2015/v0.7.0.rst create mode 100644 docs/ChangeLog/2015/v0.8.0.rst create mode 100644 docs/ChangeLog/2015/v0.9.0.rst create mode 100644 docs/ChangeLog/2016/index.rst create mode 100644 docs/ChangeLog/2016/v0.19.0.rst create mode 100644 docs/ChangeLog/2016/v0.20.0.rst create mode 100644 docs/ChangeLog/2016/v0.21.0.rst create mode 100644 docs/ChangeLog/2016/v1.0.0.rst create mode 100644 docs/ChangeLog/2016/v1.0.1.rst create mode 100644 docs/ChangeLog/2016/v1.1.0.rst create mode 100644 docs/ChangeLog/2016/v1.x.rst diff --git a/docs/ChangeLog/2014/index.rst b/docs/ChangeLog/2014/index.rst new file mode 100644 index 00000000..5a16b240 --- /dev/null +++ b/docs/ChangeLog/2014/index.rst @@ -0,0 +1,11 @@ +.. _CHANGE:2014: + +2014 +#### + +.. contents:: Content of this page + :local: + +.. toctree:: + + v0.0.0 diff --git a/docs/ChangeLog/2014/v0.0.0.rst b/docs/ChangeLog/2014/v0.0.0.rst new file mode 100644 index 00000000..fd699aef --- /dev/null +++ b/docs/ChangeLog/2014/v0.0.0.rst @@ -0,0 +1,6 @@ +.. _CHANGE:v0.0.0: + +New in v0.0.0 (16.12.2014) +================================================================================================================================================================ + +* Initial commit diff --git a/docs/ChangeLog/2015/index.rst b/docs/ChangeLog/2015/index.rst new file mode 100644 index 00000000..ebe12029 --- /dev/null +++ b/docs/ChangeLog/2015/index.rst @@ -0,0 +1,28 @@ +.. _CHANGE:2015: + +2015 +#### + +.. contents:: Content of this page + :local: + +.. toctree:: + + v0.18.0 + v0.17.0 + v0.16.0 + v0.15.0 + v0.14.0 + v0.13.0 + v0.12.0 + v0.11.0 + v0.10.0 + v0.9.0 + v0.8.0 + v0.7.0 + v0.6.0 + v0.5.0 + v0.4.0 + v0.3.0 + v0.2.0 + v0.1.0 diff --git a/docs/ChangeLog/2015/v0.1.0.rst b/docs/ChangeLog/2015/v0.1.0.rst new file mode 100644 index 00000000..e417a50f --- /dev/null +++ b/docs/ChangeLog/2015/v0.1.0.rst @@ -0,0 +1,44 @@ +.. :CHANGE:v0.1.0: + +New in v0.1.0 (19.02.2015) +================================================================================================================================================================ + +* New packages: + + * board - common development board configurations + * config - extract configuration parameters from device names + * utils - common utility functions + * strings - a helper package for string handling + * vectors - a helper package for std_logic_vector and std_logic_matrix + * arith + * fifo + +* New modules + + * PoC.arith - arithmetic modules + + * arith_counter_gray + * arith_counter_ring + * arith_div + * arith_prefix_and + * arith_prefix_or + * arith_prng + * arith_scaler + * arith_sqrt + + * PoC.fifo - FIFOs + + * fifo_cc_got + * fifo_cc_got_tempgot + * fifo_cc_got_tempput + * fifo_ic_got + * fifo_glue + * fifo_shift + + * PoC.mem.ocram - On-Chip RAMs + + * ocram_sp + * ocram_sdp + * ocram_esdp + * ocram_tdp + * ocram_wb diff --git a/docs/ChangeLog/2015/v0.10.0.rst b/docs/ChangeLog/2015/v0.10.0.rst new file mode 100644 index 00000000..dfb8c2f1 --- /dev/null +++ b/docs/ChangeLog/2015/v0.10.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.10.0: + +New in v0.10.0 (23.07.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.11.0.rst b/docs/ChangeLog/2015/v0.11.0.rst new file mode 100644 index 00000000..05e55e90 --- /dev/null +++ b/docs/ChangeLog/2015/v0.11.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.11.0: + +New in v0.11.0 (07.08.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.12.0.rst b/docs/ChangeLog/2015/v0.12.0.rst new file mode 100644 index 00000000..933f3448 --- /dev/null +++ b/docs/ChangeLog/2015/v0.12.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.12.0: + +New in v0.12.0 (25.08.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.13.0.rst b/docs/ChangeLog/2015/v0.13.0.rst new file mode 100644 index 00000000..eaa6643c --- /dev/null +++ b/docs/ChangeLog/2015/v0.13.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.13.0: + +New in v0.13.0 (04.09.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.14.0.rst b/docs/ChangeLog/2015/v0.14.0.rst new file mode 100644 index 00000000..364538f1 --- /dev/null +++ b/docs/ChangeLog/2015/v0.14.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.14.0: + +New in v0.14.0 (28.09.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.15.0.rst b/docs/ChangeLog/2015/v0.15.0.rst new file mode 100644 index 00000000..8b1f223d --- /dev/null +++ b/docs/ChangeLog/2015/v0.15.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.15.0: + +New in v0.15.0 (13.11.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.16.0.rst b/docs/ChangeLog/2015/v0.16.0.rst new file mode 100644 index 00000000..ee8f6692 --- /dev/null +++ b/docs/ChangeLog/2015/v0.16.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.16.0: + +New in v0.16.0 (01.12.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.17.0.rst b/docs/ChangeLog/2015/v0.17.0.rst new file mode 100644 index 00000000..bc53b6aa --- /dev/null +++ b/docs/ChangeLog/2015/v0.17.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.17.0: + +New in v0.17.0 (08.12.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.18.0.rst b/docs/ChangeLog/2015/v0.18.0.rst new file mode 100644 index 00000000..84757126 --- /dev/null +++ b/docs/ChangeLog/2015/v0.18.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.18.0: + +New in v0.18.0 (16.12.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.2.0.rst b/docs/ChangeLog/2015/v0.2.0.rst new file mode 100644 index 00000000..5f198e90 --- /dev/null +++ b/docs/ChangeLog/2015/v0.2.0.rst @@ -0,0 +1,46 @@ +.. :CHANGE:v0.2.0: + +New in v0.2.0 (09.03.2015) +================================================================================================================================================================ + +* New packages: + + * xil + * stream + +* New modules: + + * PoC.bus - Modules for busses + + * bus_Arbiter + + * PoC.bus.stream - Modules for the PoC.Stream protocol + + * stream_Buffer + * stream_DeMux + * stream_FrameGenerator + * stream_Mirror + * stream_Mux + * stream_Source + + * PoC.misc.sync - Cross-Clock Synchronizers + + * sync_Reset + * sync_Flag + * sync_Strobe + * sync_Vector + * sync_Command + + * PoC.xil - Xilinx specific modules + + * xil_SyncBits + * xil_SyncReset + * xil_BSCAN + * xil_Reconfigurator + * xil_SystemMonitor_Virtex6 + * xil_SystemMonitor_Series7 + +* Updated packages: + + * utils + * arith diff --git a/docs/ChangeLog/2015/v0.3.0.rst b/docs/ChangeLog/2015/v0.3.0.rst new file mode 100644 index 00000000..ea163cac --- /dev/null +++ b/docs/ChangeLog/2015/v0.3.0.rst @@ -0,0 +1,72 @@ +.. :CHANGE:v0.3.0: + +New in v0.3.0 (31.03.20015) +================================================================================================================================================================ + +* Added Python infrastructure + + * Added platform wrapper scripts (\*.sh, \*.ps1) + * Added IP-core compiler scripts Netlist.py + +* Added Tools + + * Notepad++ syntax file for Xilinx UCF/XCF files + * Git configuration script to register global aliases + +* New packages: + + * components - hardware described as functions + * physical - physical types like frequency, memory and baudrate + * io + +* New modules: + + * PoC.misc + + * misc_FrequencyMeasurement + + * PoC.io - Low-speed I/O interfaces + + * io_7SegmentMux_BCD + * io_7SegmentMux_HEX + * io_FanControl + * io_PulseWidthModulation + * io_TimingCounter + * io_Debounce + * io_GlitchFilter + +* New IP-cores: + + * PoC.xil - Xilinx specific modules + + * xil_ChipScopeICON_1 + * xil_ChipScopeICON_2 + * xil_ChipScopeICON_3 + * xil_ChipScopeICON_4 + * xil_ChipScopeICON_6 + * xil_ChipScopeICON_7 + * xil_ChipScopeICON_8 + * xil_ChipScopeICON_9 + * xil_ChipScopeICON_10 + * xil_ChipScopeICON_11 + * xil_ChipScopeICON_12 + * xil_ChipScopeICON_13 + * xil_ChipScopeICON_14 + * xil_ChipScopeICON_15 + +* New constraint files: + + * ML605 + * KC705 + * VC707 + * MetaStability + * xil_Sync + +* Updated packages: + + * board + * config + +* Updated modules: + + * xil_BSCAN diff --git a/docs/ChangeLog/2015/v0.4.0.rst b/docs/ChangeLog/2015/v0.4.0.rst new file mode 100644 index 00000000..b96307c3 --- /dev/null +++ b/docs/ChangeLog/2015/v0.4.0.rst @@ -0,0 +1,50 @@ +.. :CHANGE:v0.4.0: + +New in v0.4 (29.04.2015) +================================================================================================================================================================ + +* New Python infrastructure + + * Added simulators for: + + * GHDL + GTKWave + * Mentor Graphic QuestaSim + * Xilinx ISE Simulator + * Xilinx Vivado Simulator + +* New packages: + + * simulation + +* New modules: + + * PoC.comm - communication modules + + * comm_crc + + * PoC.comm.remote - remote communication modules + + * remote_terminal_control + +* New testbenches: + + * arith_addw_tb + * arith_counter_bcd_tb + * arith_prefix_and_tb + * arith_prefix_or_tb + * arith_prng_tb + +* Updated packages: + + * board + * config + * physical + * strings + * utils + +* Updated modules: + + * io_Debounce + * misc_FrequencyMeasurement + * sync_Bits + * sync_Reset diff --git a/docs/ChangeLog/2015/v0.5.0.rst b/docs/ChangeLog/2015/v0.5.0.rst new file mode 100644 index 00000000..cf1a8a3f --- /dev/null +++ b/docs/ChangeLog/2015/v0.5.0.rst @@ -0,0 +1,25 @@ +.. :CHANGE:v0.5.0: + +New in v0.5 (27.05.2015) +================================================================================================================================================================ + +* Updated Python infrastructure +* New testbenches: + + * sync_Reset_tb + * sync_Flag_tb + * sync_Strobe_tb + * sync_Vector_tb + * sync_Command_tb + +* Updated modules: + + * sync_Vector + * sync_Command + +* Updated packages: + + * physical + * utils + * vectors + * xil diff --git a/docs/ChangeLog/2015/v0.6.0.rst b/docs/ChangeLog/2015/v0.6.0.rst new file mode 100644 index 00000000..b7e56019 --- /dev/null +++ b/docs/ChangeLog/2015/v0.6.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.6.0: + +New in v0.6 (09.06.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.7.0.rst b/docs/ChangeLog/2015/v0.7.0.rst new file mode 100644 index 00000000..e205edeb --- /dev/null +++ b/docs/ChangeLog/2015/v0.7.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.7.0: + +New in v0.7 (27.06.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.8.0.rst b/docs/ChangeLog/2015/v0.8.0.rst new file mode 100644 index 00000000..8e02f6f2 --- /dev/null +++ b/docs/ChangeLog/2015/v0.8.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.8.0: + +New in v0.8.0 (03.07.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.9.0.rst b/docs/ChangeLog/2015/v0.9.0.rst new file mode 100644 index 00000000..629ee965 --- /dev/null +++ b/docs/ChangeLog/2015/v0.9.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.9.0: + +New in v0.9.0 (21.07.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2016/index.rst b/docs/ChangeLog/2016/index.rst new file mode 100644 index 00000000..cd534773 --- /dev/null +++ b/docs/ChangeLog/2016/index.rst @@ -0,0 +1,18 @@ +.. _CHANGE:2016: + +2016 +#### + +.. contents:: Content of this page + :local: + + +.. toctree:: + + v1.x + v1.1.0 + v1.0.1 + v1.0.0 + v0.21.0 + v0.20.0 + v0.19.0 diff --git a/docs/ChangeLog/2016/v0.19.0.rst b/docs/ChangeLog/2016/v0.19.0.rst new file mode 100644 index 00000000..8d42c3c3 --- /dev/null +++ b/docs/ChangeLog/2016/v0.19.0.rst @@ -0,0 +1,4 @@ +.. _CHANGE:v0.10: + +New in 0.19 (16.01.2016) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2016/v0.20.0.rst b/docs/ChangeLog/2016/v0.20.0.rst new file mode 100644 index 00000000..18a9577c --- /dev/null +++ b/docs/ChangeLog/2016/v0.20.0.rst @@ -0,0 +1,4 @@ +.. _CHANGE:v0.20: + +New in 0.20 (16.01.2016) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2016/v0.21.0.rst b/docs/ChangeLog/2016/v0.21.0.rst new file mode 100644 index 00000000..389c98b7 --- /dev/null +++ b/docs/ChangeLog/2016/v0.21.0.rst @@ -0,0 +1,4 @@ +.. _CHANGE:v0.21: + +New in 0.21 (17.02.2016) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2016/v1.0.0.rst b/docs/ChangeLog/2016/v1.0.0.rst new file mode 100644 index 00000000..c569c0dd --- /dev/null +++ b/docs/ChangeLog/2016/v1.0.0.rst @@ -0,0 +1,107 @@ +.. _CHANGE:v1.0.0: + +New in 1.0 (13.05.2016) +================================================================================================================================================================ + +* Python Infrastructure (Completely Reworked) + + * New Requirements + + * Python 3.5 + * py-flags + + * New command line interface + + * Synopsis: ``poc.sh|ps1 [common options] [options]`` + * Removed task specific wrapper scripts: ``testbench.sh|ps1``, ``netlist.sh|ps1``, ... + * Updated ``wrapper.ps1`` and ``wrapper.sh`` files + + * New ini-file database + + * + * Added a new config.boards.ini file to list known boards (real and virtual ones) + + * New parser for ``*.files`` files + + * conditional compiling (if-then-elseif-else) + * include statement - include other ``*.files`` files + * library statement - reference external VHDL libraries + * prepared for Cocotb testbenches + + * New parser for ``*.rules`` files + + * + + * All Tool Flows + + * Unbuffered outputs from vendor tools (realtime output to stdout from subprocess) + * Output filtering from vendor tools + + * verbose message suppression + * error and warning message highlighting + * abort flow on vendor tool errors + + * All Simulators + + * Run testbenches for different board or device configurations (see ``--board`` and ``--device`` command line options) + + * New Simulators + + * Aldec Active-HDL support (no GUI support) + + * Tested with Active-HDL from Lattice Diamond + * Tested with Active-HDL Student Edition + + * Cocotb (with QuestaSim backend on Linux) + + * New Synthesizers + + * Altera Quartus II and Quartus Prime + + * Command: ``quartus`` + + * Lattice Synthesis Engine (LSE) from Diamond + + * Command: ``lse`` + + * Xilinx Vivado + + * Command: ``vivado`` + + * GHDL + + * GHDLSimulator can distinguish different backends (mcode, gcc, llvm) + * Pre-compiled library support for GHDL + + * QuestaSim / ModelSim Altera Edition + + * Pre-compiled library support for GHDL + + * Vivado Simulator + + * Tested Vivado Simulator 2016.1 (xSim) with PoC -> still produces errors or false results + +* New Entities + + * + +* New Testbenches + + * + +* New Constraints + + * + +* New dependencies + + * Embedded Cocotb in ``/lib/cocotb`` + +* Shipped Tool and Helper Scripts + + * Updated and new Notepad++ syntax files + * Pre-compiled vendor library support + + * Added a new ``/temp/precompiled`` folder for precompiled vendor libraries + * QuestaSim supports Altera QuartusII, Xilinx ISE and Xilinx Vivado libraries + * GHDL supports Altera QuartusII, Xilinx ISE and Xilinx Vivado libraries diff --git a/docs/ChangeLog/2016/v1.0.1.rst b/docs/ChangeLog/2016/v1.0.1.rst new file mode 100644 index 00000000..888b37cb --- /dev/null +++ b/docs/ChangeLog/2016/v1.0.1.rst @@ -0,0 +1,63 @@ +.. _CHANGE:v1.0.1: + + + +New in 1.x (upcomming) +======================= + +Already documented changes are available on the ``release`` branch at GitHub. + +* Python Infrastructure + + * Common changes + + * The classes ``Simulator`` and ``Compiler`` now share common methods in base class called ``Shared``. + + * ``*.files`` Parser + + * Implemented path expressions: sub-directory expression, concatenate expression + * Implemented InterpolateLiteral: access database keys in ``*.files`` files + * New Path statement, which defines a path constant calculated from a path expression + * Replaced string arguments in statements with path expressions if the desired string was a path + * Replaced simple StringToken matches with Identifier expressions + + * All Simulators + + * + + * All Compilers + + * + + * GHDL + + * Reduced ``-P`` parameters: Removed doublings + +* Documentation + + * + +* VHDL common packages + + * + +* VHDL Simulation helpers + + * Mark a testbench as failed if (registered) processes are active while finilize is called + +* New Entities + + * + +* New Testbenches + + * + +* New Constraints + + * + +* Shipped Tool and Helper Scripts + + * Updated and new Notepad++ syntax files + diff --git a/docs/ChangeLog/2016/v1.1.0.rst b/docs/ChangeLog/2016/v1.1.0.rst new file mode 100644 index 00000000..1de07e67 --- /dev/null +++ b/docs/ChangeLog/2016/v1.1.0.rst @@ -0,0 +1,62 @@ +.. _CHANGE:v1.1.0: + + +New in 1.x (upcomming) +======================= + +Already documented changes are available on the ``release`` branch at GitHub. + +* Python Infrastructure + + * Common changes + + * The classes ``Simulator`` and ``Compiler`` now share common methods in base class called ``Shared``. + + * ``*.files`` Parser + + * Implemented path expressions: sub-directory expression, concatenate expression + * Implemented InterpolateLiteral: access database keys in ``*.files`` files + * New Path statement, which defines a path constant calculated from a path expression + * Replaced string arguments in statements with path expressions if the desired string was a path + * Replaced simple StringToken matches with Identifier expressions + + * All Simulators + + * + + * All Compilers + + * + + * GHDL + + * Reduced ``-P`` parameters: Removed doublings + +* Documentation + + * + +* VHDL common packages + + * + +* VHDL Simulation helpers + + * Mark a testbench as failed if (registered) processes are active while finilize is called + +* New Entities + + * + +* New Testbenches + + * + +* New Constraints + + * + +* Shipped Tool and Helper Scripts + + * Updated and new Notepad++ syntax files + diff --git a/docs/ChangeLog/2016/v1.x.rst b/docs/ChangeLog/2016/v1.x.rst new file mode 100644 index 00000000..ef8e8a20 --- /dev/null +++ b/docs/ChangeLog/2016/v1.x.rst @@ -0,0 +1,6 @@ +.. _CHANGE:v1.x: + +New in 1.x (upcomming) +======================= + +Already documented changes are available on the ``release`` branch at GitHub. From 9f35007bda1c2b7450d29c531e7a70475e98b6cb Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 22 Nov 2016 02:47:42 +0100 Subject: [PATCH 55/97] Improved documentation for the LaTeX backend. --- docs/IPCores/arith/arith.pkg.rst | 18 ++-- docs/IPCores/arith/arith_addw.rst | 29 +++--- docs/IPCores/arith/arith_bcdcollect.rst | 29 +++--- docs/IPCores/arith/arith_carrychain_inc.rst | 29 +++--- docs/IPCores/arith/arith_convert_bin2bcd.rst | 29 +++--- docs/IPCores/arith/arith_counter_bcd.rst | 29 +++--- docs/IPCores/arith/arith_counter_free.rst | 29 +++--- docs/IPCores/arith/arith_counter_gray.rst | 29 +++--- docs/IPCores/arith/arith_counter_ring.rst | 29 +++--- docs/IPCores/arith/arith_div.rst | 29 +++--- docs/IPCores/arith/arith_firstone.rst | 29 +++--- docs/IPCores/arith/arith_muls_wide.rst | 29 +++--- docs/IPCores/arith/arith_prefix_and.rst | 29 +++--- docs/IPCores/arith/arith_prefix_or.rst | 29 +++--- docs/IPCores/arith/arith_prng.rst | 29 +++--- docs/IPCores/arith/arith_same.rst | 29 +++--- docs/IPCores/arith/arith_scaler.rst | 29 +++--- docs/IPCores/arith/arith_shifter_barrel.rst | 29 +++--- docs/IPCores/arith/arith_sqrt.rst | 29 +++--- docs/IPCores/bus/bus_Arbiter.rst | 29 +++--- docs/IPCores/bus/stream/stream.pkg.rst | 17 ++-- docs/IPCores/bus/stream/stream_Buffer.rst | 29 +++--- docs/IPCores/bus/stream/stream_DeMux.rst | 29 +++--- .../bus/stream/stream_FrameGenerator.rst | 29 +++--- docs/IPCores/bus/stream/stream_Mirror.rst | 29 +++--- docs/IPCores/bus/stream/stream_Mux.rst | 29 +++--- docs/IPCores/bus/stream/stream_Sink.rst | 29 +++--- docs/IPCores/bus/stream/stream_Source.rst | 29 +++--- docs/IPCores/bus/wb/wb.pkg.rst | 17 ++-- docs/IPCores/bus/wb/wb_fifo_adapter.rst | 29 +++--- docs/IPCores/bus/wb/wb_ocram.rst | 29 +++--- docs/IPCores/bus/wb/wb_uart_wrapper.rst | 29 +++--- docs/IPCores/cache/cache_par.rst | 29 +++--- .../cache/cache_replacement_policy.rst | 29 +++--- docs/IPCores/cache/cache_tagunit_par.rst | 29 +++--- docs/IPCores/cache/cache_tagunit_seq.rst | 29 +++--- docs/IPCores/comm/comm.pkg.rst | 18 ++-- docs/IPCores/comm/comm_crc.rst | 29 +++--- docs/IPCores/comm/comm_scramble.rst | 29 +++--- docs/IPCores/fifo/fifo.pkg.rst | 18 ++-- docs/IPCores/fifo/fifo_cc_got.rst | 31 ++++--- docs/IPCores/fifo/fifo_cc_got_tempgot.rst | 29 +++--- docs/IPCores/fifo/fifo_cc_got_tempput.rst | 29 +++--- docs/IPCores/fifo/fifo_dc_got_sm.rst | 29 +++--- docs/IPCores/fifo/fifo_glue.rst | 29 +++--- docs/IPCores/fifo/fifo_ic_assembly.rst | 29 +++--- docs/IPCores/fifo/fifo_ic_got.rst | 29 +++--- docs/IPCores/fifo/fifo_shift.rst | 29 +++--- docs/IPCores/io/ddrio/ddrio.pkg.rst | 17 ++-- docs/IPCores/io/ddrio/ddrio_in.rst | 63 +++++++------ docs/IPCores/io/ddrio/ddrio_inout.rst | 29 +++--- docs/IPCores/io/ddrio/ddrio_out.rst | 29 +++--- docs/IPCores/io/iic/iic.pkg.rst | 17 ++-- docs/IPCores/io/iic/iic_BusController.rst | 29 +++--- docs/IPCores/io/iic/iic_Controller.rst | 29 +++--- .../IPCores/io/iic/iic_Controller_SFF8431.rst | 29 +++--- docs/IPCores/io/iic/iic_Switch_PCA9548A.rst | 29 +++--- docs/IPCores/io/io.pkg.rst | 18 ++-- docs/IPCores/io/io_7SegmentMux_BCD.rst | 29 +++--- docs/IPCores/io/io_7SegmentMux_HEX.rst | 29 +++--- docs/IPCores/io/io_Debounce.rst | 29 +++--- docs/IPCores/io/io_FanControl.rst | 29 +++--- docs/IPCores/io/io_FrequencyCounter.rst | 29 +++--- docs/IPCores/io/io_GlitchFilter.rst | 29 +++--- docs/IPCores/io/io_KeyPadScanner.rst | 29 +++--- docs/IPCores/io/io_PulseWidthModulation.rst | 29 +++--- docs/IPCores/io/io_TimingCounter.rst | 29 +++--- docs/IPCores/io/lcd/lcd.pkg.rst | 17 ++-- docs/IPCores/io/lcd/lcd_LCDBuffer.rst | 29 +++--- docs/IPCores/io/lcd/lcd_LCDBusController.rst | 29 +++--- .../io/lcd/lcd_LCDController_KS0066U.rst | 29 +++--- docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst | 29 +++--- docs/IPCores/io/lcd/lcd_dotmatrix.rst | 29 +++--- docs/IPCores/io/mdio/mdio_Controller.rst | 29 +++--- docs/IPCores/io/mdio/mdio_IIC_Adapter.rst | 29 +++--- docs/IPCores/io/pio/pio_fifo_in.rst | 29 +++--- docs/IPCores/io/pio/pio_fifo_out.rst | 29 +++--- docs/IPCores/io/pio/pio_in.rst | 29 +++--- docs/IPCores/io/pio/pio_out.rst | 29 +++--- docs/IPCores/io/pmod/pmod.pkg.rst | 17 ++-- docs/IPCores/io/pmod/pmod_KYPD.rst | 29 +++--- docs/IPCores/io/pmod/pmod_SSD.rst | 29 +++--- docs/IPCores/io/pmod/pmod_USBUART.rst | 29 +++--- docs/IPCores/io/uart/uart.pkg.rst | 17 ++-- docs/IPCores/io/uart/uart_bclk.rst | 29 +++--- docs/IPCores/io/uart/uart_fifo.rst | 29 +++--- docs/IPCores/io/uart/uart_ft245.rst | 29 +++--- docs/IPCores/io/uart/uart_rx.rst | 29 +++--- docs/IPCores/io/uart/uart_tx.rst | 29 +++--- docs/IPCores/io/vga/vga.pkg.rst | 17 ++-- docs/IPCores/io/vga/vga_phy.rst | 29 +++--- docs/IPCores/io/vga/vga_phy_ch7301c.rst | 29 +++--- docs/IPCores/io/vga/vga_timing.rst | 29 +++--- .../ddr2/ddr2_mem2mig_adapter_Spartan6.rst | 29 +++--- .../mem/ddr3/ddr3_mem2mig_adapter_Series7.rst | 29 +++--- docs/IPCores/mem/lut/lut_Sine.rst | 29 +++--- docs/IPCores/mem/mem.pkg.rst | 18 ++-- docs/IPCores/mem/ocram/ocram.pkg.rst | 17 ++-- docs/IPCores/mem/ocram/ocram_esdp.rst | 29 +++--- docs/IPCores/mem/ocram/ocram_sdp.rst | 29 +++--- docs/IPCores/mem/ocram/ocram_sp.rst | 29 +++--- docs/IPCores/mem/ocram/ocram_tdp.rst | 29 +++--- docs/IPCores/mem/ocrom/ocrom.pkg.rst | 17 ++-- docs/IPCores/mem/ocrom/ocrom_dp.rst | 29 +++--- docs/IPCores/mem/ocrom/ocrom_sp.rst | 29 +++--- docs/IPCores/mem/sdram/sdram_ctrl_de0.rst | 29 +++--- docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst | 29 +++--- docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst | 29 +++--- .../mem/sdram/sdram_ctrl_phy_s3esk.rst | 29 +++--- docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst | 29 +++--- docs/IPCores/misc/filter/filter_and.rst | 29 +++--- docs/IPCores/misc/filter/filter_mean.rst | 29 +++--- docs/IPCores/misc/filter/filter_or.rst | 29 +++--- docs/IPCores/misc/gearbox/gearbox_down_cc.rst | 29 +++--- docs/IPCores/misc/gearbox/gearbox_down_dc.rst | 29 +++--- docs/IPCores/misc/gearbox/gearbox_up_cc.rst | 29 +++--- docs/IPCores/misc/gearbox/gearbox_up_dc.rst | 29 +++--- docs/IPCores/misc/misc.pkg.rst | 18 ++-- docs/IPCores/misc/misc_BitwidthConverter.rst | 29 +++--- docs/IPCores/misc/misc_ByteAligner.rst | 29 +++--- docs/IPCores/misc/misc_Delay.rst | 29 +++--- .../misc/misc_FrequencyMeasurement.rst | 29 +++--- docs/IPCores/misc/misc_PulseTrain.rst | 29 +++--- docs/IPCores/misc/misc_Sequencer.rst | 29 +++--- docs/IPCores/misc/misc_StrobeGenerator.rst | 29 +++--- docs/IPCores/misc/misc_StrobeLimiter.rst | 29 +++--- docs/IPCores/misc/misc_bit_lz.rst | 29 +++--- docs/IPCores/misc/stat/stat_Average.rst | 29 +++--- docs/IPCores/misc/stat/stat_Histogram.rst | 29 +++--- docs/IPCores/misc/stat/stat_Maximum.rst | 29 +++--- docs/IPCores/misc/stat/stat_Minimum.rst | 29 +++--- docs/IPCores/misc/sync/sync.pkg.rst | 17 ++-- docs/IPCores/misc/sync/sync_Bits.rst | 31 ++++--- docs/IPCores/misc/sync/sync_Command.rst | 29 +++--- docs/IPCores/misc/sync/sync_Pulse.rst | 31 ++++--- docs/IPCores/misc/sync/sync_Reset.rst | 29 +++--- docs/IPCores/misc/sync/sync_Strobe.rst | 31 ++++--- docs/IPCores/misc/sync/sync_Vector.rst | 29 +++--- .../net/arp/arp_BroadCast_Receiver.rst | 29 +++--- .../net/arp/arp_BroadCast_Requester.rst | 29 +++--- docs/IPCores/net/arp/arp_Cache.rst | 29 +++--- docs/IPCores/net/arp/arp_IPPool.rst | 29 +++--- docs/IPCores/net/arp/arp_Tester.rst | 29 +++--- docs/IPCores/net/arp/arp_UniCast_Receiver.rst | 29 +++--- .../IPCores/net/arp/arp_UniCast_Responder.rst | 29 +++--- docs/IPCores/net/arp/arp_Wrapper.rst | 29 +++--- docs/IPCores/net/eth/eth_GEMAC_GMII.rst | 29 +++--- docs/IPCores/net/eth/eth_GEMAC_RX.rst | 29 +++--- docs/IPCores/net/eth/eth_GEMAC_TX.rst | 29 +++--- docs/IPCores/net/eth/eth_PHYController.rst | 29 +++--- .../eth/eth_PHYController_Marvell_88E1111.rst | 29 +++--- docs/IPCores/net/eth/eth_Wrapper.rst | 29 +++--- docs/IPCores/net/icmpv4/icmpv4_RX.rst | 29 +++--- docs/IPCores/net/icmpv4/icmpv4_TX.rst | 29 +++--- docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst | 29 +++--- docs/IPCores/net/icmpv6/icmpv6_RX.rst | 29 +++--- docs/IPCores/net/icmpv6/icmpv6_TX.rst | 29 +++--- docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst | 29 +++--- docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst | 29 +++--- docs/IPCores/net/ipv4/ipv4_RX.rst | 29 +++--- docs/IPCores/net/ipv4/ipv4_TX.rst | 29 +++--- docs/IPCores/net/ipv4/ipv4_Wrapper.rst | 29 +++--- docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst | 29 +++--- docs/IPCores/net/ipv6/ipv6_RX.rst | 29 +++--- docs/IPCores/net/ipv6/ipv6_TX.rst | 29 +++--- docs/IPCores/net/ipv6/ipv6_Wrapper.rst | 29 +++--- docs/IPCores/net/mac/mac_FrameLoopback.rst | 29 +++--- .../IPCores/net/mac/mac_RX_DestMAC_Switch.rst | 29 +++--- docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst | 29 +++--- docs/IPCores/net/mac/mac_RX_Type_Switch.rst | 29 +++--- .../net/mac/mac_TX_DestMAC_Prepender.rst | 29 +++--- .../net/mac/mac_TX_SrcMAC_Prepender.rst | 29 +++--- .../IPCores/net/mac/mac_TX_Type_Prepender.rst | 29 +++--- docs/IPCores/net/mac/mac_Wrapper.rst | 29 +++--- docs/IPCores/net/ndp/ndp_DestinationCache.rst | 29 +++--- docs/IPCores/net/ndp/ndp_FSMQuery.rst | 29 +++--- docs/IPCores/net/ndp/ndp_NeighborCache.rst | 29 +++--- docs/IPCores/net/ndp/ndp_Wrapper.rst | 29 +++--- docs/IPCores/net/net.pkg.rst | 18 ++-- docs/IPCores/net/net_FrameChecksum.rst | 29 +++--- docs/IPCores/net/net_FrameLoopback.rst | 29 +++--- .../net/net_FramePerformanceCounter.rst | 29 +++--- docs/IPCores/net/stack/stack_UDPv4.rst | 29 +++--- docs/IPCores/net/udp/udp_FrameLoopback.rst | 29 +++--- docs/IPCores/net/udp/udp_RX.rst | 29 +++--- docs/IPCores/net/udp/udp_TX.rst | 29 +++--- docs/IPCores/net/udp/udp_Wrapper.rst | 29 +++--- docs/IPCores/sort/sort_ExpireList.rst | 29 +++--- docs/IPCores/sort/sort_InsertSort.rst | 29 +++--- .../IPCores/sort/sort_LeastFrequentlyUsed.rst | 29 +++--- docs/IPCores/sort/sort_lru_cache.rst | 29 +++--- docs/IPCores/sort/sort_lru_list.rst | 29 +++--- docs/IPCores/sort/sortnet/sortnet.pkg.rst | 17 ++-- .../sort/sortnet/sortnet_BitonicSort.rst | 31 ++++--- .../sortnet/sortnet_MergeSort_Streamed.rst | 29 +++--- .../sort/sortnet/sortnet_OddEvenMergeSort.rst | 29 +++--- .../sort/sortnet/sortnet_OddEvenSort.rst | 29 +++--- .../sort/sortnet/sortnet_Stream_Adapter.rst | 29 +++--- .../sort/sortnet/sortnet_Stream_Adapter2.rst | 29 +++--- .../sort/sortnet/sortnet_Transform.rst | 29 +++--- .../xil/reconfig/reconfig_icap_fsm.rst | 29 +++--- .../xil/reconfig/reconfig_icap_wrapper.rst | 29 +++--- docs/IPCores/xil/xil.pkg.rst | 18 ++-- docs/IPCores/xil/xil_BSCAN.rst | 29 +++--- docs/IPCores/xil/xil_ChipScopeICON.rst | 31 ++++--- docs/IPCores/xil/xil_DRP_BusMux.rst | 29 +++--- docs/IPCores/xil/xil_DRP_BusSync.rst | 29 +++--- docs/IPCores/xil/xil_ICAP.rst | 29 +++--- docs/IPCores/xil/xil_Reconfigurator.rst | 29 +++--- docs/IPCores/xil/xil_SystemMonitor.rst | 29 +++--- .../IPCores/xil/xil_SystemMonitor_Series7.rst | 29 +++--- .../IPCores/xil/xil_SystemMonitor_Virtex6.rst | 29 +++--- docs/conf.py | 4 +- docs/index.rst | 91 ++++++++++++------- src/io/ddrio/ddrio_in.vhdl | 32 ++++--- src/misc/sync/sync_Strobe.vhdl | 2 +- src/sort/sortnet/sortnet_BitonicSort.vhdl | 2 +- tools/ReadTheDocs/requirements.txt | 2 +- 218 files changed, 3577 insertions(+), 2518 deletions(-) diff --git a/docs/IPCores/arith/arith.pkg.rst b/docs/IPCores/arith/arith.pkg.rst index adaa993f..4857abab 100644 --- a/docs/IPCores/arith/arith.pkg.rst +++ b/docs/IPCores/arith/arith.pkg.rst @@ -1,11 +1,13 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith.pkg.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith.pkg.vhdl + :alt: Source Code on GitHub - |gh-src| :pocsrc:`Sourcecode ` + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` .. _PKG:arith: @@ -40,4 +42,6 @@ This package holds all component declarations for this namespace. * :ref:`PoC.arith.same ` * :ref:`PoC.arith.sqrt ` -Source file: :pocsrc:`arith.pkg.vhdl ` +.. only:: latex + + Source file: :pocsrc:`arith.pkg.vhdl ` diff --git a/docs/IPCores/arith/arith_addw.rst b/docs/IPCores/arith/arith_addw.rst index 6642e8f0..19ed4d9e 100644 --- a/docs/IPCores/arith/arith_addw.rst +++ b/docs/IPCores/arith/arith_addw.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_addw.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_addw_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_addw.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_addw_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arith_addw: @@ -43,6 +46,8 @@ arith_addw :linenos: :lines: 53-70 -Source file: :pocsrc:`arith/arith_addw.vhdl ` +.. only:: latex + + Source file: :pocsrc:`arith/arith_addw.vhdl ` diff --git a/docs/IPCores/arith/arith_bcdcollect.rst b/docs/IPCores/arith/arith_bcdcollect.rst index 6bb4df6a..78da7eb2 100644 --- a/docs/IPCores/arith/arith_bcdcollect.rst +++ b/docs/IPCores/arith/arith_bcdcollect.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_bcdcollect.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_bcdcollect_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_bcdcollect.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_bcdcollect_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arith_bcdcollect: @@ -29,6 +32,8 @@ arith_bcdcollect :linenos: :lines: 37-55 -Source file: :pocsrc:`arith/arith_bcdcollect.vhdl ` +.. only:: latex + + Source file: :pocsrc:`arith/arith_bcdcollect.vhdl ` diff --git a/docs/IPCores/arith/arith_carrychain_inc.rst b/docs/IPCores/arith/arith_carrychain_inc.rst index 2ca932dd..86014f94 100644 --- a/docs/IPCores/arith/arith_carrychain_inc.rst +++ b/docs/IPCores/arith/arith_carrychain_inc.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_carrychain_inc.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_carrychain_inc_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_carrychain_inc.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_carrychain_inc_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arith_carrychain_inc: @@ -31,6 +34,8 @@ arith_carrychain_inc :linenos: :lines: 43-52 -Source file: :pocsrc:`arith/arith_carrychain_inc.vhdl ` +.. only:: latex + + Source file: :pocsrc:`arith/arith_carrychain_inc.vhdl ` diff --git a/docs/IPCores/arith/arith_convert_bin2bcd.rst b/docs/IPCores/arith/arith_convert_bin2bcd.rst index 622fc3d1..787ade16 100644 --- a/docs/IPCores/arith/arith_convert_bin2bcd.rst +++ b/docs/IPCores/arith/arith_convert_bin2bcd.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_convert_bin2bcd.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_convert_bin2bcd_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_convert_bin2bcd.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_convert_bin2bcd_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arith_convert_bin2bcd: @@ -29,6 +32,8 @@ arith_convert_bin2bcd :linenos: :lines: 40-58 -Source file: :pocsrc:`arith/arith_convert_bin2bcd.vhdl ` +.. only:: latex + + Source file: :pocsrc:`arith/arith_convert_bin2bcd.vhdl ` diff --git a/docs/IPCores/arith/arith_counter_bcd.rst b/docs/IPCores/arith/arith_counter_bcd.rst index 09f68656..8cedc60c 100644 --- a/docs/IPCores/arith/arith_counter_bcd.rst +++ b/docs/IPCores/arith/arith_counter_bcd.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_counter_bcd.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_counter_bcd_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_counter_bcd.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_counter_bcd_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arith_counter_bcd: @@ -40,6 +43,8 @@ is specified by ``val(3 downto 0)``. :linenos: :lines: 51-61 -Source file: :pocsrc:`arith/arith_counter_bcd.vhdl ` +.. only:: latex + + Source file: :pocsrc:`arith/arith_counter_bcd.vhdl ` diff --git a/docs/IPCores/arith/arith_counter_free.rst b/docs/IPCores/arith/arith_counter_free.rst index 7445fe4c..03730a4d 100644 --- a/docs/IPCores/arith/arith_counter_free.rst +++ b/docs/IPCores/arith/arith_counter_free.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_counter_free.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_counter_free_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_counter_free.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_counter_free_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arith_counter_free: @@ -36,6 +39,8 @@ input have been observed. :linenos: :lines: 41-53 -Source file: :pocsrc:`arith/arith_counter_free.vhdl ` +.. only:: latex + + Source file: :pocsrc:`arith/arith_counter_free.vhdl ` diff --git a/docs/IPCores/arith/arith_counter_gray.rst b/docs/IPCores/arith/arith_counter_gray.rst index d1ba293a..ea54e441 100644 --- a/docs/IPCores/arith/arith_counter_gray.rst +++ b/docs/IPCores/arith/arith_counter_gray.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_counter_gray.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_counter_gray_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_counter_gray.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_counter_gray_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arith_counter_gray: @@ -29,6 +32,8 @@ arith_counter_gray :linenos: :lines: 38-51 -Source file: :pocsrc:`arith/arith_counter_gray.vhdl ` +.. only:: latex + + Source file: :pocsrc:`arith/arith_counter_gray.vhdl ` diff --git a/docs/IPCores/arith/arith_counter_ring.rst b/docs/IPCores/arith/arith_counter_ring.rst index f036513c..c0e25f8f 100644 --- a/docs/IPCores/arith/arith_counter_ring.rst +++ b/docs/IPCores/arith/arith_counter_ring.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_counter_ring.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_counter_ring_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_counter_ring.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_counter_ring_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arith_counter_ring: @@ -32,6 +35,8 @@ enabling ``INVERT_FEEDBACK``. The number of counter bits is configurable with :linenos: :lines: 41-54 -Source file: :pocsrc:`arith/arith_counter_ring.vhdl ` +.. only:: latex + + Source file: :pocsrc:`arith/arith_counter_ring.vhdl ` diff --git a/docs/IPCores/arith/arith_div.rst b/docs/IPCores/arith/arith_div.rst index 15d7da85..d1397e63 100644 --- a/docs/IPCores/arith/arith_div.rst +++ b/docs/IPCores/arith/arith_div.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_div.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_div_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_div.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_div_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arith_div: @@ -33,6 +36,8 @@ outputs are undefined in this case. :linenos: :lines: 38-61 -Source file: :pocsrc:`arith/arith_div.vhdl ` +.. only:: latex + + Source file: :pocsrc:`arith/arith_div.vhdl ` diff --git a/docs/IPCores/arith/arith_firstone.rst b/docs/IPCores/arith/arith_firstone.rst index 09fa8dc1..e2f984ae 100644 --- a/docs/IPCores/arith/arith_firstone.rst +++ b/docs/IPCores/arith/arith_firstone.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_firstone.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_firstone_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_firstone.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_firstone_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arith_firstone: @@ -42,6 +45,8 @@ This implementation uses carry chains for wider implementations. :linenos: :lines: 50-61 -Source file: :pocsrc:`arith/arith_firstone.vhdl ` +.. only:: latex + + Source file: :pocsrc:`arith/arith_firstone.vhdl ` diff --git a/docs/IPCores/arith/arith_muls_wide.rst b/docs/IPCores/arith/arith_muls_wide.rst index 2e9b227d..726f87e4 100644 --- a/docs/IPCores/arith/arith_muls_wide.rst +++ b/docs/IPCores/arith/arith_muls_wide.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_muls_wide.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_muls_wide_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_muls_wide.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_muls_wide_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arith_muls_wide: @@ -31,6 +34,8 @@ For detailed documentation see below. :linenos: :lines: 38-49 -Source file: :pocsrc:`arith/arith_muls_wide.vhdl ` +.. only:: latex + + Source file: :pocsrc:`arith/arith_muls_wide.vhdl ` diff --git a/docs/IPCores/arith/arith_prefix_and.rst b/docs/IPCores/arith/arith_prefix_and.rst index 3aa6e5b2..e4b1fb25 100644 --- a/docs/IPCores/arith/arith_prefix_and.rst +++ b/docs/IPCores/arith/arith_prefix_and.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_prefix_and.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_prefix_and_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_prefix_and.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_prefix_and_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arith_prefix_and: @@ -31,6 +34,8 @@ This implementation uses carry chains for wider implementations. :linenos: :lines: 43-51 -Source file: :pocsrc:`arith/arith_prefix_and.vhdl ` +.. only:: latex + + Source file: :pocsrc:`arith/arith_prefix_and.vhdl ` diff --git a/docs/IPCores/arith/arith_prefix_or.rst b/docs/IPCores/arith/arith_prefix_or.rst index 15ae0bf7..cbd52b02 100644 --- a/docs/IPCores/arith/arith_prefix_or.rst +++ b/docs/IPCores/arith/arith_prefix_or.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_prefix_or.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_prefix_or_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_prefix_or.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_prefix_or_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arith_prefix_or: @@ -31,6 +34,8 @@ This implementation uses carry chains for wider implementations. :linenos: :lines: 43-51 -Source file: :pocsrc:`arith/arith_prefix_or.vhdl ` +.. only:: latex + + Source file: :pocsrc:`arith/arith_prefix_or.vhdl ` diff --git a/docs/IPCores/arith/arith_prng.rst b/docs/IPCores/arith/arith_prng.rst index 715483e9..b6c8f552 100644 --- a/docs/IPCores/arith/arith_prng.rst +++ b/docs/IPCores/arith/arith_prng.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_prng.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_prng_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_prng.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_prng_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arith_prng: @@ -35,6 +38,8 @@ The generated number sequence includes the value all-zeros, but not all-ones. :linenos: :lines: 46-57 -Source file: :pocsrc:`arith/arith_prng.vhdl ` +.. only:: latex + + Source file: :pocsrc:`arith/arith_prng.vhdl ` diff --git a/docs/IPCores/arith/arith_same.rst b/docs/IPCores/arith/arith_same.rst index 4c05faf9..74d5a77c 100644 --- a/docs/IPCores/arith/arith_same.rst +++ b/docs/IPCores/arith/arith_same.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_same.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_same_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_same.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_same_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arith_same: @@ -36,6 +39,8 @@ bit position as to avoid an undetected sign change between the slices. :linenos: :lines: 48-57 -Source file: :pocsrc:`arith/arith_same.vhdl ` +.. only:: latex + + Source file: :pocsrc:`arith/arith_same.vhdl ` diff --git a/docs/IPCores/arith/arith_scaler.rst b/docs/IPCores/arith/arith_scaler.rst index 54cb6370..3f86aab4 100644 --- a/docs/IPCores/arith/arith_scaler.rst +++ b/docs/IPCores/arith/arith_scaler.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_scaler.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_scaler_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_scaler.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_scaler_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arith_scaler: @@ -43,6 +46,8 @@ highest scaling ratio to be used in order to avoid a truncation overflow. :linenos: :lines: 52-69 -Source file: :pocsrc:`arith/arith_scaler.vhdl ` +.. only:: latex + + Source file: :pocsrc:`arith/arith_scaler.vhdl ` diff --git a/docs/IPCores/arith/arith_shifter_barrel.rst b/docs/IPCores/arith/arith_shifter_barrel.rst index 85907d3d..f8cc579a 100644 --- a/docs/IPCores/arith/arith_shifter_barrel.rst +++ b/docs/IPCores/arith/arith_shifter_barrel.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_shifter_barrel.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_shifter_barrel_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_shifter_barrel.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_shifter_barrel_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arith_shifter_barrel: @@ -35,6 +38,8 @@ This is equivalent to the CPU instructions: SLL, SLA, SRL, SRA, RL, RR :linenos: :lines: 45-57 -Source file: :pocsrc:`arith/arith_shifter_barrel.vhdl ` +.. only:: latex + + Source file: :pocsrc:`arith/arith_shifter_barrel.vhdl ` diff --git a/docs/IPCores/arith/arith_sqrt.rst b/docs/IPCores/arith/arith_sqrt.rst index df23659e..d1e46a8c 100644 --- a/docs/IPCores/arith/arith_sqrt.rst +++ b/docs/IPCores/arith/arith_sqrt.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_sqrt.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_sqrt_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_sqrt.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_sqrt_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arith_sqrt: @@ -31,6 +34,8 @@ Its computation requires (N+1)/2 steps for an argument bit width of N. :linenos: :lines: 38-55 -Source file: :pocsrc:`arith/arith_sqrt.vhdl ` +.. only:: latex + + Source file: :pocsrc:`arith/arith_sqrt.vhdl ` diff --git a/docs/IPCores/bus/bus_Arbiter.rst b/docs/IPCores/bus/bus_Arbiter.rst index 003969f9..9006dc37 100644 --- a/docs/IPCores/bus/bus_Arbiter.rst +++ b/docs/IPCores/bus/bus_Arbiter.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/bus_Arbiter.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/bus_Arbiter_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/bus_Arbiter.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/bus_Arbiter_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:bus_Arbiter: @@ -32,6 +35,8 @@ following arbitration strategies: :linenos: :lines: 42-60 -Source file: :pocsrc:`bus/bus_Arbiter.vhdl ` +.. only:: latex + + Source file: :pocsrc:`bus/bus_Arbiter.vhdl ` diff --git a/docs/IPCores/bus/stream/stream.pkg.rst b/docs/IPCores/bus/stream/stream.pkg.rst index c4fca429..03161076 100644 --- a/docs/IPCores/bus/stream/stream.pkg.rst +++ b/docs/IPCores/bus/stream/stream.pkg.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream.pkg.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream.pkg.vhdl + :alt: Source Code on GitHub - |gh-src| :pocsrc:`Sourcecode ` + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` .. _PKG:stream: PoC.bus.stream Package ====================== -Source file: :pocsrc:`stream.pkg.vhdl ` +.. only:: latex + Source file: :pocsrc:`stream.pkg.vhdl ` diff --git a/docs/IPCores/bus/stream/stream_Buffer.rst b/docs/IPCores/bus/stream/stream_Buffer.rst index a73a33c0..1f35811c 100644 --- a/docs/IPCores/bus/stream/stream_Buffer.rst +++ b/docs/IPCores/bus/stream/stream_Buffer.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_Buffer.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_Buffer_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_Buffer.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_Buffer_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:stream_Buffer: @@ -32,6 +35,8 @@ meta information. :linenos: :lines: 44-74 -Source file: :pocsrc:`bus/stream/stream_Buffer.vhdl ` +.. only:: latex + + Source file: :pocsrc:`bus/stream/stream_Buffer.vhdl ` diff --git a/docs/IPCores/bus/stream/stream_DeMux.rst b/docs/IPCores/bus/stream/stream_DeMux.rst index 4eac6ed5..f9f50898 100644 --- a/docs/IPCores/bus/stream/stream_DeMux.rst +++ b/docs/IPCores/bus/stream/stream_DeMux.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_DeMux.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_DeMux_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_DeMux.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_DeMux_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:stream_DeMux: @@ -29,6 +32,8 @@ stream_DeMux :linenos: :lines: 41-70 -Source file: :pocsrc:`bus/stream/stream_DeMux.vhdl ` +.. only:: latex + + Source file: :pocsrc:`bus/stream/stream_DeMux.vhdl ` diff --git a/docs/IPCores/bus/stream/stream_FrameGenerator.rst b/docs/IPCores/bus/stream/stream_FrameGenerator.rst index bf090d02..e86e59be 100644 --- a/docs/IPCores/bus/stream/stream_FrameGenerator.rst +++ b/docs/IPCores/bus/stream/stream_FrameGenerator.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_FrameGenerator.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_FrameGenerator_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_FrameGenerator.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_FrameGenerator_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:stream_FrameGenerator: @@ -29,6 +32,8 @@ stream_FrameGenerator :linenos: :lines: 40-66 -Source file: :pocsrc:`bus/stream/stream_FrameGenerator.vhdl ` +.. only:: latex + + Source file: :pocsrc:`bus/stream/stream_FrameGenerator.vhdl ` diff --git a/docs/IPCores/bus/stream/stream_Mirror.rst b/docs/IPCores/bus/stream/stream_Mirror.rst index bd7d529d..e1602042 100644 --- a/docs/IPCores/bus/stream/stream_Mirror.rst +++ b/docs/IPCores/bus/stream/stream_Mirror.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_Mirror.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_Mirror_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_Mirror.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_Mirror_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:stream_Mirror: @@ -29,6 +32,8 @@ stream_Mirror :linenos: :lines: 41-70 -Source file: :pocsrc:`bus/stream/stream_Mirror.vhdl ` +.. only:: latex + + Source file: :pocsrc:`bus/stream/stream_Mirror.vhdl ` diff --git a/docs/IPCores/bus/stream/stream_Mux.rst b/docs/IPCores/bus/stream/stream_Mux.rst index 3f7e407f..ff0cb3a0 100644 --- a/docs/IPCores/bus/stream/stream_Mux.rst +++ b/docs/IPCores/bus/stream/stream_Mux.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_Mux.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_Mux_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_Mux.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_Mux_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:stream_Mux: @@ -29,6 +32,8 @@ stream_Mux :linenos: :lines: 41-69 -Source file: :pocsrc:`bus/stream/stream_Mux.vhdl ` +.. only:: latex + + Source file: :pocsrc:`bus/stream/stream_Mux.vhdl ` diff --git a/docs/IPCores/bus/stream/stream_Sink.rst b/docs/IPCores/bus/stream/stream_Sink.rst index 1188e3c5..14aff7d5 100644 --- a/docs/IPCores/bus/stream/stream_Sink.rst +++ b/docs/IPCores/bus/stream/stream_Sink.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_Sink.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_Sink_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_Sink.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_Sink_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:stream_Sink: @@ -29,6 +32,8 @@ stream_Sink :linenos: :lines: 42-59 -Source file: :pocsrc:`bus/stream/stream_Sink.vhdl ` +.. only:: latex + + Source file: :pocsrc:`bus/stream/stream_Sink.vhdl ` diff --git a/docs/IPCores/bus/stream/stream_Source.rst b/docs/IPCores/bus/stream/stream_Source.rst index a95529f5..b32b3e0d 100644 --- a/docs/IPCores/bus/stream/stream_Source.rst +++ b/docs/IPCores/bus/stream/stream_Source.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_Source.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_Source_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_Source.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_Source_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:stream_Source: @@ -29,6 +32,8 @@ stream_Source :linenos: :lines: 42-58 -Source file: :pocsrc:`bus/stream/stream_Source.vhdl ` +.. only:: latex + + Source file: :pocsrc:`bus/stream/stream_Source.vhdl ` diff --git a/docs/IPCores/bus/wb/wb.pkg.rst b/docs/IPCores/bus/wb/wb.pkg.rst index 8a3a6106..97492a80 100644 --- a/docs/IPCores/bus/wb/wb.pkg.rst +++ b/docs/IPCores/bus/wb/wb.pkg.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/wb/wb.pkg.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/wb/wb.pkg.vhdl + :alt: Source Code on GitHub - |gh-src| :pocsrc:`Sourcecode ` + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` .. _PKG:wb: PoC.bus.wb Package ====================== -Source file: :pocsrc:`wb.pkg.vhdl ` +.. only:: latex + Source file: :pocsrc:`wb.pkg.vhdl ` diff --git a/docs/IPCores/bus/wb/wb_fifo_adapter.rst b/docs/IPCores/bus/wb/wb_fifo_adapter.rst index 1b7de9cf..09b21d66 100644 --- a/docs/IPCores/bus/wb/wb_fifo_adapter.rst +++ b/docs/IPCores/bus/wb/wb_fifo_adapter.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/wb/wb_fifo_adapter.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/wb/wb_fifo_adapter_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/wb/wb_fifo_adapter.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/wb/wb_fifo_adapter_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:wb_fifo_adapter: @@ -36,6 +39,8 @@ old comments: :linenos: :lines: 80-104 -Source file: :pocsrc:`bus/wb/wb_fifo_adapter.vhdl ` +.. only:: latex + + Source file: :pocsrc:`bus/wb/wb_fifo_adapter.vhdl ` diff --git a/docs/IPCores/bus/wb/wb_ocram.rst b/docs/IPCores/bus/wb/wb_ocram.rst index e9f18f9b..424948ee 100644 --- a/docs/IPCores/bus/wb/wb_ocram.rst +++ b/docs/IPCores/bus/wb/wb_ocram.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/wb/wb_ocram.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/wb/wb_ocram_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/wb/wb_ocram.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/wb/wb_ocram_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:ocram_wb: @@ -48,6 +51,8 @@ PIPE_STAGES = 2 :linenos: :lines: 54-80 -Source file: :pocsrc:`bus/wb/wb_ocram.vhdl ` +.. only:: latex + + Source file: :pocsrc:`bus/wb/wb_ocram.vhdl ` diff --git a/docs/IPCores/bus/wb/wb_uart_wrapper.rst b/docs/IPCores/bus/wb/wb_uart_wrapper.rst index 35cf954c..24677510 100644 --- a/docs/IPCores/bus/wb/wb_uart_wrapper.rst +++ b/docs/IPCores/bus/wb/wb_uart_wrapper.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/wb/wb_uart_wrapper.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/wb/wb_uart_wrapper_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/wb/wb_uart_wrapper.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/wb/wb_uart_wrapper_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:uart_wb: @@ -31,6 +34,8 @@ interface. Synchronized reset is used. :linenos: :lines: 40-69 -Source file: :pocsrc:`bus/wb/wb_uart_wrapper.vhdl ` +.. only:: latex + + Source file: :pocsrc:`bus/wb/wb_uart_wrapper.vhdl ` diff --git a/docs/IPCores/cache/cache_par.rst b/docs/IPCores/cache/cache_par.rst index d6e25481..96c1e358 100644 --- a/docs/IPCores/cache/cache_par.rst +++ b/docs/IPCores/cache/cache_par.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/cache/cache_par.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_par_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/cache/cache_par.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_par_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:cache_par: @@ -64,6 +67,8 @@ both with a latency of one clock cycle. :linenos: :lines: 76-100 -Source file: :pocsrc:`cache/cache_par.vhdl ` +.. only:: latex + + Source file: :pocsrc:`cache/cache_par.vhdl ` diff --git a/docs/IPCores/cache/cache_replacement_policy.rst b/docs/IPCores/cache/cache_replacement_policy.rst index eb9dd1cd..2d7dc2e4 100644 --- a/docs/IPCores/cache/cache_replacement_policy.rst +++ b/docs/IPCores/cache/cache_replacement_policy.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/cache/cache_replacement_policy.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_replacement_policy_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/cache/cache_replacement_policy.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_replacement_policy_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:cache_replacement_policy: @@ -71,6 +74,8 @@ cache set (see above). :linenos: :lines: 85-104 -Source file: :pocsrc:`cache/cache_replacement_policy.vhdl ` +.. only:: latex + + Source file: :pocsrc:`cache/cache_replacement_policy.vhdl ` diff --git a/docs/IPCores/cache/cache_tagunit_par.rst b/docs/IPCores/cache/cache_tagunit_par.rst index cf364399..93fe7905 100644 --- a/docs/IPCores/cache/cache_tagunit_par.rst +++ b/docs/IPCores/cache/cache_tagunit_par.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/cache/cache_tagunit_par.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_tagunit_par_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/cache/cache_tagunit_par.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_tagunit_par_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:cache_tagunit_par: @@ -64,6 +67,8 @@ must be a power of 2. :linenos: :lines: 75-99 -Source file: :pocsrc:`cache/cache_tagunit_par.vhdl ` +.. only:: latex + + Source file: :pocsrc:`cache/cache_tagunit_par.vhdl ` diff --git a/docs/IPCores/cache/cache_tagunit_seq.rst b/docs/IPCores/cache/cache_tagunit_seq.rst index 7558fb8d..e3f83244 100644 --- a/docs/IPCores/cache/cache_tagunit_seq.rst +++ b/docs/IPCores/cache/cache_tagunit_seq.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/cache/cache_tagunit_seq.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_tagunit_seq_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/cache/cache_tagunit_seq.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_tagunit_seq_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:cache_tagunit_seq: @@ -29,6 +32,8 @@ cache_tagunit_seq :linenos: :lines: 39-73 -Source file: :pocsrc:`cache/cache_tagunit_seq.vhdl ` +.. only:: latex + + Source file: :pocsrc:`cache/cache_tagunit_seq.vhdl ` diff --git a/docs/IPCores/comm/comm.pkg.rst b/docs/IPCores/comm/comm.pkg.rst index 199f5cd7..23080d59 100644 --- a/docs/IPCores/comm/comm.pkg.rst +++ b/docs/IPCores/comm/comm.pkg.rst @@ -1,15 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/comm/comm.pkg.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/comm/comm.pkg.vhdl + :alt: Source Code on GitHub - |gh-src| :pocsrc:`Sourcecode ` + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` .. _PKG:comm: PoC.comm Package ================ -Source file: :pocsrc:`comm.pkg.vhdl ` +.. only:: latex + + Source file: :pocsrc:`comm.pkg.vhdl ` diff --git a/docs/IPCores/comm/comm_crc.rst b/docs/IPCores/comm/comm_crc.rst index aa2d4499..0418627f 100644 --- a/docs/IPCores/comm/comm_crc.rst +++ b/docs/IPCores/comm/comm_crc.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/comm/comm_crc.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/comm/comm_crc_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/comm/comm_crc.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/comm/comm_crc_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:comm_crc: @@ -35,6 +38,8 @@ processing width. :linenos: :lines: 45-64 -Source file: :pocsrc:`comm/comm_crc.vhdl ` +.. only:: latex + + Source file: :pocsrc:`comm/comm_crc.vhdl ` diff --git a/docs/IPCores/comm/comm_scramble.rst b/docs/IPCores/comm/comm_scramble.rst index b79def24..e1905884 100644 --- a/docs/IPCores/comm/comm_scramble.rst +++ b/docs/IPCores/comm/comm_scramble.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/comm/comm_scramble.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/comm/comm_scramble_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/comm/comm_scramble.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/comm/comm_scramble_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:comm_scramble: @@ -31,6 +34,8 @@ sequence is independent from the chosen output width. :linenos: :lines: 37-51 -Source file: :pocsrc:`comm/comm_scramble.vhdl ` +.. only:: latex + + Source file: :pocsrc:`comm/comm_scramble.vhdl ` diff --git a/docs/IPCores/fifo/fifo.pkg.rst b/docs/IPCores/fifo/fifo.pkg.rst index 0ce9d086..7a11a06c 100644 --- a/docs/IPCores/fifo/fifo.pkg.rst +++ b/docs/IPCores/fifo/fifo.pkg.rst @@ -1,11 +1,13 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo.pkg.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo.pkg.vhdl + :alt: Source Code on GitHub - |gh-src| :pocsrc:`Sourcecode ` + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` .. _PKG:fifo: @@ -14,4 +16,6 @@ PoC.fifo Package This package holds all component declarations for this namespace. -Source file: :pocsrc:`fifo.pkg.vhdl ` +.. only:: latex + + Source file: :pocsrc:`fifo.pkg.vhdl ` diff --git a/docs/IPCores/fifo/fifo_cc_got.rst b/docs/IPCores/fifo/fifo_cc_got.rst index ab1274ed..fdc19e38 100644 --- a/docs/IPCores/fifo/fifo_cc_got.rst +++ b/docs/IPCores/fifo/fifo_cc_got.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_cc_got.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_cc_got_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_cc_got.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_cc_got_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:fifo_cc_got: @@ -75,8 +78,6 @@ comparator (subtractor) in their path. :linenos: :lines: 98-124 -Source file: :pocsrc:`fifo/fifo_cc_got.vhdl ` - .. seealso:: :ref:`IP:fifo_dc_got` @@ -87,3 +88,7 @@ Source file: :pocsrc:`fifo/fifo_cc_got.vhdl ` For a minimal FIFO / pipeline decoupling. + +.. only:: latex + + Source file: :pocsrc:`fifo/fifo_cc_got.vhdl ` diff --git a/docs/IPCores/fifo/fifo_cc_got_tempgot.rst b/docs/IPCores/fifo/fifo_cc_got_tempgot.rst index b9e0842a..027d78b9 100644 --- a/docs/IPCores/fifo/fifo_cc_got_tempgot.rst +++ b/docs/IPCores/fifo/fifo_cc_got_tempgot.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_cc_got_tempgot.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_cc_got_tempgot_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_cc_got_tempgot.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_cc_got_tempgot_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:fifo_cc_got_tempgot: @@ -70,6 +73,8 @@ comparator (subtractor) in their path. :linenos: :lines: 85-114 -Source file: :pocsrc:`fifo/fifo_cc_got_tempgot.vhdl ` +.. only:: latex + + Source file: :pocsrc:`fifo/fifo_cc_got_tempgot.vhdl ` diff --git a/docs/IPCores/fifo/fifo_cc_got_tempput.rst b/docs/IPCores/fifo/fifo_cc_got_tempput.rst index d6a8db8b..acbc85f4 100644 --- a/docs/IPCores/fifo/fifo_cc_got_tempput.rst +++ b/docs/IPCores/fifo/fifo_cc_got_tempput.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_cc_got_tempput.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_cc_got_tempput_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_cc_got_tempput.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_cc_got_tempput_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:fifo_cc_got_tempput: @@ -70,6 +73,8 @@ comparator (subtractor) in their path. :linenos: :lines: 85-114 -Source file: :pocsrc:`fifo/fifo_cc_got_tempput.vhdl ` +.. only:: latex + + Source file: :pocsrc:`fifo/fifo_cc_got_tempput.vhdl ` diff --git a/docs/IPCores/fifo/fifo_dc_got_sm.rst b/docs/IPCores/fifo/fifo_dc_got_sm.rst index 6c9a8af1..ff5b6c97 100644 --- a/docs/IPCores/fifo/fifo_dc_got_sm.rst +++ b/docs/IPCores/fifo/fifo_dc_got_sm.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_dc_got_sm.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_dc_got_sm_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_dc_got_sm.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_dc_got_sm_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:fifo_dc_got_sm: @@ -52,6 +55,8 @@ Synchronous reset is used. Both resets must overlap. :linenos: :lines: 62-85 -Source file: :pocsrc:`fifo/fifo_dc_got_sm.vhdl ` +.. only:: latex + + Source file: :pocsrc:`fifo/fifo_dc_got_sm.vhdl ` diff --git a/docs/IPCores/fifo/fifo_glue.rst b/docs/IPCores/fifo/fifo_glue.rst index f90e3b89..0c750607 100644 --- a/docs/IPCores/fifo/fifo_glue.rst +++ b/docs/IPCores/fifo/fifo_glue.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_glue.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_glue_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_glue.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_glue_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:fifo_glue: @@ -31,6 +34,8 @@ the ``ful`` and the ``vld`` indicators to be driven by registers. :linenos: :lines: 36-55 -Source file: :pocsrc:`fifo/fifo_glue.vhdl ` +.. only:: latex + + Source file: :pocsrc:`fifo/fifo_glue.vhdl ` diff --git a/docs/IPCores/fifo/fifo_ic_assembly.rst b/docs/IPCores/fifo/fifo_ic_assembly.rst index 18692d7b..9e985933 100644 --- a/docs/IPCores/fifo/fifo_ic_assembly.rst +++ b/docs/IPCores/fifo/fifo_ic_assembly.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_ic_assembly.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_ic_assembly_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_ic_assembly.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_ic_assembly_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:fifo_ic_assembly: @@ -40,6 +43,8 @@ the transmission of data blocks. This applies to many DMA implementations. :linenos: :lines: 45-78 -Source file: :pocsrc:`fifo/fifo_ic_assembly.vhdl ` +.. only:: latex + + Source file: :pocsrc:`fifo/fifo_ic_assembly.vhdl ` diff --git a/docs/IPCores/fifo/fifo_ic_got.rst b/docs/IPCores/fifo/fifo_ic_got.rst index dd35c6a1..778c6c5d 100644 --- a/docs/IPCores/fifo/fifo_ic_got.rst +++ b/docs/IPCores/fifo/fifo_ic_got.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_ic_got.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_ic_got_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_ic_got.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_ic_got_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:fifo_ic_got: @@ -64,6 +67,8 @@ Examples: :linenos: :lines: 77-103 -Source file: :pocsrc:`fifo/fifo_ic_got.vhdl ` +.. only:: latex + + Source file: :pocsrc:`fifo/fifo_ic_got.vhdl ` diff --git a/docs/IPCores/fifo/fifo_shift.rst b/docs/IPCores/fifo/fifo_shift.rst index 52273eeb..26b0cf6f 100644 --- a/docs/IPCores/fifo/fifo_shift.rst +++ b/docs/IPCores/fifo/fifo_shift.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_shift.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_shift_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_shift.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_shift_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:fifo_shift: @@ -35,6 +38,8 @@ The specified depth (``MIN_DEPTH``) is rounded up to the next suitable value. :linenos: :lines: 44-64 -Source file: :pocsrc:`fifo/fifo_shift.vhdl ` +.. only:: latex + + Source file: :pocsrc:`fifo/fifo_shift.vhdl ` diff --git a/docs/IPCores/io/ddrio/ddrio.pkg.rst b/docs/IPCores/io/ddrio/ddrio.pkg.rst index f3c899cd..ed54e5f3 100644 --- a/docs/IPCores/io/ddrio/ddrio.pkg.rst +++ b/docs/IPCores/io/ddrio/ddrio.pkg.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/ddrio/ddrio.pkg.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/ddrio/ddrio.pkg.vhdl + :alt: Source Code on GitHub - |gh-src| :pocsrc:`Sourcecode ` + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` .. _PKG:ddrio: PoC.io.ddrio Package ==================== -Source file: :pocsrc:`ddrio.pkg.vhdl ` +.. only:: latex + Source file: :pocsrc:`ddrio.pkg.vhdl ` diff --git a/docs/IPCores/io/ddrio/ddrio_in.rst b/docs/IPCores/io/ddrio/ddrio_in.rst index 266d5468..b9c3b7d8 100644 --- a/docs/IPCores/io/ddrio/ddrio_in.rst +++ b/docs/IPCores/io/ddrio/ddrio_in.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/ddrio/ddrio_in.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/ddrio/ddrio_in_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/ddrio/ddrio_in.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/ddrio/ddrio_in_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:ddrio_in: @@ -29,25 +32,29 @@ the falling edge of the clock as depicted in the following waveform. { signal: [ {name: 'clk', wave: 'H.L.H.L.H.L.H.L.H'}, - {name: 'pad', wave: 'x2.3.4.5.2.3.x...', data: ['0', '1', '2', '3', '4', '5'], node: '..a.b.c.d.e.f..'}, - ['DataIn', - {name: 'DataIn_low', wave: 'x...2...4...2...x', data: ['0', '2', '4'], node: '.....k...m...o.'}, - {name: 'DataIn_high', wave: 'x...3...5...3...x', data: ['1', '3', '5'], node: '.....l...n...p.'}, - ], + {name: 'pad', wave: 'x2.3.4.5.2.3.x...', data: ['0', '1', '2', '3', '4', '5'], node: '.a.b.c.d.e.f...'}, + {name: 'DataIn_low', wave: 'x...2...4...2...x', data: ['0', '2', '4'], node: '....k...m...o..'}, + {name: 'DataIn_high', wave: 'x...3...5...3...x', data: ['1', '3', '5'], node: '....l...n...p..'} ], - edge: ['a~k', 'b~l', 'c~m', 'd~n', 'e~o', 'f~p'], - foot: {text: 'PoC.io.ddrio.in'} + edge: ['a|->k', 'b|->l', 'c|->m', 'd|->n', 'e|->o', 'f|->p'], + foot: { + text: ['tspan', + ['tspan', {'font-weight': 'bold'}, 'PoC.io.ddrio.in'], + ' -- DDR Data Input sampled from pad.' + ] + } } -.. code-block:: none +.. only:: latex - __ ____ ____ __ - Clock |____| |____| |____| - Pad < 0 >< 1 >< 2 >< 3 >< 4 >< 5 > - DataIn_low ... >< 0 >< 2 >< - DataIn_high ... >< 1 >< 3 >< + .. code-block:: none + __ ____ ____ __ + Clock |____| |____| |____| + Pad < 0 >< 1 >< 2 >< 3 >< 4 >< 5 > + DataIn_low ... >< 0 >< 2 >< + DataIn_high ... >< 1 >< 3 >< - < i > is the value of the i-th data bit on the line. + < i > is the value of the i-th data bit on the line. After power-up, the output ports ``DataIn_high`` and ``DataIn_low`` both equal INIT_VALUE. @@ -63,8 +70,10 @@ IOBs. :language: vhdl :tab-width: 2 :linenos: - :lines: 78-90 + :lines: 82-94 + -Source file: :pocsrc:`io/ddrio/ddrio_in.vhdl ` +.. only:: latex + Source file: :pocsrc:`io/ddrio/ddrio_in.vhdl ` diff --git a/docs/IPCores/io/ddrio/ddrio_inout.rst b/docs/IPCores/io/ddrio/ddrio_inout.rst index 0b215c6e..caaade74 100644 --- a/docs/IPCores/io/ddrio/ddrio_inout.rst +++ b/docs/IPCores/io/ddrio/ddrio_inout.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/ddrio/ddrio_inout.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/ddrio/ddrio_inout_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/ddrio/ddrio_inout.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/ddrio/ddrio_inout_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:ddrio_inout: @@ -57,6 +60,8 @@ IOBs. :linenos: :lines: 70-88 -Source file: :pocsrc:`io/ddrio/ddrio_inout.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/ddrio/ddrio_inout.vhdl ` diff --git a/docs/IPCores/io/ddrio/ddrio_out.rst b/docs/IPCores/io/ddrio/ddrio_out.rst index b13dd7d9..171b8a00 100644 --- a/docs/IPCores/io/ddrio/ddrio_out.rst +++ b/docs/IPCores/io/ddrio/ddrio_out.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/ddrio/ddrio_out.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/ddrio/ddrio_out_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/ddrio/ddrio_out.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/ddrio/ddrio_out_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:ddrio_out: @@ -44,6 +47,8 @@ IOBs. :linenos: :lines: 57-71 -Source file: :pocsrc:`io/ddrio/ddrio_out.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/ddrio/ddrio_out.vhdl ` diff --git a/docs/IPCores/io/iic/iic.pkg.rst b/docs/IPCores/io/iic/iic.pkg.rst index 787e0094..32081b55 100644 --- a/docs/IPCores/io/iic/iic.pkg.rst +++ b/docs/IPCores/io/iic/iic.pkg.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/iic/iic.pkg.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/iic/iic.pkg.vhdl + :alt: Source Code on GitHub - |gh-src| :pocsrc:`Sourcecode ` + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` .. _PKG:iic: PoC.io.iic Package ================== -Source file: :pocsrc:`iic.pkg.vhdl ` +.. only:: latex + Source file: :pocsrc:`iic.pkg.vhdl ` diff --git a/docs/IPCores/io/iic/iic_BusController.rst b/docs/IPCores/io/iic/iic_BusController.rst index 077f90d4..8d33a198 100644 --- a/docs/IPCores/io/iic/iic_BusController.rst +++ b/docs/IPCores/io/iic/iic_BusController.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/iic/iic_BusController.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/iic/iic_BusController_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/iic/iic_BusController.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/iic/iic_BusController_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:iic_BusController: @@ -32,6 +35,8 @@ controller is compatible to the System Management Bus (SMBus). :linenos: :lines: 47-65 -Source file: :pocsrc:`io/iic/iic_BusController.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/iic/iic_BusController.vhdl ` diff --git a/docs/IPCores/io/iic/iic_Controller.rst b/docs/IPCores/io/iic/iic_Controller.rst index efb868a1..bb2ff129 100644 --- a/docs/IPCores/io/iic/iic_Controller.rst +++ b/docs/IPCores/io/iic/iic_Controller.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/iic/iic_Controller.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/iic/iic_Controller_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/iic/iic_Controller.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/iic/iic_Controller_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:iic_Controller: @@ -32,6 +35,8 @@ is compatible to the System Management Bus (SMBus). :linenos: :lines: 47-82 -Source file: :pocsrc:`io/iic/iic_Controller.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/iic/iic_Controller.vhdl ` diff --git a/docs/IPCores/io/iic/iic_Controller_SFF8431.rst b/docs/IPCores/io/iic/iic_Controller_SFF8431.rst index 85e82161..6ccb2aca 100644 --- a/docs/IPCores/io/iic/iic_Controller_SFF8431.rst +++ b/docs/IPCores/io/iic/iic_Controller_SFF8431.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/iic/iic_Controller_SFF8431.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/iic/iic_Controller_SFF8431_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/iic/iic_Controller_SFF8431.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/iic/iic_Controller_SFF8431_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:IICController_SFF8431: @@ -27,6 +30,8 @@ IICController_SFF8431 :linenos: :lines: 15-49 -Source file: :pocsrc:`io/iic/iic_Controller_SFF8431.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/iic/iic_Controller_SFF8431.vhdl ` diff --git a/docs/IPCores/io/iic/iic_Switch_PCA9548A.rst b/docs/IPCores/io/iic/iic_Switch_PCA9548A.rst index 5979dc78..07ce165f 100644 --- a/docs/IPCores/io/iic/iic_Switch_PCA9548A.rst +++ b/docs/IPCores/io/iic/iic_Switch_PCA9548A.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/iic/iic_Switch_PCA9548A.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/iic/iic_Switch_PCA9548A_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/iic/iic_Switch_PCA9548A.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/iic/iic_Switch_PCA9548A_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:iic_Switch_PCA9548A: @@ -29,6 +32,8 @@ iic_Switch_PCA9548A :linenos: :lines: 42-90 -Source file: :pocsrc:`io/iic/iic_Switch_PCA9548A.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/iic/iic_Switch_PCA9548A.vhdl ` diff --git a/docs/IPCores/io/io.pkg.rst b/docs/IPCores/io/io.pkg.rst index fb421f25..97c941c0 100644 --- a/docs/IPCores/io/io.pkg.rst +++ b/docs/IPCores/io/io.pkg.rst @@ -1,11 +1,13 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io.pkg.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io.pkg.vhdl + :alt: Source Code on GitHub - |gh-src| :pocsrc:`Sourcecode ` + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` .. _PKG:io: @@ -14,4 +16,6 @@ PoC.io Package This package holds all component declarations for this namespace. -Source file: :pocsrc:`io.pkg.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io.pkg.vhdl ` diff --git a/docs/IPCores/io/io_7SegmentMux_BCD.rst b/docs/IPCores/io/io_7SegmentMux_BCD.rst index 0217b6c4..31b702eb 100644 --- a/docs/IPCores/io/io_7SegmentMux_BCD.rst +++ b/docs/IPCores/io/io_7SegmentMux_BCD.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_7SegmentMux_BCD.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_7SegmentMux_BCD_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_7SegmentMux_BCD.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_7SegmentMux_BCD_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:io_7SegmentMux_BCD: @@ -32,6 +35,8 @@ numbers is supported. :linenos: :lines: 45-60 -Source file: :pocsrc:`io/io_7SegmentMux_BCD.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/io_7SegmentMux_BCD.vhdl ` diff --git a/docs/IPCores/io/io_7SegmentMux_HEX.rst b/docs/IPCores/io/io_7SegmentMux_HEX.rst index 98fe1f90..58b2ec48 100644 --- a/docs/IPCores/io/io_7SegmentMux_HEX.rst +++ b/docs/IPCores/io/io_7SegmentMux_HEX.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_7SegmentMux_HEX.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_7SegmentMux_HEX_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_7SegmentMux_HEX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_7SegmentMux_HEX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:io_7SegmentMux_HEX: @@ -31,6 +34,8 @@ are HEX encoded. A dot per digit is optional. :linenos: :lines: 45-60 -Source file: :pocsrc:`io/io_7SegmentMux_HEX.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/io_7SegmentMux_HEX.vhdl ` diff --git a/docs/IPCores/io/io_Debounce.rst b/docs/IPCores/io/io_Debounce.rst index 4e418c0e..04d30237 100644 --- a/docs/IPCores/io/io_Debounce.rst +++ b/docs/IPCores/io/io_Debounce.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_Debounce.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_Debounce_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_Debounce.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_Debounce_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:io_Debounce: @@ -40,6 +43,8 @@ of a two-FF input synchronizer on each input bit. :linenos: :lines: 52-67 -Source file: :pocsrc:`io/io_Debounce.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/io_Debounce.vhdl ` diff --git a/docs/IPCores/io/io_FanControl.rst b/docs/IPCores/io/io_FanControl.rst index 956ab4f2..a4d2a230 100644 --- a/docs/IPCores/io/io_FanControl.rst +++ b/docs/IPCores/io/io_FanControl.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_FanControl.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_FanControl_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_FanControl.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_FanControl_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:io_FanControl: @@ -48,6 +51,8 @@ io_FanControl :linenos: :lines: 63-81 -Source file: :pocsrc:`io/io_FanControl.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/io_FanControl.vhdl ` diff --git a/docs/IPCores/io/io_FrequencyCounter.rst b/docs/IPCores/io/io_FrequencyCounter.rst index cd53378d..90b56c8d 100644 --- a/docs/IPCores/io/io_FrequencyCounter.rst +++ b/docs/IPCores/io/io_FrequencyCounter.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_FrequencyCounter.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_FrequencyCounter_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_FrequencyCounter.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_FrequencyCounter_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:io_FrequencyCounter: @@ -29,6 +32,8 @@ io_FrequencyCounter :linenos: :lines: 40-52 -Source file: :pocsrc:`io/io_FrequencyCounter.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/io_FrequencyCounter.vhdl ` diff --git a/docs/IPCores/io/io_GlitchFilter.rst b/docs/IPCores/io/io_GlitchFilter.rst index bde06d95..3c40e808 100644 --- a/docs/IPCores/io/io_GlitchFilter.rst +++ b/docs/IPCores/io/io_GlitchFilter.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_GlitchFilter.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_GlitchFilter_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_GlitchFilter.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_GlitchFilter_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:io_GlitchFilter: @@ -30,6 +33,8 @@ cycle counts can be configured. :linenos: :lines: 41-51 -Source file: :pocsrc:`io/io_GlitchFilter.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/io_GlitchFilter.vhdl ` diff --git a/docs/IPCores/io/io_KeyPadScanner.rst b/docs/IPCores/io/io_KeyPadScanner.rst index 5fff5cfb..604a1b0a 100644 --- a/docs/IPCores/io/io_KeyPadScanner.rst +++ b/docs/IPCores/io/io_KeyPadScanner.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_KeyPadScanner.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_KeyPadScanner_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_KeyPadScanner.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_KeyPadScanner_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:io_KeyPadScanner: @@ -33,6 +36,8 @@ matrix is not debounced. :linenos: :lines: 46-63 -Source file: :pocsrc:`io/io_KeyPadScanner.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/io_KeyPadScanner.vhdl ` diff --git a/docs/IPCores/io/io_PulseWidthModulation.rst b/docs/IPCores/io/io_PulseWidthModulation.rst index 4555888a..e45c8a70 100644 --- a/docs/IPCores/io/io_PulseWidthModulation.rst +++ b/docs/IPCores/io/io_PulseWidthModulation.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_PulseWidthModulation.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_PulseWidthModulation_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_PulseWidthModulation.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_PulseWidthModulation_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:io_PulseWidthModulation: @@ -30,6 +33,8 @@ in frequency (``PWM_FREQ``) and modulation granularity (``PWM_RESOLUTION``). :linenos: :lines: 41-53 -Source file: :pocsrc:`io/io_PulseWidthModulation.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/io_PulseWidthModulation.vhdl ` diff --git a/docs/IPCores/io/io_TimingCounter.rst b/docs/IPCores/io/io_TimingCounter.rst index 85e61084..c7203047 100644 --- a/docs/IPCores/io/io_TimingCounter.rst +++ b/docs/IPCores/io/io_TimingCounter.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_TimingCounter.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_TimingCounter_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_TimingCounter.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_TimingCounter_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:io_TimingCounter: @@ -32,6 +35,8 @@ consisting of ``log2ceilnz(imax(TIMING_TABLE)) + 1`` 6-input LUTs. :linenos: :lines: 43-54 -Source file: :pocsrc:`io/io_TimingCounter.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/io_TimingCounter.vhdl ` diff --git a/docs/IPCores/io/lcd/lcd.pkg.rst b/docs/IPCores/io/lcd/lcd.pkg.rst index 63792d60..c0b93e55 100644 --- a/docs/IPCores/io/lcd/lcd.pkg.rst +++ b/docs/IPCores/io/lcd/lcd.pkg.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd.pkg.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd.pkg.vhdl + :alt: Source Code on GitHub - |gh-src| :pocsrc:`Sourcecode ` + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` .. _PKG:lcd: PoC.io.lcd Package ================== -Source file: :pocsrc:`lcd.pkg.vhdl ` +.. only:: latex + Source file: :pocsrc:`lcd.pkg.vhdl ` diff --git a/docs/IPCores/io/lcd/lcd_LCDBuffer.rst b/docs/IPCores/io/lcd/lcd_LCDBuffer.rst index 66fc6ad8..801ed2f6 100644 --- a/docs/IPCores/io/lcd/lcd_LCDBuffer.rst +++ b/docs/IPCores/io/lcd/lcd_LCDBuffer.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd_LCDBuffer.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/lcd/lcd_LCDBuffer_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd_LCDBuffer.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/lcd/lcd_LCDBuffer_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:lcd_LCDBuffer: @@ -29,6 +32,8 @@ lcd_LCDBuffer :linenos: :lines: 42-58 -Source file: :pocsrc:`io/lcd/lcd_LCDBuffer.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/lcd/lcd_LCDBuffer.vhdl ` diff --git a/docs/IPCores/io/lcd/lcd_LCDBusController.rst b/docs/IPCores/io/lcd/lcd_LCDBusController.rst index e5ead44c..fcf1e2f8 100644 --- a/docs/IPCores/io/lcd/lcd_LCDBusController.rst +++ b/docs/IPCores/io/lcd/lcd_LCDBusController.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd_LCDBusController.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/lcd/lcd_LCDBusController_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd_LCDBusController.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/lcd/lcd_LCDBusController_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:lcd_LCDBusController: @@ -29,6 +32,8 @@ lcd_LCDBusController :linenos: :lines: 43-67 -Source file: :pocsrc:`io/lcd/lcd_LCDBusController.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/lcd/lcd_LCDBusController.vhdl ` diff --git a/docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst b/docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst index 856d1428..992f5449 100644 --- a/docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst +++ b/docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd_LCDController_KS0066U.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/lcd/lcd_LCDController_KS0066U_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd_LCDController_KS0066U.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/lcd/lcd_LCDController_KS0066U_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:lcd_LCDController_KS0066U: @@ -29,6 +32,8 @@ lcd_LCDController_KS0066U :linenos: :lines: 42-64 -Source file: :pocsrc:`io/lcd/lcd_LCDController_KS0066U.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/lcd/lcd_LCDController_KS0066U.vhdl ` diff --git a/docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst b/docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst index 9d711368..c8fc89a2 100644 --- a/docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst +++ b/docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd_LCDSynchronizer.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/lcd/lcd_LCDSynchronizer_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd_LCDSynchronizer.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/lcd/lcd_LCDSynchronizer_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:lcd_LCDSynchronizer: @@ -29,6 +32,8 @@ lcd_LCDSynchronizer :linenos: :lines: 42-64 -Source file: :pocsrc:`io/lcd/lcd_LCDSynchronizer.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/lcd/lcd_LCDSynchronizer.vhdl ` diff --git a/docs/IPCores/io/lcd/lcd_dotmatrix.rst b/docs/IPCores/io/lcd/lcd_dotmatrix.rst index 5f31050c..643461de 100644 --- a/docs/IPCores/io/lcd/lcd_dotmatrix.rst +++ b/docs/IPCores/io/lcd/lcd_dotmatrix.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd_dotmatrix.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/lcd/lcd_dotmatrix_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd_dotmatrix.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/lcd/lcd_dotmatrix_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:lcd_dotmatrix: @@ -29,6 +32,8 @@ lcd_dotmatrix :linenos: :lines: 36-67 -Source file: :pocsrc:`io/lcd/lcd_dotmatrix.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/lcd/lcd_dotmatrix.vhdl ` diff --git a/docs/IPCores/io/mdio/mdio_Controller.rst b/docs/IPCores/io/mdio/mdio_Controller.rst index 210cedd0..260fe47c 100644 --- a/docs/IPCores/io/mdio/mdio_Controller.rst +++ b/docs/IPCores/io/mdio/mdio_Controller.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/mdio/mdio_Controller.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/mdio/mdio_Controller_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/mdio/mdio_Controller.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/mdio/mdio_Controller_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:mdio_Controller: @@ -29,6 +32,8 @@ mdio_Controller :linenos: :lines: 44-73 -Source file: :pocsrc:`io/mdio/mdio_Controller.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/mdio/mdio_Controller.vhdl ` diff --git a/docs/IPCores/io/mdio/mdio_IIC_Adapter.rst b/docs/IPCores/io/mdio/mdio_IIC_Adapter.rst index 6bac62e7..c8d3cabe 100644 --- a/docs/IPCores/io/mdio/mdio_IIC_Adapter.rst +++ b/docs/IPCores/io/mdio/mdio_IIC_Adapter.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/mdio/mdio_IIC_Adapter.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/mdio/mdio_IIC_Adapter_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/mdio/mdio_IIC_Adapter.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/mdio/mdio_IIC_Adapter_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:mdio_IIC_Adapter: @@ -29,6 +32,8 @@ mdio_IIC_Adapter :linenos: :lines: 44-80 -Source file: :pocsrc:`io/mdio/mdio_IIC_Adapter.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/mdio/mdio_IIC_Adapter.vhdl ` diff --git a/docs/IPCores/io/pio/pio_fifo_in.rst b/docs/IPCores/io/pio/pio_fifo_in.rst index 8c0d8df5..07a08532 100644 --- a/docs/IPCores/io/pio/pio_fifo_in.rst +++ b/docs/IPCores/io/pio/pio_fifo_in.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pio/pio_fifo_in.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pio/pio_fifo_in_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pio/pio_fifo_in.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pio/pio_fifo_in_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:pio_fifo_in: @@ -28,6 +31,8 @@ pio_fifo_in :linenos: :lines: 38-55 -Source file: :pocsrc:`io/pio/pio_fifo_in.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/pio/pio_fifo_in.vhdl ` diff --git a/docs/IPCores/io/pio/pio_fifo_out.rst b/docs/IPCores/io/pio/pio_fifo_out.rst index 784a2b1e..63b0418c 100644 --- a/docs/IPCores/io/pio/pio_fifo_out.rst +++ b/docs/IPCores/io/pio/pio_fifo_out.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pio/pio_fifo_out.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pio/pio_fifo_out_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pio/pio_fifo_out.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pio/pio_fifo_out_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:pio_fifo_out: @@ -28,6 +31,8 @@ pio_fifo_out :linenos: :lines: 38-55 -Source file: :pocsrc:`io/pio/pio_fifo_out.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/pio/pio_fifo_out.vhdl ` diff --git a/docs/IPCores/io/pio/pio_in.rst b/docs/IPCores/io/pio/pio_in.rst index f6c1b2de..48645919 100644 --- a/docs/IPCores/io/pio/pio_in.rst +++ b/docs/IPCores/io/pio/pio_in.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pio/pio_in.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pio/pio_in_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pio/pio_in.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pio/pio_in_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:pio_in: @@ -28,6 +31,8 @@ pio_in :linenos: :lines: 40-55 -Source file: :pocsrc:`io/pio/pio_in.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/pio/pio_in.vhdl ` diff --git a/docs/IPCores/io/pio/pio_out.rst b/docs/IPCores/io/pio/pio_out.rst index ff2dfea5..792644b5 100644 --- a/docs/IPCores/io/pio/pio_out.rst +++ b/docs/IPCores/io/pio/pio_out.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pio/pio_out.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pio/pio_out_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pio/pio_out.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pio/pio_out_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:pio_out: @@ -28,6 +31,8 @@ pio_out :linenos: :lines: 40-55 -Source file: :pocsrc:`io/pio/pio_out.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/pio/pio_out.vhdl ` diff --git a/docs/IPCores/io/pmod/pmod.pkg.rst b/docs/IPCores/io/pmod/pmod.pkg.rst index 0a42ad0a..c14884f6 100644 --- a/docs/IPCores/io/pmod/pmod.pkg.rst +++ b/docs/IPCores/io/pmod/pmod.pkg.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pmod/pmod.pkg.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pmod/pmod.pkg.vhdl + :alt: Source Code on GitHub - |gh-src| :pocsrc:`Sourcecode ` + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` .. _PKG:pmod: PoC.io.pmod Package =================== -Source file: :pocsrc:`pmod.pkg.vhdl ` +.. only:: latex + Source file: :pocsrc:`pmod.pkg.vhdl ` diff --git a/docs/IPCores/io/pmod/pmod_KYPD.rst b/docs/IPCores/io/pmod/pmod_KYPD.rst index 60bd0fc9..83a4ca4f 100644 --- a/docs/IPCores/io/pmod/pmod_KYPD.rst +++ b/docs/IPCores/io/pmod/pmod_KYPD.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pmod/pmod_KYPD.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pmod/pmod_KYPD_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pmod/pmod_KYPD.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pmod/pmod_KYPD_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:pmod_KYPD: @@ -34,6 +37,8 @@ the button signals. The scan frequency and bounce time can be configured. :linenos: :lines: 46-61 -Source file: :pocsrc:`io/pmod/pmod_KYPD.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/pmod/pmod_KYPD.vhdl ` diff --git a/docs/IPCores/io/pmod/pmod_SSD.rst b/docs/IPCores/io/pmod/pmod_SSD.rst index 215fdc78..4a65c8ff 100644 --- a/docs/IPCores/io/pmod/pmod_SSD.rst +++ b/docs/IPCores/io/pmod/pmod_SSD.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pmod/pmod_SSD.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pmod/pmod_SSD_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pmod/pmod_SSD.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pmod/pmod_SSD_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:pmod_SSD: @@ -42,6 +45,8 @@ Pmod connector (7 anode bits, 1 cathode bit). :linenos: :lines: 56-69 -Source file: :pocsrc:`io/pmod/pmod_SSD.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/pmod/pmod_SSD.vhdl ` diff --git a/docs/IPCores/io/pmod/pmod_USBUART.rst b/docs/IPCores/io/pmod/pmod_USBUART.rst index f34d0080..b86a0308 100644 --- a/docs/IPCores/io/pmod/pmod_USBUART.rst +++ b/docs/IPCores/io/pmod/pmod_USBUART.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pmod/pmod_USBUART.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pmod/pmod_USBUART_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pmod/pmod_USBUART.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pmod/pmod_USBUART_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:pmod_USBUART: @@ -32,6 +35,8 @@ Hardware flow control (RTS_CTS) is enabled. :linenos: :lines: 43-65 -Source file: :pocsrc:`io/pmod/pmod_USBUART.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/pmod/pmod_USBUART.vhdl ` diff --git a/docs/IPCores/io/uart/uart.pkg.rst b/docs/IPCores/io/uart/uart.pkg.rst index 9fecad90..37d06f2a 100644 --- a/docs/IPCores/io/uart/uart.pkg.rst +++ b/docs/IPCores/io/uart/uart.pkg.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart.pkg.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart.pkg.vhdl + :alt: Source Code on GitHub - |gh-src| :pocsrc:`Sourcecode ` + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` .. _PKG:uart: PoC.io.uart Package =================== -Source file: :pocsrc:`uart.pkg.vhdl ` +.. only:: latex + Source file: :pocsrc:`uart.pkg.vhdl ` diff --git a/docs/IPCores/io/uart/uart_bclk.rst b/docs/IPCores/io/uart/uart_bclk.rst index b0a9e7de..0d6381d9 100644 --- a/docs/IPCores/io/uart/uart_bclk.rst +++ b/docs/IPCores/io/uart/uart_bclk.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart_bclk.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/uart/uart_bclk_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart_bclk.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/uart/uart_bclk_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:uart_bclk: @@ -35,6 +38,8 @@ old comments: :linenos: :lines: 50-61 -Source file: :pocsrc:`io/uart/uart_bclk.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/uart/uart_bclk.vhdl ` diff --git a/docs/IPCores/io/uart/uart_fifo.rst b/docs/IPCores/io/uart/uart_fifo.rst index cd446978..3f4f79c4 100644 --- a/docs/IPCores/io/uart/uart_fifo.rst +++ b/docs/IPCores/io/uart/uart_fifo.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart_fifo.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/uart/uart_fifo_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart_fifo.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/uart/uart_fifo_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:uart_fifo: @@ -37,6 +40,8 @@ old comments: :linenos: :lines: 52-94 -Source file: :pocsrc:`io/uart/uart_fifo.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/uart/uart_fifo.vhdl ` diff --git a/docs/IPCores/io/uart/uart_ft245.rst b/docs/IPCores/io/uart/uart_ft245.rst index 457f2d72..739fe491 100644 --- a/docs/IPCores/io/uart/uart_ft245.rst +++ b/docs/IPCores/io/uart/uart_ft245.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart_ft245.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/uart/uart_ft245_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart_ft245.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/uart/uart_ft245_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:uart_ft245: @@ -29,6 +32,8 @@ uart_ft245 :linenos: :lines: 37-63 -Source file: :pocsrc:`io/uart/uart_ft245.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/uart/uart_ft245.vhdl ` diff --git a/docs/IPCores/io/uart/uart_rx.rst b/docs/IPCores/io/uart/uart_rx.rst index 6e0c91c9..a6a954ca 100644 --- a/docs/IPCores/io/uart/uart_rx.rst +++ b/docs/IPCores/io/uart/uart_rx.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart_rx.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/uart/uart_rx_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart_rx.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/uart/uart_rx_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:uart_rx: @@ -30,6 +33,8 @@ uart_rx :linenos: :lines: 39-56 -Source file: :pocsrc:`io/uart/uart_rx.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/uart/uart_rx.vhdl ` diff --git a/docs/IPCores/io/uart/uart_tx.rst b/docs/IPCores/io/uart/uart_tx.rst index 9d99c7c1..a0f3d93d 100644 --- a/docs/IPCores/io/uart/uart_tx.rst +++ b/docs/IPCores/io/uart/uart_tx.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart_tx.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/uart/uart_tx_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart_tx.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/uart/uart_tx_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:uart_tx: @@ -30,6 +33,8 @@ uart_tx :linenos: :lines: 35-50 -Source file: :pocsrc:`io/uart/uart_tx.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/uart/uart_tx.vhdl ` diff --git a/docs/IPCores/io/vga/vga.pkg.rst b/docs/IPCores/io/vga/vga.pkg.rst index ae03e623..d90f2041 100644 --- a/docs/IPCores/io/vga/vga.pkg.rst +++ b/docs/IPCores/io/vga/vga.pkg.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/vga/vga.pkg.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/vga/vga.pkg.vhdl + :alt: Source Code on GitHub - |gh-src| :pocsrc:`Sourcecode ` + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` .. _PKG:vga: PoC.io.vga Package ================== -Source file: :pocsrc:`vga.pkg.vhdl ` +.. only:: latex + Source file: :pocsrc:`vga.pkg.vhdl ` diff --git a/docs/IPCores/io/vga/vga_phy.rst b/docs/IPCores/io/vga/vga_phy.rst index 1ac7b6a4..b8fa8a02 100644 --- a/docs/IPCores/io/vga/vga_phy.rst +++ b/docs/IPCores/io/vga/vga_phy.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/vga/vga_phy.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/vga/vga_phy_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/vga/vga_phy.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/vga/vga_phy_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:vga_phy: @@ -33,6 +36,8 @@ vga_phy :linenos: :lines: 43-55 -Source file: :pocsrc:`io/vga/vga_phy.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/vga/vga_phy.vhdl ` diff --git a/docs/IPCores/io/vga/vga_phy_ch7301c.rst b/docs/IPCores/io/vga/vga_phy_ch7301c.rst index b0e639ca..63812466 100644 --- a/docs/IPCores/io/vga/vga_phy_ch7301c.rst +++ b/docs/IPCores/io/vga/vga_phy_ch7301c.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/vga/vga_phy_ch7301c.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/vga/vga_phy_ch7301c_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/vga/vga_phy_ch7301c.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/vga/vga_phy_ch7301c_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:vga_phy_ch7301c: @@ -60,6 +63,8 @@ tests/ml505/vga_test_ml505.vhdl for an example. :linenos: :lines: 70-83 -Source file: :pocsrc:`io/vga/vga_phy_ch7301c.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/vga/vga_phy_ch7301c.vhdl ` diff --git a/docs/IPCores/io/vga/vga_timing.rst b/docs/IPCores/io/vga/vga_timing.rst index aa822f74..5626ce41 100644 --- a/docs/IPCores/io/vga/vga_timing.rst +++ b/docs/IPCores/io/vga/vga_timing.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/vga/vga_timing.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/vga/vga_timing_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/vga/vga_timing.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/vga/vga_timing_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:vga_timing: @@ -68,6 +71,8 @@ differ between SMT and CVT. :linenos: :lines: 80-96 -Source file: :pocsrc:`io/vga/vga_timing.vhdl ` +.. only:: latex + + Source file: :pocsrc:`io/vga/vga_timing.vhdl ` diff --git a/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst b/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst index d9afec35..df79f3fc 100644 --- a/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst +++ b/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ddr2/ddr2_mem2mig_adapter_Spartan6_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ddr2/ddr2_mem2mig_adapter_Spartan6_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:ddr2_mem2mig_adapter_Spartan6: @@ -51,6 +54,8 @@ Containts only combinational logic. :linenos: :lines: 61-95 -Source file: :pocsrc:`mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl ` +.. only:: latex + + Source file: :pocsrc:`mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl ` diff --git a/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst b/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst index 4977ca1a..15ddeac8 100644 --- a/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst +++ b/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ddr3/ddr3_mem2mig_adapter_Series7_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ddr3/ddr3_mem2mig_adapter_Series7_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:ddr3_mem2mig_adapter_Series7: @@ -50,6 +53,8 @@ Containts only combinational logic. :linenos: :lines: 60-95 -Source file: :pocsrc:`mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl ` +.. only:: latex + + Source file: :pocsrc:`mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl ` diff --git a/docs/IPCores/mem/lut/lut_Sine.rst b/docs/IPCores/mem/lut/lut_Sine.rst index fa9dd8a5..d0c51703 100644 --- a/docs/IPCores/mem/lut/lut_Sine.rst +++ b/docs/IPCores/mem/lut/lut_Sine.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/lut/lut_Sine.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/lut/lut_Sine_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/lut/lut_Sine.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/lut/lut_Sine_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:lut_Sine: @@ -29,6 +32,8 @@ lut_Sine :linenos: :lines: 41-54 -Source file: :pocsrc:`mem/lut/lut_Sine.vhdl ` +.. only:: latex + + Source file: :pocsrc:`mem/lut/lut_Sine.vhdl ` diff --git a/docs/IPCores/mem/mem.pkg.rst b/docs/IPCores/mem/mem.pkg.rst index 5f0fc3a1..de7f45ef 100644 --- a/docs/IPCores/mem/mem.pkg.rst +++ b/docs/IPCores/mem/mem.pkg.rst @@ -1,11 +1,13 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/mem.pkg.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/mem.pkg.vhdl + :alt: Source Code on GitHub - |gh-src| :pocsrc:`Sourcecode ` + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` .. _PKG:mem: @@ -14,4 +16,6 @@ PoC.mem Package This package holds all component declarations for this namespace. -Source file: :pocsrc:`mem.pkg.vhdl ` +.. only:: latex + + Source file: :pocsrc:`mem.pkg.vhdl ` diff --git a/docs/IPCores/mem/ocram/ocram.pkg.rst b/docs/IPCores/mem/ocram/ocram.pkg.rst index f3a0e805..cd8bcb34 100644 --- a/docs/IPCores/mem/ocram/ocram.pkg.rst +++ b/docs/IPCores/mem/ocram/ocram.pkg.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram.pkg.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram.pkg.vhdl + :alt: Source Code on GitHub - |gh-src| :pocsrc:`Sourcecode ` + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` .. _PKG:ocram: PoC.mem.ocram Package ===================== -Source file: :pocsrc:`ocram.pkg.vhdl ` +.. only:: latex + Source file: :pocsrc:`ocram.pkg.vhdl ` diff --git a/docs/IPCores/mem/ocram/ocram_esdp.rst b/docs/IPCores/mem/ocram/ocram_esdp.rst index ac2be841..7ba73188 100644 --- a/docs/IPCores/mem/ocram/ocram_esdp.rst +++ b/docs/IPCores/mem/ocram/ocram_esdp.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram_esdp.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocram/ocram_esdp_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram_esdp.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocram/ocram_esdp_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:ocram_esdp: @@ -83,6 +86,8 @@ Mixed-Port Read-During-Write :linenos: :lines: 101-119 -Source file: :pocsrc:`mem/ocram/ocram_esdp.vhdl ` +.. only:: latex + + Source file: :pocsrc:`mem/ocram/ocram_esdp.vhdl ` diff --git a/docs/IPCores/mem/ocram/ocram_sdp.rst b/docs/IPCores/mem/ocram/ocram_sdp.rst index 2169056a..f00d245c 100644 --- a/docs/IPCores/mem/ocram/ocram_sdp.rst +++ b/docs/IPCores/mem/ocram/ocram_sdp.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram_sdp.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocram/ocram_sdp_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram_sdp.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocram/ocram_sdp_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:ocram_sdp: @@ -49,6 +52,8 @@ Mixed-Port Read-During-Write :linenos: :lines: 65-82 -Source file: :pocsrc:`mem/ocram/ocram_sdp.vhdl ` +.. only:: latex + + Source file: :pocsrc:`mem/ocram/ocram_sdp.vhdl ` diff --git a/docs/IPCores/mem/ocram/ocram_sp.rst b/docs/IPCores/mem/ocram/ocram_sp.rst index 86322a29..c8f392d9 100644 --- a/docs/IPCores/mem/ocram/ocram_sp.rst +++ b/docs/IPCores/mem/ocram/ocram_sp.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram_sp.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocram/ocram_sp_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram_sp.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocram/ocram_sp_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:ocram_sp: @@ -52,6 +55,8 @@ also applies to Altera M20K memory blocks as described in the Altera: :linenos: :lines: 68-82 -Source file: :pocsrc:`mem/ocram/ocram_sp.vhdl ` +.. only:: latex + + Source file: :pocsrc:`mem/ocram/ocram_sp.vhdl ` diff --git a/docs/IPCores/mem/ocram/ocram_tdp.rst b/docs/IPCores/mem/ocram/ocram_tdp.rst index ef13a067..fc35644e 100644 --- a/docs/IPCores/mem/ocram/ocram_tdp.rst +++ b/docs/IPCores/mem/ocram/ocram_tdp.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram_tdp.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocram/ocram_tdp_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram_tdp.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocram/ocram_tdp_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:ocram_tdp: @@ -68,6 +71,8 @@ Mixed-Port Read-During-Write :linenos: :lines: 84-104 -Source file: :pocsrc:`mem/ocram/ocram_tdp.vhdl ` +.. only:: latex + + Source file: :pocsrc:`mem/ocram/ocram_tdp.vhdl ` diff --git a/docs/IPCores/mem/ocrom/ocrom.pkg.rst b/docs/IPCores/mem/ocrom/ocrom.pkg.rst index df23511e..a1d7c051 100644 --- a/docs/IPCores/mem/ocrom/ocrom.pkg.rst +++ b/docs/IPCores/mem/ocrom/ocrom.pkg.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocrom/ocrom.pkg.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocrom/ocrom.pkg.vhdl + :alt: Source Code on GitHub - |gh-src| :pocsrc:`Sourcecode ` + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` .. _PKG:ocrom: PoC.mem.ocrom Package ===================== -Source file: :pocsrc:`ocrom.pkg.vhdl ` +.. only:: latex + Source file: :pocsrc:`ocrom.pkg.vhdl ` diff --git a/docs/IPCores/mem/ocrom/ocrom_dp.rst b/docs/IPCores/mem/ocrom/ocrom_dp.rst index fcbc610d..e13bb88f 100644 --- a/docs/IPCores/mem/ocrom/ocrom_dp.rst +++ b/docs/IPCores/mem/ocrom/ocrom_dp.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocrom/ocrom_dp.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocrom/ocrom_dp_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocrom/ocrom_dp.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocrom/ocrom_dp_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:ocrom_dp: @@ -40,6 +43,8 @@ TODO: implement correct behavior for RT-level simulation :linenos: :lines: 60-76 -Source file: :pocsrc:`mem/ocrom/ocrom_dp.vhdl ` +.. only:: latex + + Source file: :pocsrc:`mem/ocrom/ocrom_dp.vhdl ` diff --git a/docs/IPCores/mem/ocrom/ocrom_sp.rst b/docs/IPCores/mem/ocrom/ocrom_sp.rst index d2b7583d..68654cbd 100644 --- a/docs/IPCores/mem/ocrom/ocrom_sp.rst +++ b/docs/IPCores/mem/ocrom/ocrom_sp.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocrom/ocrom_sp.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocrom/ocrom_sp_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocrom/ocrom_sp.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocrom/ocrom_sp_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:ocrom_sp: @@ -33,6 +36,8 @@ Inferring / instantiating single-port read-only memory :linenos: :lines: 53-65 -Source file: :pocsrc:`mem/ocrom/ocrom_sp.vhdl ` +.. only:: latex + + Source file: :pocsrc:`mem/ocrom/ocrom_sp.vhdl ` diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst b/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst index 6685e72e..27104443 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/sdram/sdram_ctrl_de0.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/sdram/sdram_ctrl_de0_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/sdram/sdram_ctrl_de0.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/sdram/sdram_ctrl_de0_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:sdram_ctrl_de0: @@ -59,6 +62,8 @@ Synchronous resets are used. :linenos: :lines: 68-100 -Source file: :pocsrc:`mem/sdram/sdram_ctrl_de0.vhdl ` +.. only:: latex + + Source file: :pocsrc:`mem/sdram/sdram_ctrl_de0.vhdl ` diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst b/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst index 5f3764af..abeacbb4 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/sdram/sdram_ctrl_fsm.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/sdram/sdram_ctrl_fsm_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/sdram/sdram_ctrl_fsm.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/sdram/sdram_ctrl_fsm_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:sdram_ctrl_fsm: @@ -95,6 +98,8 @@ The write data must directly connected to the physical layer. :linenos: :lines: 104-148 -Source file: :pocsrc:`mem/sdram/sdram_ctrl_fsm.vhdl ` +.. only:: latex + + Source file: :pocsrc:`mem/sdram/sdram_ctrl_fsm.vhdl ` diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst b/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst index 5f1c946c..eb144d93 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/sdram/sdram_ctrl_phy_de0.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/sdram/sdram_ctrl_phy_de0_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/sdram/sdram_ctrl_phy_de0.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/sdram/sdram_ctrl_phy_de0_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:sdram_ctrl_phy_de0: @@ -61,6 +64,8 @@ Synchronous resets are used. Reset must be hold for at least two cycles. :linenos: :lines: 89-122 -Source file: :pocsrc:`mem/sdram/sdram_ctrl_phy_de0.vhdl ` +.. only:: latex + + Source file: :pocsrc:`mem/sdram/sdram_ctrl_phy_de0.vhdl ` diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst b/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst index 9ac446a9..2ae8d48b 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/sdram/sdram_ctrl_phy_s3esk_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/sdram/sdram_ctrl_phy_s3esk_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:sdram_ctrl_phy_s3esk: @@ -99,6 +102,8 @@ Synchronous resets are used. Reset must be hold for at least two cycles. :linenos: :lines: 107-151 -Source file: :pocsrc:`mem/sdram/sdram_ctrl_phy_s3esk.vhdl ` +.. only:: latex + + Source file: :pocsrc:`mem/sdram/sdram_ctrl_phy_s3esk.vhdl ` diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst b/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst index 19499987..8c6c5fa2 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/sdram/sdram_ctrl_s3esk.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/sdram/sdram_ctrl_s3esk_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/sdram/sdram_ctrl_s3esk.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/sdram/sdram_ctrl_s3esk_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:sdram_ctrl_s3esk: @@ -60,6 +63,8 @@ Synchronous resets are used. :linenos: :lines: 69-112 -Source file: :pocsrc:`mem/sdram/sdram_ctrl_s3esk.vhdl ` +.. only:: latex + + Source file: :pocsrc:`mem/sdram/sdram_ctrl_s3esk.vhdl ` diff --git a/docs/IPCores/misc/filter/filter_and.rst b/docs/IPCores/misc/filter/filter_and.rst index 8d47f49a..0cdcfa33 100644 --- a/docs/IPCores/misc/filter/filter_and.rst +++ b/docs/IPCores/misc/filter/filter_and.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/filter/filter_and.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/filter/filter_and_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/filter/filter_and.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/filter/filter_and_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:filter_and: @@ -29,6 +32,8 @@ filter_and :linenos: :lines: 37-48 -Source file: :pocsrc:`misc/filter/filter_and.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/filter/filter_and.vhdl ` diff --git a/docs/IPCores/misc/filter/filter_mean.rst b/docs/IPCores/misc/filter/filter_mean.rst index 13cc8e97..2dcb4a61 100644 --- a/docs/IPCores/misc/filter/filter_mean.rst +++ b/docs/IPCores/misc/filter/filter_mean.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/filter/filter_mean.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/filter/filter_mean_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/filter/filter_mean.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/filter/filter_mean_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:filter_mean: @@ -29,6 +32,8 @@ filter_mean :linenos: :lines: 37-48 -Source file: :pocsrc:`misc/filter/filter_mean.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/filter/filter_mean.vhdl ` diff --git a/docs/IPCores/misc/filter/filter_or.rst b/docs/IPCores/misc/filter/filter_or.rst index 2d8d9bf7..376f887a 100644 --- a/docs/IPCores/misc/filter/filter_or.rst +++ b/docs/IPCores/misc/filter/filter_or.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/filter/filter_or.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/filter/filter_or_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/filter/filter_or.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/filter/filter_or_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:filter_or: @@ -29,6 +32,8 @@ filter_or :linenos: :lines: 37-48 -Source file: :pocsrc:`misc/filter/filter_or.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/filter/filter_or.vhdl ` diff --git a/docs/IPCores/misc/gearbox/gearbox_down_cc.rst b/docs/IPCores/misc/gearbox/gearbox_down_cc.rst index 6cdf8fca..eb9533d4 100644 --- a/docs/IPCores/misc/gearbox/gearbox_down_cc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_down_cc.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/gearbox/gearbox_down_cc.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/gearbox/gearbox_down_cc_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/gearbox/gearbox_down_cc.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/gearbox/gearbox_down_cc_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:gearbox_down_cc: @@ -33,6 +36,8 @@ gearbox_down_cc :linenos: :lines: 46-70 -Source file: :pocsrc:`misc/gearbox/gearbox_down_cc.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/gearbox/gearbox_down_cc.vhdl ` diff --git a/docs/IPCores/misc/gearbox/gearbox_down_dc.rst b/docs/IPCores/misc/gearbox/gearbox_down_dc.rst index 5c2972c4..468765c7 100644 --- a/docs/IPCores/misc/gearbox/gearbox_down_dc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_down_dc.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/gearbox/gearbox_down_dc.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/gearbox/gearbox_down_dc_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/gearbox/gearbox_down_dc.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/gearbox/gearbox_down_dc_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:gearbox_down_dc: @@ -38,6 +41,8 @@ Assertions: :linenos: :lines: 50-64 -Source file: :pocsrc:`misc/gearbox/gearbox_down_dc.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/gearbox/gearbox_down_dc.vhdl ` diff --git a/docs/IPCores/misc/gearbox/gearbox_up_cc.rst b/docs/IPCores/misc/gearbox/gearbox_up_cc.rst index fce085ad..92758f45 100644 --- a/docs/IPCores/misc/gearbox/gearbox_up_cc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_up_cc.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/gearbox/gearbox_up_cc.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/gearbox/gearbox_up_cc_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/gearbox/gearbox_up_cc.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/gearbox/gearbox_up_cc_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:gearbox_up_cc: @@ -33,6 +36,8 @@ gearbox_up_cc :linenos: :lines: 46-69 -Source file: :pocsrc:`misc/gearbox/gearbox_up_cc.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/gearbox/gearbox_up_cc.vhdl ` diff --git a/docs/IPCores/misc/gearbox/gearbox_up_dc.rst b/docs/IPCores/misc/gearbox/gearbox_up_dc.rst index ecb9a9a6..c09146ee 100644 --- a/docs/IPCores/misc/gearbox/gearbox_up_dc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_up_dc.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/gearbox/gearbox_up_dc.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/gearbox/gearbox_up_dc_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/gearbox/gearbox_up_dc.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/gearbox/gearbox_up_dc_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:gearbox_up_dc: @@ -39,6 +42,8 @@ Assertions: :linenos: :lines: 51-66 -Source file: :pocsrc:`misc/gearbox/gearbox_up_dc.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/gearbox/gearbox_up_dc.vhdl ` diff --git a/docs/IPCores/misc/misc.pkg.rst b/docs/IPCores/misc/misc.pkg.rst index 63f01d03..77f5f7f5 100644 --- a/docs/IPCores/misc/misc.pkg.rst +++ b/docs/IPCores/misc/misc.pkg.rst @@ -1,11 +1,13 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc.pkg.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc.pkg.vhdl + :alt: Source Code on GitHub - |gh-src| :pocsrc:`Sourcecode ` + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` .. _PKG:misc: @@ -14,4 +16,6 @@ PoC.misc Package This package holds all component declarations for this namespace. -Source file: :pocsrc:`misc.pkg.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc.pkg.vhdl ` diff --git a/docs/IPCores/misc/misc_BitwidthConverter.rst b/docs/IPCores/misc/misc_BitwidthConverter.rst index dc1b1cad..0b26e5bd 100644 --- a/docs/IPCores/misc/misc_BitwidthConverter.rst +++ b/docs/IPCores/misc/misc_BitwidthConverter.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_BitwidthConverter.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_BitwidthConverter_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_BitwidthConverter.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_BitwidthConverter_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:misc_BitwidthConverter: @@ -27,6 +30,8 @@ misc_BitwidthConverter :linenos: :lines: 32-45 -Source file: :pocsrc:`misc/misc_BitwidthConverter.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/misc_BitwidthConverter.vhdl ` diff --git a/docs/IPCores/misc/misc_ByteAligner.rst b/docs/IPCores/misc/misc_ByteAligner.rst index 6c821706..b194faf1 100644 --- a/docs/IPCores/misc/misc_ByteAligner.rst +++ b/docs/IPCores/misc/misc_ByteAligner.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_ByteAligner.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_ByteAligner_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_ByteAligner.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_ByteAligner_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:misc_ByteAligner: @@ -29,6 +32,8 @@ misc_ByteAligner :linenos: :lines: 40-53 -Source file: :pocsrc:`misc/misc_ByteAligner.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/misc_ByteAligner.vhdl ` diff --git a/docs/IPCores/misc/misc_Delay.rst b/docs/IPCores/misc/misc_Delay.rst index b266b9a8..d8d61502 100644 --- a/docs/IPCores/misc/misc_Delay.rst +++ b/docs/IPCores/misc/misc_Delay.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_Delay.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_Delay_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_Delay.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_Delay_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:misc_Delay: @@ -29,6 +32,8 @@ misc_Delay :linenos: :lines: 38-50 -Source file: :pocsrc:`misc/misc_Delay.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/misc_Delay.vhdl ` diff --git a/docs/IPCores/misc/misc_FrequencyMeasurement.rst b/docs/IPCores/misc/misc_FrequencyMeasurement.rst index a933bde1..8a9baa99 100644 --- a/docs/IPCores/misc/misc_FrequencyMeasurement.rst +++ b/docs/IPCores/misc/misc_FrequencyMeasurement.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_FrequencyMeasurement.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_FrequencyMeasurement_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_FrequencyMeasurement.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_FrequencyMeasurement_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:misc_FrequencyMeasurement: @@ -31,6 +34,8 @@ value is the measured frequency in Hz. :linenos: :lines: 44-56 -Source file: :pocsrc:`misc/misc_FrequencyMeasurement.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/misc_FrequencyMeasurement.vhdl ` diff --git a/docs/IPCores/misc/misc_PulseTrain.rst b/docs/IPCores/misc/misc_PulseTrain.rst index e43344e7..9ce65b40 100644 --- a/docs/IPCores/misc/misc_PulseTrain.rst +++ b/docs/IPCores/misc/misc_PulseTrain.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_PulseTrain.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_PulseTrain_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_PulseTrain.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_PulseTrain_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:misc_PulseTrain: @@ -30,6 +33,8 @@ misc_PulseTrain :linenos: :lines: 41-51 -Source file: :pocsrc:`misc/misc_PulseTrain.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/misc_PulseTrain.vhdl ` diff --git a/docs/IPCores/misc/misc_Sequencer.rst b/docs/IPCores/misc/misc_Sequencer.rst index 9e5bac82..c8f3c56e 100644 --- a/docs/IPCores/misc/misc_Sequencer.rst +++ b/docs/IPCores/misc/misc_Sequencer.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_Sequencer.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_Sequencer_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_Sequencer.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_Sequencer_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:misc_Sequencer: @@ -29,6 +32,8 @@ misc_Sequencer :linenos: :lines: 40-56 -Source file: :pocsrc:`misc/misc_Sequencer.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/misc_Sequencer.vhdl ` diff --git a/docs/IPCores/misc/misc_StrobeGenerator.rst b/docs/IPCores/misc/misc_StrobeGenerator.rst index dba1a0a9..75529eeb 100644 --- a/docs/IPCores/misc/misc_StrobeGenerator.rst +++ b/docs/IPCores/misc/misc_StrobeGenerator.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_StrobeGenerator.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_StrobeGenerator_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_StrobeGenerator.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_StrobeGenerator_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:misc_StrobeGenerator: @@ -29,6 +32,8 @@ misc_StrobeGenerator :linenos: :lines: 40-49 -Source file: :pocsrc:`misc/misc_StrobeGenerator.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/misc_StrobeGenerator.vhdl ` diff --git a/docs/IPCores/misc/misc_StrobeLimiter.rst b/docs/IPCores/misc/misc_StrobeLimiter.rst index 3badfdf1..35e91499 100644 --- a/docs/IPCores/misc/misc_StrobeLimiter.rst +++ b/docs/IPCores/misc/misc_StrobeLimiter.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_StrobeLimiter.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_StrobeLimiter_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_StrobeLimiter.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_StrobeLimiter_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:misc_StrobeLimiter: @@ -29,6 +32,8 @@ misc_StrobeLimiter :linenos: :lines: 39-51 -Source file: :pocsrc:`misc/misc_StrobeLimiter.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/misc_StrobeLimiter.vhdl ` diff --git a/docs/IPCores/misc/misc_bit_lz.rst b/docs/IPCores/misc/misc_bit_lz.rst index 5224d825..016101c4 100644 --- a/docs/IPCores/misc/misc_bit_lz.rst +++ b/docs/IPCores/misc/misc_bit_lz.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_bit_lz.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_bit_lz_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_bit_lz.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_bit_lz_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:misc_bit_lz: @@ -65,6 +68,8 @@ misc_bit_lz :linenos: :lines: 69-91 -Source file: :pocsrc:`misc/misc_bit_lz.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/misc_bit_lz.vhdl ` diff --git a/docs/IPCores/misc/stat/stat_Average.rst b/docs/IPCores/misc/stat/stat_Average.rst index aedc5de9..9e782635 100644 --- a/docs/IPCores/misc/stat/stat_Average.rst +++ b/docs/IPCores/misc/stat/stat_Average.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/stat/stat_Average.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/stat/stat_Average_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/stat/stat_Average.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/stat/stat_Average_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:stat_Average: @@ -29,6 +32,8 @@ stat_Average :linenos: :lines: 41-58 -Source file: :pocsrc:`misc/stat/stat_Average.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/stat/stat_Average.vhdl ` diff --git a/docs/IPCores/misc/stat/stat_Histogram.rst b/docs/IPCores/misc/stat/stat_Histogram.rst index 69ae2c40..9c945b46 100644 --- a/docs/IPCores/misc/stat/stat_Histogram.rst +++ b/docs/IPCores/misc/stat/stat_Histogram.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/stat/stat_Histogram.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/stat/stat_Histogram_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/stat/stat_Histogram.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/stat/stat_Histogram_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:stat_Histogram: @@ -29,6 +32,8 @@ stat_Histogram :linenos: :lines: 40-54 -Source file: :pocsrc:`misc/stat/stat_Histogram.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/stat/stat_Histogram.vhdl ` diff --git a/docs/IPCores/misc/stat/stat_Maximum.rst b/docs/IPCores/misc/stat/stat_Maximum.rst index 65a9b785..4c57dffd 100644 --- a/docs/IPCores/misc/stat/stat_Maximum.rst +++ b/docs/IPCores/misc/stat/stat_Maximum.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/stat/stat_Maximum.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/stat/stat_Maximum_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/stat/stat_Maximum.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/stat/stat_Maximum_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:stat_Maximum: @@ -29,6 +32,8 @@ stat_Maximum :linenos: :lines: 40-57 -Source file: :pocsrc:`misc/stat/stat_Maximum.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/stat/stat_Maximum.vhdl ` diff --git a/docs/IPCores/misc/stat/stat_Minimum.rst b/docs/IPCores/misc/stat/stat_Minimum.rst index 00c43b3a..f5591b28 100644 --- a/docs/IPCores/misc/stat/stat_Minimum.rst +++ b/docs/IPCores/misc/stat/stat_Minimum.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/stat/stat_Minimum.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/stat/stat_Minimum_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/stat/stat_Minimum.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/stat/stat_Minimum_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:stat_Minimum: @@ -29,6 +32,8 @@ stat_Minimum :linenos: :lines: 40-57 -Source file: :pocsrc:`misc/stat/stat_Minimum.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/stat/stat_Minimum.vhdl ` diff --git a/docs/IPCores/misc/sync/sync.pkg.rst b/docs/IPCores/misc/sync/sync.pkg.rst index 5a3e19b8..87a92d03 100644 --- a/docs/IPCores/misc/sync/sync.pkg.rst +++ b/docs/IPCores/misc/sync/sync.pkg.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync.pkg.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync.pkg.vhdl + :alt: Source Code on GitHub - |gh-src| :pocsrc:`Sourcecode ` + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` .. _PKG:sync: PoC.misc.sync Package ===================== -Source file: :pocsrc:`sync.pkg.vhdl ` +.. only:: latex + Source file: :pocsrc:`sync.pkg.vhdl ` diff --git a/docs/IPCores/misc/sync/sync_Bits.rst b/docs/IPCores/misc/sync/sync_Bits.rst index 19c9ccff..3eb3e8bb 100644 --- a/docs/IPCores/misc/sync/sync_Bits.rst +++ b/docs/IPCores/misc/sync/sync_Bits.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Bits.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Bits_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Bits.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Bits_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:sync_Bits: @@ -47,8 +50,6 @@ Constraints: :linenos: :lines: 68-79 -Source file: :pocsrc:`misc/sync/sync_Bits.vhdl ` - .. seealso:: :doc:`PoC.misc.sync.Reset ` @@ -61,3 +62,7 @@ Source file: :pocsrc:`misc/sync/sync_Bits.vhdl ` For a multiple bits capable synchronizer. + +.. only:: latex + + Source file: :pocsrc:`misc/sync/sync_Bits.vhdl ` diff --git a/docs/IPCores/misc/sync/sync_Command.rst b/docs/IPCores/misc/sync/sync_Command.rst index aaf13394..e40fd791 100644 --- a/docs/IPCores/misc/sync/sync_Command.rst +++ b/docs/IPCores/misc/sync/sync_Command.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Command.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Command_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Command.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Command_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:sync_Command: @@ -39,6 +42,8 @@ Constraints: :linenos: :lines: 50-63 -Source file: :pocsrc:`misc/sync/sync_Command.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/sync/sync_Command.vhdl ` diff --git a/docs/IPCores/misc/sync/sync_Pulse.rst b/docs/IPCores/misc/sync/sync_Pulse.rst index b74f65d2..53ee6d34 100644 --- a/docs/IPCores/misc/sync/sync_Pulse.rst +++ b/docs/IPCores/misc/sync/sync_Pulse.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Pulse.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Pulse_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Pulse.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Pulse_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:sync_Pulse: @@ -47,8 +50,6 @@ Constraints: :linenos: :lines: 68-78 -Source file: :pocsrc:`misc/sync/sync_Pulse.vhdl ` - .. seealso:: :doc:`PoC.misc.sync.Bits ` @@ -61,3 +62,7 @@ Source file: :pocsrc:`misc/sync/sync_Pulse.vhdl ` For a multiple bits capable synchronizer. + +.. only:: latex + + Source file: :pocsrc:`misc/sync/sync_Pulse.vhdl ` diff --git a/docs/IPCores/misc/sync/sync_Reset.rst b/docs/IPCores/misc/sync/sync_Reset.rst index b89017f6..7ef53d2b 100644 --- a/docs/IPCores/misc/sync/sync_Reset.rst +++ b/docs/IPCores/misc/sync/sync_Reset.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Reset.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Reset_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Reset.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Reset_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:sync_Reset: @@ -49,6 +52,8 @@ Constraints: :linenos: :lines: 60-69 -Source file: :pocsrc:`misc/sync/sync_Reset.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/sync/sync_Reset.vhdl ` diff --git a/docs/IPCores/misc/sync/sync_Strobe.rst b/docs/IPCores/misc/sync/sync_Strobe.rst index 4f68fc44..8f558df5 100644 --- a/docs/IPCores/misc/sync/sync_Strobe.rst +++ b/docs/IPCores/misc/sync/sync_Strobe.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Strobe.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Strobe_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Strobe.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Strobe_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:sync_Strobe: @@ -27,7 +30,7 @@ suppressed by a rising edge detection. .. ATTENTION:: Use this synchronizer only for one-cycle high-active signals (strobes). -.. image:: ../../../_static/misc/sync/sync_Strobe.svg +.. image:: /_static/misc/sync/sync_Strobe.* :target: ../../../_static/misc/sync/sync_Strobe.svg Constraints: @@ -44,6 +47,8 @@ Constraints: :linenos: :lines: 54-66 -Source file: :pocsrc:`misc/sync/sync_Strobe.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/sync/sync_Strobe.vhdl ` diff --git a/docs/IPCores/misc/sync/sync_Vector.rst b/docs/IPCores/misc/sync/sync_Vector.rst index c959e08f..ce164581 100644 --- a/docs/IPCores/misc/sync/sync_Vector.rst +++ b/docs/IPCores/misc/sync/sync_Vector.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Vector.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Vector_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Vector.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Vector_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:sync_Vector: @@ -38,6 +41,8 @@ Constraints: :linenos: :lines: 49-63 -Source file: :pocsrc:`misc/sync/sync_Vector.vhdl ` +.. only:: latex + + Source file: :pocsrc:`misc/sync/sync_Vector.vhdl ` diff --git a/docs/IPCores/net/arp/arp_BroadCast_Receiver.rst b/docs/IPCores/net/arp/arp_BroadCast_Receiver.rst index 25def10c..ef17cfc7 100644 --- a/docs/IPCores/net/arp/arp_BroadCast_Receiver.rst +++ b/docs/IPCores/net/arp/arp_BroadCast_Receiver.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_BroadCast_Receiver.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_BroadCast_Receiver_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_BroadCast_Receiver.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_BroadCast_Receiver_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arp_BroadCast_Receiver: @@ -29,6 +32,8 @@ arp_BroadCast_Receiver :linenos: :lines: 42-74 -Source file: :pocsrc:`net/arp/arp_BroadCast_Receiver.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/arp/arp_BroadCast_Receiver.vhdl ` diff --git a/docs/IPCores/net/arp/arp_BroadCast_Requester.rst b/docs/IPCores/net/arp/arp_BroadCast_Requester.rst index 01e5d526..83f99dd1 100644 --- a/docs/IPCores/net/arp/arp_BroadCast_Requester.rst +++ b/docs/IPCores/net/arp/arp_BroadCast_Requester.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_BroadCast_Requester.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_BroadCast_Requester_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_BroadCast_Requester.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_BroadCast_Requester_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arp_BroadCast_Requester: @@ -29,6 +32,8 @@ arp_BroadCast_Requester :linenos: :lines: 42-73 -Source file: :pocsrc:`net/arp/arp_BroadCast_Requester.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/arp/arp_BroadCast_Requester.vhdl ` diff --git a/docs/IPCores/net/arp/arp_Cache.rst b/docs/IPCores/net/arp/arp_Cache.rst index 8103a188..3b6847f6 100644 --- a/docs/IPCores/net/arp/arp_Cache.rst +++ b/docs/IPCores/net/arp/arp_Cache.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_Cache.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_Cache_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_Cache.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_Cache_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arp_Cache: @@ -29,6 +32,8 @@ arp_Cache :linenos: :lines: 44-75 -Source file: :pocsrc:`net/arp/arp_Cache.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/arp/arp_Cache.vhdl ` diff --git a/docs/IPCores/net/arp/arp_IPPool.rst b/docs/IPCores/net/arp/arp_IPPool.rst index 27a28095..950e2069 100644 --- a/docs/IPCores/net/arp/arp_IPPool.rst +++ b/docs/IPCores/net/arp/arp_IPPool.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_IPPool.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_IPPool_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_IPPool.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_IPPool_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arp_IPPool: @@ -29,6 +32,8 @@ arp_IPPool :linenos: :lines: 43-63 -Source file: :pocsrc:`net/arp/arp_IPPool.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/arp/arp_IPPool.vhdl ` diff --git a/docs/IPCores/net/arp/arp_Tester.rst b/docs/IPCores/net/arp/arp_Tester.rst index 09e9a8cd..23275a0c 100644 --- a/docs/IPCores/net/arp/arp_Tester.rst +++ b/docs/IPCores/net/arp/arp_Tester.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_Tester.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_Tester_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_Tester.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_Tester_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arp_Tester: @@ -29,6 +32,8 @@ arp_Tester :linenos: :lines: 43-65 -Source file: :pocsrc:`net/arp/arp_Tester.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/arp/arp_Tester.vhdl ` diff --git a/docs/IPCores/net/arp/arp_UniCast_Receiver.rst b/docs/IPCores/net/arp/arp_UniCast_Receiver.rst index dcd72188..45f7f02a 100644 --- a/docs/IPCores/net/arp/arp_UniCast_Receiver.rst +++ b/docs/IPCores/net/arp/arp_UniCast_Receiver.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_UniCast_Receiver.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_UniCast_Receiver_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_UniCast_Receiver.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_UniCast_Receiver_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arp_UniCast_Receiver: @@ -29,6 +32,8 @@ arp_UniCast_Receiver :linenos: :lines: 42-76 -Source file: :pocsrc:`net/arp/arp_UniCast_Receiver.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/arp/arp_UniCast_Receiver.vhdl ` diff --git a/docs/IPCores/net/arp/arp_UniCast_Responder.rst b/docs/IPCores/net/arp/arp_UniCast_Responder.rst index 9dc59855..2e7cf30d 100644 --- a/docs/IPCores/net/arp/arp_UniCast_Responder.rst +++ b/docs/IPCores/net/arp/arp_UniCast_Responder.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_UniCast_Responder.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_UniCast_Responder_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_UniCast_Responder.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_UniCast_Responder_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arp_UniCast_Responder: @@ -29,6 +32,8 @@ arp_UniCast_Responder :linenos: :lines: 42-73 -Source file: :pocsrc:`net/arp/arp_UniCast_Responder.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/arp/arp_UniCast_Responder.vhdl ` diff --git a/docs/IPCores/net/arp/arp_Wrapper.rst b/docs/IPCores/net/arp/arp_Wrapper.rst index 44214616..5c3c1490 100644 --- a/docs/IPCores/net/arp/arp_Wrapper.rst +++ b/docs/IPCores/net/arp/arp_Wrapper.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_Wrapper.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_Wrapper_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_Wrapper.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_Wrapper_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:arp_Wrapper: @@ -29,6 +32,8 @@ arp_Wrapper :linenos: :lines: 44-100 -Source file: :pocsrc:`net/arp/arp_Wrapper.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/arp/arp_Wrapper.vhdl ` diff --git a/docs/IPCores/net/eth/eth_GEMAC_GMII.rst b/docs/IPCores/net/eth/eth_GEMAC_GMII.rst index b0ef49bf..e9818312 100644 --- a/docs/IPCores/net/eth/eth_GEMAC_GMII.rst +++ b/docs/IPCores/net/eth/eth_GEMAC_GMII.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_GEMAC_GMII.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_GEMAC_GMII_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_GEMAC_GMII.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_GEMAC_GMII_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:eth_GEMAC_GMII: @@ -29,6 +32,8 @@ eth_GEMAC_GMII :linenos: :lines: 42-101 -Source file: :pocsrc:`net/eth/eth_GEMAC_GMII.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/eth/eth_GEMAC_GMII.vhdl ` diff --git a/docs/IPCores/net/eth/eth_GEMAC_RX.rst b/docs/IPCores/net/eth/eth_GEMAC_RX.rst index bfba9622..9f2bee35 100644 --- a/docs/IPCores/net/eth/eth_GEMAC_RX.rst +++ b/docs/IPCores/net/eth/eth_GEMAC_RX.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_GEMAC_RX.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_GEMAC_RX_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_GEMAC_RX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_GEMAC_RX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:Eth_GEMAC_RX: @@ -29,6 +32,8 @@ Eth_GEMAC_RX :linenos: :lines: 42-62 -Source file: :pocsrc:`net/eth/eth_GEMAC_RX.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/eth/eth_GEMAC_RX.vhdl ` diff --git a/docs/IPCores/net/eth/eth_GEMAC_TX.rst b/docs/IPCores/net/eth/eth_GEMAC_TX.rst index 5273b154..a49a63c8 100644 --- a/docs/IPCores/net/eth/eth_GEMAC_TX.rst +++ b/docs/IPCores/net/eth/eth_GEMAC_TX.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_GEMAC_TX.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_GEMAC_TX_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_GEMAC_TX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_GEMAC_TX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:Eth_GEMAC_TX: @@ -29,6 +32,8 @@ Eth_GEMAC_TX :linenos: :lines: 42-65 -Source file: :pocsrc:`net/eth/eth_GEMAC_TX.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/eth/eth_GEMAC_TX.vhdl ` diff --git a/docs/IPCores/net/eth/eth_PHYController.rst b/docs/IPCores/net/eth/eth_PHYController.rst index 07e53335..2338483a 100644 --- a/docs/IPCores/net/eth/eth_PHYController.rst +++ b/docs/IPCores/net/eth/eth_PHYController.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_PHYController.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_PHYController_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_PHYController.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_PHYController_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:Eth_PHYController: @@ -29,6 +32,8 @@ Eth_PHYController :linenos: :lines: 45-68 -Source file: :pocsrc:`net/eth/eth_PHYController.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/eth/eth_PHYController.vhdl ` diff --git a/docs/IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst b/docs/IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst index 10a48e8f..45ffe3de 100644 --- a/docs/IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst +++ b/docs/IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_PHYController_Marvell_88E1111.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_PHYController_Marvell_88E1111_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_PHYController_Marvell_88E1111.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_PHYController_Marvell_88E1111_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:Eth_PHYController_Marvell_88E1111: @@ -29,6 +32,8 @@ Eth_PHYController_Marvell_88E1111 :linenos: :lines: 44-71 -Source file: :pocsrc:`net/eth/eth_PHYController_Marvell_88E1111.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/eth/eth_PHYController_Marvell_88E1111.vhdl ` diff --git a/docs/IPCores/net/eth/eth_Wrapper.rst b/docs/IPCores/net/eth/eth_Wrapper.rst index af4644a4..233c03f2 100644 --- a/docs/IPCores/net/eth/eth_Wrapper.rst +++ b/docs/IPCores/net/eth/eth_Wrapper.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_Wrapper.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_Wrapper_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_Wrapper.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_Wrapper_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:Eth_Wrapper: @@ -29,6 +32,8 @@ Eth_Wrapper :linenos: :lines: 68-112 -Source file: :pocsrc:`net/eth/eth_Wrapper.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/eth/eth_Wrapper.vhdl ` diff --git a/docs/IPCores/net/icmpv4/icmpv4_RX.rst b/docs/IPCores/net/icmpv4/icmpv4_RX.rst index f9d08143..7cf26dc4 100644 --- a/docs/IPCores/net/icmpv4/icmpv4_RX.rst +++ b/docs/IPCores/net/icmpv4/icmpv4_RX.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv4/icmpv4_RX.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv4/icmpv4_RX_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv4/icmpv4_RX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv4/icmpv4_RX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:icmpv4_RX: @@ -29,6 +32,8 @@ icmpv4_RX :linenos: :lines: 42-88 -Source file: :pocsrc:`net/icmpv4/icmpv4_RX.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/icmpv4/icmpv4_RX.vhdl ` diff --git a/docs/IPCores/net/icmpv4/icmpv4_TX.rst b/docs/IPCores/net/icmpv4/icmpv4_TX.rst index 893bc63f..4e046d03 100644 --- a/docs/IPCores/net/icmpv4/icmpv4_TX.rst +++ b/docs/IPCores/net/icmpv4/icmpv4_TX.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv4/icmpv4_TX.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv4/icmpv4_TX_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv4/icmpv4_TX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv4/icmpv4_TX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:icmpv4_TX: @@ -29,6 +32,8 @@ icmpv4_TX :linenos: :lines: 42-78 -Source file: :pocsrc:`net/icmpv4/icmpv4_TX.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/icmpv4/icmpv4_TX.vhdl ` diff --git a/docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst b/docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst index 72e1c648..2a493e69 100644 --- a/docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst +++ b/docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv4/icmpv4_Wrapper.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv4/icmpv4_Wrapper_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv4/icmpv4_Wrapper.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv4/icmpv4_Wrapper_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:icmpv4_Wrapper: @@ -29,6 +32,8 @@ icmpv4_Wrapper :linenos: :lines: 42-91 -Source file: :pocsrc:`net/icmpv4/icmpv4_Wrapper.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/icmpv4/icmpv4_Wrapper.vhdl ` diff --git a/docs/IPCores/net/icmpv6/icmpv6_RX.rst b/docs/IPCores/net/icmpv6/icmpv6_RX.rst index 8ea87cea..c6f42734 100644 --- a/docs/IPCores/net/icmpv6/icmpv6_RX.rst +++ b/docs/IPCores/net/icmpv6/icmpv6_RX.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv6/icmpv6_RX.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv6/icmpv6_RX_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv6/icmpv6_RX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv6/icmpv6_RX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:icmpv6_RX: @@ -29,6 +32,8 @@ icmpv6_RX :linenos: :lines: 42-57 -Source file: :pocsrc:`net/icmpv6/icmpv6_RX.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/icmpv6/icmpv6_RX.vhdl ` diff --git a/docs/IPCores/net/icmpv6/icmpv6_TX.rst b/docs/IPCores/net/icmpv6/icmpv6_TX.rst index 50305e8a..58e191fc 100644 --- a/docs/IPCores/net/icmpv6/icmpv6_TX.rst +++ b/docs/IPCores/net/icmpv6/icmpv6_TX.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv6/icmpv6_TX.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv6/icmpv6_TX_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv6/icmpv6_TX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv6/icmpv6_TX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:icmpv6_TX: @@ -29,6 +32,8 @@ icmpv6_TX :linenos: :lines: 42-56 -Source file: :pocsrc:`net/icmpv6/icmpv6_TX.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/icmpv6/icmpv6_TX.vhdl ` diff --git a/docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst b/docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst index 8247e1b2..467bd619 100644 --- a/docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst +++ b/docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv6/icmpv6_Wrapper.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv6/icmpv6_Wrapper_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv6/icmpv6_Wrapper.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv6/icmpv6_Wrapper_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:icmpv6_Wrapper: @@ -29,6 +32,8 @@ icmpv6_Wrapper :linenos: :lines: 42-67 -Source file: :pocsrc:`net/icmpv6/icmpv6_Wrapper.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/icmpv6/icmpv6_Wrapper.vhdl ` diff --git a/docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst b/docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst index 07212aee..9e73d8bc 100644 --- a/docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst +++ b/docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv4/ipv4_FrameLoopback.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv4/ipv4_FrameLoopback_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv4/ipv4_FrameLoopback.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv4/ipv4_FrameLoopback_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:ipv4_FrameLoopback: @@ -29,6 +32,8 @@ ipv4_FrameLoopback :linenos: :lines: 42-74 -Source file: :pocsrc:`net/ipv4/ipv4_FrameLoopback.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/ipv4/ipv4_FrameLoopback.vhdl ` diff --git a/docs/IPCores/net/ipv4/ipv4_RX.rst b/docs/IPCores/net/ipv4/ipv4_RX.rst index 635c8c7e..9f9871cb 100644 --- a/docs/IPCores/net/ipv4/ipv4_RX.rst +++ b/docs/IPCores/net/ipv4/ipv4_RX.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv4/ipv4_RX.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv4/ipv4_RX_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv4/ipv4_RX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv4/ipv4_RX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:ipv4_RX: @@ -29,6 +32,8 @@ ipv4_RX :linenos: :lines: 42-82 -Source file: :pocsrc:`net/ipv4/ipv4_RX.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/ipv4/ipv4_RX.vhdl ` diff --git a/docs/IPCores/net/ipv4/ipv4_TX.rst b/docs/IPCores/net/ipv4/ipv4_TX.rst index 74c27035..4659dd78 100644 --- a/docs/IPCores/net/ipv4/ipv4_TX.rst +++ b/docs/IPCores/net/ipv4/ipv4_TX.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv4/ipv4_TX.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv4/ipv4_TX_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv4/ipv4_TX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv4/ipv4_TX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:ipv4_TX: @@ -29,6 +32,8 @@ ipv4_TX :linenos: :lines: 42-81 -Source file: :pocsrc:`net/ipv4/ipv4_TX.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/ipv4/ipv4_TX.vhdl ` diff --git a/docs/IPCores/net/ipv4/ipv4_Wrapper.rst b/docs/IPCores/net/ipv4/ipv4_Wrapper.rst index 2255d2e0..74144807 100644 --- a/docs/IPCores/net/ipv4/ipv4_Wrapper.rst +++ b/docs/IPCores/net/ipv4/ipv4_Wrapper.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv4/ipv4_Wrapper.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv4/ipv4_Wrapper_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv4/ipv4_Wrapper.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv4/ipv4_Wrapper_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:ipv4_Wrapper: @@ -29,6 +32,8 @@ ipv4_Wrapper :linenos: :lines: 42-112 -Source file: :pocsrc:`net/ipv4/ipv4_Wrapper.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/ipv4/ipv4_Wrapper.vhdl ` diff --git a/docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst b/docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst index 5a0daced..2bb6f0be 100644 --- a/docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst +++ b/docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv6/ipv6_FrameLoopback.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv6/ipv6_FrameLoopback_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv6/ipv6_FrameLoopback.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv6/ipv6_FrameLoopback_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:ipv6_FrameLoopback: @@ -29,6 +32,8 @@ ipv6_FrameLoopback :linenos: :lines: 42-74 -Source file: :pocsrc:`net/ipv6/ipv6_FrameLoopback.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/ipv6/ipv6_FrameLoopback.vhdl ` diff --git a/docs/IPCores/net/ipv6/ipv6_RX.rst b/docs/IPCores/net/ipv6/ipv6_RX.rst index 8a3da845..86f13dfd 100644 --- a/docs/IPCores/net/ipv6/ipv6_RX.rst +++ b/docs/IPCores/net/ipv6/ipv6_RX.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv6/ipv6_RX.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv6/ipv6_RX_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv6/ipv6_RX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv6/ipv6_RX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:ipv6_RX: @@ -29,6 +32,8 @@ ipv6_RX :linenos: :lines: 42-84 -Source file: :pocsrc:`net/ipv6/ipv6_RX.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/ipv6/ipv6_RX.vhdl ` diff --git a/docs/IPCores/net/ipv6/ipv6_TX.rst b/docs/IPCores/net/ipv6/ipv6_TX.rst index 4014f33f..93de91d2 100644 --- a/docs/IPCores/net/ipv6/ipv6_TX.rst +++ b/docs/IPCores/net/ipv6/ipv6_TX.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv6/ipv6_TX.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv6/ipv6_TX_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv6/ipv6_TX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv6/ipv6_TX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:ipv6_TX: @@ -29,6 +32,8 @@ ipv6_TX :linenos: :lines: 42-84 -Source file: :pocsrc:`net/ipv6/ipv6_TX.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/ipv6/ipv6_TX.vhdl ` diff --git a/docs/IPCores/net/ipv6/ipv6_Wrapper.rst b/docs/IPCores/net/ipv6/ipv6_Wrapper.rst index c7ed9000..45d16817 100644 --- a/docs/IPCores/net/ipv6/ipv6_Wrapper.rst +++ b/docs/IPCores/net/ipv6/ipv6_Wrapper.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv6/ipv6_Wrapper.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv6/ipv6_Wrapper_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv6/ipv6_Wrapper.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv6/ipv6_Wrapper_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:ipv6_Wrapper: @@ -29,6 +32,8 @@ ipv6_Wrapper :linenos: :lines: 42-116 -Source file: :pocsrc:`net/ipv6/ipv6_Wrapper.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/ipv6/ipv6_Wrapper.vhdl ` diff --git a/docs/IPCores/net/mac/mac_FrameLoopback.rst b/docs/IPCores/net/mac/mac_FrameLoopback.rst index 5d0c016b..a93c36ab 100644 --- a/docs/IPCores/net/mac/mac_FrameLoopback.rst +++ b/docs/IPCores/net/mac/mac_FrameLoopback.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_FrameLoopback.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_FrameLoopback_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_FrameLoopback.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_FrameLoopback_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:mac_FrameLoopback: @@ -29,6 +32,8 @@ mac_FrameLoopback :linenos: :lines: 42-72 -Source file: :pocsrc:`net/mac/mac_FrameLoopback.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/mac/mac_FrameLoopback.vhdl ` diff --git a/docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst b/docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst index 7af23c2c..fd3aef19 100644 --- a/docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst +++ b/docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_RX_DestMAC_Switch.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_RX_DestMAC_Switch_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_RX_DestMAC_Switch.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_RX_DestMAC_Switch_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:mac_RX_DestMAC_Switch: @@ -29,6 +32,8 @@ mac_RX_DestMAC_Switch :linenos: :lines: 42-67 -Source file: :pocsrc:`net/mac/mac_RX_DestMAC_Switch.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/mac/mac_RX_DestMAC_Switch.vhdl ` diff --git a/docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst b/docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst index ecb00675..ad03c8da 100644 --- a/docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst +++ b/docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_RX_SrcMAC_Filter.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_RX_SrcMAC_Filter_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_RX_SrcMAC_Filter.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_RX_SrcMAC_Filter_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:mac_RX_SrcMAC_Filter: @@ -29,6 +32,8 @@ mac_RX_SrcMAC_Filter :linenos: :lines: 42-72 -Source file: :pocsrc:`net/mac/mac_RX_SrcMAC_Filter.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/mac/mac_RX_SrcMAC_Filter.vhdl ` diff --git a/docs/IPCores/net/mac/mac_RX_Type_Switch.rst b/docs/IPCores/net/mac/mac_RX_Type_Switch.rst index 46417d5d..79208eef 100644 --- a/docs/IPCores/net/mac/mac_RX_Type_Switch.rst +++ b/docs/IPCores/net/mac/mac_RX_Type_Switch.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_RX_Type_Switch.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_RX_Type_Switch_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_RX_Type_Switch.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_RX_Type_Switch_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:mac_RX_Type_Switch: @@ -29,6 +32,8 @@ mac_RX_Type_Switch :linenos: :lines: 42-74 -Source file: :pocsrc:`net/mac/mac_RX_Type_Switch.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/mac/mac_RX_Type_Switch.vhdl ` diff --git a/docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst b/docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst index 905376b9..a25257b3 100644 --- a/docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst +++ b/docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_TX_DestMAC_Prepender.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_TX_DestMAC_Prepender_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_TX_DestMAC_Prepender.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_TX_DestMAC_Prepender_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:mac_TX_DestMAC_Prepender: @@ -29,6 +32,8 @@ mac_TX_DestMAC_Prepender :linenos: :lines: 42-65 -Source file: :pocsrc:`net/mac/mac_TX_DestMAC_Prepender.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/mac/mac_TX_DestMAC_Prepender.vhdl ` diff --git a/docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst b/docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst index 56749127..a81234dc 100644 --- a/docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst +++ b/docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_TX_SrcMAC_Prepender.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_TX_SrcMAC_Prepender_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_TX_SrcMAC_Prepender.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_TX_SrcMAC_Prepender_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:mac_TX_SrcMAC_Prepender: @@ -29,6 +32,8 @@ mac_TX_SrcMAC_Prepender :linenos: :lines: 42-69 -Source file: :pocsrc:`net/mac/mac_TX_SrcMAC_Prepender.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/mac/mac_TX_SrcMAC_Prepender.vhdl ` diff --git a/docs/IPCores/net/mac/mac_TX_Type_Prepender.rst b/docs/IPCores/net/mac/mac_TX_Type_Prepender.rst index 184b7132..dd74a017 100644 --- a/docs/IPCores/net/mac/mac_TX_Type_Prepender.rst +++ b/docs/IPCores/net/mac/mac_TX_Type_Prepender.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_TX_Type_Prepender.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_TX_Type_Prepender_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_TX_Type_Prepender.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_TX_Type_Prepender_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:mac_TX_Type_Prepender: @@ -29,6 +32,8 @@ mac_TX_Type_Prepender :linenos: :lines: 42-69 -Source file: :pocsrc:`net/mac/mac_TX_Type_Prepender.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/mac/mac_TX_Type_Prepender.vhdl ` diff --git a/docs/IPCores/net/mac/mac_Wrapper.rst b/docs/IPCores/net/mac/mac_Wrapper.rst index bf728d43..a6f9bdff 100644 --- a/docs/IPCores/net/mac/mac_Wrapper.rst +++ b/docs/IPCores/net/mac/mac_Wrapper.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_Wrapper.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_Wrapper_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_Wrapper.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_Wrapper_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:mac_Wrapper: @@ -29,6 +32,8 @@ mac_Wrapper :linenos: :lines: 42-84 -Source file: :pocsrc:`net/mac/mac_Wrapper.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/mac/mac_Wrapper.vhdl ` diff --git a/docs/IPCores/net/ndp/ndp_DestinationCache.rst b/docs/IPCores/net/ndp/ndp_DestinationCache.rst index 90721a73..c86e6808 100644 --- a/docs/IPCores/net/ndp/ndp_DestinationCache.rst +++ b/docs/IPCores/net/ndp/ndp_DestinationCache.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ndp/ndp_DestinationCache.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ndp/ndp_DestinationCache_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ndp/ndp_DestinationCache.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ndp/ndp_DestinationCache_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:ndp_DestinationCache: @@ -29,6 +32,8 @@ ndp_DestinationCache :linenos: :lines: 42-65 -Source file: :pocsrc:`net/ndp/ndp_DestinationCache.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/ndp/ndp_DestinationCache.vhdl ` diff --git a/docs/IPCores/net/ndp/ndp_FSMQuery.rst b/docs/IPCores/net/ndp/ndp_FSMQuery.rst index ec3d5aa5..a410c634 100644 --- a/docs/IPCores/net/ndp/ndp_FSMQuery.rst +++ b/docs/IPCores/net/ndp/ndp_FSMQuery.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ndp/ndp_FSMQuery.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ndp/ndp_FSMQuery_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ndp/ndp_FSMQuery.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ndp/ndp_FSMQuery_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:ndp_FSMQuery: @@ -29,6 +32,8 @@ ndp_FSMQuery :linenos: :lines: 42-79 -Source file: :pocsrc:`net/ndp/ndp_FSMQuery.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/ndp/ndp_FSMQuery.vhdl ` diff --git a/docs/IPCores/net/ndp/ndp_NeighborCache.rst b/docs/IPCores/net/ndp/ndp_NeighborCache.rst index 30d792e6..a5b30a5f 100644 --- a/docs/IPCores/net/ndp/ndp_NeighborCache.rst +++ b/docs/IPCores/net/ndp/ndp_NeighborCache.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ndp/ndp_NeighborCache.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ndp/ndp_NeighborCache_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ndp/ndp_NeighborCache.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ndp/ndp_NeighborCache_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:ndp_NeighborCache: @@ -29,6 +32,8 @@ ndp_NeighborCache :linenos: :lines: 42-65 -Source file: :pocsrc:`net/ndp/ndp_NeighborCache.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/ndp/ndp_NeighborCache.vhdl ` diff --git a/docs/IPCores/net/ndp/ndp_Wrapper.rst b/docs/IPCores/net/ndp/ndp_Wrapper.rst index 06ae73fb..52a84c19 100644 --- a/docs/IPCores/net/ndp/ndp_Wrapper.rst +++ b/docs/IPCores/net/ndp/ndp_Wrapper.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ndp/ndp_Wrapper.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ndp/ndp_Wrapper_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ndp/ndp_Wrapper.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ndp/ndp_Wrapper_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:NDP_Wrapper: @@ -29,6 +32,8 @@ NDP_Wrapper :linenos: :lines: 43-65 -Source file: :pocsrc:`net/ndp/ndp_Wrapper.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/ndp/ndp_Wrapper.vhdl ` diff --git a/docs/IPCores/net/net.pkg.rst b/docs/IPCores/net/net.pkg.rst index 5a64d231..5ee24dfd 100644 --- a/docs/IPCores/net/net.pkg.rst +++ b/docs/IPCores/net/net.pkg.rst @@ -1,15 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/net.pkg.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/net.pkg.vhdl + :alt: Source Code on GitHub - |gh-src| :pocsrc:`Sourcecode ` + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` .. _PKG:net: PoC.net Package =============== -Source file: :pocsrc:`net.pkg.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net.pkg.vhdl ` diff --git a/docs/IPCores/net/net_FrameChecksum.rst b/docs/IPCores/net/net_FrameChecksum.rst index f4ceb14f..dc86d61c 100644 --- a/docs/IPCores/net/net_FrameChecksum.rst +++ b/docs/IPCores/net/net_FrameChecksum.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/net_FrameChecksum.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/net_FrameChecksum_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/net_FrameChecksum.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/net_FrameChecksum_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:net_FrameChecksum: @@ -29,6 +32,8 @@ net_FrameChecksum :linenos: :lines: 41-72 -Source file: :pocsrc:`net/net_FrameChecksum.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/net_FrameChecksum.vhdl ` diff --git a/docs/IPCores/net/net_FrameLoopback.rst b/docs/IPCores/net/net_FrameLoopback.rst index c3e4be93..b0a2f58c 100644 --- a/docs/IPCores/net/net_FrameLoopback.rst +++ b/docs/IPCores/net/net_FrameLoopback.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/net_FrameLoopback.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/net_FrameLoopback_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/net_FrameLoopback.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/net_FrameLoopback_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:FrameLoopback: @@ -29,6 +32,8 @@ FrameLoopback :linenos: :lines: 41-65 -Source file: :pocsrc:`net/net_FrameLoopback.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/net_FrameLoopback.vhdl ` diff --git a/docs/IPCores/net/net_FramePerformanceCounter.rst b/docs/IPCores/net/net_FramePerformanceCounter.rst index cbb9f29b..f71798f9 100644 --- a/docs/IPCores/net/net_FramePerformanceCounter.rst +++ b/docs/IPCores/net/net_FramePerformanceCounter.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/net_FramePerformanceCounter.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/net_FramePerformanceCounter_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/net_FramePerformanceCounter.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/net_FramePerformanceCounter_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:LocalLink_PerformanceCounter: @@ -27,6 +30,8 @@ LocalLink_PerformanceCounter :linenos: :lines: 11-35 -Source file: :pocsrc:`net/net_FramePerformanceCounter.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/net_FramePerformanceCounter.vhdl ` diff --git a/docs/IPCores/net/stack/stack_UDPv4.rst b/docs/IPCores/net/stack/stack_UDPv4.rst index afc9b2e8..c343eef6 100644 --- a/docs/IPCores/net/stack/stack_UDPv4.rst +++ b/docs/IPCores/net/stack/stack_UDPv4.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/stack/stack_UDPv4.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/stack/stack_UDPv4_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/stack/stack_UDPv4.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/stack/stack_UDPv4_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:stack_UDPv4: @@ -29,6 +32,8 @@ stack_UDPv4 :linenos: :lines: 44-111 -Source file: :pocsrc:`net/stack/stack_UDPv4.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/stack/stack_UDPv4.vhdl ` diff --git a/docs/IPCores/net/udp/udp_FrameLoopback.rst b/docs/IPCores/net/udp/udp_FrameLoopback.rst index 6cd1292c..fbffcfde 100644 --- a/docs/IPCores/net/udp/udp_FrameLoopback.rst +++ b/docs/IPCores/net/udp/udp_FrameLoopback.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/udp/udp_FrameLoopback.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/udp/udp_FrameLoopback_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/udp/udp_FrameLoopback.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/udp/udp_FrameLoopback_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:udp_FrameLoopback: @@ -29,6 +32,8 @@ udp_FrameLoopback :linenos: :lines: 42-77 -Source file: :pocsrc:`net/udp/udp_FrameLoopback.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/udp/udp_FrameLoopback.vhdl ` diff --git a/docs/IPCores/net/udp/udp_RX.rst b/docs/IPCores/net/udp/udp_RX.rst index e79611ea..fa442a93 100644 --- a/docs/IPCores/net/udp/udp_RX.rst +++ b/docs/IPCores/net/udp/udp_RX.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/udp/udp_RX.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/udp/udp_RX_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/udp/udp_RX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/udp/udp_RX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:udp_RX: @@ -29,6 +32,8 @@ udp_RX :linenos: :lines: 42-95 -Source file: :pocsrc:`net/udp/udp_RX.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/udp/udp_RX.vhdl ` diff --git a/docs/IPCores/net/udp/udp_TX.rst b/docs/IPCores/net/udp/udp_TX.rst index e6745093..e1f42a3e 100644 --- a/docs/IPCores/net/udp/udp_TX.rst +++ b/docs/IPCores/net/udp/udp_TX.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/udp/udp_TX.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/udp/udp_TX_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/udp/udp_TX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/udp/udp_TX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:udp_TX: @@ -29,6 +32,8 @@ udp_TX :linenos: :lines: 42-78 -Source file: :pocsrc:`net/udp/udp_TX.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/udp/udp_TX.vhdl ` diff --git a/docs/IPCores/net/udp/udp_Wrapper.rst b/docs/IPCores/net/udp/udp_Wrapper.rst index 9f375442..f522ed83 100644 --- a/docs/IPCores/net/udp/udp_Wrapper.rst +++ b/docs/IPCores/net/udp/udp_Wrapper.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/udp/udp_Wrapper.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/udp/udp_Wrapper_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/udp/udp_Wrapper.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/udp/udp_Wrapper_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:udp_Wrapper: @@ -29,6 +32,8 @@ udp_Wrapper :linenos: :lines: 42-120 -Source file: :pocsrc:`net/udp/udp_Wrapper.vhdl ` +.. only:: latex + + Source file: :pocsrc:`net/udp/udp_Wrapper.vhdl ` diff --git a/docs/IPCores/sort/sort_ExpireList.rst b/docs/IPCores/sort/sort_ExpireList.rst index c69703b9..06d23708 100644 --- a/docs/IPCores/sort/sort_ExpireList.rst +++ b/docs/IPCores/sort/sort_ExpireList.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sort_ExpireList.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sort_ExpireList_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sort_ExpireList.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sort_ExpireList_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:list_expire: @@ -29,6 +32,8 @@ list_expire :linenos: :lines: 42-61 -Source file: :pocsrc:`sort/sort_ExpireList.vhdl ` +.. only:: latex + + Source file: :pocsrc:`sort/sort_ExpireList.vhdl ` diff --git a/docs/IPCores/sort/sort_InsertSort.rst b/docs/IPCores/sort/sort_InsertSort.rst index 2c77a188..ae1e9db8 100644 --- a/docs/IPCores/sort/sort_InsertSort.rst +++ b/docs/IPCores/sort/sort_InsertSort.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sort_InsertSort.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sort_InsertSort_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sort_InsertSort.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sort_InsertSort_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:list_lru_systolic: @@ -29,6 +32,8 @@ list_lru_systolic :linenos: :lines: 44-64 -Source file: :pocsrc:`sort/sort_InsertSort.vhdl ` +.. only:: latex + + Source file: :pocsrc:`sort/sort_InsertSort.vhdl ` diff --git a/docs/IPCores/sort/sort_LeastFrequentlyUsed.rst b/docs/IPCores/sort/sort_LeastFrequentlyUsed.rst index 58059f94..29dbe53d 100644 --- a/docs/IPCores/sort/sort_LeastFrequentlyUsed.rst +++ b/docs/IPCores/sort/sort_LeastFrequentlyUsed.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sort_LeastFrequentlyUsed.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sort_LeastFrequentlyUsed_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sort_LeastFrequentlyUsed.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sort_LeastFrequentlyUsed_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:sort_LeastFrequentlyUsed: @@ -29,6 +32,8 @@ sort_LeastFrequentlyUsed :linenos: :lines: 36-53 -Source file: :pocsrc:`sort/sort_LeastFrequentlyUsed.vhdl ` +.. only:: latex + + Source file: :pocsrc:`sort/sort_LeastFrequentlyUsed.vhdl ` diff --git a/docs/IPCores/sort/sort_lru_cache.rst b/docs/IPCores/sort/sort_lru_cache.rst index 59feed50..c56bbb1f 100644 --- a/docs/IPCores/sort/sort_lru_cache.rst +++ b/docs/IPCores/sort/sort_lru_cache.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sort_lru_cache.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sort_lru_cache_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sort_lru_cache.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sort_lru_cache_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:sort_lru_cache: @@ -43,6 +46,8 @@ Supported operations: :linenos: :lines: 56-70 -Source file: :pocsrc:`sort/sort_lru_cache.vhdl ` +.. only:: latex + + Source file: :pocsrc:`sort/sort_lru_cache.vhdl ` diff --git a/docs/IPCores/sort/sort_lru_list.rst b/docs/IPCores/sort/sort_lru_list.rst index d595a965..dbc00620 100644 --- a/docs/IPCores/sort/sort_lru_list.rst +++ b/docs/IPCores/sort/sort_lru_list.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sort_lru_list.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sort_lru_list_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sort_lru_list.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sort_lru_list_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:sort_lru_list: @@ -41,6 +44,8 @@ Supported operations: :linenos: :lines: 55-74 -Source file: :pocsrc:`sort/sort_lru_list.vhdl ` +.. only:: latex + + Source file: :pocsrc:`sort/sort_lru_list.vhdl ` diff --git a/docs/IPCores/sort/sortnet/sortnet.pkg.rst b/docs/IPCores/sort/sortnet/sortnet.pkg.rst index a63cffc1..ed9f79f8 100644 --- a/docs/IPCores/sort/sortnet/sortnet.pkg.rst +++ b/docs/IPCores/sort/sortnet/sortnet.pkg.rst @@ -1,11 +1,13 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet.pkg.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet.pkg.vhdl + :alt: Source Code on GitHub - |gh-src| :pocsrc:`Sourcecode ` + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` .. _PKG:sortnet: @@ -32,5 +34,6 @@ PoC.sort.sortnet Package Instantiate a :ref:`IP:sortnet_BitonicSort` sorting network. -Source file: :pocsrc:`sortnet.pkg.vhdl ` +.. only:: latex + Source file: :pocsrc:`sortnet.pkg.vhdl ` diff --git a/docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst b/docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst index 48e2095a..433dd431 100644 --- a/docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst +++ b/docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_BitonicSort.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_BitonicSort.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:sortnet_BitonicSort: @@ -19,7 +22,7 @@ sortnet_BitonicSort This sorting network uses the *bitonic sort* algorithm. -.. image:: ../../../_static/sort/sortnet/sortnet_BitonicSort.svg +.. image:: /_static/sort/sortnet/sortnet_BitonicSort.* :target: ../../../_static/sort/sortnet/sortnet_BitonicSort.svg @@ -32,6 +35,8 @@ This sorting network uses the *bitonic sort* algorithm. :linenos: :lines: 46-72 -Source file: :pocsrc:`sort/sortnet/sortnet_BitonicSort.vhdl ` +.. only:: latex + + Source file: :pocsrc:`sort/sortnet/sortnet_BitonicSort.vhdl ` diff --git a/docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst b/docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst index 1a50a964..089fcd40 100644 --- a/docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst +++ b/docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_MergeSort_Streamed.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_MergeSort_Streamed_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_MergeSort_Streamed.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_MergeSort_Streamed_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:sortnet_MergeSort_Streamed: @@ -29,6 +32,8 @@ sortnet_MergeSort_Streamed :linenos: :lines: 41-68 -Source file: :pocsrc:`sort/sortnet/sortnet_MergeSort_Streamed.vhdl ` +.. only:: latex + + Source file: :pocsrc:`sort/sortnet/sortnet_MergeSort_Streamed.vhdl ` diff --git a/docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst b/docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst index db8e2923..c8e75728 100644 --- a/docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst +++ b/docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_OddEvenMergeSort.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_OddEvenMergeSort.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:sortnet_OddEvenMergeSort: @@ -29,6 +32,8 @@ sortnet_OddEvenMergeSort :linenos: :lines: 43-69 -Source file: :pocsrc:`sort/sortnet/sortnet_OddEvenMergeSort.vhdl ` +.. only:: latex + + Source file: :pocsrc:`sort/sortnet/sortnet_OddEvenMergeSort.vhdl ` diff --git a/docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst b/docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst index 758fd9e3..8ef03011 100644 --- a/docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst +++ b/docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_OddEvenSort.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_OddEvenSort.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:sortnet_OddEvenSort: @@ -29,6 +32,8 @@ sortnet_OddEvenSort :linenos: :lines: 42-68 -Source file: :pocsrc:`sort/sortnet/sortnet_OddEvenSort.vhdl ` +.. only:: latex + + Source file: :pocsrc:`sort/sortnet/sortnet_OddEvenSort.vhdl ` diff --git a/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst index 55d6c869..0eb96718 100644 --- a/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst +++ b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_Stream_Adapter.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_Stream_Adapter_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_Stream_Adapter.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_Stream_Adapter_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:sortnet_Stream_Adapter: @@ -29,6 +32,8 @@ sortnet_Stream_Adapter :linenos: :lines: 42-68 -Source file: :pocsrc:`sort/sortnet/sortnet_Stream_Adapter.vhdl ` +.. only:: latex + + Source file: :pocsrc:`sort/sortnet/sortnet_Stream_Adapter.vhdl ` diff --git a/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst index b81d5f56..cb3dd294 100644 --- a/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst +++ b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_Stream_Adapter2.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_Stream_Adapter2_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_Stream_Adapter2.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_Stream_Adapter2_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:sortnet_Stream_Adapter2: @@ -29,6 +32,8 @@ sortnet_Stream_Adapter2 :linenos: :lines: 42-76 -Source file: :pocsrc:`sort/sortnet/sortnet_Stream_Adapter2.vhdl ` +.. only:: latex + + Source file: :pocsrc:`sort/sortnet/sortnet_Stream_Adapter2.vhdl ` diff --git a/docs/IPCores/sort/sortnet/sortnet_Transform.rst b/docs/IPCores/sort/sortnet/sortnet_Transform.rst index f1d59223..b954a50e 100644 --- a/docs/IPCores/sort/sortnet/sortnet_Transform.rst +++ b/docs/IPCores/sort/sortnet/sortnet_Transform.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_Transform.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_Transform_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_Transform.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_Transform_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:sortnet_Transform: @@ -29,6 +32,8 @@ sortnet_Transform :linenos: :lines: 41-61 -Source file: :pocsrc:`sort/sortnet/sortnet_Transform.vhdl ` +.. only:: latex + + Source file: :pocsrc:`sort/sortnet/sortnet_Transform.vhdl ` diff --git a/docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst b/docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst index 82937980..328b9b7e 100644 --- a/docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst +++ b/docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/reconfig/reconfig_icap_fsm.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/reconfig/reconfig_icap_fsm_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/reconfig/reconfig_icap_fsm.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/reconfig/reconfig_icap_fsm_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:reconfig_icap_fsm: @@ -33,6 +36,8 @@ primitives to generate control signals. Tested on: :linenos: :lines: 42-63 -Source file: :pocsrc:`xil/reconfig/reconfig_icap_fsm.vhdl ` +.. only:: latex + + Source file: :pocsrc:`xil/reconfig/reconfig_icap_fsm.vhdl ` diff --git a/docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst b/docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst index 4caa2e01..e93e4843 100644 --- a/docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst +++ b/docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/reconfig/reconfig_icap_wrapper.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/reconfig/reconfig_icap_wrapper_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/reconfig/reconfig_icap_wrapper.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/reconfig/reconfig_icap_wrapper_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:reconfig_icap_wrapper: @@ -32,6 +35,8 @@ tbd :linenos: :lines: 43-68 -Source file: :pocsrc:`xil/reconfig/reconfig_icap_wrapper.vhdl ` +.. only:: latex + + Source file: :pocsrc:`xil/reconfig/reconfig_icap_wrapper.vhdl ` diff --git a/docs/IPCores/xil/xil.pkg.rst b/docs/IPCores/xil/xil.pkg.rst index 356a78ee..09fd08f4 100644 --- a/docs/IPCores/xil/xil.pkg.rst +++ b/docs/IPCores/xil/xil.pkg.rst @@ -1,11 +1,13 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil.pkg.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil.pkg.vhdl + :alt: Source Code on GitHub - |gh-src| :pocsrc:`Sourcecode ` + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` .. _PKG:xil: @@ -14,4 +16,6 @@ PoC.xil Package This package holds all component declarations for this namespace. -Source file: :pocsrc:`xil.pkg.vhdl ` +.. only:: latex + + Source file: :pocsrc:`xil.pkg.vhdl ` diff --git a/docs/IPCores/xil/xil_BSCAN.rst b/docs/IPCores/xil/xil_BSCAN.rst index ac44d30f..1eb64cc8 100644 --- a/docs/IPCores/xil/xil_BSCAN.rst +++ b/docs/IPCores/xil/xil_BSCAN.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_BSCAN.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_BSCAN_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_BSCAN.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_BSCAN_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:xil_BSCAN: @@ -34,6 +37,8 @@ Supported devices are: :linenos: :lines: 47-65 -Source file: :pocsrc:`xil/xil_BSCAN.vhdl ` +.. only:: latex + + Source file: :pocsrc:`xil/xil_BSCAN.vhdl ` diff --git a/docs/IPCores/xil/xil_ChipScopeICON.rst b/docs/IPCores/xil/xil_ChipScopeICON.rst index 381740a0..d0d9e912 100644 --- a/docs/IPCores/xil/xil_ChipScopeICON.rst +++ b/docs/IPCores/xil/xil_ChipScopeICON.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_ChipScopeICON.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_ChipScopeICON_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_ChipScopeICON.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_ChipScopeICON_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:xil_ChipScopeICON: @@ -42,11 +45,13 @@ the needed source and netlist files on your local machine. :linenos: :lines: 56-63 -Source file: :pocsrc:`xil/xil_ChipScopeICON.vhdl ` - .. seealso:: :doc:`Using PoC -> Synthesis ` For how to run synthesis with PoC and CoreGenerator. + +.. only:: latex + + Source file: :pocsrc:`xil/xil_ChipScopeICON.vhdl ` diff --git a/docs/IPCores/xil/xil_DRP_BusMux.rst b/docs/IPCores/xil/xil_DRP_BusMux.rst index 4c8c39b4..9f0ffa38 100644 --- a/docs/IPCores/xil/xil_DRP_BusMux.rst +++ b/docs/IPCores/xil/xil_DRP_BusMux.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_DRP_BusMux.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_DRP_BusMux_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_DRP_BusMux.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_DRP_BusMux_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:xil_DRP_BusMux: @@ -29,6 +32,8 @@ xil_DRP_BusMux :linenos: :lines: 42-65 -Source file: :pocsrc:`xil/xil_DRP_BusMux.vhdl ` +.. only:: latex + + Source file: :pocsrc:`xil/xil_DRP_BusMux.vhdl ` diff --git a/docs/IPCores/xil/xil_DRP_BusSync.rst b/docs/IPCores/xil/xil_DRP_BusSync.rst index c398d6e1..d405f302 100644 --- a/docs/IPCores/xil/xil_DRP_BusSync.rst +++ b/docs/IPCores/xil/xil_DRP_BusSync.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_DRP_BusSync.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_DRP_BusSync_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_DRP_BusSync.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_DRP_BusSync_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:xil_DRP_BusSync: @@ -29,6 +32,8 @@ xil_DRP_BusSync :linenos: :lines: 40-58 -Source file: :pocsrc:`xil/xil_DRP_BusSync.vhdl ` +.. only:: latex + + Source file: :pocsrc:`xil/xil_DRP_BusSync.vhdl ` diff --git a/docs/IPCores/xil/xil_ICAP.rst b/docs/IPCores/xil/xil_ICAP.rst index ab2b8468..2df83a46 100644 --- a/docs/IPCores/xil/xil_ICAP.rst +++ b/docs/IPCores/xil/xil_ICAP.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_ICAP.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_ICAP_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_ICAP.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_ICAP_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:xil_ICAP: @@ -34,6 +37,8 @@ Supported devices are: :linenos: :lines: 47-66 -Source file: :pocsrc:`xil/xil_ICAP.vhdl ` +.. only:: latex + + Source file: :pocsrc:`xil/xil_ICAP.vhdl ` diff --git a/docs/IPCores/xil/xil_Reconfigurator.rst b/docs/IPCores/xil/xil_Reconfigurator.rst index 1efa9174..3d994dae 100644 --- a/docs/IPCores/xil/xil_Reconfigurator.rst +++ b/docs/IPCores/xil/xil_Reconfigurator.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_Reconfigurator.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_Reconfigurator_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_Reconfigurator.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_Reconfigurator_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:xil_Reconfigurator: @@ -37,6 +40,8 @@ completes with another strobe on ``ReconfigDone``. :linenos: :lines: 51-72 -Source file: :pocsrc:`xil/xil_Reconfigurator.vhdl ` +.. only:: latex + + Source file: :pocsrc:`xil/xil_Reconfigurator.vhdl ` diff --git a/docs/IPCores/xil/xil_SystemMonitor.rst b/docs/IPCores/xil/xil_SystemMonitor.rst index 5fb4952a..28781e9a 100644 --- a/docs/IPCores/xil/xil_SystemMonitor.rst +++ b/docs/IPCores/xil/xil_SystemMonitor.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_SystemMonitor.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_SystemMonitor_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_SystemMonitor.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_SystemMonitor_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:xil_SystemMonitor: @@ -47,6 +50,8 @@ monitors (normal, user temperature, over temperature). :linenos: :lines: 62-73 -Source file: :pocsrc:`xil/xil_SystemMonitor.vhdl ` +.. only:: latex + + Source file: :pocsrc:`xil/xil_SystemMonitor.vhdl ` diff --git a/docs/IPCores/xil/xil_SystemMonitor_Series7.rst b/docs/IPCores/xil/xil_SystemMonitor_Series7.rst index 4c1c1f32..4c19aa6f 100644 --- a/docs/IPCores/xil/xil_SystemMonitor_Series7.rst +++ b/docs/IPCores/xil/xil_SystemMonitor_Series7.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_SystemMonitor_Series7.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_SystemMonitor_Series7_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_SystemMonitor_Series7.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_SystemMonitor_Series7_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:xil_SystemMonitor_Series7: @@ -46,6 +49,8 @@ are overrun. The XADC was formerly known as "System Monitor". :linenos: :lines: 56-66 -Source file: :pocsrc:`xil/xil_SystemMonitor_Series7.vhdl ` +.. only:: latex + + Source file: :pocsrc:`xil/xil_SystemMonitor_Series7.vhdl ` diff --git a/docs/IPCores/xil/xil_SystemMonitor_Virtex6.rst b/docs/IPCores/xil/xil_SystemMonitor_Virtex6.rst index ec135982..86eae81b 100644 --- a/docs/IPCores/xil/xil_SystemMonitor_Virtex6.rst +++ b/docs/IPCores/xil/xil_SystemMonitor_Virtex6.rst @@ -1,16 +1,19 @@ -.. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_SystemMonitor_Virtex6.vhdl - :alt: Source Code on GitHub -.. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png - :scale: 40 - :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_SystemMonitor_Virtex6_tb.vhdl - :alt: Source Code on GitHub +.. only:: html -.. sidebar:: GitHub Links + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_SystemMonitor_Virtex6.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_SystemMonitor_Virtex6_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` - * |gh-src| :pocsrc:`Sourcecode ` - * |gh-tb| :poctb:`Testbench ` .. _IP:xil_SystemMonitor_Virtex6: @@ -46,6 +49,8 @@ temperature values are overrun. :linenos: :lines: 56-66 -Source file: :pocsrc:`xil/xil_SystemMonitor_Virtex6.vhdl ` +.. only:: latex + + Source file: :pocsrc:`xil/xil_SystemMonitor_Virtex6.vhdl ` diff --git a/docs/conf.py b/docs/conf.py index a90739dd..fcc3c817 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -246,7 +246,7 @@ def _LatestTagName(latestTagHash): #html_use_index = True # If true, the index is split into individual pages for each letter. -#html_split_index = False +# html_split_index = True # If true, links to the reST sources are added to the pages. #html_show_sourcelink = True @@ -313,7 +313,7 @@ def _LatestTagName(latestTagHash): # For "manual" documents, if this is true, then toplevel headings are parts, # not chapters. -#latex_use_parts = False +latex_use_parts = True # If true, show page references after internal links. #latex_show_pagerefs = False diff --git a/docs/index.rst b/docs/index.rst index 49263291..4b45392e 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -3,33 +3,41 @@ and Architecture** - Faculty of Computer Science, Technische Universität Dresde Germany |br| `https://tu-dresden.de/ing/informatik/ti/vlsi `_ -.. image:: /_static/logos/tu-dresden.jpg - :scale: 10 - :alt: Technische Universität Dresden - --------------------------------------------------------------------------------- - -.. image:: /_static/logos/GitHub-Mark-32px.png - :scale: 60 - :target: https://www.github.com/VLSI-EDA/PoC - :alt: Source Code on GitHub -.. image:: https://landscape.io/github/VLSI-EDA/PoC/release/landscape.svg?style=flat - :target: https://landscape.io/github/VLSI-EDA/PoC/release - :alt: Code Health -.. image:: https://travis-ci.org/VLSI-EDA/PoC.svg?branch=release - :target: https://travis-ci.org/VLSI-EDA/PoC - :alt: Build Results -.. image:: https://badges.gitter.im/VLSI-EDA/PoC.svg - :target: https://gitter.im/VLSI-EDA/PoC - :alt: Join -.. image:: https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat - :alt: Latest tag -.. image:: https://img.shields.io/github/release/VLSI-EDA/PoC.svg?style=flat - :target: https://github.com/VLSI-EDA/PoC/releases - :alt: Latest release -.. image:: https://img.shields.io/github/license/VLSI-EDA/PoC.svg?style=flat - :target: References/Licenses/License.html - :alt: Apache License 2.0 +.. only:: html + + .. image:: /_static/logos/tu-dresden.jpg + :scale: 10 + :alt: Technische Universität Dresden + +.. only:: latex + + .. image:: /_static/logos/tu-dresden.jpg + :scale: 80 + :alt: Technische Universität Dresden + +.. only:: html + + .. image:: /_static/logos/GitHub-Mark-32px.png + :scale: 60 + :target: https://www.github.com/VLSI-EDA/PoC + :alt: Source Code on GitHub + .. image:: https://landscape.io/github/VLSI-EDA/PoC/release/landscape.svg?style=flat + :target: https://landscape.io/github/VLSI-EDA/PoC/release + :alt: Code Health + .. image:: https://travis-ci.org/VLSI-EDA/PoC.svg?branch=release + :target: https://travis-ci.org/VLSI-EDA/PoC + :alt: Build Results + .. image:: https://badges.gitter.im/VLSI-EDA/PoC.svg + :target: https://gitter.im/VLSI-EDA/PoC + :alt: Join + .. image:: https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat + :alt: Latest tag + .. image:: https://img.shields.io/github/release/VLSI-EDA/PoC.svg?style=flat + :target: https://github.com/VLSI-EDA/PoC/releases + :alt: Latest release + .. image:: https://img.shields.io/github/license/VLSI-EDA/PoC.svg?style=flat + :target: References/Licenses/License.html + :alt: Apache License 2.0 -------------------------------------------------------------------------------- @@ -52,11 +60,17 @@ PoC. To generalize all supported free and commercial vendor tool chains, PoC is shipped with a Python based infrastructure to offer a command line based frontend. -News -**** +.. only:: html + + News + **** + + 13.05.2016 - PoC 1.0.0 was released. + ==================================== + +.. only:: latex -13.05.2016 - PoC 1.0.0 was released. -==================================== + .. rubric:: 13.05.2016 - PoC 1.0.0 was released. Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor @@ -64,8 +78,14 @@ sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet -Cite the PoC-Library -******************** +.. only:: html + + Cite the PoC-Library + ******************** + +.. only:: latex + + .. rubric:: Cite the PoC-Library The PoC-Library hosted at `GitHub.com `_. Please use the following `biblatex `_ entry to cite us: @@ -86,7 +106,10 @@ following `biblatex `_ entry to cite us: .. |docdate| date:: %b %d, %Y - %H:%M -This document was generated on |docdate|. +.. only:: html + + This document was generated on |docdate|. + .. toctree:: :caption: Introduction diff --git a/src/io/ddrio/ddrio_in.vhdl b/src/io/ddrio/ddrio_in.vhdl index acc228f4..e2fed10d 100644 --- a/src/io/ddrio/ddrio_in.vhdl +++ b/src/io/ddrio/ddrio_in.vhdl @@ -21,25 +21,29 @@ -- -- { signal: [ -- {name: 'clk', wave: 'H.L.H.L.H.L.H.L.H'}, --- {name: 'pad', wave: 'x2.3.4.5.2.3.x...', data: ['0', '1', '2', '3', '4', '5'], node: '..a.b.c.d.e.f..'}, --- ['DataIn', --- {name: 'DataIn_low', wave: 'x...2...4...2...x', data: ['0', '2', '4'], node: '.....k...m...o.'}, --- {name: 'DataIn_high', wave: 'x...3...5...3...x', data: ['1', '3', '5'], node: '.....l...n...p.'}, --- ], +-- {name: 'pad', wave: 'x2.3.4.5.2.3.x...', data: ['0', '1', '2', '3', '4', '5'], node: '.a.b.c.d.e.f...'}, +-- {name: 'DataIn_low', wave: 'x...2...4...2...x', data: ['0', '2', '4'], node: '....k...m...o..'}, +-- {name: 'DataIn_high', wave: 'x...3...5...3...x', data: ['1', '3', '5'], node: '....l...n...p..'} -- ], --- edge: ['a~k', 'b~l', 'c~m', 'd~n', 'e~o', 'f~p'], --- foot: {text: 'PoC.io.ddrio.in'} +-- edge: ['a|->k', 'b|->l', 'c|->m', 'd|->n', 'e|->o', 'f|->p'], +-- foot: { +-- text: ['tspan', +-- ['tspan', {'font-weight': 'bold'}, 'PoC.io.ddrio.in'], +-- ' -- DDR Data Input sampled from pad.' +-- ] +-- } -- } -- --- .. code-block:: none +-- .. only:: latex -- --- __ ____ ____ __ --- Clock |____| |____| |____| --- Pad < 0 >< 1 >< 2 >< 3 >< 4 >< 5 > --- DataIn_low ... >< 0 >< 2 >< --- DataIn_high ... >< 1 >< 3 >< +-- .. code-block:: none +-- __ ____ ____ __ +-- Clock |____| |____| |____| +-- Pad < 0 >< 1 >< 2 >< 3 >< 4 >< 5 > +-- DataIn_low ... >< 0 >< 2 >< +-- DataIn_high ... >< 1 >< 3 >< -- --- < i > is the value of the i-th data bit on the line. +-- < i > is the value of the i-th data bit on the line. -- -- After power-up, the output ports ``DataIn_high`` and ``DataIn_low`` both equal -- INIT_VALUE. diff --git a/src/misc/sync/sync_Strobe.vhdl b/src/misc/sync/sync_Strobe.vhdl index cdf9427c..c6b90aea 100644 --- a/src/misc/sync/sync_Strobe.vhdl +++ b/src/misc/sync/sync_Strobe.vhdl @@ -19,7 +19,7 @@ -- .. ATTENTION:: -- Use this synchronizer only for one-cycle high-active signals (strobes). -- --- .. image:: ../../../_static/misc/sync/sync_Strobe.svg +-- .. image:: /_static/misc/sync/sync_Strobe.* -- :target: ../../../_static/misc/sync/sync_Strobe.svg -- -- Constraints: diff --git a/src/sort/sortnet/sortnet_BitonicSort.vhdl b/src/sort/sortnet/sortnet_BitonicSort.vhdl index 1f945434..49e0dd90 100644 --- a/src/sort/sortnet/sortnet_BitonicSort.vhdl +++ b/src/sort/sortnet/sortnet_BitonicSort.vhdl @@ -10,7 +10,7 @@ -- ------------------------------------- -- This sorting network uses the *bitonic sort* algorithm. -- --- .. image:: ../../../_static/sort/sortnet/sortnet_BitonicSort.svg +-- .. image:: /_static/sort/sortnet/sortnet_BitonicSort.* -- :target: ../../../_static/sort/sortnet/sortnet_BitonicSort.svg -- -- License: diff --git a/tools/ReadTheDocs/requirements.txt b/tools/ReadTheDocs/requirements.txt index c69a1670..66263f6c 100644 --- a/tools/ReadTheDocs/requirements.txt +++ b/tools/ReadTheDocs/requirements.txt @@ -3,7 +3,7 @@ sphinx>=1.4.8 sphinxcontrib-autoprogram>=0.1.3 #sphinxcontrib-actdiag>=0.8.5 #sphinxcontrib-seqdiag>=0.8.5 -sphinxcontrib-wavedrom>=1.2.0 +sphinxcontrib-wavedrom>=1.3.0 # sphinxcontrib-textstyle>=0.2.1 # sphinxcontrib-spelling>=2.2.0 autoapi From 4a2d43912a89152a777164d29a07a747763d6a20 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 22 Nov 2016 11:21:58 +0100 Subject: [PATCH 56/97] Improved PDF documentation layout. --- docs/conf.py | 2 +- docs/index.rst | 25 ++++++++++++++++++++++++- 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/docs/conf.py b/docs/conf.py index fcc3c817..731c3baa 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -313,7 +313,7 @@ def _LatestTagName(latestTagHash): # For "manual" documents, if this is true, then toplevel headings are parts, # not chapters. -latex_use_parts = True +# latex_use_parts = True # If true, show page references after internal links. #latex_show_pagerefs = False diff --git a/docs/index.rst b/docs/index.rst index 4b45392e..ebaf168c 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -1,3 +1,7 @@ +.. raw:: latex + + \part{Introduction} + This library is published and maintained by **Chair for VLSI Design, Diagnostics and Architecture** - Faculty of Computer Science, Technische Universität Dresden, Germany |br| @@ -15,6 +19,8 @@ Germany |br| :scale: 80 :alt: Technische Universität Dresden +-------------------------------------------------------------------------------- + .. only:: html .. image:: /_static/logos/GitHub-Mark-32px.png @@ -39,7 +45,8 @@ Germany |br| :target: References/Licenses/License.html :alt: Apache License 2.0 --------------------------------------------------------------------------------- + ----------------------------------------------------------------------------- + The PoC-Library Documentation ############################# @@ -120,6 +127,10 @@ following `biblatex `_ entry to cite us: GetInvolved/index References/Licenses/License +.. raw:: latex + + \part{Main Documentation} + .. toctree:: :caption: Main Documentation :hidden: @@ -130,6 +141,10 @@ following `biblatex `_ entry to cite us: Miscelaneous/ThirdParty ConstraintFiles/index +.. raw:: latex + + \part{References} + .. toctree:: :caption: References :hidden: @@ -139,6 +154,10 @@ following `biblatex `_ entry to cite us: PyInfrastructure/index More ... +.. raw:: latex + + \part{Appendix} + .. toctree:: :caption: Appendix :hidden: @@ -148,6 +167,10 @@ following `biblatex `_ entry to cite us: .. ifconfig:: visibility in ('PoCInternal') + .. raw:: latex + + \part{Main Internal} + .. toctree:: :caption: Internal :hidden: From cf8c6d49fe1650d9fef0635fe9898e8e577c1600 Mon Sep 17 00:00:00 2001 From: Martin Zabel Date: Tue, 22 Nov 2016 13:44:49 +0100 Subject: [PATCH 57/97] New IPCore PoC.mem.ocram.sdp_wf --- docs/ChangeLog/2016/v1.x.rst | 33 ++- docs/ChangeLog/template.rst | 2 + docs/IPCores/mem/ocram/index.rst | 9 +- docs/IPCores/mem/ocram/ocram_sdp_wf.rst | 47 ++++ py/config.entity.ini | 13 ++ py/config.structure.ini | 1 + src/mem/ocram/ocram_sdp_wf.files | 12 + src/mem/ocram/ocram_sdp_wf.vhdl | 165 +++++++++++++ tb/mem/ocram/ocram_sdp_wf_tb.files | 11 + tb/mem/ocram/ocram_sdp_wf_tb.vhdl | 298 ++++++++++++++++++++++++ 10 files changed, 589 insertions(+), 2 deletions(-) create mode 100644 docs/IPCores/mem/ocram/ocram_sdp_wf.rst create mode 100644 src/mem/ocram/ocram_sdp_wf.files create mode 100644 src/mem/ocram/ocram_sdp_wf.vhdl create mode 100644 tb/mem/ocram/ocram_sdp_wf_tb.files create mode 100644 tb/mem/ocram/ocram_sdp_wf_tb.vhdl diff --git a/docs/ChangeLog/2016/v1.x.rst b/docs/ChangeLog/2016/v1.x.rst index ef8e8a20..1fdd0ec2 100644 --- a/docs/ChangeLog/2016/v1.x.rst +++ b/docs/ChangeLog/2016/v1.x.rst @@ -1,6 +1,37 @@ .. _CHANGE:v1.x: -New in 1.x (upcomming) +New in 1.x (upcoming) ======================= Already documented changes are available on the ``release`` branch at GitHub. + +* Python Infrastructure + + * Common changes + * All Simulators + * Aldec Active-HDL + * GHDL + * Mentor QuestaSim + * Xilinx ISE Simulator + * Xilinx Vivado Simulator + * All Compilers + * Altera Quartus Synthesis + * Lattice Diamond (LSE) + * Xilinx ISE (XST) + * Xilinx ISE Core Generator + * Xilinx Vivado Synthesis + +* Documentation +* VHDL common packages +* VHDL Simulation helpers + +* New Entities + + * :ref:`IP:ocram_sdp_wf` + +* New Testbenches + + * Testbench for :ref:`IP:ocram_sdp_wf` + +* New Constraints +* Shipped Tool and Helper Scripts diff --git a/docs/ChangeLog/template.rst b/docs/ChangeLog/template.rst index d658b010..2a68e93b 100644 --- a/docs/ChangeLog/template.rst +++ b/docs/ChangeLog/template.rst @@ -8,6 +8,7 @@ New in 1.x (upcomming) Already documented changes are available on the ``release`` branch at GitHub. * Python Infrastructure + * Common changes * All Simulators * Aldec Active-HDL @@ -21,6 +22,7 @@ Already documented changes are available on the ``release`` branch at GitHub. * Xilinx ISE (XST) * Xilinx ISE Core Generator * Xilinx Vivado Synthesis + * Documentation * VHDL common packages * VHDL Simulation helpers diff --git a/docs/IPCores/mem/ocram/index.rst b/docs/IPCores/mem/ocram/index.rst index dc07fbe9..567b47ae 100644 --- a/docs/IPCores/mem/ocram/index.rst +++ b/docs/IPCores/mem/ocram/index.rst @@ -19,6 +19,8 @@ The package PoC.mem.ocram holds all component declarations for this namespace. * :ref:`IP:ocram_sp` - An on-chip RAM with a single port interface. * :ref:`IP:ocram_sdp` - An on-chip RAM with a simple dual port interface. + * :ref:`IP:ocram_sdp_wf` - An on-chip RAM with a simple dual port + interface and write-first behavior. * :ref:`IP:ocram_tdp` - An on-chip RAM with a true dual port interface. **Deprecated Entities** @@ -35,6 +37,11 @@ The package PoC.mem.ocram holds all component declarations for this namespace. :hidden: ocram_sp - ocram_esdp ocram_sdp + ocram_sdp_wf ocram_tdp + +.. toctree:: + :hidden: + + ocram_esdp diff --git a/docs/IPCores/mem/ocram/ocram_sdp_wf.rst b/docs/IPCores/mem/ocram/ocram_sdp_wf.rst new file mode 100644 index 00000000..4843b95e --- /dev/null +++ b/docs/IPCores/mem/ocram/ocram_sdp_wf.rst @@ -0,0 +1,47 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram_sdp_wf.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocram/ocram_sdp_wf_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + + +.. _IP:ocram_sdp_wf: + +ocram_sdp_wf +############ + +Inferring / instantiating simple dual-port memory, with: + +* single clock, clock enable, +* 1 read port plus 1 write port. + +Mixed-Port Read-During-Write + When reading at the write address, the read value will be the new data, + aka. "write-first behavior". Of course, the read is still synchronous, + i.e, the latency is still one clock cyle. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/ocram/ocram_sdp_wf.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-58 + + + +.. only:: latex + + Source file: :pocsrc:`mem/ocram/ocram_sdp_wf.vhdl ` diff --git a/py/config.entity.ini b/py/config.entity.ini index b2071912..776f8721 100644 --- a/py/config.entity.ini +++ b/py/config.entity.ini @@ -433,6 +433,19 @@ HDLParameters = A_BITS=12; D_BITS=16 [XST.mem.ocram.sdp.nl3] [VIVADO.mem.ocram.sdp.nl4] +[IP.mem.ocram.sdp_wf] +tb = VHDLTestbench +nl1 = LSENetlist +nl2 = QuartusNetlist +nl3 = XSTNetlist +nl4 = VivadoNetlist +HDLParameters = A_BITS=12; D_BITS=16 +[TB.mem.ocram.sdp_wf.tb] +[LSE.mem.ocram.sdp_wf.nl1] +[QMAP.mem.ocram.sdp_wf.nl2] +[XST.mem.ocram.sdp_wf.nl3] +[VIVADO.mem.ocram.sdp_wf.nl4] + [IP.mem.ocram.sp] tb = VHDLTestbench nl1 = LSENetlist diff --git a/py/config.structure.ini b/py/config.structure.ini index 48cef497..c37b0920 100644 --- a/py/config.structure.ini +++ b/py/config.structure.ini @@ -212,6 +212,7 @@ Sine = Entity [PoC.mem.ocram] esdp = Entity sdp = Entity +sdp_wf = Entity sp = Entity tdp = Entity diff --git a/src/mem/ocram/ocram_sdp_wf.files b/src/mem/ocram/ocram_sdp_wf.files new file mode 100644 index 00000000..06b94eb3 --- /dev/null +++ b/src/mem/ocram/ocram_sdp_wf.files @@ -0,0 +1,12 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# ============================================================================== +# Note: all files are relative to PoC root directory +# +# Common PoC packages for configuration, synthesis and simulation +include "src/common/common.files" + +# PoC.mem.ocram +include "src/mem/ocram/ocram_sdp.files" +vhdl poc "src/mem/ocram/ocram_sdp_wf.vhdl" diff --git a/src/mem/ocram/ocram_sdp_wf.vhdl b/src/mem/ocram/ocram_sdp_wf.vhdl new file mode 100644 index 00000000..c5bce72d --- /dev/null +++ b/src/mem/ocram/ocram_sdp_wf.vhdl @@ -0,0 +1,165 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Martin Zabel +-- +-- Entity: Simple dual-port memory with write-first behavior. +-- +-- Description: +-- ------------------------------------- +-- Inferring / instantiating simple dual-port memory, with: +-- +-- * single clock, clock enable, +-- * 1 read port plus 1 write port. +-- +-- Mixed-Port Read-During-Write +-- When reading at the write address, the read value will be the new data, +-- aka. "write-first behavior". Of course, the read is still synchronous, +-- i.e, the latency is still one clock cyle. +-- +-- License: +-- ============================================================================= +-- Copyright 2008-2015 Technische Universitaet Dresden - Germany +-- Chair of VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ocram_sdp_wf is + generic ( + A_BITS : positive; -- number of address bits + D_BITS : positive; -- number of data bits + FILENAME : string := "" -- file-name for RAM initialization + ); + port ( + clk : in std_logic; -- clock + ce : in std_logic; -- clock-enable + we : in std_logic; -- write enable + ra : in unsigned(A_BITS-1 downto 0); -- read address + wa : in unsigned(A_BITS-1 downto 0); -- write address + d : in std_logic_vector(D_BITS-1 downto 0); -- data in + q : out std_logic_vector(D_BITS-1 downto 0) -- data out + ); +end entity; + + +architecture rtl of ocram_sdp_wf is + -- Implementation Notes: + -- --------------------- + -- + -- I have also checked a modified version of the unit `ocram_sp` with just a + -- single clock and an asynchronous read like:: + -- + -- process(clk) + -- begin + -- if rising_edge(clk) then + -- if ce = '1' then + -- ra_r <= ra; + -- end if; + -- end if; + -- end process; + -- + -- q <= ram(to_integer(ra_r)); + -- + -- But the result from various FPGA synthesis tools was as follows: + -- + -- * Altera Quartus 13.0: adds proper bypass-logic as expected. + -- + -- * Lattice Synthesis Engine: adds proper bypass-logic, but there was an + -- unneccessary multiplexer for the read address to mimic the read enable. + -- + -- * XST 14.7: RAM is mapped to Block-RAM which has not the desired + -- read-during-write behavior and also no bypass logic is added. XST adds + -- also an unneccessary multiplexer for the read address to mimic the read + -- enable. + -- + -- Enforcing distributed RAM gives the desired behavior when synthesizing + -- just this unit. But synthesis has failed in complex projects when + -- KEEP_HIERARCHY was set to NO. + -- + -- * Vivado 2016.2: RAM is mapped to Block-RAM which has not the desired + -- read-during-write behavior and also no bypass logic is added. Vivado + -- adds also an unneccessary multiplexer for the read address to mimic the + -- read enable. + -- + -- Enforcing distributed RAM gives the desired behavior when synthesizing + -- just this unit. Synthesis results have not yet been checked for larger + -- designs. + -- + -- Thus, the solution below is to explictly implement the bypass logic. + + + signal wd_r : std_logic_vector(d'range); -- write data + signal fwd_r : std_logic; -- forward write data + signal ram_q : std_logic_vector(q'range); -- RAM output + + -- Compares two addresses, returns 'X' if either ``a1`` or ``a2`` contains + -- meta-values, otherwise returns '1' if ``a1 == a2`` is true else + -- '0'. Returns 'X' even when the addresses contain '-' values, to signal an + -- undefined outcome. + function addr_equal(a1 : unsigned; a2 : unsigned) return X01 is + begin + -- synthesis translate_off + if is_x(a1) or is_x(a2) then return 'X'; end if; + -- synthesis translate_on + if to_x01(std_logic_vector(a1)) = to_x01(std_logic_vector(a2)) then + return '1'; + end if; + return '0'; + end function; + +begin + process(clk) + begin + if rising_edge(clk) then + case to_x01(ce) is + when '1' => + wd_r <= to_x01(d); + fwd_r <= addr_equal(ra, wa) and we; + + when '0' => null; -- keep previous state + + when others => -- X propagation in simulation + wd_r <= (others => 'X'); + fwd_r <= 'X'; + end case; + end if; + end process; + + ram_sdp: entity work.ocram_sdp + generic map ( + A_BITS => A_BITS, + D_BITS => D_BITS, + FILENAME => FILENAME) + port map ( + rclk => clk, + rce => ce, + wclk => clk, + wce => ce, + we => we, + ra => ra, + wa => wa, + d => d, + q => ram_q); + + with fwd_r select q <= + wd_r when '1', + ram_q when '0', + (others => 'X') when others; -- X propagation in simulation + +end architecture; diff --git a/tb/mem/ocram/ocram_sdp_wf_tb.files b/tb/mem/ocram/ocram_sdp_wf_tb.files new file mode 100644 index 00000000..9e04ce11 --- /dev/null +++ b/tb/mem/ocram/ocram_sdp_wf_tb.files @@ -0,0 +1,11 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# ============================================================================== +# Note: all files are relative to PoC root directory +# +# PoC.mem.ocram +include "src/mem/ocram/ocram_sdp_wf.files" # Unit Under Test + +# Testbench files +vhdl test "tb/mem/ocram/ocram_sdp_wf_tb.vhdl" # Testbench diff --git a/tb/mem/ocram/ocram_sdp_wf_tb.vhdl b/tb/mem/ocram/ocram_sdp_wf_tb.vhdl new file mode 100644 index 00000000..88f0aa63 --- /dev/null +++ b/tb/mem/ocram/ocram_sdp_wf_tb.vhdl @@ -0,0 +1,298 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Authors: Martin Zabel +-- +-- Testbench: On-Chip-RAM: Simple-Dual-Port (SDP) with write-first. +-- +-- Description: +-- ------------------------------------ +-- Automated testbench for PoC.mem.ocram.sdp_wf +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library PoC; +use PoC.utils.all; +use PoC.physical.all; +-- simulation only packages +use PoC.sim_types.all; +use PoC.simulation.all; +use PoC.waveform.all; + + +entity ocram_sdp_wf_tb is +end entity; + +architecture tb of ocram_sdp_wf_tb is + constant CLOCK_FREQ : FREQ := 100 MHz; + + -- component generics + -- Set to values used for synthesis when simulating a netlist. + constant A_BITS : positive := 8; + constant D_BITS : positive := 16; + + -- component ports + signal clk : std_logic; + signal ce : std_logic; + signal we1 : std_logic; + signal a1 : unsigned(A_BITS-1 downto 0); + signal a2 : unsigned(A_BITS-1 downto 0); + signal d1 : std_logic_vector(D_BITS-1 downto 0); + signal q2 : std_logic_vector(D_BITS-1 downto 0); + + -- Expected read data, assign together with read command + -- Set to '-'es when result doesn't care. + -- Set to 'X'es when expecting unknown result due to mixed-port collision. + signal rd_d2 : std_logic_vector(D_BITS-1 downto 0); + + -- Derived expected output on q2. + signal exp_q2 : std_logic_vector(D_BITS-1 downto 0) := (others => '-'); + + -- Signaling between Stimuli and Checker process + signal finished1 : boolean := false; + signal finished2 : boolean := false; +begin + -- initialize global simulation status + simInitialize; + + -- generate global testbench clock + simGenerateClock(clk, CLOCK_FREQ); + + -- component instantiation + UUT: entity poc.ocram_sdp_wf + generic map ( + A_BITS => A_BITS, + D_BITS => D_BITS, + FILENAME => "") + port map ( + clk => clk, + ce => ce, + we => we1, + wa => a1, + ra => a2, + d => d1, + q => q2); + + -- NOTE: Clock enable is controlled by Stimuli1. It must be '1' for all + -- test pattern which do not read and write at the same time. + + -- Input stimuli for Port 1 (Write) + -- =========================================================================== + Stimuli1: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Stimuli1"); + begin + -- No operation on first rising clock edge + ce <= '0'; + we1 <= '-'; + a1 <= (others => '-'); + d1 <= (others => '-'); + + -- Write in 8 consecutive clock cycles on port 1, read one cycle later on + -- port 2 + ------------------------------------------------------------------------- + for i in 0 to 7 loop + simWaitUntilRisingEdge(clk, 1); + ce <= '1'; + we1 <= '1'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + simWaitUntilRisingEdge(clk, 1); + -- last read on port 2 here + ce <= '1'; + we1 <= '0'; + a1 <= (others => '-'); + d1 <= (others => '-'); + + -- Alternating write on port 1 / read on port 2 + ------------------------------------------------------------------------- + for i in 8 to 15 loop + simWaitUntilRisingEdge(clk, 1); + ce <= '1'; + we1 <= '1'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + simWaitUntilRisingEdge(clk, 1); + -- last read on port 2 here + ce <= '1'; + we1 <= '0'; + a1 <= (others => '-'); + d1 <= (others => '-'); + + -- Read in 8 consecutive clock cycles on port 2, write one cycle later on + -- port 1 + ------------------------------------------------------------------------- + simWaitUntilRisingEdge(clk, 1); + -- first read on port 2 here + ce <= '1'; + we1 <= '0'; + a1 <= (others => '-'); + d1 <= (others => '-'); + + for i in 16 to 23 loop + simWaitUntilRisingEdge(clk, 1); + ce <= '1'; + we1 <= '1'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + -- Read and write in 8 consecutive clock cycles at the same time + ------------------------------------------------------------------------- + for i in 24 to 31 loop + simWaitUntilRisingEdge(clk, 1); + ce <= '1'; + we1 <= '1'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + -- Read and write 8 times at the same time every second clock cycle + ------------------------------------------------------------------------- + for i in 32 to 47 loop + simWaitUntilRisingEdge(clk, 1); + ce <= not ce; + we1 <= '1'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + ------------------------------------------------------------------------- + -- Finish + simWaitUntilRisingEdge(clk, 1); + ce <= '0'; + we1 <= '-'; + a1 <= (others => '-'); + d1 <= (others => '-'); + + -- This process is finished + finished1 <= true; + simDeactivateProcess(simProcessID); + wait; -- forever + end process Stimuli1; + + -- Input stimuli for Port 2 (Read) + -- =========================================================================== + Stimuli2: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Stimuli2"); + begin + -- No operation on first rising clock edge + a2 <= (others => '-'); + rd_d2 <= (others => '-'); + + -- Write in 8 consecutive clock cycles on port 1, read one cycle later on + -- port 2 + ------------------------------------------------------------------------- + simWaitUntilRisingEdge(clk, 1); + -- first write on port 1 here + a2 <= (others => '-'); + rd_d2 <= (others => '-'); + + for i in 0 to 7 loop + simWaitUntilRisingEdge(clk, 1); + a2 <= to_unsigned(i, A_BITS); + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + -- Alternating write on port 1 / read on port 2 + ------------------------------------------------------------------------- + simWaitUntilRisingEdge(clk, 1); + -- first write on port 1 here + a2 <= (others => '-'); + rd_d2 <= (others => '-'); + + for i in 8 to 15 loop + simWaitUntilRisingEdge(clk, 1); + a2 <= to_unsigned(i, A_BITS); + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + -- Read in 8 consecutive clock cycles on port 2, write one cycle later on + -- port 1 + ------------------------------------------------------------------------- + for i in 16 to 23 loop + simWaitUntilRisingEdge(clk, 1); + a2 <= to_unsigned(i, A_BITS); + rd_d2 <= (others => 'U'); -- memory not yet initialized + end loop; + + simWaitUntilRisingEdge(clk, 1); + -- last write on port 1 here + a2 <= (others => '-'); + rd_d2 <= (others => '-'); + + -- Read and write in 8 consecutive clock cycles at the same time + ------------------------------------------------------------------------- + for i in 24 to 31 loop + simWaitUntilRisingEdge(clk, 1); + a2 <= to_unsigned(i, A_BITS); + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + -- Read and write 8 times at the same time every second clock cycle + ------------------------------------------------------------------------- + for i in 32 to 47 loop + simWaitUntilRisingEdge(clk, 1); + a2 <= to_unsigned(i, A_BITS); + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + ------------------------------------------------------------------------- + -- Finish + simWaitUntilRisingEdge(clk, 1); + a2 <= (others => '-'); + rd_d2 <= (others => '-'); + + -- This process is finished + finished2 <= true; + simDeactivateProcess(simProcessID); + wait; -- forever + end process Stimuli2; + + -- Checker + -- =========================================================================== + + -- Also checks if old value is kept if ce = '0' + exp_q2 <= rd_d2 when rising_edge(clk) and ce = '1'; + + Checker2: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Checker2"); + variable i : integer; + begin + while not finished2 loop + simWaitUntilRisingEdge(clk, 1); + simAssertion((q2 = exp_q2) or -- also matches 'X'es + std_match(q2, exp_q2)); -- also matches '-'es + end loop; + + -- This process is finished + simDeactivateProcess(simProcessID); + wait; -- forever + end process Checker2; + +end architecture; From c90631fb4718d1fd428f47b99bd03225181fb33c Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 22 Nov 2016 17:36:52 +0100 Subject: [PATCH 58/97] Catch "Ctrl+C" while configuring PoC. Implemented ToolMixIn for class GHDL. --- py/PoC.py | 3 +++ py/ToolChains/GHDL.py | 7 +++++-- py/ToolChains/Git.py | 33 +++------------------------------ 3 files changed, 11 insertions(+), 32 deletions(-) diff --git a/py/PoC.py b/py/PoC.py index b57fad15..39fe3b26 100644 --- a/py/PoC.py +++ b/py/PoC.py @@ -446,6 +446,9 @@ def HandleConfiguration(self, args): break except ExceptionBase as ex: print(" {RED}FAULT:{NOCOLOR} {0}".format(ex.message, **Init.Foreground)) + except KeyboardInterrupt: + print("\n\n{RED}Abort configuration.\nNo files have been created or changed.{NOCOLOR}".format(**Init.Foreground)) + return # write and re-read configuration self.__WritePoCConfiguration() diff --git a/py/ToolChains/GHDL.py b/py/ToolChains/GHDL.py index cebd6040..0c6e1e72 100644 --- a/py/ToolChains/GHDL.py +++ b/py/ToolChains/GHDL.py @@ -38,6 +38,7 @@ from re import compile as re_compile from subprocess import check_output, CalledProcessError +from lib.Functions import CallByRefParam from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException from Base.Exceptions import PlatformNotSupportedException from Base.Executable import Executable, LongValuedFlagArgument @@ -46,7 +47,7 @@ from Base.Logging import LogEntry, Severity from Base.Simulator import PoCSimulationResultFilter, SimulationResult from Base.ToolChain import ToolChainException -from lib.Functions import CallByRefParam +from ToolChains import ToolMixIn __api__ = [ @@ -179,8 +180,10 @@ def __WriteGHDLSection(self, binPath): self._host.PoCConfig[self._section]['Backend'] = backend -class GHDL(Executable): +class GHDL(Executable, ToolMixIn): def __init__(self, platform, dryrun, binaryDirectoryPath, version, backend, logger=None): + ToolMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger=logger) + if (platform == "Windows"): executablePath = binaryDirectoryPath / "ghdl.exe" elif (platform == "Linux"): executablePath = binaryDirectoryPath / "ghdl" elif (platform == "Darwin"): executablePath = binaryDirectoryPath / "ghdl" diff --git a/py/ToolChains/Git.py b/py/ToolChains/Git.py index 2512f47e..8f73852b 100644 --- a/py/ToolChains/Git.py +++ b/py/ToolChains/Git.py @@ -42,42 +42,15 @@ from Base.Exceptions import PlatformNotSupportedException, CommonException from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException, SkipConfigurationException -from Base.Executable import Executable, ExecutableArgument, CommandLineArgumentList, CommandArgument, LongFlagArgument, ValuedFlagArgument, StringArgument, \ - LongValuedFlagArgument, LongTupleArgument +from Base.Executable import Executable, ExecutableArgument, CommandLineArgumentList +from Base.Executable import CommandArgument, LongFlagArgument, ValuedFlagArgument, StringArgument, LongValuedFlagArgument, LongTupleArgument from Base.ToolChain import ToolChainException -from ToolChains import ToolMixIn - -__api__ = [ - 'GitException', - 'Configuration', - 'Git', - 'GitSCM', - 'GitRevParse', - 'GitRevList', - 'GitDescribe', - 'GitConfig' -] -__all__ = __api__ - - -__api__ = [ - 'GitException', - 'Configuration', - 'GitMixIn', - 'Git', - 'GitSCM', - 'GitRevParse', - 'GitRevList', - 'GitDescribe', - 'GitConfig' -] -__all__ = __api__ +from ToolChains import ToolMixIn __api__ = [ 'GitException', 'Configuration', - 'GitMixIn', 'Git', 'GitSCM', 'GitRevParse', From 33e80e6e2a668bb64a9c585f0f1c2345746abfaa Mon Sep 17 00:00:00 2001 From: Martin Zabel Date: Tue, 22 Nov 2016 17:57:36 +0100 Subject: [PATCH 59/97] New and updated IP cores for Caches. Related updates in other IP cores. Minor fix in toolchain. --- docs/ChangeLog/2016/v1.x.rst | 12 + docs/IPCores/cache/cache_cpu.rst | 177 +++++++ docs/IPCores/cache/cache_mem.rst | 137 ++++++ docs/IPCores/cache/cache_par.rst | 17 +- docs/IPCores/cache/cache_par2.rst | 121 +++++ docs/IPCores/cache/cache_tagunit_par.rst | 47 +- docs/IPCores/cache/index.rst | 32 +- .../ddr2/ddr2_mem2mig_adapter_Spartan6.rst | 2 +- .../mem/ddr3/ddr3_mem2mig_adapter_Series7.rst | 2 +- py/.idea/workspace.xml | 183 +++---- py/ToolChains/Altera/Quartus.py | 2 + py/config.entity.ini | 44 ++ py/config.structure.ini | 3 + src/cache/README.md | 38 +- src/cache/cache_cpu.files | 12 + src/cache/cache_cpu.vhdl | 422 ++++++++++++++++ src/cache/cache_mem.files | 16 + src/cache/cache_mem.vhdl | 348 +++++++++++++ src/cache/cache_par.vhdl | 22 +- src/cache/cache_par2.files | 19 + src/cache/cache_par2.vhdl | 253 ++++++++++ src/cache/cache_tagunit_par.vhdl | 191 +++++-- .../ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl | 3 +- .../ddr3/ddr3_mem2mig_adapter_Series7.vhdl | 17 +- tb/cache/cache_cpu_tb.files | 15 + tb/cache/cache_cpu_tb.vhdl | 450 +++++++++++++++++ tb/cache/cache_mem_tb.files | 15 + tb/cache/cache_mem_tb.vhdl | 464 ++++++++++++++++++ tb/cache/cache_par2_cocotb.py | 342 +++++++++++++ tb/cache/cache_par2_tb.files | 17 + tb/cache/cache_par_cocotb.py | 6 +- tb/mem/mem_model.vhdl | 206 ++++++++ 32 files changed, 3401 insertions(+), 234 deletions(-) create mode 100644 docs/IPCores/cache/cache_cpu.rst create mode 100644 docs/IPCores/cache/cache_mem.rst create mode 100644 docs/IPCores/cache/cache_par2.rst create mode 100644 src/cache/cache_cpu.files create mode 100644 src/cache/cache_cpu.vhdl create mode 100644 src/cache/cache_mem.files create mode 100644 src/cache/cache_mem.vhdl create mode 100644 src/cache/cache_par2.files create mode 100644 src/cache/cache_par2.vhdl create mode 100644 tb/cache/cache_cpu_tb.files create mode 100644 tb/cache/cache_cpu_tb.vhdl create mode 100644 tb/cache/cache_mem_tb.files create mode 100644 tb/cache/cache_mem_tb.vhdl create mode 100644 tb/cache/cache_par2_cocotb.py create mode 100644 tb/cache/cache_par2_tb.files create mode 100644 tb/mem/mem_model.vhdl diff --git a/docs/ChangeLog/2016/v1.x.rst b/docs/ChangeLog/2016/v1.x.rst index 1fdd0ec2..3c2d7649 100644 --- a/docs/ChangeLog/2016/v1.x.rst +++ b/docs/ChangeLog/2016/v1.x.rst @@ -28,10 +28,22 @@ Already documented changes are available on the ``release`` branch at GitHub. * New Entities * :ref:`IP:ocram_sdp_wf` + * :ref:`IP:cache_par2` + * :ref:`IP:cache_cpu` + * :ref:`IP:cache_mem` + +* Updated Entities + + * Interface of :ref:`IP:cache_tagunit_par` changed slightly. + * New port "write-mask" in :ref:`IP:ddr3_mem2mig_adapter_Series7`. + * New port "write-mask" in :ref:`IP:ddr2_mem2mig_adapter_Spartan6`. * New Testbenches * Testbench for :ref:`IP:ocram_sdp_wf` + * Testbench for :ref:`IP:cache_par2` + * Testbench for :ref:`IP:cache_cpu` + * Testbench for :ref:`IP:cache_mem` * New Constraints * Shipped Tool and Helper Scripts diff --git a/docs/IPCores/cache/cache_cpu.rst b/docs/IPCores/cache/cache_cpu.rst new file mode 100644 index 00000000..c0b62cb1 --- /dev/null +++ b/docs/IPCores/cache/cache_cpu.rst @@ -0,0 +1,177 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/cache/cache_cpu.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_cpu_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + + +.. _IP:cache_cpu: + +cache_cpu +######### + +This unit provides a cache (:ref:`IP:cache_par2`) together +with a cache controller which reads / writes cache lines from / to memory. +The memory is accessed using a :ref:`INT:PoC.Mem` interfaces, the related +ports and parameters are prefixed with ``mem_``. + +The CPU side (prefix ``cpu_``) has a modified PoC.Mem interface, so that +this unit can be easily integrated into processor pipelines. For example, +let's have a pipeline where a load/store instruction is executed in 3 +stages (after fetching, decoding, ...): + +1. Execute (EX) for address calculation, +2. Load/Store 1 (LS1) for the cache access, +3. Load/Store 2 (LS2) where the cache returns the read data. + +The read data is always returned one cycle after the cache access completes, +so there is conceptually a pipeline register within this unit. The stage LS2 +can be merged with a write-back stage if the clock period allows so. + +The stage LS1 and thus EX and LS2 must stall, until the cache access is +completed, i.e., the EX/LS1 pipeline register must hold the cache request +until it is acknowledged by the cache. This is signaled by ``cpu_got`` as +described in Section Operation below. The pipeline moves forward (is +enabled) when:: + + pipeline_enable <= (not cpu_req) or cpu_got; + +If the pipeline can stall due to other reasons, care must be taken to not +unintentionally executing the cache access twice or missing the read data. + +Of course, the EX/LS1 pipeline register can be omitted and the CPU side +directly fed by the address caculator. But be aware of the high setup time +of this unit and high propate time for ``cpu_got``. + +This unit supports only one outstanding CPU request. More outstanding +requests are provided by :ref:`IP:cache_mem`. + + +Configuration +************* + ++--------------------+-----------------------------------------------------+ +| Parameter | Description | ++====================+=====================================================+ +| REPLACEMENT_POLICY | Replacement policy of embedded cache. For supported | +| | values see PoC.cache_replacement_policy. | ++--------------------+-----------------------------------------------------+ +| CACHE_LINES | Number of cache lines. | ++--------------------+-----------------------------------------------------+ +| ASSOCIATIVITY | Associativity of embedded cache. | ++--------------------+-----------------------------------------------------+ +| CPU_ADDR_BITS | Number of address bits on the CPU side. Each address| +| | identifies one memory word as seen from the CPU. | +| | Calculated from other parameters as described below.| ++--------------------+-----------------------------------------------------+ +| CPU_DATA_BITS | Width of the data bus (in bits) on the CPU side. | +| | CPU_DATA_BITS must be divisible by 8. | ++--------------------+-----------------------------------------------------+ +| MEM_ADDR_BITS | Number of address bits on the memory side. Each | +| | address identifies one word in the memory. | ++--------------------+-----------------------------------------------------+ +| MEM_DATA_BITS | Width of a memory word and of a cache line in bits. | +| | MEM_DATA_BITS must be divisible by CPU_DATA_BITS. | ++--------------------+-----------------------------------------------------+ + +If the CPU data-bus width is smaller than the memory data-bus width, then +the CPU needs additional address bits to identify one CPU data word inside a +memory word. Thus, the CPU address-bus width is calculated from:: + + CPU_ADDR_BITS=log2ceil(MEM_DATA_BITS/CPU_DATA_BITS)+MEM_ADDR_BITS + +The write policy is: write-through, no-write-allocate. + + +Operation +********* + +Alignment of Cache / Memory Accesses +++++++++++++++++++++++++++++++++++++ + +Memory accesses are always aligned to a word boundary. Each memory word +(and each cache line) consists of MEM_DATA_BITS bits. +For example if MEM_DATA_BITS=128: + +* memory address 0 selects the bits 0..127 in memory, +* memory address 1 selects the bits 128..256 in memory, and so on. + +Cache accesses are always aligned to a CPU word boundary. Each CPU word +consists of CPU_DATA_BITS bits. For example if CPU_DATA_BITS=32: + +* CPU address 0 selects the bits 0.. 31 in memory word 0, +* CPU address 1 selects the bits 32.. 63 in memory word 0, +* CPU address 2 selects the bits 64.. 95 in memory word 0, +* CPU address 3 selects the bits 96..127 in memory word 0, +* CPU address 4 selects the bits 0.. 31 in memory word 1, +* CPU address 5 selects the bits 32.. 63 in memory word 1, and so on. + + +Shared and Memory Side Interface +++++++++++++++++++++++++++++++++ + +A synchronous reset must be applied even on a FPGA. + +The memory side interface is documented in detail :ref:`here `. + + +CPU Side Interface +++++++++++++++++++ + +The CPU (pipeline stage LS1, see above) issues a request by setting +``cpu_req``, ``cpu_write``, ``cpu_addr``, ``cpu_wdata`` and ``cpu_wmask`` as +in the :ref:`INT:PoC.Mem` interface. The cache acknowledges the request by +setting ``cpu_got`` to '1'. If the request is not acknowledged (``cpu_got = +'0'``) in the current clock cycle, then the request must be repeated in the +following clock cycle(s) until it is acknowledged, i.e., the pipeline must +stall. + +A cache access is completed when it is acknowledged. A new request can be +issued in the following clock cycle. + +Of course, ``cpu_got`` may be asserted in the same clock cycle where the +request was issued if a read hit occurs. This allows a throughput of one +(read) request per clock cycle, but the drawback is, that ``cpu_got`` has a +high propagation delay. Thus, this output should only control a simple +pipeline enable logic. + +When ``cpu_got`` is asserted for a read access, then the read data will be +available in the following clock cycle. + +Due to the write-through policy, a write will always take several clock +cycles and acknowledged when the data has been issued to the memory. + +.. WARNING:: + + If the design is synthesized with Xilinx ISE / XST, then the synthesis + option "Keep Hierarchy" must be set to SOFT or TRUE. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/cache/cache_cpu.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 175-207 + +.. seealso:: + + :ref:`IP:cache_mem` + + + +.. only:: latex + + Source file: :pocsrc:`cache/cache_cpu.vhdl ` diff --git a/docs/IPCores/cache/cache_mem.rst b/docs/IPCores/cache/cache_mem.rst new file mode 100644 index 00000000..dd2c4b2f --- /dev/null +++ b/docs/IPCores/cache/cache_mem.rst @@ -0,0 +1,137 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/cache/cache_mem.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_mem_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + + +.. _IP:cache_mem: + +cache_mem +######### + +This unit provides a cache (:ref:`IP:cache_par2`) together +with a cache controller which reads / writes cache lines from / to memory. +It has two :ref:`INT:PoC.Mem` interfaces: + +* one for the "CPU" side (ports with prefix ``cpu_``), and +* one for the memory side (ports with prefix ``mem_``). + +Thus, this unit can be placed into an already available memory path between +the CPU and the memory (controller). If you want to plugin a cache into a +CPU pipeline, see :ref:`IP:cache_cpu`. + + +Configuration +************* + ++--------------------+-----------------------------------------------------+ +| Parameter | Description | ++====================+=====================================================+ +| REPLACEMENT_POLICY | Replacement policy of embedded cache. For supported | +| | values see PoC.cache_replacement_policy. | ++--------------------+-----------------------------------------------------+ +| CACHE_LINES | Number of cache lines. | ++--------------------+-----------------------------------------------------+ +| ASSOCIATIVITY | Associativity of embedded cache. | ++--------------------+-----------------------------------------------------+ +| CPU_ADDR_BITS | Number of address bits on the CPU side. Each address| +| | identifies one memory word as seen from the CPU. | +| | Calculated from other parameters as described below.| ++--------------------+-----------------------------------------------------+ +| CPU_DATA_BITS | Width of the data bus (in bits) on the CPU side. | +| | CPU_DATA_BITS must be divisible by 8. | ++--------------------+-----------------------------------------------------+ +| MEM_ADDR_BITS | Number of address bits on the memory side. Each | +| | address identifies one word in the memory. | ++--------------------+-----------------------------------------------------+ +| MEM_DATA_BITS | Width of a memory word and of a cache line in bits. | +| | MEM_DATA_BITS must be divisible by CPU_DATA_BITS. | ++--------------------+-----------------------------------------------------+ +| OUTSTANDING_REQ | Number of oustanding requests, see notes below. | ++--------------------+-----------------------------------------------------+ + +If the CPU data-bus width is smaller than the memory data-bus width, then +the CPU needs additional address bits to identify one CPU data word inside a +memory word. Thus, the CPU address-bus width is calculated from:: + + CPU_ADDR_BITS=log2ceil(MEM_DATA_BITS/CPU_DATA_BITS)+MEM_ADDR_BITS + +The write policy is: write-through, no-write-allocate. + +The maximum throughput is one request per clock cycle, except for +``OUSTANDING_REQ = 1``. + +If ``OUTSTANDING_REQ`` is: + +* 1: then 1 request is buffered by a single register. To give a short + critical path (clock-to-output delay) for ``cpu_rdy``, the throughput is + degraded to one request per 2 clock cycles at maximum. + +* 2: then 2 requests are buffered by :ref:`IP:fifo_glue`. This setting has + the lowest area requirements without degrading the performance. + +* >2: then the requests are buffered by :ref:`IP:fifo_cc_got`. The number of + outstanding requests is rounded up to the next suitable value. This setting + is useful in applications with out-of-order execution (of other + operations). The CPU requests to the cache are always processed in-order. + + +Operation +********* + +Memory accesses are always aligned to a word boundary. Each memory word +(and each cache line) consists of MEM_DATA_BITS bits. +For example if MEM_DATA_BITS=128: + +* memory address 0 selects the bits 0..127 in memory, +* memory address 1 selects the bits 128..256 in memory, and so on. + +Cache accesses are always aligned to a CPU word boundary. Each CPU word +consists of CPU_DATA_BITS bits. For example if CPU_DATA_BITS=32: + +* CPU address 0 selects the bits 0.. 31 in memory word 0, +* CPU address 1 selects the bits 32.. 63 in memory word 0, +* CPU address 2 selects the bits 64.. 95 in memory word 0, +* CPU address 3 selects the bits 96..127 in memory word 0, +* CPU address 4 selects the bits 0.. 31 in memory word 1, +* CPU address 5 selects the bits 32.. 63 in memory word 1, and so on. + +A synchronous reset must be applied even on a FPGA. + +The interface is documented in detail :ref:`here `. + +.. WARNING:: + + If the design is synthesized with Xilinx ISE / XST, then the synthesis + option "Keep Hierarchy" must be set to SOFT or TRUE. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/cache/cache_mem.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 135-169 + +.. seealso:: + + :ref:`IP:cache_cpu` + + + +.. only:: latex + + Source file: :pocsrc:`cache/cache_mem.vhdl ` diff --git a/docs/IPCores/cache/cache_par.rst b/docs/IPCores/cache/cache_par.rst index 96c1e358..879f6ee1 100644 --- a/docs/IPCores/cache/cache_par.rst +++ b/docs/IPCores/cache/cache_par.rst @@ -20,6 +20,16 @@ cache_par ######### +Implements a cache with parallel tag-unit and data memory. + +.. NOTE:: + This component infers a single-port memory with read-first behavior, that + is, upon writes the old-data is returned on the read output. Such memory + (e.g. LUT-RAM) is not available on all devices. Thus, synthesis may + infer a lot of flip-flops plus multiplexers instead, which is very inefficient. + It is recommended to use :doc:`PoC.cache.par2 ` instead which has a + slightly different interface. + All inputs are synchronous to the rising-edge of the clock `clock`. **Command truth table:** @@ -57,6 +67,11 @@ Upon replacing a cache line, the new content is given by ``CacheLineIn``. The old content is outputed on ``CacheLineOut`` and the old tag on ``OldAddress``, both with a latency of one clock cycle. +.. WARNING:: + + If the design is synthesized with Xilinx ISE / XST, then the synthesis + option "Keep Hierarchy" must be set to SOFT or TRUE. + .. rubric:: Entity Declaration: @@ -65,7 +80,7 @@ both with a latency of one clock cycle. :language: vhdl :tab-width: 2 :linenos: - :lines: 76-100 + :lines: 91-115 diff --git a/docs/IPCores/cache/cache_par2.rst b/docs/IPCores/cache/cache_par2.rst new file mode 100644 index 00000000..f3e8134f --- /dev/null +++ b/docs/IPCores/cache/cache_par2.rst @@ -0,0 +1,121 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/cache/cache_par2.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_par2_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + + +.. _IP:cache_par2: + +cache_par2 +########## + +Cache with parallel tag-unit and data memory. For the data memory, +:ref:`IP:ocram_sp` is used. + +Configuration +************* + ++--------------------+----------------------------------------------------+ +| Parameter | Description | ++====================+====================================================+ +| REPLACEMENT_POLICY | Replacement policy. For supported policies see | +| | PoC.cache_replacement_policy. | ++--------------------+----------------------------------------------------+ +| CACHE_LINES | Number of cache lines. | ++--------------------+----------------------------------------------------+ +| ASSOCIATIVITY | Associativity of the cache. | ++--------------------+----------------------------------------------------+ +| ADDR_BITS | Number of address bits. Each address identifies | +| | exactly one cache line in memory. | ++--------------------+----------------------------------------------------+ +| DATA_BITS | Size of a cache line in bits. | +| | DATA_BITS must be divisible by 8. | ++--------------------+----------------------------------------------------+ + + +Command truth table +******************* + ++---------+-----------+-------------+---------+---------------------------------+ +| Request | ReadWrite | Invalidate | Replace | Command | ++=========+===========+=============+=========+=================================+ +| 0 | 0 | 0 | 0 | None | ++---------+-----------+-------------+---------+---------------------------------+ +| 1 | 0 | 0 | 0 | Read cache line | ++---------+-----------+-------------+---------+---------------------------------+ +| 1 | 1 | 0 | 0 | Update cache line | ++---------+-----------+-------------+---------+---------------------------------+ +| 1 | 0 | 1 | 0 | Read cache line and discard it | ++---------+-----------+-------------+---------+---------------------------------+ +| 1 | 1 | 1 | 0 | Write cache line and discard it | ++---------+-----------+-------------+---------+---------------------------------+ +| 0 | 0 | 0 | 1 | Read cache line before replace. | ++---------+-----------+-------------+---------+---------------------------------+ +| 0 | 1 | 0 | 1 | Replace cache line. | ++---------+-----------+-------------+---------+---------------------------------+ + + +Operation +********* + +All inputs are synchronous to the rising-edge of the clock `clock`. + +All commands use ``Address`` to lookup (request) or replace a cache line. +``Address`` and ``OldAddress`` do not include the word/byte select part. +Each command is completed within one clock cycle, but outputs are delayed as +described below. + +Upon requests, the outputs ``CacheMiss`` and ``CacheHit`` indicate (high-active) +whether the ``Address`` is stored within the cache, or not. Both outputs have a +latency of one clock cycle (pipelined) if ``HIT_MISS_REG`` is true, otherwise the +result is outputted immediately (combinational). + +Upon writing a cache line, the new content is given by ``CacheLineIn``. +Only the bytes which are not masked, i.e. the corresponding bit in WriteMask +is '0', are actually written. + +Upon reading a cache line, the current content is outputed on ``CacheLineOut`` +with a latency of one clock cycle. + +Replacing a cache line requires two steps, both with ``Replace = '1'``: + +1. Read old contents of cache line by setting ``ReadWrite`` to '0'. The old + content is outputed on ``CacheLineOut`` and the old tag on ``OldAddress``, + both with a latency of one clock cycle. + +2. Write new cache line by setting ``ReadWrite`` to '1'. The new content is + given by ``CacheLineIn``. All bytes shall be written, i.e. + ``WriteMask = 0``. The new cache line content will be outputed + again on ``CacheLineOut`` in the next clock cycle (latency = 1). + +.. WARNING:: + + If the design is synthesized with Xilinx ISE / XST, then the synthesis + option "Keep Hierarchy" must be set to SOFT or TRUE. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/cache/cache_par2.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 123-149 + + + +.. only:: latex + + Source file: :pocsrc:`cache/cache_par2.vhdl ` diff --git a/docs/IPCores/cache/cache_tagunit_par.rst b/docs/IPCores/cache/cache_tagunit_par.rst index 93fe7905..7f2cbb25 100644 --- a/docs/IPCores/cache/cache_tagunit_par.rst +++ b/docs/IPCores/cache/cache_tagunit_par.rst @@ -20,9 +20,28 @@ cache_tagunit_par ################# -All inputs are synchronous to the rising-edge of the clock ``clock``. +Tag-unit with fully-parallel compare of tag. -**Command thruth table:** +Configuration +************* + ++--------------------+----------------------------------------------------+ +| Parameter | Description | ++====================+====================================================+ +| REPLACEMENT_POLICY | Replacement policy. For supported policies see | +| | PoC.cache_replacement_policy. | ++--------------------+----------------------------------------------------+ +| CACHE_LINES | Number of cache lines. | ++--------------------+----------------------------------------------------+ +| ASSOCIATIVITY | Associativity of the cache. | ++--------------------+----------------------------------------------------+ +| ADDRESS_BITS | Number of address bits. Each address identifies | +| | exactly one cache line in memory. | ++--------------------+----------------------------------------------------+ + + +Command truth table +******************* +---------+-----------+-------------+---------+----------------------------------+ | Request | ReadWrite | Invalidate | Replace | Command | @@ -40,6 +59,12 @@ All inputs are synchronous to the rising-edge of the clock ``clock``. | 0 | | 0 | 1 | Replace cache line. | +---------+-----------+-------------+---------+----------------------------------+ + +Operation +********* + +All inputs are synchronous to the rising-edge of the clock `clock`. + All commands use ``Address`` to lookup (request) or replace a cache line. Each command is completed within one clock cycle. @@ -50,13 +75,27 @@ If hit, ``LineIndex`` specifies the cache line where to find the content. The output ``ReplaceLineIndex`` indicates which cache line will be replaced as next by a replace command. The output ``OldAddress`` specifies the old tag stored at this -index. The replace command will store the ``NewAddress`` and update the cache-line +index. The replace command will store the ``Address`` and update the cache-line usage at the rising-edge of the clock. For a direct-mapped cache, the number of ``CACHE_LINES`` must be a power of 2. For a set-associative cache, the expression ``CACHE_LINES / ASSOCIATIVITY`` must be a power of 2. +.. NOTE:: + The port ``NewAddress`` has been removed. Use ``Address`` instead as + described above. + + If ``Address`` is fed from a register and an Altera FPGA is used, then + Quartus Map converts the tag memory from a memory with asynchronous read to a + memory with synchronous read by adding a pass-through logic. Quartus Map + reports warning 276020 which is intended. + +.. WARNING:: + + If the design is synthesized with Xilinx ISE / XST, then the synthesis + option "Keep Hierarchy" must be set to SOFT or TRUE. + .. rubric:: Entity Declaration: @@ -65,7 +104,7 @@ must be a power of 2. :language: vhdl :tab-width: 2 :linenos: - :lines: 75-99 + :lines: 114-137 diff --git a/docs/IPCores/cache/index.rst b/docs/IPCores/cache/index.rst index 033ac76e..ae107330 100644 --- a/docs/IPCores/cache/index.rst +++ b/docs/IPCores/cache/index.rst @@ -3,19 +3,43 @@ PoC.cache ========= -These are cache entities.... +The namespace `PoC.cache` offers different cache implementations. **Entities** - * :ref:`IP:cache_par` - * :ref:`IP:cache_tagunit_par` - * :ref:`IP:cache_tagunit_seq` + * :ref:`IP:cache_cpu`: Cache with cache controller to be used within a CPU. + + * :ref:`IP:cache_mem`: Cache with :ref:`INT:PoC.Mem` interface on the "CPU" side. + + * :ref:`IP:cache_par`: Cache with parallel tag-unit and + data memory (using infered memory). + + * :ref:`IP:cache_par2`: Cache with parallel tag-unit and + data memory (using :ref:`IP:ocram_sp`). + + * :ref:`IP:cache_tagunit_par`: Tag-Unit with + parallel tag comparison. Configurable as: + + * Full-associative cache, + * Direct-mapped cache, or + * Set-associative cache. + + * :ref:`IP:cache_tagunit_seq`: Tag-Unit with + sequential tag comparison. Configurable as: + + * Full-associative cache, + * Direct-mapped cache, or + * Set-associative cache. + .. toctree:: :hidden: + cache_cpu + cache_mem cache_par + cache_par2 cache_replacement_policy cache_tagunit_par cache_tagunit_seq diff --git a/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst b/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst index df79f3fc..8e74a2a7 100644 --- a/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst +++ b/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst @@ -52,7 +52,7 @@ Containts only combinational logic. :language: vhdl :tab-width: 2 :linenos: - :lines: 61-95 + :lines: 61-96 diff --git a/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst b/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst index 15ddeac8..5d8cf0e1 100644 --- a/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst +++ b/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst @@ -51,7 +51,7 @@ Containts only combinational logic. :language: vhdl :tab-width: 2 :linenos: - :lines: 60-95 + :lines: 60-96 diff --git a/py/.idea/workspace.xml b/py/.idea/workspace.xml index 66b83662..aeb0ff9d 100644 --- a/py/.idea/workspace.xml +++ b/py/.idea/workspace.xml @@ -3,12 +3,6 @@ - - - - - - @@ -31,8 +25,8 @@ - - + + @@ -41,7 +35,7 @@ - + @@ -51,7 +45,7 @@ - + @@ -61,23 +55,13 @@ - + - - - - - - - - - - @@ -92,7 +76,7 @@ - + @@ -102,10 +86,8 @@ - - - - + + @@ -114,7 +96,7 @@ - + @@ -125,7 +107,10 @@ - + + + + @@ -133,11 +118,9 @@ - + - - - + @@ -156,7 +139,7 @@ - + @@ -281,24 +264,6 @@ - - - - - - - - - - - - - - @@ -363,22 +328,26 @@ + + + + + - - - - + + + @@ -792,21 +761,21 @@ - - - - + + + + @@ -823,11 +792,6 @@ - - file://$PROJECT_DIR$/Parser/RulesCodeDOM.py - 234 - file://$PROJECT_DIR$/PoC.py 491 @@ -861,13 +825,7 @@ - - - - - - - + @@ -897,13 +855,7 @@ - - - - - - - + @@ -995,13 +947,7 @@ - - - - - - - + @@ -1021,7 +967,6 @@ - @@ -1029,7 +974,6 @@ - @@ -1047,13 +991,7 @@ - - - - - - - + @@ -1079,7 +1017,6 @@ - @@ -1108,7 +1045,7 @@ - + @@ -1117,17 +1054,18 @@ - + + + + - + - - - + @@ -1149,7 +1087,6 @@ - @@ -1157,14 +1094,13 @@ - - + @@ -1172,17 +1108,15 @@ - - - - + + - - + + @@ -1190,14 +1124,14 @@ - + - + @@ -1205,7 +1139,7 @@ - + @@ -1213,20 +1147,13 @@ - + - - - - - - - - + diff --git a/py/ToolChains/Altera/Quartus.py b/py/ToolChains/Altera/Quartus.py index e647c786..0bf6bb8c 100644 --- a/py/ToolChains/Altera/Quartus.py +++ b/py/ToolChains/Altera/Quartus.py @@ -254,6 +254,8 @@ def MapFilter(gen): yield LogEntry(line, Severity.Warning) elif line.startswith(" Info ("): yield LogEntry(line, Severity.Verbose) + elif line.startswith(" Info ("): + yield LogEntry(line, Severity.Verbose) elif line.startswith("Info:"): yield LogEntry(line, Severity.Info) elif line.startswith(" Info:"): diff --git a/py/config.entity.ini b/py/config.entity.ini index 776f8721..be61c3b9 100644 --- a/py/config.entity.ini +++ b/py/config.entity.ini @@ -163,18 +163,62 @@ HDLParameters = BITS=32 # PoC.cache # ============================================================================== +[IP.cache.cpu] +tb = VHDLTestbench +nl1 = XSTNetlist +nl2 = QuartusNetlist +nl3 = LSENetlist +nl4 = VivadoNetlist +# 64 KiByte 4-way set-associative, 4 GiB RAM (2**26 x 512 bit), 64 bytes per cache line +HDLParameters = CACHE_LINES=1024; ASSOCIATIVITY=4; MEM_ADDR_BITS=26; MEM_DATA_BITS=512; CPU_DATA_BITS=32 +[TB.cache.cpu.tb] +[XST.cache.cpu.nl1] +[QMAP.cache.cpu.nl2] +[LSE.cache.cpu.nl3] +[VIVADO.cache.cpu.nl4] + +[IP.cache.mem] +tb = VHDLTestbench +nl1 = XSTNetlist +nl2 = QuartusNetlist +nl3 = LSENetlist +nl4 = VivadoNetlist +# 64 KiByte 4-way set-associative, 4 GiB RAM (2**26 x 512 bit), 64 bytes per cache line +HDLParameters = CACHE_LINES=1024; ASSOCIATIVITY=4; MEM_ADDR_BITS=26; MEM_DATA_BITS=512; CPU_DATA_BITS=32 +[TB.cache.mem.tb] +[XST.cache.mem.nl1] +[QMAP.cache.mem.nl2] +[LSE.cache.mem.nl3] +[VIVADO.cache.mem.nl4] + [IP.cache.par] cocotb = CocoTestbench nl1 = XSTNetlist nl2 = QuartusNetlist nl3 = LSENetlist nl4 = VivadoNetlist +# 64 KiByte 4-way set-associative, 32-bit address space, 64 bytes per cache line +HDLParameters = CACHE_LINES=1024; ASSOCIATIVITY=4; ADDRESS_BITS=26; DATA_BITS=512 [COCOTB.cache.par.cocotb] [XST.cache.par.nl1] [QMAP.cache.par.nl2] [LSE.cache.par.nl3] [VIVADO.cache.par.nl4] +[IP.cache.par2] +cocotb = CocoTestbench +nl1 = XSTNetlist +nl2 = QuartusNetlist +nl3 = LSENetlist +nl4 = VivadoNetlist +# 64 KiByte 4-way set-associative, 32-bit address space, 64 bytes per cache line +HDLParameters = CACHE_LINES=1024; ASSOCIATIVITY=4; ADDR_BITS=32; BYTE_ADDR_BITS=6; DATA_BITS=512 +[COCOTB.cache.par2.cocotb] +[XST.cache.par2.nl1] +[QMAP.cache.par2.nl2] +[LSE.cache.par2.nl3] +[VIVADO.cache.par2.nl4] + [IP.cache.replacement_policy] # tb = VHDLTestbench # [TB.cache.replacement_policy.tb] diff --git a/py/config.structure.ini b/py/config.structure.ini index c37b0920..e12976e9 100644 --- a/py/config.structure.ini +++ b/py/config.structure.ini @@ -103,7 +103,10 @@ ocram_adapter = Entity uart_wrapper = Entity [PoC.cache] +cpu = Entity +mem = Entity par = Entity +par2 = Entity replacement_policy = Entity tagunit_par = Entity tagunit_seq = Entity diff --git a/src/cache/README.md b/src/cache/README.md index 3aafd56b..5a656ec8 100644 --- a/src/cache/README.md +++ b/src/cache/README.md @@ -1,39 +1,5 @@ # Namespace `PoC.cache` -The namespace `PoC.cache` offers different cache implementations. +The namespace `PoC.cache` offers different cache implementations, like full-associative, direct-mapped, and set-associative caches. - -## Package - -The package [`PoC.cache`][cache.pkg] holds all component declarations for this namespace. - - -## Entities - - - [`cache_par`][cache_par] - Cache with parallel tag-unit and data memory. - The cache can be configured as: - - Full-associative cache - - Direct-mapped cache - - Set-assoziative cache - - as well as in data and tag memory size (`CACHE_LINES`, `ADDRESS_BITS`, `DATA_BITS`) - - [`cache_replacement_policy`][cache_replacement_policy] - Wrap different cache replacement policies. - Selectable replacement policies: - - LRU - - *TODO: implement more policies* - - [`cache_tagunit_par`][cache_tagunit_par] - Tag-unit with fully-parallel compare of tag. - The tagunit can be configured as: - - Full-associative cache - - Direct-mapped cache - - Set-assoziative cache - - as well as in tag memory size (`CACHE_LINES`, `ADDRESS_BITS`) - - [`cache_tagunit_seq`][cache_tagunit_seq] - Tag-unit with sequential compare of tag. - - - [cache.pkg]: cache.pkg.vhdl - - [cache_par]: cache_par.vhdl - [cache_replacement_policy]: cache_replacement_policy.vhdl - [cache_tagunit_par]: cache_tagunit_par.vhdl - [cache_tagunit_seq]: cache_tagunit_seq.vhdl +Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/PoC/cache/index.html). diff --git a/src/cache/cache_cpu.files b/src/cache/cache_cpu.files new file mode 100644 index 00000000..94737170 --- /dev/null +++ b/src/cache/cache_cpu.files @@ -0,0 +1,12 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# ============================================================================== +# Note: all files are relative to PoC root directory +# +# Common PoC packages for configuration, synthesis and simulation +include "src/common/common.files" # load common packages + +# PoC.cache +include "src/cache/cache_par2.files" # Embedded Cache +vhdl poc "src/cache/cache_cpu.vhdl" # Top Level diff --git a/src/cache/cache_cpu.vhdl b/src/cache/cache_cpu.vhdl new file mode 100644 index 00000000..4e6e5cd9 --- /dev/null +++ b/src/cache/cache_cpu.vhdl @@ -0,0 +1,422 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Martin Zabel +-- +-- Entity: Cache with cache controller to be used within a CPU +-- +-- Description: +-- ------------------------------------- +-- This unit provides a cache (:ref:`IP:cache_par2`) together +-- with a cache controller which reads / writes cache lines from / to memory. +-- The memory is accessed using a :ref:`INT:PoC.Mem` interfaces, the related +-- ports and parameters are prefixed with ``mem_``. +-- +-- The CPU side (prefix ``cpu_``) has a modified PoC.Mem interface, so that +-- this unit can be easily integrated into processor pipelines. For example, +-- let's have a pipeline where a load/store instruction is executed in 3 +-- stages (after fetching, decoding, ...): +-- +-- 1. Execute (EX) for address calculation, +-- 2. Load/Store 1 (LS1) for the cache access, +-- 3. Load/Store 2 (LS2) where the cache returns the read data. +-- +-- The read data is always returned one cycle after the cache access completes, +-- so there is conceptually a pipeline register within this unit. The stage LS2 +-- can be merged with a write-back stage if the clock period allows so. +-- +-- The stage LS1 and thus EX and LS2 must stall, until the cache access is +-- completed, i.e., the EX/LS1 pipeline register must hold the cache request +-- until it is acknowledged by the cache. This is signaled by ``cpu_got`` as +-- described in Section Operation below. The pipeline moves forward (is +-- enabled) when:: +-- +-- pipeline_enable <= (not cpu_req) or cpu_got; +-- +-- If the pipeline can stall due to other reasons, care must be taken to not +-- unintentionally executing the cache access twice or missing the read data. +-- +-- Of course, the EX/LS1 pipeline register can be omitted and the CPU side +-- directly fed by the address caculator. But be aware of the high setup time +-- of this unit and high propate time for ``cpu_got``. +-- +-- This unit supports only one outstanding CPU request. More outstanding +-- requests are provided by :ref:`IP:cache_mem`. +-- +-- +-- Configuration +-- ************* +-- +-- +--------------------+-----------------------------------------------------+ +-- | Parameter | Description | +-- +====================+=====================================================+ +-- | REPLACEMENT_POLICY | Replacement policy of embedded cache. For supported | +-- | | values see PoC.cache_replacement_policy. | +-- +--------------------+-----------------------------------------------------+ +-- | CACHE_LINES | Number of cache lines. | +-- +--------------------+-----------------------------------------------------+ +-- | ASSOCIATIVITY | Associativity of embedded cache. | +-- +--------------------+-----------------------------------------------------+ +-- | CPU_ADDR_BITS | Number of address bits on the CPU side. Each address| +-- | | identifies one memory word as seen from the CPU. | +-- | | Calculated from other parameters as described below.| +-- +--------------------+-----------------------------------------------------+ +-- | CPU_DATA_BITS | Width of the data bus (in bits) on the CPU side. | +-- | | CPU_DATA_BITS must be divisible by 8. | +-- +--------------------+-----------------------------------------------------+ +-- | MEM_ADDR_BITS | Number of address bits on the memory side. Each | +-- | | address identifies one word in the memory. | +-- +--------------------+-----------------------------------------------------+ +-- | MEM_DATA_BITS | Width of a memory word and of a cache line in bits. | +-- | | MEM_DATA_BITS must be divisible by CPU_DATA_BITS. | +-- +--------------------+-----------------------------------------------------+ +-- +-- If the CPU data-bus width is smaller than the memory data-bus width, then +-- the CPU needs additional address bits to identify one CPU data word inside a +-- memory word. Thus, the CPU address-bus width is calculated from:: +-- +-- CPU_ADDR_BITS=log2ceil(MEM_DATA_BITS/CPU_DATA_BITS)+MEM_ADDR_BITS +-- +-- The write policy is: write-through, no-write-allocate. +-- +-- +-- Operation +-- ********* +-- +-- Alignment of Cache / Memory Accesses +-- ++++++++++++++++++++++++++++++++++++ +-- +-- Memory accesses are always aligned to a word boundary. Each memory word +-- (and each cache line) consists of MEM_DATA_BITS bits. +-- For example if MEM_DATA_BITS=128: +-- +-- * memory address 0 selects the bits 0..127 in memory, +-- * memory address 1 selects the bits 128..256 in memory, and so on. +-- +-- Cache accesses are always aligned to a CPU word boundary. Each CPU word +-- consists of CPU_DATA_BITS bits. For example if CPU_DATA_BITS=32: +-- +-- * CPU address 0 selects the bits 0.. 31 in memory word 0, +-- * CPU address 1 selects the bits 32.. 63 in memory word 0, +-- * CPU address 2 selects the bits 64.. 95 in memory word 0, +-- * CPU address 3 selects the bits 96..127 in memory word 0, +-- * CPU address 4 selects the bits 0.. 31 in memory word 1, +-- * CPU address 5 selects the bits 32.. 63 in memory word 1, and so on. +-- +-- +-- Shared and Memory Side Interface +-- ++++++++++++++++++++++++++++++++ +-- +-- A synchronous reset must be applied even on a FPGA. +-- +-- The memory side interface is documented in detail :ref:`here `. +-- +-- +-- CPU Side Interface +-- ++++++++++++++++++ +-- +-- The CPU (pipeline stage LS1, see above) issues a request by setting +-- ``cpu_req``, ``cpu_write``, ``cpu_addr``, ``cpu_wdata`` and ``cpu_wmask`` as +-- in the :ref:`INT:PoC.Mem` interface. The cache acknowledges the request by +-- setting ``cpu_got`` to '1'. If the request is not acknowledged (``cpu_got = +-- '0'``) in the current clock cycle, then the request must be repeated in the +-- following clock cycle(s) until it is acknowledged, i.e., the pipeline must +-- stall. +-- +-- A cache access is completed when it is acknowledged. A new request can be +-- issued in the following clock cycle. +-- +-- Of course, ``cpu_got`` may be asserted in the same clock cycle where the +-- request was issued if a read hit occurs. This allows a throughput of one +-- (read) request per clock cycle, but the drawback is, that ``cpu_got`` has a +-- high propagation delay. Thus, this output should only control a simple +-- pipeline enable logic. +-- +-- When ``cpu_got`` is asserted for a read access, then the read data will be +-- available in the following clock cycle. +-- +-- Due to the write-through policy, a write will always take several clock +-- cycles and acknowledged when the data has been issued to the memory. +-- +-- .. WARNING:: +-- +-- If the design is synthesized with Xilinx ISE / XST, then the synthesis +-- option "Keep Hierarchy" must be set to SOFT or TRUE. +-- +-- SeeAlso: +-- :ref:`IP:cache_mem` +-- +-- License: +-- ============================================================================= +-- Copyright 2016-2016 Technische Universitaet Dresden - Germany +-- Chair of VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library poc; +use poc.utils.all; + +entity cache_cpu is + generic ( + REPLACEMENT_POLICY : string := "LRU"; + CACHE_LINES : positive; + ASSOCIATIVITY : positive; + CPU_DATA_BITS : positive; + MEM_ADDR_BITS : positive; + MEM_DATA_BITS : positive + ); + port ( + clk : in std_logic; -- clock + rst : in std_logic; -- reset + + -- "CPU" side + cpu_req : in std_logic; + cpu_write : in std_logic; + cpu_addr : in unsigned(log2ceil(MEM_DATA_BITS/CPU_DATA_BITS)+MEM_ADDR_BITS-1 downto 0); + cpu_wdata : in std_logic_vector(CPU_DATA_BITS-1 downto 0); + cpu_wmask : in std_logic_vector(CPU_DATA_BITS/8-1 downto 0); + cpu_got : out std_logic; + cpu_rdata : out std_logic_vector(CPU_DATA_BITS-1 downto 0); + + -- Memory side + mem_req : out std_logic; + mem_write : out std_logic; + mem_addr : out unsigned(MEM_ADDR_BITS-1 downto 0); + mem_wdata : out std_logic_vector(MEM_DATA_BITS-1 downto 0); + mem_wmask : out std_logic_vector(MEM_DATA_BITS/8-1 downto 0); + mem_rdy : in std_logic; + mem_rstb : in std_logic; + mem_rdata : in std_logic_vector(MEM_DATA_BITS-1 downto 0) + ); +end entity; + +architecture rtl of cache_cpu is + -- Ratio 1:n between CPU data bus and cache-line size (memory data bus) + constant RATIO : positive := MEM_DATA_BITS/CPU_DATA_BITS; + + -- Number of address bits identifying the CPU data word within a cache line (memory word) + constant LOWER_ADDR_BITS : natural := log2ceil(RATIO); + + -- Widened CPU data path + signal cpu_wdata_wide : std_logic_vector(MEM_DATA_BITS-1 downto 0); + signal cpu_wmask_wide : std_logic_vector(MEM_DATA_BITS/8-1 downto 0); + + -- Interface to Cache instance. + signal cache_Request : std_logic; + signal cache_ReadWrite : std_logic; + signal cache_Writemask : std_logic_vector(MEM_DATA_BITS/8-1 downto 0); + signal cache_Invalidate : std_logic; + signal cache_Replace : std_logic; + signal cache_Address : std_logic_vector(MEM_ADDR_BITS-1 downto 0); + signal cache_LineIn : std_logic_vector(MEM_DATA_BITS-1 downto 0); + signal cache_LineOut : std_logic_vector(MEM_DATA_BITS-1 downto 0); + signal cache_Hit : std_logic; + signal cache_Miss : std_logic; + + -- FSM and other state registers + type T_FSM is (READY, ACCESS_MEM, READING_MEM, UNKNOWN); + signal fsm_cs : T_FSM -- current state + -- synthesis translate_off + := UNKNOWN + -- synthesis translate_on + ; + signal fsm_ns : T_FSM;-- next state + +begin -- architecture rtl + + cache_inst: entity work.cache_par2 + generic map ( + REPLACEMENT_POLICY => REPLACEMENT_POLICY, + CACHE_LINES => CACHE_LINES, + ASSOCIATIVITY => ASSOCIATIVITY, + ADDR_BITS => MEM_ADDR_BITS, + DATA_BITS => MEM_DATA_BITS, + HIT_MISS_REG => false) + port map ( + Clock => clk, + Reset => rst, + Request => cache_Request, + ReadWrite => cache_ReadWrite, + WriteMask => cache_WriteMask, + Invalidate => cache_Invalidate, + Replace => cache_Replace, + Address => cache_Address, + CacheLineIn => cache_LineIn, + CacheLineOut => cache_LineOut, + CacheHit => cache_Hit, + CacheMiss => cache_Miss, + OldAddress => open); + + -- Address and Data path + -- =========================================================================== + gEqual: if RATIO = 1 generate -- Cache line size equals CPU data bus size + cpu_wdata_wide <= cpu_wdata; + cpu_wmask_wide <= cpu_wmask; + cpu_rdata <= cache_LineOut; + end generate gEqual; + + gWider: if RATIO > 1 generate -- Cache line size is greater than CPU data bus size + signal lower_addr : unsigned(LOWER_ADDR_BITS-1 downto 0); + signal lower_addr_r : unsigned(LOWER_ADDR_BITS-1 downto 0); + type T_ARRAY is array(0 to RATIO-1) of std_logic_vector(CPU_DATA_BITS-1 downto 0); + signal cache_LineOut_array : T_ARRAY; + begin + -- CPU Request Data Path + lower_addr <= cpu_addr(LOWER_ADDR_BITS-1 downto 0); + + l0: for i in 0 to RATIO-1 generate + cpu_wdata_wide((i+1)*CPU_DATA_BITS-1 downto i*CPU_DATA_BITS) <= cpu_wdata; + + cpu_wmask_wide((i+1)*CPU_DATA_BITS/8-1 downto i*CPU_DATA_BITS/8) <= + -- synthesis translate_off + (others => 'X') when is_x(lower_addr) else + -- synthesis translate_on + cpu_wmask when to_integer(lower_addr) = i else + (others => '1'); + end generate l0; + + -- CPU Reply Data Path + lower_addr_r <= lower_addr when rising_edge(clk); -- pipeline register + + l1: for i in 0 to RATIO-1 generate + cache_LineOut_array(i) <= cache_LineOut((i+1)*CPU_DATA_BITS-1 downto i*CPU_DATA_BITS); + end generate l1; + + cpu_rdata <= + -- synthesis translate_off + (others => 'X') when is_x(lower_addr_r) else + -- synthesis translate_on + cache_LineOut_array(to_integer(lower_addr_r)); + end generate gWider; + + -- Cache Request Data Path + cache_Address <= std_logic_vector(cpu_addr(cpu_addr'left downto LOWER_ADDR_BITS)); + cache_LineIn <= mem_rdata when fsm_cs = READING_MEM else cpu_wdata_wide; + cache_WriteMask <= (others => '0') when fsm_cs = READING_MEM else cpu_wmask_wide; + + -- These outputs can be fed from buffer registers, but this is not + -- neccessary because the cpu_* signals will typically be connected to a + -- pipeline register. And even if this pipeline register is omitted, then the + -- cache tag comparison will dominate the critical path. + mem_write <= cpu_write; + mem_addr <= cpu_addr(cpu_addr'left downto LOWER_ADDR_BITS); + mem_wdata <= cpu_wdata_wide; + mem_wmask <= cpu_wmask_wide; + + -- FSM + -- =========================================================================== + process(fsm_cs, cpu_req, cpu_write, cache_Hit, cache_Miss, mem_rdy, mem_rstb) + begin + -- Update state registers + fsm_ns <= fsm_cs; + + -- Control signals for cache access + cache_Request <= '0'; + cache_ReadWrite <= '-'; + cache_Invalidate <= '-'; + cache_Replace <= '0'; + + -- Control / status signals for CPU and MEM side + cpu_got <= '0'; + mem_req <= '0'; + + case fsm_cs is + when READY => + -- Ready for a new cache access. + -- ----------------------------- + cache_Request <= to_x01(cpu_req); + cache_ReadWrite <= to_x01(cpu_write); -- doesn't care if no request + cache_Invalidate <= '0'; + + case ((cache_Hit and cpu_write) or cache_Miss) is + when '1' => -- write successfull but write-through, or cache miss + fsm_ns <= ACCESS_MEM; + when '0' => -- read successfull, or no request + cpu_got <= to_x01(cpu_req); + when others => -- invalid input + fsm_ns <= UNKNOWN; + cpu_got <= 'X'; + end case; + + + when ACCESS_MEM => + -- Access memory. + -- -------------- + mem_req <= '1'; + case to_x01(mem_rdy) is + when '1' => -- access granted + case to_x01(cpu_write) is + when '1' => fsm_ns <= READY; cpu_got <= '1'; -- write + when '0' => fsm_ns <= READING_MEM; -- read + when others => fsm_ns <= UNKNOWN; cpu_got <= 'X'; -- invalid input + end case; + + when '0' => null; -- still waiting + when others => fsm_ns <= UNKNOWN; -- invalid input + end case; + + + when READING_MEM => + -- Wait for incoming read data and write it to cache. + -- -------------------------------------------------- + cache_ReadWrite <= '1'; + + case to_x01(mem_rstb) is + when '1' => -- read data available + fsm_ns <= READY; + cpu_got <= '1'; -- cache access is complete now + cache_Replace <= '1'; -- replace cache line + -- The new data will be available on cache_LineOut in the following + -- clock cycle. + + when '0' => null;-- still waiting + when others => -- invalid input + fsm_ns <= UNKNOWN; + cpu_got <= 'X'; + cache_Replace <= 'X'; + end case; + + + when UNKNOWN => + -- Catches invalid state transitions. + -- ---------------------------------- + fsm_ns <= UNKNOWN; + cpu_got <= 'X'; + cache_Request <= 'X'; + cache_ReadWrite <= 'X'; + cache_Invalidate <= 'X'; + cache_Replace <= 'X'; + end case; + end process; + + process(clk) + begin + if rising_edge(clk) then + case to_x01(rst) is + when '1' => + fsm_cs <= READY; + when '0' => + fsm_cs <= fsm_ns; + when others => + fsm_cs <= UNKNOWN; + end case; + end if; + end process; + +end architecture rtl; diff --git a/src/cache/cache_mem.files b/src/cache/cache_mem.files new file mode 100644 index 00000000..92cb00d5 --- /dev/null +++ b/src/cache/cache_mem.files @@ -0,0 +1,16 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# ============================================================================== +# Note: all files are relative to PoC root directory +# +# Common PoC packages for configuration, synthesis and simulation +include "src/common/common.files" # load common packages + +# PoC.fifo +include "src/fifo/fifo_glue.files" +include "src/fifo/fifo_cc_got.files" + +# PoC.cache +include "src/cache/cache_cpu.files" # Embedded CPU Cache +vhdl poc "src/cache/cache_mem.vhdl" # Top Level diff --git a/src/cache/cache_mem.vhdl b/src/cache/cache_mem.vhdl new file mode 100644 index 00000000..f1a707f9 --- /dev/null +++ b/src/cache/cache_mem.vhdl @@ -0,0 +1,348 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Martin Zabel +-- +-- Entity: Cache with :ref:`INT:PoC.Mem` interface on the "CPU" side +-- +-- Description: +-- ------------------------------------- +-- This unit provides a cache (:ref:`IP:cache_par2`) together +-- with a cache controller which reads / writes cache lines from / to memory. +-- It has two :ref:`INT:PoC.Mem` interfaces: +-- +-- * one for the "CPU" side (ports with prefix ``cpu_``), and +-- * one for the memory side (ports with prefix ``mem_``). +-- +-- Thus, this unit can be placed into an already available memory path between +-- the CPU and the memory (controller). If you want to plugin a cache into a +-- CPU pipeline, see :ref:`IP:cache_cpu`. +-- +-- +-- Configuration +-- ************* +-- +-- +--------------------+-----------------------------------------------------+ +-- | Parameter | Description | +-- +====================+=====================================================+ +-- | REPLACEMENT_POLICY | Replacement policy of embedded cache. For supported | +-- | | values see PoC.cache_replacement_policy. | +-- +--------------------+-----------------------------------------------------+ +-- | CACHE_LINES | Number of cache lines. | +-- +--------------------+-----------------------------------------------------+ +-- | ASSOCIATIVITY | Associativity of embedded cache. | +-- +--------------------+-----------------------------------------------------+ +-- | CPU_ADDR_BITS | Number of address bits on the CPU side. Each address| +-- | | identifies one memory word as seen from the CPU. | +-- | | Calculated from other parameters as described below.| +-- +--------------------+-----------------------------------------------------+ +-- | CPU_DATA_BITS | Width of the data bus (in bits) on the CPU side. | +-- | | CPU_DATA_BITS must be divisible by 8. | +-- +--------------------+-----------------------------------------------------+ +-- | MEM_ADDR_BITS | Number of address bits on the memory side. Each | +-- | | address identifies one word in the memory. | +-- +--------------------+-----------------------------------------------------+ +-- | MEM_DATA_BITS | Width of a memory word and of a cache line in bits. | +-- | | MEM_DATA_BITS must be divisible by CPU_DATA_BITS. | +-- +--------------------+-----------------------------------------------------+ +-- | OUTSTANDING_REQ | Number of oustanding requests, see notes below. | +-- +--------------------+-----------------------------------------------------+ +-- +-- If the CPU data-bus width is smaller than the memory data-bus width, then +-- the CPU needs additional address bits to identify one CPU data word inside a +-- memory word. Thus, the CPU address-bus width is calculated from:: +-- +-- CPU_ADDR_BITS=log2ceil(MEM_DATA_BITS/CPU_DATA_BITS)+MEM_ADDR_BITS +-- +-- The write policy is: write-through, no-write-allocate. +-- +-- The maximum throughput is one request per clock cycle, except for +-- ``OUSTANDING_REQ = 1``. +-- +-- If ``OUTSTANDING_REQ`` is: +-- +-- * 1: then 1 request is buffered by a single register. To give a short +-- critical path (clock-to-output delay) for ``cpu_rdy``, the throughput is +-- degraded to one request per 2 clock cycles at maximum. +-- +-- * 2: then 2 requests are buffered by :ref:`IP:fifo_glue`. This setting has +-- the lowest area requirements without degrading the performance. +-- +-- * >2: then the requests are buffered by :ref:`IP:fifo_cc_got`. The number of +-- outstanding requests is rounded up to the next suitable value. This setting +-- is useful in applications with out-of-order execution (of other +-- operations). The CPU requests to the cache are always processed in-order. +-- +-- +-- Operation +-- ********* +-- +-- Memory accesses are always aligned to a word boundary. Each memory word +-- (and each cache line) consists of MEM_DATA_BITS bits. +-- For example if MEM_DATA_BITS=128: +-- +-- * memory address 0 selects the bits 0..127 in memory, +-- * memory address 1 selects the bits 128..256 in memory, and so on. +-- +-- Cache accesses are always aligned to a CPU word boundary. Each CPU word +-- consists of CPU_DATA_BITS bits. For example if CPU_DATA_BITS=32: +-- +-- * CPU address 0 selects the bits 0.. 31 in memory word 0, +-- * CPU address 1 selects the bits 32.. 63 in memory word 0, +-- * CPU address 2 selects the bits 64.. 95 in memory word 0, +-- * CPU address 3 selects the bits 96..127 in memory word 0, +-- * CPU address 4 selects the bits 0.. 31 in memory word 1, +-- * CPU address 5 selects the bits 32.. 63 in memory word 1, and so on. +-- +-- A synchronous reset must be applied even on a FPGA. +-- +-- The interface is documented in detail :ref:`here `. +-- +-- .. WARNING:: +-- +-- If the design is synthesized with Xilinx ISE / XST, then the synthesis +-- option "Keep Hierarchy" must be set to SOFT or TRUE. +-- +-- SeeAlso: +-- :ref:`IP:cache_cpu` +-- +-- License: +-- ============================================================================= +-- Copyright 2016-2016 Technische Universitaet Dresden - Germany +-- Chair of VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library poc; +use poc.utils.all; + +entity cache_mem is + generic ( + REPLACEMENT_POLICY : string := "LRU"; + CACHE_LINES : positive; + ASSOCIATIVITY : positive; + CPU_DATA_BITS : positive; + MEM_ADDR_BITS : positive; + MEM_DATA_BITS : positive; + OUTSTANDING_REQ : positive := 2 + ); + port ( + clk : in std_logic; -- clock + rst : in std_logic; -- reset + + -- "CPU" side + cpu_req : in std_logic; + cpu_write : in std_logic; + cpu_addr : in unsigned(log2ceil(MEM_DATA_BITS/CPU_DATA_BITS)+MEM_ADDR_BITS-1 downto 0); + cpu_wdata : in std_logic_vector(CPU_DATA_BITS-1 downto 0); + cpu_wmask : in std_logic_vector(CPU_DATA_BITS/8-1 downto 0) := (others => '0'); + cpu_rdy : out std_logic; + cpu_rstb : out std_logic; + cpu_rdata : out std_logic_vector(CPU_DATA_BITS-1 downto 0); + + -- Memory side + mem_req : out std_logic; + mem_write : out std_logic; + mem_addr : out unsigned(MEM_ADDR_BITS-1 downto 0); + mem_wdata : out std_logic_vector(MEM_DATA_BITS-1 downto 0); + mem_wmask : out std_logic_vector(MEM_DATA_BITS/8-1 downto 0); + mem_rdy : in std_logic; + mem_rstb : in std_logic; + mem_rdata : in std_logic_vector(MEM_DATA_BITS-1 downto 0) + ); +end entity; + +architecture rtl of cache_mem is + constant CPU_ADDR_BITS : positive := log2ceil(MEM_DATA_BITS/CPU_DATA_BITS)+MEM_ADDR_BITS; + + -- signals to internal cache_cpu + signal int_req : std_logic; + signal int_write : std_logic; + signal int_addr : unsigned(CPU_ADDR_BITS-1 downto 0); + signal int_wdata : std_logic_vector(CPU_DATA_BITS-1 downto 0); + signal int_wmask : std_logic_vector(CPU_DATA_BITS/8-1 downto 0); + signal int_got : std_logic; + signal int_rdata : std_logic_vector(CPU_DATA_BITS-1 downto 0); + +begin + + cache_cpu_inst: entity work.cache_cpu + generic map ( + REPLACEMENT_POLICY => REPLACEMENT_POLICY, + CACHE_LINES => CACHE_LINES, + ASSOCIATIVITY => ASSOCIATIVITY, + CPU_DATA_BITS => CPU_DATA_BITS, + MEM_ADDR_BITS => MEM_ADDR_BITS, + MEM_DATA_BITS => MEM_DATA_BITS) + port map ( + clk => clk, + rst => rst, + cpu_req => int_req, + cpu_write => int_write, + cpu_addr => int_addr, + cpu_wdata => int_wdata, + cpu_wmask => int_wmask, + cpu_got => int_got, + cpu_rdata => int_rdata, + mem_req => mem_req, + mem_write => mem_write, + mem_addr => mem_addr, + mem_wdata => mem_wdata, + mem_wmask => mem_wmask, + mem_rdy => mem_rdy, + mem_rstb => mem_rstb, + mem_rdata => mem_rdata); + + -- read data is valid one clock cycle after int_got is asserted + cpu_rstb <= (not rst) and (not int_write) and int_got when rising_edge(clk); + cpu_rdata <= int_rdata; -- already delayed by one clock cycle + + + ------------------------------------------------------------------------------ + g1: if OUTSTANDING_REQ = 1 generate + signal cpu_req_r : std_logic; + signal cpu_write_r : std_logic; + signal cpu_addr_r : unsigned(CPU_ADDR_BITS-1 downto 0); + signal cpu_wdata_r : std_logic_vector(CPU_DATA_BITS-1 downto 0); + signal cpu_wmask_r : std_logic_vector(CPU_DATA_BITS/8-1 downto 0); + signal cpu_rdy_r : std_logic; + signal cpu_rstb_r : std_logic; + signal cpu_rdata_r : std_logic_vector(CPU_DATA_BITS-1 downto 0); + begin + -- cpu_rdy should have a short clock-to-output delay, but int_got has a large + -- propagation delay. Thus, do not depend cpu_rdy and int_got. + -- This single entry FIFO stores a valid request if cpu_req_r = '1', + -- otherwise it is empty. + process(clk) + begin + if rising_edge(clk) then + -- store new request only if FIFO is empty + case to_x01(cpu_req_r) is + when '1' => null; -- FIFO is full + when '0' => + cpu_write_r <= cpu_write; + cpu_addr_r <= cpu_addr; + cpu_wdata_r <= cpu_wdata; + cpu_wmask_r <= cpu_wmask; + + when others => -- just for simulation + cpu_write_r <= 'X'; + cpu_addr_r <= (others => 'X'); + cpu_wdata_r <= (others => 'X'); + cpu_wmask_r <= (others => 'X'); + end case; + + -- FIFO state logic + case to_x01(rst) is + when '1' => cpu_req_r <= '0'; + when '0' => cpu_req_r <= + (cpu_req_r and not int_got) or -- keep if not yet acknowledged + (not cpu_req_r and cpu_req); -- or new request when empty + when others => cpu_req_r <= 'X'; + end case; + end if; + end process; + + cpu_rdy <= not cpu_req_r; -- ready when empty + + int_req <= cpu_req_r; + int_write <= cpu_write_r; + int_addr <= cpu_addr_r; + int_wdata <= cpu_wdata_r; + int_wmask <= cpu_wmask_r; + end generate g1; + + + ------------------------------------------------------------------------------ + g2: if OUTSTANDING_REQ = 2 generate + constant D_BITS : positive := CPU_DATA_BITS/8+CPU_DATA_BITS+CPU_ADDR_BITS+1; + + signal put : std_logic; + signal din : std_logic_vector(D_BITS-1 downto 0); + signal full : std_logic; + signal valid : std_logic; + signal dout : std_logic_vector(D_BITS-1 downto 0); + begin + req_fifo: entity work.fifo_glue + generic map ( + D_BITS => D_BITS) + port map ( + clk => clk, + rst => rst, + put => put, + di => din, + ful => full, + vld => valid, + do => dout, + got => int_got); + + din <= cpu_wmask & cpu_wdata & std_logic_vector(cpu_addr) & (0 downto 0 => cpu_write); + put <= cpu_req; + + int_req <= valid; + int_write <= dout(0); + int_addr <= unsigned(dout(CPU_ADDR_BITS+1-1 downto 1)); + int_wdata <= dout(CPU_DATA_BITS+CPU_ADDR_BITS+1-1 downto CPU_ADDR_BITS+1); + int_wmask <= dout(CPU_DATA_BITS/8+CPU_DATA_BITS+CPU_ADDR_BITS+1-1 downto CPU_DATA_BITS+CPU_ADDR_BITS+1); + + cpu_rdy <= not full; + end generate g2; + + + ------------------------------------------------------------------------------ + gt2: if OUTSTANDING_REQ > 2 generate + constant D_BITS : positive := CPU_DATA_BITS/8+CPU_DATA_BITS+CPU_ADDR_BITS+1; + + signal put : std_logic; + signal din : std_logic_vector(D_BITS-1 downto 0); + signal full : std_logic; + signal valid : std_logic; + signal dout : std_logic_vector(D_BITS-1 downto 0); + begin + req_fifo: entity work.fifo_cc_got + generic map ( + D_BITS => D_BITS, + MIN_DEPTH => OUTSTANDING_REQ, + DATA_REG => false, -- otherwise OUTPUT_REG has no effect + STATE_REG => true, + OUTPUT_REG => true) -- extra register required for optimal synthesis on Altera FPGAs + port map ( + rst => rst, + clk => clk, + put => put, + din => din, + full => full, + estate_wr => open, + got => int_got, + dout => dout, + valid => valid, + fstate_rd => open); + + din <= cpu_wmask & cpu_wdata & std_logic_vector(cpu_addr) & (0 downto 0 => cpu_write); + put <= cpu_req; + + int_req <= valid; + int_write <= dout(0); + int_addr <= unsigned(dout(CPU_ADDR_BITS+1-1 downto 1)); + int_wdata <= dout(CPU_DATA_BITS+CPU_ADDR_BITS+1-1 downto CPU_ADDR_BITS+1); + int_wmask <= dout(CPU_DATA_BITS/8+CPU_DATA_BITS+CPU_ADDR_BITS+1-1 downto CPU_DATA_BITS+CPU_ADDR_BITS+1); + + cpu_rdy <= not full; + end generate gt2; +end architecture rtl; diff --git a/src/cache/cache_par.vhdl b/src/cache/cache_par.vhdl index fc008b61..cfb90576 100644 --- a/src/cache/cache_par.vhdl +++ b/src/cache/cache_par.vhdl @@ -2,13 +2,23 @@ -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= --- Authors: Patrick Lehmann --- Martin Zabel +-- Authors: Patrick Lehmann +-- Martin Zabel -- --- Entity: Cache with parallel tag-unit and data memory. +-- Entity: Cache with parallel tag-unit and data memory. -- -- Description: -- ------------------------------------- +-- Implements a cache with parallel tag-unit and data memory. +-- +-- .. NOTE:: +-- This component infers a single-port memory with read-first behavior, that +-- is, upon writes the old-data is returned on the read output. Such memory +-- (e.g. LUT-RAM) is not available on all devices. Thus, synthesis may +-- infer a lot of flip-flops plus multiplexers instead, which is very inefficient. +-- It is recommended to use :doc:`PoC.cache.par2 ` instead which has a +-- slightly different interface. +-- -- All inputs are synchronous to the rising-edge of the clock `clock`. -- -- **Command truth table:** @@ -46,6 +56,11 @@ -- old content is outputed on ``CacheLineOut`` and the old tag on ``OldAddress``, -- both with a latency of one clock cycle. -- +-- .. WARNING:: +-- +-- If the design is synthesized with Xilinx ISE / XST, then the synthesis +-- option "Keep Hierarchy" must be set to SOFT or TRUE. +-- -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany @@ -136,7 +151,6 @@ begin Replace => Replace, ReplaceLineIndex => TU_ReplaceLineIndex, - NewAddress => Address, OldAddress => TU_OldAddress, Request => Request, diff --git a/src/cache/cache_par2.files b/src/cache/cache_par2.files new file mode 100644 index 00000000..eaf2fcc2 --- /dev/null +++ b/src/cache/cache_par2.files @@ -0,0 +1,19 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# ============================================================================== +# Note: all files are relative to PoC root directory +# +# Common PoC packages for configuration, synthesis and simulation +include "src/common/common.files" # load common packages + +# PoC.mem +include "src/mem/ocram/ocram_sp.files" + +# PoC.sort +include "src/sort/sort_lru_cache.files" + +# PoC.cache +vhdl poc "src/cache/cache_replacement_policy.vhdl" +vhdl poc "src/cache/cache_tagunit_par.vhdl" +vhdl poc "src/cache/cache_par2.vhdl" # Top Level diff --git a/src/cache/cache_par2.vhdl b/src/cache/cache_par2.vhdl new file mode 100644 index 00000000..25177658 --- /dev/null +++ b/src/cache/cache_par2.vhdl @@ -0,0 +1,253 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Martin Zabel +-- Patrick Lehmann +-- +-- Entity: Cache with parallel tag-unit and data memory. +-- +-- Description: +-- ------------------------------------- +-- Cache with parallel tag-unit and data memory. For the data memory, +-- :ref:`IP:ocram_sp` is used. +-- +-- Configuration +-- ************* +-- +-- +--------------------+----------------------------------------------------+ +-- | Parameter | Description | +-- +====================+====================================================+ +-- | REPLACEMENT_POLICY | Replacement policy. For supported policies see | +-- | | PoC.cache_replacement_policy. | +-- +--------------------+----------------------------------------------------+ +-- | CACHE_LINES | Number of cache lines. | +-- +--------------------+----------------------------------------------------+ +-- | ASSOCIATIVITY | Associativity of the cache. | +-- +--------------------+----------------------------------------------------+ +-- | ADDR_BITS | Number of address bits. Each address identifies | +-- | | exactly one cache line in memory. | +-- +--------------------+----------------------------------------------------+ +-- | DATA_BITS | Size of a cache line in bits. | +-- | | DATA_BITS must be divisible by 8. | +-- +--------------------+----------------------------------------------------+ +-- +-- +-- Command truth table +-- ******************* +-- +-- +---------+-----------+-------------+---------+---------------------------------+ +-- | Request | ReadWrite | Invalidate | Replace | Command | +-- +=========+===========+=============+=========+=================================+ +-- | 0 | 0 | 0 | 0 | None | +-- +---------+-----------+-------------+---------+---------------------------------+ +-- | 1 | 0 | 0 | 0 | Read cache line | +-- +---------+-----------+-------------+---------+---------------------------------+ +-- | 1 | 1 | 0 | 0 | Update cache line | +-- +---------+-----------+-------------+---------+---------------------------------+ +-- | 1 | 0 | 1 | 0 | Read cache line and discard it | +-- +---------+-----------+-------------+---------+---------------------------------+ +-- | 1 | 1 | 1 | 0 | Write cache line and discard it | +-- +---------+-----------+-------------+---------+---------------------------------+ +-- | 0 | 0 | 0 | 1 | Read cache line before replace. | +-- +---------+-----------+-------------+---------+---------------------------------+ +-- | 0 | 1 | 0 | 1 | Replace cache line. | +-- +---------+-----------+-------------+---------+---------------------------------+ +-- +-- +-- Operation +-- ********* +-- +-- All inputs are synchronous to the rising-edge of the clock `clock`. +-- +-- All commands use ``Address`` to lookup (request) or replace a cache line. +-- ``Address`` and ``OldAddress`` do not include the word/byte select part. +-- Each command is completed within one clock cycle, but outputs are delayed as +-- described below. +-- +-- Upon requests, the outputs ``CacheMiss`` and ``CacheHit`` indicate (high-active) +-- whether the ``Address`` is stored within the cache, or not. Both outputs have a +-- latency of one clock cycle (pipelined) if ``HIT_MISS_REG`` is true, otherwise the +-- result is outputted immediately (combinational). +-- +-- Upon writing a cache line, the new content is given by ``CacheLineIn``. +-- Only the bytes which are not masked, i.e. the corresponding bit in WriteMask +-- is '0', are actually written. +-- +-- Upon reading a cache line, the current content is outputed on ``CacheLineOut`` +-- with a latency of one clock cycle. +-- +-- Replacing a cache line requires two steps, both with ``Replace = '1'``: +-- +-- 1. Read old contents of cache line by setting ``ReadWrite`` to '0'. The old +-- content is outputed on ``CacheLineOut`` and the old tag on ``OldAddress``, +-- both with a latency of one clock cycle. +-- +-- 2. Write new cache line by setting ``ReadWrite`` to '1'. The new content is +-- given by ``CacheLineIn``. All bytes shall be written, i.e. +-- ``WriteMask = 0``. The new cache line content will be outputed +-- again on ``CacheLineOut`` in the next clock cycle (latency = 1). +-- +-- .. WARNING:: +-- +-- If the design is synthesized with Xilinx ISE / XST, then the synthesis +-- option "Keep Hierarchy" must be set to SOFT or TRUE. +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany +-- Chair of VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +library PoC; +use PoC.utils.all; +use PoC.vectors.all; + + +entity cache_par2 is + generic ( + REPLACEMENT_POLICY : string := "LRU"; + CACHE_LINES : positive := 32; + ASSOCIATIVITY : positive := 32; + ADDR_BITS : positive := 8; + DATA_BITS : positive := 8; + HIT_MISS_REG : boolean := true -- must be true for Cocotb. + ); + port ( + Clock : in std_logic; + Reset : in std_logic; + + Request : in std_logic; + ReadWrite : in std_logic; + WriteMask : in std_logic_vector(DATA_BITS/8 - 1 downto 0) := (others => '0'); + Invalidate : in std_logic; + Replace : in std_logic; + Address : in std_logic_vector(ADDR_BITS-1 downto 0); + + CacheLineIn : in std_logic_vector(DATA_BITS - 1 downto 0); + CacheLineOut : out std_logic_vector(DATA_BITS - 1 downto 0); + CacheHit : out std_logic := '0'; + CacheMiss : out std_logic := '0'; + OldAddress : out std_logic_vector(ADDR_BITS-1 downto 0) + ); +end entity; + + +architecture rtl of cache_par2 is + attribute KEEP : boolean; + + constant LINE_INDEX_BITS : positive := log2ceilnz(CACHE_LINES); + + subtype T_CACHE_LINE is std_logic_vector(DATA_BITS - 1 downto 0); + type T_CACHE_LINE_VECTOR is array (natural range <>) of T_CACHE_LINE; + + -- look-up (request) + signal TU_LineIndex : std_logic_vector(LINE_INDEX_BITS - 1 downto 0); + signal TU_TagHit : std_logic; + signal TU_TagMiss : std_logic; + + -- replace + signal ReplaceWrite : std_logic; + signal TU_ReplaceLineIndex : std_logic_vector(LINE_INDEX_BITS - 1 downto 0); + signal TU_OldAddress : std_logic_vector(OldAddress'range); + + -- data memory + signal MemoryIndex_us : unsigned(LINE_INDEX_BITS - 1 downto 0); + signal MemoryAccess : std_logic; + +begin + + ReplaceWrite <= Replace and ReadWrite; + + -- Cache TagUnit + TU : entity PoC.cache_tagunit_par + generic map ( + REPLACEMENT_POLICY => REPLACEMENT_POLICY, + CACHE_LINES => CACHE_LINES, + ASSOCIATIVITY => ASSOCIATIVITY, + ADDRESS_BITS => ADDR_BITS + ) + port map ( + Clock => Clock, + Reset => Reset, + + Replace => ReplaceWrite, + ReplaceLineIndex => TU_ReplaceLineIndex, + OldAddress => TU_OldAddress, + + Request => Request, + ReadWrite => ReadWrite, + Invalidate => Invalidate, + Address => Address, + LineIndex => TU_LineIndex, + TagHit => TU_TagHit, + TagMiss => TU_TagMiss + ); + + -- Address selector + MemoryIndex_us <= unsigned(TU_LineIndex) when Request = '1' else + unsigned(TU_ReplaceLineIndex); + + MemoryAccess <= (Request and TU_TagHit) or Replace; + + -- Data Memory + gLane: for i in 0 to DATA_BITS/8 - 1 generate + signal we : std_logic; + begin + we <= ReadWrite and not WriteMask(i); + + data_mem: entity work.ocram_sp + generic map ( + A_BITS => LINE_INDEX_BITS, + D_BITS => 8, -- 8 bit per lane + FILENAME => "") + port map ( + clk => Clock, + ce => MemoryAccess, + we => we, + a => MemoryIndex_us, + d => CacheLineIn (i*8+7 downto i*8), + q => CacheLineOut(i*8+7 downto i*8)); + end generate gLane; + + -- Hit / Miss + gNoHitMissReg: if not HIT_MISS_REG generate + CacheMiss <= TU_TagMiss; + CacheHit <= TU_TagHit; + end generate gNoHitMissReg; + + gHitMissReg: if HIT_MISS_REG generate -- Pipelined outputs. + process(Clock) + begin + if rising_edge(Clock) then + if Reset = '1' then + CacheMiss <= '0'; + CacheHit <= '0'; + else + CacheMiss <= TU_TagMiss; + CacheHit <= TU_TagHit; + end if; + end if; + end process; + end generate gHitMissReg; + + -- Same latency as CacheLineOut + OldAddress <= TU_OldAddress when rising_edge(Clock); + +end architecture; diff --git a/src/cache/cache_tagunit_par.vhdl b/src/cache/cache_tagunit_par.vhdl index 3b2c11ea..a42ebc65 100644 --- a/src/cache/cache_tagunit_par.vhdl +++ b/src/cache/cache_tagunit_par.vhdl @@ -9,9 +9,28 @@ -- -- Description: -- ------------------------------------- --- All inputs are synchronous to the rising-edge of the clock ``clock``. +-- Tag-unit with fully-parallel compare of tag. -- --- **Command thruth table:** +-- Configuration +-- ************* +-- +-- +--------------------+----------------------------------------------------+ +-- | Parameter | Description | +-- +====================+====================================================+ +-- | REPLACEMENT_POLICY | Replacement policy. For supported policies see | +-- | | PoC.cache_replacement_policy. | +-- +--------------------+----------------------------------------------------+ +-- | CACHE_LINES | Number of cache lines. | +-- +--------------------+----------------------------------------------------+ +-- | ASSOCIATIVITY | Associativity of the cache. | +-- +--------------------+----------------------------------------------------+ +-- | ADDRESS_BITS | Number of address bits. Each address identifies | +-- | | exactly one cache line in memory. | +-- +--------------------+----------------------------------------------------+ +-- +-- +-- Command truth table +-- ******************* -- -- +---------+-----------+-------------+---------+----------------------------------+ -- | Request | ReadWrite | Invalidate | Replace | Command | @@ -29,6 +48,12 @@ -- | 0 | | 0 | 1 | Replace cache line. | -- +---------+-----------+-------------+---------+----------------------------------+ -- +-- +-- Operation +-- ********* +-- +-- All inputs are synchronous to the rising-edge of the clock `clock`. +-- -- All commands use ``Address`` to lookup (request) or replace a cache line. -- Each command is completed within one clock cycle. -- @@ -39,13 +64,27 @@ -- -- The output ``ReplaceLineIndex`` indicates which cache line will be replaced as -- next by a replace command. The output ``OldAddress`` specifies the old tag stored at this --- index. The replace command will store the ``NewAddress`` and update the cache-line +-- index. The replace command will store the ``Address`` and update the cache-line -- usage at the rising-edge of the clock. -- -- For a direct-mapped cache, the number of ``CACHE_LINES`` must be a power of 2. -- For a set-associative cache, the expression ``CACHE_LINES / ASSOCIATIVITY`` -- must be a power of 2. -- +-- .. NOTE:: +-- The port ``NewAddress`` has been removed. Use ``Address`` instead as +-- described above. +-- +-- If ``Address`` is fed from a register and an Altera FPGA is used, then +-- Quartus Map converts the tag memory from a memory with asynchronous read to a +-- memory with synchronous read by adding a pass-through logic. Quartus Map +-- reports warning 276020 which is intended. +-- +-- .. WARNING:: +-- +-- If the design is synthesized with Xilinx ISE / XST, then the synthesis +-- option "Keep Hierarchy" must be set to SOFT or TRUE. +-- -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany @@ -77,7 +116,7 @@ entity cache_tagunit_par is REPLACEMENT_POLICY : string := "LRU"; CACHE_LINES : positive := 32; ASSOCIATIVITY : positive := 32; - ADDRESS_BITS : positive := 8 + ADDRESS_BITS : positive := 8 ); port ( Clock : in std_logic; @@ -85,7 +124,6 @@ entity cache_tagunit_par is Replace : in std_logic; ReplaceLineIndex : out std_logic_vector(log2ceilnz(CACHE_LINES) - 1 downto 0); - NewAddress : in std_logic_vector(ADDRESS_BITS - 1 downto 0); OldAddress : out std_logic_vector(ADDRESS_BITS - 1 downto 0); Request : in std_logic; @@ -103,6 +141,19 @@ architecture rtl of cache_tagunit_par is constant SETS : positive := CACHE_LINES / ASSOCIATIVITY; + -- Returns true if unsigned value contains metalogical values. + -- Similar function is_x(unsigned) is only shipped with VHDL'08. + function contains_x(value : unsigned) return boolean is + begin + -- Use pragma to get rid of meaningless Quartus warning 10325 "ignored + -- choice containing meta-values ..." in function is_x(std_logic_vector). + -- Synthesis tools which ignore this pragma should return false for is_x(). + -- synthesis translate_off + return is_x(std_logic_vector(value)); + -- synthesis translate_on + return false; -- no meta-values in hardware here + end function; + begin -- =========================================================================== -- Full-Associative Cache @@ -146,7 +197,7 @@ begin begin if rising_edge(Clock) then if (Replace = '1') then - TagMemory(to_integer(ReplaceWay_us)) <= NewAddress; + TagMemory(to_integer(ReplaceWay_us)) <= Address; end if; for i in ValidMemory'range loop @@ -172,7 +223,8 @@ begin ReplaceWay_us <= unsigned(Policy_ReplaceWay); ReplaceLineIndex <= Policy_ReplaceWay; - OldAddress <= TagMemory(to_integer(ReplaceWay_us)); + OldAddress <= (others => 'X') when contains_x(ReplaceWay_us) else + TagMemory(to_integer(ReplaceWay_us)); -- replacement policy Policy : entity PoC.cache_replacement_policy @@ -207,47 +259,61 @@ begin signal Address_Tag : T_TAG_LINE; signal Address_Index : unsigned(INDEX_BITS - 1 downto 0); - signal NewAddress_Tag : T_TAG_LINE; - signal NewAddress_Index : unsigned(INDEX_BITS - 1 downto 0); signal DM_TagHit : std_logic; -- includes Valid signal TagMemory : T_TAG_LINE_VECTOR(CACHE_LINES-1 downto 0); signal ValidMemory : std_logic_vector(CACHE_LINES-1 downto 0) := (others => '0'); - signal ValidUpdateIndex : unsigned(INDEX_BITS-1 downto 0); + -- If Address is fed from a register, then: + -- + -- * the TagMemory must be implemented as distributed RAM on Xilinx + -- FPGAs because only this RAM has the intended mixed-port + -- read-during-write behavior. But even if ``ram_style`` is set, + -- synthesis sometimes generates a wrong netlist if KEEP_HIERARCHY is + -- set to off (default). + -- + -- * Mapping the TagMemory to block RAM is however possible on Altera + -- FPGAs because Quartus adds the neccessary bypass logic. + -- + -- If Address is not fed from a register, then: + -- + -- * distributed RAM will be used on Xilinx FPGAs anyway, + -- * LUTs and FFs are used on Altera FPGAs. + attribute ram_style : string; -- XST specific + attribute ram_style of TagMemory : signal is "distributed"; signal TagHit_i : std_logic; signal TagMiss_i : std_logic; + signal Tag : T_TAG_LINE; -- read tag from memory + signal Valid : std_logic; -- read valid from memory + begin assert CACHE_LINES = 2**INDEX_BITS report "Unsupported number of cache lines." severity failure; - -- Split incoming 'Address' and 'NewAddress' + -- Split incoming 'Address' Address_Tag <= Address(Address'left downto INDEX_BITS); Address_Index <= unsigned(Address(INDEX_BITS-1 downto 0)); - NewAddress_Tag <= NewAddress(NewAddress'left downto INDEX_BITS); - NewAddress_Index <= unsigned(NewAddress(INDEX_BITS-1 downto 0)); - - -- access tag memory and compare tags / valids - DM_TagHit <= to_sl(TagMemory (to_integer(Address_Index)) = Address_Tag and - ValidMemory(to_integer(Address_Index)) = '1'); - -- index for writing into ValidMemory - ValidUpdateIndex <= NewAddress_Index when Replace = '1' else - Address_Index; + -- Access tag / valid memory and compare tags. + Tag <= (others => 'X') when contains_x(Address_Index) else + TagMemory (to_integer(Address_Index)); + Valid <= 'X' when contains_x(Address_Index) else + ValidMemory(to_integer(Address_Index)); + DM_TagHit <= to_sl(Tag = Address_Tag) and Valid; process(Clock) begin if rising_edge(Clock) then if (Replace = '1') then - TagMemory(to_integer(NewAddress_Index)) <= NewAddress_Tag; + TagMemory(to_integer(Address_Index)) <= Address_Tag; end if; if Reset = '1' then ValidMemory <= (others => '0'); elsif (Replace = '1') or (TagHit_i = '1' and Invalidate = '1') then - ValidMemory(to_integer(ValidUpdateIndex)) <= Replace; -- clear when Invalidate + ValidMemory(to_integer(Address_Index)) <= Replace; -- clear when Invalidate end if; end if; end process; @@ -261,8 +327,8 @@ begin TagHit <= TagHit_i; TagMiss <= TagMiss_i; - ReplaceLineIndex <= std_logic_vector(NewAddress_Index); - OldAddress <= TagMemory(to_integer(NewAddress_Index)) & std_logic_vector(NewAddress_Index); + ReplaceLineIndex <= std_logic_vector(Address_Index); + OldAddress <= Tag & std_logic_vector(Address_Index); end generate; -- =========================================================================== @@ -283,8 +349,6 @@ begin -- Splitted address signal Address_Tag : T_TAG_LINE; signal Address_Index : unsigned(INDEX_BITS - 1 downto 0); - signal NewAddress_Tag : T_TAG_LINE; - signal NewAddress_Index : unsigned(INDEX_BITS - 1 downto 0); -- Way-specific signals signal TagHits : std_logic_vector(ASSOCIATIVITY-1 downto 0); -- includes Valid @@ -308,13 +372,11 @@ begin assert CACHE_SETS = 2**INDEX_BITS report "Unsupported number of cache-sets." severity failure; ---------------------------------------------------------------------------- - -- Split incoming 'Address' and 'NewAddress' + -- Split incoming 'Address' -- Enable only one cache-set ---------------------------------------------------------------------------- Address_Tag <= Address(Address'left downto INDEX_BITS); Address_Index <= unsigned(Address(INDEX_BITS-1 downto 0)); - NewAddress_Tag <= NewAddress(NewAddress'left downto INDEX_BITS); - NewAddress_Index <= unsigned(NewAddress(INDEX_BITS-1 downto 0)); ---------------------------------------------------------------------------- -- Generate tag-memory and comparators for each way @@ -323,23 +385,48 @@ begin genWay : for way in 0 to ASSOCIATIVITY-1 generate signal TagMemory : T_TAG_LINE_VECTOR(CACHE_SETS-1 downto 0); signal ValidMemory : std_logic_vector(CACHE_SETS-1 downto 0) := (others => '0'); + + -- If Address is fed from a register, then: + -- + -- * the TagMemory must be implemented as distributed RAM on Xilinx + -- FPGAs because only this RAM has the intended mixed-port + -- read-during-write behavior. But even if ``ram_style`` is set, + -- synthesis sometimes generates a wrong netlist if KEEP_HIERARCHY is + -- set to off (default). + -- + -- * Mapping the TagMemory to block RAM is however possible on Altera + -- FPGAs because Quartus adds the neccessary bypass logic. + -- + -- If Address is not fed from a register, then: + -- + -- * distributed RAM will be used on Xilinx FPGAs anyway, + -- * LUTs and FFs are used on Altera FPGAs. + attribute ram_style : string; -- XST specific + attribute ram_style of TagMemory : signal is "distributed"; + + signal Tag : T_TAG_LINE; -- read tag from memory + signal Valid : std_logic; -- read valid from memory begin - -- comparator - TagHits(way) <= to_sl(TagMemory (to_integer(Address_Index)) = Address_Tag and - ValidMemory(to_integer(Address_Index)) = '1'); + -- Access tag / valid memory and compare tags. + Tag <= (others => 'X') when contains_x(Address_Index) else + TagMemory (to_integer(Address_Index)); + Valid <= 'X' when contains_x(Address_Index) else + ValidMemory(to_integer(Address_Index)); + + TagHits(way) <= to_sl(Tag = Address_Tag) and Valid; -- memory update process (Clock) is begin -- process if rising_edge(Clock) then if Replace = '1' and ReplaceWay = way then - TagMemory(to_integer(NewAddress_Index)) <= NewAddress_Tag; + TagMemory(to_integer(Address_Index)) <= Address_Tag; end if; if Reset = '1' then ValidMemory <= (others => '0'); elsif Replace = '1' and ReplaceWay = way then - ValidMemory(to_integer(NewAddress_Index)) <= '1'; + ValidMemory(to_integer(Address_Index)) <= '1'; elsif Invalidate = '1' and TagHits(way) = '1' then ValidMemory(to_integer(Address_Index)) <= '0'; end if; @@ -347,7 +434,7 @@ begin end process; -- old address when replacing - OldTags(way) <= TagMemory(to_integer(NewAddress_Index)); + OldTags(way) <= Tag; end generate genWay; HitWay <= onehot2bin(TagHits, 0); @@ -365,18 +452,34 @@ begin ---------------------------------------------------------------------------- -- Generate policy for each cache-set ---------------------------------------------------------------------------- - process(Address_Index, TagHit_i, Invalidate) + process(Address_Index, TagHit_i) begin CS_TagAccess <= (others => '0'); - CS_TagAccess(to_integer(Address_Index)) <= TagHit_i; + if contains_x(Address_Index) then -- for simulation only + null;--TODO: CS_TagAccess <= (others => 'X'); + else + CS_TagAccess(to_integer(Address_Index)) <= TagHit_i; + end if; + end process; + + process(Address_Index, Invalidate) + begin CS_Invalidate <= (others => '0'); - CS_Invalidate(to_integer(Address_Index)) <= Invalidate; + if contains_x(Address_Index) then -- for simulation only + null;--TODO: CS_Invalidate <= (others => 'X'); + else + CS_Invalidate(to_integer(Address_Index)) <= Invalidate; + end if; end process; - process(NewAddress_Index, Replace) + process(Address_Index, Replace) begin CS_Replace <= (others => '0'); - CS_Replace(to_integer(NewAddress_Index)) <= Replace; + if contains_x(Address_Index) then -- for simulation only + null;--TODO: CS_Replace <= (others => 'X'); + else + CS_Replace(to_integer(Address_Index)) <= Replace; + end if; end process; genSet : for cs in 0 to CACHE_SETS-1 generate @@ -400,13 +503,15 @@ begin ); end generate genSet; - ReplaceWay <= unsigned(Policy_ReplaceWay(to_integer(NewAddress_Index))); + ReplaceWay <= (others => 'X') when contains_x(Address_Index) else + unsigned(Policy_ReplaceWay(to_integer(Address_Index))); ---------------------------------------------------------------------------- -- Replace-specific outputs ---------------------------------------------------------------------------- - ReplaceLineIndex <= std_logic_vector(ReplaceWay) & std_logic_vector(NewAddress_Index); - OldAddress <= OldTags(to_integer(ReplaceWay)) & std_logic_vector(NewAddress_Index); + ReplaceLineIndex <= std_logic_vector(ReplaceWay) & std_logic_vector(Address_Index); + OldAddress <= (others => 'X') when contains_x(ReplaceWay) else + OldTags(to_integer(ReplaceWay)) & std_logic_vector(Address_Index); end generate; end architecture; diff --git a/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl b/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl index 8f1e1dd0..a0136a0b 100644 --- a/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl +++ b/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl @@ -72,6 +72,7 @@ entity ddr2_mem2mig_adapter_Spartan6 is mem_write : in std_logic; mem_addr : in unsigned(MEM_A_BITS-1 downto 0); mem_wdata : in std_logic_vector(D_BITS-1 downto 0); + mem_wmask : in std_logic_vector(D_BITS/8-1 downto 0) := (others => '0'); mem_rdy : out std_logic; mem_rstb : out std_logic; mem_rdata : out std_logic_vector(D_BITS-1 downto 0); @@ -120,7 +121,7 @@ begin -- architecture rtl -- write data & mask mig_wr_data <= mem_wdata; - mig_wr_mask <= (others => '0'); -- all bytes + mig_wr_mask <= mem_wmask; -- read reply mig_rd_en <= not mig_rd_empty; diff --git a/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl b/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl index cb8b6d5a..b9c3c1c6 100644 --- a/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl +++ b/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl @@ -68,13 +68,14 @@ entity ddr3_mem2mig_adapter_Series7 is port ( -- PoC.Mem interface - mem_req : in std_logic; - mem_write : in std_logic; - mem_addr : in unsigned(MEM_A_BITS-1 downto 0); - mem_wdata : in std_logic_vector(D_BITS-1 downto 0); - mem_rdy : out std_logic; - mem_rstb : out std_logic; - mem_rdata : out std_logic_vector(D_BITS-1 downto 0); + mem_req : in std_logic; + mem_write : in std_logic; + mem_addr : in unsigned(MEM_A_BITS-1 downto 0); + mem_wdata : in std_logic_vector(D_BITS-1 downto 0); + mem_wmask : in std_logic_vector(D_BITS/8-1 downto 0) := (others => '0'); + mem_rdy : out std_logic; + mem_rstb : out std_logic; + mem_rdata : out std_logic_vector(D_BITS-1 downto 0); -- Xilinx MIG IP Core interface init_calib_complete : in std_logic; @@ -123,7 +124,7 @@ begin -- architecture rtl -- write data & mask app_wdf_data <= mem_wdata; - app_wdf_mask <= (others => '0'); -- all bytes + app_wdf_mask <= mem_wmask; -- read reply mem_rstb <= app_rd_data_valid; diff --git a/tb/cache/cache_cpu_tb.files b/tb/cache/cache_cpu_tb.files new file mode 100644 index 00000000..e5c721d7 --- /dev/null +++ b/tb/cache/cache_cpu_tb.files @@ -0,0 +1,15 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# ============================================================================== +# Note: all files are relative to PoC root directory +# +# PoC.cache +include "src/cache/cache_cpu.files" # UUT (Unit Under Test) + +# PoC.arith +include "src/arith/arith_prng.files" + +# Testbench files +vhdl test "tb/mem/mem_model.vhdl" # Memory Model +vhdl test "tb/cache/cache_cpu_tb.vhdl" # Testbench diff --git a/tb/cache/cache_cpu_tb.vhdl b/tb/cache/cache_cpu_tb.vhdl new file mode 100644 index 00000000..22beed54 --- /dev/null +++ b/tb/cache/cache_cpu_tb.vhdl @@ -0,0 +1,450 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================ +-- Authors: Martin Zabel +-- +-- Testbench: Testbench for cache_cpu. +-- +-- Description: +-- ------------------------------------ +-- Test cache_cpu using two memories. One connected behind the cache, and one +-- directly attached to the CPU. The CPU compares the result of read requests +-- issued to the cache with the result from the direct attached memory. +-- +-- CPU ---+--- Cache (UUT) ---- 1st memory +-- | +-- +--- 2nd memory +-- +-- License: +-- ============================================================================ +-- Copyright 2016-2016 Technische Universitaet Dresden - Germany, +-- Chair of VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +library poc; +use poc.utils.all; +use poc.physical.all; +-- simulation only packages +use poc.sim_types.all; +use poc.simulation.all; +use poc.waveform.all; + +entity cache_cpu_tb is +end entity cache_cpu_tb; + +architecture sim of cache_cpu_tb is + constant CLOCK_FREQ : FREQ := 100 MHz; + + -- Cache configuration + constant REPLACEMENT_POLICY : string := "LRU"; + constant CACHE_LINES : positive := 32; + constant ASSOCIATIVITY : positive := 4; + + -- Memory configuration + constant MEM_ADDR_BITS : positive := 6; + constant MEM_DATA_BITS : positive := 128; + + -- NOTE: + -- Memory accesses are always aligned to a word boundary. Each memory word + -- (and each cache line) consists of MEM_DATA_BITS bits. + -- For example if MEM_DATA_BITS=128: + -- + -- * memory address 0 selects the bits 0..127 in memory, + -- * memory address 1 selects the bits 128..256 in memory, and so on. + + -- CPU configuration + constant CPU_DATA_BITS : positive := 32; + constant CPU_ADDR_BITS : positive := log2ceil(MEM_DATA_BITS/CPU_DATA_BITS)+MEM_ADDR_BITS; + constant MEMORY_WORDS : positive := 2**CPU_ADDR_BITS; + constant BYTES_PER_WORD : positive := CPU_DATA_BITS/8; + + -- NOTE: + -- Cache accesses are always aligned to a CPU word boundary. Each CPU word + -- consists of CPU_DATA_BITS bits. For example if CPU_DATA_BITS=32: + -- + -- * CPU address 0 selects the bits 0.. 31 in memory word 0, + -- * CPU address 1 selects the bits 32.. 63 in memory word 0, + -- * CPU address 2 selects the bits 64.. 95 in memory word 0, + -- * CPU address 3 selects the bits 96..127 in memory word 0, + -- * CPU address 4 selects the bits 0.. 31 in memory word 1, + -- * CPU address 5 selects the bits 32.. 63 in memory word 1, and so on. + + -- Global signals + signal clk : std_logic := '1'; + signal rst : std_logic; + + -- Request from CPU + signal cpu_req : std_logic; + signal cpu_write : std_logic; + signal cpu_addr : unsigned(CPU_ADDR_BITS-1 downto 0); + signal cpu_wdata : std_logic_vector(CPU_DATA_BITS-1 downto 0); + signal cpu_wmask : std_logic_vector(CPU_DATA_BITS/8-1 downto 0); + signal cpu_got : std_logic; + + -- Bus between CPU and Cache + -- write / addr / wdata are directly connected to the CPU + signal cache_req : std_logic; + signal cache_rstb : std_logic; + signal cache_rdata : std_logic_vector(CPU_DATA_BITS-1 downto 0); + + -- Bus between Cache and 1st Memory + signal mem1_req : std_logic; + signal mem1_write : std_logic; + signal mem1_addr : unsigned(MEM_ADDR_BITS-1 downto 0); + signal mem1_wdata : std_logic_vector(MEM_DATA_BITS-1 downto 0); + signal mem1_wmask : std_logic_vector(MEM_DATA_BITS/8-1 downto 0); + signal mem1_rdy : std_logic; + signal mem1_rstb : std_logic; + signal mem1_rdata : std_logic_vector(MEM_DATA_BITS-1 downto 0); + + -- Bus between CPU and 2nd Memory + -- write / addr / wdata are directly connected to the CPU + signal mem2_req : std_logic; + signal mem2_rdy : std_logic; + signal mem2_rstb : std_logic; + signal mem2_rdata : std_logic_vector(CPU_DATA_BITS-1 downto 0); + + -- Write-Data Generator + signal wdata_got : std_logic; + signal wdata_val : std_logic_vector(CPU_DATA_BITS-1 downto 0); + + -- Control signals between Request Generator and Checker of CPU + signal finished : boolean := false; + +begin + -- initialize global simulation status + simInitialize; + -- generate global testbench clock + simGenerateClock(clk, CLOCK_FREQ); + + -- The Cache + UUT: entity poc.cache_cpu + generic map ( + REPLACEMENT_POLICY => REPLACEMENT_POLICY, + CACHE_LINES => CACHE_LINES, + ASSOCIATIVITY => ASSOCIATIVITY, + CPU_DATA_BITS => CPU_DATA_BITS, + MEM_ADDR_BITS => MEM_ADDR_BITS, + MEM_DATA_BITS => MEM_DATA_BITS) + port map ( + clk => clk, + rst => rst, + cpu_req => cache_req, + cpu_write => cpu_write, + cpu_addr => cpu_addr, + cpu_wdata => cpu_wdata, + cpu_wmask => cpu_wmask, + cpu_got => cpu_got, + cpu_rdata => cache_rdata, + mem_req => mem1_req, + mem_write => mem1_write, + mem_addr => mem1_addr, + mem_wdata => mem1_wdata, + mem_wmask => mem1_wmask, + mem_rdy => mem1_rdy, + mem_rstb => mem1_rstb, + mem_rdata => mem1_rdata); + + -- request only if also 2nd memory is ready + cache_req <= cpu_req and mem2_rdy; + + -- read data is valid one clock cycle after cpu_got si asserted + cache_rstb <= (not rst) and (not cpu_write) and cpu_got when rising_edge(clk); + + -- The 1st Memory + memory1: entity work.mem_model + generic map ( + A_BITS => MEM_ADDR_BITS, + D_BITS => MEM_DATA_BITS) + port map ( + clk => clk, + rst => rst, + mem_req => mem1_req, + mem_write => mem1_write, + mem_addr => mem1_addr, + mem_wdata => mem1_wdata, + mem_wmask => mem1_wmask, + mem_rdy => mem1_rdy, + mem_rstb => mem1_rstb, + mem_rdata => mem1_rdata); + + -- The 2nd Memory + memory2: entity work.mem_model + generic map ( + A_BITS => CPU_ADDR_BITS, + D_BITS => CPU_DATA_BITS) + port map ( + clk => clk, + rst => rst, + mem_req => mem2_req, + mem_write => cpu_write, + mem_addr => cpu_addr, + mem_wdata => cpu_wdata, + mem_wmask => cpu_wmask, + mem_rdy => mem2_rdy, + mem_rstb => mem2_rstb, + mem_rdata => mem2_rdata); + + -- request only if request is acknowledged by cache + mem2_req <= cpu_got; + + -- The Write-Data Generator of the CPU + wdata_prng: entity poc.arith_prng + generic map (BITS => CPU_DATA_BITS) + port map ( + clk => clk, + rst => rst, + got => wdata_got, + val => wdata_val); + + cpu_wdata <= wdata_val when cpu_write = '1' else (others => '-'); + wdata_got <= cpu_write and cpu_got and mem2_rdy; + + -- The Request Generator of the CPU + CPU_RequestGen: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("CPU RequestGen"); + + -- no operation + procedure nop is + begin + cpu_req <= '0'; + cpu_write <= '-'; + cpu_addr <= (others => '-'); + cpu_wmask <= (others => '-'); + wait until rising_edge(clk); + end procedure; + + -- Write random data at given word address. + -- Waits until cache and 2nd memory are ready. + procedure write( + addr : in natural; + wmask : in std_logic_vector(BYTES_PER_WORD-1 downto 0) := (others => '0') + ) is + begin + -- apply request (will be ignored if not ready) + cpu_req <= '1'; + cpu_write <= '1'; + cpu_addr <= to_unsigned(addr, CPU_ADDR_BITS); + cpu_wmask <= wmask; + while true loop + wait until rising_edge(clk); + exit when cpu_got = '1'; + end loop; + end procedure; + + -- Write single byte of random data at given word address. + -- Waits until cache and 2nd memory are ready. + procedure write_byte( + word_addr : in natural; + byte_addr : in natural range 0 to BYTES_PER_WORD-1 + ) is + variable mask : std_logic_vector(BYTES_PER_WORD-1 downto 0); + begin + mask := (others => '1'); + mask(byte_addr) := '0'; + write(word_addr, mask); + end procedure; + + -- Read at given word address. + -- Waits until cache and 2nd memory are ready. + procedure read(addr : in natural) is + begin + -- apply request (will be ignored if not ready) + cpu_req <= '1'; + cpu_write <= '0'; + cpu_addr <= to_unsigned(addr, CPU_ADDR_BITS); + cpu_wmask <= (others => '-'); + while true loop + wait until rising_edge(clk); + exit when cpu_got = '1'; + end loop; + end procedure; + + -- Seeds for random request generation + variable seed1 : positive := 1; + variable seed2 : positive := 1; + + variable temp_r : real; + variable temp_r2: real; + + begin + -- Reset is mandatory + rst <= '1'; + wait until rising_edge(clk); + rst <= '0'; + + -- Check No Operation + -- -------------------------------------------- + for i in 0 to 3 loop nop; end loop; + + -- Fill memory with valid data and read it back + -- -------------------------------------------- + -- Due to the No-Write-Allocate policy no cache hit occurs. + + -- Write / read whole word + -- *********************** + for addr in 0 to MEMORY_WORDS-1 loop + write(addr); + end loop; -- addr + for addr in 0 to MEMORY_WORDS-1 loop + read(addr); + end loop; -- addr + for i in 0 to 3 loop nop; end loop; + + -- Write single bytes, read whole word + -- *********************************** + for word_addr in 0 to MEMORY_WORDS-1 loop + for byte_addr in 0 to BYTES_PER_WORD-1 loop + write_byte(word_addr, byte_addr); + end loop; + end loop; -- addr + for addr in 0 to MEMORY_WORDS-1 loop + read(addr); + end loop; -- addr + for i in 0 to 3 loop nop; end loop; + + -- Linear access, read/write/read at every address + -- ----------------------------------------------- + + -- Write / read whole word + -- *********************** + for addr in 0 to MEMORY_WORDS-1 loop + read(addr); -- cache hit only if cache size equals memory size. + write(addr); -- cache hit, write-through + read(addr); -- cache hit + nop; + end loop; + for i in 0 to 3 loop nop; end loop; + + -- Write single bytes, read whole word + -- *********************************** + for word_addr in 0 to MEMORY_WORDS-1 loop + read(word_addr); -- cache hit only if cache size equals memory size. + for byte_addr in 0 to BYTES_PER_WORD-1 loop + write_byte(word_addr, byte_addr); + -- cache hit, write-through + end loop; + read(word_addr); -- cache hit + nop; + end loop; -- word_addr + for i in 0 to 3 loop nop; end loop; + + -- Linear access in chunks of cache size, read/write/read every chunk + -- ------------------------------------------------------------------ + + -- Write / read whole word + -- *********************** + for chunk in 0 to (MEMORY_WORDS / CACHE_LINES)-1 loop + for addr in chunk*CACHE_LINES to (chunk+1)*CACHE_LINES-1 loop + read(addr); -- cache hit only if cache size equals memory size. + end loop; -- addr + for addr in chunk*CACHE_LINES to (chunk+1)*CACHE_LINES-1 loop + write(addr); -- cache hit, write-through + end loop; -- addr + for addr in chunk*CACHE_LINES to (chunk+1)*CACHE_LINES-1 loop + read(addr); -- cache hit + end loop; -- addr + nop; + end loop; -- chunk + for i in 0 to 3 loop nop; end loop; + + -- Write single bytes, read whole word + -- *********************************** + for chunk in 0 to (MEMORY_WORDS / CACHE_LINES)-1 loop + for word_addr in chunk*CACHE_LINES to (chunk+1)*CACHE_LINES-1 loop + read(word_addr); -- cache hit only if cache size equals memory size. + end loop; -- word_addr + for word_addr in chunk*CACHE_LINES to (chunk+1)*CACHE_LINES-1 loop + for byte_addr in 0 to BYTES_PER_WORD-1 loop + write_byte(word_addr, byte_addr); -- cache hit, write-through + end loop; + end loop; -- word_addr + for word_addr in chunk*CACHE_LINES to (chunk+1)*CACHE_LINES-1 loop + read(word_addr); -- cache hit + end loop; -- word_addr + nop; + end loop; -- chunk + for i in 0 to 3 loop nop; end loop; + + -- Random access + -- ------------- + for i in 1 to 2000 loop + uniform(seed1, seed2, temp_r); + if temp_r < 0.5 then -- read + uniform(seed1, seed2, temp_r); + read(natural(floor(temp_r * real(MEMORY_WORDS)))); + else -- write + uniform(seed1, seed2, temp_r); + if temp_r < 0.5 then -- write whole word + uniform(seed1, seed2, temp_r); + write(natural(floor(temp_r * real(MEMORY_WORDS)))); + else -- write single byte + temp_r2 := (temp_r-0.5) * 2.0; -- change range to [0:1) + uniform(seed1, seed2, temp_r); + write_byte( + natural(floor(temp_r * real(MEMORY_WORDS))), + natural(floor(temp_r2 * real(BYTES_PER_WORD)))); + end if; + end if; + end loop; + + -- Finished + -- -------- + nop; + finished <= true; + simDeactivateProcess(simProcessID); + wait; + end process CPU_RequestGen; + + -- The Checker of the CPU + CPU_Checker: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("CPU Checker"); + variable saved_rdata : std_logic_vector(CPU_DATA_BITS-1 downto 0); + begin + -- wait until reset completes + wait until rising_edge(clk) and rst = '0'; + + -- wait until all requests have been applied + while not finished loop + wait until rising_edge(clk); + simAssertion(not is_x(cache_rstb) and not is_x(mem2_rstb), "Meta-value on rstb."); + if mem2_rstb = '1' then + saved_rdata := mem2_rdata; + -- If cache does not return data in same clock cycle (i.e. cache miss), + -- then wait for cache_rstb. + while cache_rstb = '0' loop + wait until rising_edge(clk); + -- No new data from 2nd memory must arrive here. + simAssertion(not is_x(cache_rstb) and mem2_rstb = '0', + "Meta-value on rstb or invalid reply from 2nd memory."); + end loop; + + simAssertion(cache_rdata = saved_rdata, "Read data differs."); + end if; + end loop; + + simDeactivateProcess(simProcessID); + simFinalize; + wait; + end process CPU_Checker; + +end architecture sim; diff --git a/tb/cache/cache_mem_tb.files b/tb/cache/cache_mem_tb.files new file mode 100644 index 00000000..4f847a35 --- /dev/null +++ b/tb/cache/cache_mem_tb.files @@ -0,0 +1,15 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# ============================================================================== +# Note: all files are relative to PoC root directory +# +# PoC.cache +include "src/cache/cache_mem.files" # UUT (Unit Under Test) + +# PoC.arith +include "src/arith/arith_prng.files" + +# Testbench files +vhdl test "tb/mem/mem_model.vhdl" # Memory Model +vhdl test "tb/cache/cache_mem_tb.vhdl" # Testbench diff --git a/tb/cache/cache_mem_tb.vhdl b/tb/cache/cache_mem_tb.vhdl new file mode 100644 index 00000000..55b7a48d --- /dev/null +++ b/tb/cache/cache_mem_tb.vhdl @@ -0,0 +1,464 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================ +-- Authors: Martin Zabel +-- +-- Testbench: Testbench for cache_mem. +-- +-- Description: +-- ------------------------------------ +-- Test cache_mem using two memories. One connected behind the cache, and one +-- directly attached to the CPU. The CPU compares the result of read requests +-- issued to the cache with the result from the direct attached memory. +-- +-- CPU ---+--- Cache (UUT) ---- 1st memory +-- | +-- +--- 2nd memory with FIFO for read replies +-- +-- License: +-- ============================================================================ +-- Copyright 2016-2016 Technische Universitaet Dresden - Germany, +-- Chair of VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +library poc; +use poc.utils.all; +use poc.physical.all; +-- simulation only packages +use poc.sim_types.all; +use poc.simulation.all; +use poc.waveform.all; + +entity cache_mem_tb is +end entity cache_mem_tb; + +architecture sim of cache_mem_tb is + constant CLOCK_FREQ : FREQ := 100 MHz; + + -- Cache configuration + constant REPLACEMENT_POLICY : string := "LRU"; + constant CACHE_LINES : positive := 32; + constant ASSOCIATIVITY : positive := 4; + + -- Memory configuration + constant MEM_ADDR_BITS : positive := 6; + constant MEM_DATA_BITS : positive := 128; + + -- NOTE: + -- Memory accesses are always aligned to a word boundary. Each memory word + -- (and each cache line) consists of MEM_DATA_BITS bits. + -- For example if MEM_DATA_BITS=128: + -- + -- * memory address 0 selects the bits 0..127 in memory, + -- * memory address 1 selects the bits 128..256 in memory, and so on. + + -- CPU configuration + constant CPU_DATA_BITS : positive := 32; + constant CPU_ADDR_BITS : positive := log2ceil(MEM_DATA_BITS/CPU_DATA_BITS)+MEM_ADDR_BITS; + constant MEMORY_WORDS : positive := 2**CPU_ADDR_BITS; + constant BYTES_PER_WORD : positive := CPU_DATA_BITS/8; + constant OUTSTANDING_REQ : positive := 2; + + -- NOTE: + -- Cache accesses are always aligned to a CPU word boundary. Each CPU word + -- consists of CPU_DATA_BITS bits. For example if CPU_DATA_BITS=32: + -- + -- * CPU address 0 selects the bits 0.. 31 in memory word 0, + -- * CPU address 1 selects the bits 32.. 63 in memory word 0, + -- * CPU address 2 selects the bits 64.. 95 in memory word 0, + -- * CPU address 3 selects the bits 96..127 in memory word 0, + -- * CPU address 4 selects the bits 0.. 31 in memory word 1, + -- * CPU address 5 selects the bits 32.. 63 in memory word 1, and so on. + + -- Global signals + signal clk : std_logic := '1'; + signal rst : std_logic; + + -- Request from CPU + signal cpu_req : std_logic; + signal cpu_write : std_logic; + signal cpu_addr : unsigned(CPU_ADDR_BITS-1 downto 0); + signal cpu_wdata : std_logic_vector(CPU_DATA_BITS-1 downto 0); + signal cpu_wmask : std_logic_vector(CPU_DATA_BITS/8-1 downto 0); + + -- Bus between CPU and Cache + -- write / addr / wdata are directly connected to the CPU + signal cache_req : std_logic; + signal cache_rdy : std_logic; + signal cache_rstb : std_logic; + signal cache_rdata : std_logic_vector(CPU_DATA_BITS-1 downto 0); + + -- Bus between Cache and 1st Memory + signal mem1_req : std_logic; + signal mem1_write : std_logic; + signal mem1_addr : unsigned(MEM_ADDR_BITS-1 downto 0); + signal mem1_wdata : std_logic_vector(MEM_DATA_BITS-1 downto 0); + signal mem1_wmask : std_logic_vector(MEM_DATA_BITS/8-1 downto 0); + signal mem1_rdy : std_logic; + signal mem1_rstb : std_logic; + signal mem1_rdata : std_logic_vector(MEM_DATA_BITS-1 downto 0); + + -- Bus between CPU and 2nd Memory + -- write / addr / wdata are directly connected to the CPU + signal mem2_req : std_logic; + signal mem2_rdy : std_logic; + signal mem2_rstb : std_logic; + signal mem2_rdata : std_logic_vector(CPU_DATA_BITS-1 downto 0); + + signal rply2_valid : std_logic; + signal rply2_rdata : std_logic_vector(CPU_DATA_BITS-1 downto 0); + + -- Write-Data Generator + signal wdata_got : std_logic; + signal wdata_val : std_logic_vector(CPU_DATA_BITS-1 downto 0); + + -- Control signals between Request Generator and Checker of CPU + signal finished : boolean := false; + +begin + -- initialize global simulation status + simInitialize; + -- generate global testbench clock + simGenerateClock(clk, CLOCK_FREQ); + + -- The Cache + UUT: entity poc.cache_mem + generic map ( + REPLACEMENT_POLICY => REPLACEMENT_POLICY, + CACHE_LINES => CACHE_LINES, + ASSOCIATIVITY => ASSOCIATIVITY, + CPU_DATA_BITS => CPU_DATA_BITS, + MEM_ADDR_BITS => MEM_ADDR_BITS, + MEM_DATA_BITS => MEM_DATA_BITS, + OUTSTANDING_REQ => OUTSTANDING_REQ) + port map ( + clk => clk, + rst => rst, + cpu_req => cache_req, + cpu_write => cpu_write, + cpu_addr => cpu_addr, + cpu_wdata => cpu_wdata, + cpu_wmask => cpu_wmask, + cpu_rdy => cache_rdy, + cpu_rstb => cache_rstb, + cpu_rdata => cache_rdata, + mem_req => mem1_req, + mem_write => mem1_write, + mem_addr => mem1_addr, + mem_wdata => mem1_wdata, + mem_wmask => mem1_wmask, + mem_rdy => mem1_rdy, + mem_rstb => mem1_rstb, + mem_rdata => mem1_rdata); + + -- request only if also 2nd memory is ready + cache_req <= cpu_req and mem2_rdy; + + -- The 1st Memory + memory1: entity work.mem_model + generic map ( + A_BITS => MEM_ADDR_BITS, + D_BITS => MEM_DATA_BITS) + port map ( + clk => clk, + rst => rst, + mem_req => mem1_req, + mem_write => mem1_write, + mem_addr => mem1_addr, + mem_wdata => mem1_wdata, + mem_wmask => mem1_wmask, + mem_rdy => mem1_rdy, + mem_rstb => mem1_rstb, + mem_rdata => mem1_rdata); + + -- The 2nd Memory + memory2: entity work.mem_model + generic map ( + A_BITS => CPU_ADDR_BITS, + D_BITS => CPU_DATA_BITS) + port map ( + clk => clk, + rst => rst, + mem_req => mem2_req, + mem_write => cpu_write, + mem_addr => cpu_addr, + mem_wdata => cpu_wdata, + mem_wmask => cpu_wmask, + mem_rdy => mem2_rdy, + mem_rstb => mem2_rstb, + mem_rdata => mem2_rdata); + + -- request only if also cache is ready + mem2_req <= cpu_req and cache_rdy; + + -- Buffer the replies from 2nd memory for later comparison + rply2_fifo: entity poc.fifo_cc_got + generic map ( + D_BITS => CPU_DATA_BITS, + MIN_DEPTH => imax(OUTSTANDING_REQ, 2), + DATA_REG => OUTSTANDING_REQ <= 2, -- matches cache_mem implementation + OUTPUT_REG => OUTSTANDING_REQ > 2) -- matches cache_mem implementation + port map ( + rst => rst, + clk => clk, + put => mem2_rstb, + din => mem2_rdata, + full => open, -- should not overflow + estate_wr => open, + got => cache_rstb, + dout => rply2_rdata, + valid => rply2_valid, + fstate_rd => open); + + -- The Write-Data Generator of the CPU + wdata_prng: entity poc.arith_prng + generic map (BITS => CPU_DATA_BITS) + port map ( + clk => clk, + rst => rst, + got => wdata_got, + val => wdata_val); + + cpu_wdata <= wdata_val when cpu_write = '1' else (others => '-'); + wdata_got <= cpu_write and cache_rdy and mem2_rdy; + + -- The Request Generator of the CPU + CPU_RequestGen: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("CPU RequestGen"); + + -- no operation + procedure nop is + begin + cpu_req <= '0'; + cpu_write <= '-'; + cpu_addr <= (others => '-'); + cpu_wmask <= (others => '-'); + wait until rising_edge(clk); + end procedure; + + -- Write random data at given word address. + -- Waits until cache and 2nd memory are ready. + procedure write( + addr : in natural; + wmask : in std_logic_vector(BYTES_PER_WORD-1 downto 0) := (others => '0') + ) is + begin + -- apply request (will be ignored if not ready) + cpu_req <= '1'; + cpu_write <= '1'; + cpu_addr <= to_unsigned(addr, CPU_ADDR_BITS); + cpu_wmask <= wmask; + while true loop + wait until rising_edge(clk); + exit when (cache_rdy and mem2_rdy) = '1'; + end loop; + end procedure; + + -- Write single byte of random data at given word address. + -- Waits until cache and 2nd memory are ready. + procedure write_byte( + word_addr : in natural; + byte_addr : in natural range 0 to BYTES_PER_WORD-1 + ) is + variable mask : std_logic_vector(BYTES_PER_WORD-1 downto 0); + begin + mask := (others => '1'); + mask(byte_addr) := '0'; + write(word_addr, mask); + end procedure; + + -- Read at given word address. + -- Waits until cache and 2nd memory are ready. + procedure read(addr : in natural) is + begin + -- apply request (will be ignored if not ready) + cpu_req <= '1'; + cpu_write <= '0'; + cpu_addr <= to_unsigned(addr, CPU_ADDR_BITS); + cpu_wmask <= (others => '-'); + while true loop + wait until rising_edge(clk); + exit when (cache_rdy and mem2_rdy) = '1'; + end loop; + end procedure; + + -- Seeds for random request generation + variable seed1 : positive := 1; + variable seed2 : positive := 1; + + variable temp_r : real; + variable temp_r2: real; + + begin + -- Reset is mandatory + rst <= '1'; + wait until rising_edge(clk); + rst <= '0'; + + -- Check No Operation + -- -------------------------------------------- + for i in 0 to 3 loop nop; end loop; + + -- Fill memory with valid data and read it back + -- -------------------------------------------- + -- Due to the No-Write-Allocate policy no cache hit occurs. + + -- Write / read whole word + -- *********************** + for addr in 0 to MEMORY_WORDS-1 loop + write(addr); + end loop; -- addr + for addr in 0 to MEMORY_WORDS-1 loop + read(addr); + end loop; -- addr + for i in 0 to 3 loop nop; end loop; + + -- Write single bytes, read whole word + -- *********************************** + for word_addr in 0 to MEMORY_WORDS-1 loop + for byte_addr in 0 to BYTES_PER_WORD-1 loop + write_byte(word_addr, byte_addr); + end loop; + end loop; -- addr + for addr in 0 to MEMORY_WORDS-1 loop + read(addr); + end loop; -- addr + for i in 0 to 3 loop nop; end loop; + + -- Linear access, read/write/read at every address + -- ----------------------------------------------- + + -- Write / read whole word + -- *********************** + for addr in 0 to MEMORY_WORDS-1 loop + read(addr); -- cache hit only if cache size equals memory size. + write(addr); -- cache hit, write-through + read(addr); -- cache hit + nop; + end loop; + for i in 0 to 3 loop nop; end loop; + + -- Write single bytes, read whole word + -- *********************************** + for word_addr in 0 to MEMORY_WORDS-1 loop + read(word_addr); -- cache hit only if cache size equals memory size. + for byte_addr in 0 to BYTES_PER_WORD-1 loop + write_byte(word_addr, byte_addr); + -- cache hit, write-through + end loop; + read(word_addr); -- cache hit + nop; + end loop; -- word_addr + for i in 0 to 3 loop nop; end loop; + + -- Linear access in chunks of cache size, read/write/read every chunk + -- ------------------------------------------------------------------ + + -- Write / read whole word + -- *********************** + for chunk in 0 to (MEMORY_WORDS / CACHE_LINES)-1 loop + for addr in chunk*CACHE_LINES to (chunk+1)*CACHE_LINES-1 loop + read(addr); -- cache hit only if cache size equals memory size. + end loop; -- addr + for addr in chunk*CACHE_LINES to (chunk+1)*CACHE_LINES-1 loop + write(addr); -- cache hit, write-through + end loop; -- addr + for addr in chunk*CACHE_LINES to (chunk+1)*CACHE_LINES-1 loop + read(addr); -- cache hit + end loop; -- addr + nop; + end loop; -- chunk + for i in 0 to 3 loop nop; end loop; + + -- Write single bytes, read whole word + -- *********************************** + for chunk in 0 to (MEMORY_WORDS / CACHE_LINES)-1 loop + for word_addr in chunk*CACHE_LINES to (chunk+1)*CACHE_LINES-1 loop + read(word_addr); -- cache hit only if cache size equals memory size. + end loop; -- word_addr + for word_addr in chunk*CACHE_LINES to (chunk+1)*CACHE_LINES-1 loop + for byte_addr in 0 to BYTES_PER_WORD-1 loop + write_byte(word_addr, byte_addr); -- cache hit, write-through + end loop; + end loop; -- word_addr + for word_addr in chunk*CACHE_LINES to (chunk+1)*CACHE_LINES-1 loop + read(word_addr); -- cache hit + end loop; -- word_addr + nop; + end loop; -- chunk + for i in 0 to 3 loop nop; end loop; + + -- Random access + -- ------------- + for i in 1 to 2000 loop + uniform(seed1, seed2, temp_r); + if temp_r < 0.5 then -- read + uniform(seed1, seed2, temp_r); + read(natural(floor(temp_r * real(MEMORY_WORDS)))); + else -- write + uniform(seed1, seed2, temp_r); + if temp_r < 0.5 then -- write whole word + uniform(seed1, seed2, temp_r); + write(natural(floor(temp_r * real(MEMORY_WORDS)))); + else -- write single byte + temp_r2 := (temp_r-0.5) * 2.0; -- change range to [0:1) + uniform(seed1, seed2, temp_r); + write_byte( + natural(floor(temp_r * real(MEMORY_WORDS))), + natural(floor(temp_r2 * real(BYTES_PER_WORD)))); + end if; + end if; + end loop; + + -- Finished + -- -------- + nop; + finished <= true; + simDeactivateProcess(simProcessID); + wait; + end process CPU_RequestGen; + + -- The Checker of the CPU + CPU_Checker: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("CPU Checker"); + begin + -- wait until reset completes + wait until rising_edge(clk) and rst = '0'; + + -- wait until all requests have been applied + while not finished loop + wait until rising_edge(clk); + simAssertion(not is_x(cache_rstb) and not is_x(rply2_valid), "Meta-value on rstb or valid."); + if cache_rstb = '1' then + simAssertion(rply2_valid = '1', "No read data expected."); + if rply2_valid = '1' then + simAssertion(cache_rdata = rply2_rdata, "Read data differs."); + end if; + end if; + end loop; + + simDeactivateProcess(simProcessID); + simFinalize; + wait; + end process CPU_Checker; + +end architecture sim; diff --git a/tb/cache/cache_par2_cocotb.py b/tb/cache/cache_par2_cocotb.py new file mode 100644 index 00000000..7b67b005 --- /dev/null +++ b/tb/cache/cache_par2_cocotb.py @@ -0,0 +1,342 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Martin Zabel +# +# Cocotb Testbench: Cache with parallel access to tags and data. +# +# Description: +# ------------------------------------ +# Automated testbench for PoC.cache_par2 +# +# Supported configuration: +# * REPLACEMENT_POLICY = "LRU" +# +# License: +# ============================================================================== +# Copyright 2016-2016 Technische Universitaet Dresden - Germany +# Chair of VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== + +#import traceback +import random + +import cocotb +from cocotb.decorators import coroutine +from cocotb.triggers import Timer, RisingEdge +from cocotb.monitors import BusMonitor +from cocotb.drivers import BusDriver +from cocotb.binary import BinaryValue +from cocotb.regression import TestFactory +from cocotb.scoreboard import Scoreboard +from cocotb.result import TestFailure + +from lru_dict import LeastRecentlyUsedDict +from utils import log2ceil + +# debug level +DEBUG=0 + +# ============================================================================== +class InputDriver(BusDriver): + """Drives inputs of DUT.""" + _signals = [ "Request", "ReadWrite", "Invalidate", "Replace", "Address", "CacheLineIn" ] + + def __init__(self, dut): + BusDriver.__init__(self, dut, None, dut.Clock) + + +class InputTransaction(object): + """Transaction to be send by InputDriver""" + def __init__(self, tb, request=0, readWrite=0, invalidate=0, replace=0, address=0, cacheLineIn=0): + "tb must be an instance of the Testbench class" + if (replace==1) and ((request==1) or (invalidate==1)): + raise ValueError("InputTransaction.__init__ called with request=%d, invalidate=%d, replace=%d" + % request, invalidate, replace) + + self.Replace = BinaryValue(replace, 1) + self.Request = BinaryValue(request, 1) + self.ReadWrite = BinaryValue(readWrite, 1) + self.Invalidate = BinaryValue(invalidate, 1) + self.Address = BinaryValue(address, tb.address_bits, False) + self.CacheLineIn = BinaryValue(cacheLineIn, tb.data_bits, False) + + +class OutputTransaction(object): + """Transaction to be expected / received by OutputMonitor.""" + def __init__(self, tb=None, cacheLineOut=None, cacheHit=0, cacheMiss=0, oldAddress=None): + """For expected transactions, value 'None' means don't care. tb must be an instance of the Testbench class.""" + if cacheLineOut is not None and isinstance(cacheLineOut, int): cacheLineOut = BinaryValue(cacheLineOut, tb.data_bits, False) + if cacheHit is not None and isinstance(cacheHit, int): cacheHit = BinaryValue(cacheHit, 1) + if cacheMiss is not None and isinstance(cacheMiss, int): cacheMiss = BinaryValue(cacheMiss, 1) + if oldAddress is not None and isinstance(oldAddress, int): oldAddress = BinaryValue(oldAddress, tb.address_bits, False) + self.value = (cacheLineOut, cacheHit, cacheMiss, oldAddress) + + def __eq__(self, other): + if not isinstance(other, OutputTransaction): + raise ValueError("Other value in comparison is not an OutputTransaction, was {0!s} instead.".format(type(other))) + + equal = True + for i, val1 in enumerate(self.value): + val2 = other.value[i] + if val1 is not None and val2 is not None: + if val1 != val2: equal = False + return equal + + def __ne__(self, other): + return not self.__eq__(other) + + def __str__(self): + return ", ".join([str(i) for i in self.value]) + +# ============================================================================== +class InputMonitor(BusMonitor): + """Observes inputs of DUT.""" + _signals = [ "Request", "ReadWrite", "Invalidate", "Replace", "Address", "CacheLineIn" ] + + def __init__(self, dut, callback=None, event=None): + BusMonitor.__init__(self, dut, None, dut.Clock, dut.Reset, callback=callback, event=event) + self.name = "in" + + @coroutine + def _monitor_recv(self): + clkedge = RisingEdge(self.clock) + + while True: + # Capture signals at rising-edge of clock. + yield clkedge + vec = (self.bus.Request.value.integer, + self.bus.ReadWrite.value.integer, + self.bus.Invalidate.value.integer, + self.bus.Replace.value.integer, + self.bus.Address.value.integer, + self.bus.CacheLineIn.value.integer) + self._recv(vec) + +# ============================================================================== +class OutputMonitor(BusMonitor): + """Observes outputs of DUT.""" + _signals = [ "CacheLineOut", "CacheHit", "CacheMiss", "OldAddress" ] + + def __init__(self, dut, tb, callback=None, event=None): + """tb must be an instance of the Testbench class.""" + BusMonitor.__init__(self, dut, None, dut.Clock, dut.Reset, callback=callback, event=event) + self.name = "out" + self.tb = tb + + @coroutine + def _monitor_recv(self): + clkedge = RisingEdge(self.clock) + + while True: + # Capture signals at rising-edge of clock. + yield clkedge + + self._recv(OutputTransaction(self.tb, self.bus.CacheLineOut.value, self.bus.CacheHit.value, + self.bus.CacheMiss.value, self.bus.OldAddress.value)) + +# ============================================================================== +class Testbench(object): + class MyScoreboard(Scoreboard): + def compare(self, got, exp, log, **_): + if got != exp: + self.errors += 1 + log.error("Received transaction differed from expected output.") + log.warning("Expected: {0!s}.\nReceived: {1!s}.".format(exp, got)) + if self._imm: + raise TestFailure("Received transaction differed from expected transaction.") + + + def __init__(self, dut): + self.dut = dut + self.stopped = False + self.address_bits = dut.ADDR_BITS.value + self.data_bits = dut.DATA_BITS.value + + cache_lines = dut.CACHE_LINES.value # total number of cache lines + self.associativity = dut.ASSOCIATIVITY.value + self.cache_sets = cache_lines / self.associativity # number of cache sets + + self.index_bits = log2ceil(self.cache_sets) + tag_bits = self.address_bits - self.index_bits + + self.index_mask = 2**self.index_bits-1 + self.tag_mask = 2**tag_bits-1 + + if DEBUG: print("Testbench: {0}, {1}, {2}".format(self.index_bits, self.index_mask, self.tag_mask)) + + replacement_policy = dut.REPLACEMENT_POLICY.value + if replacement_policy != "LRU": + raise TestFailure("Unsupported configuration: REPLACEMENT_POLICY=%s" % replacement_policy) + + # TODO: create LRU dictionary for each cache set + self.lrus = tuple([LeastRecentlyUsedDict(size_limit=self.associativity) for _ in range(self.cache_sets)]) + + init_val = OutputTransaction(self) + + self.input_drv = InputDriver(dut) + self.output_mon = OutputMonitor(dut, self) + + # Create a scoreboard on the outputs + self.expected_output = [ init_val ] + self.scoreboard = Testbench.MyScoreboard(dut) + self.scoreboard.add_interface(self.output_mon, self.expected_output) + + # Reconstruct the input transactions from the pins + # and send them to our 'model' + self.input_mon = InputMonitor(dut, callback=self.model) + + def model(self, transaction): + '''Model the DUT based on the input transaction.''' + request, readWrite, invalidate, replace, address, cacheLineIn = transaction + if DEBUG >= 1: print("=== model called with stopped={0!r}, Request={1}, ReadWrite={2}, Invalidate={3}, Replace={4}, Address={5}, CacheLineIn={6}". + format(self.stopped, request, readWrite, invalidate, replace, address, cacheLineIn)) + + index = address & self.index_mask + #tag = (address >> self.index_bits) & self.tag_mask + + # expected outputs, None means ignore + cacheLineOut, cacheHit, cacheMiss, oldAddress = None, 0, 0, None + if not self.stopped: + if request == 1: + if address in self.lrus[index]: + cacheHit = 1 + if readWrite == 1: + self.lrus[index][address] = cacheLineIn + else: + cacheLineOut = self.lrus[index][address] + self.lrus[index][address] = cacheLineOut # move to recently-used position + + if invalidate == 1: + del self.lrus[index][address] + + else: + cacheMiss = 1 + + elif replace == 1: + if readWrite == 0: # step 1 + # check if a valid cache line will be replaced + if len(self.lrus[index]) == self.associativity: + oldAddress, cacheLineOut = self.lrus[index].iteritems().next() + + else: # step 2 + # actual replace + self.lrus[index][address] = cacheLineIn + + if DEBUG >= 1: print("=== model: lrus[{0}] = {1!s}".format(index, self.lrus[index].items())) + # convert all not None values to BinaryValue + self.expected_output.append( OutputTransaction(self, cacheLineOut, cacheHit, cacheMiss, oldAddress) ) + + def stop(self): + """ + Stop generation of expected output transactions. + One more clock cycle must be executed afterwards, so that, output of + D-FF can be checked. + """ + self.stopped = True + + +# ============================================================================== +def random_input_gen(tb,n=100000): + """ + Generate random input data to be applied by InputDriver. + Returns up to n instances of InputTransaction. + tb must an instance of the Testbench class. + """ + address_high = 2**tb.address_bits-1 + data_high = 2**tb.data_bits-1 + + # it is forbidden to replace a cache line when the new address is already within the cache + # we cannot directly access the content of the LRU list in the testbench because this function is called asynchronously + lru_tags = tuple([LeastRecentlyUsedDict(size_limit=tb.associativity) for _ in range(tb.cache_sets)]) + + for i in range(n): + if DEBUG and (i % 1000 == 0): print("Generating transaction #{0} ...".format(i)) + + command = random.randint(1,60) + request, readWrite, invalidate, replace = 0, 0, 0, 0 + # 10% for each possible command + if command > 50: request = 1; readWrite = 0; invalidate = 0 + elif command > 40: request = 1; readWrite = 1; invalidate = 0 + elif command > 30: request = 1; readWrite = 0; invalidate = 1 + elif command > 20: request = 1; readWrite = 1; invalidate = 1 + elif command > 10: replace = 1 + + # Upon request, check if address is in LRU list. + while True: + address = random.randint(0,address_high) + index = address & tb.index_mask + tag = (address >> tb.index_bits) & tb.tag_mask + #print "while loop: %d, %d, %d" % (address, index, tag) + if (replace == 0) or (tag not in lru_tags[index]): break + + # Update LRU list + if request == 1: + if tag in lru_tags[index]: + if invalidate == 1: + del lru_tags[index][tag] # free cache line + else: + lru_tags[index][tag] = 1 # tag access + elif replace == 1: + lru_tags[index][tag] = 1 # allocate cache line + + #replace step 1: + yield InputTransaction(tb, request, 0, invalidate, replace, address, random.randint(0,data_high)) + + #replace step 2: + readWrite = 1 # ... and continue below + + if DEBUG >= 2: print("=== random_input_gen: request={0}, readWrite={1}, invalidate={2}, replace={3}, address={4}".format(request, readWrite, invalidate, replace, address)) + if DEBUG >= 2: print("=== random_input_gen: lru_tags[{0}]={1!s}".format(index, lru_tags[index].items())) + + yield InputTransaction(tb, request, readWrite, invalidate, replace, address, random.randint(0,data_high)) + +@cocotb.coroutine +def clock_gen(signal): + while True: + signal <= 0 + yield Timer(5000) # ps + signal <= 1 + yield Timer(5000) # ps + +@cocotb.coroutine +def run_test(dut): + cocotb.fork(clock_gen(dut.Clock)) + tb = Testbench(dut) + dut.Reset <= 0 + + input_gen = random_input_gen(tb) + + # Issue first transaction immediately. + yield tb.input_drv.send(input_gen.next(), False) + + # Issue next transactions. + for t in input_gen: + yield tb.input_drv.send(t) + + # Wait for rising-edge of clock to execute last transaction from above. + # Apply idle command in following clock cycle, but stop generation of expected output data. + # Finish clock cycle to capture the resulting output from the last transaction above. + yield tb.input_drv.send(InputTransaction(tb)) + tb.stop() + yield RisingEdge(dut.Clock) + + # Print result of scoreboard. + raise tb.scoreboard.result + +factory = TestFactory(run_test) +factory.generate_tests() diff --git a/tb/cache/cache_par2_tb.files b/tb/cache/cache_par2_tb.files new file mode 100644 index 00000000..34415a0e --- /dev/null +++ b/tb/cache/cache_par2_tb.files @@ -0,0 +1,17 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# ============================================================================== +# Note: all files are relative to PoC root directory +# +# PoC.cache +include "src/cache/cache_par2.files" # UUT (Unit Under Test) + +# Testbench file(s) +if (ToolChain = "Cocotb") then + cocotb "tb/common/utils.py" + cocotb "tb/common/lru_dict.py" + cocotb "tb/cache/cache_par2_cocotb.py" # Cocotb Testbench +else + report "Only Cocotb testbench available." +end if diff --git a/tb/cache/cache_par_cocotb.py b/tb/cache/cache_par_cocotb.py index 62a70aca..8ba98e1b 100644 --- a/tb/cache/cache_par_cocotb.py +++ b/tb/cache/cache_par_cocotb.py @@ -3,9 +3,9 @@ # kate: tab-width 2; replace-tabs off; indent-width 2; # # ============================================================================== -# Authors: Martin Zabel +# Authors: Martin Zabel # -# Cocotb Testbench: Cache with parallel access to tags and data. +# Cocotb Testbench: Cache with parallel access to tags and data. # # Description: # ------------------------------------ @@ -16,7 +16,7 @@ # # License: # ============================================================================== -# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Copyright 2016-2016 Technische Universitaet Dresden - Germany # Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/tb/mem/mem_model.vhdl b/tb/mem/mem_model.vhdl new file mode 100644 index 00000000..2e2ea489 --- /dev/null +++ b/tb/mem/mem_model.vhdl @@ -0,0 +1,206 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================ +-- Authors: Martin Zabel +-- +-- Module: Model of pipelined memory with PoC.Mem interface. +-- +-- Description: +-- ------------------------------------ +-- Model of pipelined memory with +-- :doc:`PoC.Mem ` interface. +-- +-- To be used for simulation as a replacement for a real memory controller. +-- +-- The interface is documented in detail :doc:`here `. +-- +-- Additional parameter: LATENCY = the latency of the pipelined read. +-- +-- .. NOTE:: +-- Synchronous reset is required after simulation startup. +-- +-- License: +-- ============================================================================ +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany, +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================ + + +------------------------------------------------------------------------------- +-- Naming Conventions: +-- (Based on: Keating and Bricaud: "Reuse Methodology Manual") +-- +-- active low signals: "*_n" +-- clock signals: "clk", "clk_div#", "clk_#x" +-- reset signals: "rst", "rst_n" +-- generics: all UPPERCASE +-- user defined types: "*_TYPE" +-- state machine next state: "*_ns" +-- state machine current state: "*_cs" +-- output of a register: "*_r" +-- asynchronous signal: "*_a" +-- pipelined or register delay signals: "*_p#" +-- data before being registered into register with the same name: "*_nxt" +-- clock enable signals: "*_ce" +-- internal version of output port: "*_i" +-- tristate internal signal "*_z" +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity mem_model is + + generic ( + A_BITS : positive; + D_BITS : positive; + LATENCY : positive := 1 + ); + + port ( + clk : in std_logic; + rst : in std_logic; + + mem_req : in std_logic; + mem_write : in std_logic; + mem_addr : in unsigned(A_BITS-1 downto 0); + mem_wdata : in std_logic_vector(D_BITS-1 downto 0); + mem_wmask : in std_logic_vector(D_BITS/8-1 downto 0) := (others => '0'); + mem_rdy : out std_logic; + mem_rstb : out std_logic; + mem_rdata : out std_logic_vector(D_BITS-1 downto 0)); + +end entity mem_model; + +architecture sim of mem_model is + -- data types + type RAM_T is array(natural range<>) of std_logic_vector(D_BITS-1 downto 0); + signal ram : RAM_T(0 to 2**A_BITS-1); + + -- read pipeline + type RDATA_T is array(natural range<>) of std_logic_vector(D_BITS-1 downto 0); + signal rdata_p : RDATA_T(1 to LATENCY); + signal rstb_p : std_logic_vector(1 to LATENCY) := (others => '0'); + + -- FSM + type T_FSM is (RESET, READY, UNKNOWN); + signal fsm_cs : T_FSM := UNKNOWN; -- current state + + signal req_write : X01; + signal req_read : X01; + +begin -- architecture sim + + -- Command decoding, handle 'U' as 'X' + req_write <= to_x01(mem_req and mem_write); + req_read <= to_x01(mem_req and not mem_write); + + -- TODO: implement some logic / FSM which introduces wait states + process(clk) + variable fsm_ns : T_FSM; -- next state + begin + if rising_edge(clk) then + fsm_ns := fsm_cs; + + case fsm_cs is + when READY => + -- check for valid command + if is_x(req_read) or is_x(req_write) then + report "Invalid read/write command." severity error; + fsm_ns := UNKNOWN; + end if; + + when RESET => fsm_ns := READY; + when UNKNOWN => null; + end case; + + -- Reset override + case to_x01(rst) is + when '1' => fsm_cs <= RESET; + when '0' => fsm_cs <= fsm_ns; + when 'X' => fsm_cs <= UNKNOWN; + end case; + end if; + end process; + + -- Memory and Read Pipeline + process(clk) + begin + if rising_edge(clk) then + rstb_p(1) <= '0'; -- default + + -- access memory only when ready, ignore requests otherwise + if fsm_cs = READY then + if (req_write) = '1' then + if Is_X(std_logic_vector(mem_addr)) then + report "Invalid address during write." severity error; + ram <= (others => (others => 'X')); + else + for i in 0 to D_BITS/8-1 loop + if Is_X(mem_wmask(i)) then + ram(to_integer(mem_addr))(i*8+7 downto i*8) <= (others => 'X'); + elsif mem_wmask(i) = '0' then + ram(to_integer(mem_addr))(i*8+7 downto i*8) <= to_ux01(mem_wdata(i*8+7 downto i*8)); + end if; + end loop; -- i + end if; + elsif (req_write = 'X') then + -- error is reported above + ram <= (others => (others => 'X')); + end if; + + if req_read = '1' then + rstb_p(1) <= '1'; + if Is_X(std_logic_vector(mem_addr)) then + report "Invalid address during read." severity error; + rdata_p(1) <= (others => 'X'); + else + rdata_p(1) <= ram(to_integer(mem_addr)); + end if; + elsif req_read = 'X' then + -- error is reported above + rstb_p(1) <= 'X'; + rdata_p(1) <= (others => 'X'); + end if; + end if; + + -- read pipeline + if LATENCY > 1 then + rstb_p (2 to LATENCY) <= rstb_p (1 to LATENCY-1); + rdata_p(2 to LATENCY) <= rdata_p(1 to LATENCY-1); + end if; + + -- reset only read strobe + case to_x01(rst) is + when '1' => rstb_p <= (others => '0'); + when '0' => null; + when 'X' => rstb_p <= (others => 'X'); + end case; + end if; + end process; + + -- Outputs + with fsm_cs select mem_rdy <= + '1' when READY, + 'X' when UNKNOWN, + '0' when others; + + mem_rdata <= rdata_p(LATENCY); + mem_rstb <= rstb_p (LATENCY); + +end architecture sim; From f7ff5ad07212f13e0656e5966065d95108cd63c2 Mon Sep 17 00:00:00 2001 From: Martin Zabel Date: Wed, 23 Nov 2016 15:18:48 +0100 Subject: [PATCH 60/97] New simulation model for dual-port RAMs, updated testbenches for dual-port RAMs. New IPCore ocram_tdp_wf. Fixed dstruct_deque. --- docs/ChangeLog/2016/v1.x.rst | 10 + docs/IPCores/mem/ocram/index.rst | 18 +- docs/IPCores/mem/ocram/ocram_esdp.rst | 12 +- docs/IPCores/mem/ocram/ocram_sdp.rst | 12 +- docs/IPCores/mem/ocram/ocram_sdp_wf.rst | 16 +- docs/IPCores/mem/ocram/ocram_tdp.rst | 18 +- docs/IPCores/mem/ocram/ocram_tdp_sim.rst | 47 ++ docs/IPCores/mem/ocram/ocram_tdp_wf.rst | 77 +++ py/DataBase/Query.py | 1 - py/DataBase/__init__.py | 1 - py/config.entity.ini | 13 + py/config.structure.ini | 1 + src/dstruct/dstruct_deque.files | 2 +- src/dstruct/dstruct_deque.vhdl | 8 +- src/mem/ocram/ocram_esdp.files | 3 + src/mem/ocram/ocram_esdp.vhdl | 63 +- src/mem/ocram/ocram_sdp.files | 3 + src/mem/ocram/ocram_sdp.vhdl | 88 ++- src/mem/ocram/ocram_sdp_wf.vhdl | 14 + src/mem/ocram/ocram_sp.vhdl | 2 +- src/mem/ocram/ocram_tdp.files | 3 + src/mem/ocram/ocram_tdp.vhdl | 69 +- src/mem/ocram/ocram_tdp_wf.files | 12 + src/mem/ocram/ocram_tdp_wf.vhdl | 191 ++++++ tb/mem/ocram/ocram_esdp_tb.vhdl | 438 ++++++++---- tb/mem/ocram/ocram_sdp_tb.vhdl | 363 +++++++--- tb/mem/ocram/ocram_sdp_wf_tb.vhdl | 27 +- tb/mem/ocram/ocram_tdp_tb.vhdl | 822 ++++++++++++++++------- tb/mem/ocram/ocram_tdp_wf_tb.files | 11 + tb/mem/ocram/ocram_tdp_wf_tb.vhdl | 644 ++++++++++++++++++ 30 files changed, 2397 insertions(+), 592 deletions(-) create mode 100644 docs/IPCores/mem/ocram/ocram_tdp_sim.rst create mode 100644 docs/IPCores/mem/ocram/ocram_tdp_wf.rst create mode 100644 src/mem/ocram/ocram_tdp_wf.files create mode 100644 src/mem/ocram/ocram_tdp_wf.vhdl create mode 100644 tb/mem/ocram/ocram_tdp_wf_tb.files create mode 100644 tb/mem/ocram/ocram_tdp_wf_tb.vhdl diff --git a/docs/ChangeLog/2016/v1.x.rst b/docs/ChangeLog/2016/v1.x.rst index 3c2d7649..4a1332a2 100644 --- a/docs/ChangeLog/2016/v1.x.rst +++ b/docs/ChangeLog/2016/v1.x.rst @@ -28,22 +28,32 @@ Already documented changes are available on the ``release`` branch at GitHub. * New Entities * :ref:`IP:ocram_sdp_wf` + * :ref:`IP:ocram_tdp_wf` * :ref:`IP:cache_par2` * :ref:`IP:cache_cpu` * :ref:`IP:cache_mem` + * Simulation helper :ref:`IP:ocram_tdp_sim` * Updated Entities * Interface of :ref:`IP:cache_tagunit_par` changed slightly. * New port "write-mask" in :ref:`IP:ddr3_mem2mig_adapter_Series7`. * New port "write-mask" in :ref:`IP:ddr2_mem2mig_adapter_Spartan6`. + * Fixed :ref:`IP:dstruct_deque` * New Testbenches * Testbench for :ref:`IP:ocram_sdp_wf` + * Testbench for :ref:`IP:ocram_tdp_wf` * Testbench for :ref:`IP:cache_par2` * Testbench for :ref:`IP:cache_cpu` * Testbench for :ref:`IP:cache_mem` +* Updated Testbenches + + * Testbench for :ref:`IP:ocram_sdp` + * Testbench for :ref:`IP:ocram_esdp` + * Testbench for :ref:`IP:ocram_tdp` + * New Constraints * Shipped Tool and Helper Scripts diff --git a/docs/IPCores/mem/ocram/index.rst b/docs/IPCores/mem/ocram/index.rst index 567b47ae..c415e438 100644 --- a/docs/IPCores/mem/ocram/index.rst +++ b/docs/IPCores/mem/ocram/index.rst @@ -18,10 +18,16 @@ The package PoC.mem.ocram holds all component declarations for this namespace. **Entities** * :ref:`IP:ocram_sp` - An on-chip RAM with a single port interface. - * :ref:`IP:ocram_sdp` - An on-chip RAM with a simple dual port interface. - * :ref:`IP:ocram_sdp_wf` - An on-chip RAM with a simple dual port + * :ref:`IP:ocram_sdp` - An on-chip RAM with a simple dual-port interface. + * :ref:`IP:ocram_sdp_wf` - An on-chip RAM with a simple dual-port interface and write-first behavior. - * :ref:`IP:ocram_tdp` - An on-chip RAM with a true dual port interface. + * :ref:`IP:ocram_tdp` - An on-chip RAM with a true dual-port interface. + * :ref:`IP:ocram_tdp_wf` - An on-chip RAM with a true dual-port + interface and write-first behavior. + +**Simulation Helper** + + * :ref:`IP:ocram_tdp_sim` - Simulation model of on-chip RAM with a true dual port interface. **Deprecated Entities** @@ -40,6 +46,12 @@ The package PoC.mem.ocram holds all component declarations for this namespace. ocram_sdp ocram_sdp_wf ocram_tdp + ocram_tdp_wf + +.. toctree:: + :hidden: + + ocram_tdp_sim .. toctree:: :hidden: diff --git a/docs/IPCores/mem/ocram/ocram_esdp.rst b/docs/IPCores/mem/ocram/ocram_esdp.rst index 7ba73188..6d102f95 100644 --- a/docs/IPCores/mem/ocram/ocram_esdp.rst +++ b/docs/IPCores/mem/ocram/ocram_esdp.rst @@ -60,10 +60,7 @@ Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows: Same-Port Read-During-Write When writing data through port 1, the read output of the same port (``q1``) will output the new data (``d1``, in the following clock cycle) - which is aka. "write-first behavior". This behavior also applies to Altera - M20K memory blocks as described in the Altera: "Stratix 5 Device Handbook" - (S5-5V1). The documentation in the Altera: "Embedded Memory User Guide" - (UG-01068) is wrong. + which is aka. "write-first behavior". Mixed-Port Read-During-Write When reading at the write address, the read value will be unknown which is @@ -72,9 +69,8 @@ Mixed-Port Read-During-Write rising-edge of the write clock (``clk1``) and (in the worst case) extends until the next rising-edge of the write clock. -.. WARNING:: - The simulated behavior on RT-level is too optimistic. When reading - at the write address always the new data will be returned. +For simulation, always our dedicated simulation model :ref:`IP:ocram_tdp_sim` +is used. @@ -84,7 +80,7 @@ Mixed-Port Read-During-Write :language: vhdl :tab-width: 2 :linenos: - :lines: 101-119 + :lines: 97-115 diff --git a/docs/IPCores/mem/ocram/ocram_sdp.rst b/docs/IPCores/mem/ocram/ocram_sdp.rst index f00d245c..4257ae7b 100644 --- a/docs/IPCores/mem/ocram/ocram_sdp.rst +++ b/docs/IPCores/mem/ocram/ocram_sdp.rst @@ -25,6 +25,10 @@ Inferring / instantiating simple dual-port memory, with: * dual clock, clock enable, * 1 read port plus 1 write port. +Both reading and writing are synchronous to the rising-edge of the clock. +Thus, when reading, the memory data will be outputted after the +clock edge, i.e, in the following clock cycle. + The generalized behavior across Altera and Xilinx FPGAs since Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows: @@ -35,12 +39,8 @@ Mixed-Port Read-During-Write rising-edge of the write clock and (in the worst case) extends until the next rising-edge of the write clock. -.. WARNING:: - The simulated behavior on RT-level is too optimistic. The - mixed-port read-during-write behavior is only valid if the read and write - clock are in phase. Otherwise, simulation will always show known data. - -.. TODO:: Implement correct behavior for RT-level simulation. +For simulation, always our dedicated simulation model :ref:`IP:ocram_tdp_sim` +is used. diff --git a/docs/IPCores/mem/ocram/ocram_sdp_wf.rst b/docs/IPCores/mem/ocram/ocram_sdp_wf.rst index 4843b95e..4fa2f9c7 100644 --- a/docs/IPCores/mem/ocram/ocram_sdp_wf.rst +++ b/docs/IPCores/mem/ocram/ocram_sdp_wf.rst @@ -25,6 +25,20 @@ Inferring / instantiating simple dual-port memory, with: * single clock, clock enable, * 1 read port plus 1 write port. +Command truth table: + +== == =============================== +ce we Command +== == =============================== +0 X No operation +1 0 Read only from memory +1 1 Read from and Write to memory +== == =============================== + +Both reading and writing are synchronous to the rising-edge of the clock. +Thus, when reading, the memory data will be outputted after the +clock edge, i.e, in the following clock cycle. + Mixed-Port Read-During-Write When reading at the write address, the read value will be the new data, aka. "write-first behavior". Of course, the read is still synchronous, @@ -38,7 +52,7 @@ Mixed-Port Read-During-Write :language: vhdl :tab-width: 2 :linenos: - :lines: 43-58 + :lines: 57-72 diff --git a/docs/IPCores/mem/ocram/ocram_tdp.rst b/docs/IPCores/mem/ocram/ocram_tdp.rst index fc35644e..18b0ef52 100644 --- a/docs/IPCores/mem/ocram/ocram_tdp.rst +++ b/docs/IPCores/mem/ocram/ocram_tdp.rst @@ -35,16 +35,17 @@ ce1 we1 Command 1 1 Write to memory === === ================ +Both reading and writing are synchronous to the rising-edge of the clock. +Thus, when reading, the memory data will be outputted after the +clock edge, i.e, in the following clock cycle. + The generalized behavior across Altera and Xilinx FPGAs since Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows: Same-Port Read-During-Write When writing data through port 1, the read output of the same port (``q1``) will output the new data (``d1``, in the following clock cycle) - which is aka. "write-first behavior". This behavior also applies to Altera - M20K memory blocks as described in the Altera: "Stratix 5 Device Handbook" - (S5-5V1). The documentation in the Altera: "Embedded Memory User Guide" - (UG-01068) is wrong. + which is aka. "write-first behavior". Same applies to port 2. @@ -55,11 +56,8 @@ Mixed-Port Read-During-Write rising-edge of the write clock and (in the worst case) extends until the next rising-edge of that write clock. -.. WARNING:: - The simulated behavior on RT-level is too optimistic. When reading - at the write address always the new data will be returned. - -.. TODO:: Implement correct behavior for RT-level simulation. +For simulation, always our dedicated simulation model :ref:`IP:ocram_tdp_sim` +is used. @@ -69,7 +67,7 @@ Mixed-Port Read-During-Write :language: vhdl :tab-width: 2 :linenos: - :lines: 84-104 + :lines: 82-102 diff --git a/docs/IPCores/mem/ocram/ocram_tdp_sim.rst b/docs/IPCores/mem/ocram/ocram_tdp_sim.rst new file mode 100644 index 00000000..64b9645d --- /dev/null +++ b/docs/IPCores/mem/ocram/ocram_tdp_sim.rst @@ -0,0 +1,47 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram_tdp_sim.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocram/ocram_tdp_sim_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + + +.. _IP:ocram_tdp_sim: + +ocram_tdp_sim +############# + +Simulation model for true dual-port memory, with: + +* dual clock, clock enable, +* 2 read/write ports. + +The interface matches that of the IP core PoC.mem.ocram.tdp. +But the implementation there is restricted to the description supported by +various synthesis compilers. The implementation here also simulates the +correct Mixed-Port Read-During-Write Behavior and handles X propagation. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/ocram/ocram_tdp_sim.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 51-71 + + + +.. only:: latex + + Source file: :pocsrc:`mem/ocram/ocram_tdp_sim.vhdl ` diff --git a/docs/IPCores/mem/ocram/ocram_tdp_wf.rst b/docs/IPCores/mem/ocram/ocram_tdp_wf.rst new file mode 100644 index 00000000..130cade3 --- /dev/null +++ b/docs/IPCores/mem/ocram/ocram_tdp_wf.rst @@ -0,0 +1,77 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram_tdp_wf.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocram/ocram_tdp_wf_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + + +.. _IP:ocram_tdp_wf: + +ocram_tdp_wf +############ + +Inferring / instantiating true dual-port memory, with: + +* single clock, clock enable, +* 2 read/write ports. + +Command truth table: + +== === === ===================================================== +ce we1 we2 Command +== === === ===================================================== +0 X X No operation +1 0 0 Read only from memory +1 0 1 Read from memory on port 1, write to memory on port 2 +1 1 0 Write to memory on port 1, read from memory on port 2 +1 1 1 Write to memory on both ports +== === === ===================================================== + +Both reads and writes are synchronous to the clock. + +The generalized behavior across Altera and Xilinx FPGAs since +Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows: + +Same-Port Read-During-Write + When writing data through port 1, the read output of the same port + (``q1``) will output the new data (``d1``, in the following clock cycle) + which is aka. "write-first behavior". + + Same applies to port 2. + +Mixed-Port Read-During-Write + When reading at the write address, the read value will be the new data, + aka. "write-first behavior". Of course, the read is still synchronous, + i.e, the latency is still one clock cyle. + +If a write is issued on both ports to the same address, then the output of +this unit and the content of the addressed memory cell are undefined. + +For simulation, always our dedicated simulation model :ref:`IP:ocram_tdp_sim` +is used. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/ocram/ocram_tdp_wf.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 83-101 + + + +.. only:: latex + + Source file: :pocsrc:`mem/ocram/ocram_tdp_wf.vhdl ` diff --git a/py/DataBase/Query.py b/py/DataBase/Query.py index 511c8b30..7ba8a340 100644 --- a/py/DataBase/Query.py +++ b/py/DataBase/Query.py @@ -117,4 +117,3 @@ def _GetXilinxVivadoSettingsFile(self): raise PlatformNotSupportedException(self.Platform) else: raise NotConfiguredException("ERROR: Xilinx ISE is not configured on this system.") - diff --git a/py/DataBase/__init__.py b/py/DataBase/__init__.py index da726182..b7f7c9a5 100644 --- a/py/DataBase/__init__.py +++ b/py/DataBase/__init__.py @@ -43,4 +43,3 @@ __POC_SOLUTION_KEYWORD__ = "Solution" __POC_PROJECT_KEYWORD__ = "Project" - diff --git a/py/config.entity.ini b/py/config.entity.ini index be61c3b9..a4a68d88 100644 --- a/py/config.entity.ini +++ b/py/config.entity.ini @@ -517,6 +517,19 @@ HDLParameters = A_BITS=12; D_BITS=16 [XST.mem.ocram.tdp.nl3] [VIVADO.mem.ocram.tdp.nl4] +[IP.mem.ocram.tdp_wf] +tb = VHDLTestbench +nl1 = LSENetlist +nl2 = QuartusNetlist +nl3 = XSTNetlist +nl4 = VivadoNetlist +HDLParameters = A_BITS=12; D_BITS=16 +[TB.mem.ocram.tdp_wf.tb] +[LSE.mem.ocram.tdp_wf.nl1] +[QMAP.mem.ocram.tdp_wf.nl2] +[XST.mem.ocram.tdp_wf.nl3] +[VIVADO.mem.ocram.tdp_wf.nl4] + # PoC.mem.ocrom # ------------------------------------------------------------------------------ diff --git a/py/config.structure.ini b/py/config.structure.ini index e12976e9..37bb8175 100644 --- a/py/config.structure.ini +++ b/py/config.structure.ini @@ -218,6 +218,7 @@ sdp = Entity sdp_wf = Entity sp = Entity tdp = Entity +tdp_wf = Entity [PoC.mem.ocrom] sp = Entity diff --git a/src/dstruct/dstruct_deque.files b/src/dstruct/dstruct_deque.files index aaf4f7ac..02d2b1b6 100644 --- a/src/dstruct/dstruct_deque.files +++ b/src/dstruct/dstruct_deque.files @@ -8,7 +8,7 @@ include "src/common/common.files" # load common packages # PoC.mem.ocram -include "src/mem/ocram/ocram_tdp.files" # True dual-port RAM +include "src/mem/ocram/ocram_tdp_wf.files" # True dual-port RAM # PoC.dstruct vhdl PoC "src/dstruct/dstruct.pkg.vhdl" # PoC.bus package diff --git a/src/dstruct/dstruct_deque.vhdl b/src/dstruct/dstruct_deque.vhdl index aeb995ac..9ec0b02f 100644 --- a/src/dstruct/dstruct_deque.vhdl +++ b/src/dstruct/dstruct_deque.vhdl @@ -115,17 +115,15 @@ architecture rtl of dstruct_deque is begin - ram : entity poc.ocram_tdp + ram : entity poc.ocram_tdp_wf generic map( A_BITS => A_BITS, D_BITS => D_BITS, FILENAME => "" ) port map( - clk1 => clk, - clk2 => clk, - ce1 => '1', - ce2 => '1', + clk => clk, + ce => '1', we1 => weA, we2 => weB, a1 => adrA, diff --git a/src/mem/ocram/ocram_esdp.files b/src/mem/ocram/ocram_esdp.files index fbfb3a57..9313e311 100644 --- a/src/mem/ocram/ocram_esdp.files +++ b/src/mem/ocram/ocram_esdp.files @@ -16,5 +16,8 @@ if (DeviceVendor = "Altera") then include "lib/Altera.files" vhdl poc "src/mem/ocram/altera/ocram_tdp_altera.vhdl" # Altera specific extended simple dual-port RAM end if +if (Environment = "Simulation") then + vhdl poc "src/mem/ocram/ocram_tdp_sim.vhdl" # Simulation model +end if vhdl poc "src/mem/ocram/ocram_tdp.vhdl" # True dual-port RAM vhdl poc "src/mem/ocram/ocram_esdp.vhdl" # Extended simple dual-port RAM diff --git a/src/mem/ocram/ocram_esdp.vhdl b/src/mem/ocram/ocram_esdp.vhdl index b6a70ed2..30e0cc07 100644 --- a/src/mem/ocram/ocram_esdp.vhdl +++ b/src/mem/ocram/ocram_esdp.vhdl @@ -49,10 +49,7 @@ -- Same-Port Read-During-Write -- When writing data through port 1, the read output of the same port -- (``q1``) will output the new data (``d1``, in the following clock cycle) --- which is aka. "write-first behavior". This behavior also applies to Altera --- M20K memory blocks as described in the Altera: "Stratix 5 Device Handbook" --- (S5-5V1). The documentation in the Altera: "Embedded Memory User Guide" --- (UG-01068) is wrong. +-- which is aka. "write-first behavior". -- -- Mixed-Port Read-During-Write -- When reading at the write address, the read value will be unknown which is @@ -61,13 +58,12 @@ -- rising-edge of the write clock (``clk1``) and (in the worst case) extends -- until the next rising-edge of the write clock. -- --- .. WARNING:: --- The simulated behavior on RT-level is too optimistic. When reading --- at the write address always the new data will be returned. +-- For simulation, always our dedicated simulation model :ref:`IP:ocram_tdp_sim` +-- is used. -- -- License: -- ============================================================================= --- Copyright 2008-2015 Technische Universitaet Dresden - Germany +-- Copyright 2008-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); @@ -123,7 +119,7 @@ architecture rtl of ocram_esdp is constant DEPTH : positive := 2**A_BITS; begin - gInfer : if (VENDOR = VENDOR_GENERIC) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX) generate + gInfer : if not SIMULATION and ((VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX)) generate -- For Xilinx ISE, Xilinx Vivado and Lattice LSE we can reuse the ocram_tdp. -- @@ -149,7 +145,7 @@ begin q2 => q2); end generate gInfer; - gAltera: if VENDOR = VENDOR_ALTERA generate + gAltera: if not SIMULATION and (VENDOR = VENDOR_ALTERA) generate component ocram_tdp_altera generic ( A_BITS : positive; @@ -175,7 +171,7 @@ begin -- Direct instantiation of altsyncram (including component -- declaration above) is not sufficient for ModelSim. -- That requires also usage of altera_mf library. - ram_tdp: ocram_tdp_altera + ram_altera: ocram_tdp_altera generic map ( A_BITS => A_BITS, D_BITS => D_BITS, @@ -197,7 +193,50 @@ begin ); end generate gAltera; - assert ((VENDOR = VENDOR_ALTERA) or (VENDOR = VENDOR_GENERIC) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX)) + gSim: if SIMULATION generate + -- Use component instantiation so that simulation model can be excluded + -- from synthesis. + component ocram_tdp_sim is + generic ( + A_BITS : positive; + D_BITS : positive; + FILENAME : string); + port ( + clk1 : in std_logic; + clk2 : in std_logic; + ce1 : in std_logic; + ce2 : in std_logic; + we1 : in std_logic; + we2 : in std_logic; + a1 : in unsigned(A_BITS-1 downto 0); + a2 : in unsigned(A_BITS-1 downto 0); + d1 : in std_logic_vector(D_BITS-1 downto 0); + d2 : in std_logic_vector(D_BITS-1 downto 0); + q1 : out std_logic_vector(D_BITS-1 downto 0); + q2 : out std_logic_vector(D_BITS-1 downto 0)); + end component ocram_tdp_sim; + begin + sim_tdp: ocram_tdp_sim + generic map ( + A_BITS => A_BITS, + D_BITS => D_BITS, + FILENAME => FILENAME) + port map ( + clk1 => clk1, + clk2 => clk2, + ce1 => ce1, + ce2 => ce2, + we1 => we1, + we2 => '0', + a1 => a1, + a2 => a2, + d1 => d1, + d2 => (others => '0'), + q1 => q1, + q2 => q2); + end generate gSim; + + assert ((VENDOR = VENDOR_ALTERA) or (VENDOR = VENDOR_GENERIC and SIMULATION) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX)) report "Vendor '" & T_VENDOR'image(VENDOR) & "' not yet supported." severity failure; end architecture; diff --git a/src/mem/ocram/ocram_sdp.files b/src/mem/ocram/ocram_sdp.files index 36a0b5c4..abb4b4b1 100644 --- a/src/mem/ocram/ocram_sdp.files +++ b/src/mem/ocram/ocram_sdp.files @@ -12,4 +12,7 @@ vhdl poc "src/mem/mem.pkg.vhdl" # Memory package # PoC.mem.ocram vhdl poc "src/mem/ocram/ocram.pkg.vhdl" # On-Chip-RAM +if (Environment = "Simulation") then + vhdl poc "src/mem/ocram/ocram_tdp_sim.vhdl" # Simulation model +end if vhdl poc "src/mem/ocram/ocram_sdp.vhdl" # Simple dual-port RAM diff --git a/src/mem/ocram/ocram_sdp.vhdl b/src/mem/ocram/ocram_sdp.vhdl index 12a7d3b1..0f3d860f 100644 --- a/src/mem/ocram/ocram_sdp.vhdl +++ b/src/mem/ocram/ocram_sdp.vhdl @@ -15,6 +15,10 @@ -- * dual clock, clock enable, -- * 1 read port plus 1 write port. -- +-- Both reading and writing are synchronous to the rising-edge of the clock. +-- Thus, when reading, the memory data will be outputted after the +-- clock edge, i.e, in the following clock cycle. +-- -- The generalized behavior across Altera and Xilinx FPGAs since -- Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows: -- @@ -25,16 +29,12 @@ -- rising-edge of the write clock and (in the worst case) extends until the -- next rising-edge of the write clock. -- --- .. WARNING:: --- The simulated behavior on RT-level is too optimistic. The --- mixed-port read-during-write behavior is only valid if the read and write --- clock are in phase. Otherwise, simulation will always show known data. --- --- .. TODO:: Implement correct behavior for RT-level simulation. +-- For simulation, always our dedicated simulation model :ref:`IP:ocram_tdp_sim` +-- is used. -- -- License: -- ============================================================================= --- Copyright 2008-2015 Technische Universitaet Dresden - Germany +-- Copyright 2008-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); @@ -87,7 +87,7 @@ architecture rtl of ocram_sdp is begin - gInfer : if (VENDOR = VENDOR_ALTERA) or (VENDOR = VENDOR_GENERIC) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX) generate + gInfer : if not SIMULATION and ((VENDOR = VENDOR_ALTERA) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX)) generate -- RAM can be inferred correctly -- Xilinx notes: -- WRITE_MODE is set to WRITE_FIRST, but this also means that read data @@ -134,18 +134,7 @@ begin begin if rising_edge(wclk) then if (wce and we) = '1' then - -- Note: Hide plausibility tests from synthesis to ensure - -- proper RAM inference. - --synthesis translate_off - if Is_X(std_logic_vector(wa)) then - report "ocram_sdp: Writing to ill-defined address." - severity error; - else - --synthesis translate_on ram(to_integer(wa)) <= d; - --synthesis translate_off - end if; - --synthesis translate_on end if; end if; end process; @@ -154,29 +143,56 @@ begin begin if rising_edge(rclk) then if rce = '1' then - -- Note: Hide plausibility tests from synthesis to ensure - -- proper RAM inference. - --synthesis translate_off - if Is_X(std_logic_vector(ra)) then - q <= (others => 'X'); - elsif wce = '1' and we = '1' and ra = wa and rising_edge(wclk) then - -- read data unknown when reading at write address, - -- and both clock-edges are at almost the same time - q <= (others => 'X'); - report "ocram_sdp: Reading from address just writing: Unknown result." - severity warning; - else - --synthesis translate_on q <= ram(to_integer(ra)); - --synthesis translate_off - end if; - --synthesis translate_on end if; end if; end process; end generate gInfer; - assert ((VENDOR = VENDOR_ALTERA) or (VENDOR = VENDOR_GENERIC) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX)) + gSim: if SIMULATION generate + -- Use component instantiation so that simulation model can be excluded + -- from synthesis. + component ocram_tdp_sim is + generic ( + A_BITS : positive; + D_BITS : positive; + FILENAME : string); + port ( + clk1 : in std_logic; + clk2 : in std_logic; + ce1 : in std_logic; + ce2 : in std_logic; + we1 : in std_logic; + we2 : in std_logic; + a1 : in unsigned(A_BITS-1 downto 0); + a2 : in unsigned(A_BITS-1 downto 0); + d1 : in std_logic_vector(D_BITS-1 downto 0); + d2 : in std_logic_vector(D_BITS-1 downto 0); + q1 : out std_logic_vector(D_BITS-1 downto 0); + q2 : out std_logic_vector(D_BITS-1 downto 0)); + end component ocram_tdp_sim; + begin + sim_tdp: ocram_tdp_sim + generic map ( + A_BITS => A_BITS, + D_BITS => D_BITS, + FILENAME => FILENAME) + port map ( + clk1 => wclk, + clk2 => rclk, + ce1 => wce, + ce2 => rce, + we1 => we, + we2 => '0', + a1 => wa, + a2 => ra, + d1 => d, + d2 => (others => '0'), + q1 => open, + q2 => q); + end generate gSim; + + assert ((VENDOR = VENDOR_ALTERA) or (VENDOR = VENDOR_GENERIC and SIMULATION) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX)) report "Vendor '" & T_VENDOR'image(VENDOR) & "' not yet supported." severity failure; end architecture; diff --git a/src/mem/ocram/ocram_sdp_wf.vhdl b/src/mem/ocram/ocram_sdp_wf.vhdl index c5bce72d..bba3cf86 100644 --- a/src/mem/ocram/ocram_sdp_wf.vhdl +++ b/src/mem/ocram/ocram_sdp_wf.vhdl @@ -13,6 +13,20 @@ -- * single clock, clock enable, -- * 1 read port plus 1 write port. -- +-- Command truth table: +-- +-- == == =============================== +-- ce we Command +-- == == =============================== +-- 0 X No operation +-- 1 0 Read only from memory +-- 1 1 Read from and Write to memory +-- == == =============================== +-- +-- Both reading and writing are synchronous to the rising-edge of the clock. +-- Thus, when reading, the memory data will be outputted after the +-- clock edge, i.e, in the following clock cycle. +-- -- Mixed-Port Read-During-Write -- When reading at the write address, the read value will be the new data, -- aka. "write-first behavior". Of course, the read is still synchronous, diff --git a/src/mem/ocram/ocram_sp.vhdl b/src/mem/ocram/ocram_sp.vhdl index 63846c2a..bb268cc6 100644 --- a/src/mem/ocram/ocram_sp.vhdl +++ b/src/mem/ocram/ocram_sp.vhdl @@ -155,7 +155,7 @@ begin -- Direct instantiation of altsyncram (including component -- declaration above) is not sufficient for ModelSim. -- That requires also usage of altera_mf library. - i: ocram_sp_altera + ram_altera: ocram_sp_altera generic map ( A_BITS => A_BITS, D_BITS => D_BITS, diff --git a/src/mem/ocram/ocram_tdp.files b/src/mem/ocram/ocram_tdp.files index f94e2625..2f5ac3c9 100644 --- a/src/mem/ocram/ocram_tdp.files +++ b/src/mem/ocram/ocram_tdp.files @@ -16,4 +16,7 @@ if (DeviceVendor = "Altera") then include "lib/Altera.files" vhdl poc "src/mem/ocram/altera/ocram_tdp_altera.vhdl" # Altera specific true dual-port RAM end if +if (Environment = "Simulation") then + vhdl poc "src/mem/ocram/ocram_tdp_sim.vhdl" # Simulation model +end if vhdl poc "src/mem/ocram/ocram_tdp.vhdl" # True dual-port RAM diff --git a/src/mem/ocram/ocram_tdp.vhdl b/src/mem/ocram/ocram_tdp.vhdl index 123ccd09..39999221 100644 --- a/src/mem/ocram/ocram_tdp.vhdl +++ b/src/mem/ocram/ocram_tdp.vhdl @@ -24,16 +24,17 @@ -- 1 1 Write to memory -- === === ================ -- +-- Both reading and writing are synchronous to the rising-edge of the clock. +-- Thus, when reading, the memory data will be outputted after the +-- clock edge, i.e, in the following clock cycle. +-- -- The generalized behavior across Altera and Xilinx FPGAs since -- Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows: -- -- Same-Port Read-During-Write -- When writing data through port 1, the read output of the same port -- (``q1``) will output the new data (``d1``, in the following clock cycle) --- which is aka. "write-first behavior". This behavior also applies to Altera --- M20K memory blocks as described in the Altera: "Stratix 5 Device Handbook" --- (S5-5V1). The documentation in the Altera: "Embedded Memory User Guide" --- (UG-01068) is wrong. +-- which is aka. "write-first behavior". -- -- Same applies to port 2. -- @@ -44,15 +45,12 @@ -- rising-edge of the write clock and (in the worst case) extends -- until the next rising-edge of that write clock. -- --- .. WARNING:: --- The simulated behavior on RT-level is too optimistic. When reading --- at the write address always the new data will be returned. --- --- .. TODO:: Implement correct behavior for RT-level simulation. +-- For simulation, always our dedicated simulation model :ref:`IP:ocram_tdp_sim` +-- is used. -- -- License: -- ============================================================================= --- Copyright 2008-2015 Technische Universitaet Dresden - Germany +-- Copyright 2008-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); @@ -108,7 +106,7 @@ architecture rtl of ocram_tdp is constant DEPTH : positive := 2**A_BITS; begin - gInfer : if (VENDOR = VENDOR_GENERIC) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX) generate + gInfer : if not SIMULATION and ((VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX)) generate -- RAM can be inferred correctly only if '-use_new_parser yes' is enabled in XST options subtype word_t is std_logic_vector(D_BITS - 1 downto 0); type ram_t is array(0 to DEPTH - 1) of word_t; @@ -170,7 +168,7 @@ begin ram(to_integer(a2_reg)); -- returns new data end generate gInfer; - gAltera: if VENDOR = VENDOR_ALTERA generate + gAltera: if not SIMULATION and (VENDOR = VENDOR_ALTERA) generate component ocram_tdp_altera generic ( A_BITS : positive; @@ -197,7 +195,7 @@ begin -- declaration above) is not sufficient for ModelSim. -- That requires also usage of altera_mf library. - ram_tdp: ocram_tdp_altera + ram_altera: ocram_tdp_altera generic map ( A_BITS => A_BITS, D_BITS => D_BITS, @@ -219,7 +217,50 @@ begin ); end generate gAltera; - assert ((VENDOR = VENDOR_ALTERA) or (VENDOR = VENDOR_GENERIC) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX)) + gSim: if SIMULATION generate + -- Use component instantiation so that simulation model can be excluded + -- from synthesis. + component ocram_tdp_sim is + generic ( + A_BITS : positive; + D_BITS : positive; + FILENAME : string); + port ( + clk1 : in std_logic; + clk2 : in std_logic; + ce1 : in std_logic; + ce2 : in std_logic; + we1 : in std_logic; + we2 : in std_logic; + a1 : in unsigned(A_BITS-1 downto 0); + a2 : in unsigned(A_BITS-1 downto 0); + d1 : in std_logic_vector(D_BITS-1 downto 0); + d2 : in std_logic_vector(D_BITS-1 downto 0); + q1 : out std_logic_vector(D_BITS-1 downto 0); + q2 : out std_logic_vector(D_BITS-1 downto 0)); + end component ocram_tdp_sim; + begin + sim_tdp: ocram_tdp_sim + generic map ( + A_BITS => A_BITS, + D_BITS => D_BITS, + FILENAME => FILENAME) + port map ( + clk1 => clk1, + clk2 => clk2, + ce1 => ce1, + ce2 => ce2, + we1 => we1, + we2 => we2, + a1 => a1, + a2 => a2, + d1 => d1, + d2 => d2, + q1 => q1, + q2 => q2); + end generate gSim; + + assert ((VENDOR = VENDOR_ALTERA) or (VENDOR = VENDOR_GENERIC and SIMULATION) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX)) report "Vendor '" & T_VENDOR'image(VENDOR) & "' not yet supported." severity failure; end architecture; diff --git a/src/mem/ocram/ocram_tdp_wf.files b/src/mem/ocram/ocram_tdp_wf.files new file mode 100644 index 00000000..34a7c4b9 --- /dev/null +++ b/src/mem/ocram/ocram_tdp_wf.files @@ -0,0 +1,12 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# ============================================================================== +# Note: all files are relative to PoC root directory +# +# Common PoC packages for configuration, synthesis and simulation +include "src/common/common.files" + +# PoC.mem.ocram +include "src/mem/ocram/ocram_tdp.files" +vhdl poc "src/mem/ocram/ocram_tdp_wf.vhdl" diff --git a/src/mem/ocram/ocram_tdp_wf.vhdl b/src/mem/ocram/ocram_tdp_wf.vhdl new file mode 100644 index 00000000..95594f30 --- /dev/null +++ b/src/mem/ocram/ocram_tdp_wf.vhdl @@ -0,0 +1,191 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Martin Zabel +-- Patrick Lehmann +-- +-- Entity: True dual-port memory with write-first behavior. +-- +-- Description: +-- ------------------------------------- +-- Inferring / instantiating true dual-port memory, with: +-- +-- * single clock, clock enable, +-- * 2 read/write ports. +-- +-- Command truth table: +-- +-- == === === ===================================================== +-- ce we1 we2 Command +-- == === === ===================================================== +-- 0 X X No operation +-- 1 0 0 Read only from memory +-- 1 0 1 Read from memory on port 1, write to memory on port 2 +-- 1 1 0 Write to memory on port 1, read from memory on port 2 +-- 1 1 1 Write to memory on both ports +-- == === === ===================================================== +-- +-- Both reads and writes are synchronous to the clock. +-- +-- The generalized behavior across Altera and Xilinx FPGAs since +-- Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows: +-- +-- Same-Port Read-During-Write +-- When writing data through port 1, the read output of the same port +-- (``q1``) will output the new data (``d1``, in the following clock cycle) +-- which is aka. "write-first behavior". +-- +-- Same applies to port 2. +-- +-- Mixed-Port Read-During-Write +-- When reading at the write address, the read value will be the new data, +-- aka. "write-first behavior". Of course, the read is still synchronous, +-- i.e, the latency is still one clock cyle. +-- +-- If a write is issued on both ports to the same address, then the output of +-- this unit and the content of the addressed memory cell are undefined. +-- +-- For simulation, always our dedicated simulation model :ref:`IP:ocram_tdp_sim` +-- is used. +-- +-- License: +-- ============================================================================= +-- Copyright 2008-2016 Technische Universitaet Dresden - Germany +-- Chair of VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library PoC; +use PoC.config.all; +use PoC.utils.all; +use PoC.strings.all; +use PoC.vectors.all; +use PoC.mem.all; + + +entity ocram_tdp_wf is + generic ( + A_BITS : positive; -- number of address bits + D_BITS : positive; -- number of data bits + FILENAME : string := "" -- file-name for RAM initialization + ); + port ( + clk : in std_logic; -- clock + ce : in std_logic; -- clock-enable + we1 : in std_logic; -- write-enable for 1st port + we2 : in std_logic; -- write-enable for 2nd port + a1 : in unsigned(A_BITS-1 downto 0); -- address for 1st port + a2 : in unsigned(A_BITS-1 downto 0); -- address for 2nd port + d1 : in std_logic_vector(D_BITS-1 downto 0); -- write-data for 1st port + d2 : in std_logic_vector(D_BITS-1 downto 0); -- write-data for 2nd port + q1 : out std_logic_vector(D_BITS-1 downto 0); -- read-data from 1st port + q2 : out std_logic_vector(D_BITS-1 downto 0) -- read-data from 2nd port + ); +end entity; + + +architecture rtl of ocram_tdp_wf is + -- Two read/write ports are only supported in true-dual port block memories + -- on FPGAs. But not all synthesis tools, do infer the required bypass logic + -- as already shown for :ref:`IP:ocram_sdp_wf`. + -- Thus, bypass logic has to be explicitly described to get the intended + -- write-first behavior. + + signal wd1_r : std_logic_vector(d1'range); -- write data from port 1 + signal wd2_r : std_logic_vector(d2'range); -- write data from port 2 + signal fwd1_r : std_logic; -- forward write data from port 1 to port 2 + signal fwd2_r : std_logic; -- forward write data from port 2 to port 1 + signal ram_q1 : std_logic_vector(q1'range); -- RAM output, port 1 + signal ram_q2 : std_logic_vector(q2'range); -- RAM output, port 2 + + -- Compares two addresses, returns 'X' if either ``a1`` or ``a2`` contains + -- meta-values, otherwise returns '1' if ``a1 == a2`` is true else + -- '0'. Returns 'X' even when the addresses contain '-' values, to signal an + -- undefined outcome. + function addr_equal(a1 : unsigned; a2 : unsigned) return X01 is + begin + -- synthesis translate_off + if is_x(a1) or is_x(a2) then return 'X'; end if; + -- synthesis translate_on + if to_x01(std_logic_vector(a1)) = to_x01(std_logic_vector(a2)) then + return '1'; + end if; + return '0'; + end function; + +begin + process(clk) + variable addr_eq : X01; + begin + if rising_edge(clk) then + case to_x01(ce) is + when '1' => + wd1_r <= to_x01(d1); + wd2_r <= to_x01(d2); + addr_eq := addr_equal(a1, a2); + fwd1_r <= addr_eq and we1; + fwd2_r <= addr_eq and we2; + + when '0' => null; -- keep previous state + + when others => -- X propagation in simulation + wd1_r <= (others => 'X'); + fwd1_r <= 'X'; + fwd2_r <= 'X'; + end case; + + if SIMULATION then + if (fwd1_r and fwd2_r) = '1' then + report "ERROR: both ports write to the same address." severity error; + end if; + end if; + end if; + end process; + + ram_tdp: entity work.ocram_tdp + generic map ( + A_BITS => A_BITS, + D_BITS => D_BITS, + FILENAME => FILENAME) + port map ( + clk1 => clk, + clk2 => clk, + ce1 => ce, + ce2 => ce, + we1 => we1, + we2 => we2, + a1 => a1, + a2 => a2, + d1 => d1, + d2 => d2, + q1 => ram_q1, + q2 => ram_q2); + + with fwd1_r select q2 <= + wd1_r when '1', + ram_q2 when '0', + (others => 'X') when others; -- X propagation in simulation + + with fwd2_r select q1 <= + wd2_r when '1', + ram_q1 when '0', + (others => 'X') when others; -- X propagation in simulation + +end architecture; diff --git a/tb/mem/ocram/ocram_esdp_tb.vhdl b/tb/mem/ocram/ocram_esdp_tb.vhdl index eb28b482..04f6cbe6 100644 --- a/tb/mem/ocram/ocram_esdp_tb.vhdl +++ b/tb/mem/ocram/ocram_esdp_tb.vhdl @@ -48,160 +48,300 @@ end entity; architecture tb of ocram_esdp_tb is constant CLOCK_FREQ : FREQ := 100 MHz; - -- clock - signal clk : std_logic; - -- component generics -- Set to values used for synthesis when simulating a netlist. - constant A_BITS : positive := 10; - constant D_BITS : positive := 32; - - -- component ports - signal ce1 : std_logic; - signal ce2 : std_logic; - signal we1 : std_logic; - signal a1 : unsigned(A_BITS-1 downto 0); - signal a2 : unsigned(A_BITS-1 downto 0); - signal d1 : std_logic_vector(D_BITS-1 downto 0); - signal q1 : std_logic_vector(D_BITS-1 downto 0); - signal q2 : std_logic_vector(D_BITS-1 downto 0); - - -- Expected read data, assign together with read command - signal rd_d1 : std_logic_vector(D_BITS-1 downto 0); - signal rd_d2 : std_logic_vector(D_BITS-1 downto 0); - - -- Derived expected output on q1 / q2. - signal exp_q1 : std_logic_vector(D_BITS-1 downto 0) := (others => '-'); - signal exp_q2 : std_logic_vector(D_BITS-1 downto 0) := (others => '-'); - - -- Signaling between Stimuli and Checker process - signal finished : boolean := false; + constant A_BITS : positive := 8; + constant D_BITS : positive := 16; + + -- test configurations + type T_TEST_CONFIG is record + phase1 : T_PHASE; -- phase of clk1 + phase2 : T_PHASE; -- phase of clk2 + end record; + + type T_TEST_CONFIG_VEC is array (natural range<>) of T_TEST_CONFIG; + -- phase = 0 means 360 degrees + constant TEST_CONFIGS : T_TEST_CONFIG_VEC := ( + 0 => (phase1 => 180 deg, phase2 => 180 deg), -- clocks in-phase (including delta cyle) + 1 => (phase1 => 180 deg, phase2 => 90 deg), -- provoke mixed-port read-during-write + 2 => (phase1 => 90 deg, phase2 => 180 deg) -- dito + ); begin -- initialize global simulation status simInitialize; - -- generate global testbench clock - simGenerateClock(clk, CLOCK_FREQ); - - -- component instantiation - DUT: entity poc.ocram_esdp - generic map ( - A_BITS => A_BITS, - D_BITS => D_BITS, - FILENAME => "") - port map ( - clk1 => clk, - clk2 => clk, - ce1 => ce1, - ce2 => ce2, - we1 => we1, - a1 => a1, - a2 => a2, - d1 => d1, - q1 => q1, - q2 => q2); - - -- waveform generation - Stimuli: process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Stimuli process"); - begin - -- No operation on first rising clock edge - ce1 <= '0'; - we1 <= '-'; - a1 <= (others => '-'); - d1 <= (others => '-'); - rd_d1 <= (others => '-'); - ce2 <= '0'; - a2 <= (others => '-'); - rd_d2 <= (others => '-'); - - ------------------------------------------------------------------------- - -- Write in 8 consecutive clock cycles, read one cycle later - - for i in 0 to 7 loop - simWaitUntilRisingEdge(clk, 1); - ce1 <= '1'; - we1 <= '1'; - a1 <= to_unsigned(i, a1'length); - d1 <= std_logic_vector(to_unsigned(i, d1'length)); - rd_d1 <= std_logic_vector(to_unsigned(i, d1'length)); - - -- read is delayed by one clock cycle - ce2 <= ce1; - a2 <= a1; - rd_d2 <= d1; -- data to be read - end loop; - - simWaitUntilRisingEdge(clk, 1); - ce1 <= '0'; - we1 <= '0'; - a1 <= (others => '-'); - rd_d1 <= (others => '-'); - - -- last read is delayed by one clock cycle - ce2 <= ce1; - a2 <= a1; - rd_d2 <= d1; -- data to be read - - ------------------------------------------------------------------------- - -- Alternating write / read - for i in 8 to 15 loop - simWaitUntilRisingEdge(clk, 1); - ce1 <= not ce1; -- write @ even addresses - we1 <= '1'; - a1 <= to_unsigned(i, a1'length); - d1 <= std_logic_vector(to_unsigned(i, d1'length)); - rd_d1 <= std_logic_vector(to_unsigned(i, d1'length)); - - -- read is delayed by one clock cycle - ce2 <= ce1; - a2 <= a1; - rd_d2 <= d1; -- data to be read - end loop; - - simWaitUntilRisingEdge(clk, 1); - ce1 <= '0'; - we1 <= '0'; - a1 <= (others => '-'); - rd_d1 <= (others => '-'); - - -- last read is delayed by one clock cycle - ce2 <= ce1; - a2 <= a1; - rd_d2 <= d1; -- data to be read - - ------------------------------------------------------------------------- - -- Finish - simWaitUntilRisingEdge(clk, 1); - ce2 <= '0'; - a2 <= (others => '-'); - - finished <= true; - - -- This process is finished - simDeactivateProcess(simProcessID); - wait; -- forever - end process Stimuli; - - -- Also checks if old value is kept if ce1 = '0' - exp_q1 <= rd_d1 when rising_edge(clk) and ce1 = '1'; - - -- Also checks if old value is kept if ce2 = '0' - exp_q2 <= rd_d2 when rising_edge(clk) and ce2 = '1'; - - Checker: process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Checker process"); - variable i : integer; - begin - while not finished loop - simWaitUntilRisingEdge(clk, 1); - simAssertion(std_match(q1, exp_q1)); - simAssertion(std_match(q2, exp_q2)); - end loop; - - -- This process is finished - simDeactivateProcess(simProcessID); - wait; -- forever - end process Checker; + + gTest: for test in TEST_CONFIGS'range generate + constant CLOCK1_PHASE : T_PHASE := TEST_CONFIGS(test).phase1; + constant CLOCK2_PHASE : T_PHASE := TEST_CONFIGS(test).phase2; + + constant simTestID : T_SIM_TEST_ID := simCreateTest("Phase1="&integer'image(CLOCK1_PHASE / 1 deg)& + " Phase2="&integer'image(CLOCK2_PHASE / 1 deg)); + + -- component ports + signal clk1 : std_logic; + signal clk2 : std_logic; + signal ce1 : std_logic; + signal ce2 : std_logic; + signal we1 : std_logic; + signal a1 : unsigned(A_BITS-1 downto 0); + signal a2 : unsigned(A_BITS-1 downto 0); + signal d1 : std_logic_vector(D_BITS-1 downto 0); + signal q1 : std_logic_vector(D_BITS-1 downto 0); + signal q2 : std_logic_vector(D_BITS-1 downto 0); + + -- Expected read data, assign together with read command + -- Set to '-'es when result doesn't care. + -- Set to 'X'es when expecting unknown result due to mixed-port collision. + signal rd_d1 : std_logic_vector(D_BITS-1 downto 0); + signal rd_d2 : std_logic_vector(D_BITS-1 downto 0); + + -- Derived expected output on q1 / q2. + signal exp_q1 : std_logic_vector(D_BITS-1 downto 0) := (others => '-'); + signal exp_q2 : std_logic_vector(D_BITS-1 downto 0) := (others => '-'); + + -- Signaling between Stimuli and Checker process + signal finished1 : boolean := false; + signal finished2 : boolean := false; + + begin + -- generate global testbench clock + simGenerateClock(simTestID, clk1, CLOCK_FREQ, CLOCK1_PHASE); + simGenerateClock(simTestID, clk2, CLOCK_FREQ, CLOCK2_PHASE); + + -- component instantiation + UUT: entity poc.ocram_esdp + generic map ( + A_BITS => A_BITS, + D_BITS => D_BITS, + FILENAME => "") + port map ( + clk1 => clk1, + clk2 => clk2, + ce1 => ce1, + ce2 => ce2, + we1 => we1, + a1 => a1, + a2 => a2, + d1 => d1, + q1 => q1, + q2 => q2); + + -- Input stimuli for Port 1 + -- =========================================================================== + Stimuli1: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "TestID "&integer'image(simTestID)&", Stimuli1"); + begin + -- No operation on first rising clock edge + ce1 <= '0'; + we1 <= '-'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + + -- Write in 8 consecutive clock cycles on port 1, read one cycle later on + -- port 2 + ------------------------------------------------------------------------- + for i in 0 to 7 loop + simWaitUntilRisingEdge(clk1, 1); + ce1 <= '1'; + we1 <= '1'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + simWaitUntilRisingEdge(clk1, 1); + -- last read on port 2 here + ce1 <= '0'; + we1 <= '0'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + + -- Alternating write on port 1 / read on port 2 + ------------------------------------------------------------------------- + for i in 8 to 15 loop + simWaitUntilRisingEdge(clk1, 1); + ce1 <= not ce1; -- write @ even addresses + we1 <= '1'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + simWaitUntilRisingEdge(clk1, 1); + -- last read on port 2 here + ce1 <= '0'; + we1 <= '0'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + + -- Read in 8 consecutive clock cycles on port 2, write one cycle later on + -- port 1 + ------------------------------------------------------------------------- + simWaitUntilRisingEdge(clk1, 1); + -- first read on port 2 here + ce1 <= '0'; + we1 <= '0'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + + for i in 56 to 63 loop + simWaitUntilRisingEdge(clk1, 1); + ce1 <= '1'; + we1 <= '1'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + ------------------------------------------------------------------------- + -- Finish + simWaitUntilRisingEdge(clk1, 1); + ce1 <= '0'; + we1 <= '-'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + + -- This process is finished + finished1 <= true; + simDeactivateProcess(simProcessID); + wait; -- forever + end process Stimuli1; + + -- Input stimuli for Port 2 + -- =========================================================================== + Stimuli2: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "TestID "&integer'image(simTestID)&", Stimuli2"); + begin + -- No operation on first rising clock edge + ce2 <= '0'; + a2 <= (others => '-'); + rd_d2 <= (others => '-'); + + -- Write in 8 consecutive clock cycles on port 1, read one cycle later on + -- port 2 + ------------------------------------------------------------------------- + simWaitUntilRisingEdge(clk2, 1); + -- first write on port 1 here + ce2 <= '0'; + a2 <= (others => '-'); + rd_d2 <= (others => '-'); + + for i in 0 to 7 loop + simWaitUntilRisingEdge(clk2, 1); + ce2 <= '1'; + a2 <= to_unsigned(i, A_BITS); + if CLOCK2_PHASE >= CLOCK1_PHASE then + -- read succeeds either if clocks are in phase or read clock is + -- behind write clock + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + else + -- read-during-write at same address + rd_d2 <= (others => 'X'); + end if; + end loop; + + -- Alternating write on port 1 / read on port 2 + ------------------------------------------------------------------------- + simWaitUntilRisingEdge(clk2, 1); + -- first write on port 1 here + ce2 <= '0'; + a2 <= (others => '-'); + rd_d2 <= (others => '-'); + + for i in 8 to 15 loop + simWaitUntilRisingEdge(clk2, 1); + ce2 <= not ce2; + a2 <= to_unsigned(i, A_BITS); + if CLOCK2_PHASE >= CLOCK1_PHASE then + -- read succeeds either if clocks are in phase or read clock is + -- behind write clock + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + else + -- read-during-write at same address + rd_d2 <= (others => 'X'); + end if; + end loop; + + -- Read in 8 consecutive clock cycles on port 2, write one cycle later on + -- port 1 + ------------------------------------------------------------------------- + for i in 56 to 63 loop + simWaitUntilRisingEdge(clk2, 1); + ce2 <= '1'; + a2 <= to_unsigned(i, A_BITS); + if CLOCK2_PHASE <= CLOCK1_PHASE then + -- read succeeds if clocks are in phase or if read clock is before + -- write clock + rd_d2 <= (others => 'U'); -- memory not yet initialized + else + -- write-during-read at same address + rd_d2 <= (others => 'X'); + end if; + end loop; + + simWaitUntilRisingEdge(clk2, 1); + -- last write on port 1 here + ce2 <= '0'; + a2 <= (others => '-'); + rd_d2 <= (others => '-'); + + ------------------------------------------------------------------------- + -- Finish + simWaitUntilRisingEdge(clk2, 1); + ce2 <= '0'; + a2 <= (others => '-'); + rd_d2 <= (others => '-'); + + -- This process is finished + finished2 <= true; + simDeactivateProcess(simProcessID); + wait; -- forever + end process Stimuli2; + + -- Checker + -- =========================================================================== + + -- Also checks if old value is kept if ce1 = '0' + exp_q1 <= rd_d1 when rising_edge(clk1) and ce1 = '1'; + + -- Also checks if old value is kept if ce2 = '0' + exp_q2 <= rd_d2 when rising_edge(clk2) and ce2 = '1'; + + Checker1: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "TestID "&integer'image(simTestID)&", Checker1"); + variable i : integer; + begin + while not finished1 loop + simWaitUntilRisingEdge(clk1, 1); + simAssertion((q1 = exp_q1) or -- also matches 'X'es + std_match(q1, exp_q1)); -- also matches '-'es + end loop; + + -- This process is finished + simDeactivateProcess(simProcessID); + wait; -- forever + end process Checker1; + + Checker2: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "TestID "&integer'image(simTestID)&", Checker2"); + variable i : integer; + begin + while not finished2 loop + simWaitUntilRisingEdge(clk2, 1); + simAssertion((q2 = exp_q2) or -- also matches 'X'es + std_match(q2, exp_q2)); -- also matches '-'es + end loop; + + -- This process is finished + simDeactivateProcess(simProcessID); + wait; -- forever + end process Checker2; + end generate gTest; end architecture; diff --git a/tb/mem/ocram/ocram_sdp_tb.vhdl b/tb/mem/ocram/ocram_sdp_tb.vhdl index b42f4aca..5203bdf2 100644 --- a/tb/mem/ocram/ocram_sdp_tb.vhdl +++ b/tb/mem/ocram/ocram_sdp_tb.vhdl @@ -50,115 +50,268 @@ architecture tb of ocram_sdp_tb is -- component generics -- Set to values used for synthesis when simulating a netlist. - constant A_BITS : positive := 10; - constant D_BITS : positive := 32; + constant A_BITS : positive := 8; + constant D_BITS : positive := 16; - -- component ports - signal rce : std_logic; - signal wce : std_logic; - signal we : std_logic; - signal ra : unsigned(A_BITS-1 downto 0); - signal wa : unsigned(A_BITS-1 downto 0); - signal d : std_logic_vector(D_BITS-1 downto 0); - signal q : std_logic_vector(D_BITS-1 downto 0); + -- test configurations + type T_TEST_CONFIG is record + phase1 : T_PHASE; -- phase of clk1 + phase2 : T_PHASE; -- phase of clk2 + end record; - -- clock - signal clk : std_logic; + type T_TEST_CONFIG_VEC is array (natural range<>) of T_TEST_CONFIG; + -- phase = 0 means 360 degrees + constant TEST_CONFIGS : T_TEST_CONFIG_VEC := ( + 0 => (phase1 => 180 deg, phase2 => 180 deg), -- clocks in-phase (including delta cyle) + 1 => (phase1 => 180 deg, phase2 => 90 deg), -- provoke mixed-port read-during-write + 2 => (phase1 => 90 deg, phase2 => 180 deg) -- dito + ); begin -- initialize global simulation status simInitialize; - -- generate global testbench clock - simGenerateClock(clk, CLOCK_FREQ); - - -- component instantiation - UUT: entity PoC.ocram_sdp - generic map( - A_BITS => A_BITS, - D_BITS => D_BITS - ) - port map ( - rclk => clk, - rce => rce, - wclk => clk, - wce => wce, - we => we, - ra => ra, - wa => wa, - d => d, - q => q - ); - - -- waveform generation - WaveGen_Proc: process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Stimuli process"); - begin - -- insert signal assignments here - ra <= (others => '0'); - wa <= (others => '0'); - rce <= '0'; - wce <= '0'; - we <= '0'; - simWaitUntilRisingEdge(clk, 2); - - wait until falling_edge(clk); - - d <= x"11111111"; - we <= '1'; - wce <= '1'; - rce <= '0'; - wait until falling_edge(clk); - - we <= '0'; - wce <= '1'; - rce <= '1'; -- normal read after write - wait until falling_edge(clk); - simAssertion((q = x"11111111"), "Wrong read data1"); - - d <= x"22222222"; - we <= '1'; - wce <= '1'; - rce <= '1'; -- read-during-write on opposite port - wait until falling_edge(clk); - - we <= '0'; - wce <= '1'; - rce <= '1'; -- read again - wait until falling_edge(clk); - simAssertion((q = x"22222222"), "Wrong read data1"); - - d <= x"33333333"; - we <= '1'; -- write new value - wce <= '1'; - rce <= '0'; -- no read - wait until falling_edge(clk); - simAssertion((q = x"22222222"), "Wrong read data1"); - - we <= '0'; -- no write - wce <= '1'; - rce <= '0'; -- no read - wait until falling_edge(clk); - simAssertion((q = x"22222222"), "Wrong read data1"); - - d <= x"44444444"; - we <= '1'; - wce <= '1'; - rce <= '1'; -- read-during-write on opposite port - wait until falling_edge(clk); - - d <= x"55555555"; - we <= '1'; - wce <= '0'; -- write clock disabled - rce <= '1'; -- should be normal read - wait until falling_edge(clk); - simAssertion((q = x"44444444"), "Wrong read data1"); - - we <= '0'; - wce <= '0'; - rce <= '0'; - - -- This process is finished - simDeactivateProcess(simProcessID); - wait; -- forever - end process WaveGen_Proc; + + gTest: for test in TEST_CONFIGS'range generate + constant CLOCK1_PHASE : T_PHASE := TEST_CONFIGS(test).phase1; + constant CLOCK2_PHASE : T_PHASE := TEST_CONFIGS(test).phase2; + + constant simTestID : T_SIM_TEST_ID := simCreateTest("Phase1="&integer'image(CLOCK1_PHASE / 1 deg)& + " Phase2="&integer'image(CLOCK2_PHASE / 1 deg)); + + -- component ports + signal clk1 : std_logic; + signal clk2 : std_logic; + signal ce1 : std_logic; + signal ce2 : std_logic; + signal we1 : std_logic; + signal a1 : unsigned(A_BITS-1 downto 0); + signal a2 : unsigned(A_BITS-1 downto 0); + signal d1 : std_logic_vector(D_BITS-1 downto 0); + signal q2 : std_logic_vector(D_BITS-1 downto 0); + + -- Expected read data, assign together with read command + -- Set to '-'es when result doesn't care. + -- Set to 'X'es when expecting unknown result due to mixed-port collision. + signal rd_d2 : std_logic_vector(D_BITS-1 downto 0); + + -- Derived expected output on q1 / q2. + signal exp_q2 : std_logic_vector(D_BITS-1 downto 0) := (others => '-'); + + -- Signaling between Stimuli and Checker process + signal finished1 : boolean := false; + signal finished2 : boolean := false; + + begin + -- generate global testbench clock + simGenerateClock(simTestID, clk1, CLOCK_FREQ, CLOCK1_PHASE); + simGenerateClock(simTestID, clk2, CLOCK_FREQ, CLOCK2_PHASE); + + -- component instantiation + UUT: entity poc.ocram_sdp + generic map ( + A_BITS => A_BITS, + D_BITS => D_BITS, + FILENAME => "") + port map ( + wclk => clk1, + rclk => clk2, + wce => ce1, + rce => ce2, + we => we1, + wa => a1, + ra => a2, + d => d1, + q => q2); + + -- Input stimuli for Port 1 (Write) + -- =========================================================================== + Stimuli1: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "TestID "&integer'image(simTestID)&", Stimuli1"); + begin + -- No operation on first rising clock edge + ce1 <= '0'; + we1 <= '-'; + a1 <= (others => '-'); + d1 <= (others => '-'); + + -- Write in 8 consecutive clock cycles on port 1, read one cycle later on + -- port 2 + ------------------------------------------------------------------------- + for i in 0 to 7 loop + simWaitUntilRisingEdge(clk1, 1); + ce1 <= '1'; + we1 <= '1'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + simWaitUntilRisingEdge(clk1, 1); + -- last read on port 2 here + ce1 <= '0'; + we1 <= '0'; + a1 <= (others => '-'); + d1 <= (others => '-'); + + -- Alternating write on port 1 / read on port 2 + ------------------------------------------------------------------------- + for i in 8 to 15 loop + simWaitUntilRisingEdge(clk1, 1); + ce1 <= not ce1; -- write @ even addresses + we1 <= '1'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + simWaitUntilRisingEdge(clk1, 1); + -- last read on port 2 here + ce1 <= '0'; + we1 <= '0'; + a1 <= (others => '-'); + d1 <= (others => '-'); + + -- Read in 8 consecutive clock cycles on port 2, write one cycle later on + -- port 1 + ------------------------------------------------------------------------- + simWaitUntilRisingEdge(clk1, 1); + -- first read on port 2 here + ce1 <= '0'; + we1 <= '0'; + a1 <= (others => '-'); + d1 <= (others => '-'); + + for i in 56 to 63 loop + simWaitUntilRisingEdge(clk1, 1); + ce1 <= '1'; + we1 <= '1'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + ------------------------------------------------------------------------- + -- Finish + simWaitUntilRisingEdge(clk1, 1); + ce1 <= '0'; + we1 <= '-'; + a1 <= (others => '-'); + d1 <= (others => '-'); + + -- This process is finished + finished1 <= true; + simDeactivateProcess(simProcessID); + wait; -- forever + end process Stimuli1; + + -- Input stimuli for Port 2 (Read) + -- =========================================================================== + Stimuli2: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "TestID "&integer'image(simTestID)&", Stimuli2"); + begin + -- No operation on first rising clock edge + ce2 <= '0'; + a2 <= (others => '-'); + rd_d2 <= (others => '-'); + + -- Write in 8 consecutive clock cycles on port 1, read one cycle later on + -- port 2 + ------------------------------------------------------------------------- + simWaitUntilRisingEdge(clk2, 1); + -- first write on port 1 here + ce2 <= '0'; + a2 <= (others => '-'); + rd_d2 <= (others => '-'); + + for i in 0 to 7 loop + simWaitUntilRisingEdge(clk2, 1); + ce2 <= '1'; + a2 <= to_unsigned(i, A_BITS); + if CLOCK2_PHASE >= CLOCK1_PHASE then + -- read succeeds either if clocks are in phase or read clock is + -- behind write clock + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + else + -- read-during-write at same address + rd_d2 <= (others => 'X'); + end if; + end loop; + + -- Alternating write on port 1 / read on port 2 + ------------------------------------------------------------------------- + simWaitUntilRisingEdge(clk2, 1); + -- first write on port 1 here + ce2 <= '0'; + a2 <= (others => '-'); + rd_d2 <= (others => '-'); + + for i in 8 to 15 loop + simWaitUntilRisingEdge(clk2, 1); + ce2 <= not ce2; + a2 <= to_unsigned(i, A_BITS); + if CLOCK2_PHASE >= CLOCK1_PHASE then + -- read succeeds either if clocks are in phase or read clock is + -- behind write clock + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + else + -- read-during-write at same address + rd_d2 <= (others => 'X'); + end if; + end loop; + + -- Read in 8 consecutive clock cycles on port 2, write one cycle later on + -- port 1 + ------------------------------------------------------------------------- + for i in 56 to 63 loop + simWaitUntilRisingEdge(clk2, 1); + ce2 <= '1'; + a2 <= to_unsigned(i, A_BITS); + if CLOCK2_PHASE <= CLOCK1_PHASE then + -- read succeeds if clocks are in phase or if read clock is before + -- write clock + rd_d2 <= (others => 'U'); -- memory not yet initialized + else + -- write-during-read at same address + rd_d2 <= (others => 'X'); + end if; + end loop; + + simWaitUntilRisingEdge(clk2, 1); + -- last write on port 1 here + ce2 <= '0'; + a2 <= (others => '-'); + rd_d2 <= (others => '-'); + + ------------------------------------------------------------------------- + -- Finish + simWaitUntilRisingEdge(clk2, 1); + ce2 <= '0'; + a2 <= (others => '-'); + rd_d2 <= (others => '-'); + + -- This process is finished + finished2 <= true; + simDeactivateProcess(simProcessID); + wait; -- forever + end process Stimuli2; + + -- Checker + -- =========================================================================== + + -- Also checks if old value is kept if ce2 = '0' + exp_q2 <= rd_d2 when rising_edge(clk2) and ce2 = '1'; + + Checker2: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "TestID "&integer'image(simTestID)&", Checker2"); + variable i : integer; + begin + while not finished2 loop + simWaitUntilRisingEdge(clk2, 1); + simAssertion((q2 = exp_q2) or -- also matches 'X'es + std_match(q2, exp_q2)); -- also matches '-'es + end loop; + + -- This process is finished + simDeactivateProcess(simProcessID); + wait; -- forever + end process Checker2; + end generate gTest; + end architecture; diff --git a/tb/mem/ocram/ocram_sdp_wf_tb.vhdl b/tb/mem/ocram/ocram_sdp_wf_tb.vhdl index 88f0aa63..4744c3c1 100644 --- a/tb/mem/ocram/ocram_sdp_wf_tb.vhdl +++ b/tb/mem/ocram/ocram_sdp_wf_tb.vhdl @@ -132,7 +132,7 @@ begin for i in 8 to 15 loop simWaitUntilRisingEdge(clk, 1); ce <= '1'; - we1 <= '1'; + we1 <= not we1; a1 <= to_unsigned(i, A_BITS); d1 <= std_logic_vector(to_unsigned(i, D_BITS)); end loop; @@ -162,9 +162,9 @@ begin d1 <= std_logic_vector(to_unsigned(i, D_BITS)); end loop; - -- Read and write in 8 consecutive clock cycles at the same time + -- Read and write in 8 consecutive clock cycles at the same address ------------------------------------------------------------------------- - for i in 24 to 31 loop + for i in 64 to 71 loop simWaitUntilRisingEdge(clk, 1); ce <= '1'; we1 <= '1'; @@ -172,9 +172,9 @@ begin d1 <= std_logic_vector(to_unsigned(i, D_BITS)); end loop; - -- Read and write 8 times at the same time every second clock cycle + -- Read and write 8 times at the same address every second clock cycle ------------------------------------------------------------------------- - for i in 32 to 47 loop + for i in 72 to 87 loop simWaitUntilRisingEdge(clk, 1); ce <= not ce; we1 <= '1'; @@ -200,6 +200,7 @@ begin -- =========================================================================== Stimuli2: process constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Stimuli2"); + variable re2 : boolean; begin -- No operation on first rising clock edge a2 <= (others => '-'); @@ -223,13 +224,19 @@ begin ------------------------------------------------------------------------- simWaitUntilRisingEdge(clk, 1); -- first write on port 1 here + re2 := false; a2 <= (others => '-'); rd_d2 <= (others => '-'); for i in 8 to 15 loop simWaitUntilRisingEdge(clk, 1); + re2 := not re2; -- only compare read result every second cycle a2 <= to_unsigned(i, A_BITS); - rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + if re2 then + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + else + rd_d2 <= (others => '-'); + end if; end loop; -- Read in 8 consecutive clock cycles on port 2, write one cycle later on @@ -246,17 +253,17 @@ begin a2 <= (others => '-'); rd_d2 <= (others => '-'); - -- Read and write in 8 consecutive clock cycles at the same time + -- Read and write in 8 consecutive clock cycles at the same address ------------------------------------------------------------------------- - for i in 24 to 31 loop + for i in 64 to 71 loop simWaitUntilRisingEdge(clk, 1); a2 <= to_unsigned(i, A_BITS); rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); end loop; - -- Read and write 8 times at the same time every second clock cycle + -- Read and write 8 times at the same address every second clock cycle ------------------------------------------------------------------------- - for i in 32 to 47 loop + for i in 72 to 87 loop simWaitUntilRisingEdge(clk, 1); a2 <= to_unsigned(i, A_BITS); rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); diff --git a/tb/mem/ocram/ocram_tdp_tb.vhdl b/tb/mem/ocram/ocram_tdp_tb.vhdl index 51cae942..9125b08a 100644 --- a/tb/mem/ocram/ocram_tdp_tb.vhdl +++ b/tb/mem/ocram/ocram_tdp_tb.vhdl @@ -48,239 +48,603 @@ end entity; architecture tb of ocram_tdp_tb is constant CLOCK_FREQ : FREQ := 100 MHz; - -- clock - signal clk : std_logic; - -- component generics -- Set to values used for synthesis when simulating a netlist. - constant A_BITS : positive := 10; - constant D_BITS : positive := 32; - - -- component ports - signal ce1 : std_logic; - signal ce2 : std_logic; - signal we1 : std_logic; - signal we2 : std_logic; - signal a1 : unsigned(A_BITS-1 downto 0); - signal a2 : unsigned(A_BITS-1 downto 0); - signal d1 : std_logic_vector(D_BITS-1 downto 0); - signal d2 : std_logic_vector(D_BITS-1 downto 0); - signal q1 : std_logic_vector(D_BITS-1 downto 0); - signal q2 : std_logic_vector(D_BITS-1 downto 0); - - -- Expected read data, assign together with read command - signal rd_d1 : std_logic_vector(D_BITS-1 downto 0); - signal rd_d2 : std_logic_vector(D_BITS-1 downto 0); - - -- Derived expected output on q1 / q2. - signal exp_q1 : std_logic_vector(D_BITS-1 downto 0) := (others => '-'); - signal exp_q2 : std_logic_vector(D_BITS-1 downto 0) := (others => '-'); - - -- Signaling between Stimuli and Checker process - signal finished : boolean := false; - + constant A_BITS : positive := 8; + constant D_BITS : positive := 16; + + -- test configurations + type T_TEST_CONFIG is record + phase1 : T_PHASE; -- phase of clk1 + phase2 : T_PHASE; -- phase of clk2 + end record; + + type T_TEST_CONFIG_VEC is array (natural range<>) of T_TEST_CONFIG; + + -- phase = 0 means 360 degrees + constant TEST_CONFIGS : T_TEST_CONFIG_VEC := ( + 0 => (phase1 => 180 deg, phase2 => 180 deg), -- clocks in-phase (including delta cyle) + 1 => (phase1 => 180 deg, phase2 => 90 deg), -- provoke mixed-port read-during-write + 2 => (phase1 => 90 deg, phase2 => 180 deg) -- dito + ); begin -- initialize global simulation status simInitialize; - -- generate global testbench clock - simGenerateClock(clk, CLOCK_FREQ); - - -- component instantiation - DUT: entity poc.ocram_tdp - generic map ( - A_BITS => A_BITS, - D_BITS => D_BITS, - FILENAME => "") - port map ( - clk1 => clk, - clk2 => clk, - ce1 => ce1, - ce2 => ce2, - we1 => we1, - we2 => we2, - a1 => a1, - a2 => a2, - d1 => d1, - d2 => d2, - q1 => q1, - q2 => q2); - - -- waveform generation - Stimuli: process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Stimuli process"); - begin - -- No operation on first rising clock edge - ce1 <= '0'; - we1 <= '-'; - a1 <= (others => '-'); - d1 <= (others => '-'); - rd_d1 <= (others => '-'); - ce2 <= '0'; - we2 <= '-'; - a2 <= (others => '-'); - d2 <= (others => '-'); - rd_d2 <= (others => '-'); - - ------------------------------------------------------------------------- - -- Write in 8 consecutive clock cycles on port 1, read one cycle later on - -- port 2 - - for i in 0 to 7 loop - simWaitUntilRisingEdge(clk, 1); - ce1 <= '1'; - we1 <= '1'; - a1 <= to_unsigned(i, a1'length); - d1 <= std_logic_vector(to_unsigned(i, d1'length)); - rd_d1 <= std_logic_vector(to_unsigned(i, d1'length)); - - -- read is delayed by one clock cycle - ce2 <= ce1; - we2 <= '0'; - a2 <= a1; - rd_d2 <= d1; -- data to be read - end loop; - - simWaitUntilRisingEdge(clk, 1); - ce1 <= '0'; - we1 <= '0'; - a1 <= (others => '-'); - rd_d1 <= (others => '-'); - - -- last read is delayed by one clock cycle - ce2 <= ce1; - we2 <= '0'; - a2 <= a1; - rd_d2 <= d1; -- data to be read - - ------------------------------------------------------------------------- - -- Alternating write on port 1 / read on port 2 - for i in 8 to 15 loop - simWaitUntilRisingEdge(clk, 1); - ce1 <= not ce1; -- write @ even addresses - we1 <= '1'; - a1 <= to_unsigned(i, a1'length); - d1 <= std_logic_vector(to_unsigned(i, d1'length)); - rd_d1 <= std_logic_vector(to_unsigned(i, d1'length)); - - -- read is delayed by one clock cycle - ce2 <= ce1; - we2 <= '0'; - a2 <= a1; - rd_d2 <= d1; -- data to be read - end loop; - - simWaitUntilRisingEdge(clk, 1); - ce1 <= '0'; - we1 <= '0'; - a1 <= (others => '-'); - rd_d1 <= (others => '-'); - - -- last read is delayed by one clock cycle - ce2 <= ce1; - we2 <= '0'; - a2 <= a1; - rd_d2 <= d1; -- data to be read - - simWaitUntilRisingEdge(clk, 1); - ce2 <= '0'; - we2 <= '-'; - a2 <= (others => '-'); - rd_d2 <= (others => '-'); - - ------------------------------------------------------------------------- - -- Write in 8 consecutive clock cycles on port 2, read one cycle later on - -- port 1 - - for i in 16 to 23 loop - simWaitUntilRisingEdge(clk, 1); - ce2 <= '1'; - we2 <= '1'; - a2 <= to_unsigned(i, a1'length); - d2 <= std_logic_vector(to_unsigned(i, d1'length)); - rd_d2 <= std_logic_vector(to_unsigned(i, d1'length)); - - -- read is delayed by one clock cycle - ce1 <= ce2; - we1 <= '0'; - a1 <= a2; - rd_d1 <= d2; -- data to be read - end loop; - - simWaitUntilRisingEdge(clk, 1); - ce2 <= '0'; - we2 <= '0'; - a2 <= (others => '-'); - rd_d2 <= (others => '-'); - - -- last read is delayed by one clock cycle - ce1 <= ce2; - we1 <= '0'; - a1 <= a2; - rd_d1 <= d2; -- data to be read - - ------------------------------------------------------------------------- - -- Alternating write on port 2 / read on port 1 - for i in 24 to 31 loop - simWaitUntilRisingEdge(clk, 1); - ce2 <= not ce2; -- write @ even addresses - we2 <= '1'; - a2 <= to_unsigned(i, a1'length); - d2 <= std_logic_vector(to_unsigned(i, d1'length)); - rd_d2 <= std_logic_vector(to_unsigned(i, d1'length)); - - -- read is delayed by one clock cycle - ce1 <= ce2; - we1 <= '0'; - a1 <= a2; - rd_d1 <= d2; -- data to be read - end loop; - - simWaitUntilRisingEdge(clk, 1); - ce2 <= '0'; - we2 <= '0'; - a2 <= (others => '-'); - rd_d2 <= (others => '-'); - - -- last read is delayed by one clock cycle - ce1 <= ce2; - we1 <= '0'; - a1 <= a2; - rd_d1 <= d2; -- data to be read - - simWaitUntilRisingEdge(clk, 1); - ce1 <= '0'; - we1 <= '-'; - a1 <= (others => '-'); - rd_d1 <= (others => '-'); - - ------------------------------------------------------------------------- - -- Finish - finished <= true; - - -- This process is finished - simDeactivateProcess(simProcessID); - wait; -- forever - end process Stimuli; - - -- Also checks if old value is kept if ce1 = '0' - exp_q1 <= rd_d1 when rising_edge(clk) and ce1 = '1'; - - -- Also checks if old value is kept if ce2 = '0' - exp_q2 <= rd_d2 when rising_edge(clk) and ce2 = '1'; - - Checker: process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Checker process"); - variable i : integer; - begin - while not finished loop - simWaitUntilRisingEdge(clk, 1); - simAssertion(std_match(q1, exp_q1)); - simAssertion(std_match(q2, exp_q2)); - end loop; - - -- This process is finished - simDeactivateProcess(simProcessID); - wait; -- forever - end process Checker; + + gTest: for test in TEST_CONFIGS'range generate + constant CLOCK1_PHASE : T_PHASE := TEST_CONFIGS(test).phase1; + constant CLOCK2_PHASE : T_PHASE := TEST_CONFIGS(test).phase2; + + constant simTestID : T_SIM_TEST_ID := simCreateTest("Phase1="&integer'image(CLOCK1_PHASE / 1 deg)& + " Phase2="&integer'image(CLOCK2_PHASE / 1 deg)); + + -- component ports + signal clk1 : std_logic; + signal clk2 : std_logic; + signal ce1 : std_logic; + signal ce2 : std_logic; + signal we1 : std_logic; + signal we2 : std_logic; + signal a1 : unsigned(A_BITS-1 downto 0); + signal a2 : unsigned(A_BITS-1 downto 0); + signal d1 : std_logic_vector(D_BITS-1 downto 0); + signal d2 : std_logic_vector(D_BITS-1 downto 0); + signal q1 : std_logic_vector(D_BITS-1 downto 0); + signal q2 : std_logic_vector(D_BITS-1 downto 0); + + -- Expected read data, assign together with read command + -- Set to '-'es when result doesn't care. + -- Set to 'X'es when expecting unknown result due to mixed-port collision. + signal rd_d1 : std_logic_vector(D_BITS-1 downto 0); + signal rd_d2 : std_logic_vector(D_BITS-1 downto 0); + + -- Derived expected output on q1 / q2. + signal exp_q1 : std_logic_vector(D_BITS-1 downto 0) := (others => '-'); + signal exp_q2 : std_logic_vector(D_BITS-1 downto 0) := (others => '-'); + + -- Signaling between Stimuli and Checker process + signal finished1 : boolean := false; + signal finished2 : boolean := false; + + begin + -- generate global testbench clock + simGenerateClock(simTestID, clk1, CLOCK_FREQ, CLOCK1_PHASE); + simGenerateClock(simTestID, clk2, CLOCK_FREQ, CLOCK2_PHASE); + + -- component instantiation + UUT: entity poc.ocram_tdp + generic map ( + A_BITS => A_BITS, + D_BITS => D_BITS, + FILENAME => "") + port map ( + clk1 => clk1, + clk2 => clk2, + ce1 => ce1, + ce2 => ce2, + we1 => we1, + we2 => we2, + a1 => a1, + a2 => a2, + d1 => d1, + d2 => d2, + q1 => q1, + q2 => q2); + + -- Input stimuli for Port 1 + -- =========================================================================== + Stimuli1: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "TestID "&integer'image(simTestID)&", Stimuli1"); + begin + -- No operation on first rising clock edge + ce1 <= '0'; + we1 <= '-'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + + -- Write in 8 consecutive clock cycles on port 1, read one cycle later on + -- port 2 + ------------------------------------------------------------------------- + for i in 0 to 7 loop + simWaitUntilRisingEdge(clk1, 1); + ce1 <= '1'; + we1 <= '1'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + simWaitUntilRisingEdge(clk1, 1); + -- last read on port 2 here + ce1 <= '0'; + we1 <= '0'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + + -- Alternating write on port 1 / read on port 2 + ------------------------------------------------------------------------- + for i in 8 to 15 loop + simWaitUntilRisingEdge(clk1, 1); + ce1 <= not ce1; -- write @ even addresses + we1 <= '1'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + simWaitUntilRisingEdge(clk1, 1); + -- last read on port 2 here + ce1 <= '0'; + we1 <= '0'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + + -- Write in 8 consecutive clock cycles on port 2, read one cycle later on + -- port 1 + ------------------------------------------------------------------------- + simWaitUntilRisingEdge(clk1, 1); + -- first write on port 2 here + ce1 <= '0'; + we1 <= '-'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + + for i in 16 to 23 loop + simWaitUntilRisingEdge(clk1, 1); + ce1 <= '1'; + we1 <= '0'; + a1 <= to_unsigned(i, A_BITS); + d1 <= (others => '-'); + if CLOCK1_PHASE >= CLOCK2_PHASE then + -- read succeeds either if clocks are in phase or read clock is + -- behind write clock + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + else + -- read-during-write at same address + rd_d1 <= (others => 'X'); + end if; + end loop; + + -- Alternating write on port 2 / read on port 1 + ------------------------------------------------------------------------- + simWaitUntilRisingEdge(clk1, 1); + -- first write on port 2 here + ce1 <= '0'; + we1 <= '-'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + + for i in 24 to 31 loop + simWaitUntilRisingEdge(clk1, 1); + ce1 <= not ce1; + we1 <= '0'; + a1 <= to_unsigned(i, A_BITS); + d1 <= (others => '-'); + if CLOCK1_PHASE >= CLOCK2_PHASE then + -- read succeeds either if clocks are in phase or read clock is + -- behind write clock + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + else + -- read-during-write at same address + rd_d1 <= (others => 'X'); + end if; + end loop; + + ------------------------------------------------------------------------- + -- Alternate between write on port 1 and write on port 2 to the same + -- address. Data is read again from memory after all writes. + for i in 32 to 39 loop + simWaitUntilRisingEdge(clk1, 1); + ce1 <= '1'; + we1 <= '1'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + + simWaitUntilRisingEdge(clk1, 1); + -- write on port 2 + ce1 <= '0'; + we1 <= '-'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + end loop; + + for i in 32 to 39 loop + simWaitUntilRisingEdge(clk1, 1); + ce1 <= '1'; + we1 <= '0'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + if CLOCK2_PHASE >= CLOCK1_PHASE then + -- write succeeds either if clocks are in phase or if clock of second + -- write is behind clock of first write + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + else + -- write-during-write at same address + rd_d1 <= (others => 'X'); + end if; + end loop; + + ------------------------------------------------------------------------- + -- Alternate between write on port 2 and write on port 1 to the same + -- address. Data is read again from memory after all writes. + for i in 40 to 47 loop + simWaitUntilRisingEdge(clk1, 1); + -- write on port 2 + ce1 <= '0'; + we1 <= '-'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + + simWaitUntilRisingEdge(clk1, 1); + ce1 <= '1'; + we1 <= '1'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + for i in 40 to 47 loop + simWaitUntilRisingEdge(clk1, 1); + ce1 <= '1'; + we1 <= '0'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + if CLOCK1_PHASE >= CLOCK2_PHASE then + -- write succeeds either if clocks are in phase or if clock of second + -- write is behind clock of first write + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + else + -- write-during-write at same address + rd_d1 <= (others => 'X'); + end if; + end loop; + + -- Read in 8 consecutive clock cycles on port 1, write one cycle later on + -- port 2 + ------------------------------------------------------------------------- + for i in 48 to 55 loop + simWaitUntilRisingEdge(clk1, 1); + ce1 <= '1'; + we1 <= '0'; + a1 <= to_unsigned(i, A_BITS); + d1 <= (others => '-'); + if CLOCK1_PHASE <= CLOCK2_PHASE then + -- read succeeds if clocks are in phase or if read clock is before + -- write clock + rd_d1 <= (others => 'U'); -- memory not yet initialized + else + -- write-during-read at same address + rd_d1 <= (others => 'X'); + end if; + end loop; + + simWaitUntilRisingEdge(clk1, 1); + -- last write on port 2 here + ce1 <= '0'; + we1 <= '0'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + + -- Read in 8 consecutive clock cycles on port 2, write one cycle later on + -- port 1 + ------------------------------------------------------------------------- + simWaitUntilRisingEdge(clk1, 1); + -- first read on port 2 here + ce1 <= '0'; + we1 <= '0'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + + for i in 56 to 63 loop + simWaitUntilRisingEdge(clk1, 1); + ce1 <= '1'; + we1 <= '1'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + ------------------------------------------------------------------------- + -- Finish + simWaitUntilRisingEdge(clk1, 1); + ce1 <= '0'; + we1 <= '-'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + + -- This process is finished + finished1 <= true; + simDeactivateProcess(simProcessID); + wait; -- forever + end process Stimuli1; + + -- Input stimuli for Port 2 + -- =========================================================================== + Stimuli2: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "TestID "&integer'image(simTestID)&", Stimuli2"); + begin + -- No operation on first rising clock edge + ce2 <= '0'; + we2 <= '-'; + a2 <= (others => '-'); + d2 <= (others => '-'); + rd_d2 <= (others => '-'); + + -- Write in 8 consecutive clock cycles on port 1, read one cycle later on + -- port 2 + ------------------------------------------------------------------------- + simWaitUntilRisingEdge(clk2, 1); + -- first write on port 1 here + ce2 <= '0'; + we2 <= '-'; + a2 <= (others => '-'); + d2 <= (others => '-'); + rd_d2 <= (others => '-'); + + for i in 0 to 7 loop + simWaitUntilRisingEdge(clk2, 1); + ce2 <= '1'; + we2 <= '0'; + a2 <= to_unsigned(i, A_BITS); + d2 <= (others => '-'); + if CLOCK2_PHASE >= CLOCK1_PHASE then + -- read succeeds either if clocks are in phase or read clock is + -- behind write clock + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + else + -- read-during-write at same address + rd_d2 <= (others => 'X'); + end if; + end loop; + + -- Alternating write on port 1 / read on port 2 + ------------------------------------------------------------------------- + simWaitUntilRisingEdge(clk2, 1); + -- first write on port 1 here + ce2 <= '0'; + we2 <= '-'; + a2 <= (others => '-'); + d2 <= (others => '-'); + rd_d2 <= (others => '-'); + + for i in 8 to 15 loop + simWaitUntilRisingEdge(clk2, 1); + ce2 <= not ce2; + we2 <= '0'; + a2 <= to_unsigned(i, A_BITS); + d2 <= (others => '-'); + if CLOCK2_PHASE >= CLOCK1_PHASE then + -- read succeeds either if clocks are in phase or read clock is + -- behind write clock + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + else + -- read-during-write at same address + rd_d2 <= (others => 'X'); + end if; + end loop; + + -- Write in 8 consecutive clock cycles on port 2, read one cycle later on + -- port 1 + ------------------------------------------------------------------------- + for i in 16 to 23 loop + simWaitUntilRisingEdge(clk2, 1); + ce2 <= '1'; + we2 <= '1'; + a2 <= to_unsigned(i, A_BITS); + d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + simWaitUntilRisingEdge(clk2, 1); + -- last read on port 1 here + ce2 <= '0'; + we2 <= '0'; + a2 <= (others => '-'); + d2 <= (others => '-'); + rd_d2 <= (others => '-'); + + ------------------------------------------------------------------------- + -- Alternating write on port 2 / read on port 1 + for i in 24 to 31 loop + simWaitUntilRisingEdge(clk2, 1); + ce2 <= not ce2; -- write @ even addresses + we2 <= '1'; + a2 <= to_unsigned(i, A_BITS); + d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + simWaitUntilRisingEdge(clk2, 1); + -- last read on port 1 here + ce2 <= '0'; + we2 <= '0'; + a2 <= (others => '-'); + d2 <= (others => '-'); + rd_d2 <= (others => '-'); + + ------------------------------------------------------------------------- + -- Alternate between write on port 1 and write on port 2 to the same + -- address. Data is read again from memory after all writes. + for i in 32 to 39 loop + simWaitUntilRisingEdge(clk2, 1); + -- write on port 1 + ce2 <= '0'; + we2 <= '-'; + a2 <= (others => '-'); + d2 <= (others => '-'); + rd_d2 <= (others => '-'); + + simWaitUntilRisingEdge(clk2, 1); + ce2 <= '1'; + we2 <= '1'; + a2 <= to_unsigned(i, A_BITS); + d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + for i in 32 to 39 loop + simWaitUntilRisingEdge(clk2, 1); + ce2 <= '1'; + we2 <= '0'; + a2 <= to_unsigned(i, A_BITS); + d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + if CLOCK2_PHASE >= CLOCK1_PHASE then + -- write succeeds either if clocks are in phase or if clock of second + -- write is behind clock of first write + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + else + -- write-during-write at same address + rd_d2 <= (others => 'X'); + end if; + end loop; + + ------------------------------------------------------------------------- + -- Alternate between write on port 2 and write on port 1 to the same + -- address. Data is read again from memory after all writes. + for i in 40 to 47 loop + simWaitUntilRisingEdge(clk2, 1); + ce2 <= '1'; + we2 <= '1'; + a2 <= to_unsigned(i, A_BITS); + d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + + simWaitUntilRisingEdge(clk2, 1); + -- write on port 1 + ce2 <= '0'; + we2 <= '-'; + a2 <= (others => '-'); + d2 <= (others => '-'); + rd_d2 <= (others => '-'); + end loop; + + for i in 40 to 47 loop + simWaitUntilRisingEdge(clk2, 1); + ce2 <= '1'; + we2 <= '0'; + a2 <= to_unsigned(i, A_BITS); + d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + if CLOCK1_PHASE >= CLOCK2_PHASE then + -- write succeeds either if clocks are in phase or if clock of second + -- write is behind clock of first write + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + else + -- write-during-write at same address + rd_d2 <= (others => 'X'); + end if; + end loop; + + -- Read in 8 consecutive clock cycles on port 1, write one cycle later on + -- port 2 + ------------------------------------------------------------------------- + simWaitUntilRisingEdge(clk2, 1); + -- first read on port 1 here + ce2 <= '0'; + we2 <= '0'; + a2 <= (others => '-'); + d2 <= (others => '-'); + rd_d2 <= (others => '-'); + + for i in 48 to 55 loop + simWaitUntilRisingEdge(clk2, 1); + ce2 <= '1'; + we2 <= '1'; + a2 <= to_unsigned(i, A_BITS); + d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + -- Read in 8 consecutive clock cycles on port 2, write one cycle later on + -- port 1 + ------------------------------------------------------------------------- + for i in 56 to 63 loop + simWaitUntilRisingEdge(clk2, 1); + ce2 <= '1'; + we2 <= '0'; + a2 <= to_unsigned(i, A_BITS); + d2 <= (others => '-'); + if CLOCK2_PHASE <= CLOCK1_PHASE then + -- read succeeds if clocks are in phase or if read clock is before + -- write clock + rd_d2 <= (others => 'U'); -- memory not yet initialized + else + -- write-during-read at same address + rd_d2 <= (others => 'X'); + end if; + end loop; + + simWaitUntilRisingEdge(clk2, 1); + -- last write on port 1 here + ce2 <= '0'; + we2 <= '0'; + a2 <= (others => '-'); + d2 <= (others => '-'); + rd_d2 <= (others => '-'); + + ------------------------------------------------------------------------- + -- Finish + simWaitUntilRisingEdge(clk2, 1); + ce2 <= '0'; + we2 <= '-'; + a2 <= (others => '-'); + d2 <= (others => '-'); + rd_d2 <= (others => '-'); + + -- This process is finished + finished2 <= true; + simDeactivateProcess(simProcessID); + wait; -- forever + end process Stimuli2; + + -- Checker + -- =========================================================================== + + -- Also checks if old value is kept if ce1 = '0' + exp_q1 <= rd_d1 when rising_edge(clk1) and ce1 = '1'; + + -- Also checks if old value is kept if ce2 = '0' + exp_q2 <= rd_d2 when rising_edge(clk2) and ce2 = '1'; + + Checker1: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "TestID "&integer'image(simTestID)&", Checker1"); + variable i : integer; + begin + while not finished1 loop + simWaitUntilRisingEdge(clk1, 1); + simAssertion((q1 = exp_q1) or -- also matches 'X'es + std_match(q1, exp_q1)); -- also matches '-'es + end loop; + + -- This process is finished + simDeactivateProcess(simProcessID); + wait; -- forever + end process Checker1; + + Checker2: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "TestID "&integer'image(simTestID)&", Checker2"); + variable i : integer; + begin + while not finished2 loop + simWaitUntilRisingEdge(clk2, 1); + simAssertion((q2 = exp_q2) or -- also matches 'X'es + std_match(q2, exp_q2)); -- also matches '-'es + end loop; + + -- This process is finished + simDeactivateProcess(simProcessID); + wait; -- forever + end process Checker2; + end generate gTest; end architecture; diff --git a/tb/mem/ocram/ocram_tdp_wf_tb.files b/tb/mem/ocram/ocram_tdp_wf_tb.files new file mode 100644 index 00000000..e52d8e2c --- /dev/null +++ b/tb/mem/ocram/ocram_tdp_wf_tb.files @@ -0,0 +1,11 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# ============================================================================== +# Note: all files are relative to PoC root directory +# +# PoC.mem.ocram +include "src/mem/ocram/ocram_tdp_wf.files" # Unit Under Test + +# Testbench files +vhdl test "tb/mem/ocram/ocram_tdp_wf_tb.vhdl" # Testbench diff --git a/tb/mem/ocram/ocram_tdp_wf_tb.vhdl b/tb/mem/ocram/ocram_tdp_wf_tb.vhdl new file mode 100644 index 00000000..d9378694 --- /dev/null +++ b/tb/mem/ocram/ocram_tdp_wf_tb.vhdl @@ -0,0 +1,644 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Authors: Martin Zabel +-- +-- Testbench: On-Chip-RAM: True-Dual-Port (TDP) with write-first. +-- +-- Description: +-- ------------------------------------ +-- Automated testbench for PoC.mem.ocram.tdp_wf +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library PoC; +use PoC.utils.all; +use PoC.physical.all; +-- simulation only packages +use PoC.sim_types.all; +use PoC.simulation.all; +use PoC.waveform.all; + + +entity ocram_tdp_wf_tb is +end entity; + +architecture tb of ocram_tdp_wf_tb is + constant CLOCK_FREQ : FREQ := 100 MHz; + + -- component generics + -- Set to values used for synthesis when simulating a netlist. + constant A_BITS : positive := 8; + constant D_BITS : positive := 16; + + -- component ports + signal clk : std_logic; + signal ce : std_logic; + signal we1 : std_logic; + signal we2 : std_logic; + signal a1 : unsigned(A_BITS-1 downto 0); + signal a2 : unsigned(A_BITS-1 downto 0); + signal d1 : std_logic_vector(D_BITS-1 downto 0); + signal d2 : std_logic_vector(D_BITS-1 downto 0); + signal q1 : std_logic_vector(D_BITS-1 downto 0); + signal q2 : std_logic_vector(D_BITS-1 downto 0); + + -- Expected read data, assign together with read command + -- Set to '-'es when result doesn't care. + -- Set to 'X'es when expecting unknown result due to mixed-port collision. + signal rd_d1 : std_logic_vector(D_BITS-1 downto 0); + signal rd_d2 : std_logic_vector(D_BITS-1 downto 0); + + -- Derived expected output on q1. + signal exp_q1 : std_logic_vector(D_BITS-1 downto 0) := (others => '-'); + + -- Derived expected output on q2. + signal exp_q2 : std_logic_vector(D_BITS-1 downto 0) := (others => '-'); + + -- Signaling between Stimuli and Checker process + signal finished1 : boolean := false; + signal finished2 : boolean := false; +begin + -- initialize global simulation status + simInitialize; + + -- generate global testbench clock + simGenerateClock(clk, CLOCK_FREQ); + + -- component instantiation + UUT: entity poc.ocram_tdp_wf + generic map ( + A_BITS => A_BITS, + D_BITS => D_BITS, + FILENAME => "") + port map ( + clk => clk, + ce => ce, + we1 => we1, + we2 => we2, + a1 => a1, + a2 => a2, + d1 => d1, + d2 => d2, + q1 => q1, + q2 => q2); + + -- NOTE: Clock enable is controlled by Stimuli1. It must be '1' for all + -- test pattern which do not read and write at the same time. + + -- Input stimuli for Port 1 (Write) + -- =========================================================================== + Stimuli1: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Stimuli1"); + variable re1 : boolean; + begin + -- No operation on first rising clock edge + ce <= '0'; + we1 <= '-'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + + -- Write in 8 consecutive clock cycles on port 1, read one cycle later on + -- port 2 + ------------------------------------------------------------------------- + for i in 0 to 7 loop + simWaitUntilRisingEdge(clk, 1); + ce <= '1'; + we1 <= '1'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + simWaitUntilRisingEdge(clk, 1); + -- last read on port 2 here + ce <= '1'; + we1 <= '0'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + + -- Alternating write on port 1 / read on port 2 + ------------------------------------------------------------------------- + for i in 8 to 15 loop + simWaitUntilRisingEdge(clk, 1); + ce <= '1'; + we1 <= not we1; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + if we1 = '0' then -- next is write + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + else + rd_d1 <= (others => '-'); + end if; + end loop; + + simWaitUntilRisingEdge(clk, 1); + -- last read on port 2 here + ce <= '1'; + we1 <= '0'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + + -- Read in 8 consecutive clock cycles on port 2, write one cycle later on + -- port 1 + ------------------------------------------------------------------------- + simWaitUntilRisingEdge(clk, 1); + -- first read on port 2 here + ce <= '1'; + we1 <= '0'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + + for i in 16 to 23 loop + simWaitUntilRisingEdge(clk, 1); + ce <= '1'; + we1 <= '1'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + -- Alternating write on port 2 / read on port 1 + ------------------------------------------------------------------------- + simWaitUntilRisingEdge(clk, 1); + -- first write on port 2 here + ce <= '1'; + re1 := false; + we1 <= '0'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + + for i in 24 to 31 loop + simWaitUntilRisingEdge(clk, 1); + ce <= '1'; + re1 := not re1; -- only compare result every second clock cycle + we1 <= '0'; + a1 <= to_unsigned(i, A_BITS); + d1 <= (others => '-'); + if re1 then + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + else + rd_d1 <= (others => '-'); + end if; + end loop; + + ------------------------------------------------------------------------- + -- Alternate between write on port 1 and write on port 2 to the same + -- address. Data is read again from memory after all writes. + for i in 32 to 39 loop + simWaitUntilRisingEdge(clk, 1); + ce <= '1'; + we1 <= '1'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + + simWaitUntilRisingEdge(clk, 1); + -- write on port 2 + ce <= '1'; + we1 <= '0'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + end loop; + + for i in 32 to 39 loop + simWaitUntilRisingEdge(clk, 1); + ce <= '1'; + we1 <= '0'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + ------------------------------------------------------------------------- + -- Alternate between write on port 2 and write on port 1 to the same + -- address. Data is read again from memory after all writes. + for i in 40 to 47 loop + simWaitUntilRisingEdge(clk, 1); + -- write on port 2 + ce <= '1'; + we1 <= '0'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + + simWaitUntilRisingEdge(clk, 1); + ce <= '1'; + we1 <= '1'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + for i in 40 to 47 loop + simWaitUntilRisingEdge(clk, 1); + ce <= '1'; + we1 <= '0'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + -- Read in 8 consecutive clock cycles on port 1, write one cycle later on + -- port 2 + ------------------------------------------------------------------------- + for i in 48 to 55 loop + simWaitUntilRisingEdge(clk, 1); + ce <= '1'; + we1 <= '0'; + a1 <= to_unsigned(i, A_BITS); + d1 <= (others => '-'); + rd_d1 <= (others => 'U'); -- memory not yet initialized + end loop; + + simWaitUntilRisingEdge(clk, 1); + -- last write on port 2 here + ce <= '1'; + we1 <= '0'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + + -- Read in 8 consecutive clock cycles on port 2, write one cycle later on + -- port 1 + ------------------------------------------------------------------------- + simWaitUntilRisingEdge(clk, 1); + -- first read on port 2 here + ce <= '1'; + we1 <= '0'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + + for i in 56 to 63 loop + simWaitUntilRisingEdge(clk, 1); + ce <= '1'; + we1 <= '1'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + -- Read (port 2) and write (port 1) in 8 consecutive clock cycles at the + -- same address + ------------------------------------------------------------------------- + for i in 64 to 71 loop + simWaitUntilRisingEdge(clk, 1); + ce <= '1'; + we1 <= '1'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + -- Read (port 2) and write (port 1) 8 times at the same address every second + -- clock cycle + ------------------------------------------------------------------------- + for i in 72 to 87 loop + simWaitUntilRisingEdge(clk, 1); + ce <= not ce; + we1 <= '1'; + a1 <= to_unsigned(i, A_BITS); + d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + -- Read (port 1) and write (port 2) in 8 consecutive clock cycles at the + -- same address + ------------------------------------------------------------------------- + for i in 88 to 95 loop + simWaitUntilRisingEdge(clk, 1); + ce <= '1'; + we1 <= '0'; + a1 <= to_unsigned(i, A_BITS); + d1 <= (others => '-'); + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + -- Read (port 1) and write (port 2) 8 times at the same address every second + -- clock cycle + ------------------------------------------------------------------------- + for i in 96 to 111 loop + simWaitUntilRisingEdge(clk, 1); + ce <= not ce; + we1 <= '0'; + a1 <= to_unsigned(i, A_BITS); + d1 <= (others => '-'); + rd_d1 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + ------------------------------------------------------------------------- + -- Finish + simWaitUntilRisingEdge(clk, 1); + ce <= '0'; + we1 <= '-'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + + -- This process is finished + finished1 <= true; + simDeactivateProcess(simProcessID); + wait; -- forever + end process Stimuli1; + + -- Input stimuli for Port 2 (Read) + -- =========================================================================== + Stimuli2: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Stimuli2"); + variable re2 : boolean; + begin + -- No operation on first rising clock edge + we2 <= '-'; + a2 <= (others => '-'); + d2 <= (others => '-'); + rd_d2 <= (others => '-'); + + -- Write in 8 consecutive clock cycles on port 1, read one cycle later on + -- port 2 + ------------------------------------------------------------------------- + simWaitUntilRisingEdge(clk, 1); + -- first write on port 1 here + we2 <= '0'; + a2 <= (others => '-'); + rd_d2 <= (others => '-'); + + for i in 0 to 7 loop + simWaitUntilRisingEdge(clk, 1); + a2 <= to_unsigned(i, A_BITS); + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + -- Alternating write on port 1 / read on port 2 + ------------------------------------------------------------------------- + simWaitUntilRisingEdge(clk, 1); + -- first write on port 1 here + re2 := false; + we2 <= '0'; + a2 <= (others => '-'); + d2 <= (others => '-'); + rd_d2 <= (others => '-'); + + for i in 8 to 15 loop + simWaitUntilRisingEdge(clk, 1); + re2 := not re2; -- only compare read result every second cycle + a2 <= to_unsigned(i, A_BITS); + d2 <= (others => '-'); + if re2 then + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + else + rd_d2 <= (others => '-'); + end if; + end loop; + + -- Read in 8 consecutive clock cycles on port 2, write one cycle later on + -- port 1 + ------------------------------------------------------------------------- + for i in 16 to 23 loop + simWaitUntilRisingEdge(clk, 1); + we2 <= '0'; + a2 <= to_unsigned(i, A_BITS); + d2 <= (others => '-'); + rd_d2 <= (others => 'U'); -- memory not yet initialized + end loop; + + simWaitUntilRisingEdge(clk, 1); + -- last write on port 1 here + we2 <= '0'; + a2 <= (others => '-'); + d2 <= (others => '-'); + rd_d2 <= (others => '-'); + + ------------------------------------------------------------------------- + -- Alternating write on port 2 / read on port 1 + for i in 24 to 31 loop + simWaitUntilRisingEdge(clk, 1); + we2 <= not we2; + a2 <= to_unsigned(i, A_BITS); + d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + if we2 = '0' then -- next is write + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + else + rd_d2 <= (others => '-'); + end if; + end loop; + + simWaitUntilRisingEdge(clk, 1); + -- last read on port 1 here + we2 <= '0'; + a2 <= (others => '-'); + d2 <= (others => '-'); + rd_d2 <= (others => '-'); + + ------------------------------------------------------------------------- + -- Alternate between write on port 1 and write on port 2 to the same + -- address. Data is read again from memory after all writes. + for i in 32 to 39 loop + simWaitUntilRisingEdge(clk, 1); + -- write on port 1 + we2 <= '0'; + a2 <= (others => '-'); + d2 <= (others => '-'); + rd_d2 <= (others => '-'); + + simWaitUntilRisingEdge(clk, 1); + we2 <= '1'; + a2 <= to_unsigned(i, A_BITS); + d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + for i in 32 to 39 loop + simWaitUntilRisingEdge(clk, 1); + we2 <= '0'; + a2 <= to_unsigned(i, A_BITS); + d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + ------------------------------------------------------------------------- + -- Alternate between write on port 2 and write on port 1 to the same + -- address. Data is read again from memory after all writes. + for i in 40 to 47 loop + simWaitUntilRisingEdge(clk, 1); + we2 <= '1'; + a2 <= to_unsigned(i, A_BITS); + d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + + simWaitUntilRisingEdge(clk, 1); + -- write on port 1 + we2 <= '0'; + a2 <= (others => '-'); + d2 <= (others => '-'); + rd_d2 <= (others => '-'); + end loop; + + for i in 40 to 47 loop + simWaitUntilRisingEdge(clk, 1); + we2 <= '0'; + a2 <= to_unsigned(i, A_BITS); + d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + -- Read in 8 consecutive clock cycles on port 1, write one cycle later on + -- port 2 + ------------------------------------------------------------------------- + simWaitUntilRisingEdge(clk, 1); + -- first read on port 1 here + we2 <= '0'; + a2 <= (others => '-'); + d2 <= (others => '-'); + rd_d2 <= (others => '-'); + + for i in 48 to 55 loop + simWaitUntilRisingEdge(clk, 1); + we2 <= '1'; + a2 <= to_unsigned(i, A_BITS); + d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + -- Read in 8 consecutive clock cycles on port 2, write one cycle later on + -- port 1 + ------------------------------------------------------------------------- + for i in 56 to 63 loop + simWaitUntilRisingEdge(clk, 1); + we2 <= '0'; + a2 <= to_unsigned(i, A_BITS); + d2 <= (others => '-'); + rd_d2 <= (others => 'U'); -- memory not yet initialized + end loop; + + simWaitUntilRisingEdge(clk, 1); + -- last write on port 1 here + we2 <= '0'; + a2 <= (others => '-'); + d2 <= (others => '-'); + rd_d2 <= (others => '-'); + + -- Read (port 2) and write (port 1) in 8 consecutive clock cycles at the + -- same address + ------------------------------------------------------------------------- + for i in 64 to 71 loop + simWaitUntilRisingEdge(clk, 1); + we2 <= '0'; + a2 <= to_unsigned(i, A_BITS); + d2 <= (others => '-'); + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + -- Read (port 2) and write (port 1) 8 times at the same address every second + -- clock cycle + ------------------------------------------------------------------------- + for i in 72 to 87 loop + simWaitUntilRisingEdge(clk, 1); + we2 <= '0'; + a2 <= to_unsigned(i, A_BITS); + d2 <= (others => '-'); + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + -- Read (port 2) and write (port 1) in 8 consecutive clock cycles at the + -- same address + ------------------------------------------------------------------------- + for i in 88 to 95 loop + simWaitUntilRisingEdge(clk, 1); + we2 <= '1'; + a2 <= to_unsigned(i, A_BITS); + d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + -- Read (port 2) and write (port 1) 8 times at the same address every second + -- clock cycle + ------------------------------------------------------------------------- + for i in 96 to 111 loop + simWaitUntilRisingEdge(clk, 1); + we2 <= '1'; + a2 <= to_unsigned(i, A_BITS); + d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + rd_d2 <= std_logic_vector(to_unsigned(i, D_BITS)); + end loop; + + ------------------------------------------------------------------------- + -- Finish + simWaitUntilRisingEdge(clk, 1); + we2 <= '-'; + a2 <= (others => '-'); + d2 <= (others => '-'); + rd_d2 <= (others => '-'); + + -- This process is finished + finished2 <= true; + simDeactivateProcess(simProcessID); + wait; -- forever + end process Stimuli2; + + -- Checker + -- =========================================================================== + + -- Also checks if old value is kept if ce = '0' + exp_q1 <= rd_d1 when rising_edge(clk) and ce = '1'; + exp_q2 <= rd_d2 when rising_edge(clk) and ce = '1'; + + Checker1: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Checker1"); + variable i : integer; + begin + while not finished1 loop + simWaitUntilRisingEdge(clk, 1); + simAssertion((q1 = exp_q1) or -- also matches 'X'es + std_match(q1, exp_q1)); -- also matches '-'es + end loop; + + -- This process is finished + simDeactivateProcess(simProcessID); + wait; -- forever + end process Checker1; + + Checker2: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Checker2"); + variable i : integer; + begin + while not finished2 loop + simWaitUntilRisingEdge(clk, 1); + simAssertion((q2 = exp_q2) or -- also matches 'X'es + std_match(q2, exp_q2)); -- also matches '-'es + end loop; + + -- This process is finished + simDeactivateProcess(simProcessID); + wait; -- forever + end process Checker2; + +end architecture; From 2ec72c552ba0403287d60c906722fa97f239b1ff Mon Sep 17 00:00:00 2001 From: Martin Zabel Date: Wed, 23 Nov 2016 15:50:34 +0100 Subject: [PATCH 61/97] Added missing ocram_tdp_sim.vhdl --- src/mem/ocram/ocram_tdp_sim.vhdl | 304 +++++++++++++++++++++++++++++++ 1 file changed, 304 insertions(+) create mode 100644 src/mem/ocram/ocram_tdp_sim.vhdl diff --git a/src/mem/ocram/ocram_tdp_sim.vhdl b/src/mem/ocram/ocram_tdp_sim.vhdl new file mode 100644 index 00000000..60d6b798 --- /dev/null +++ b/src/mem/ocram/ocram_tdp_sim.vhdl @@ -0,0 +1,304 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Martin Zabel +-- +-- Entity: Simulation model for true dual-port memory. +-- +-- Description: +-- ------------------------------------- +-- Simulation model for true dual-port memory, with: +-- +-- * dual clock, clock enable, +-- * 2 read/write ports. +-- +-- The interface matches that of the IP core PoC.mem.ocram.tdp. +-- But the implementation there is restricted to the description supported by +-- various synthesis compilers. The implementation here also simulates the +-- correct Mixed-Port Read-During-Write Behavior and handles X propagation. +-- +-- License: +-- ============================================================================= +-- Copyright 2016-2016 Technische Universitaet Dresden - Germany +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library PoC; +use PoC.utils.all; +use PoC.strings.all; +use PoC.vectors.all; +use PoC.mem.all; + + +entity ocram_tdp_sim is + generic ( + A_BITS : positive; -- number of address bits + D_BITS : positive; -- number of data bits + FILENAME : string := "" -- file-name for RAM initialization + ); + port ( + clk1 : in std_logic; -- clock for 1st port + clk2 : in std_logic; -- clock for 2nd port + ce1 : in std_logic; -- clock-enable for 1st port + ce2 : in std_logic; -- clock-enable for 2nd port + we1 : in std_logic; -- write-enable for 1st port + we2 : in std_logic; -- write-enable for 2nd port + a1 : in unsigned(A_BITS-1 downto 0); -- address for 1st port + a2 : in unsigned(A_BITS-1 downto 0); -- address for 2nd port + d1 : in std_logic_vector(D_BITS-1 downto 0); -- write-data for 1st port + d2 : in std_logic_vector(D_BITS-1 downto 0); -- write-data for 2nd port + q1 : out std_logic_vector(D_BITS-1 downto 0); -- read-data from 1st port + q2 : out std_logic_vector(D_BITS-1 downto 0) -- read-data from 2nd port + ); +end entity; + + +architecture sim of ocram_tdp_sim is + constant DEPTH : positive := 2**A_BITS; + subtype word_t is std_logic_vector(D_BITS - 1 downto 0); + type ram_t is array(0 to DEPTH - 1) of word_t; + + impure function ocram_InitMemory(FilePath : string) return ram_t is + variable Memory : T_SLM(DEPTH - 1 downto 0, word_t'range); + variable res : ram_t; + begin + if str_length(FilePath) = 0 then + -- shortcut required by Vivado + return (others => (others => ite(SIMULATION, 'U', '0'))); + elsif mem_FileExtension(FilePath) = "mem" then + Memory := mem_ReadMemoryFile(FilePath, DEPTH, word_t'length, MEM_FILEFORMAT_XILINX_MEM, MEM_CONTENT_HEX); + else + Memory := mem_ReadMemoryFile(FilePath, DEPTH, word_t'length, MEM_FILEFORMAT_INTEL_HEX, MEM_CONTENT_HEX); + end if; + + for i in Memory'range(1) loop + for j in word_t'range loop + res(i)(j) := Memory(i, j); + end loop; + end loop; + return res; + end function; + + signal ram : ram_t := ocram_InitMemory(FILENAME); + + -- write to memory, 'X' means maybe write + signal write1 : X01; + signal write2 : X01; + + -- read only from memory, 'X' means maybe read + signal read1 : X01; + signal read2 : X01; +begin + assert SIMULATION report "This model is only for simulation." severity error; + + -- handle 'U' as 'X' + write1 <= to_x01(ce1 and we1); + read1 <= to_x01(ce1 and not we1); + write2 <= to_x01(ce2 and we2); + read2 <= to_x01(ce2 and not we2); + + process (clk1, clk2) + -- Flag and address indicating whether a write occurs in the current clock + -- cycle. Set and cleared at the rising_edge of the port's clock. + -- The write address is set to don't care when the write location is + -- undefined, to match all addresses in collision checks from other port. + variable writing1 : boolean; + variable writing2 : boolean; + variable waddr1 : unsigned(A_BITS-1 downto 0); + variable waddr2 : unsigned(A_BITS-1 downto 0); + + -- Check for write-collision check on port 1. Only set during one execution + -- of the process. + variable check_wr1 : boolean; + + -- Flag and address indicating whether a read occurs in the current clock + -- cycle. Set and cleared at the rising_edge of the port's clock. + -- In opposition to the writing flag, the reading flag is only set if the + -- address is well known and the read succeeded at the rising clock edge. + -- A read fails afterwards if a write happens during the read clock cycle. + variable reading1 : boolean; + variable reading2 : boolean; + variable raddr1 : unsigned(A_BITS-1 downto 0); + variable raddr2 : unsigned(A_BITS-1 downto 0); + + begin -- process + check_wr1 := false; + + -- Writing to Memory + -- ========================================================================= + if rising_edge(clk1) then + writing1 := false; + waddr1 := (others => '-'); + + if write1 = '1' then + -- RAM is definitely written ... + writing1 := true; + if is_x(std_logic_vector(a1)) then + -- ... but address is unknown + ram <= (others => (others => 'X')); + else + --- ... and address is well known + waddr1 := a1; + ram(to_integer(a1)) <= to_ux01(d1); + -- writing2 and waddr2 are not yet up-to-date, check for + -- write-collision below + check_wr1 := true; + end if; + -- same-port read during write: return new data + q1 <= to_ux01(d1); + + elsif write1 = 'X' then + -- RAM may be written ... + writing1 := true; + if is_x(std_logic_vector(a1)) then + -- ... but address is unknown + ram <= (others => (others => 'X')); + else + --- ... and address is well known + waddr1 := a1; + ram(to_integer(a1)) <= (others => 'X'); + end if; + -- same-port read during write: unknown data + q1 <= (others => 'X'); + end if; + end if; + + -- Must be executed after write to port 1 due to write-collsion check + if rising_edge(clk2) then + writing2 := false; + waddr2 := (others => '-'); + + if write2 = '1' then + -- RAM is definitely written ... + writing2 := true; + if is_x(std_logic_vector(a2)) then + -- ... but address is unknown + ram <= (others => (others => 'X')); + else + --- ... and address is well known + waddr2 := a2; + -- writing1 and waddr1 are up-to-date, check for write-collision + if writing1 and std_match(waddr1, a2) then + ram(to_integer(a2)) <= (others => 'X'); + else + ram(to_integer(a2)) <= to_ux01(d2); + end if; + end if; + -- same-port read during write: return new data + q2 <= to_ux01(d2); + + elsif write2 = 'X' then + -- RAM may be written ... + writing2 := true; + if is_x(std_logic_vector(a2)) then + -- ... but address is unknown + ram <= (others => (others => 'X')); + else + --- ... and address is well known + waddr2 := a2; + ram(to_integer(a2)) <= (others => 'X'); + end if; + -- same-port read during write: unknown data + q1 <= (others => 'X'); + end if; + end if; + + -- writing1 and waddr1 are up-to-date, check for write-collision + if check_wr1 then + if writing2 and std_match(waddr2, a1) then + ram(to_integer(a1)) <= (others => 'X'); + end if; + end if; + + -- Reading (only) from Memory + -- ========================================================================= + if rising_edge(clk1) then + reading1 := false; + raddr1 := (others => '-'); + + if read1 = '1' then + -- Definitely read only from RAM ... + if is_x(std_logic_vector(a1)) then + -- ... but address is unknown + q1 <= (others => 'X'); + else + -- check for mixed-port read-during-write + if writing2 and std_match(a1,waddr2) then + q1 <= (others => 'X'); + else + -- further checks are only required if address is well known + reading1 := true; + raddr1 := a1; + q1 <= ram(to_integer(a1)); + end if; + end if; + elsif read1 = 'X' then + -- Maybe read only from RAM + q1 <= (others => 'X'); + end if; + end if; + + if rising_edge(clk2) then + reading2 := false; + raddr2 := (others => '-'); + + if read2 = '1' then + -- Definitely read only from RAM ... + if is_x(std_logic_vector(a2)) then + -- ... but address is unknown + q2 <= (others => 'X'); + else + -- check for mixed-port read-during-write + if writing1 and std_match(a2,waddr1) then + q2 <= (others => 'X'); + else + -- further checks are only required if address is well known + reading2 := true; + raddr2 := a2; + q2 <= ram(to_integer(a2)); + end if; + end if; + elsif read2 = 'X' then + -- Maybe read only from RAM + q2 <= (others => 'X'); + end if; + end if; + + -- Write-during-read check + -- ========================================================================= + -- cannot be included in read part above, because check is performed on a + -- following rising edge of the write clock (not read clock!). + if rising_edge(clk1) and writing1 then + if reading2 and std_match(raddr2, waddr1) then + -- read is disturbed by a write during the read clock cycle + q2 <= (others => 'X'); + end if; + end if; + + if rising_edge(clk2) and writing2 then + if reading1 and std_match(raddr1, waddr2) then + -- read is disturbed by a write during the read clock cycle + q1 <= (others => 'X'); + end if; + end if; + end process; + +end architecture; From 822e7ebde0076f58f15b417a7597ad8fd097b37d Mon Sep 17 00:00:00 2001 From: Martin Zabel Date: Wed, 23 Nov 2016 16:04:48 +0100 Subject: [PATCH 62/97] Using OSVVM scoreboard in testbenches for sort.sortnet.*, but deactived until GHDL is fixed. --- py/config.entity.ini | 3 + tb/sort/sortnet/sortnet_BitonicSort_tb.files | 1 + tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl | 142 +++++++----------- .../sortnet/sortnet_OddEvenMergeSort_tb.files | 1 + .../sortnet/sortnet_OddEvenMergeSort_tb.vhdl | 127 +++++++++------- tb/sort/sortnet/sortnet_OddEvenSort_tb.files | 1 + tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl | 133 ++++++++-------- tb/sort/sortnet/sortnet_tb.pkg.vhdl | 125 +++++++++++++++ tools/precompile/compile-osvvm.ps1 | 2 + tools/precompile/compile-osvvm.sh | 2 + 10 files changed, 328 insertions(+), 209 deletions(-) create mode 100644 tb/sort/sortnet/sortnet_tb.pkg.vhdl diff --git a/py/config.entity.ini b/py/config.entity.ini index a4a68d88..bd492aec 100644 --- a/py/config.entity.ini +++ b/py/config.entity.ini @@ -906,6 +906,7 @@ cocotb = CocoTestbench # PoC.sort.sortnet # ------------------------------------------------------------------------------ [IP.sort.sortnet.BitonicSort] +Visibility = Private tb = VHDLTestbench nl1 = LSENetlist nl2 = QuartusNetlist @@ -921,6 +922,7 @@ HDLParameters = INPUTS=32; KEY_BITS=32; DATA_BITS=64; PIPELINE_STAGE_AFTER=2 [IP.sort.sortnet.OddEvenMergeSort] +Visibility = Private tb = VHDLTestbench nl1 = LSENetlist nl2 = QuartusNetlist @@ -934,6 +936,7 @@ HDLParameters = INPUTS=32; KEY_BITS=32; DATA_BITS=64; PIPELINE_STAGE_AFTER=2 [VIVADO.sort.sortnet.OddEvenMergeSort.nl4] [IP.sort.sortnet.OddEvenSort] +Visibility = Private tb = VHDLTestbench nl1 = LSENetlist nl2 = QuartusNetlist diff --git a/tb/sort/sortnet/sortnet_BitonicSort_tb.files b/tb/sort/sortnet/sortnet_BitonicSort_tb.files index 46e75522..a4ad125c 100644 --- a/tb/sort/sortnet/sortnet_BitonicSort_tb.files +++ b/tb/sort/sortnet/sortnet_BitonicSort_tb.files @@ -11,4 +11,5 @@ include "lib/OSVVM.files" # Open Source VHDL Verification Meth include "src/sort/sortnet/sortnet_BitonicSort.files" # UUT (Unit Under Test) # Testbench file(s) +vhdl test "tb/sort/sortnet/sortnet_tb.pkg.vhdl" # Testbench package vhdl test "tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl" # Testbench diff --git a/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl b/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl index 6ddeb525..de8d8013 100644 --- a/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl +++ b/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl @@ -33,6 +33,9 @@ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; +library OSVVM; +use OSVVM.RandomPkg.all; + library PoC; use PoC.math.all; use PoC.utils.all; @@ -44,8 +47,7 @@ use PoC.sim_types.all; use PoC.simulation.all; use PoC.waveform.all; -library OSVVM; -use OSVVM.RandomPkg.all; +library Test; entity sortnet_BitonicSort_tb is @@ -53,14 +55,13 @@ end entity; architecture tb of sortnet_BitonicSort_tb is - constant TAG_BITS : positive := 4; constant INPUTS : positive := 64; constant DATA_COLUMNS : positive := 2; - constant KEY_BITS : positive := 8; - constant DATA_BITS : positive := 32; + constant KEY_BITS : positive := 32; + constant DATA_BITS : positive := 64; constant META_BITS : positive := TAG_BITS; constant PIPELINE_STAGE_AFTER : natural := 2; @@ -69,61 +70,13 @@ architecture tb of sortnet_BitonicSort_tb is constant STAGES : positive := triangularNumber(log2ceil(INPUTS)); constant DELAY : natural := STAGES / PIPELINE_STAGE_AFTER; - subtype T_DATA is std_logic_vector(DATA_BITS - 1 downto 0); - type T_DATA_VECTOR is array(natural range <>) of T_DATA; - - type T_SB_KEY_VECTOR is array(natural range <>) of std_logic_vector(KEY_BITS - 1 downto 0); - type T_SB_DATA_VECTOR is array(natural range <>) of std_logic_vector((DATA_BITS - KEY_BITS) - 1 downto 0); - - type T_SCOREBOARD_DATA is record - IsKey : std_logic; - Meta : std_logic_vector(META_BITS - 1 downto 0); - Key : T_SB_KEY_VECTOR(INPUTS - 1 downto 0); - Data : T_SB_DATA_VECTOR(INPUTS - 1 downto 0); - end record; - - function match(expected : T_SCOREBOARD_DATA; actual : T_SCOREBOARD_DATA) return boolean is - begin - report "checking: "; -- & to_string(expected.Meta) severity note; - return TRUE; - end function; - - function to_string(vector : T_SCOREBOARD_DATA) return string is - begin - return "to_string"; - end function; - - package P_Scoreboard is new osvvm.ScoreboardGenericPkg + package P_SORTNET_TB is new Test.sortnet_tb generic map ( - ExpectedType => T_SCOREBOARD_DATA, - ActualType => T_SCOREBOARD_DATA, - Match => match, - expected_to_string => to_string, --[T_SCOREBOARD_DATA return string], - actual_to_string => to_string + META_BITS => META_BITS, + DATA_BITS => DATA_BITS, + INPUTS => INPUTS ); - alias T_SCOREBOARD is P_Scoreboard.ScoreBoardPType; - - function to_dv(slm : T_SLM) return T_DATA_VECTOR is - variable Result : T_DATA_VECTOR(slm'range(1)); - begin - for i in slm'high(1) downto slm'low(1) loop - for j in T_DATA'range loop - Result(i)(j) := slm(i, j); - end loop; - end loop; - return Result; - end function; - - function to_slm(dv : T_DATA_VECTOR) return T_SLM is - variable Result : T_SLM(dv'range, T_DATA'range); - begin - for i in dv'range loop - for j in T_DATA'range loop - Result(i, j) := dv(i)(j); - end loop; - end loop; - return Result; - end function; + use P_SORTNET_TB.all; constant CLOCK_FREQ : FREQ := 100 MHz; signal Clock : std_logic := '1'; @@ -141,7 +94,7 @@ architecture tb of sortnet_BitonicSort_tb is signal DataInputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0); signal DataOutputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0); - shared variable ScoreBoard : T_SCOREBOARD; + shared variable ScoreBoard : PT_SCOREBOARD; begin -- initialize global simulation status @@ -156,20 +109,28 @@ begin simGenerateClock(Clock, CLOCK_FREQ); procGenerator : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Generator"); - variable RandomVar : RandomPType; -- protected type from RandomPkg + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Generator"); + variable RandomVar : RandomPType; -- protected type from RandomPkg - variable KeyInput : std_logic_vector(KEY_BITS - 1 downto 0); - variable DataInput : std_logic_vector(DATA_BITS - KEY_BITS - 1 downto 0); - variable TagInput : std_logic_vector(TAG_BITS - 1 downto 0); + variable KeyInput : std_logic_vector(KEY_BITS - 1 downto 0); + variable DataInput : std_logic_vector(DATA_BITS - KEY_BITS - 1 downto 0); + variable TagInput : std_logic_vector(TAG_BITS - 1 downto 0); + variable Generator_Input : T_DATA_VECTOR(INPUTS - 1 downto 0); - variable ScoreBoardData : T_SCOREBOARD_DATA; + function GreaterThan(L : std_logic_vector; R : std_logic_vector) return boolean is + alias LL is L(KEY_BITS - 1 downto 0); + alias RR is R(KEY_BITS - 1 downto 0); + begin + return unsigned(LL) > unsigned(RR); + end function; + + variable ScoreBoardData : T_SCOREBOARD_DATA; begin RandomVar.InitSeed(RandomVar'instance_name); -- Generate initial seeds Generator_Valid <= '0'; Generator_IsKey <= '0'; - Generator_Data <= (others => (others => '0')); + Generator_Input := (others => (others => '0')); Generator_Meta <= (others => '0'); wait until rising_edge(Clock); @@ -179,18 +140,32 @@ begin ScoreBoardData.IsKey := to_sl(i mod DATA_COLUMNS = 0); ScoreBoardData.Meta := resize(TagInput, META_BITS); - for j in 0 to INPUTS - 1 loop + Generator_IsKey <= ScoreBoardData.IsKey; + Generator_Meta <= ScoreBoardData.Meta; + + KeyInput := RandomVar.RandSlv(KEY_BITS); + DataInput := RandomVar.RandSlv(DATA_BITS - KEY_BITS); + Generator_Input(0) := DataInput & KeyInput; + ScoreBoardData.Data(0):= Generator_Input(0); + + loop_j: for j in 1 to INPUTS - 1 loop KeyInput := RandomVar.RandSlv(KEY_BITS); DataInput := RandomVar.RandSlv(DATA_BITS - KEY_BITS); - - ScoreBoardData.Key(j) := KeyInput; - ScoreBoardData.Data(j) := DataInput; - Generator_Data(j) <= DataInput & KeyInput; + Generator_Input(j) := DataInput & KeyInput; + + for k in j downto 1 loop + if GreaterThan(ScoreBoardData.Data(k - 1), Generator_Input(j)) then + ScoreBoardData.Data(k) := ScoreBoardData.Data(k - 1); + else + ScoreBoardData.Data(k) := Generator_Input(j); + next loop_j; + end if; + end loop; + ScoreBoardData.Data(0) := Generator_Input(j); end loop; - ScoreBoard.Push(ScoreBoardData); - Generator_IsKey <= ScoreBoardData.IsKey; - Generator_Meta <= ScoreBoardData.Meta; + Generator_Data <= Generator_Input; + ScoreBoard.Push(ScoreBoardData); wait until rising_edge(Clock); end loop; @@ -245,25 +220,10 @@ begin Check := TRUE; ScoreBoardData.IsKey := Sort_IsKey; ScoreBoardData.Meta := Sort_Meta; - for j in 0 to INPUTS - 1 loop - ScoreBoardData.Key(j) := Sort_Data(j)(KEY_BITS - 1 downto 0); - ScoreBoardData.Data(j) := Sort_Data(j)(DATA_BITS - 1 downto KEY_BITS); - end loop; - - if (Sort_IsKey = '1') then - LastValue := (others => '0'); - for j in 0 to INPUTS - 1 loop - CurValue := unsigned(Sort_Data(j)(KEY_BITS - 1 downto 0)); - Check := Check and (LastValue <= CurValue); - LastValue := CurValue; - end loop; - simAssertion(Check, "Result is not monotonic." & raw_format_slv_hex(std_logic_vector(LastValue))); - else - -- no routine implemented to check if sorting network is switched as in the previous cycles - end if; - + ScoreBoardData.Data := Sort_Data; ScoreBoard.Check(ScoreBoardData); end loop; + -- simAssertion(Check, "Result is not monotonic." & raw_format_slv_hex(std_logic_vector(LastValue))); -- This process is finished simDeactivateProcess(simProcessID); diff --git a/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.files b/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.files index f49be92d..ad73d43f 100644 --- a/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.files +++ b/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.files @@ -11,4 +11,5 @@ include "lib/OSVVM.files" # Open Source VHDL Verification M include "src/sort/sortnet/sortnet_OddEvenMergeSort.files" # UUT (Unit Under Test) # Testbench file(s) +vhdl test "tb/sort/sortnet/sortnet_tb.pkg.vhdl" # Testbench package vhdl test "tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.vhdl" # Testbench diff --git a/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.vhdl b/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.vhdl index f2c7f151..e3d805b4 100644 --- a/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.vhdl +++ b/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.vhdl @@ -33,6 +33,9 @@ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; +library OSVVM; +use OSVVM.RandomPkg.all; + library PoC; use PoC.math.all; use PoC.utils.all; @@ -44,8 +47,7 @@ use PoC.sim_types.all; use PoC.simulation.all; use PoC.waveform.all; -library OSVVM; -use OSVVM.RandomPkg.all; +library Test; entity sortnet_OddEvenMergeSort_tb is @@ -69,30 +71,13 @@ architecture tb of sortnet_OddEvenMergeSort_tb is constant STAGES : positive := triangularNumber(log2ceil(INPUTS)); constant DELAY : natural := STAGES / PIPELINE_STAGE_AFTER; - subtype T_DATA is std_logic_vector(DATA_BITS - 1 downto 0); - type T_DATA_VECTOR is array(natural range <>) of T_DATA; - - function to_dv(slm : T_SLM) return T_DATA_VECTOR is - variable Result : T_DATA_VECTOR(slm'range(1)); - begin - for i in slm'high(1) downto slm'low(1) loop - for j in T_DATA'range loop - Result(i)(j) := slm(i, j); - end loop; - end loop; - return Result; - end function; - - function to_slm(dv : T_DATA_VECTOR) return T_SLM is - variable Result : T_SLM(dv'range, T_DATA'range); - begin - for i in dv'range loop - for j in T_DATA'range loop - Result(i, j) := dv(i)(j); - end loop; - end loop; - return Result; - end function; + package P_SORTNET_TB is new Test.sortnet_tb + generic map ( + META_BITS => META_BITS, + DATA_BITS => DATA_BITS, + INPUTS => INPUTS + ); + use P_SORTNET_TB.all; constant CLOCK_FREQ : FREQ := 100 MHz; signal Clock : std_logic := '1'; @@ -110,6 +95,8 @@ architecture tb of sortnet_OddEvenMergeSort_tb is signal DataInputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0); signal DataOutputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0); + shared variable ScoreBoard : PT_SCOREBOARD; + begin -- initialize global simulation status simInitialize; @@ -123,33 +110,63 @@ begin simGenerateClock(Clock, CLOCK_FREQ); procGenerator : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Generator"); - variable RandomVar : RandomPType; -- protected type from RandomPkg - - variable KeyInput : std_logic_vector(KEY_BITS - 1 downto 0); - variable DataInput : std_logic_vector(DATA_BITS - KEY_BITS - 1 downto 0); - variable TagInput : std_logic_vector(TAG_BITS - 1 downto 0); - + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Generator"); + variable RandomVar : RandomPType; -- protected type from RandomPkg + + variable KeyInput : std_logic_vector(KEY_BITS - 1 downto 0); + variable DataInput : std_logic_vector(DATA_BITS - KEY_BITS - 1 downto 0); + variable TagInput : std_logic_vector(TAG_BITS - 1 downto 0); + variable Generator_Input : T_DATA_VECTOR(INPUTS - 1 downto 0); + + function GreaterThan(L : std_logic_vector; R : std_logic_vector) return boolean is + alias LL is L(KEY_BITS - 1 downto 0); + alias RR is R(KEY_BITS - 1 downto 0); + begin + return unsigned(LL) > unsigned(RR); + end function; + + variable ScoreBoardData : T_SCOREBOARD_DATA; begin RandomVar.InitSeed(RandomVar'instance_name); -- Generate initial seeds Generator_Valid <= '0'; Generator_IsKey <= '0'; - Generator_Data <= (others => (others => '0')); + Generator_Input := (others => (others => '0')); Generator_Meta <= (others => '0'); wait until rising_edge(Clock); Generator_Valid <= '1'; for i in 0 to LOOP_COUNT - 1 loop - Generator_IsKey <= to_sl(i mod DATA_COLUMNS = 0); - for j in 0 to INPUTS - 1 loop - KeyInput := RandomVar.RandSlv(KEY_BITS); - DataInput := RandomVar.RandSlv(DATA_BITS - KEY_BITS); - TagInput := RandomVar.RandSlv(TAG_BITS); - - Generator_Data(j) <= DataInput & KeyInput; - Generator_Meta <= resize(TagInput, META_BITS); + TagInput := RandomVar.RandSlv(TAG_BITS); + + ScoreBoardData.IsKey := to_sl(i mod DATA_COLUMNS = 0); + ScoreBoardData.Meta := resize(TagInput, META_BITS); + Generator_IsKey <= ScoreBoardData.IsKey; + Generator_Meta <= ScoreBoardData.Meta; + + KeyInput := RandomVar.RandSlv(KEY_BITS); + DataInput := RandomVar.RandSlv(DATA_BITS - KEY_BITS); + Generator_Input(0) := DataInput & KeyInput; + ScoreBoardData.Data(0):= Generator_Input(0); + + loop_j: for j in 1 to INPUTS - 1 loop + KeyInput := RandomVar.RandSlv(KEY_BITS); + DataInput := RandomVar.RandSlv(DATA_BITS - KEY_BITS); + Generator_Input(j) := DataInput & KeyInput; + + for k in j downto 1 loop + if GreaterThan(ScoreBoardData.Data(k - 1), Generator_Input(j)) then + ScoreBoardData.Data(k) := ScoreBoardData.Data(k - 1); + else + ScoreBoardData.Data(k) := Generator_Input(j); + next loop_j; + end if; + end loop; + ScoreBoardData.Data(0) := Generator_Input(j); end loop; + + Generator_Data <= Generator_Input; + ScoreBoard.Push(ScoreBoardData); wait until rising_edge(Clock); end loop; @@ -189,10 +206,12 @@ begin Sort_Data <= to_dv(DataOutputMatrix); procChecker : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Checker"); - variable Check : boolean; - variable CurValue : unsigned(KEY_BITS - 1 downto 0); - variable LastValue : unsigned(KEY_BITS - 1 downto 0); + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Checker"); + variable Check : boolean; + variable CurValue : unsigned(KEY_BITS - 1 downto 0); + variable LastValue : unsigned(KEY_BITS - 1 downto 0); + + variable ScoreBoardData : T_SCOREBOARD_DATA; begin wait until rising_edge(Sort_Valid); @@ -200,18 +219,12 @@ begin wait until falling_edge(Clock); Check := TRUE; - if (Sort_IsKey = '1') then - LastValue := (others => '0'); - for j in 0 to INPUTS - 1 loop - CurValue := unsigned(Sort_Data(j)(KEY_BITS - 1 downto 0)); - Check := Check and (LastValue <= CurValue); - LastValue := CurValue; - end loop; - simAssertion(Check, "Result is not monotonic." & raw_format_slv_hex(std_logic_vector(LastValue))); - else - -- no routine implemented to check if sorting network is switched as in the previous cycles - end if; + ScoreBoardData.IsKey := Sort_IsKey; + ScoreBoardData.Meta := Sort_Meta; + ScoreBoardData.Data := Sort_Data; + ScoreBoard.Check(ScoreBoardData); end loop; + -- simAssertion(Check, "Result is not monotonic." & raw_format_slv_hex(std_logic_vector(LastValue))); -- This process is finished simDeactivateProcess(simProcessID); diff --git a/tb/sort/sortnet/sortnet_OddEvenSort_tb.files b/tb/sort/sortnet/sortnet_OddEvenSort_tb.files index 55fd9955..2aab8cf0 100644 --- a/tb/sort/sortnet/sortnet_OddEvenSort_tb.files +++ b/tb/sort/sortnet/sortnet_OddEvenSort_tb.files @@ -11,4 +11,5 @@ include "lib/OSVVM.files" # Open Source VHDL Verification Meth include "src/sort/sortnet/sortnet_OddEvenSort.files" # UUT (Unit Under Test) # Testbench file(s) +vhdl test "tb/sort/sortnet/sortnet_tb.pkg.vhdl" # Testbench package vhdl test "tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl" # Testbench diff --git a/tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl b/tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl index f254ea5b..42ba4c6e 100644 --- a/tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl +++ b/tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl @@ -33,6 +33,9 @@ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; +library OSVVM; +use OSVVM.RandomPkg.all; + library PoC; use PoC.utils.all; use PoC.vectors.all; @@ -43,8 +46,7 @@ use PoC.sim_types.all; use PoC.simulation.all; use PoC.waveform.all; -library OSVVM; -use OSVVM.RandomPkg.all; +library Test; entity sortnet_OddEvenSort_tb is @@ -52,14 +54,13 @@ end entity; architecture tb of sortnet_OddEvenSort_tb is - constant TAG_BITS : positive := 4; constant INPUTS : positive := 64; constant DATA_COLUMNS : positive := 2; - constant KEY_BITS : positive := 8; - constant DATA_BITS : positive := 32; + constant KEY_BITS : positive := 32; + constant DATA_BITS : positive := 64; constant META_BITS : positive := TAG_BITS; constant PIPELINE_STAGE_AFTER : natural := 2; @@ -68,30 +69,13 @@ architecture tb of sortnet_OddEvenSort_tb is constant STAGES : positive := INPUTS; constant DELAY : natural := STAGES / PIPELINE_STAGE_AFTER; - subtype T_DATA is std_logic_vector(DATA_BITS - 1 downto 0); - type T_DATA_VECTOR is array(natural range <>) of T_DATA; - - function to_dv(slm : T_SLM) return T_DATA_VECTOR is - variable Result : T_DATA_VECTOR(slm'range(1)); - begin - for i in slm'high(1) downto slm'low(1) loop - for j in T_DATA'range loop - Result(i)(j) := slm(i, j); - end loop; - end loop; - return Result; - end function; - - function to_slm(dv : T_DATA_VECTOR) return T_SLM is - variable Result : T_SLM(dv'range, T_DATA'range); - begin - for i in dv'range loop - for j in T_DATA'range loop - Result(i, j) := dv(i)(j); - end loop; - end loop; - return Result; - end function; + package P_SORTNET_TB is new Test.sortnet_tb + generic map ( + META_BITS => META_BITS, + DATA_BITS => DATA_BITS, + INPUTS => INPUTS + ); + use P_SORTNET_TB.all; constant CLOCK_FREQ : FREQ := 100 MHz; signal Clock : std_logic := '1'; @@ -109,6 +93,8 @@ architecture tb of sortnet_OddEvenSort_tb is signal DataInputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0); signal DataOutputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0); + shared variable ScoreBoard : PT_SCOREBOARD; + begin -- initialize global simulation status simInitialize; @@ -123,34 +109,63 @@ begin simGenerateClock(Clock, CLOCK_FREQ); procGenerator : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Generator"); - - variable RandomVar : RandomPType; -- protected type from RandomPkg - - variable KeyInput : std_logic_vector(KEY_BITS - 1 downto 0); - variable DataInput : std_logic_vector(DATA_BITS - KEY_BITS - 1 downto 0); - variable TagInput : std_logic_vector(TAG_BITS - 1 downto 0); - + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Generator"); + variable RandomVar : RandomPType; -- protected type from RandomPkg + + variable KeyInput : std_logic_vector(KEY_BITS - 1 downto 0); + variable DataInput : std_logic_vector(DATA_BITS - KEY_BITS - 1 downto 0); + variable TagInput : std_logic_vector(TAG_BITS - 1 downto 0); + variable Generator_Input : T_DATA_VECTOR(INPUTS - 1 downto 0); + + function GreaterThan(L : std_logic_vector; R : std_logic_vector) return boolean is + alias LL is L(KEY_BITS - 1 downto 0); + alias RR is R(KEY_BITS - 1 downto 0); + begin + return unsigned(LL) > unsigned(RR); + end function; + + variable ScoreBoardData : T_SCOREBOARD_DATA; begin RandomVar.InitSeed(RandomVar'instance_name); -- Generate initial seeds Generator_Valid <= '0'; Generator_IsKey <= '0'; - Generator_Data <= (others => (others => '0')); + Generator_Input := (others => (others => '0')); Generator_Meta <= (others => '0'); wait until rising_edge(Clock); Generator_Valid <= '1'; for i in 0 to LOOP_COUNT - 1 loop - Generator_IsKey <= to_sl(i mod DATA_COLUMNS = 0); - for j in 0 to INPUTS - 1 loop - KeyInput := RandomVar.RandSlv(KEY_BITS); - DataInput := RandomVar.RandSlv(DATA_BITS - KEY_BITS); - TagInput := RandomVar.RandSlv(TAG_BITS); - - Generator_Data(j) <= DataInput & KeyInput; - Generator_Meta <= resize(TagInput, META_BITS); + TagInput := RandomVar.RandSlv(TAG_BITS); + + ScoreBoardData.IsKey := to_sl(i mod DATA_COLUMNS = 0); + ScoreBoardData.Meta := resize(TagInput, META_BITS); + Generator_IsKey <= ScoreBoardData.IsKey; + Generator_Meta <= ScoreBoardData.Meta; + + KeyInput := RandomVar.RandSlv(KEY_BITS); + DataInput := RandomVar.RandSlv(DATA_BITS - KEY_BITS); + Generator_Input(0) := DataInput & KeyInput; + ScoreBoardData.Data(0):= Generator_Input(0); + + loop_j: for j in 1 to INPUTS - 1 loop + KeyInput := RandomVar.RandSlv(KEY_BITS); + DataInput := RandomVar.RandSlv(DATA_BITS - KEY_BITS); + Generator_Input(j) := DataInput & KeyInput; + + for k in j downto 1 loop + if GreaterThan(ScoreBoardData.Data(k - 1), Generator_Input(j)) then + ScoreBoardData.Data(k) := ScoreBoardData.Data(k - 1); + else + ScoreBoardData.Data(k) := Generator_Input(j); + next loop_j; + end if; + end loop; + ScoreBoardData.Data(0) := Generator_Input(j); end loop; + + Generator_Data <= Generator_Input; + ScoreBoard.Push(ScoreBoardData); wait until rising_edge(Clock); end loop; @@ -190,10 +205,12 @@ begin Sort_Data <= to_dv(DataOutputMatrix); procChecker : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Checker"); - variable Check : boolean; - variable CurValue : unsigned(KEY_BITS - 1 downto 0); - variable LastValue : unsigned(KEY_BITS - 1 downto 0); + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Checker"); + variable Check : boolean; + variable CurValue : unsigned(KEY_BITS - 1 downto 0); + variable LastValue : unsigned(KEY_BITS - 1 downto 0); + + variable ScoreBoardData : T_SCOREBOARD_DATA; begin wait until rising_edge(Sort_Valid); @@ -201,18 +218,12 @@ begin wait until falling_edge(Clock); Check := TRUE; - if (Sort_IsKey = '1') then - LastValue := (others => '0'); - for j in 0 to INPUTS - 1 loop - CurValue := unsigned(Sort_Data(j)(KEY_BITS - 1 downto 0)); - Check := Check and (LastValue <= CurValue); - LastValue := CurValue; - end loop; - simAssertion(Check, "Result is not monotonic." & raw_format_slv_hex(std_logic_vector(LastValue))); - else - -- no routine implemented to check if sorting network is switched as in the previous cycles - end if; + ScoreBoardData.IsKey := Sort_IsKey; + ScoreBoardData.Meta := Sort_Meta; + ScoreBoardData.Data := Sort_Data; + ScoreBoard.Check(ScoreBoardData); end loop; + -- simAssertion(Check, "Result is not monotonic." & raw_format_slv_hex(std_logic_vector(LastValue))); -- This process is finished simDeactivateProcess(simProcessID); diff --git a/tb/sort/sortnet/sortnet_tb.pkg.vhdl b/tb/sort/sortnet/sortnet_tb.pkg.vhdl new file mode 100644 index 00000000..a70137a7 --- /dev/null +++ b/tb/sort/sortnet/sortnet_tb.pkg.vhdl @@ -0,0 +1,125 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Authors: Patrick Lehmann +-- +-- Module: TODO +-- +-- Description: +-- ------------------------------------ +-- TODO +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany +-- Chair of VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +library OSVVM; + +library PoC; +use PoC.utils.all; +use PoC.vectors.all; +use PoC.strings.all; + + +package sortnet_tb is + generic ( + META_BITS : positive; + DATA_BITS : positive; + INPUTS : positive + ); + + subtype T_DATA is std_logic_vector(DATA_BITS - 1 downto 0); + type T_DATA_VECTOR is array(natural range <>) of T_DATA; + + function to_dv(slm : T_SLM) return T_DATA_VECTOR; + function to_slm(dv : T_DATA_VECTOR) return T_SLM; + + type T_SCOREBOARD_DATA is record + IsKey : std_logic; + Meta : std_logic_vector(META_BITS - 1 downto 0); + Data : T_DATA_VECTOR(INPUTS - 1 downto 0); + end record; + + function match(expected : T_SCOREBOARD_DATA; actual : T_SCOREBOARD_DATA) return boolean; + function to_string(dataset : T_SCOREBOARD_DATA) return string; + + package P_SCOREBOARD is new OSVVM.ScoreboardGenericPkg + generic map ( + ExpectedType => T_SCOREBOARD_DATA, + ActualType => T_SCOREBOARD_DATA, + Match => match, + expected_to_string => to_string, --[T_SCOREBOARD_DATA return string], + actual_to_string => to_string + ); + + alias PT_SCOREBOARD is P_SCOREBOARD.ScoreBoardPType; +end package; + + +package body sortnet_tb is + function match(expected : T_SCOREBOARD_DATA; actual : T_SCOREBOARD_DATA) return boolean is + variable good : boolean; + begin + good := (expected.IsKey = actual.IsKey); + good := good and (expected.Meta = actual.Meta); + if (expected.IsKey = '1') then + for i in expected.Data'range loop + good := good and (expected.Data(i) = actual.Data(i)); + exit when (good = FALSE); + end loop; + end if; + return good; + end function; + + function to_string(dataset : T_SCOREBOARD_DATA) return string is + variable KeyMarker : string(1 to 2); + begin + KeyMarker := ite((dataset.IsKey = '1'), "* ", " "); + -- for i in 0 to 0 loop --dataset.Key'range loop + return "Data: " & to_string(dataset.Data(0), 'h') & KeyMarker & + " Meta: " & to_string(dataset.Meta, 'h'); + -- end loop; + end function; + + function to_dv(slm : T_SLM) return T_DATA_VECTOR is + variable Result : T_DATA_VECTOR(slm'range(1)); + begin + for i in slm'high(1) downto slm'low(1) loop + for j in T_DATA'range loop + Result(i)(j) := slm(i, j); + end loop; + end loop; + return Result; + end function; + + function to_slm(dv : T_DATA_VECTOR) return T_SLM is + variable Result : T_SLM(dv'range, T_DATA'range); + begin + for i in dv'range loop + for j in T_DATA'range loop + Result(i, j) := dv(i)(j); + end loop; + end loop; + return Result; + end function; +end package body; diff --git a/tools/precompile/compile-osvvm.ps1 b/tools/precompile/compile-osvvm.ps1 index 7bd374fb..6c32ec2f 100644 --- a/tools/precompile/compile-osvvm.ps1 +++ b/tools/precompile/compile-osvvm.ps1 @@ -151,6 +151,8 @@ if ($Questa) "AlertLogPkg.vhd", "MemoryPkg.vhd", "MessagePkg.vhd", + "SortListGenericPkg.vhd", + "SortListPkg.vhd", "SortListPkg_int.vhd", "RandomBasePkg.vhd", "RandomPkg.vhd", diff --git a/tools/precompile/compile-osvvm.sh b/tools/precompile/compile-osvvm.sh index fe9b7ffd..de30b57e 100755 --- a/tools/precompile/compile-osvvm.sh +++ b/tools/precompile/compile-osvvm.sh @@ -206,6 +206,8 @@ if [ "$COMPILE_FOR_VSIM" == "TRUE" ]; then AlertLogPkg.vhd MemoryPkg.vhd MessagePkg.vhd + SortListGenericPkg.vhd + SortListPkg.vhd SortListPkg_int.vhd RandomBasePkg.vhd RandomPkg.vhd From e875336930feaad06cc2902f1b067aedec8037f3 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 23 Nov 2016 16:58:33 +0100 Subject: [PATCH 63/97] Fixed links in README files. Added files for the Appveyor flow. --- py/Base/Logging.py | 51 ++++++++++++++++-------------- py/ToolChains/Aldec/ActiveHDL.py | 12 +++---- py/ToolChains/Altera/Quartus.py | 8 ++--- py/ToolChains/GHDL.py | 6 ++-- py/ToolChains/Git.py | 4 +-- py/ToolChains/Lattice/Diamond.py | 4 +-- py/ToolChains/Mentor/QuestaSim.py | 12 +++---- py/ToolChains/Xilinx/ISE.py | 14 ++++---- py/ToolChains/Xilinx/Vivado.py | 12 +++---- py/ToolChains/__init__.py | 2 +- src/mem/README.md | 2 +- src/mem/ddr2/README.md | 2 +- src/mem/ddr3/README.md | 2 +- src/mem/lut/README.md | 2 +- src/mem/ocram/README.md | 2 +- src/mem/ocrom/README.md | 2 +- src/mem/sdram/README.md | 2 +- tools/AppVeyor/config.private.ini | 50 +++++++++++++++++++++++++++++ tools/AppVeyor/my_project.vhdl | 47 +++++++++++++++++++++++++++ tools/AppVeyor/requirements.txt | 1 + tools/Travis-CI/config.private.ini | 25 +++++++++++---- tools/Travis-CI/my_project.vhdl | 4 +-- 22 files changed, 190 insertions(+), 76 deletions(-) create mode 100644 tools/AppVeyor/config.private.ini create mode 100644 tools/AppVeyor/my_project.vhdl create mode 100644 tools/AppVeyor/requirements.txt diff --git a/py/Base/Logging.py b/py/Base/Logging.py index 4d41b6b2..256b15b5 100644 --- a/py/Base/Logging.py +++ b/py/Base/Logging.py @@ -190,64 +190,67 @@ def WriteDryRun(self, message, indent=2): class ILogable: + """A mixin class to support local logging methods.""" def __init__(self, logger=None): - self._Logger = logger + self._logger = logger @property def Logger(self): - return self._Logger + """Return the local logger instance.""" + return self._logger def Log(self, entry): - if self._Logger is not None: - return self._Logger.Write(entry) + """Write an entry to the local logger.""" + if self._logger is not None: + return self._logger.Write(entry) return False def _TryLog(self, *args, **kwargs): - if self._Logger is not None: - return self._Logger.TryWrite(*args, **kwargs) + if self._logger is not None: + return self._logger.TryWrite(*args, **kwargs) return False def LogFatal(self, *args, **kwargs): - if self._Logger is not None: - return self._Logger.WriteFatal(*args, **kwargs) + if self._logger is not None: + return self._logger.WriteFatal(*args, **kwargs) return False def LogError(self, *args, **kwargs): - if self._Logger is not None: - return self._Logger.WriteError(*args, **kwargs) + if self._logger is not None: + return self._logger.WriteError(*args, **kwargs) return False def LogWarning(self, *args, **kwargs): - if self._Logger is not None: - return self._Logger.WriteWarning(*args, **kwargs) + if self._logger is not None: + return self._logger.WriteWarning(*args, **kwargs) return False def LogInfo(self, *args, **kwargs): - if self._Logger is not None: - return self._Logger.WriteInfo(*args, **kwargs) + if self._logger is not None: + return self._logger.WriteInfo(*args, **kwargs) return False def LogQuiet(self, *args, **kwargs): - if self._Logger is not None: - return self._Logger.WriteQuiet(*args, **kwargs) + if self._logger is not None: + return self._logger.WriteQuiet(*args, **kwargs) return False def LogNormal(self, *args, **kwargs): - if self._Logger is not None: - return self._Logger.WriteNormal(*args, **kwargs) + if self._logger is not None: + return self._logger.WriteNormal(*args, **kwargs) return False def LogVerbose(self, *args, **kwargs): - if self._Logger is not None: - return self._Logger.WriteVerbose(*args, **kwargs) + if self._logger is not None: + return self._logger.WriteVerbose(*args, **kwargs) return False def LogDebug(self, *args, **kwargs): - if self._Logger is not None: - return self._Logger.WriteDebug(*args, **kwargs) + if self._logger is not None: + return self._logger.WriteDebug(*args, **kwargs) return False def LogDryRun(self, *args, **kwargs): - if self._Logger is not None: - return self._Logger.WriteDryRun(*args, **kwargs) + if self._logger is not None: + return self._logger.WriteDryRun(*args, **kwargs) return False diff --git a/py/ToolChains/Aldec/ActiveHDL.py b/py/ToolChains/Aldec/ActiveHDL.py index f65241b6..f49a3083 100644 --- a/py/ToolChains/Aldec/ActiveHDL.py +++ b/py/ToolChains/Aldec/ActiveHDL.py @@ -134,11 +134,11 @@ class VHDLCompiler(Executable, ToolMixIn): def __init__(self, toolchain : ToolMixIn): ToolMixIn.__init__( self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, - toolchain._Logger) + toolchain._logger) if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "vcom.exe" else: raise PlatformNotSupportedException(self._platform) - super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._logger) self._hasOutput = False self._hasWarnings = False @@ -233,11 +233,11 @@ class StandaloneSimulator(Executable, ToolMixIn): def __init__(self, toolchain : ToolMixIn): ToolMixIn.__init__( self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, - toolchain._Logger) + toolchain._logger) if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "vsimsa.exe" else: raise PlatformNotSupportedException(self._platform) - super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._logger) self._hasOutput = False self._hasWarnings = False @@ -374,11 +374,11 @@ class ActiveHDLVHDLLibraryTool(Executable, ToolMixIn): def __init__(self, toolchain : ToolMixIn): ToolMixIn.__init__( self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, - toolchain._Logger) + toolchain._logger) if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "vlib.exe" else: raise PlatformNotSupportedException(self._platform) - super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._logger) self._hasOutput = False self._hasWarnings = False diff --git a/py/ToolChains/Altera/Quartus.py b/py/ToolChains/Altera/Quartus.py index 0bf6bb8c..2468e548 100644 --- a/py/ToolChains/Altera/Quartus.py +++ b/py/ToolChains/Altera/Quartus.py @@ -131,12 +131,12 @@ class Map(Executable, ToolMixIn): def __init__(self, toolchain : ToolMixIn): ToolMixIn.__init__( self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, - toolchain._Logger) + toolchain._logger) if (self._platform == "Windows") : executablePath = self._binaryDirectoryPath / "quartus_map.exe" elif (self._platform == "Linux") : executablePath = self._binaryDirectoryPath / "quartus_map" else : raise PlatformNotSupportedException(self._platform) - Executable.__init__(self, self._platform, self._dryrun, executablePath, logger=self._Logger) + Executable.__init__(self, self._platform, self._dryrun, executablePath, logger=self._logger) self.Parameters[self.Executable] = executablePath @@ -215,12 +215,12 @@ class TclShell(Executable, ToolMixIn): def __init__(self, toolchain : ToolMixIn): ToolMixIn.__init__( self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, - toolchain._Logger) + toolchain._logger) if (self._platform == "Windows") : executablePath = self._binaryDirectoryPath / "quartus_sh.exe" elif (self._platform == "Linux") : executablePath = self._binaryDirectoryPath / "quartus_sh" else : raise PlatformNotSupportedException(self._platform) - super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._logger) self.Parameters[self.Executable] = executablePath diff --git a/py/ToolChains/GHDL.py b/py/ToolChains/GHDL.py index 0c6e1e72..e55a1cba 100644 --- a/py/ToolChains/GHDL.py +++ b/py/ToolChains/GHDL.py @@ -332,7 +332,7 @@ class SwitchWaveformOptionFile(metaclass=LongValuedFlagArgument): ) def GetGHDLAnalyze(self): - ghdl = GHDLAnalyze(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, self._backend, logger=self._Logger) + ghdl = GHDLAnalyze(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, self._backend, logger=self._logger) for param in ghdl.Parameters: if (param is not ghdl.Executable): ghdl.Parameters[param] = None @@ -340,7 +340,7 @@ def GetGHDLAnalyze(self): return ghdl def GetGHDLElaborate(self): - ghdl = GHDLElaborate(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, self._backend, logger=self._Logger) + ghdl = GHDLElaborate(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, self._backend, logger=self._logger) for param in ghdl.Parameters: if (param is not ghdl.Executable): ghdl.Parameters[param] = None @@ -348,7 +348,7 @@ def GetGHDLElaborate(self): return ghdl def GetGHDLRun(self): - ghdl = GHDLRun(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, self._backend, logger=self._Logger) + ghdl = GHDLRun(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, self._backend, logger=self._logger) for param in ghdl.Parameters: if (param is not ghdl.Executable): ghdl.Parameters[param] = None diff --git a/py/ToolChains/Git.py b/py/ToolChains/Git.py index 8f73852b..cabf66e0 100644 --- a/py/ToolChains/Git.py +++ b/py/ToolChains/Git.py @@ -352,13 +352,13 @@ class GitSCM(Executable, ToolMixIn): def __init__(self, toolchain : ToolMixIn): ToolMixIn.__init__( self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, - toolchain._Logger) + toolchain._logger) if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "git.exe" elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "git" elif (self._platform == "Darwin"): executablePath = self._binaryDirectoryPath / "git" else: raise PlatformNotSupportedException(self._platform) - super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._logger) self.Parameters[self.Executable] = executablePath diff --git a/py/ToolChains/Lattice/Diamond.py b/py/ToolChains/Lattice/Diamond.py index f425800d..55c023e3 100644 --- a/py/ToolChains/Lattice/Diamond.py +++ b/py/ToolChains/Lattice/Diamond.py @@ -149,12 +149,12 @@ class Synth(Executable, ToolMixIn): def __init__(self, toolchain : ToolMixIn): ToolMixIn.__init__( self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, - toolchain._Logger) + toolchain._logger) if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "synthesis.exe" elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "synthesis" else: raise PlatformNotSupportedException(self._platform) - super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._logger) self.Parameters[self.Executable] = executablePath diff --git a/py/ToolChains/Mentor/QuestaSim.py b/py/ToolChains/Mentor/QuestaSim.py index 45c9b482..834c1d8f 100644 --- a/py/ToolChains/Mentor/QuestaSim.py +++ b/py/ToolChains/Mentor/QuestaSim.py @@ -154,12 +154,12 @@ class QuestaVHDLCompiler(Executable, ToolMixIn): def __init__(self, toolchain : ToolMixIn): ToolMixIn.__init__( self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, - toolchain._Logger) + toolchain._logger) if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "vcom.exe" elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "vcom" else: raise PlatformNotSupportedException(self._platform) - super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._logger) self.Parameters[self.Executable] = executablePath @@ -275,12 +275,12 @@ class QuestaSimulator(Executable, ToolMixIn): def __init__(self, toolchain : ToolMixIn): ToolMixIn.__init__( self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, - toolchain._Logger) + toolchain._logger) if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "vsim.exe" elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "vsim" else: raise PlatformNotSupportedException(self._platform) - super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._logger) self.Parameters[self.Executable] = executablePath @@ -418,12 +418,12 @@ class QuestaVHDLLibraryTool(Executable, ToolMixIn): def __init__(self, toolchain : ToolMixIn): ToolMixIn.__init__( self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, - toolchain._Logger) + toolchain._logger) if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "vlib.exe" elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "vlib" else: raise PlatformNotSupportedException(self._platform) - super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._logger) self.Parameters[self.Executable] = executablePath diff --git a/py/ToolChains/Xilinx/ISE.py b/py/ToolChains/Xilinx/ISE.py index 83c3727a..f3e2b95f 100644 --- a/py/ToolChains/Xilinx/ISE.py +++ b/py/ToolChains/Xilinx/ISE.py @@ -127,7 +127,7 @@ def __CheckISEVersion(self, binPath): class ISE(ToolMixIn): def GetVHDLCompiler(self): raise NotImplementedError("ISE.GetVHDLCompiler") - # return ISEVHDLCompiler(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) + # return ISEVHDLCompiler(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._logger) def GetFuse(self): return Fuse(self) @@ -143,12 +143,12 @@ class Fuse(Executable, ToolMixIn): def __init__(self, toolchain : ToolMixIn): ToolMixIn.__init__( self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, - toolchain._Logger) + toolchain._logger) if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "fuse.exe" elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "fuse" else: raise PlatformNotSupportedException(self._platform) - super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._logger) self.Parameters[self.Executable] = executablePath @@ -324,12 +324,12 @@ class Xst(Executable, ToolMixIn): def __init__(self, toolchain : ToolMixIn): ToolMixIn.__init__( self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, - toolchain._Logger) + toolchain._logger) if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "xst.exe" elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "xst" else: raise PlatformNotSupportedException(self._platform) - Executable.__init__(self, self._platform, self._dryrun, executablePath, logger=self._Logger) + Executable.__init__(self, self._platform, self._dryrun, executablePath, logger=self._logger) self.Parameters[self.Executable] = executablePath @@ -407,12 +407,12 @@ class CoreGenerator(Executable, ToolMixIn): def __init__(self, toolchain : ToolMixIn): ToolMixIn.__init__( self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, - toolchain._Logger) + toolchain._logger) if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "coregen.exe" elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "coregen" else: raise PlatformNotSupportedException(self._platform) - super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._logger) self.Parameters[self.Executable] = executablePath diff --git a/py/ToolChains/Xilinx/Vivado.py b/py/ToolChains/Xilinx/Vivado.py index 30d35cbf..66e9c386 100644 --- a/py/ToolChains/Xilinx/Vivado.py +++ b/py/ToolChains/Xilinx/Vivado.py @@ -136,12 +136,12 @@ class XElab(Executable, ToolMixIn): def __init__(self, toolchain : ToolMixIn): ToolMixIn.__init__( self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, - toolchain._Logger) + toolchain._logger) if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "xelab.bat" elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "xelab" else: raise PlatformNotSupportedException(self._platform) - super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._logger) self.Parameters[self.Executable] = executablePath @@ -266,12 +266,12 @@ class XSim(Executable, ToolMixIn): def __init__(self, toolchain : ToolMixIn): ToolMixIn.__init__( self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, - toolchain._Logger) + toolchain._logger) if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "xsim.bat" elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "xsim" else: raise PlatformNotSupportedException(self._platform) - super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._logger) self.Parameters[self.Executable] = executablePath @@ -364,12 +364,12 @@ class Synth(Executable, ToolMixIn): def __init__(self, toolchain : ToolMixIn): ToolMixIn.__init__( self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, - toolchain._Logger) + toolchain._logger) if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "vivado.bat" elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "vivado" else: raise PlatformNotSupportedException(self._platform) - super().__init__(self._platform, self._dryrun, executablePath, logger=self._Logger) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._logger) self.Parameters[self.Executable] = executablePath diff --git a/py/ToolChains/__init__.py b/py/ToolChains/__init__.py index 1cfae690..c3f6d23b 100644 --- a/py/ToolChains/__init__.py +++ b/py/ToolChains/__init__.py @@ -37,7 +37,7 @@ def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): self._dryrun = dryrun self._binaryDirectoryPath = binaryDirectoryPath self._version = version - self._Logger = logger + self._logger = logger from .PoC import Configuration as PoC_Configuration diff --git a/src/mem/README.md b/src/mem/README.md index cd035aaa..56b692da 100644 --- a/src/mem/README.md +++ b/src/mem/README.md @@ -13,4 +13,4 @@ implementations. - [`PoC.mem.ocrom`](ocrom) - On-Chip ROM abstraction layer - [`PoC.mem.sdram`](sdram) - SDRAM controllers -Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/PoC/mem/index.html). +Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/IPCores/mem/index.html). diff --git a/src/mem/ddr2/README.md b/src/mem/ddr2/README.md index 8174dc17..53c00217 100644 --- a/src/mem/ddr2/README.md +++ b/src/mem/ddr2/README.md @@ -5,4 +5,4 @@ DDR2 memory controllers as well as for adapters for vendor-specific implementations. At the top-level, all controllers and adapters provide the same simple memory interface to the user application. -Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/PoC/mem/ddr2/index.html). +Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/IPCores/mem/ddr2/index.html). diff --git a/src/mem/ddr3/README.md b/src/mem/ddr3/README.md index c305d45a..3676a3c5 100644 --- a/src/mem/ddr3/README.md +++ b/src/mem/ddr3/README.md @@ -5,4 +5,4 @@ DDR3 memory controllers as well as for adapters for vendor-specific implementations. At the top-level, all controllers and adapters provide the same simple memory interface to the user application. -Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/PoC/mem/ddr3/index.html). +Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/IPCores/mem/ddr3/index.html). diff --git a/src/mem/lut/README.md b/src/mem/lut/README.md index b30ca7d5..1f59e77b 100644 --- a/src/mem/lut/README.md +++ b/src/mem/lut/README.md @@ -2,4 +2,4 @@ The namespace `PoC.mem.lut` offers different lookup-tables (LUTs). -Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/PoC/mem/lut/index.html). +Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/IPCores/mem/lut/index.html). diff --git a/src/mem/ocram/README.md b/src/mem/ocram/README.md index f71bcc4d..ee48dab4 100644 --- a/src/mem/ocram/README.md +++ b/src/mem/ocram/README.md @@ -2,4 +2,4 @@ The namespace `PoC.mem.ocram` offers different on-chip RAM abstractions. -Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/PoC/mem/ocram/index.html). +Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/IPCores/mem/ocram/index.html). diff --git a/src/mem/ocrom/README.md b/src/mem/ocrom/README.md index 9144b65a..d4157939 100644 --- a/src/mem/ocrom/README.md +++ b/src/mem/ocrom/README.md @@ -2,4 +2,4 @@ The namespace `PoC.mem.ocrom` offers different on-chip ROM abstractions. -Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/PoC/mem/ocrom/index.html). +Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/IPCores/mem/ocrom/index.html). diff --git a/src/mem/sdram/README.md b/src/mem/sdram/README.md index c98e79d6..69df19ea 100644 --- a/src/mem/sdram/README.md +++ b/src/mem/sdram/README.md @@ -6,4 +6,4 @@ columns. Different physical layers are provide for the single-data-rate (SDR) or double-data-rate (DDR, DDR2, ...) data bus. One has to instantiate the specific module required by the FPGA board. -Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/PoC/mem/sdram/index.html). +Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/IPCores/mem/sdram/index.html). diff --git a/tools/AppVeyor/config.private.ini b/tools/AppVeyor/config.private.ini new file mode 100644 index 00000000..a2d0df44 --- /dev/null +++ b/tools/AppVeyor/config.private.ini @@ -0,0 +1,50 @@ +[INSTALL.PoC] +Version = 1.1.0 +InstallationDirectory = C:\projects\poc +RepositoryKind = Public +IsGitRepository = True +GitRemoteBranch = release + +[SOLUTION.Solutions] + +[INSTALL.Aldec] + +[INSTALL.Aldec.ActiveHDL] + +[INSTALL.Altera] + +[INSTALL.Altera.Quartus] + +[INSTALL.Altera.ModelSim] + +[INSTALL.Lattice] + +[INSTALL.Lattice.Diamond] + +[INSTALL.Lattice.ActiveHDL] + +[INSTALL.Mentor] + +[INSTALL.Mentor.ModelSimPE] + +[INSTALL.Mentor.QuestaSim] + +[INSTALL.Xilinx] + +[INSTALL.Xilinx.ISE] + +[INSTALL.Xilinx.Vivado] + +[INSTALL.Git] +InstallationDirectory = C:/Program Files/Git +BinaryDirectory = ${InstallationDirectory}/cmd +Version = 2.10.1 + +[INSTALL.GHDL] +Version = 0.34dev +InstallationDirectory = ${INSTALL.PoC:InstallationDirectory}/temp/AppVeyor/GHDL +BinaryDirectory = ${InstallationDirectory}/bin +ScriptDirectory = ${InstallationDirectory}/lib/ghdl/vendors +Backend = llvm + +[INSTALL.GTKWave] diff --git a/tools/AppVeyor/my_project.vhdl b/tools/AppVeyor/my_project.vhdl new file mode 100644 index 00000000..0dc04b69 --- /dev/null +++ b/tools/AppVeyor/my_project.vhdl @@ -0,0 +1,47 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Authors: Patrick Lehmann +-- +-- Package: Project specific configuration. +-- +-- Description: +-- ------------------------------------ +-- This is a template file. +-- +-- TODO +-- +-- USAGE: +-- 1) Copy this file into your project's source directory and rename it to +-- "my_project.vhdl". +-- 2) Add file to library "poc" in your synthesis tool. +-- 3) Change setup appropriately. +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany, +-- Chair of VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= +-- +library PoC; + + +package my_project is + -- Change these lines to setup configuration. + constant MY_PROJECT_DIR : string := "C:\projects\poc\"; + constant MY_OPERATING_SYSTEM : string := "WINDOWS"; +end package; diff --git a/tools/AppVeyor/requirements.txt b/tools/AppVeyor/requirements.txt new file mode 100644 index 00000000..522360ea --- /dev/null +++ b/tools/AppVeyor/requirements.txt @@ -0,0 +1 @@ +-r ../../requirements.txt diff --git a/tools/Travis-CI/config.private.ini b/tools/Travis-CI/config.private.ini index 7bd4c30b..57f11a91 100644 --- a/tools/Travis-CI/config.private.ini +++ b/tools/Travis-CI/config.private.ini @@ -12,19 +12,18 @@ InstallationDirectory = /home/travis/build/VLSI-EDA/PoC [INSTALL.Altera.Quartus] -[INSTALL.GHDL] -Version = 0.34dev -InstallationDirectory = ${INSTALL.PoC:InstallationDirectory}/temp/Travis-CI -BinaryDirectory = ${InstallationDirectory}/bin -ScriptDirectory = ${InstallationDirectory}/lib/ghdl/vendors -Backend = llvm +[INSTALL.Altera.ModelSim] [INSTALL.Lattice] [INSTALL.Lattice.Diamond] +[INSTALL.Lattice.ActiveHDL] + [INSTALL.Mentor] +[INSTALL.Mentor.ModelSimPE] + [INSTALL.Mentor.QuestaSim] [INSTALL.Xilinx] @@ -32,3 +31,17 @@ Backend = llvm [INSTALL.Xilinx.ISE] [INSTALL.Xilinx.Vivado] + +[INSTALL.Git] +InstallationDirectory = /usr +BinaryDirectory = ${InstallationDirectory}/bin +Version = 2.10.1 + +[INSTALL.GHDL] +Version = 0.34dev +InstallationDirectory = ${INSTALL.PoC:InstallationDirectory}/temp/Travis-CI +BinaryDirectory = ${InstallationDirectory}/bin +ScriptDirectory = ${InstallationDirectory}/lib/ghdl/vendors +Backend = llvm + +[INSTALL.GTKWave] diff --git a/tools/Travis-CI/my_project.vhdl b/tools/Travis-CI/my_project.vhdl index 675016e8..b9b02d8c 100644 --- a/tools/Travis-CI/my_project.vhdl +++ b/tools/Travis-CI/my_project.vhdl @@ -36,7 +36,7 @@ -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= - +-- library PoC; @@ -44,4 +44,4 @@ package my_project is -- Change these lines to setup configuration. constant MY_PROJECT_DIR : string := "/home/travis/build/VLSI-EDA/PoC/"; constant MY_OPERATING_SYSTEM : string := "LINUX"; -end; +end package; From aeae5e96ba7597fe052c73571607fcc755b08c79 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 23 Nov 2016 17:13:17 +0100 Subject: [PATCH 64/97] Added AppVeyor configuration file. --- .appveyor.yml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 .appveyor.yml diff --git a/.appveyor.yml b/.appveyor.yml new file mode 100644 index 00000000..fcb24d2f --- /dev/null +++ b/.appveyor.yml @@ -0,0 +1,14 @@ +version: 1.1.0-b{build} +clone_folder: c:\projects\poc +init: + # Checking that DEP is enabled + - ps: Write-Host "Initializing virtual machine ..." + - ps: git --version + +install: + - ps: Write-Host "Installing requirements..." + - ps: cp .\tools\AppVeyor\config.private.ini .\py\ + - ps: cp .\tools\AppVeyor\my_project.vhdl .\tb\common\ + - ps: .\poc.ps1 + +build: off From f2fb2415cfbfe45b75cb1a427cadb82fd05f51dd Mon Sep 17 00:00:00 2001 From: Martin Zabel Date: Wed, 23 Nov 2016 17:23:47 +0100 Subject: [PATCH 65/97] Updated documentation of PoC.mem package. --- docs/IPCores/mem/mem.pkg.rst | 16 +++++++++++++++- src/mem/mem.pkg.vhdl | 18 +++++++++++++++--- 2 files changed, 30 insertions(+), 4 deletions(-) diff --git a/docs/IPCores/mem/mem.pkg.rst b/docs/IPCores/mem/mem.pkg.rst index de7f45ef..35fa5997 100644 --- a/docs/IPCores/mem/mem.pkg.rst +++ b/docs/IPCores/mem/mem.pkg.rst @@ -14,7 +14,21 @@ PoC.mem Package =============== -This package holds all component declarations for this namespace. +This package holds all component declarations, types and functions of the +:ref:`PoC.mem ` namespace. + +It provides the following enumerations: + +* ``T_MEM_FILEFORMAT`` specifies whether a file is in Intel Hex, Lattice + Mem, or Xilinx Mem format. + +* ``T_MEM_CONTENT`` specifies whether data in text file is in binary, decimal + or hexadecimal format. + +It provides the following functions: + +* ``mem_FileExtension`` returns the file extension of a given filename. +* ``mem_ReadMemoryFile`` reads initial memory content from a given file. .. only:: latex diff --git a/src/mem/mem.pkg.vhdl b/src/mem/mem.pkg.vhdl index 3c804d06..4c7570e3 100644 --- a/src/mem/mem.pkg.vhdl +++ b/src/mem/mem.pkg.vhdl @@ -6,13 +6,25 @@ -- Patrick Lehmann -- -- Package: VHDL package for component declarations, types and functions --- associated to the PoC.mem.ocram namespace +-- of the PoC.mem namespace -- -- Description: -- ------------------------------------- --- On-Chip RAMs (Random-Access-Memory/Read-Write-Memory - RWM) for FPGAs. +-- This package holds all component declarations, types and functions of the +-- :ref:`PoC.mem ` namespace. -- --- A detailed documentation is included in each module. +-- It provides the following enumerations: +-- +-- * ``T_MEM_FILEFORMAT`` specifies whether a file is in Intel Hex, Lattice +-- Mem, or Xilinx Mem format. +-- +-- * ``T_MEM_CONTENT`` specifies whether data in text file is in binary, decimal +-- or hexadecimal format. +-- +-- It provides the following functions: +-- +-- * ``mem_FileExtension`` returns the file extension of a given filename. +-- * ``mem_ReadMemoryFile`` reads initial memory content from a given file. -- -- License: -- ============================================================================= From 8ed59845934e6cb6dabf0c86a0397261a30caecb Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 23 Nov 2016 17:58:26 +0100 Subject: [PATCH 66/97] Appveyor: Added test for Python version. Let PIP install all requirements. --- .appveyor.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.appveyor.yml b/.appveyor.yml index fcb24d2f..27e869b4 100644 --- a/.appveyor.yml +++ b/.appveyor.yml @@ -4,11 +4,14 @@ init: # Checking that DEP is enabled - ps: Write-Host "Initializing virtual machine ..." - ps: git --version + - ps: ll c:\ install: - ps: Write-Host "Installing requirements..." - ps: cp .\tools\AppVeyor\config.private.ini .\py\ - ps: cp .\tools\AppVeyor\my_project.vhdl .\tb\common\ + - ps: python --version + - ps: python -m pip install -r .\requirements.txt - ps: .\poc.ps1 build: off From c170898291699e814b162d8c61168fe4a44dbcae Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 23 Nov 2016 18:01:27 +0100 Subject: [PATCH 67/97] AppVeyor: Changed command 'll' to 'ls'. --- .appveyor.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.appveyor.yml b/.appveyor.yml index 27e869b4..461e96fb 100644 --- a/.appveyor.yml +++ b/.appveyor.yml @@ -4,7 +4,7 @@ init: # Checking that DEP is enabled - ps: Write-Host "Initializing virtual machine ..." - ps: git --version - - ps: ll c:\ + - ps: dir c:\ install: - ps: Write-Host "Installing requirements..." From 1ba63d6962c993e09770d92383167c3a4acae64f Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 23 Nov 2016 18:19:07 +0100 Subject: [PATCH 68/97] AppVeyor: Debugging the environment. --- .appveyor.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.appveyor.yml b/.appveyor.yml index 461e96fb..b445cf73 100644 --- a/.appveyor.yml +++ b/.appveyor.yml @@ -10,6 +10,8 @@ install: - ps: Write-Host "Installing requirements..." - ps: cp .\tools\AppVeyor\config.private.ini .\py\ - ps: cp .\tools\AppVeyor\my_project.vhdl .\tb\common\ + - ps: dir env: + - ps: $env:PATH - ps: python --version - ps: python -m pip install -r .\requirements.txt - ps: .\poc.ps1 From 671e0c624e01f007d68be7fcf7ef2f927137b42e Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 23 Nov 2016 18:21:18 +0100 Subject: [PATCH 69/97] AppVeyor: Fixed Syntax error. --- .appveyor.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.appveyor.yml b/.appveyor.yml index b445cf73..e2fd13f4 100644 --- a/.appveyor.yml +++ b/.appveyor.yml @@ -10,8 +10,8 @@ install: - ps: Write-Host "Installing requirements..." - ps: cp .\tools\AppVeyor\config.private.ini .\py\ - ps: cp .\tools\AppVeyor\my_project.vhdl .\tb\common\ - - ps: dir env: - - ps: $env:PATH + - ps: dir "env:" + - ps: Write-Host $env:PATH - ps: python --version - ps: python -m pip install -r .\requirements.txt - ps: .\poc.ps1 From 57f8c9cd44b73b2c3ca125944700382ade7e18be Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 23 Nov 2016 18:36:54 +0100 Subject: [PATCH 70/97] AppVeyor: Configured Python 3.5 64-bit as default Python version. --- .appveyor.yml | 7 +++---- tools/AppVeyor/config.private.ini | 2 +- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/.appveyor.yml b/.appveyor.yml index e2fd13f4..8ef75a51 100644 --- a/.appveyor.yml +++ b/.appveyor.yml @@ -5,15 +5,14 @@ init: - ps: Write-Host "Initializing virtual machine ..." - ps: git --version - ps: dir c:\ + - ps: $env:Path = $env:Path.Replace("Python27", "Python35-x64") install: - ps: Write-Host "Installing requirements..." + - ps: python -m pip install -r .\requirements.txt + - ps: Write-Host "Configuring PoC..." - ps: cp .\tools\AppVeyor\config.private.ini .\py\ - ps: cp .\tools\AppVeyor\my_project.vhdl .\tb\common\ - - ps: dir "env:" - - ps: Write-Host $env:PATH - - ps: python --version - - ps: python -m pip install -r .\requirements.txt - ps: .\poc.ps1 build: off diff --git a/tools/AppVeyor/config.private.ini b/tools/AppVeyor/config.private.ini index a2d0df44..fc0d6409 100644 --- a/tools/AppVeyor/config.private.ini +++ b/tools/AppVeyor/config.private.ini @@ -38,7 +38,7 @@ GitRemoteBranch = release [INSTALL.Git] InstallationDirectory = C:/Program Files/Git BinaryDirectory = ${InstallationDirectory}/cmd -Version = 2.10.1 +Version = 2.8.2 [INSTALL.GHDL] Version = 0.34dev From 91defd34ab0a2c9a73353a1a1c14e8ce11e3e24a Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 23 Nov 2016 18:48:33 +0100 Subject: [PATCH 71/97] AppVeyor: Upgrade PIP to avoid a bad return code. --- .appveyor.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.appveyor.yml b/.appveyor.yml index 8ef75a51..fe02d666 100644 --- a/.appveyor.yml +++ b/.appveyor.yml @@ -9,7 +9,10 @@ init: install: - ps: Write-Host "Installing requirements..." + - ps: python --version + - ps: python -m pip --upgrade pip - ps: python -m pip install -r .\requirements.txt + - ps: python -m pip list - ps: Write-Host "Configuring PoC..." - ps: cp .\tools\AppVeyor\config.private.ini .\py\ - ps: cp .\tools\AppVeyor\my_project.vhdl .\tb\common\ From c183d0604d3dc1a8447959564c8fca2e9da35a08 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 23 Nov 2016 18:50:29 +0100 Subject: [PATCH 72/97] AppVeyor: Next try. --- .appveyor.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.appveyor.yml b/.appveyor.yml index fe02d666..5e7fc551 100644 --- a/.appveyor.yml +++ b/.appveyor.yml @@ -10,7 +10,7 @@ init: install: - ps: Write-Host "Installing requirements..." - ps: python --version - - ps: python -m pip --upgrade pip + - ps: python -m pip install pip --upgrade - ps: python -m pip install -r .\requirements.txt - ps: python -m pip list - ps: Write-Host "Configuring PoC..." From b6503322c4868df641777cb78c45799ba6cf40e0 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 23 Nov 2016 18:58:57 +0100 Subject: [PATCH 73/97] AppVeyor: Added '--format' option to suppress DEPRECADED warning. --- .appveyor.yml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/.appveyor.yml b/.appveyor.yml index 5e7fc551..4f649c90 100644 --- a/.appveyor.yml +++ b/.appveyor.yml @@ -4,7 +4,6 @@ init: # Checking that DEP is enabled - ps: Write-Host "Initializing virtual machine ..." - ps: git --version - - ps: dir c:\ - ps: $env:Path = $env:Path.Replace("Python27", "Python35-x64") install: @@ -12,7 +11,7 @@ install: - ps: python --version - ps: python -m pip install pip --upgrade - ps: python -m pip install -r .\requirements.txt - - ps: python -m pip list + - ps: python -m pip list --format=columns - ps: Write-Host "Configuring PoC..." - ps: cp .\tools\AppVeyor\config.private.ini .\py\ - ps: cp .\tools\AppVeyor\my_project.vhdl .\tb\common\ From d0ed7c8c853ed17d2b36efb5504029e86e208706 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 23 Nov 2016 19:25:40 +0100 Subject: [PATCH 74/97] Added AppVeyor shield. --- README.md | 1 + README.tpl | 1 + docs/ChangeLog/2016/v1.x.rst | 50 ++++++++++++++++++------------ docs/_templates/autoapi/module.rst | 5 --- docs/index.rst | 5 ++- 5 files changed, 36 insertions(+), 26 deletions(-) diff --git a/README.md b/README.md index 2ef66b28..97a4631e 100644 --- a/README.md +++ b/README.md @@ -3,6 +3,7 @@ [![Python Infrastructure tested by Landscape.io](https://landscape.io/github/VLSI-EDA/PoC/release/landscape.svg?style=flat)](https://landscape.io/github/VLSI-EDA/PoC/release) [![Build Status by Travis-CI](https://travis-ci.org/VLSI-EDA/PoC.svg?branch=release)](https://travis-ci.org/VLSI-EDA/PoC/branches) +[![Build status by AppVeyor](https://ci.appveyor.com/api/projects/status/r5dtv6amsppigpsp/branch/release?svg=true)](https://ci.appveyor.com/project/Paebbels/poc/branch/release) [![Documentation Status](https://readthedocs.org/projects/poc-library/badge/?version=latest)](http://poc-library.readthedocs.io/en/latest/?badge=latest) [![Join the chat at https://gitter.im/VLSI-EDA/PoC](https://badges.gitter.im/VLSI-EDA/PoC.svg)](https://gitter.im/VLSI-EDA/PoC) ![Latest tag](https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat) diff --git a/README.tpl b/README.tpl index c68ec27a..56dcb74a 100644 --- a/README.tpl +++ b/README.tpl @@ -3,6 +3,7 @@ [![Python Infrastructure tested by Landscape.io](https://landscape.io/github/VLSI-EDA/PoC/{@BRANCH@}/landscape.svg?style=flat)](https://landscape.io/github/VLSI-EDA/PoC/{@BRANCH@}) [![Build Status by Travis-CI](https://travis-ci.org/VLSI-EDA/PoC.svg?branch={@BRANCH@})](https://travis-ci.org/VLSI-EDA/PoC/branches) +[![Build status by AppVeyor](https://ci.appveyor.com/api/projects/status/r5dtv6amsppigpsp/branch/release?svg=true)](https://ci.appveyor.com/project/Paebbels/poc/branch/release) [![Documentation Status](https://readthedocs.org/projects/poc-library/badge/?version=latest)](http://poc-library.readthedocs.io/en/latest/?badge=latest) [![Join the chat at https://gitter.im/VLSI-EDA/PoC](https://badges.gitter.im/VLSI-EDA/PoC.svg)](https://gitter.im/VLSI-EDA/PoC) ![Latest tag](https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat) diff --git a/docs/ChangeLog/2016/v1.x.rst b/docs/ChangeLog/2016/v1.x.rst index 4a1332a2..f690763d 100644 --- a/docs/ChangeLog/2016/v1.x.rst +++ b/docs/ChangeLog/2016/v1.x.rst @@ -5,23 +5,6 @@ New in 1.x (upcoming) Already documented changes are available on the ``release`` branch at GitHub. -* Python Infrastructure - - * Common changes - * All Simulators - * Aldec Active-HDL - * GHDL - * Mentor QuestaSim - * Xilinx ISE Simulator - * Xilinx Vivado Simulator - * All Compilers - * Altera Quartus Synthesis - * Lattice Diamond (LSE) - * Xilinx ISE (XST) - * Xilinx ISE Core Generator - * Xilinx Vivado Synthesis - -* Documentation * VHDL common packages * VHDL Simulation helpers @@ -51,9 +34,36 @@ Already documented changes are available on the ``release`` branch at GitHub. * Updated Testbenches - * Testbench for :ref:`IP:ocram_sdp` - * Testbench for :ref:`IP:ocram_esdp` - * Testbench for :ref:`IP:ocram_tdp` + * Testbench for :ref:`IP:ocram_sdp` + * Testbench for :ref:`IP:ocram_esdp` + * Testbench for :ref:`IP:ocram_tdp` + * Testbench for :ref:`IP:sortnet_BitonicSort` + * Testbench for :ref:`IP:sortnet_OddEvenSort` + * Testbench for :ref:`IP:sortnet_OddEvenMergeSort` * New Constraints +* Updated Constraints * Shipped Tool and Helper Scripts +* Python Infrastructure + + * Common changes + * All Simulators + * Aldec Active-HDL + * GHDL + * Mentor QuestaSim + * Xilinx ISE Simulator + * Xilinx Vivado Simulator + * All Compilers + * Altera Quartus Synthesis + * Lattice Diamond (LSE) + * Xilinx ISE (XST) + * Xilinx ISE Core Generator + * Xilinx Vivado Synthesis + +* Continuous Integration + + * Implemented a simple Python infrastructe test on AppVeyor + +* Documentation + + * Improved PDF rendering diff --git a/docs/_templates/autoapi/module.rst b/docs/_templates/autoapi/module.rst index f4d129f4..b54b2cbc 100644 --- a/docs/_templates/autoapi/module.rst +++ b/docs/_templates/autoapi/module.rst @@ -3,7 +3,6 @@ =={{ '=' * node.name|length }}== .. automodule:: {{ node.name }} - :noindex: {##} {%- block modules -%} @@ -75,7 +74,6 @@ {%- if node.variables %} {% for item, obj in node.variables.items() %} .. autodata:: {{ item }} - :noindex: :annotation: .. code-block:: guess @@ -95,7 +93,6 @@ {% for item in node.exceptions %} .. autoexception:: {{ item }} :members: - :noindex: :private-members: :inherited-members: :undoc-members: @@ -118,7 +115,6 @@ {% for item in node.classes %} .. autoclass:: {{ item }} :members: - :noindex: :private-members: :undoc-members: :inherited-members: @@ -142,7 +138,6 @@ {% for item in node.functions %} .. autofunction:: {{ item }} - :noindex: {##} {%- endfor -%} {%- endif -%} diff --git a/docs/index.rst b/docs/index.rst index ebaf168c..3939315a 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -32,7 +32,10 @@ Germany |br| :alt: Code Health .. image:: https://travis-ci.org/VLSI-EDA/PoC.svg?branch=release :target: https://travis-ci.org/VLSI-EDA/PoC - :alt: Build Results + :alt: Build status by Travis-CI + .. image:: https://ci.appveyor.com/api/projects/status/r5dtv6amsppigpsp/branch/release?svg=true + :target: https://ci.appveyor.com/project/Paebbels/poc/branch/release + :alt: Build status by AppVeyor .. image:: https://badges.gitter.im/VLSI-EDA/PoC.svg :target: https://gitter.im/VLSI-EDA/PoC :alt: Join From 7117fb53a6d7fe3480d91d11756a5d71c0b47a14 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 23 Nov 2016 20:17:35 +0100 Subject: [PATCH 75/97] Minor documentation changes. --- docs/ChangeLog/2015/index.rst | 67 ++++++++++++++++++++++++---------- docs/ChangeLog/2016/index.rst | 31 ++++++++++++---- docs/ChangeLog/index.rst | 19 ++++++++-- docs/ChangeLog/template.rst | 16 +++++--- docs/ConstraintFiles/index.rst | 56 +++++++++++++++------------- docs/ToolChains/index.rst | 34 +++++++++++++++++ docs/index.rst | 1 + py/Base/Exceptions.py | 4 ++ 8 files changed, 165 insertions(+), 63 deletions(-) create mode 100644 docs/ToolChains/index.rst diff --git a/docs/ChangeLog/2015/index.rst b/docs/ChangeLog/2015/index.rst index ebe12029..22bcfb5f 100644 --- a/docs/ChangeLog/2015/index.rst +++ b/docs/ChangeLog/2015/index.rst @@ -6,23 +6,50 @@ .. contents:: Content of this page :local: -.. toctree:: - - v0.18.0 - v0.17.0 - v0.16.0 - v0.15.0 - v0.14.0 - v0.13.0 - v0.12.0 - v0.11.0 - v0.10.0 - v0.9.0 - v0.8.0 - v0.7.0 - v0.6.0 - v0.5.0 - v0.4.0 - v0.3.0 - v0.2.0 - v0.1.0 +.. only:: html + + .. toctree:: + + v0.18.0 + v0.17.0 + v0.16.0 + v0.15.0 + v0.14.0 + v0.13.0 + v0.12.0 + v0.11.0 + v0.10.0 + v0.9.0 + v0.8.0 + v0.7.0 + v0.6.0 + v0.5.0 + v0.4.0 + v0.3.0 + v0.2.0 + v0.1.0 + + + +.. only:: latex + + .. toctree:: + + v0.1.0 + v0.2.0 + v0.3.0 + v0.4.0 + v0.5.0 + v0.6.0 + v0.7.0 + v0.8.0 + v0.9.0 + v0.10.0 + v0.11.0 + v0.12.0 + v0.13.0 + v0.14.0 + v0.15.0 + v0.16.0 + v0.17.0 + v0.18.0 diff --git a/docs/ChangeLog/2016/index.rst b/docs/ChangeLog/2016/index.rst index cd534773..7ce94019 100644 --- a/docs/ChangeLog/2016/index.rst +++ b/docs/ChangeLog/2016/index.rst @@ -6,13 +6,28 @@ .. contents:: Content of this page :local: +.. only:: html -.. toctree:: + .. toctree:: - v1.x - v1.1.0 - v1.0.1 - v1.0.0 - v0.21.0 - v0.20.0 - v0.19.0 + v1.x + v1.1.0 + v1.0.1 + v1.0.0 + v0.21.0 + v0.20.0 + v0.19.0 + + + +.. only:: latex + + .. toctree:: + + v0.19.0 + v0.20.0 + v0.21.0 + v1.0.0 + v1.0.1 + v1.1.0 + v1.x diff --git a/docs/ChangeLog/index.rst b/docs/ChangeLog/index.rst index 89ae8038..f4854538 100644 --- a/docs/ChangeLog/index.rst +++ b/docs/ChangeLog/index.rst @@ -3,11 +3,22 @@ Change Log ########## +.. only:: html -.. toctree:: + .. toctree:: - 2016/index - 2015/index - 2014/index + 2016/index + 2015/index + 2014/index + + + +.. only:: latex + + .. toctree:: + + 2014/index + 2015/index + 2016/index .. # 2017/index diff --git a/docs/ChangeLog/template.rst b/docs/ChangeLog/template.rst index 2a68e93b..9980438c 100644 --- a/docs/ChangeLog/template.rst +++ b/docs/ChangeLog/template.rst @@ -7,6 +7,15 @@ New in 1.x (upcomming) Already documented changes are available on the ``release`` branch at GitHub. +* VHDL common packages +* VHDL Simulation helpers +* New Entities +* Updated Entities +* New Testbenches +* Updated Testbenches +* New Constraints +* Updated Constraints +* Shipped Tool and Helper Scripts * Python Infrastructure * Common changes @@ -23,10 +32,5 @@ Already documented changes are available on the ``release`` branch at GitHub. * Xilinx ISE Core Generator * Xilinx Vivado Synthesis +* Continuous Integration * Documentation -* VHDL common packages -* VHDL Simulation helpers -* New Entities -* New Testbenches -* New Constraints -* Shipped Tool and Helper Scripts diff --git a/docs/ConstraintFiles/index.rst b/docs/ConstraintFiles/index.rst index 9a2e28b1..b593e029 100644 --- a/docs/ConstraintFiles/index.rst +++ b/docs/ConstraintFiles/index.rst @@ -6,43 +6,49 @@ Constraint Files IP Core Constraint Files ************************ - * fifo - * misc - * sync - * net - * eth +* fifo +* misc + + * sync + +* net + + * eth .. toctree:: :hidden: - fifo/index - misc/index - net/index + fifo + misc + net Board Constraint Files ********************** - * Altera Boards - * Cyclone III - * Stratix IV - * Stratix V - * Lattice Boards - * Xilinx Boards - * Spartan-3 Boards - * Spartan-6 Boards - * Artix-7 - * Kintex-7 - * Virtex-5 - * Virtex-6 - * Virtex-7 - * Zynq-7000 +* Altera Boards + + * Cyclone III + * Stratix IV + * Stratix V + +* Lattice Boards +* Xilinx Boards + + * Artix-7 + * Kintex-7 + * Spartan-3 Boards + * Spartan-6 Boards + * Virtex-5 + * Virtex-6 + * Virtex-7 + * Zynq-7000 .. toctree:: :hidden: - Altera/index - Lattice/index - Xilinx/index + Altera + Lattice + Xilinx diff --git a/docs/ToolChains/index.rst b/docs/ToolChains/index.rst new file mode 100644 index 00000000..c90fb085 --- /dev/null +++ b/docs/ToolChains/index.rst @@ -0,0 +1,34 @@ +.. _CHAIN: + +Tool Chain Specifics +#################### + +.. attention:: + + This page is under construction. + + +Aldec Active-HDL +================ + +.. todo:: + + * No GUI mode supported + * VHDL-2008 parser bug in Active-HDL 10.3 + + +Mentor QuestaSim +================ + +Special feature: embedded poc prodecures to recompile relaunch, rerun and save waveforms... + +Xilinx ISE +========== + +* Describe the ``use_new_parser yes`` option + +Xilinx Vivado +============= + +* Describe the ``vivado`` branch (Git). + diff --git a/docs/index.rst b/docs/index.rst index 3939315a..94200015 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -143,6 +143,7 @@ following `biblatex `_ entry to cite us: IPCores/index Miscelaneous/ThirdParty ConstraintFiles/index + ToolChains/index .. raw:: latex diff --git a/py/Base/Exceptions.py b/py/Base/Exceptions.py index 623371f4..f3fc16e7 100644 --- a/py/Base/Exceptions.py +++ b/py/Base/Exceptions.py @@ -65,6 +65,10 @@ def __str__(self): """Returns the exception's message text.""" return self.message + @DocumentMemberAttribute(False) + def with_traceback(self, tb): + super().with_traceback(tb) + # @DocumentMemberAttribute(False) # @MethodAlias(Exception.with_traceback) # def with_traceback(self): pass From d8304bd22f12277160b2e9fb2e4a9ea1a706b1d8 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 23 Nov 2016 21:50:23 +0100 Subject: [PATCH 76/97] Fixed inheritance in ExecutableException. --- docs/Examples/index.rst | 10 +++++++ docs/GetInvolved/index.rst | 59 ++++++++++++++++++++------------------ docs/index.rst | 1 + py/Base/Executable.py | 14 +++++---- 4 files changed, 50 insertions(+), 34 deletions(-) create mode 100644 docs/Examples/index.rst diff --git a/docs/Examples/index.rst b/docs/Examples/index.rst new file mode 100644 index 00000000..eef3b790 --- /dev/null +++ b/docs/Examples/index.rst @@ -0,0 +1,10 @@ +.. _EX: + +Examples +######## + +.. note:: + + Under construction. + +PoC-Exmaples repository on GitHub. diff --git a/docs/GetInvolved/index.rst b/docs/GetInvolved/index.rst index ca4d7589..a1986e8c 100644 --- a/docs/GetInvolved/index.rst +++ b/docs/GetInvolved/index.rst @@ -3,12 +3,12 @@ Get Involved ############ A first step might be to use and explore PoC and it's infrastructure in an own -project. Moreover, we encurage to read our `online help `_ -which covers all aspects from quickstart example up to detailed IP core -documentation. While using PoC, you might discover issues or missing feature. -Please report them as `listed below <#report-a-bug>`_. If you have an -interresting project, please send us feedback or get listed on our -:doc:`Who uses PoC? ` +project. Moreover, we encurage to read our online help which covers all aspects +from quickstart example up to detailed IP core documentation. While using PoC, +you might discover issues or missing feature. Please report them as +`listed below <#report-a-bug>`_. If you have an interresting project, please +send us feedback or get listed on our :doc:`Who uses PoC? ` +page. If you are more familiar with PoC and it's components, you might start asking youself how components internally work. Please read our more advanced topics in @@ -35,7 +35,7 @@ Report a Bug Please report issues of any kind in our Git provider's issue tracker. This allows us to categorize issues into groups and assign developers to them. You can track -the issue's state and see how it's getting closed. All enhancements and feature +the issue's state and see how it's getting solved. All enhancements and feature requests are tracked on GitHub at `GitHub Issues `_. @@ -58,7 +58,7 @@ Talk to us on Gitter You can chat with us on `Gitter `_ in our Giiter Room `VLSI-EDA/PoC `_. You can use Gitter for free -with your GitHub account. +with your existing GitHub or Twitter account. Contributers License Agreement @@ -66,13 +66,13 @@ Contributers License Agreement We require all contributers to sign a Contributor License Agreement (CLA). If you don't know whatfore a CLA is needed and how it prevents legal issues on both -sides, read `this short blog `_ post.PoC +sides, read `this short blog `_ post. PoC uses the :doc:`Apache Contributor License Agreement ` to match the :doc:`Apache License 2.0 `. So to get started, `sign the Contributor License Agreement (CLA) `_ -at `CLAHub.com `_. You can can login with your GitHub -account. +at `CLAHub.com `_. You can authenticate yourself with +an existing GitHub account. Contribute to PoC @@ -82,21 +82,23 @@ Contribute to PoC Contibuting source code via Git is very easy. We don't provide direct write access to our repositories. Git offers the fork and pull-request philosophy, -which means: You clone a repository, provide you changes in your own repository -and notify us about outstanding changes via pull-requests. +which means: You clone a repository, provide your changes in your own repository +and notify us about outstanding changes via a pull-requests. We will then review +your proposed changes and integrate them into our repository. -The steps 1 to 5 are done only once for setting up a forked repository. +*Steps 1 to 5 are done only once for setting up a forked repository.* -1. Fork our Repository -====================== +1. Fork the PoC Repository +========================== .. image:: https://img.shields.io/github/forks/VLSI-EDA/PoC.svg :target: https://github.com/VLSI-EDA/PoC/network/members Git repositories can be cloned on a Git provider's server. This procedure is -called *forking*. This allows Git providers to track the repositories network -and if repositories are related to each other and if pull-requests are possible. +called *forking*. This allows Git providers to track the repository's network, +check if repositories are related to each other and notify if pull-requests are +available. Fork our repository ``VLSI-EDA/PoC`` on GitHub into your or your's Git organisation's account. In the following the forked repository is referenced as @@ -105,7 +107,7 @@ organisation's account. In the following the forked repository is referenced as 2. Clone the new Fork ===================== -Clone this new fork to your machine. See :doc:`Downloading via git clone ` +Clone this new fork to your machine. See :ref:`Downloading via Git clone ` for more details on how to clone PoC. If you have already cloned PoC, then you can setup the new fork as an additional *remote*. You should set ``VLSI-EDA/PoC`` as fetch target and the new fork ``/PoC`` as push target. @@ -140,19 +142,18 @@ Checkout the ``master`` or ``release`` branch and maybe stash outstanding change .. code-block:: PowerShell cd PoCRoot - git checkout master + git checkout release 4. Setup PoC for Developers =========================== -Run PoC's :doc:`configuration routines ` and setup -the developer tools. You can skip (:kbd:`P`) all tool chain questions until you -reach the Git questions. +Run PoC's :ref:`configuration routines ` and setup the +developer tools. .. code-block:: PowerShell cd PoCRoot - .\PoC.ps1 configure + .\PoC.ps1 configure git 5. Create your own ``master`` Branch ==================================== @@ -177,11 +178,11 @@ branch names: +-----------------+--------------------------------------+ | Branch name | Description | +=================+======================================+ -| bugfix-utils | Fixes a bug in ``utils.vhdl`` | +| bugfix-utils | Fixes a bug in ``utils.vhdl``. | +-----------------+--------------------------------------+ -| docs-spelling | Fixes the documentation | +| docs-spelling | Fixes the documentation. | +-----------------+--------------------------------------+ -| spi-controller | A new SPI controller implementation | +| spi-controller | A new SPI controller implementation. | +-----------------+--------------------------------------+ @@ -194,7 +195,8 @@ branch names: 7. Commit and Push Changes ========================== -Commit your porposed changes to your feature branch and push all changes to GitHub. + +Commit your porposed changes onto your feature branch and push all changes to GitHub. .. code-block:: PowerShell @@ -246,6 +248,7 @@ Voß, Jens jens.voss@mailbox.tu-dresden.de Zabel, Martin [#f2]_ martin.zabel@tu-dresden.de ========================= ============================================================ +-------------------------------------------------------------------------------- .. rubric:: Footnotes diff --git a/docs/index.rst b/docs/index.rst index 94200015..46b3cf0d 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -144,6 +144,7 @@ following `biblatex `_ entry to cite us: Miscelaneous/ThirdParty ConstraintFiles/index ToolChains/index + Examples/index .. raw:: latex diff --git a/py/Base/Executable.py b/py/Base/Executable.py index 7311aa70..c7a4a289 100644 --- a/py/Base/Executable.py +++ b/py/Base/Executable.py @@ -33,12 +33,12 @@ # # load dependencies from pathlib import Path -from subprocess import Popen as Subprocess_Popen -from subprocess import PIPE as Subprocess_Pipe -from subprocess import STDOUT as Subprocess_StdOut +from subprocess import Popen as Subprocess_Popen +from subprocess import PIPE as Subprocess_Pipe +from subprocess import STDOUT as Subprocess_StdOut -from Base.Exceptions import CommonException -from Base.Logging import ILogable +from Base.Exceptions import CommonException, ExceptionBase +from Base.Logging import ILogable __api__ = [ @@ -60,11 +60,12 @@ __all__ = __api__ -class ExecutableException(BaseException): +class ExecutableException(ExceptionBase): def __init__(self, message=""): super().__init__(message) self.message = message + class CommandLineArgument(type): _value = None @@ -72,6 +73,7 @@ class CommandLineArgument(type): # print("CommandLineArgument.new: %s - %s" % (name, nmspc)) # return super(CommandLineArgument, mcls).__new__(mcls, name, bases, nmspc) + class ExecutableArgument(CommandLineArgument): @property def Value(self): From 1bbf3814ceb92ae82259dba2724942b219266b15 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 24 Nov 2016 00:57:45 +0100 Subject: [PATCH 77/97] Updated Sphinx to 1.4.9. Changed IP core name to EntityFullName. Added more wavedrom waveforms. --- docs/IPCores/arith/arith_addw.rst | 11 ++-- docs/IPCores/arith/arith_bcdcollect.rst | 11 ++-- docs/IPCores/arith/arith_carrychain_inc.rst | 11 ++-- docs/IPCores/arith/arith_convert_bin2bcd.rst | 11 ++-- docs/IPCores/arith/arith_counter_bcd.rst | 11 ++-- docs/IPCores/arith/arith_counter_free.rst | 11 ++-- docs/IPCores/arith/arith_counter_gray.rst | 11 ++-- docs/IPCores/arith/arith_counter_ring.rst | 11 ++-- docs/IPCores/arith/arith_div.rst | 11 ++-- docs/IPCores/arith/arith_firstone.rst | 11 ++-- docs/IPCores/arith/arith_muls_wide.rst | 11 ++-- docs/IPCores/arith/arith_prefix_and.rst | 11 ++-- docs/IPCores/arith/arith_prefix_or.rst | 11 ++-- docs/IPCores/arith/arith_prng.rst | 11 ++-- docs/IPCores/arith/arith_same.rst | 11 ++-- docs/IPCores/arith/arith_scaler.rst | 11 ++-- docs/IPCores/arith/arith_shifter_barrel.rst | 11 ++-- docs/IPCores/arith/arith_sqrt.rst | 11 ++-- docs/IPCores/bus/bus_Arbiter.rst | 11 ++-- docs/IPCores/bus/stream/stream_Buffer.rst | 11 ++-- docs/IPCores/bus/stream/stream_DeMux.rst | 11 ++-- .../bus/stream/stream_FrameGenerator.rst | 11 ++-- docs/IPCores/bus/stream/stream_Mirror.rst | 11 ++-- docs/IPCores/bus/stream/stream_Mux.rst | 11 ++-- docs/IPCores/bus/stream/stream_Sink.rst | 11 ++-- docs/IPCores/bus/stream/stream_Source.rst | 11 ++-- docs/IPCores/bus/wb/wb_fifo_adapter.rst | 11 ++-- docs/IPCores/bus/wb/wb_ocram.rst | 11 ++-- docs/IPCores/bus/wb/wb_uart_wrapper.rst | 11 ++-- docs/IPCores/cache/cache_cpu.rst | 11 ++-- docs/IPCores/cache/cache_mem.rst | 11 ++-- docs/IPCores/cache/cache_par.rst | 11 ++-- docs/IPCores/cache/cache_par2.rst | 11 ++-- .../cache/cache_replacement_policy.rst | 11 ++-- docs/IPCores/cache/cache_tagunit_par.rst | 11 ++-- docs/IPCores/cache/cache_tagunit_seq.rst | 11 ++-- docs/IPCores/comm/comm_crc.rst | 11 ++-- docs/IPCores/comm/comm_scramble.rst | 11 ++-- docs/IPCores/fifo/fifo_cc_got.rst | 11 ++-- docs/IPCores/fifo/fifo_cc_got_tempgot.rst | 11 ++-- docs/IPCores/fifo/fifo_cc_got_tempput.rst | 11 ++-- docs/IPCores/fifo/fifo_dc_got_sm.rst | 11 ++-- docs/IPCores/fifo/fifo_glue.rst | 11 ++-- docs/IPCores/fifo/fifo_ic_assembly.rst | 11 ++-- docs/IPCores/fifo/fifo_ic_got.rst | 11 ++-- docs/IPCores/fifo/fifo_shift.rst | 11 ++-- docs/IPCores/io/ddrio/ddrio_in.rst | 41 ++++++--------- docs/IPCores/io/ddrio/ddrio_inout.rst | 50 +++++++++++++------ docs/IPCores/io/ddrio/ddrio_out.rst | 35 ++++++++++--- docs/IPCores/io/iic/iic_BusController.rst | 11 ++-- docs/IPCores/io/iic/iic_Controller.rst | 11 ++-- .../IPCores/io/iic/iic_Controller_SFF8431.rst | 11 ++-- docs/IPCores/io/iic/iic_Switch_PCA9548A.rst | 11 ++-- docs/IPCores/io/io_7SegmentMux_BCD.rst | 11 ++-- docs/IPCores/io/io_7SegmentMux_HEX.rst | 11 ++-- docs/IPCores/io/io_Debounce.rst | 11 ++-- docs/IPCores/io/io_FanControl.rst | 11 ++-- docs/IPCores/io/io_FrequencyCounter.rst | 11 ++-- docs/IPCores/io/io_GlitchFilter.rst | 11 ++-- docs/IPCores/io/io_KeyPadScanner.rst | 11 ++-- docs/IPCores/io/io_PulseWidthModulation.rst | 11 ++-- docs/IPCores/io/io_TimingCounter.rst | 11 ++-- docs/IPCores/io/lcd/lcd_LCDBuffer.rst | 11 ++-- docs/IPCores/io/lcd/lcd_LCDBusController.rst | 11 ++-- .../io/lcd/lcd_LCDController_KS0066U.rst | 11 ++-- docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst | 11 ++-- docs/IPCores/io/lcd/lcd_dotmatrix.rst | 11 ++-- docs/IPCores/io/mdio/mdio_Controller.rst | 11 ++-- docs/IPCores/io/mdio/mdio_IIC_Adapter.rst | 11 ++-- docs/IPCores/io/pio/pio_fifo_in.rst | 11 ++-- docs/IPCores/io/pio/pio_fifo_out.rst | 11 ++-- docs/IPCores/io/pio/pio_in.rst | 11 ++-- docs/IPCores/io/pio/pio_out.rst | 11 ++-- docs/IPCores/io/pmod/pmod_KYPD.rst | 11 ++-- docs/IPCores/io/pmod/pmod_SSD.rst | 11 ++-- docs/IPCores/io/pmod/pmod_USBUART.rst | 11 ++-- docs/IPCores/io/uart/uart_bclk.rst | 11 ++-- docs/IPCores/io/uart/uart_fifo.rst | 11 ++-- docs/IPCores/io/uart/uart_ft245.rst | 11 ++-- docs/IPCores/io/uart/uart_rx.rst | 11 ++-- docs/IPCores/io/uart/uart_tx.rst | 11 ++-- docs/IPCores/io/vga/vga_phy.rst | 11 ++-- docs/IPCores/io/vga/vga_phy_ch7301c.rst | 11 ++-- docs/IPCores/io/vga/vga_timing.rst | 11 ++-- .../ddr2/ddr2_mem2mig_adapter_Spartan6.rst | 11 ++-- .../mem/ddr3/ddr3_mem2mig_adapter_Series7.rst | 11 ++-- docs/IPCores/mem/lut/lut_Sine.rst | 11 ++-- docs/IPCores/mem/ocram/ocram_esdp.rst | 11 ++-- docs/IPCores/mem/ocram/ocram_sdp.rst | 11 ++-- docs/IPCores/mem/ocram/ocram_sdp_wf.rst | 11 ++-- docs/IPCores/mem/ocram/ocram_sp.rst | 11 ++-- docs/IPCores/mem/ocram/ocram_tdp.rst | 11 ++-- docs/IPCores/mem/ocram/ocram_tdp_sim.rst | 11 ++-- docs/IPCores/mem/ocram/ocram_tdp_wf.rst | 11 ++-- docs/IPCores/mem/ocrom/ocrom_dp.rst | 11 ++-- docs/IPCores/mem/ocrom/ocrom_sp.rst | 11 ++-- docs/IPCores/mem/sdram/sdram_ctrl_de0.rst | 11 ++-- docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst | 11 ++-- docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst | 11 ++-- .../mem/sdram/sdram_ctrl_phy_s3esk.rst | 11 ++-- docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst | 11 ++-- docs/IPCores/misc/filter/filter_and.rst | 11 ++-- docs/IPCores/misc/filter/filter_mean.rst | 11 ++-- docs/IPCores/misc/filter/filter_or.rst | 11 ++-- docs/IPCores/misc/gearbox/gearbox_down_cc.rst | 11 ++-- docs/IPCores/misc/gearbox/gearbox_down_dc.rst | 11 ++-- docs/IPCores/misc/gearbox/gearbox_up_cc.rst | 11 ++-- docs/IPCores/misc/gearbox/gearbox_up_dc.rst | 11 ++-- docs/IPCores/misc/misc_BitwidthConverter.rst | 11 ++-- docs/IPCores/misc/misc_ByteAligner.rst | 11 ++-- docs/IPCores/misc/misc_Delay.rst | 11 ++-- .../misc/misc_FrequencyMeasurement.rst | 11 ++-- docs/IPCores/misc/misc_PulseTrain.rst | 11 ++-- docs/IPCores/misc/misc_Sequencer.rst | 11 ++-- docs/IPCores/misc/misc_StrobeGenerator.rst | 11 ++-- docs/IPCores/misc/misc_StrobeLimiter.rst | 11 ++-- docs/IPCores/misc/misc_bit_lz.rst | 11 ++-- docs/IPCores/misc/stat/stat_Average.rst | 11 ++-- docs/IPCores/misc/stat/stat_Histogram.rst | 11 ++-- docs/IPCores/misc/stat/stat_Maximum.rst | 11 ++-- docs/IPCores/misc/stat/stat_Minimum.rst | 11 ++-- docs/IPCores/misc/sync/sync_Bits.rst | 11 ++-- docs/IPCores/misc/sync/sync_Command.rst | 11 ++-- docs/IPCores/misc/sync/sync_Pulse.rst | 11 ++-- docs/IPCores/misc/sync/sync_Reset.rst | 11 ++-- docs/IPCores/misc/sync/sync_Strobe.rst | 11 ++-- docs/IPCores/misc/sync/sync_Vector.rst | 11 ++-- .../net/arp/arp_BroadCast_Receiver.rst | 11 ++-- .../net/arp/arp_BroadCast_Requester.rst | 11 ++-- docs/IPCores/net/arp/arp_Cache.rst | 11 ++-- docs/IPCores/net/arp/arp_IPPool.rst | 11 ++-- docs/IPCores/net/arp/arp_Tester.rst | 11 ++-- docs/IPCores/net/arp/arp_UniCast_Receiver.rst | 11 ++-- .../IPCores/net/arp/arp_UniCast_Responder.rst | 11 ++-- docs/IPCores/net/arp/arp_Wrapper.rst | 11 ++-- docs/IPCores/net/eth/eth_GEMAC_GMII.rst | 11 ++-- docs/IPCores/net/eth/eth_GEMAC_RX.rst | 11 ++-- docs/IPCores/net/eth/eth_GEMAC_TX.rst | 11 ++-- docs/IPCores/net/eth/eth_PHYController.rst | 11 ++-- .../eth/eth_PHYController_Marvell_88E1111.rst | 11 ++-- docs/IPCores/net/eth/eth_Wrapper.rst | 11 ++-- docs/IPCores/net/icmpv4/icmpv4_RX.rst | 11 ++-- docs/IPCores/net/icmpv4/icmpv4_TX.rst | 11 ++-- docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst | 11 ++-- docs/IPCores/net/icmpv6/icmpv6_RX.rst | 11 ++-- docs/IPCores/net/icmpv6/icmpv6_TX.rst | 11 ++-- docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst | 11 ++-- docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst | 11 ++-- docs/IPCores/net/ipv4/ipv4_RX.rst | 11 ++-- docs/IPCores/net/ipv4/ipv4_TX.rst | 11 ++-- docs/IPCores/net/ipv4/ipv4_Wrapper.rst | 11 ++-- docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst | 11 ++-- docs/IPCores/net/ipv6/ipv6_RX.rst | 11 ++-- docs/IPCores/net/ipv6/ipv6_TX.rst | 11 ++-- docs/IPCores/net/ipv6/ipv6_Wrapper.rst | 11 ++-- docs/IPCores/net/mac/mac_FrameLoopback.rst | 11 ++-- .../IPCores/net/mac/mac_RX_DestMAC_Switch.rst | 11 ++-- docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst | 11 ++-- docs/IPCores/net/mac/mac_RX_Type_Switch.rst | 11 ++-- .../net/mac/mac_TX_DestMAC_Prepender.rst | 11 ++-- .../net/mac/mac_TX_SrcMAC_Prepender.rst | 11 ++-- .../IPCores/net/mac/mac_TX_Type_Prepender.rst | 11 ++-- docs/IPCores/net/mac/mac_Wrapper.rst | 11 ++-- docs/IPCores/net/ndp/ndp_DestinationCache.rst | 11 ++-- docs/IPCores/net/ndp/ndp_FSMQuery.rst | 11 ++-- docs/IPCores/net/ndp/ndp_NeighborCache.rst | 11 ++-- docs/IPCores/net/ndp/ndp_Wrapper.rst | 11 ++-- docs/IPCores/net/net_FrameChecksum.rst | 11 ++-- docs/IPCores/net/net_FrameLoopback.rst | 11 ++-- .../net/net_FramePerformanceCounter.rst | 11 ++-- docs/IPCores/net/stack/stack_UDPv4.rst | 11 ++-- docs/IPCores/net/udp/udp_FrameLoopback.rst | 11 ++-- docs/IPCores/net/udp/udp_RX.rst | 11 ++-- docs/IPCores/net/udp/udp_TX.rst | 11 ++-- docs/IPCores/net/udp/udp_Wrapper.rst | 11 ++-- docs/IPCores/sort/sort_ExpireList.rst | 11 ++-- docs/IPCores/sort/sort_InsertSort.rst | 11 ++-- .../IPCores/sort/sort_LeastFrequentlyUsed.rst | 11 ++-- docs/IPCores/sort/sort_lru_cache.rst | 11 ++-- docs/IPCores/sort/sort_lru_list.rst | 11 ++-- .../sort/sortnet/sortnet_BitonicSort.rst | 11 ++-- .../sortnet/sortnet_MergeSort_Streamed.rst | 11 ++-- .../sort/sortnet/sortnet_OddEvenMergeSort.rst | 11 ++-- .../sort/sortnet/sortnet_OddEvenSort.rst | 11 ++-- .../sort/sortnet/sortnet_Stream_Adapter.rst | 11 ++-- .../sort/sortnet/sortnet_Stream_Adapter2.rst | 11 ++-- .../sort/sortnet/sortnet_Transform.rst | 11 ++-- .../xil/reconfig/reconfig_icap_fsm.rst | 11 ++-- .../xil/reconfig/reconfig_icap_wrapper.rst | 11 ++-- docs/IPCores/xil/xil_BSCAN.rst | 11 ++-- docs/IPCores/xil/xil_ChipScopeICON.rst | 11 ++-- docs/IPCores/xil/xil_DRP_BusMux.rst | 11 ++-- docs/IPCores/xil/xil_DRP_BusSync.rst | 11 ++-- docs/IPCores/xil/xil_ICAP.rst | 11 ++-- docs/IPCores/xil/xil_Reconfigurator.rst | 11 ++-- docs/IPCores/xil/xil_SystemMonitor.rst | 11 ++-- .../IPCores/xil/xil_SystemMonitor_Series7.rst | 11 ++-- .../IPCores/xil/xil_SystemMonitor_Virtex6.rst | 11 ++-- docs/conf.py | 2 +- docs/poc.py | 15 +++--- src/io/ddrio/ddrio_in.vhdl | 28 ++++------- src/io/ddrio/ddrio_inout.vhdl | 37 ++++++++++---- src/io/ddrio/ddrio_out.vhdl | 22 ++++++++ tools/ReadTheDocs/requirements.txt | 2 +- 204 files changed, 1124 insertions(+), 1253 deletions(-) diff --git a/docs/IPCores/arith/arith_addw.rst b/docs/IPCores/arith/arith_addw.rst index 19ed4d9e..857d0123 100644 --- a/docs/IPCores/arith/arith_addw.rst +++ b/docs/IPCores/arith/arith_addw.rst @@ -1,3 +1,8 @@ +.. _IP:arith_addw: + +PoC.arith.addw +############## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arith_addw: - -arith_addw -########## - Implements wide addition providing several options all based on an adaptation of a carry-select approach. diff --git a/docs/IPCores/arith/arith_bcdcollect.rst b/docs/IPCores/arith/arith_bcdcollect.rst index 78da7eb2..9fcf9e1b 100644 --- a/docs/IPCores/arith/arith_bcdcollect.rst +++ b/docs/IPCores/arith/arith_bcdcollect.rst @@ -1,3 +1,8 @@ +.. _IP:arith_bcdcollect: + +PoC.arith.bcdcollect +#################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arith_bcdcollect: - -arith_bcdcollect -################ - .. TODO:: No documentation available. diff --git a/docs/IPCores/arith/arith_carrychain_inc.rst b/docs/IPCores/arith/arith_carrychain_inc.rst index 86014f94..19a28b35 100644 --- a/docs/IPCores/arith/arith_carrychain_inc.rst +++ b/docs/IPCores/arith/arith_carrychain_inc.rst @@ -1,3 +1,8 @@ +.. _IP:arith_carrychain_inc: + +PoC.arith.carrychain_inc +######################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arith_carrychain_inc: - -arith_carrychain_inc -#################### - This is a generic carry-chain abstraction for increment by one operations. Y <= X + (0...0) & Cin diff --git a/docs/IPCores/arith/arith_convert_bin2bcd.rst b/docs/IPCores/arith/arith_convert_bin2bcd.rst index 787ade16..4267b204 100644 --- a/docs/IPCores/arith/arith_convert_bin2bcd.rst +++ b/docs/IPCores/arith/arith_convert_bin2bcd.rst @@ -1,3 +1,8 @@ +.. _IP:arith_convert_bin2bcd: + +PoC.arith.convert_bin2bcd +######################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arith_convert_bin2bcd: - -arith_convert_bin2bcd -##################### - .. TODO:: No documentation available. diff --git a/docs/IPCores/arith/arith_counter_bcd.rst b/docs/IPCores/arith/arith_counter_bcd.rst index 8cedc60c..6e683c06 100644 --- a/docs/IPCores/arith/arith_counter_bcd.rst +++ b/docs/IPCores/arith/arith_counter_bcd.rst @@ -1,3 +1,8 @@ +.. _IP:arith_counter_bcd: + +PoC.arith.counter_bcd +##################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arith_counter_bcd: - -arith_counter_bcd -################# - Counter with output in binary coded decimal (BCD). The number of BCD digits is configurable by ``DIGITS``. diff --git a/docs/IPCores/arith/arith_counter_free.rst b/docs/IPCores/arith/arith_counter_free.rst index 03730a4d..741f2d91 100644 --- a/docs/IPCores/arith/arith_counter_free.rst +++ b/docs/IPCores/arith/arith_counter_free.rst @@ -1,3 +1,8 @@ +.. _IP:arith_counter_free: + +PoC.arith.counter_free +###################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arith_counter_free: - -arith_counter_free -################## - Implements a free-running counter that generates a strobe signal every DIVIDER-th cycle the increment input was asserted. There is deliberately no output or specification of the counter value so as to allow an implementation diff --git a/docs/IPCores/arith/arith_counter_gray.rst b/docs/IPCores/arith/arith_counter_gray.rst index ea54e441..d6ee1e68 100644 --- a/docs/IPCores/arith/arith_counter_gray.rst +++ b/docs/IPCores/arith/arith_counter_gray.rst @@ -1,3 +1,8 @@ +.. _IP:arith_counter_gray: + +PoC.arith.counter_gray +###################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arith_counter_gray: - -arith_counter_gray -################## - .. TODO:: No documentation available. diff --git a/docs/IPCores/arith/arith_counter_ring.rst b/docs/IPCores/arith/arith_counter_ring.rst index c0e25f8f..c7541bcb 100644 --- a/docs/IPCores/arith/arith_counter_ring.rst +++ b/docs/IPCores/arith/arith_counter_ring.rst @@ -1,3 +1,8 @@ +.. _IP:arith_counter_ring: + +PoC.arith.counter_ring +###################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arith_counter_ring: - -arith_counter_ring -################## - This module implements an up/down ring-counter with loadable initial value (``seed``) on reset. The counter can be configured to a Johnson counter by enabling ``INVERT_FEEDBACK``. The number of counter bits is configurable with diff --git a/docs/IPCores/arith/arith_div.rst b/docs/IPCores/arith/arith_div.rst index d1397e63..2a3ee2ad 100644 --- a/docs/IPCores/arith/arith_div.rst +++ b/docs/IPCores/arith/arith_div.rst @@ -1,3 +1,8 @@ +.. _IP:arith_div: + +PoC.arith.div +############# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arith_div: - -arith_div -######### - Implementation of a Non-Performing restoring divider with a configurable radix. The multi-cycle division is controlled by 'start' / 'rdy'. A new division is started by asserting 'start'. The result Q = A/D is available when 'rdy' diff --git a/docs/IPCores/arith/arith_firstone.rst b/docs/IPCores/arith/arith_firstone.rst index e2f984ae..10755ee9 100644 --- a/docs/IPCores/arith/arith_firstone.rst +++ b/docs/IPCores/arith/arith_firstone.rst @@ -1,3 +1,8 @@ +.. _IP:arith_firstone: + +PoC.arith.firstone +################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arith_firstone: - -arith_firstone -############## - Computes from an input word, a word of the same size that has, at most, one bit set. The output contains a set bit at the position of the rightmost set bit of the input if and only if such a set bit exists in the input. diff --git a/docs/IPCores/arith/arith_muls_wide.rst b/docs/IPCores/arith/arith_muls_wide.rst index 726f87e4..68ed6a99 100644 --- a/docs/IPCores/arith/arith_muls_wide.rst +++ b/docs/IPCores/arith/arith_muls_wide.rst @@ -1,3 +1,8 @@ +.. _IP:arith_muls_wide: + +PoC.arith.muls_wide +################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arith_muls_wide: - -arith_muls_wide -############### - Signed wide multiplication spanning multiple DSP or MULT blocks. Small partial products are calculated through LUTs. For detailed documentation see below. diff --git a/docs/IPCores/arith/arith_prefix_and.rst b/docs/IPCores/arith/arith_prefix_and.rst index e4b1fb25..df992f4a 100644 --- a/docs/IPCores/arith/arith_prefix_and.rst +++ b/docs/IPCores/arith/arith_prefix_and.rst @@ -1,3 +1,8 @@ +.. _IP:arith_prefix_and: + +PoC.arith.prefix_and +#################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arith_prefix_and: - -arith_prefix_and -################ - Prefix AND computation: ``y(i) <= '1' when x(i downto 0) = (i downto 0 => '1') else '0';`` This implementation uses carry chains for wider implementations. diff --git a/docs/IPCores/arith/arith_prefix_or.rst b/docs/IPCores/arith/arith_prefix_or.rst index cbd52b02..22ca9db2 100644 --- a/docs/IPCores/arith/arith_prefix_or.rst +++ b/docs/IPCores/arith/arith_prefix_or.rst @@ -1,3 +1,8 @@ +.. _IP:arith_prefix_or: + +PoC.arith.prefix_or +################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arith_prefix_or: - -arith_prefix_or -############### - Prefix OR computation: ``y(i) <= '0' when x(i downto 0) = (i downto 0 => '0') else '1';`` This implementation uses carry chains for wider implementations. diff --git a/docs/IPCores/arith/arith_prng.rst b/docs/IPCores/arith/arith_prng.rst index b6c8f552..935f8b80 100644 --- a/docs/IPCores/arith/arith_prng.rst +++ b/docs/IPCores/arith/arith_prng.rst @@ -1,3 +1,8 @@ +.. _IP:arith_prng: + +PoC.arith.prng +############## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arith_prng: - -arith_prng -########## - This module implementes a Pseudo-Random Number Generator (PRNG) with configurable bit count (``BITS``). This module uses an internal list of FPGA optimized polynomials from 3 to 168 bits. The polynomials have at most 5 tap diff --git a/docs/IPCores/arith/arith_same.rst b/docs/IPCores/arith/arith_same.rst index 74d5a77c..605f25df 100644 --- a/docs/IPCores/arith/arith_same.rst +++ b/docs/IPCores/arith/arith_same.rst @@ -1,3 +1,8 @@ +.. _IP:arith_same: + +PoC.arith.same +############## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arith_same: - -arith_same -########## - This circuit may, for instance, be used to detect the first sign change and, thus, the range of a two's complement number. diff --git a/docs/IPCores/arith/arith_scaler.rst b/docs/IPCores/arith/arith_scaler.rst index 3f86aab4..6ca0174f 100644 --- a/docs/IPCores/arith/arith_scaler.rst +++ b/docs/IPCores/arith/arith_scaler.rst @@ -1,3 +1,8 @@ +.. _IP:arith_scaler: + +PoC.arith.scaler +################ + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arith_scaler: - -arith_scaler -############ - A flexible scaler for fixed-point values. The scaler is implemented for a set of multiplier and divider values. Each individual scaling operation can arbitrarily select one value from each these sets. diff --git a/docs/IPCores/arith/arith_shifter_barrel.rst b/docs/IPCores/arith/arith_shifter_barrel.rst index f8cc579a..ee45718b 100644 --- a/docs/IPCores/arith/arith_shifter_barrel.rst +++ b/docs/IPCores/arith/arith_shifter_barrel.rst @@ -1,3 +1,8 @@ +.. _IP:arith_shifter_barrel: + +PoC.arith.shifter_barrel +######################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arith_shifter_barrel: - -arith_shifter_barrel -#################### - This Barrel-Shifter supports: * shifting and rotating diff --git a/docs/IPCores/arith/arith_sqrt.rst b/docs/IPCores/arith/arith_sqrt.rst index d1e46a8c..f69b40d1 100644 --- a/docs/IPCores/arith/arith_sqrt.rst +++ b/docs/IPCores/arith/arith_sqrt.rst @@ -1,3 +1,8 @@ +.. _IP:arith_sqrt: + +PoC.arith.sqrt +############## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arith_sqrt: - -arith_sqrt -########## - Iterative Square Root Extractor. Its computation requires (N+1)/2 steps for an argument bit width of N. diff --git a/docs/IPCores/bus/bus_Arbiter.rst b/docs/IPCores/bus/bus_Arbiter.rst index 9006dc37..becfeccd 100644 --- a/docs/IPCores/bus/bus_Arbiter.rst +++ b/docs/IPCores/bus/bus_Arbiter.rst @@ -1,3 +1,8 @@ +.. _IP:bus_Arbiter: + +PoC.bus.Arbiter +############### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:bus_Arbiter: - -bus_Arbiter -########### - This module implements a generic arbiter. It currently supports the following arbitration strategies: diff --git a/docs/IPCores/bus/stream/stream_Buffer.rst b/docs/IPCores/bus/stream/stream_Buffer.rst index 1f35811c..1f304032 100644 --- a/docs/IPCores/bus/stream/stream_Buffer.rst +++ b/docs/IPCores/bus/stream/stream_Buffer.rst @@ -1,3 +1,8 @@ +.. _IP:stream_Buffer: + +PoC.bus.stream.Buffer +##################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:stream_Buffer: - -stream_Buffer -############# - This module implements a generic buffer (FIFO) for the :doc:`PoC.Stream ` protocol. It is generic in ``DATA_BITS`` and in ``META_BITS`` as well as in FIFO depths for data and diff --git a/docs/IPCores/bus/stream/stream_DeMux.rst b/docs/IPCores/bus/stream/stream_DeMux.rst index f9f50898..46a9f747 100644 --- a/docs/IPCores/bus/stream/stream_DeMux.rst +++ b/docs/IPCores/bus/stream/stream_DeMux.rst @@ -1,3 +1,8 @@ +.. _IP:stream_DeMux: + +PoC.bus.stream.DeMux +#################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:stream_DeMux: - -stream_DeMux -############ - .. TODO:: No documentation available. diff --git a/docs/IPCores/bus/stream/stream_FrameGenerator.rst b/docs/IPCores/bus/stream/stream_FrameGenerator.rst index e86e59be..9e4c36f5 100644 --- a/docs/IPCores/bus/stream/stream_FrameGenerator.rst +++ b/docs/IPCores/bus/stream/stream_FrameGenerator.rst @@ -1,3 +1,8 @@ +.. _IP:stream_FrameGenerator: + +PoC.bus.stream.FrameGenerator +############################# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:stream_FrameGenerator: - -stream_FrameGenerator -##################### - .. TODO:: No documentation available. diff --git a/docs/IPCores/bus/stream/stream_Mirror.rst b/docs/IPCores/bus/stream/stream_Mirror.rst index e1602042..c4796273 100644 --- a/docs/IPCores/bus/stream/stream_Mirror.rst +++ b/docs/IPCores/bus/stream/stream_Mirror.rst @@ -1,3 +1,8 @@ +.. _IP:stream_Mirror: + +PoC.bus.stream.Mirror +##################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:stream_Mirror: - -stream_Mirror -############# - .. TODO:: No documentation available. diff --git a/docs/IPCores/bus/stream/stream_Mux.rst b/docs/IPCores/bus/stream/stream_Mux.rst index ff0cb3a0..0c08de95 100644 --- a/docs/IPCores/bus/stream/stream_Mux.rst +++ b/docs/IPCores/bus/stream/stream_Mux.rst @@ -1,3 +1,8 @@ +.. _IP:stream_Mux: + +PoC.bus.stream.Mux +################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:stream_Mux: - -stream_Mux -########## - .. TODO:: No documentation available. diff --git a/docs/IPCores/bus/stream/stream_Sink.rst b/docs/IPCores/bus/stream/stream_Sink.rst index 14aff7d5..1066b091 100644 --- a/docs/IPCores/bus/stream/stream_Sink.rst +++ b/docs/IPCores/bus/stream/stream_Sink.rst @@ -1,3 +1,8 @@ +.. _IP:stream_Sink: + +PoC.bus.stream.Sink +################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:stream_Sink: - -stream_Sink -########### - .. TODO:: No documentation available. diff --git a/docs/IPCores/bus/stream/stream_Source.rst b/docs/IPCores/bus/stream/stream_Source.rst index b32b3e0d..1e3a5d76 100644 --- a/docs/IPCores/bus/stream/stream_Source.rst +++ b/docs/IPCores/bus/stream/stream_Source.rst @@ -1,3 +1,8 @@ +.. _IP:stream_Source: + +PoC.bus.stream.Source +##################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:stream_Source: - -stream_Source -############# - .. TODO:: No documentation available. diff --git a/docs/IPCores/bus/wb/wb_fifo_adapter.rst b/docs/IPCores/bus/wb/wb_fifo_adapter.rst index 09b21d66..52ef58e2 100644 --- a/docs/IPCores/bus/wb/wb_fifo_adapter.rst +++ b/docs/IPCores/bus/wb/wb_fifo_adapter.rst @@ -1,3 +1,8 @@ +.. _IP:wb_fifo_adapter: + +PoC.bus.wb.fifo_adapter +####################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:wb_fifo_adapter: - -wb_fifo_adapter -############### - Small FIFOs are included in this module, if larger or asynchronous transmit / receive FIFOs are required, then they must be connected externally. diff --git a/docs/IPCores/bus/wb/wb_ocram.rst b/docs/IPCores/bus/wb/wb_ocram.rst index 424948ee..b6c3e2d8 100644 --- a/docs/IPCores/bus/wb/wb_ocram.rst +++ b/docs/IPCores/bus/wb/wb_ocram.rst @@ -1,3 +1,8 @@ +.. _IP:ocram_wb: + +PoC.bus.wb.ocram +################ + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ocram_wb: - -ocram_wb -######## - This slave supports Wishbone Registered Feedback bus cycles (aka. burst transfers / advanced synchronous cycle termination). The mode "Incrementing burst cycle" (CTI = 010) with "Linear burst" (BTE = 00) is supported. diff --git a/docs/IPCores/bus/wb/wb_uart_wrapper.rst b/docs/IPCores/bus/wb/wb_uart_wrapper.rst index 24677510..2036cff0 100644 --- a/docs/IPCores/bus/wb/wb_uart_wrapper.rst +++ b/docs/IPCores/bus/wb/wb_uart_wrapper.rst @@ -1,3 +1,8 @@ +.. _IP:uart_wb: + +PoC.bus.wb.uart_wrapper +####################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:uart_wb: - -uart_wb -####### - Wrapper module for :doc:`PoC.io.uart.rx ` and :doc:`PoC.io.uart.tx ` to support the Wishbone interface. Synchronized reset is used. diff --git a/docs/IPCores/cache/cache_cpu.rst b/docs/IPCores/cache/cache_cpu.rst index c0b62cb1..55274fa1 100644 --- a/docs/IPCores/cache/cache_cpu.rst +++ b/docs/IPCores/cache/cache_cpu.rst @@ -1,3 +1,8 @@ +.. _IP:cache_cpu: + +PoC.cache.cpu +############# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:cache_cpu: - -cache_cpu -######### - This unit provides a cache (:ref:`IP:cache_par2`) together with a cache controller which reads / writes cache lines from / to memory. The memory is accessed using a :ref:`INT:PoC.Mem` interfaces, the related diff --git a/docs/IPCores/cache/cache_mem.rst b/docs/IPCores/cache/cache_mem.rst index dd2c4b2f..a0da1e10 100644 --- a/docs/IPCores/cache/cache_mem.rst +++ b/docs/IPCores/cache/cache_mem.rst @@ -1,3 +1,8 @@ +.. _IP:cache_mem: + +PoC.cache.mem +############# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:cache_mem: - -cache_mem -######### - This unit provides a cache (:ref:`IP:cache_par2`) together with a cache controller which reads / writes cache lines from / to memory. It has two :ref:`INT:PoC.Mem` interfaces: diff --git a/docs/IPCores/cache/cache_par.rst b/docs/IPCores/cache/cache_par.rst index 879f6ee1..821b84f7 100644 --- a/docs/IPCores/cache/cache_par.rst +++ b/docs/IPCores/cache/cache_par.rst @@ -1,3 +1,8 @@ +.. _IP:cache_par: + +PoC.cache.par +############# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:cache_par: - -cache_par -######### - Implements a cache with parallel tag-unit and data memory. .. NOTE:: diff --git a/docs/IPCores/cache/cache_par2.rst b/docs/IPCores/cache/cache_par2.rst index f3e8134f..1c45ad63 100644 --- a/docs/IPCores/cache/cache_par2.rst +++ b/docs/IPCores/cache/cache_par2.rst @@ -1,3 +1,8 @@ +.. _IP:cache_par2: + +PoC.cache.par2 +############## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:cache_par2: - -cache_par2 -########## - Cache with parallel tag-unit and data memory. For the data memory, :ref:`IP:ocram_sp` is used. diff --git a/docs/IPCores/cache/cache_replacement_policy.rst b/docs/IPCores/cache/cache_replacement_policy.rst index 2d7dc2e4..da989e77 100644 --- a/docs/IPCores/cache/cache_replacement_policy.rst +++ b/docs/IPCores/cache/cache_replacement_policy.rst @@ -1,3 +1,8 @@ +.. _IP:cache_replacement_policy: + +PoC.cache.replacement_policy +############################ + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -15,12 +20,6 @@ * |gh-tb| :poctb:`Testbench ` -.. _IP:cache_replacement_policy: - -cache_replacement_policy -######################## - - **Supported policies:** +----------+-----------------------+-----------+ diff --git a/docs/IPCores/cache/cache_tagunit_par.rst b/docs/IPCores/cache/cache_tagunit_par.rst index 7f2cbb25..b0d9e6a8 100644 --- a/docs/IPCores/cache/cache_tagunit_par.rst +++ b/docs/IPCores/cache/cache_tagunit_par.rst @@ -1,3 +1,8 @@ +.. _IP:cache_tagunit_par: + +PoC.cache.tagunit_par +##################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:cache_tagunit_par: - -cache_tagunit_par -################# - Tag-unit with fully-parallel compare of tag. Configuration diff --git a/docs/IPCores/cache/cache_tagunit_seq.rst b/docs/IPCores/cache/cache_tagunit_seq.rst index e3f83244..3c6e0af9 100644 --- a/docs/IPCores/cache/cache_tagunit_seq.rst +++ b/docs/IPCores/cache/cache_tagunit_seq.rst @@ -1,3 +1,8 @@ +.. _IP:cache_tagunit_seq: + +PoC.cache.tagunit_seq +##################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:cache_tagunit_seq: - -cache_tagunit_seq -################# - .. TODO:: No documentation available. diff --git a/docs/IPCores/comm/comm_crc.rst b/docs/IPCores/comm/comm_crc.rst index 0418627f..29607682 100644 --- a/docs/IPCores/comm/comm_crc.rst +++ b/docs/IPCores/comm/comm_crc.rst @@ -1,3 +1,8 @@ +.. _IP:comm_crc: + +PoC.comm.crc +############ + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:comm_crc: - -comm_crc -######## - Computes the Cyclic Redundancy Check (CRC) for a data packet as remainder of the polynomial division of the message by the given generator polynomial (GEN). diff --git a/docs/IPCores/comm/comm_scramble.rst b/docs/IPCores/comm/comm_scramble.rst index e1905884..031e60f7 100644 --- a/docs/IPCores/comm/comm_scramble.rst +++ b/docs/IPCores/comm/comm_scramble.rst @@ -1,3 +1,8 @@ +.. _IP:comm_scramble: + +PoC.comm.scramble +################# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:comm_scramble: - -comm_scramble -############# - The LFSR computation is unrolled to generate an arbitrary number of mask bits in parallel. The mask are output in little endian. The generated bit sequence is independent from the chosen output width. diff --git a/docs/IPCores/fifo/fifo_cc_got.rst b/docs/IPCores/fifo/fifo_cc_got.rst index fdc19e38..2e32c363 100644 --- a/docs/IPCores/fifo/fifo_cc_got.rst +++ b/docs/IPCores/fifo/fifo_cc_got.rst @@ -1,3 +1,8 @@ +.. _IP:fifo_cc_got: + +PoC.fifo.cc_got +############### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:fifo_cc_got: - -fifo_cc_got -########### - This module implements a regular FIFO with common clock (cc), pipelined interface. Common clock means read and write port use the same clock. The FIFO size can be configured in word width (``D_BITS``) and minimum word count diff --git a/docs/IPCores/fifo/fifo_cc_got_tempgot.rst b/docs/IPCores/fifo/fifo_cc_got_tempgot.rst index 027d78b9..80420277 100644 --- a/docs/IPCores/fifo/fifo_cc_got_tempgot.rst +++ b/docs/IPCores/fifo/fifo_cc_got_tempgot.rst @@ -1,3 +1,8 @@ +.. _IP:fifo_cc_got_tempgot: + +PoC.fifo.cc_got_tempgot +####################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:fifo_cc_got_tempgot: - -fifo_cc_got_tempgot -################### - The specified depth (``MIN_DEPTH``) is rounded up to the next suitable value. As uncommitted reads occupy FIFO space that is not yet available for diff --git a/docs/IPCores/fifo/fifo_cc_got_tempput.rst b/docs/IPCores/fifo/fifo_cc_got_tempput.rst index acbc85f4..7035089d 100644 --- a/docs/IPCores/fifo/fifo_cc_got_tempput.rst +++ b/docs/IPCores/fifo/fifo_cc_got_tempput.rst @@ -1,3 +1,8 @@ +.. _IP:fifo_cc_got_tempput: + +PoC.fifo.cc_got_tempput +####################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:fifo_cc_got_tempput: - -fifo_cc_got_tempput -################### - The specified depth (``MIN_DEPTH``) is rounded up to the next suitable value. As uncommitted writes populate FIFO space that is not yet available for diff --git a/docs/IPCores/fifo/fifo_dc_got_sm.rst b/docs/IPCores/fifo/fifo_dc_got_sm.rst index ff5b6c97..810f11c0 100644 --- a/docs/IPCores/fifo/fifo_dc_got_sm.rst +++ b/docs/IPCores/fifo/fifo_dc_got_sm.rst @@ -1,3 +1,8 @@ +.. _IP:fifo_dc_got_sm: + +PoC.fifo.dc_got_sm +################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:fifo_dc_got_sm: - -fifo_dc_got_sm -############## - Dependent clocks meens, that one clock must be a multiple of the other one. And your synthesis tool must check for setup- and hold-time violations. diff --git a/docs/IPCores/fifo/fifo_glue.rst b/docs/IPCores/fifo/fifo_glue.rst index 0c750607..9734977c 100644 --- a/docs/IPCores/fifo/fifo_glue.rst +++ b/docs/IPCores/fifo/fifo_glue.rst @@ -1,3 +1,8 @@ +.. _IP:fifo_glue: + +PoC.fifo.glue +############# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:fifo_glue: - -fifo_glue -######### - Its primary use is the decoupling of enable domains in a processing pipeline. Data storage is limited to two words only so as to allow both the ``ful`` and the ``vld`` indicators to be driven by registers. diff --git a/docs/IPCores/fifo/fifo_ic_assembly.rst b/docs/IPCores/fifo/fifo_ic_assembly.rst index 9e985933..66feb06a 100644 --- a/docs/IPCores/fifo/fifo_ic_assembly.rst +++ b/docs/IPCores/fifo/fifo_ic_assembly.rst @@ -1,3 +1,8 @@ +.. _IP:fifo_ic_assembly: + +PoC.fifo.ic_assembly +#################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:fifo_ic_assembly: - -fifo_ic_assembly -################ - This module assembles a FIFO stream from data blocks that may arrive slightly out of order. The arriving data is ordered according to their address. The streamed output starts with the data word written to diff --git a/docs/IPCores/fifo/fifo_ic_got.rst b/docs/IPCores/fifo/fifo_ic_got.rst index 778c6c5d..3a6e5dbc 100644 --- a/docs/IPCores/fifo/fifo_ic_got.rst +++ b/docs/IPCores/fifo/fifo_ic_got.rst @@ -1,3 +1,8 @@ +.. _IP:fifo_ic_got: + +PoC.fifo.ic_got +############### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:fifo_ic_got: - -fifo_ic_got -########### - Independent clocks meens that read and write clock are unrelated. This implementation uses dedicated block RAM for storing data. diff --git a/docs/IPCores/fifo/fifo_shift.rst b/docs/IPCores/fifo/fifo_shift.rst index 26b0cf6f..25f3162b 100644 --- a/docs/IPCores/fifo/fifo_shift.rst +++ b/docs/IPCores/fifo/fifo_shift.rst @@ -1,3 +1,8 @@ +.. _IP:fifo_shift: + +PoC.fifo.shift +############## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:fifo_shift: - -fifo_shift -########## - This FIFO implementation is based on an internal shift register. This is especially useful for smaller FIFO sizes, which can be implemented in LUT storage on some devices (e.g. Xilinx' SRLs). Only a single read pointer is diff --git a/docs/IPCores/io/ddrio/ddrio_in.rst b/docs/IPCores/io/ddrio/ddrio_in.rst index b9c3b7d8..20711814 100644 --- a/docs/IPCores/io/ddrio/ddrio_in.rst +++ b/docs/IPCores/io/ddrio/ddrio_in.rst @@ -1,3 +1,8 @@ +.. _IP:ddrio_in: + +PoC.io.ddrio.in +############### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ddrio_in: - -ddrio_in -######## - Instantiates chip-specific :abbr:`DDR (Double Data Rate)` input registers. Both data ``DataIn_high/low`` are synchronously outputted to the on-chip logic @@ -31,31 +30,23 @@ the falling edge of the clock as depicted in the following waveform. .. wavedrom:: { signal: [ - {name: 'clk', wave: 'H.L.H.L.H.L.H.L.H'}, - {name: 'pad', wave: 'x2.3.4.5.2.3.x...', data: ['0', '1', '2', '3', '4', '5'], node: '.a.b.c.d.e.f...'}, - {name: 'DataIn_low', wave: 'x...2...4...2...x', data: ['0', '2', '4'], node: '....k...m...o..'}, - {name: 'DataIn_high', wave: 'x...3...5...3...x', data: ['1', '3', '5'], node: '....l...n...p..'} + ['DataIn', + {name: 'ClockIn', wave: 'L.H.L.H.L.H.L.H.L.'}, + {name: 'ClockInEnable', wave: '01............0...'}, + {name: 'DataIn_low', wave: 'x.....2...4...x...', data: ['0', '2'], node: '......u...w.'}, + {name: 'DataIn_high', wave: 'x.....3...5...x...', data: ['1', '3'], node: '......v...x.'} + ], + {name: 'Pad', wave: 'x2.3.4.5.x........', data: ['0', '1', '2', '3'], node: '.a.b.c.d.....'}, ], - edge: ['a|->k', 'b|->l', 'c|->m', 'd|->n', 'e|->o', 'f|->p'], + edge: ['a~>u', 'b~>v', 'c~>w', 'd~>x'], foot: { text: ['tspan', - ['tspan', {'font-weight': 'bold'}, 'PoC.io.ddrio.in'], - ' -- DDR Data Input sampled from pad.' + ['tspan', {'font-weight': 'bold'}, 'PoC.io.ddrio.inout'], + ' -- DDR Data Input/Output sampled from pad.' ] } } -.. only:: latex - - .. code-block:: none - __ ____ ____ __ - Clock |____| |____| |____| - Pad < 0 >< 1 >< 2 >< 3 >< 4 >< 5 > - DataIn_low ... >< 0 >< 2 >< - DataIn_high ... >< 1 >< 3 >< - - < i > is the value of the i-th data bit on the line. - After power-up, the output ports ``DataIn_high`` and ``DataIn_low`` both equal INIT_VALUE. @@ -70,7 +61,7 @@ IOBs. :language: vhdl :tab-width: 2 :linenos: - :lines: 82-94 + :lines: 74-86 diff --git a/docs/IPCores/io/ddrio/ddrio_inout.rst b/docs/IPCores/io/ddrio/ddrio_inout.rst index caaade74..56dfd31c 100644 --- a/docs/IPCores/io/ddrio/ddrio_inout.rst +++ b/docs/IPCores/io/ddrio/ddrio_inout.rst @@ -1,3 +1,8 @@ +.. _IP:ddrio_inout: + +PoC.io.ddrio.inout +################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ddrio_inout: - -ddrio_inout -########### - Instantiates chip-specific :abbr:`DDR (Double Data Rate)` input and output registers. @@ -37,15 +36,34 @@ sampled with the same rising edge. ``DataIn_low`` is the value sampled with the falling edge directly before this rising edge. Thus sampling starts with the falling edge of the clock as depicted in the following waveform. -.. code-block:: none - - __ ____ ____ __ - Clock |____| |____| |____| - Pad < 0 >< 1 >< 2 >< 3 >< 4 >< 5 > - DataIn_low ... >< 0 >< 2 >< - DataIn_high ... >< 1 >< 3 >< - - < i > is the value of the i-th data bit on the line. +.. wavedrom:: + + { signal: [ + ['DataOut', + {name: 'ClockOut', wave: 'LH.L.H.L.H.L.H.L.H.L.H.'}, + {name: 'ClockOutEnable', wave: '0..1...................'}, + {name: 'OutputEnable', wave: '0.......1.......0......'}, + {name: 'DataOut_low', wave: 'x.......2...4...x......', data: ['4', '6'], node: '........k...m...o..'}, + {name: 'DataOut_high', wave: 'x.......3...5...x......', data: ['5', '7'], node: '........l...n...p..'} + ], + {}, + {name: 'Pad', wave: 'x2.3.4.5.z...2.3.4.5.z.', data: ['0', '1', '2', '3', '4', '5', '6', '7'], node: '.a.b.c.d.....e.f.g.h.'}, + {}, + ['DataIn', + {name: 'ClockIn', wave: 'L.H.L.H.L.H.L.H.L.H.L.H'}, + {name: 'ClockInEnable', wave: '01.......0.............'}, + {name: 'DataIn_low', wave: 'x.....2...4...z...2...4', data: ['0', '2', '4'], node: '......u...w.......y..'}, + {name: 'DataIn_high', wave: 'x.....3...5...z...3...5', data: ['1', '3', '5'], node: '......v...x.......z..'} + ] + ], + edge: ['a~>u', 'b~>v', 'c~>w', 'd~>x', 'k~>e', 'l~>f', 'm~>g', 'n~>h', 'e~>y', 'f~>z'], + foot: { + text: ['tspan', + ['tspan', {'font-weight': 'bold'}, 'PoC.io.ddrio.inout'], + ' -- DDR Data Input/Output sampled from pad.' + ] + } + } ``Pad`` must be connected to a PAD because FPGAs only have these registers in IOBs. @@ -58,7 +76,7 @@ IOBs. :language: vhdl :tab-width: 2 :linenos: - :lines: 70-88 + :lines: 89-107 diff --git a/docs/IPCores/io/ddrio/ddrio_out.rst b/docs/IPCores/io/ddrio/ddrio_out.rst index 171b8a00..569ad84b 100644 --- a/docs/IPCores/io/ddrio/ddrio_out.rst +++ b/docs/IPCores/io/ddrio/ddrio_out.rst @@ -1,3 +1,8 @@ +.. _IP:ddrio_out: + +PoC.io.ddrio.out +################ + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ddrio_out: - -ddrio_out -######### - Instantiates chip-specific :abbr:`DDR (Double Data Rate)` output registers. Both data ``DataOut_high/low`` as well as ``OutputEnable`` are sampled with @@ -34,6 +33,28 @@ setting ``NO_OUTPUT_ENABLE = true``. If ``NO_OUTPUT_ENABLE = false`` then output is disabled after power-up. If ``NO_OUTPUT_ENABLE = true`` then output after power-up equals ``INIT_VALUE``. +.. wavedrom:: + + { signal: [ + ['DataOut', + {name: 'ClockOut', wave: 'L.H.L.H.L.H.L.H.'}, + {name: 'ClockOutEnable', wave: '01...........0..'}, + {name: 'OutputEnable', wave: '01.......0......'}, + {name: 'DataOut_low', wave: 'x2...4...x......', data: ['0', '2'], node: '.k...m'}, + {name: 'DataOut_high', wave: 'x3...5...x......', data: ['1', '3'], node: '.l...n'} + ], + {}, + {name: 'Pad', wave: 'x.....2.3.4.5.z.', data: ['0', '1', '2', '3'], node: '......a.b.c.d.'}, + ], + edge: ['k~>a', 'l~>b', 'm~>c', 'n~>d'], + foot: { + text: ['tspan', + ['tspan', {'font-weight': 'bold'}, 'PoC.io.ddrio.out'], + ' -- DDR Data Output sampled from pad.' + ] + } + } + ``Pad`` must be connected to a PAD because FPGAs only have these registers in IOBs. @@ -45,7 +66,7 @@ IOBs. :language: vhdl :tab-width: 2 :linenos: - :lines: 57-71 + :lines: 79-93 diff --git a/docs/IPCores/io/iic/iic_BusController.rst b/docs/IPCores/io/iic/iic_BusController.rst index 8d33a198..170035e7 100644 --- a/docs/IPCores/io/iic/iic_BusController.rst +++ b/docs/IPCores/io/iic/iic_BusController.rst @@ -1,3 +1,8 @@ +.. _IP:iic_BusController: + +PoC.io.iic.BusController +######################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:iic_BusController: - -iic_BusController -################# - The I2C BusController transmitts bits over the I2C bus (SerialClock - SCL, SerialData - SDA) and also receives them. To send/receive words over the I2C bus, use the I2C Controller, which utilizes this controller. This diff --git a/docs/IPCores/io/iic/iic_Controller.rst b/docs/IPCores/io/iic/iic_Controller.rst index bb2ff129..cd76f285 100644 --- a/docs/IPCores/io/iic/iic_Controller.rst +++ b/docs/IPCores/io/iic/iic_Controller.rst @@ -1,3 +1,8 @@ +.. _IP:iic_Controller: + +PoC.io.iic.Controller +##################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:iic_Controller: - -iic_Controller -############## - The I2C Controller transmitts words over the I2C bus (SerialClock - SCL, SerialData - SDA) and also receives them. This controller utilizes the I2C BusController to send/receive bits over the I2C bus. This controller diff --git a/docs/IPCores/io/iic/iic_Controller_SFF8431.rst b/docs/IPCores/io/iic/iic_Controller_SFF8431.rst index 6ccb2aca..0504ccc8 100644 --- a/docs/IPCores/io/iic/iic_Controller_SFF8431.rst +++ b/docs/IPCores/io/iic/iic_Controller_SFF8431.rst @@ -1,3 +1,8 @@ +.. _IP:IICController_SFF8431: + +PoC.io.iic.Controller_SFF8431 +############################# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -15,12 +20,6 @@ * |gh-tb| :poctb:`Testbench ` -.. _IP:IICController_SFF8431: - -IICController_SFF8431 -##################### - - .. rubric:: Entity Declaration: diff --git a/docs/IPCores/io/iic/iic_Switch_PCA9548A.rst b/docs/IPCores/io/iic/iic_Switch_PCA9548A.rst index 07ce165f..cc16c51c 100644 --- a/docs/IPCores/io/iic/iic_Switch_PCA9548A.rst +++ b/docs/IPCores/io/iic/iic_Switch_PCA9548A.rst @@ -1,3 +1,8 @@ +.. _IP:iic_Switch_PCA9548A: + +PoC.io.iic.Switch_PCA9548A +########################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:iic_Switch_PCA9548A: - -iic_Switch_PCA9548A -################### - .. TODO:: No documentation available. TODO diff --git a/docs/IPCores/io/io_7SegmentMux_BCD.rst b/docs/IPCores/io/io_7SegmentMux_BCD.rst index 31b702eb..282b5263 100644 --- a/docs/IPCores/io/io_7SegmentMux_BCD.rst +++ b/docs/IPCores/io/io_7SegmentMux_BCD.rst @@ -1,3 +1,8 @@ +.. _IP:io_7SegmentMux_BCD: + +PoC.io.7SegmentMux_BCD +###################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:io_7SegmentMux_BCD: - -io_7SegmentMux_BCD -################## - This module is a 7 segment display controller that uses time multiplexing to control a common anode for each digit in the display. The shown characters are BCD encoded. A dot per digit is optional. A minus sign for negative diff --git a/docs/IPCores/io/io_7SegmentMux_HEX.rst b/docs/IPCores/io/io_7SegmentMux_HEX.rst index 58b2ec48..f039534b 100644 --- a/docs/IPCores/io/io_7SegmentMux_HEX.rst +++ b/docs/IPCores/io/io_7SegmentMux_HEX.rst @@ -1,3 +1,8 @@ +.. _IP:io_7SegmentMux_HEX: + +PoC.io.7SegmentMux_HEX +###################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:io_7SegmentMux_HEX: - -io_7SegmentMux_HEX -################## - This module is a 7 segment display controller that uses time multiplexing to control a common anode for each digit in the display. The shown characters are HEX encoded. A dot per digit is optional. diff --git a/docs/IPCores/io/io_Debounce.rst b/docs/IPCores/io/io_Debounce.rst index 04d30237..e56df96b 100644 --- a/docs/IPCores/io/io_Debounce.rst +++ b/docs/IPCores/io/io_Debounce.rst @@ -1,3 +1,8 @@ +.. _IP:io_Debounce: + +PoC.io.Debounce +############### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:io_Debounce: - -io_Debounce -########### - This module debounces several input pins preventing input changes following a previous one within the configured ``BOUNCE_TIME`` to pass. Internally, the forwarded state is locked for, at least, this ``BOUNCE_TIME``. diff --git a/docs/IPCores/io/io_FanControl.rst b/docs/IPCores/io/io_FanControl.rst index a4d2a230..6858fc80 100644 --- a/docs/IPCores/io/io_FanControl.rst +++ b/docs/IPCores/io/io_FanControl.rst @@ -1,3 +1,8 @@ +.. _IP:io_FanControl: + +PoC.io.FanControl +################# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:io_FanControl: - -io_FanControl -############# - .. code-block:: none This module generates a PWM signal for a 3-pin (transistor controlled) or diff --git a/docs/IPCores/io/io_FrequencyCounter.rst b/docs/IPCores/io/io_FrequencyCounter.rst index 90b56c8d..ef678db1 100644 --- a/docs/IPCores/io/io_FrequencyCounter.rst +++ b/docs/IPCores/io/io_FrequencyCounter.rst @@ -1,3 +1,8 @@ +.. _IP:io_FrequencyCounter: + +PoC.io.FrequencyCounter +####################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:io_FrequencyCounter: - -io_FrequencyCounter -################### - .. TODO:: No documentation available. diff --git a/docs/IPCores/io/io_GlitchFilter.rst b/docs/IPCores/io/io_GlitchFilter.rst index 3c40e808..21a8a8d3 100644 --- a/docs/IPCores/io/io_GlitchFilter.rst +++ b/docs/IPCores/io/io_GlitchFilter.rst @@ -1,3 +1,8 @@ +.. _IP:io_GlitchFilter: + +PoC.io.GlitchFilter +################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:io_GlitchFilter: - -io_GlitchFilter -############### - This module filters glitches on a wire. The high and low spike suppression cycle counts can be configured. diff --git a/docs/IPCores/io/io_KeyPadScanner.rst b/docs/IPCores/io/io_KeyPadScanner.rst index 604a1b0a..9e894bcc 100644 --- a/docs/IPCores/io/io_KeyPadScanner.rst +++ b/docs/IPCores/io/io_KeyPadScanner.rst @@ -1,3 +1,8 @@ +.. _IP:io_KeyPadScanner: + +PoC.io.KeyPadScanner +#################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:io_KeyPadScanner: - -io_KeyPadScanner -################ - This module drives a one-hot encoded column vector to read back a rows vector. By scanning column-by-column it's possible to extract the current button state of the whole keypad. The scanner uses high-active logic. The diff --git a/docs/IPCores/io/io_PulseWidthModulation.rst b/docs/IPCores/io/io_PulseWidthModulation.rst index e45c8a70..43f23ee2 100644 --- a/docs/IPCores/io/io_PulseWidthModulation.rst +++ b/docs/IPCores/io/io_PulseWidthModulation.rst @@ -1,3 +1,8 @@ +.. _IP:io_PulseWidthModulation: + +PoC.io.PulseWidthModulation +########################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:io_PulseWidthModulation: - -io_PulseWidthModulation -####################### - This module generates a pulse width modulated signal, that can be configured in frequency (``PWM_FREQ``) and modulation granularity (``PWM_RESOLUTION``). diff --git a/docs/IPCores/io/io_TimingCounter.rst b/docs/IPCores/io/io_TimingCounter.rst index c7203047..eaaf8251 100644 --- a/docs/IPCores/io/io_TimingCounter.rst +++ b/docs/IPCores/io/io_TimingCounter.rst @@ -1,3 +1,8 @@ +.. _IP:io_TimingCounter: + +PoC.io.TimingCounter +#################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:io_TimingCounter: - -io_TimingCounter -################ - This down-counter can be configured with a ``TIMING_TABLE`` (a ROM), from which the initial counter value is loaded. The table index can be selected by ``Slot``. ``Timeout`` is a registered output. Up to 16 values fit into one ROM diff --git a/docs/IPCores/io/lcd/lcd_LCDBuffer.rst b/docs/IPCores/io/lcd/lcd_LCDBuffer.rst index 801ed2f6..4803a156 100644 --- a/docs/IPCores/io/lcd/lcd_LCDBuffer.rst +++ b/docs/IPCores/io/lcd/lcd_LCDBuffer.rst @@ -1,3 +1,8 @@ +.. _IP:lcd_LCDBuffer: + +PoC.io.lcd.LCDBuffer +#################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:lcd_LCDBuffer: - -lcd_LCDBuffer -############# - .. TODO:: No documentation available. diff --git a/docs/IPCores/io/lcd/lcd_LCDBusController.rst b/docs/IPCores/io/lcd/lcd_LCDBusController.rst index fcf1e2f8..45d3a0ef 100644 --- a/docs/IPCores/io/lcd/lcd_LCDBusController.rst +++ b/docs/IPCores/io/lcd/lcd_LCDBusController.rst @@ -1,3 +1,8 @@ +.. _IP:lcd_LCDBusController: + +PoC.io.lcd.LCDBusController +########################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:lcd_LCDBusController: - -lcd_LCDBusController -#################### - .. TODO:: No documentation available. diff --git a/docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst b/docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst index 992f5449..9bc9f717 100644 --- a/docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst +++ b/docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst @@ -1,3 +1,8 @@ +.. _IP:lcd_LCDController_KS0066U: + +PoC.io.lcd.LCDController_KS0066U +################################ + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:lcd_LCDController_KS0066U: - -lcd_LCDController_KS0066U -######################### - .. TODO:: No documentation available. diff --git a/docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst b/docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst index c8fc89a2..576e9c3d 100644 --- a/docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst +++ b/docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst @@ -1,3 +1,8 @@ +.. _IP:lcd_LCDSynchronizer: + +PoC.io.lcd.LCDSynchronizer +########################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:lcd_LCDSynchronizer: - -lcd_LCDSynchronizer -################### - .. TODO:: No documentation available. diff --git a/docs/IPCores/io/lcd/lcd_dotmatrix.rst b/docs/IPCores/io/lcd/lcd_dotmatrix.rst index 643461de..300ca5ff 100644 --- a/docs/IPCores/io/lcd/lcd_dotmatrix.rst +++ b/docs/IPCores/io/lcd/lcd_dotmatrix.rst @@ -1,3 +1,8 @@ +.. _IP:lcd_dotmatrix: + +PoC.io.lcd.dotmatrix +#################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:lcd_dotmatrix: - -lcd_dotmatrix -############# - .. TODO:: No documentation available. diff --git a/docs/IPCores/io/mdio/mdio_Controller.rst b/docs/IPCores/io/mdio/mdio_Controller.rst index 260fe47c..c3b4c654 100644 --- a/docs/IPCores/io/mdio/mdio_Controller.rst +++ b/docs/IPCores/io/mdio/mdio_Controller.rst @@ -1,3 +1,8 @@ +.. _IP:mdio_Controller: + +PoC.io.mdio.Controller +###################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:mdio_Controller: - -mdio_Controller -############### - .. TODO:: No documentation available. diff --git a/docs/IPCores/io/mdio/mdio_IIC_Adapter.rst b/docs/IPCores/io/mdio/mdio_IIC_Adapter.rst index c8d3cabe..fea3d8dd 100644 --- a/docs/IPCores/io/mdio/mdio_IIC_Adapter.rst +++ b/docs/IPCores/io/mdio/mdio_IIC_Adapter.rst @@ -1,3 +1,8 @@ +.. _IP:mdio_IIC_Adapter: + +PoC.io.mdio.IIC_Adapter +####################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:mdio_IIC_Adapter: - -mdio_IIC_Adapter -################ - .. TODO:: No documentation available. diff --git a/docs/IPCores/io/pio/pio_fifo_in.rst b/docs/IPCores/io/pio/pio_fifo_in.rst index 07a08532..3c1564a0 100644 --- a/docs/IPCores/io/pio/pio_fifo_in.rst +++ b/docs/IPCores/io/pio/pio_fifo_in.rst @@ -1,3 +1,8 @@ +.. _IP:pio_fifo_in: + +PoC.io.pio.fifo_in +################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -15,12 +20,6 @@ * |gh-tb| :poctb:`Testbench ` -.. _IP:pio_fifo_in: - -pio_fifo_in -########### - - .. rubric:: Entity Declaration: diff --git a/docs/IPCores/io/pio/pio_fifo_out.rst b/docs/IPCores/io/pio/pio_fifo_out.rst index 63b0418c..7d7f7aa2 100644 --- a/docs/IPCores/io/pio/pio_fifo_out.rst +++ b/docs/IPCores/io/pio/pio_fifo_out.rst @@ -1,3 +1,8 @@ +.. _IP:pio_fifo_out: + +PoC.io.pio.fifo_out +################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -15,12 +20,6 @@ * |gh-tb| :poctb:`Testbench ` -.. _IP:pio_fifo_out: - -pio_fifo_out -############ - - .. rubric:: Entity Declaration: diff --git a/docs/IPCores/io/pio/pio_in.rst b/docs/IPCores/io/pio/pio_in.rst index 48645919..89365672 100644 --- a/docs/IPCores/io/pio/pio_in.rst +++ b/docs/IPCores/io/pio/pio_in.rst @@ -1,3 +1,8 @@ +.. _IP:pio_in: + +PoC.io.pio.in +############# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -15,12 +20,6 @@ * |gh-tb| :poctb:`Testbench ` -.. _IP:pio_in: - -pio_in -###### - - .. rubric:: Entity Declaration: diff --git a/docs/IPCores/io/pio/pio_out.rst b/docs/IPCores/io/pio/pio_out.rst index 792644b5..b9a8c652 100644 --- a/docs/IPCores/io/pio/pio_out.rst +++ b/docs/IPCores/io/pio/pio_out.rst @@ -1,3 +1,8 @@ +.. _IP:pio_out: + +PoC.io.pio.out +############## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -15,12 +20,6 @@ * |gh-tb| :poctb:`Testbench ` -.. _IP:pio_out: - -pio_out -####### - - .. rubric:: Entity Declaration: diff --git a/docs/IPCores/io/pmod/pmod_KYPD.rst b/docs/IPCores/io/pmod/pmod_KYPD.rst index 83a4ca4f..338a9e65 100644 --- a/docs/IPCores/io/pmod/pmod_KYPD.rst +++ b/docs/IPCores/io/pmod/pmod_KYPD.rst @@ -1,3 +1,8 @@ +.. _IP:pmod_KYPD: + +PoC.io.pmod.KYPD +################ + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:pmod_KYPD: - -pmod_KYPD -######### - This module drives a 4-bit one-cold encoded column vector to read back a 4-bit rows vector. By scanning column-by-column it's possible to extract the current button state of the whole keypad. This wrapper converts the diff --git a/docs/IPCores/io/pmod/pmod_SSD.rst b/docs/IPCores/io/pmod/pmod_SSD.rst index 4a65c8ff..f59e2f3d 100644 --- a/docs/IPCores/io/pmod/pmod_SSD.rst +++ b/docs/IPCores/io/pmod/pmod_SSD.rst @@ -1,3 +1,8 @@ +.. _IP:pmod_SSD: + +PoC.io.pmod.SSD +############### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:pmod_SSD: - -pmod_SSD -######## - This module drives a dual-digit 7-segment display (Pmod_SSD). The module expects two binary encoded 4-bit ``Digit`` signals and drives a 2x6 bit Pmod connector (7 anode bits, 1 cathode bit). diff --git a/docs/IPCores/io/pmod/pmod_USBUART.rst b/docs/IPCores/io/pmod/pmod_USBUART.rst index b86a0308..db37da9d 100644 --- a/docs/IPCores/io/pmod/pmod_USBUART.rst +++ b/docs/IPCores/io/pmod/pmod_USBUART.rst @@ -1,3 +1,8 @@ +.. _IP:pmod_USBUART: + +PoC.io.pmod.USBUART +################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:pmod_USBUART: - -pmod_USBUART -############ - This module abstracts a FTDI FT232R USB-UART bridge by instantiating a :doc:`PoC.io.uart.fifo <../uart/uart_fifo>`. The FT232R supports up to 3 MBaud. A synchronous FIFO interface with a 32 words buffer is provided. diff --git a/docs/IPCores/io/uart/uart_bclk.rst b/docs/IPCores/io/uart/uart_bclk.rst index 0d6381d9..c4e848c3 100644 --- a/docs/IPCores/io/uart/uart_bclk.rst +++ b/docs/IPCores/io/uart/uart_bclk.rst @@ -1,3 +1,8 @@ +.. _IP:uart_bclk: + +PoC.io.uart.bclk +################ + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:uart_bclk: - -uart_bclk -######### - .. TODO:: No documentation available. old comments: diff --git a/docs/IPCores/io/uart/uart_fifo.rst b/docs/IPCores/io/uart/uart_fifo.rst index 3f4f79c4..06d56bf3 100644 --- a/docs/IPCores/io/uart/uart_fifo.rst +++ b/docs/IPCores/io/uart/uart_fifo.rst @@ -1,3 +1,8 @@ +.. _IP:uart_fifo: + +PoC.io.uart.fifo +################ + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:uart_fifo: - -uart_fifo -######### - Small :abbr:`FIFO (first-in, first-out)` s are included in this module, if larger or asynchronous transmit / receive FIFOs are required, then they must be connected externally. diff --git a/docs/IPCores/io/uart/uart_ft245.rst b/docs/IPCores/io/uart/uart_ft245.rst index 739fe491..7ec4cb90 100644 --- a/docs/IPCores/io/uart/uart_ft245.rst +++ b/docs/IPCores/io/uart/uart_ft245.rst @@ -1,3 +1,8 @@ +.. _IP:uart_ft245: + +PoC.io.uart.ft245 +################# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:uart_ft245: - -uart_ft245 -########## - .. TODO:: No documentation available. diff --git a/docs/IPCores/io/uart/uart_rx.rst b/docs/IPCores/io/uart/uart_rx.rst index a6a954ca..90fba9c0 100644 --- a/docs/IPCores/io/uart/uart_rx.rst +++ b/docs/IPCores/io/uart/uart_rx.rst @@ -1,3 +1,8 @@ +.. _IP:uart_rx: + +PoC.io.uart.rx +############## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:uart_rx: - -uart_rx -####### - :abbr:`UART (Universal Asynchronous Receiver Transmitter)` Receiver: 1 Start + 8 Data + 1 Stop diff --git a/docs/IPCores/io/uart/uart_tx.rst b/docs/IPCores/io/uart/uart_tx.rst index a0f3d93d..5ec05da9 100644 --- a/docs/IPCores/io/uart/uart_tx.rst +++ b/docs/IPCores/io/uart/uart_tx.rst @@ -1,3 +1,8 @@ +.. _IP:uart_tx: + +PoC.io.uart.tx +############## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:uart_tx: - -uart_tx -####### - :abbr:`UART (Universal Asynchronous Receiver Transmitter)` Transmitter: 1 Start + 8 Data + 1 Stop diff --git a/docs/IPCores/io/vga/vga_phy.rst b/docs/IPCores/io/vga/vga_phy.rst index b8fa8a02..1e08bc4d 100644 --- a/docs/IPCores/io/vga/vga_phy.rst +++ b/docs/IPCores/io/vga/vga_phy.rst @@ -1,3 +1,8 @@ +.. _IP:vga_phy: + +PoC.io.vga.phy +############## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:vga_phy: - -vga_phy -####### - The clock frequency must be the same as used for the timing module. The number of color-bits per pixel can be configured with the generic diff --git a/docs/IPCores/io/vga/vga_phy_ch7301c.rst b/docs/IPCores/io/vga/vga_phy_ch7301c.rst index 63812466..fc82c28f 100644 --- a/docs/IPCores/io/vga/vga_phy_ch7301c.rst +++ b/docs/IPCores/io/vga/vga_phy_ch7301c.rst @@ -1,3 +1,8 @@ +.. _IP:vga_phy_ch7301c: + +PoC.io.vga.phy_ch7301c +###################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:vga_phy_ch7301c: - -vga_phy_ch7301c -############### - The clock frequency must be the same as used for the timing module, e.g., 25 MHZ for VGA 640x480. A phase-shifted clock must be provided: - clk0 : 0 degrees diff --git a/docs/IPCores/io/vga/vga_timing.rst b/docs/IPCores/io/vga/vga_timing.rst index 5626ce41..4cff541f 100644 --- a/docs/IPCores/io/vga/vga_timing.rst +++ b/docs/IPCores/io/vga/vga_timing.rst @@ -1,3 +1,8 @@ +.. _IP:vga_timing: + +PoC.io.vga.timing +################# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:vga_timing: - -vga_timing -########## - Configuration: -------------- MODE = 0: VGA mode with 640x480 pixels, 60 Hz, frequency(clk) ~ 25 MHz diff --git a/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst b/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst index 8e74a2a7..62ba441c 100644 --- a/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst +++ b/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst @@ -1,3 +1,8 @@ +.. _IP:ddr2_mem2mig_adapter_Spartan6: + +PoC.mem.ddr2.mem2mig_adapter_Spartan6 +##################################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ddr2_mem2mig_adapter_Spartan6: - -ddr2_mem2mig_adapter_Spartan6 -############################# - Adapter between the :ref:`PoC.Mem ` interface and the User Interface of the Xilinx MIG IP core for the Spartan-6 FPGA Memory Controller Block (MCB). The MCB can be configured to diff --git a/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst b/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst index 5d8cf0e1..f02332da 100644 --- a/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst +++ b/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst @@ -1,3 +1,8 @@ +.. _IP:ddr3_mem2mig_adapter_Series7: + +PoC.mem.ddr3.mem2mig_adapter_Series7 +#################################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ddr3_mem2mig_adapter_Series7: - -ddr3_mem2mig_adapter_Series7 -############################ - Adapter between the :ref:`PoC.Mem ` interface and the application interface ("app") of the Xilinx MIG IP core for 7-Series FPGAs. diff --git a/docs/IPCores/mem/lut/lut_Sine.rst b/docs/IPCores/mem/lut/lut_Sine.rst index d0c51703..20d21936 100644 --- a/docs/IPCores/mem/lut/lut_Sine.rst +++ b/docs/IPCores/mem/lut/lut_Sine.rst @@ -1,3 +1,8 @@ +.. _IP:lut_Sine: + +PoC.mem.lut.Sine +################ + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:lut_Sine: - -lut_Sine -######## - .. TODO:: No documentation available. diff --git a/docs/IPCores/mem/ocram/ocram_esdp.rst b/docs/IPCores/mem/ocram/ocram_esdp.rst index 6d102f95..e34c7bb5 100644 --- a/docs/IPCores/mem/ocram/ocram_esdp.rst +++ b/docs/IPCores/mem/ocram/ocram_esdp.rst @@ -1,3 +1,8 @@ +.. _IP:ocram_esdp: + +PoC.mem.ocram.esdp +################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ocram_esdp: - -ocram_esdp -########## - Inferring / instantiating enhanced simple dual-port memory, with: * dual clock, clock enable, diff --git a/docs/IPCores/mem/ocram/ocram_sdp.rst b/docs/IPCores/mem/ocram/ocram_sdp.rst index 4257ae7b..a55989eb 100644 --- a/docs/IPCores/mem/ocram/ocram_sdp.rst +++ b/docs/IPCores/mem/ocram/ocram_sdp.rst @@ -1,3 +1,8 @@ +.. _IP:ocram_sdp: + +PoC.mem.ocram.sdp +################# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ocram_sdp: - -ocram_sdp -######### - Inferring / instantiating simple dual-port memory, with: * dual clock, clock enable, diff --git a/docs/IPCores/mem/ocram/ocram_sdp_wf.rst b/docs/IPCores/mem/ocram/ocram_sdp_wf.rst index 4fa2f9c7..66561a39 100644 --- a/docs/IPCores/mem/ocram/ocram_sdp_wf.rst +++ b/docs/IPCores/mem/ocram/ocram_sdp_wf.rst @@ -1,3 +1,8 @@ +.. _IP:ocram_sdp_wf: + +PoC.mem.ocram.sdp_wf +#################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ocram_sdp_wf: - -ocram_sdp_wf -############ - Inferring / instantiating simple dual-port memory, with: * single clock, clock enable, diff --git a/docs/IPCores/mem/ocram/ocram_sp.rst b/docs/IPCores/mem/ocram/ocram_sp.rst index c8f392d9..8318520e 100644 --- a/docs/IPCores/mem/ocram/ocram_sp.rst +++ b/docs/IPCores/mem/ocram/ocram_sp.rst @@ -1,3 +1,8 @@ +.. _IP:ocram_sp: + +PoC.mem.ocram.sp +################ + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ocram_sp: - -ocram_sp -######## - Inferring / instantiating single port memory, with: * single clock, clock enable, diff --git a/docs/IPCores/mem/ocram/ocram_tdp.rst b/docs/IPCores/mem/ocram/ocram_tdp.rst index 18b0ef52..91bee648 100644 --- a/docs/IPCores/mem/ocram/ocram_tdp.rst +++ b/docs/IPCores/mem/ocram/ocram_tdp.rst @@ -1,3 +1,8 @@ +.. _IP:ocram_tdp: + +PoC.mem.ocram.tdp +################# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ocram_tdp: - -ocram_tdp -######### - Inferring / instantiating true dual-port memory, with: * dual clock, clock enable, diff --git a/docs/IPCores/mem/ocram/ocram_tdp_sim.rst b/docs/IPCores/mem/ocram/ocram_tdp_sim.rst index 64b9645d..050c0154 100644 --- a/docs/IPCores/mem/ocram/ocram_tdp_sim.rst +++ b/docs/IPCores/mem/ocram/ocram_tdp_sim.rst @@ -1,3 +1,8 @@ +.. _IP:ocram_tdp_sim: + +PoC.mem.ocram.tdp_sim +##################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ocram_tdp_sim: - -ocram_tdp_sim -############# - Simulation model for true dual-port memory, with: * dual clock, clock enable, diff --git a/docs/IPCores/mem/ocram/ocram_tdp_wf.rst b/docs/IPCores/mem/ocram/ocram_tdp_wf.rst index 130cade3..59f51b2a 100644 --- a/docs/IPCores/mem/ocram/ocram_tdp_wf.rst +++ b/docs/IPCores/mem/ocram/ocram_tdp_wf.rst @@ -1,3 +1,8 @@ +.. _IP:ocram_tdp_wf: + +PoC.mem.ocram.tdp_wf +#################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ocram_tdp_wf: - -ocram_tdp_wf -############ - Inferring / instantiating true dual-port memory, with: * single clock, clock enable, diff --git a/docs/IPCores/mem/ocrom/ocrom_dp.rst b/docs/IPCores/mem/ocrom/ocrom_dp.rst index e13bb88f..53f67d78 100644 --- a/docs/IPCores/mem/ocrom/ocrom_dp.rst +++ b/docs/IPCores/mem/ocrom/ocrom_dp.rst @@ -1,3 +1,8 @@ +.. _IP:ocrom_dp: + +PoC.mem.ocrom.dp +################ + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ocrom_dp: - -ocrom_dp -######## - Inferring / instantiating dual-port read-only memory, with: * dual clock, clock enable, diff --git a/docs/IPCores/mem/ocrom/ocrom_sp.rst b/docs/IPCores/mem/ocrom/ocrom_sp.rst index 68654cbd..ae2e4ed3 100644 --- a/docs/IPCores/mem/ocrom/ocrom_sp.rst +++ b/docs/IPCores/mem/ocrom/ocrom_sp.rst @@ -1,3 +1,8 @@ +.. _IP:ocrom_sp: + +PoC.mem.ocrom.sp +################ + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ocrom_sp: - -ocrom_sp -######## - Inferring / instantiating single-port read-only memory - single clock, clock enable diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst b/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst index 27104443..854dbf14 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst @@ -1,3 +1,8 @@ +.. _IP:sdram_ctrl_de0: + +PoC.mem.sdram.ctrl_de0 +###################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:sdram_ctrl_de0: - -sdram_ctrl_de0 -############## - Complete controller for ISSI SDR-SDRAM for Altera DE0 Board. SDRAM Device: IS42S16400F diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst b/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst index abeacbb4..4641c2eb 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst @@ -1,3 +1,8 @@ +.. _IP:sdram_ctrl_fsm: + +PoC.mem.sdram.ctrl_fsm +###################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:sdram_ctrl_fsm: - -sdram_ctrl_fsm -############## - This file contains the FSM as well as parts of the datapath. The board specific physical layer is defined in another file. diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst b/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst index eb144d93..8029a2d4 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst @@ -1,3 +1,8 @@ +.. _IP:sdram_ctrl_phy_de0: + +PoC.mem.sdram.ctrl_phy_de0 +########################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:sdram_ctrl_phy_de0: - -sdram_ctrl_phy_de0 -################## - Physical layer used by module :ref:`sdram_ctrl_de0 `. Instantiates input and output buffer components and adjusts the timing for diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst b/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst index 2ae8d48b..111958c1 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst @@ -1,3 +1,8 @@ +.. _IP:sdram_ctrl_phy_s3esk: + +PoC.mem.sdram.ctrl_phy_s3esk +############################ + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:sdram_ctrl_phy_s3esk: - -sdram_ctrl_phy_s3esk -#################### - Physical layer used by module :ref:`sdram_ctrl_s3esk `. Instantiates input and output buffer components and adjusts the timing for diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst b/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst index 8c6c5fa2..c4f927a2 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst @@ -1,3 +1,8 @@ +.. _IP:sdram_ctrl_s3esk: + +PoC.mem.sdram.ctrl_s3esk +######################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:sdram_ctrl_s3esk: - -sdram_ctrl_s3esk -################ - Controller for Micron DDR-SDRAM on Spartan-3E Starter Kit Board. SDRAM Device: MT46V32M16-6T diff --git a/docs/IPCores/misc/filter/filter_and.rst b/docs/IPCores/misc/filter/filter_and.rst index 0cdcfa33..3118b285 100644 --- a/docs/IPCores/misc/filter/filter_and.rst +++ b/docs/IPCores/misc/filter/filter_and.rst @@ -1,3 +1,8 @@ +.. _IP:filter_and: + +PoC.misc.filter.and +################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:filter_and: - -filter_and -########## - .. TODO:: No documentation available. diff --git a/docs/IPCores/misc/filter/filter_mean.rst b/docs/IPCores/misc/filter/filter_mean.rst index 2dcb4a61..b1d4b66a 100644 --- a/docs/IPCores/misc/filter/filter_mean.rst +++ b/docs/IPCores/misc/filter/filter_mean.rst @@ -1,3 +1,8 @@ +.. _IP:filter_mean: + +PoC.misc.filter.mean +#################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:filter_mean: - -filter_mean -########### - .. TODO:: No documentation available. diff --git a/docs/IPCores/misc/filter/filter_or.rst b/docs/IPCores/misc/filter/filter_or.rst index 376f887a..6d3151eb 100644 --- a/docs/IPCores/misc/filter/filter_or.rst +++ b/docs/IPCores/misc/filter/filter_or.rst @@ -1,3 +1,8 @@ +.. _IP:filter_or: + +PoC.misc.filter.or +################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:filter_or: - -filter_or -######### - .. TODO:: No documentation available. diff --git a/docs/IPCores/misc/gearbox/gearbox_down_cc.rst b/docs/IPCores/misc/gearbox/gearbox_down_cc.rst index eb9533d4..7c8384fe 100644 --- a/docs/IPCores/misc/gearbox/gearbox_down_cc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_down_cc.rst @@ -1,3 +1,8 @@ +.. _IP:gearbox_down_cc: + +PoC.misc.gearbox.down_cc +######################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:gearbox_down_cc: - -gearbox_down_cc -############### - This module provides a downscaling gearbox with a common clock (cc) interface. It perfoems a 'word' to 'byte' splitting. The default order is LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" and output "Out_Data" diff --git a/docs/IPCores/misc/gearbox/gearbox_down_dc.rst b/docs/IPCores/misc/gearbox/gearbox_down_dc.rst index 468765c7..18ff0e8f 100644 --- a/docs/IPCores/misc/gearbox/gearbox_down_dc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_down_dc.rst @@ -1,3 +1,8 @@ +.. _IP:gearbox_down_dc: + +PoC.misc.gearbox.down_dc +######################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:gearbox_down_dc: - -gearbox_down_dc -############### - This module provides a downscaling gearbox with a dependent clock (dc) interface. It perfoems a 'word' to 'byte' splitting. The default order is LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" is of clock domain diff --git a/docs/IPCores/misc/gearbox/gearbox_up_cc.rst b/docs/IPCores/misc/gearbox/gearbox_up_cc.rst index 92758f45..c059c90e 100644 --- a/docs/IPCores/misc/gearbox/gearbox_up_cc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_up_cc.rst @@ -1,3 +1,8 @@ +.. _IP:gearbox_up_cc: + +PoC.misc.gearbox.up_cc +###################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:gearbox_up_cc: - -gearbox_up_cc -############# - This module provides a downscaling gearbox with a common clock (cc) interface. It perfoems a 'byte' to 'word' collection. The default order is LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" and output "Out_Data" diff --git a/docs/IPCores/misc/gearbox/gearbox_up_dc.rst b/docs/IPCores/misc/gearbox/gearbox_up_dc.rst index c09146ee..36fc1365 100644 --- a/docs/IPCores/misc/gearbox/gearbox_up_dc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_up_dc.rst @@ -1,3 +1,8 @@ +.. _IP:gearbox_up_dc: + +PoC.misc.gearbox.up_dc +###################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:gearbox_up_dc: - -gearbox_up_dc -############# - This module provides a upscaling gearbox with a dependent clock (dc) interface. It perfoems a 'byte' to 'word' collection. The default order is LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" is of clock domain diff --git a/docs/IPCores/misc/misc_BitwidthConverter.rst b/docs/IPCores/misc/misc_BitwidthConverter.rst index 0b26e5bd..77a1d6b9 100644 --- a/docs/IPCores/misc/misc_BitwidthConverter.rst +++ b/docs/IPCores/misc/misc_BitwidthConverter.rst @@ -1,3 +1,8 @@ +.. _IP:misc_BitwidthConverter: + +PoC.misc.BitwidthConverter +########################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -15,12 +20,6 @@ * |gh-tb| :poctb:`Testbench ` -.. _IP:misc_BitwidthConverter: - -misc_BitwidthConverter -###################### - - .. rubric:: Entity Declaration: diff --git a/docs/IPCores/misc/misc_ByteAligner.rst b/docs/IPCores/misc/misc_ByteAligner.rst index b194faf1..3352d216 100644 --- a/docs/IPCores/misc/misc_ByteAligner.rst +++ b/docs/IPCores/misc/misc_ByteAligner.rst @@ -1,3 +1,8 @@ +.. _IP:misc_ByteAligner: + +PoC.misc.ByteAligner +#################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:misc_ByteAligner: - -misc_ByteAligner -################ - .. TODO:: No documentation available. diff --git a/docs/IPCores/misc/misc_Delay.rst b/docs/IPCores/misc/misc_Delay.rst index d8d61502..f4fd8571 100644 --- a/docs/IPCores/misc/misc_Delay.rst +++ b/docs/IPCores/misc/misc_Delay.rst @@ -1,3 +1,8 @@ +.. _IP:misc_Delay: + +PoC.misc.Delay +############## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:misc_Delay: - -misc_Delay -########## - .. TODO:: No documentation available. diff --git a/docs/IPCores/misc/misc_FrequencyMeasurement.rst b/docs/IPCores/misc/misc_FrequencyMeasurement.rst index 8a9baa99..abf4290a 100644 --- a/docs/IPCores/misc/misc_FrequencyMeasurement.rst +++ b/docs/IPCores/misc/misc_FrequencyMeasurement.rst @@ -1,3 +1,8 @@ +.. _IP:misc_FrequencyMeasurement: + +PoC.misc.FrequencyMeasurement +############################# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:misc_FrequencyMeasurement: - -misc_FrequencyMeasurement -######################### - This module counts 1 second in a reference timer at reference clock. This reference time is used to start and stop a timer at input clock. The counter value is the measured frequency in Hz. diff --git a/docs/IPCores/misc/misc_PulseTrain.rst b/docs/IPCores/misc/misc_PulseTrain.rst index 9ce65b40..461b75ed 100644 --- a/docs/IPCores/misc/misc_PulseTrain.rst +++ b/docs/IPCores/misc/misc_PulseTrain.rst @@ -1,3 +1,8 @@ +.. _IP:misc_PulseTrain: + +PoC.misc.PulseTrain +################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:misc_PulseTrain: - -misc_PulseTrain -############### - This module generates pulse trains. This module was written as a answer for a StackOverflow question: http://stackoverflow.com/questions/25783320 diff --git a/docs/IPCores/misc/misc_Sequencer.rst b/docs/IPCores/misc/misc_Sequencer.rst index c8f3c56e..907e0535 100644 --- a/docs/IPCores/misc/misc_Sequencer.rst +++ b/docs/IPCores/misc/misc_Sequencer.rst @@ -1,3 +1,8 @@ +.. _IP:misc_Sequencer: + +PoC.misc.Sequencer +################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:misc_Sequencer: - -misc_Sequencer -############## - .. TODO:: No documentation available. diff --git a/docs/IPCores/misc/misc_StrobeGenerator.rst b/docs/IPCores/misc/misc_StrobeGenerator.rst index 75529eeb..c7f80240 100644 --- a/docs/IPCores/misc/misc_StrobeGenerator.rst +++ b/docs/IPCores/misc/misc_StrobeGenerator.rst @@ -1,3 +1,8 @@ +.. _IP:misc_StrobeGenerator: + +PoC.misc.StrobeGenerator +######################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:misc_StrobeGenerator: - -misc_StrobeGenerator -#################### - .. TODO:: No documentation available. diff --git a/docs/IPCores/misc/misc_StrobeLimiter.rst b/docs/IPCores/misc/misc_StrobeLimiter.rst index 35e91499..d5fe5d23 100644 --- a/docs/IPCores/misc/misc_StrobeLimiter.rst +++ b/docs/IPCores/misc/misc_StrobeLimiter.rst @@ -1,3 +1,8 @@ +.. _IP:misc_StrobeLimiter: + +PoC.misc.StrobeLimiter +###################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:misc_StrobeLimiter: - -misc_StrobeLimiter -################## - .. TODO:: No documentation available. diff --git a/docs/IPCores/misc/misc_bit_lz.rst b/docs/IPCores/misc/misc_bit_lz.rst index 016101c4..61db582f 100644 --- a/docs/IPCores/misc/misc_bit_lz.rst +++ b/docs/IPCores/misc/misc_bit_lz.rst @@ -1,3 +1,8 @@ +.. _IP:misc_bit_lz: + +PoC.misc.bit_lz +############### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -15,12 +20,6 @@ * |gh-tb| :poctb:`Testbench ` -.. _IP:misc_bit_lz: - -misc_bit_lz -########### - - An LZ77-based bit stream compressor. Output Format diff --git a/docs/IPCores/misc/stat/stat_Average.rst b/docs/IPCores/misc/stat/stat_Average.rst index 9e782635..16367534 100644 --- a/docs/IPCores/misc/stat/stat_Average.rst +++ b/docs/IPCores/misc/stat/stat_Average.rst @@ -1,3 +1,8 @@ +.. _IP:stat_Average: + +PoC.misc.stat.Average +##################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:stat_Average: - -stat_Average -############ - .. TODO:: No documentation available. diff --git a/docs/IPCores/misc/stat/stat_Histogram.rst b/docs/IPCores/misc/stat/stat_Histogram.rst index 9c945b46..55c90d0e 100644 --- a/docs/IPCores/misc/stat/stat_Histogram.rst +++ b/docs/IPCores/misc/stat/stat_Histogram.rst @@ -1,3 +1,8 @@ +.. _IP:stat_Histogram: + +PoC.misc.stat.Histogram +####################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:stat_Histogram: - -stat_Histogram -############## - .. TODO:: No documentation available. diff --git a/docs/IPCores/misc/stat/stat_Maximum.rst b/docs/IPCores/misc/stat/stat_Maximum.rst index 4c57dffd..555e7f26 100644 --- a/docs/IPCores/misc/stat/stat_Maximum.rst +++ b/docs/IPCores/misc/stat/stat_Maximum.rst @@ -1,3 +1,8 @@ +.. _IP:stat_Maximum: + +PoC.misc.stat.Maximum +##################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:stat_Maximum: - -stat_Maximum -############ - .. TODO:: No documentation available. diff --git a/docs/IPCores/misc/stat/stat_Minimum.rst b/docs/IPCores/misc/stat/stat_Minimum.rst index f5591b28..b47d71a9 100644 --- a/docs/IPCores/misc/stat/stat_Minimum.rst +++ b/docs/IPCores/misc/stat/stat_Minimum.rst @@ -1,3 +1,8 @@ +.. _IP:stat_Minimum: + +PoC.misc.stat.Minimum +##################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:stat_Minimum: - -stat_Minimum -############ - .. TODO:: No documentation available. diff --git a/docs/IPCores/misc/sync/sync_Bits.rst b/docs/IPCores/misc/sync/sync_Bits.rst index 3eb3e8bb..9247b6d4 100644 --- a/docs/IPCores/misc/sync/sync_Bits.rst +++ b/docs/IPCores/misc/sync/sync_Bits.rst @@ -1,3 +1,8 @@ +.. _IP:sync_Bits: + +PoC.misc.sync.Bits +################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:sync_Bits: - -sync_Bits -######### - This module synchronizes multiple flag bits into clock-domain ``Clock``. The clock-domain boundary crossing is done by two synchronizer D-FFs. All bits are independent from each other. If a known vendor like Altera or Xilinx diff --git a/docs/IPCores/misc/sync/sync_Command.rst b/docs/IPCores/misc/sync/sync_Command.rst index e40fd791..33d68f71 100644 --- a/docs/IPCores/misc/sync/sync_Command.rst +++ b/docs/IPCores/misc/sync/sync_Command.rst @@ -1,3 +1,8 @@ +.. _IP:sync_Command: + +PoC.misc.sync.Command +##################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:sync_Command: - -sync_Command -############ - This module synchronizes a vector of bits from clock-domain ``Clock1`` to clock-domain ``Clock2``. The clock-domain boundary crossing is done by a change comparator, a T-FF, two synchronizer D-FFs and a reconstructive diff --git a/docs/IPCores/misc/sync/sync_Pulse.rst b/docs/IPCores/misc/sync/sync_Pulse.rst index 53ee6d34..36015518 100644 --- a/docs/IPCores/misc/sync/sync_Pulse.rst +++ b/docs/IPCores/misc/sync/sync_Pulse.rst @@ -1,3 +1,8 @@ +.. _IP:sync_Pulse: + +PoC.misc.sync.Pulse +################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:sync_Pulse: - -sync_Pulse -########## - This module synchronizes multiple pulsed bits into the clock-domain ``Clock``. The clock-domain boundary crossing is done by two synchronizer D-FFs. All bits are independent from each other. If a known vendor like Altera or Xilinx are diff --git a/docs/IPCores/misc/sync/sync_Reset.rst b/docs/IPCores/misc/sync/sync_Reset.rst index 7ef53d2b..aa6f170a 100644 --- a/docs/IPCores/misc/sync/sync_Reset.rst +++ b/docs/IPCores/misc/sync/sync_Reset.rst @@ -1,3 +1,8 @@ +.. _IP:sync_Reset: + +PoC.misc.sync.Reset +################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:sync_Reset: - -sync_Reset -########## - This module synchronizes an asynchronous reset signal to the clock ``Clock``. The ``Input`` can be asserted and de-asserted at any time. The ``Output`` is asserted asynchronously and de-asserted synchronously diff --git a/docs/IPCores/misc/sync/sync_Strobe.rst b/docs/IPCores/misc/sync/sync_Strobe.rst index 8f558df5..63751033 100644 --- a/docs/IPCores/misc/sync/sync_Strobe.rst +++ b/docs/IPCores/misc/sync/sync_Strobe.rst @@ -1,3 +1,8 @@ +.. _IP:sync_Strobe: + +PoC.misc.sync.Strobe +#################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:sync_Strobe: - -sync_Strobe -########### - This module synchronizes multiple high-active bits from clock-domain ``Clock1`` to clock-domain ``Clock2``. The clock-domain boundary crossing is done by a T-FF, two synchronizer D-FFs and a reconstructive XOR. A busy diff --git a/docs/IPCores/misc/sync/sync_Vector.rst b/docs/IPCores/misc/sync/sync_Vector.rst index ce164581..b963c1df 100644 --- a/docs/IPCores/misc/sync/sync_Vector.rst +++ b/docs/IPCores/misc/sync/sync_Vector.rst @@ -1,3 +1,8 @@ +.. _IP:sync_Vector: + +PoC.misc.sync.Vector +#################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:sync_Vector: - -sync_Vector -########### - This module synchronizes a vector of bits from clock-domain ``Clock1`` to clock-domain ``Clock2``. The clock-domain boundary crossing is done by a change comparator, a T-FF, two synchronizer D-FFs and a reconstructive diff --git a/docs/IPCores/net/arp/arp_BroadCast_Receiver.rst b/docs/IPCores/net/arp/arp_BroadCast_Receiver.rst index ef17cfc7..f59c31fd 100644 --- a/docs/IPCores/net/arp/arp_BroadCast_Receiver.rst +++ b/docs/IPCores/net/arp/arp_BroadCast_Receiver.rst @@ -1,3 +1,8 @@ +.. _IP:arp_BroadCast_Receiver: + +PoC.net.arp.BroadCast_Receiver +############################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arp_BroadCast_Receiver: - -arp_BroadCast_Receiver -###################### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/arp/arp_BroadCast_Requester.rst b/docs/IPCores/net/arp/arp_BroadCast_Requester.rst index 83f99dd1..99d68b0d 100644 --- a/docs/IPCores/net/arp/arp_BroadCast_Requester.rst +++ b/docs/IPCores/net/arp/arp_BroadCast_Requester.rst @@ -1,3 +1,8 @@ +.. _IP:arp_BroadCast_Requester: + +PoC.net.arp.BroadCast_Requester +############################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arp_BroadCast_Requester: - -arp_BroadCast_Requester -####################### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/arp/arp_Cache.rst b/docs/IPCores/net/arp/arp_Cache.rst index 3b6847f6..27dccbf0 100644 --- a/docs/IPCores/net/arp/arp_Cache.rst +++ b/docs/IPCores/net/arp/arp_Cache.rst @@ -1,3 +1,8 @@ +.. _IP:arp_Cache: + +PoC.net.arp.Cache +################# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arp_Cache: - -arp_Cache -######### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/arp/arp_IPPool.rst b/docs/IPCores/net/arp/arp_IPPool.rst index 950e2069..ad696224 100644 --- a/docs/IPCores/net/arp/arp_IPPool.rst +++ b/docs/IPCores/net/arp/arp_IPPool.rst @@ -1,3 +1,8 @@ +.. _IP:arp_IPPool: + +PoC.net.arp.IPPool +################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arp_IPPool: - -arp_IPPool -########## - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/arp/arp_Tester.rst b/docs/IPCores/net/arp/arp_Tester.rst index 23275a0c..c179f606 100644 --- a/docs/IPCores/net/arp/arp_Tester.rst +++ b/docs/IPCores/net/arp/arp_Tester.rst @@ -1,3 +1,8 @@ +.. _IP:arp_Tester: + +PoC.net.arp.Tester +################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arp_Tester: - -arp_Tester -########## - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/arp/arp_UniCast_Receiver.rst b/docs/IPCores/net/arp/arp_UniCast_Receiver.rst index 45f7f02a..98180b97 100644 --- a/docs/IPCores/net/arp/arp_UniCast_Receiver.rst +++ b/docs/IPCores/net/arp/arp_UniCast_Receiver.rst @@ -1,3 +1,8 @@ +.. _IP:arp_UniCast_Receiver: + +PoC.net.arp.UniCast_Receiver +############################ + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arp_UniCast_Receiver: - -arp_UniCast_Receiver -#################### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/arp/arp_UniCast_Responder.rst b/docs/IPCores/net/arp/arp_UniCast_Responder.rst index 2e7cf30d..ec4da49f 100644 --- a/docs/IPCores/net/arp/arp_UniCast_Responder.rst +++ b/docs/IPCores/net/arp/arp_UniCast_Responder.rst @@ -1,3 +1,8 @@ +.. _IP:arp_UniCast_Responder: + +PoC.net.arp.UniCast_Responder +############################# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arp_UniCast_Responder: - -arp_UniCast_Responder -##################### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/arp/arp_Wrapper.rst b/docs/IPCores/net/arp/arp_Wrapper.rst index 5c3c1490..58750f5a 100644 --- a/docs/IPCores/net/arp/arp_Wrapper.rst +++ b/docs/IPCores/net/arp/arp_Wrapper.rst @@ -1,3 +1,8 @@ +.. _IP:arp_Wrapper: + +PoC.net.arp.Wrapper +################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:arp_Wrapper: - -arp_Wrapper -########### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/eth/eth_GEMAC_GMII.rst b/docs/IPCores/net/eth/eth_GEMAC_GMII.rst index e9818312..59edd608 100644 --- a/docs/IPCores/net/eth/eth_GEMAC_GMII.rst +++ b/docs/IPCores/net/eth/eth_GEMAC_GMII.rst @@ -1,3 +1,8 @@ +.. _IP:eth_GEMAC_GMII: + +PoC.net.eth.GEMAC_GMII +###################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:eth_GEMAC_GMII: - -eth_GEMAC_GMII -############## - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/eth/eth_GEMAC_RX.rst b/docs/IPCores/net/eth/eth_GEMAC_RX.rst index 9f2bee35..a3a48f69 100644 --- a/docs/IPCores/net/eth/eth_GEMAC_RX.rst +++ b/docs/IPCores/net/eth/eth_GEMAC_RX.rst @@ -1,3 +1,8 @@ +.. _IP:Eth_GEMAC_RX: + +PoC.net.eth.GEMAC_RX +#################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:Eth_GEMAC_RX: - -Eth_GEMAC_RX -############ - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/eth/eth_GEMAC_TX.rst b/docs/IPCores/net/eth/eth_GEMAC_TX.rst index a49a63c8..5a8e6e45 100644 --- a/docs/IPCores/net/eth/eth_GEMAC_TX.rst +++ b/docs/IPCores/net/eth/eth_GEMAC_TX.rst @@ -1,3 +1,8 @@ +.. _IP:Eth_GEMAC_TX: + +PoC.net.eth.GEMAC_TX +#################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:Eth_GEMAC_TX: - -Eth_GEMAC_TX -############ - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/eth/eth_PHYController.rst b/docs/IPCores/net/eth/eth_PHYController.rst index 2338483a..45b6f121 100644 --- a/docs/IPCores/net/eth/eth_PHYController.rst +++ b/docs/IPCores/net/eth/eth_PHYController.rst @@ -1,3 +1,8 @@ +.. _IP:Eth_PHYController: + +PoC.net.eth.PHYController +######################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:Eth_PHYController: - -Eth_PHYController -################# - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst b/docs/IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst index 45ffe3de..9912b632 100644 --- a/docs/IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst +++ b/docs/IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst @@ -1,3 +1,8 @@ +.. _IP:Eth_PHYController_Marvell_88E1111: + +PoC.net.eth.PHYController_Marvell_88E1111 +######################################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:Eth_PHYController_Marvell_88E1111: - -Eth_PHYController_Marvell_88E1111 -################################# - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/eth/eth_Wrapper.rst b/docs/IPCores/net/eth/eth_Wrapper.rst index 233c03f2..aebdc49d 100644 --- a/docs/IPCores/net/eth/eth_Wrapper.rst +++ b/docs/IPCores/net/eth/eth_Wrapper.rst @@ -1,3 +1,8 @@ +.. _IP:Eth_Wrapper: + +PoC.net.eth.Wrapper +################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:Eth_Wrapper: - -Eth_Wrapper -########### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/icmpv4/icmpv4_RX.rst b/docs/IPCores/net/icmpv4/icmpv4_RX.rst index 7cf26dc4..74acdffa 100644 --- a/docs/IPCores/net/icmpv4/icmpv4_RX.rst +++ b/docs/IPCores/net/icmpv4/icmpv4_RX.rst @@ -1,3 +1,8 @@ +.. _IP:icmpv4_RX: + +PoC.net.icmpv4.RX +################# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:icmpv4_RX: - -icmpv4_RX -######### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/icmpv4/icmpv4_TX.rst b/docs/IPCores/net/icmpv4/icmpv4_TX.rst index 4e046d03..8ff373e7 100644 --- a/docs/IPCores/net/icmpv4/icmpv4_TX.rst +++ b/docs/IPCores/net/icmpv4/icmpv4_TX.rst @@ -1,3 +1,8 @@ +.. _IP:icmpv4_TX: + +PoC.net.icmpv4.TX +################# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:icmpv4_TX: - -icmpv4_TX -######### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst b/docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst index 2a493e69..268f394a 100644 --- a/docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst +++ b/docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst @@ -1,3 +1,8 @@ +.. _IP:icmpv4_Wrapper: + +PoC.net.icmpv4.Wrapper +###################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:icmpv4_Wrapper: - -icmpv4_Wrapper -############## - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/icmpv6/icmpv6_RX.rst b/docs/IPCores/net/icmpv6/icmpv6_RX.rst index c6f42734..e08c5751 100644 --- a/docs/IPCores/net/icmpv6/icmpv6_RX.rst +++ b/docs/IPCores/net/icmpv6/icmpv6_RX.rst @@ -1,3 +1,8 @@ +.. _IP:icmpv6_RX: + +PoC.net.icmpv6.RX +################# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:icmpv6_RX: - -icmpv6_RX -######### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/icmpv6/icmpv6_TX.rst b/docs/IPCores/net/icmpv6/icmpv6_TX.rst index 58e191fc..cf1b6bc6 100644 --- a/docs/IPCores/net/icmpv6/icmpv6_TX.rst +++ b/docs/IPCores/net/icmpv6/icmpv6_TX.rst @@ -1,3 +1,8 @@ +.. _IP:icmpv6_TX: + +PoC.net.icmpv6.TX +################# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:icmpv6_TX: - -icmpv6_TX -######### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst b/docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst index 467bd619..0c424ce0 100644 --- a/docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst +++ b/docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst @@ -1,3 +1,8 @@ +.. _IP:icmpv6_Wrapper: + +PoC.net.icmpv6.Wrapper +###################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:icmpv6_Wrapper: - -icmpv6_Wrapper -############## - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst b/docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst index 9e73d8bc..13779ba2 100644 --- a/docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst +++ b/docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst @@ -1,3 +1,8 @@ +.. _IP:ipv4_FrameLoopback: + +PoC.net.ipv4.FrameLoopback +########################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ipv4_FrameLoopback: - -ipv4_FrameLoopback -################## - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/ipv4/ipv4_RX.rst b/docs/IPCores/net/ipv4/ipv4_RX.rst index 9f9871cb..f665cd30 100644 --- a/docs/IPCores/net/ipv4/ipv4_RX.rst +++ b/docs/IPCores/net/ipv4/ipv4_RX.rst @@ -1,3 +1,8 @@ +.. _IP:ipv4_RX: + +PoC.net.ipv4.RX +############### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ipv4_RX: - -ipv4_RX -####### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/ipv4/ipv4_TX.rst b/docs/IPCores/net/ipv4/ipv4_TX.rst index 4659dd78..f0e4e333 100644 --- a/docs/IPCores/net/ipv4/ipv4_TX.rst +++ b/docs/IPCores/net/ipv4/ipv4_TX.rst @@ -1,3 +1,8 @@ +.. _IP:ipv4_TX: + +PoC.net.ipv4.TX +############### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ipv4_TX: - -ipv4_TX -####### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/ipv4/ipv4_Wrapper.rst b/docs/IPCores/net/ipv4/ipv4_Wrapper.rst index 74144807..6f9cf25d 100644 --- a/docs/IPCores/net/ipv4/ipv4_Wrapper.rst +++ b/docs/IPCores/net/ipv4/ipv4_Wrapper.rst @@ -1,3 +1,8 @@ +.. _IP:ipv4_Wrapper: + +PoC.net.ipv4.Wrapper +#################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ipv4_Wrapper: - -ipv4_Wrapper -############ - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst b/docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst index 2bb6f0be..0f2e6a9a 100644 --- a/docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst +++ b/docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst @@ -1,3 +1,8 @@ +.. _IP:ipv6_FrameLoopback: + +PoC.net.ipv6.FrameLoopback +########################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ipv6_FrameLoopback: - -ipv6_FrameLoopback -################## - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/ipv6/ipv6_RX.rst b/docs/IPCores/net/ipv6/ipv6_RX.rst index 86f13dfd..6a8a7bea 100644 --- a/docs/IPCores/net/ipv6/ipv6_RX.rst +++ b/docs/IPCores/net/ipv6/ipv6_RX.rst @@ -1,3 +1,8 @@ +.. _IP:ipv6_RX: + +PoC.net.ipv6.RX +############### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ipv6_RX: - -ipv6_RX -####### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/ipv6/ipv6_TX.rst b/docs/IPCores/net/ipv6/ipv6_TX.rst index 93de91d2..39ab179b 100644 --- a/docs/IPCores/net/ipv6/ipv6_TX.rst +++ b/docs/IPCores/net/ipv6/ipv6_TX.rst @@ -1,3 +1,8 @@ +.. _IP:ipv6_TX: + +PoC.net.ipv6.TX +############### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ipv6_TX: - -ipv6_TX -####### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/ipv6/ipv6_Wrapper.rst b/docs/IPCores/net/ipv6/ipv6_Wrapper.rst index 45d16817..7bce03cc 100644 --- a/docs/IPCores/net/ipv6/ipv6_Wrapper.rst +++ b/docs/IPCores/net/ipv6/ipv6_Wrapper.rst @@ -1,3 +1,8 @@ +.. _IP:ipv6_Wrapper: + +PoC.net.ipv6.Wrapper +#################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ipv6_Wrapper: - -ipv6_Wrapper -############ - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/mac/mac_FrameLoopback.rst b/docs/IPCores/net/mac/mac_FrameLoopback.rst index a93c36ab..13950b61 100644 --- a/docs/IPCores/net/mac/mac_FrameLoopback.rst +++ b/docs/IPCores/net/mac/mac_FrameLoopback.rst @@ -1,3 +1,8 @@ +.. _IP:mac_FrameLoopback: + +PoC.net.mac.FrameLoopback +######################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:mac_FrameLoopback: - -mac_FrameLoopback -################# - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst b/docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst index fd3aef19..a9d4decf 100644 --- a/docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst +++ b/docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst @@ -1,3 +1,8 @@ +.. _IP:mac_RX_DestMAC_Switch: + +PoC.net.mac.RX_DestMAC_Switch +############################# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:mac_RX_DestMAC_Switch: - -mac_RX_DestMAC_Switch -##################### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst b/docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst index ad03c8da..798b3c62 100644 --- a/docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst +++ b/docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst @@ -1,3 +1,8 @@ +.. _IP:mac_RX_SrcMAC_Filter: + +PoC.net.mac.RX_SrcMAC_Filter +############################ + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:mac_RX_SrcMAC_Filter: - -mac_RX_SrcMAC_Filter -#################### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/mac/mac_RX_Type_Switch.rst b/docs/IPCores/net/mac/mac_RX_Type_Switch.rst index 79208eef..405916ff 100644 --- a/docs/IPCores/net/mac/mac_RX_Type_Switch.rst +++ b/docs/IPCores/net/mac/mac_RX_Type_Switch.rst @@ -1,3 +1,8 @@ +.. _IP:mac_RX_Type_Switch: + +PoC.net.mac.RX_Type_Switch +########################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:mac_RX_Type_Switch: - -mac_RX_Type_Switch -################## - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst b/docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst index a25257b3..e1c35e1c 100644 --- a/docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst +++ b/docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst @@ -1,3 +1,8 @@ +.. _IP:mac_TX_DestMAC_Prepender: + +PoC.net.mac.TX_DestMAC_Prepender +################################ + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:mac_TX_DestMAC_Prepender: - -mac_TX_DestMAC_Prepender -######################## - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst b/docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst index a81234dc..3d2bf089 100644 --- a/docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst +++ b/docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst @@ -1,3 +1,8 @@ +.. _IP:mac_TX_SrcMAC_Prepender: + +PoC.net.mac.TX_SrcMAC_Prepender +############################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:mac_TX_SrcMAC_Prepender: - -mac_TX_SrcMAC_Prepender -####################### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/mac/mac_TX_Type_Prepender.rst b/docs/IPCores/net/mac/mac_TX_Type_Prepender.rst index dd74a017..cba4445c 100644 --- a/docs/IPCores/net/mac/mac_TX_Type_Prepender.rst +++ b/docs/IPCores/net/mac/mac_TX_Type_Prepender.rst @@ -1,3 +1,8 @@ +.. _IP:mac_TX_Type_Prepender: + +PoC.net.mac.TX_Type_Prepender +############################# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:mac_TX_Type_Prepender: - -mac_TX_Type_Prepender -##################### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/mac/mac_Wrapper.rst b/docs/IPCores/net/mac/mac_Wrapper.rst index a6f9bdff..b930cff8 100644 --- a/docs/IPCores/net/mac/mac_Wrapper.rst +++ b/docs/IPCores/net/mac/mac_Wrapper.rst @@ -1,3 +1,8 @@ +.. _IP:mac_Wrapper: + +PoC.net.mac.Wrapper +################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:mac_Wrapper: - -mac_Wrapper -########### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/ndp/ndp_DestinationCache.rst b/docs/IPCores/net/ndp/ndp_DestinationCache.rst index c86e6808..ea92da57 100644 --- a/docs/IPCores/net/ndp/ndp_DestinationCache.rst +++ b/docs/IPCores/net/ndp/ndp_DestinationCache.rst @@ -1,3 +1,8 @@ +.. _IP:ndp_DestinationCache: + +PoC.net.ndp.DestinationCache +############################ + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ndp_DestinationCache: - -ndp_DestinationCache -#################### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/ndp/ndp_FSMQuery.rst b/docs/IPCores/net/ndp/ndp_FSMQuery.rst index a410c634..22220f80 100644 --- a/docs/IPCores/net/ndp/ndp_FSMQuery.rst +++ b/docs/IPCores/net/ndp/ndp_FSMQuery.rst @@ -1,3 +1,8 @@ +.. _IP:ndp_FSMQuery: + +PoC.net.ndp.FSMQuery +#################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ndp_FSMQuery: - -ndp_FSMQuery -############ - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/ndp/ndp_NeighborCache.rst b/docs/IPCores/net/ndp/ndp_NeighborCache.rst index a5b30a5f..b1dd16ee 100644 --- a/docs/IPCores/net/ndp/ndp_NeighborCache.rst +++ b/docs/IPCores/net/ndp/ndp_NeighborCache.rst @@ -1,3 +1,8 @@ +.. _IP:ndp_NeighborCache: + +PoC.net.ndp.NeighborCache +######################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:ndp_NeighborCache: - -ndp_NeighborCache -################# - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/ndp/ndp_Wrapper.rst b/docs/IPCores/net/ndp/ndp_Wrapper.rst index 52a84c19..643a32c4 100644 --- a/docs/IPCores/net/ndp/ndp_Wrapper.rst +++ b/docs/IPCores/net/ndp/ndp_Wrapper.rst @@ -1,3 +1,8 @@ +.. _IP:NDP_Wrapper: + +PoC.net.ndp.Wrapper +################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:NDP_Wrapper: - -NDP_Wrapper -########### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/net_FrameChecksum.rst b/docs/IPCores/net/net_FrameChecksum.rst index dc86d61c..9bd64e5b 100644 --- a/docs/IPCores/net/net_FrameChecksum.rst +++ b/docs/IPCores/net/net_FrameChecksum.rst @@ -1,3 +1,8 @@ +.. _IP:net_FrameChecksum: + +PoC.net.FrameChecksum +##################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:net_FrameChecksum: - -net_FrameChecksum -################# - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/net_FrameLoopback.rst b/docs/IPCores/net/net_FrameLoopback.rst index b0a2f58c..9ea66a2a 100644 --- a/docs/IPCores/net/net_FrameLoopback.rst +++ b/docs/IPCores/net/net_FrameLoopback.rst @@ -1,3 +1,8 @@ +.. _IP:FrameLoopback: + +PoC.net.FrameLoopback +##################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:FrameLoopback: - -FrameLoopback -############# - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/net_FramePerformanceCounter.rst b/docs/IPCores/net/net_FramePerformanceCounter.rst index f71798f9..81fc24e1 100644 --- a/docs/IPCores/net/net_FramePerformanceCounter.rst +++ b/docs/IPCores/net/net_FramePerformanceCounter.rst @@ -1,3 +1,8 @@ +.. _IP:LocalLink_PerformanceCounter: + +PoC.net.FramePerformanceCounter +############################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -15,12 +20,6 @@ * |gh-tb| :poctb:`Testbench ` -.. _IP:LocalLink_PerformanceCounter: - -LocalLink_PerformanceCounter -############################ - - .. rubric:: Entity Declaration: diff --git a/docs/IPCores/net/stack/stack_UDPv4.rst b/docs/IPCores/net/stack/stack_UDPv4.rst index c343eef6..a9caf2ab 100644 --- a/docs/IPCores/net/stack/stack_UDPv4.rst +++ b/docs/IPCores/net/stack/stack_UDPv4.rst @@ -1,3 +1,8 @@ +.. _IP:stack_UDPv4: + +PoC.net.stack.UDPv4 +################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:stack_UDPv4: - -stack_UDPv4 -########### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/udp/udp_FrameLoopback.rst b/docs/IPCores/net/udp/udp_FrameLoopback.rst index fbffcfde..a2138d1e 100644 --- a/docs/IPCores/net/udp/udp_FrameLoopback.rst +++ b/docs/IPCores/net/udp/udp_FrameLoopback.rst @@ -1,3 +1,8 @@ +.. _IP:udp_FrameLoopback: + +PoC.net.udp.FrameLoopback +######################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:udp_FrameLoopback: - -udp_FrameLoopback -################# - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/udp/udp_RX.rst b/docs/IPCores/net/udp/udp_RX.rst index fa442a93..35c2a6d5 100644 --- a/docs/IPCores/net/udp/udp_RX.rst +++ b/docs/IPCores/net/udp/udp_RX.rst @@ -1,3 +1,8 @@ +.. _IP:udp_RX: + +PoC.net.udp.RX +############## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:udp_RX: - -udp_RX -###### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/udp/udp_TX.rst b/docs/IPCores/net/udp/udp_TX.rst index e1f42a3e..c8be4697 100644 --- a/docs/IPCores/net/udp/udp_TX.rst +++ b/docs/IPCores/net/udp/udp_TX.rst @@ -1,3 +1,8 @@ +.. _IP:udp_TX: + +PoC.net.udp.TX +############## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:udp_TX: - -udp_TX -###### - .. TODO:: No documentation available. diff --git a/docs/IPCores/net/udp/udp_Wrapper.rst b/docs/IPCores/net/udp/udp_Wrapper.rst index f522ed83..97d4cdb5 100644 --- a/docs/IPCores/net/udp/udp_Wrapper.rst +++ b/docs/IPCores/net/udp/udp_Wrapper.rst @@ -1,3 +1,8 @@ +.. _IP:udp_Wrapper: + +PoC.net.udp.Wrapper +################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:udp_Wrapper: - -udp_Wrapper -########### - .. TODO:: No documentation available. diff --git a/docs/IPCores/sort/sort_ExpireList.rst b/docs/IPCores/sort/sort_ExpireList.rst index 06d23708..4b46c28d 100644 --- a/docs/IPCores/sort/sort_ExpireList.rst +++ b/docs/IPCores/sort/sort_ExpireList.rst @@ -1,3 +1,8 @@ +.. _IP:list_expire: + +PoC.sort.ExpireList +################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:list_expire: - -list_expire -########### - .. TODO:: No documentation available. diff --git a/docs/IPCores/sort/sort_InsertSort.rst b/docs/IPCores/sort/sort_InsertSort.rst index ae1e9db8..4616c485 100644 --- a/docs/IPCores/sort/sort_InsertSort.rst +++ b/docs/IPCores/sort/sort_InsertSort.rst @@ -1,3 +1,8 @@ +.. _IP:list_lru_systolic: + +PoC.sort.InsertSort +################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:list_lru_systolic: - -list_lru_systolic -################# - .. TODO:: No documentation available. diff --git a/docs/IPCores/sort/sort_LeastFrequentlyUsed.rst b/docs/IPCores/sort/sort_LeastFrequentlyUsed.rst index 29dbe53d..14227dff 100644 --- a/docs/IPCores/sort/sort_LeastFrequentlyUsed.rst +++ b/docs/IPCores/sort/sort_LeastFrequentlyUsed.rst @@ -1,3 +1,8 @@ +.. _IP:sort_LeastFrequentlyUsed: + +PoC.sort.LeastFrequentlyUsed +############################ + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:sort_LeastFrequentlyUsed: - -sort_LeastFrequentlyUsed -######################## - .. TODO:: No documentation available. diff --git a/docs/IPCores/sort/sort_lru_cache.rst b/docs/IPCores/sort/sort_lru_cache.rst index c56bbb1f..b97b72c2 100644 --- a/docs/IPCores/sort/sort_lru_cache.rst +++ b/docs/IPCores/sort/sort_lru_cache.rst @@ -1,3 +1,8 @@ +.. _IP:sort_lru_cache: + +PoC.sort.lru_cache +################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:sort_lru_cache: - -sort_lru_cache -############## - This is an optimized implementation of ``sort_lru_list`` to be used for caches. Only keys are stored within this list, and these keys are the index of the cache lines. The list initially contains all indizes from 0 to ELEMENTS-1. diff --git a/docs/IPCores/sort/sort_lru_list.rst b/docs/IPCores/sort/sort_lru_list.rst index dbc00620..f61b148f 100644 --- a/docs/IPCores/sort/sort_lru_list.rst +++ b/docs/IPCores/sort/sort_lru_list.rst @@ -1,3 +1,8 @@ +.. _IP:sort_lru_list: + +PoC.sort.lru_list +################# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:sort_lru_list: - -sort_lru_list -############# - List storing ``(key, value)`` pairs. The least-recently inserted pair is outputed on ``DataOut`` if ``Valid = '1'``. If ``Valid = '0'``, then the list empty. diff --git a/docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst b/docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst index 433dd431..58274b6d 100644 --- a/docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst +++ b/docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst @@ -1,3 +1,8 @@ +.. _IP:sortnet_BitonicSort: + +PoC.sort.sortnet.BitonicSort +############################ + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:sortnet_BitonicSort: - -sortnet_BitonicSort -################### - This sorting network uses the *bitonic sort* algorithm. .. image:: /_static/sort/sortnet/sortnet_BitonicSort.* diff --git a/docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst b/docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst index 089fcd40..eaeb3c3f 100644 --- a/docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst +++ b/docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst @@ -1,3 +1,8 @@ +.. _IP:sortnet_MergeSort_Streamed: + +PoC.sort.sortnet.MergeSort_Streamed +################################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:sortnet_MergeSort_Streamed: - -sortnet_MergeSort_Streamed -########################## - .. TODO:: No documentation available. diff --git a/docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst b/docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst index c8e75728..53ff3811 100644 --- a/docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst +++ b/docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst @@ -1,3 +1,8 @@ +.. _IP:sortnet_OddEvenMergeSort: + +PoC.sort.sortnet.OddEvenMergeSort +################################# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:sortnet_OddEvenMergeSort: - -sortnet_OddEvenMergeSort -######################## - .. TODO:: No documentation available. diff --git a/docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst b/docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst index 8ef03011..3b27af41 100644 --- a/docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst +++ b/docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst @@ -1,3 +1,8 @@ +.. _IP:sortnet_OddEvenSort: + +PoC.sort.sortnet.OddEvenSort +############################ + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:sortnet_OddEvenSort: - -sortnet_OddEvenSort -################### - .. TODO:: No documentation available. diff --git a/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst index 0eb96718..a9330679 100644 --- a/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst +++ b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst @@ -1,3 +1,8 @@ +.. _IP:sortnet_Stream_Adapter: + +PoC.sort.sortnet.Stream_Adapter +############################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:sortnet_Stream_Adapter: - -sortnet_Stream_Adapter -###################### - .. TODO:: No documentation available. diff --git a/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst index cb3dd294..3043097c 100644 --- a/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst +++ b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst @@ -1,3 +1,8 @@ +.. _IP:sortnet_Stream_Adapter2: + +PoC.sort.sortnet.Stream_Adapter2 +################################ + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:sortnet_Stream_Adapter2: - -sortnet_Stream_Adapter2 -####################### - .. TODO:: No documentation available. diff --git a/docs/IPCores/sort/sortnet/sortnet_Transform.rst b/docs/IPCores/sort/sortnet/sortnet_Transform.rst index b954a50e..cbb43a5f 100644 --- a/docs/IPCores/sort/sortnet/sortnet_Transform.rst +++ b/docs/IPCores/sort/sortnet/sortnet_Transform.rst @@ -1,3 +1,8 @@ +.. _IP:sortnet_Transform: + +PoC.sort.sortnet.Transform +########################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:sortnet_Transform: - -sortnet_Transform -################# - .. TODO:: No documentation available. diff --git a/docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst b/docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst index 328b9b7e..5d9d2544 100644 --- a/docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst +++ b/docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst @@ -1,3 +1,8 @@ +.. _IP:reconfig_icap_fsm: + +PoC.xil.reconfig.icap_fsm +######################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:reconfig_icap_fsm: - -reconfig_icap_fsm -################# - This module parses the data stream to the Xilinx "Internal Configuration Access Port" (ICAP) primitives to generate control signals. Tested on: diff --git a/docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst b/docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst index e93e4843..3bbfba70 100644 --- a/docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst +++ b/docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst @@ -1,3 +1,8 @@ +.. _IP:reconfig_icap_wrapper: + +PoC.xil.reconfig.icap_wrapper +############################# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:reconfig_icap_wrapper: - -reconfig_icap_wrapper -##################### - This module was designed to connect the Xilinx "Internal Configuration Access Port" (ICAP) to a PCIe endpoint on a Dini board. Tested on: diff --git a/docs/IPCores/xil/xil_BSCAN.rst b/docs/IPCores/xil/xil_BSCAN.rst index 1eb64cc8..77c31e1d 100644 --- a/docs/IPCores/xil/xil_BSCAN.rst +++ b/docs/IPCores/xil/xil_BSCAN.rst @@ -1,3 +1,8 @@ +.. _IP:xil_BSCAN: + +PoC.xil.BSCAN +############# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:xil_BSCAN: - -xil_BSCAN -######### - This module wraps Xilinx "Boundary Scan" (JTAG) primitives in a generic module. |br| Supported devices are: diff --git a/docs/IPCores/xil/xil_ChipScopeICON.rst b/docs/IPCores/xil/xil_ChipScopeICON.rst index d0d9e912..924e0561 100644 --- a/docs/IPCores/xil/xil_ChipScopeICON.rst +++ b/docs/IPCores/xil/xil_ChipScopeICON.rst @@ -1,3 +1,8 @@ +.. _IP:xil_ChipScopeICON: + +PoC.xil.ChipScopeICON +##################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:xil_ChipScopeICON: - -xil_ChipScopeICON -################# - This module wraps 15 ChipScope ICON IP core netlists generated from ChipScope ICON xco files. The generic parameter ``PORTS`` selects the apropriate ICON instance with 1 to 15 ICON ``ControlBus`` ports. Each ``ControlBus`` port is diff --git a/docs/IPCores/xil/xil_DRP_BusMux.rst b/docs/IPCores/xil/xil_DRP_BusMux.rst index 9f0ffa38..5f2182e7 100644 --- a/docs/IPCores/xil/xil_DRP_BusMux.rst +++ b/docs/IPCores/xil/xil_DRP_BusMux.rst @@ -1,3 +1,8 @@ +.. _IP:xil_DRP_BusMux: + +PoC.xil.DRP_BusMux +################## + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:xil_DRP_BusMux: - -xil_DRP_BusMux -############## - .. TODO:: No documentation available. diff --git a/docs/IPCores/xil/xil_DRP_BusSync.rst b/docs/IPCores/xil/xil_DRP_BusSync.rst index d405f302..431dfbe1 100644 --- a/docs/IPCores/xil/xil_DRP_BusSync.rst +++ b/docs/IPCores/xil/xil_DRP_BusSync.rst @@ -1,3 +1,8 @@ +.. _IP:xil_DRP_BusSync: + +PoC.xil.DRP_BusSync +################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:xil_DRP_BusSync: - -xil_DRP_BusSync -############### - .. TODO:: No documentation available. diff --git a/docs/IPCores/xil/xil_ICAP.rst b/docs/IPCores/xil/xil_ICAP.rst index 2df83a46..4a7bcc27 100644 --- a/docs/IPCores/xil/xil_ICAP.rst +++ b/docs/IPCores/xil/xil_ICAP.rst @@ -1,3 +1,8 @@ +.. _IP:xil_ICAP: + +PoC.xil.ICAP +############ + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:xil_ICAP: - -xil_ICAP -######## - This module wraps Xilinx "Internal Configuration Access Port" (ICAP) primitives in a generic module. |br| Supported devices are: diff --git a/docs/IPCores/xil/xil_Reconfigurator.rst b/docs/IPCores/xil/xil_Reconfigurator.rst index 3d994dae..f1256b3f 100644 --- a/docs/IPCores/xil/xil_Reconfigurator.rst +++ b/docs/IPCores/xil/xil_Reconfigurator.rst @@ -1,3 +1,8 @@ +.. _IP:xil_Reconfigurator: + +PoC.xil.Reconfigurator +###################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:xil_Reconfigurator: - -xil_Reconfigurator -################## - Many complex primitives in a Xilinx device offer a Dynamic Reconfiguration Port (DRP) to reconfigure a primitive at runtime without reconfiguring the whole FPGA. diff --git a/docs/IPCores/xil/xil_SystemMonitor.rst b/docs/IPCores/xil/xil_SystemMonitor.rst index 28781e9a..232e2a8c 100644 --- a/docs/IPCores/xil/xil_SystemMonitor.rst +++ b/docs/IPCores/xil/xil_SystemMonitor.rst @@ -1,3 +1,8 @@ +.. _IP:xil_SystemMonitor: + +PoC.xil.SystemMonitor +##################### + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:xil_SystemMonitor: - -xil_SystemMonitor -################# - This module generates a PWM signal for a 3-pin (transistor controlled) or 4-pin fan header. The FPGAs temperature is read from device specific system monitors (normal, user temperature, over temperature). diff --git a/docs/IPCores/xil/xil_SystemMonitor_Series7.rst b/docs/IPCores/xil/xil_SystemMonitor_Series7.rst index 4c19aa6f..f67f6813 100644 --- a/docs/IPCores/xil/xil_SystemMonitor_Series7.rst +++ b/docs/IPCores/xil/xil_SystemMonitor_Series7.rst @@ -1,3 +1,8 @@ +.. _IP:xil_SystemMonitor_Series7: + +PoC.xil.SystemMonitor_Series7 +############################# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:xil_SystemMonitor_Series7: - -xil_SystemMonitor_Series7 -######################### - This module wraps a Series-7 XADC to report if preconfigured temperature values are overrun. The XADC was formerly known as "System Monitor". diff --git a/docs/IPCores/xil/xil_SystemMonitor_Virtex6.rst b/docs/IPCores/xil/xil_SystemMonitor_Virtex6.rst index 86eae81b..41363b27 100644 --- a/docs/IPCores/xil/xil_SystemMonitor_Virtex6.rst +++ b/docs/IPCores/xil/xil_SystemMonitor_Virtex6.rst @@ -1,3 +1,8 @@ +.. _IP:xil_SystemMonitor_Virtex6: + +PoC.xil.SystemMonitor_Virtex6 +############################# + .. only:: html .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png @@ -14,12 +19,6 @@ * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - -.. _IP:xil_SystemMonitor_Virtex6: - -xil_SystemMonitor_Virtex6 -######################### - This module wraps a Virtex-6 System Monitor primitive to report if preconfigured temperature values are overrun. diff --git a/docs/conf.py b/docs/conf.py index 731c3baa..d6491cf6 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -29,7 +29,7 @@ # -- General configuration ------------------------------------------------ # If your documentation needs a minimal Sphinx version, state it here. -needs_sphinx = '1.4.8' +needs_sphinx = '1.4.9' # Add any Sphinx extension module names here, as strings. They can be # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom diff --git a/docs/poc.py b/docs/poc.py index 96ca0510..9e5232c9 100644 --- a/docs/poc.py +++ b/docs/poc.py @@ -48,6 +48,7 @@ class SourceFile: def __init__(self, entitySourceCodeRange): #, entityName, entitySourceCodeRange, summary, description, seeAlso): self.File = entitySourceCodeRange.SourceFile self.EntityName = "" # entityName + self.EntityFullName = "" # entityName self.EntitySourceCodeRange = entitySourceCodeRange self.Authors = [] self.Summary = "" # summary @@ -124,7 +125,8 @@ def writeReST(self, sourceFile): outputContent = self.templateContent.format( EntityName=sourceFile.EntityName, - EntityNameUnderline="#" * len(sourceFile.EntityName), + EntityFullName=sourceFile.EntityFullName, + EntityNameUnderline="#" * len(sourceFile.EntityFullName), EntityDescription=sourceFile.Description, EntityFilePath=relSourceFile.as_posix(), EntityDeclarationFromTo="{0}-{1}".format(sourceFile.EntitySourceCodeRange.StartRow, sourceFile.EntitySourceCodeRange.EndRow), @@ -230,11 +232,12 @@ class State(Enum): # Construct Result Object result = SourceFile(SourceCodeRange(sourceFile, 0, 0)) - result.Authors = [author for author in sections['Authors'].splitlines()] - result.Summary = sections['Entity'] - result.Description = sections['Description'] - result.SeeAlso = sections['SeeAlso'] - result.EntityName = entityName + result.Authors = [author for author in sections['Authors'].splitlines()] + result.Summary = sections['Entity'] + result.Description = sections['Description'] + result.SeeAlso = sections['SeeAlso'] + result.EntityName = entityName + result.EntityFullName = "PoC." + ".".join(sourceFile.parts[2:-1]) + "." + sourceFile.stem[len(sourceFile.parts[-2])+1:] result.EntitySourceCodeRange.StartRow = entityStartLine result.EntitySourceCodeRange.EndRow = entityEndLine return result diff --git a/src/io/ddrio/ddrio_in.vhdl b/src/io/ddrio/ddrio_in.vhdl index e2fed10d..a67e7edc 100644 --- a/src/io/ddrio/ddrio_in.vhdl +++ b/src/io/ddrio/ddrio_in.vhdl @@ -20,31 +20,23 @@ -- .. wavedrom:: -- -- { signal: [ --- {name: 'clk', wave: 'H.L.H.L.H.L.H.L.H'}, --- {name: 'pad', wave: 'x2.3.4.5.2.3.x...', data: ['0', '1', '2', '3', '4', '5'], node: '.a.b.c.d.e.f...'}, --- {name: 'DataIn_low', wave: 'x...2...4...2...x', data: ['0', '2', '4'], node: '....k...m...o..'}, --- {name: 'DataIn_high', wave: 'x...3...5...3...x', data: ['1', '3', '5'], node: '....l...n...p..'} +-- ['DataIn', +-- {name: 'ClockIn', wave: 'L.H.L.H.L.H.L.H.L.'}, +-- {name: 'ClockInEnable', wave: '01............0...'}, +-- {name: 'DataIn_low', wave: 'x.....2...4...x...', data: ['0', '2'], node: '......u...w.'}, +-- {name: 'DataIn_high', wave: 'x.....3...5...x...', data: ['1', '3'], node: '......v...x.'} -- ], --- edge: ['a|->k', 'b|->l', 'c|->m', 'd|->n', 'e|->o', 'f|->p'], +-- {name: 'Pad', wave: 'x2.3.4.5.x........', data: ['0', '1', '2', '3'], node: '.a.b.c.d.....'}, +-- ], +-- edge: ['a~>u', 'b~>v', 'c~>w', 'd~>x'], -- foot: { -- text: ['tspan', --- ['tspan', {'font-weight': 'bold'}, 'PoC.io.ddrio.in'], --- ' -- DDR Data Input sampled from pad.' +-- ['tspan', {'font-weight': 'bold'}, 'PoC.io.ddrio.inout'], +-- ' -- DDR Data Input/Output sampled from pad.' -- ] -- } -- } -- --- .. only:: latex --- --- .. code-block:: none --- __ ____ ____ __ --- Clock |____| |____| |____| --- Pad < 0 >< 1 >< 2 >< 3 >< 4 >< 5 > --- DataIn_low ... >< 0 >< 2 >< --- DataIn_high ... >< 1 >< 3 >< --- --- < i > is the value of the i-th data bit on the line. --- -- After power-up, the output ports ``DataIn_high`` and ``DataIn_low`` both equal -- INIT_VALUE. -- diff --git a/src/io/ddrio/ddrio_inout.vhdl b/src/io/ddrio/ddrio_inout.vhdl index 24806b2e..dcff53a5 100644 --- a/src/io/ddrio/ddrio_inout.vhdl +++ b/src/io/ddrio/ddrio_inout.vhdl @@ -26,22 +26,41 @@ -- the falling edge directly before this rising edge. Thus sampling starts with -- the falling edge of the clock as depicted in the following waveform. -- --- .. code-block:: none +-- .. wavedrom:: -- --- __ ____ ____ __ --- Clock |____| |____| |____| --- Pad < 0 >< 1 >< 2 >< 3 >< 4 >< 5 > --- DataIn_low ... >< 0 >< 2 >< --- DataIn_high ... >< 1 >< 3 >< --- --- < i > is the value of the i-th data bit on the line. +-- { signal: [ +-- ['DataOut', +-- {name: 'ClockOut', wave: 'LH.L.H.L.H.L.H.L.H.L.H.'}, +-- {name: 'ClockOutEnable', wave: '0..1...................'}, +-- {name: 'OutputEnable', wave: '0.......1.......0......'}, +-- {name: 'DataOut_low', wave: 'x.......2...4...x......', data: ['4', '6'], node: '........k...m...o..'}, +-- {name: 'DataOut_high', wave: 'x.......3...5...x......', data: ['5', '7'], node: '........l...n...p..'} +-- ], +-- {}, +-- {name: 'Pad', wave: 'x2.3.4.5.z...2.3.4.5.z.', data: ['0', '1', '2', '3', '4', '5', '6', '7'], node: '.a.b.c.d.....e.f.g.h.'}, +-- {}, +-- ['DataIn', +-- {name: 'ClockIn', wave: 'L.H.L.H.L.H.L.H.L.H.L.H'}, +-- {name: 'ClockInEnable', wave: '01.......0.............'}, +-- {name: 'DataIn_low', wave: 'x.....2...4...z...2...4', data: ['0', '2', '4'], node: '......u...w.......y..'}, +-- {name: 'DataIn_high', wave: 'x.....3...5...z...3...5', data: ['1', '3', '5'], node: '......v...x.......z..'} +-- ] +-- ], +-- edge: ['a~>u', 'b~>v', 'c~>w', 'd~>x', 'k~>e', 'l~>f', 'm~>g', 'n~>h', 'e~>y', 'f~>z'], +-- foot: { +-- text: ['tspan', +-- ['tspan', {'font-weight': 'bold'}, 'PoC.io.ddrio.inout'], +-- ' -- DDR Data Input/Output sampled from pad.' +-- ] +-- } +-- } -- -- ``Pad`` must be connected to a PAD because FPGAs only have these registers in -- IOBs. -- -- License: -- ============================================================================= --- Copyright 2007-2015 Technische Universitaet Dresden - Germany, +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/src/io/ddrio/ddrio_out.vhdl b/src/io/ddrio/ddrio_out.vhdl index 77c7874b..a93e8161 100644 --- a/src/io/ddrio/ddrio_out.vhdl +++ b/src/io/ddrio/ddrio_out.vhdl @@ -23,6 +23,28 @@ -- If ``NO_OUTPUT_ENABLE = false`` then output is disabled after power-up. -- If ``NO_OUTPUT_ENABLE = true`` then output after power-up equals ``INIT_VALUE``. -- +-- .. wavedrom:: +-- +-- { signal: [ +-- ['DataOut', +-- {name: 'ClockOut', wave: 'L.H.L.H.L.H.L.H.'}, +-- {name: 'ClockOutEnable', wave: '01...........0..'}, +-- {name: 'OutputEnable', wave: '01.......0......'}, +-- {name: 'DataOut_low', wave: 'x2...4...x......', data: ['0', '2'], node: '.k...m'}, +-- {name: 'DataOut_high', wave: 'x3...5...x......', data: ['1', '3'], node: '.l...n'} +-- ], +-- {}, +-- {name: 'Pad', wave: 'x.....2.3.4.5.z.', data: ['0', '1', '2', '3'], node: '......a.b.c.d.'}, +-- ], +-- edge: ['k~>a', 'l~>b', 'm~>c', 'n~>d'], +-- foot: { +-- text: ['tspan', +-- ['tspan', {'font-weight': 'bold'}, 'PoC.io.ddrio.out'], +-- ' -- DDR Data Output sampled from pad.' +-- ] +-- } +-- } +-- -- ``Pad`` must be connected to a PAD because FPGAs only have these registers in -- IOBs. -- diff --git a/tools/ReadTheDocs/requirements.txt b/tools/ReadTheDocs/requirements.txt index 66263f6c..ba27718e 100644 --- a/tools/ReadTheDocs/requirements.txt +++ b/tools/ReadTheDocs/requirements.txt @@ -1,5 +1,5 @@ -r ../../requirements.txt -sphinx>=1.4.8 +sphinx>=1.4.9 sphinxcontrib-autoprogram>=0.1.3 #sphinxcontrib-actdiag>=0.8.5 #sphinxcontrib-seqdiag>=0.8.5 From 2cbd7bf458aa5ea06c315d8eaa2267f65b546fee Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 24 Nov 2016 01:15:42 +0100 Subject: [PATCH 78/97] Fixed markup in some VHDL files. --- docs/IPCores/arith/arith_addw.rst | 29 ++++++++++--------- docs/IPCores/arith/arith_carrychain_inc.rst | 4 +-- docs/IPCores/misc/gearbox/gearbox_down_cc.rst | 10 +++---- docs/IPCores/misc/gearbox/gearbox_down_dc.rst | 14 ++++----- docs/IPCores/misc/gearbox/gearbox_up_cc.rst | 10 +++---- docs/IPCores/misc/gearbox/gearbox_up_dc.rst | 16 +++++----- src/arith/arith_addw.vhdl | 27 ++++++++--------- src/arith/arith_carrychain_inc.vhdl | 4 +-- src/misc/gearbox/gearbox_down_cc.vhdl | 10 +++---- src/misc/gearbox/gearbox_down_dc.vhdl | 14 ++++----- src/misc/gearbox/gearbox_up_cc.vhdl | 10 +++---- src/misc/gearbox/gearbox_up_dc.vhdl | 16 +++++----- 12 files changed, 83 insertions(+), 81 deletions(-) diff --git a/docs/IPCores/arith/arith_addw.rst b/docs/IPCores/arith/arith_addw.rst index 857d0123..b6884c8f 100644 --- a/docs/IPCores/arith/arith_addw.rst +++ b/docs/IPCores/arith/arith_addw.rst @@ -19,21 +19,22 @@ PoC.arith.addw * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - Implements wide addition providing several options all based - on an adaptation of a carry-select approach. +Implements wide addition providing several options all based +on an adaptation of a carry-select approach. - References: - * Hong Diep Nguyen and Bogdan Pasca and Thomas B. Preusser: - FPGA-Specific Arithmetic Optimizations of Short-Latency Adders, - FPL 2011. - -> ARCH: AAM, CAI, CCA - -> SKIPPING: CCC +References: - * Marcin Rogawski, Kris Gaj and Ekawat Homsirikamol: - A Novel Modular Adder for One Thousand Bits and More - Using Fast Carry Chains of Modern FPGAs, FPL 2014. - -> ARCH: PAI - -> SKIPPING: PPN_KS, PPN_BK +* Hong Diep Nguyen and Bogdan Pasca and Thomas B. Preusser: + FPGA-Specific Arithmetic Optimizations of Short-Latency Adders, + FPL 2011. + -> ARCH: AAM, CAI, CCA + -> SKIPPING: CCC + +* Marcin Rogawski, Kris Gaj and Ekawat Homsirikamol: + A Novel Modular Adder for One Thousand Bits and More + Using Fast Carry Chains of Modern FPGAs, FPL 2014. + -> ARCH: PAI + -> SKIPPING: PPN_KS, PPN_BK @@ -43,7 +44,7 @@ PoC.arith.addw :language: vhdl :tab-width: 2 :linenos: - :lines: 53-70 + :lines: 54-71 diff --git a/docs/IPCores/arith/arith_carrychain_inc.rst b/docs/IPCores/arith/arith_carrychain_inc.rst index 19a28b35..aeb6eedd 100644 --- a/docs/IPCores/arith/arith_carrychain_inc.rst +++ b/docs/IPCores/arith/arith_carrychain_inc.rst @@ -19,9 +19,9 @@ PoC.arith.carrychain_inc * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - This is a generic carry-chain abstraction for increment by one operations. +This is a generic carry-chain abstraction for increment by one operations. - Y <= X + (0...0) & Cin +Y <= X + (0...0) & Cin diff --git a/docs/IPCores/misc/gearbox/gearbox_down_cc.rst b/docs/IPCores/misc/gearbox/gearbox_down_cc.rst index 7c8384fe..72eb096f 100644 --- a/docs/IPCores/misc/gearbox/gearbox_down_cc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_down_cc.rst @@ -19,11 +19,11 @@ PoC.misc.gearbox.down_cc * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - This module provides a downscaling gearbox with a common clock (cc) - interface. It perfoems a 'word' to 'byte' splitting. The default order is - LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" and output "Out_Data" - are of the same clock domain "Clock". Optional input and output registers - can be added by enabling (ADD_***PUT_REGISTERS = TRUE). +This module provides a downscaling gearbox with a common clock (cc) +interface. It perfoems a 'word' to 'byte' splitting. The default order is +LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" and output "Out_Data" +are of the same clock domain "Clock". Optional input and output registers +can be added by enabling (ADD_***PUT_REGISTERS = TRUE). diff --git a/docs/IPCores/misc/gearbox/gearbox_down_dc.rst b/docs/IPCores/misc/gearbox/gearbox_down_dc.rst index 18ff0e8f..1470f504 100644 --- a/docs/IPCores/misc/gearbox/gearbox_down_dc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_down_dc.rst @@ -19,16 +19,16 @@ PoC.misc.gearbox.down_dc * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - This module provides a downscaling gearbox with a dependent clock (dc) - interface. It perfoems a 'word' to 'byte' splitting. The default order is - LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" is of clock domain - "Clock1"; output "Out_Data" is of clock domain "Clock2". Optional input and - output registers can be added by enabling (ADD_***PUT_REGISTERS = TRUE). +This module provides a downscaling gearbox with a dependent clock (dc) +interface. It perfoems a 'word' to 'byte' splitting. The default order is +LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" is of clock domain +"Clock1"; output "Out_Data" is of clock domain "Clock2". Optional input and +output registers can be added by enabling (ADD_***PUT_REGISTERS = TRUE). Assertions: =========== - - Clock periods of Clock1 and Clock2 MUST be multiples of each other. - - Clock1 and Clock2 MUST be phase aligned (related) to each other. +- Clock periods of Clock1 and Clock2 MUST be multiples of each other. +- Clock1 and Clock2 MUST be phase aligned (related) to each other. diff --git a/docs/IPCores/misc/gearbox/gearbox_up_cc.rst b/docs/IPCores/misc/gearbox/gearbox_up_cc.rst index c059c90e..c76107e0 100644 --- a/docs/IPCores/misc/gearbox/gearbox_up_cc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_up_cc.rst @@ -19,11 +19,11 @@ PoC.misc.gearbox.up_cc * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - This module provides a downscaling gearbox with a common clock (cc) - interface. It perfoems a 'byte' to 'word' collection. The default order is - LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" and output "Out_Data" - are of the same clock domain "Clock". Optional input and output registers - can be added by enabling (ADD_***PUT_REGISTERS = TRUE). +This module provides a downscaling gearbox with a common clock (cc) +interface. It perfoems a 'byte' to 'word' collection. The default order is +LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" and output "Out_Data" +are of the same clock domain "Clock". Optional input and output registers +can be added by enabling (ADD_***PUT_REGISTERS = TRUE). diff --git a/docs/IPCores/misc/gearbox/gearbox_up_dc.rst b/docs/IPCores/misc/gearbox/gearbox_up_dc.rst index 36fc1365..2df5fef6 100644 --- a/docs/IPCores/misc/gearbox/gearbox_up_dc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_up_dc.rst @@ -19,17 +19,17 @@ PoC.misc.gearbox.up_dc * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - This module provides a upscaling gearbox with a dependent clock (dc) - interface. It perfoems a 'byte' to 'word' collection. The default order is - LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" is of clock domain - "Clock1"; output "Out_Data" is of clock domain "Clock2". The "In_Align" - is required to mark the starting byte in the word. An optional input - register can be added by enabling (ADD_INPUT_REGISTERS = TRUE). +This module provides a upscaling gearbox with a dependent clock (dc) +interface. It perfoems a 'byte' to 'word' collection. The default order is +LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" is of clock domain +"Clock1"; output "Out_Data" is of clock domain "Clock2". The "In_Align" +is required to mark the starting byte in the word. An optional input +register can be added by enabling (ADD_INPUT_REGISTERS = TRUE). Assertions: =========== - - Clock periods of Clock1 and Clock2 MUST be multiples of each other. - - Clock1 and Clock2 MUST be phase aligned (related) to each other. +- Clock periods of Clock1 and Clock2 MUST be multiples of each other. +- Clock1 and Clock2 MUST be phase aligned (related) to each other. diff --git a/src/arith/arith_addw.vhdl b/src/arith/arith_addw.vhdl index 0b364c4d..7dd25f26 100644 --- a/src/arith/arith_addw.vhdl +++ b/src/arith/arith_addw.vhdl @@ -8,21 +8,22 @@ -- -- Description: -- ------------------------------------- --- Implements wide addition providing several options all based --- on an adaptation of a carry-select approach. +-- Implements wide addition providing several options all based +-- on an adaptation of a carry-select approach. -- --- References: --- * Hong Diep Nguyen and Bogdan Pasca and Thomas B. Preusser: --- FPGA-Specific Arithmetic Optimizations of Short-Latency Adders, --- FPL 2011. --- -> ARCH: AAM, CAI, CCA --- -> SKIPPING: CCC +-- References: -- --- * Marcin Rogawski, Kris Gaj and Ekawat Homsirikamol: --- A Novel Modular Adder for One Thousand Bits and More --- Using Fast Carry Chains of Modern FPGAs, FPL 2014. --- -> ARCH: PAI --- -> SKIPPING: PPN_KS, PPN_BK +-- * Hong Diep Nguyen and Bogdan Pasca and Thomas B. Preusser: +-- FPGA-Specific Arithmetic Optimizations of Short-Latency Adders, +-- FPL 2011. +-- -> ARCH: AAM, CAI, CCA +-- -> SKIPPING: CCC +-- +-- * Marcin Rogawski, Kris Gaj and Ekawat Homsirikamol: +-- A Novel Modular Adder for One Thousand Bits and More +-- Using Fast Carry Chains of Modern FPGAs, FPL 2014. +-- -> ARCH: PAI +-- -> SKIPPING: PPN_KS, PPN_BK -- -- License: -- ============================================================================= diff --git a/src/arith/arith_carrychain_inc.vhdl b/src/arith/arith_carrychain_inc.vhdl index c97fc0e8..7768fecb 100644 --- a/src/arith/arith_carrychain_inc.vhdl +++ b/src/arith/arith_carrychain_inc.vhdl @@ -8,9 +8,9 @@ -- -- Description: -- ------------------------------------- --- This is a generic carry-chain abstraction for increment by one operations. +-- This is a generic carry-chain abstraction for increment by one operations. -- --- Y <= X + (0...0) & Cin +-- Y <= X + (0...0) & Cin -- -- License: -- ============================================================================= diff --git a/src/misc/gearbox/gearbox_down_cc.vhdl b/src/misc/gearbox/gearbox_down_cc.vhdl index 2f5d7ac2..596d083a 100644 --- a/src/misc/gearbox/gearbox_down_cc.vhdl +++ b/src/misc/gearbox/gearbox_down_cc.vhdl @@ -8,11 +8,11 @@ -- -- Description: -- ------------------------------------- --- This module provides a downscaling gearbox with a common clock (cc) --- interface. It perfoems a 'word' to 'byte' splitting. The default order is --- LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" and output "Out_Data" --- are of the same clock domain "Clock". Optional input and output registers --- can be added by enabling (ADD_***PUT_REGISTERS = TRUE). +-- This module provides a downscaling gearbox with a common clock (cc) +-- interface. It perfoems a 'word' to 'byte' splitting. The default order is +-- LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" and output "Out_Data" +-- are of the same clock domain "Clock". Optional input and output registers +-- can be added by enabling (ADD_***PUT_REGISTERS = TRUE). -- -- License: -- ============================================================================= diff --git a/src/misc/gearbox/gearbox_down_dc.vhdl b/src/misc/gearbox/gearbox_down_dc.vhdl index a68a4d0e..ce1d507c 100644 --- a/src/misc/gearbox/gearbox_down_dc.vhdl +++ b/src/misc/gearbox/gearbox_down_dc.vhdl @@ -8,16 +8,16 @@ -- -- Description: -- ------------------------------------- --- This module provides a downscaling gearbox with a dependent clock (dc) --- interface. It perfoems a 'word' to 'byte' splitting. The default order is --- LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" is of clock domain --- "Clock1"; output "Out_Data" is of clock domain "Clock2". Optional input and --- output registers can be added by enabling (ADD_***PUT_REGISTERS = TRUE). +-- This module provides a downscaling gearbox with a dependent clock (dc) +-- interface. It perfoems a 'word' to 'byte' splitting. The default order is +-- LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" is of clock domain +-- "Clock1"; output "Out_Data" is of clock domain "Clock2". Optional input and +-- output registers can be added by enabling (ADD_***PUT_REGISTERS = TRUE). -- -- Assertions: -- =========== --- - Clock periods of Clock1 and Clock2 MUST be multiples of each other. --- - Clock1 and Clock2 MUST be phase aligned (related) to each other. +-- - Clock periods of Clock1 and Clock2 MUST be multiples of each other. +-- - Clock1 and Clock2 MUST be phase aligned (related) to each other. -- -- License: -- ============================================================================= diff --git a/src/misc/gearbox/gearbox_up_cc.vhdl b/src/misc/gearbox/gearbox_up_cc.vhdl index e3c34051..05de056d 100644 --- a/src/misc/gearbox/gearbox_up_cc.vhdl +++ b/src/misc/gearbox/gearbox_up_cc.vhdl @@ -8,11 +8,11 @@ -- -- Description: -- ------------------------------------- --- This module provides a downscaling gearbox with a common clock (cc) --- interface. It perfoems a 'byte' to 'word' collection. The default order is --- LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" and output "Out_Data" --- are of the same clock domain "Clock". Optional input and output registers --- can be added by enabling (ADD_***PUT_REGISTERS = TRUE). +-- This module provides a downscaling gearbox with a common clock (cc) +-- interface. It perfoems a 'byte' to 'word' collection. The default order is +-- LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" and output "Out_Data" +-- are of the same clock domain "Clock". Optional input and output registers +-- can be added by enabling (ADD_***PUT_REGISTERS = TRUE). -- -- License: -- ============================================================================= diff --git a/src/misc/gearbox/gearbox_up_dc.vhdl b/src/misc/gearbox/gearbox_up_dc.vhdl index 0e451df3..594b2215 100644 --- a/src/misc/gearbox/gearbox_up_dc.vhdl +++ b/src/misc/gearbox/gearbox_up_dc.vhdl @@ -8,17 +8,17 @@ -- -- Description: -- ------------------------------------- --- This module provides a upscaling gearbox with a dependent clock (dc) --- interface. It perfoems a 'byte' to 'word' collection. The default order is --- LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" is of clock domain --- "Clock1"; output "Out_Data" is of clock domain "Clock2". The "In_Align" --- is required to mark the starting byte in the word. An optional input --- register can be added by enabling (ADD_INPUT_REGISTERS = TRUE). +-- This module provides a upscaling gearbox with a dependent clock (dc) +-- interface. It perfoems a 'byte' to 'word' collection. The default order is +-- LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" is of clock domain +-- "Clock1"; output "Out_Data" is of clock domain "Clock2". The "In_Align" +-- is required to mark the starting byte in the word. An optional input +-- register can be added by enabling (ADD_INPUT_REGISTERS = TRUE). -- -- Assertions: -- =========== --- - Clock periods of Clock1 and Clock2 MUST be multiples of each other. --- - Clock1 and Clock2 MUST be phase aligned (related) to each other. +-- - Clock periods of Clock1 and Clock2 MUST be multiples of each other. +-- - Clock1 and Clock2 MUST be phase aligned (related) to each other. -- -- License: -- ============================================================================= From 0698c4067680eb992756220ef827b3945e7618ed Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 24 Nov 2016 01:25:35 +0100 Subject: [PATCH 79/97] AppVeyor: Added first dryrun tests. --- .appveyor.yml | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/.appveyor.yml b/.appveyor.yml index 4f649c90..d69a96b4 100644 --- a/.appveyor.yml +++ b/.appveyor.yml @@ -17,4 +17,18 @@ install: - ps: cp .\tools\AppVeyor\my_project.vhdl .\tb\common\ - ps: .\poc.ps1 -build: off +build: + - ps: Write-Host "Testing query interface..." + - ps: .\poc.ps1 query INSTALL.PoC:InstallationDirectory + - ps: Write-Host "Testing information interface..." + - ps: .\poc.ps1 list-testbench + - ps: .\poc.ps1 list-netlist + - ps: Write-Host "Testing simulators..." + - ps: .\poc.ps1 --dryrun ghdl PoC.arith.prng --analyze --elaborate + - ps: Write-Host "Testing synthesizers..." + - ps: .\poc.ps1 --dryrun quartus PoC.arith.prng --board=DE4 + - ps: .\poc.ps1 --dryrun lse PoC.arith.prng --board=ECP5Versa + - ps: .\poc.ps1 --dryrun xst PoC.arith.prng --board=KC705 + - ps: .\poc.ps1 --dryrun vivado PoC.arith.prng --board=KC705 + - ps: Write-Host "Testing core generators..." + - ps: .\poc.ps1 --dryrun coregen PoC.xil.mig.Atlys_1x128 --board=Atlys From 737422e52e410124047e9c881f4e065dbb77943b Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 24 Nov 2016 01:32:06 +0100 Subject: [PATCH 80/97] AppVeyor: Fixed typo. --- .appveyor.yml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/.appveyor.yml b/.appveyor.yml index d69a96b4..8bba1926 100644 --- a/.appveyor.yml +++ b/.appveyor.yml @@ -17,7 +17,9 @@ install: - ps: cp .\tools\AppVeyor\my_project.vhdl .\tb\common\ - ps: .\poc.ps1 -build: +build: off + +build_script: - ps: Write-Host "Testing query interface..." - ps: .\poc.ps1 query INSTALL.PoC:InstallationDirectory - ps: Write-Host "Testing information interface..." From 47dbaac4b487faa2e34e14ebf2ca38794015198e Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 24 Nov 2016 01:34:08 +0100 Subject: [PATCH 81/97] AppVeyor: Fixed typo in list-*** commands. --- .appveyor.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.appveyor.yml b/.appveyor.yml index 8bba1926..c1ac857c 100644 --- a/.appveyor.yml +++ b/.appveyor.yml @@ -23,8 +23,8 @@ build_script: - ps: Write-Host "Testing query interface..." - ps: .\poc.ps1 query INSTALL.PoC:InstallationDirectory - ps: Write-Host "Testing information interface..." - - ps: .\poc.ps1 list-testbench - - ps: .\poc.ps1 list-netlist + - ps: .\poc.ps1 list-testbench PoC.* + - ps: .\poc.ps1 list-netlist PoC.* - ps: Write-Host "Testing simulators..." - ps: .\poc.ps1 --dryrun ghdl PoC.arith.prng --analyze --elaborate - ps: Write-Host "Testing synthesizers..." From 634045373fc173d920aea149fc3f9016d7420683 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 24 Nov 2016 01:38:52 +0100 Subject: [PATCH 82/97] AppVeyor: Disabled dryrun tests for synthesizers. --- .appveyor.yml | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/.appveyor.yml b/.appveyor.yml index c1ac857c..64986a16 100644 --- a/.appveyor.yml +++ b/.appveyor.yml @@ -28,9 +28,9 @@ build_script: - ps: Write-Host "Testing simulators..." - ps: .\poc.ps1 --dryrun ghdl PoC.arith.prng --analyze --elaborate - ps: Write-Host "Testing synthesizers..." - - ps: .\poc.ps1 --dryrun quartus PoC.arith.prng --board=DE4 - - ps: .\poc.ps1 --dryrun lse PoC.arith.prng --board=ECP5Versa - - ps: .\poc.ps1 --dryrun xst PoC.arith.prng --board=KC705 - - ps: .\poc.ps1 --dryrun vivado PoC.arith.prng --board=KC705 - - ps: Write-Host "Testing core generators..." - - ps: .\poc.ps1 --dryrun coregen PoC.xil.mig.Atlys_1x128 --board=Atlys +# - ps: .\poc.ps1 --dryrun quartus PoC.arith.prng --board=DE4 +# - ps: .\poc.ps1 --dryrun lse PoC.arith.prng --board=ECP5Versa +# - ps: .\poc.ps1 --dryrun xst PoC.arith.prng --board=KC705 +# - ps: .\poc.ps1 --dryrun vivado PoC.arith.prng --board=KC705 +# - ps: Write-Host "Testing core generators..." +# - ps: .\poc.ps1 --dryrun coregen PoC.xil.mig.Atlys_1x128 --board=Atlys From c17165ee3da10ec35f98db7f9989220df38b82b4 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 24 Nov 2016 02:22:57 +0100 Subject: [PATCH 83/97] Added requirements checker shield. --- README.md | 1 + README.tpl | 1 + docs/IPCores/misc/misc_PulseTrain.rst | 4 ++-- docs/index.rst | 7 ++++++- 4 files changed, 10 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 97a4631e..f171c50f 100644 --- a/README.md +++ b/README.md @@ -5,6 +5,7 @@ [![Build Status by Travis-CI](https://travis-ci.org/VLSI-EDA/PoC.svg?branch=release)](https://travis-ci.org/VLSI-EDA/PoC/branches) [![Build status by AppVeyor](https://ci.appveyor.com/api/projects/status/r5dtv6amsppigpsp/branch/release?svg=true)](https://ci.appveyor.com/project/Paebbels/poc/branch/release) [![Documentation Status](https://readthedocs.org/projects/poc-library/badge/?version=latest)](http://poc-library.readthedocs.io/en/latest/?badge=latest) +[![Requirements Status](https://requires.io/github/VLSI-EDA/PoC/requirements.svg?branch=release)](https://requires.io/github/VLSI-EDA/PoC/requirements/?branch=release) [![Join the chat at https://gitter.im/VLSI-EDA/PoC](https://badges.gitter.im/VLSI-EDA/PoC.svg)](https://gitter.im/VLSI-EDA/PoC) ![Latest tag](https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat) [![Latest release](https://img.shields.io/github/release/VLSI-EDA/PoC.svg?style=flat)](https://github.com/VLSI-EDA/PoC/releases) diff --git a/README.tpl b/README.tpl index 56dcb74a..6423c0a0 100644 --- a/README.tpl +++ b/README.tpl @@ -5,6 +5,7 @@ [![Build Status by Travis-CI](https://travis-ci.org/VLSI-EDA/PoC.svg?branch={@BRANCH@})](https://travis-ci.org/VLSI-EDA/PoC/branches) [![Build status by AppVeyor](https://ci.appveyor.com/api/projects/status/r5dtv6amsppigpsp/branch/release?svg=true)](https://ci.appveyor.com/project/Paebbels/poc/branch/release) [![Documentation Status](https://readthedocs.org/projects/poc-library/badge/?version=latest)](http://poc-library.readthedocs.io/en/latest/?badge=latest) +[![Requirements Status](https://requires.io/github/VLSI-EDA/PoC/requirements.svg?branch=release)](https://requires.io/github/VLSI-EDA/PoC/requirements/?branch=release) [![Join the chat at https://gitter.im/VLSI-EDA/PoC](https://badges.gitter.im/VLSI-EDA/PoC.svg)](https://gitter.im/VLSI-EDA/PoC) ![Latest tag](https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat) [![Latest release](https://img.shields.io/github/release/VLSI-EDA/PoC.svg?style=flat)](https://github.com/VLSI-EDA/PoC/releases) diff --git a/docs/IPCores/misc/misc_PulseTrain.rst b/docs/IPCores/misc/misc_PulseTrain.rst index 461b75ed..e5186ad5 100644 --- a/docs/IPCores/misc/misc_PulseTrain.rst +++ b/docs/IPCores/misc/misc_PulseTrain.rst @@ -19,8 +19,8 @@ PoC.misc.PulseTrain * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - This module generates pulse trains. This module was written as a answer for - a StackOverflow question: http://stackoverflow.com/questions/25783320 +This module generates pulse trains. This module was written as a answer for +a StackOverflow question: http://stackoverflow.com/questions/25783320 diff --git a/docs/index.rst b/docs/index.rst index 46b3cf0d..b2014035 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -36,6 +36,9 @@ Germany |br| .. image:: https://ci.appveyor.com/api/projects/status/r5dtv6amsppigpsp/branch/release?svg=true :target: https://ci.appveyor.com/project/Paebbels/poc/branch/release :alt: Build status by AppVeyor + .. image:: https://requires.io/github/VLSI-EDA/PoC/requirements.svg?branch=release + :target: https://requires.io/github/VLSI-EDA/PoC/requirements/?branch=release + :alt: Requirements Status .. image:: https://badges.gitter.im/VLSI-EDA/PoC.svg :target: https://gitter.im/VLSI-EDA/PoC :alt: Join @@ -48,7 +51,9 @@ Germany |br| :target: References/Licenses/License.html :alt: Apache License 2.0 - ----------------------------------------------------------------------------- + .. raw:: html + +

The PoC-Library Documentation From aa679623dc818d0c392880ce09d5ef81170565bd Mon Sep 17 00:00:00 2001 From: Martin Zabel Date: Fri, 25 Nov 2016 17:38:16 +0100 Subject: [PATCH 84/97] Documented known issues about synthesis of tri-state drivers and bidirectional records. Minor other fixes. --- .appveyor.yml | 16 ---- README.md | 1 - README.tpl | 1 - docs/IPCores/misc/misc_PulseTrain.rst | 4 +- docs/References/KnownIssues.rst | 114 ++++++++++++++++++++++---- docs/index.rst | 7 +- src/io/io.pkg.vhdl | 21 +++-- 7 files changed, 119 insertions(+), 45 deletions(-) diff --git a/.appveyor.yml b/.appveyor.yml index 64986a16..4f649c90 100644 --- a/.appveyor.yml +++ b/.appveyor.yml @@ -18,19 +18,3 @@ install: - ps: .\poc.ps1 build: off - -build_script: - - ps: Write-Host "Testing query interface..." - - ps: .\poc.ps1 query INSTALL.PoC:InstallationDirectory - - ps: Write-Host "Testing information interface..." - - ps: .\poc.ps1 list-testbench PoC.* - - ps: .\poc.ps1 list-netlist PoC.* - - ps: Write-Host "Testing simulators..." - - ps: .\poc.ps1 --dryrun ghdl PoC.arith.prng --analyze --elaborate - - ps: Write-Host "Testing synthesizers..." -# - ps: .\poc.ps1 --dryrun quartus PoC.arith.prng --board=DE4 -# - ps: .\poc.ps1 --dryrun lse PoC.arith.prng --board=ECP5Versa -# - ps: .\poc.ps1 --dryrun xst PoC.arith.prng --board=KC705 -# - ps: .\poc.ps1 --dryrun vivado PoC.arith.prng --board=KC705 -# - ps: Write-Host "Testing core generators..." -# - ps: .\poc.ps1 --dryrun coregen PoC.xil.mig.Atlys_1x128 --board=Atlys diff --git a/README.md b/README.md index f171c50f..97a4631e 100644 --- a/README.md +++ b/README.md @@ -5,7 +5,6 @@ [![Build Status by Travis-CI](https://travis-ci.org/VLSI-EDA/PoC.svg?branch=release)](https://travis-ci.org/VLSI-EDA/PoC/branches) [![Build status by AppVeyor](https://ci.appveyor.com/api/projects/status/r5dtv6amsppigpsp/branch/release?svg=true)](https://ci.appveyor.com/project/Paebbels/poc/branch/release) [![Documentation Status](https://readthedocs.org/projects/poc-library/badge/?version=latest)](http://poc-library.readthedocs.io/en/latest/?badge=latest) -[![Requirements Status](https://requires.io/github/VLSI-EDA/PoC/requirements.svg?branch=release)](https://requires.io/github/VLSI-EDA/PoC/requirements/?branch=release) [![Join the chat at https://gitter.im/VLSI-EDA/PoC](https://badges.gitter.im/VLSI-EDA/PoC.svg)](https://gitter.im/VLSI-EDA/PoC) ![Latest tag](https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat) [![Latest release](https://img.shields.io/github/release/VLSI-EDA/PoC.svg?style=flat)](https://github.com/VLSI-EDA/PoC/releases) diff --git a/README.tpl b/README.tpl index 6423c0a0..56dcb74a 100644 --- a/README.tpl +++ b/README.tpl @@ -5,7 +5,6 @@ [![Build Status by Travis-CI](https://travis-ci.org/VLSI-EDA/PoC.svg?branch={@BRANCH@})](https://travis-ci.org/VLSI-EDA/PoC/branches) [![Build status by AppVeyor](https://ci.appveyor.com/api/projects/status/r5dtv6amsppigpsp/branch/release?svg=true)](https://ci.appveyor.com/project/Paebbels/poc/branch/release) [![Documentation Status](https://readthedocs.org/projects/poc-library/badge/?version=latest)](http://poc-library.readthedocs.io/en/latest/?badge=latest) -[![Requirements Status](https://requires.io/github/VLSI-EDA/PoC/requirements.svg?branch=release)](https://requires.io/github/VLSI-EDA/PoC/requirements/?branch=release) [![Join the chat at https://gitter.im/VLSI-EDA/PoC](https://badges.gitter.im/VLSI-EDA/PoC.svg)](https://gitter.im/VLSI-EDA/PoC) ![Latest tag](https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat) [![Latest release](https://img.shields.io/github/release/VLSI-EDA/PoC.svg?style=flat)](https://github.com/VLSI-EDA/PoC/releases) diff --git a/docs/IPCores/misc/misc_PulseTrain.rst b/docs/IPCores/misc/misc_PulseTrain.rst index e5186ad5..461b75ed 100644 --- a/docs/IPCores/misc/misc_PulseTrain.rst +++ b/docs/IPCores/misc/misc_PulseTrain.rst @@ -19,8 +19,8 @@ PoC.misc.PulseTrain * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` -This module generates pulse trains. This module was written as a answer for -a StackOverflow question: http://stackoverflow.com/questions/25783320 + This module generates pulse trains. This module was written as a answer for + a StackOverflow question: http://stackoverflow.com/questions/25783320 diff --git a/docs/References/KnownIssues.rst b/docs/References/KnownIssues.rst index 2521b483..dc6a005a 100644 --- a/docs/References/KnownIssues.rst +++ b/docs/References/KnownIssues.rst @@ -1,38 +1,124 @@ +.. _ISSUE: Known Issues ############ -Aldec -***** -Active-HDL Student-Edition -========================== +.. _ISSUE:General: + +General +******* + + +.. _ISSUE:General:tristate: + +Synthesis of tri-state signals +============================== + +Tri-state signals should be only used when they are connected +(through the hierarchy) to top-level bidirectional or output pins. + +Descriptions which infer a tri-state driver like:: + + pin <= data when tri = '0' else 'Z'; + +should not be included in any IP core description because these hinder +or even inhibit block-based design flows. If a netlist is generated +from such an IP core, the netlist may contain only a simple internal +(on-chip) tri-state buffer instead of the correct tri-state I/O block +primitive because I/O buffers are not automatically added for netlist +generation. If the netlist is then used in another design, the +mapper, e.g. Xilinx ISE Map, may fail to merge the +internal tri-state buffer of the IP core netlist with the I/O buffer +automatically created for the top-level netlist. This failing behavior +is not considered as a tool bug. + +Thus, if tri-state drivers should be included in an IP core, then the +IP core description must instantiate the appropiate I/O block +primitive of the target architecture like it is done by the Xilinx MIG. + + +.. _ISSUE:General:inout_records: + +Synthesis of bidirectional records +================================== + +Records are useful to group several signals of an IP core +interface. But the corresponding port of this record type should not +be of mode ``inout`` to pass data in both direction. This restriction +holds even if a record member will be driven only by one source in the +real hardware and even if all possible drivers of this port are visible +to the current synthesis run (AND-OR based multiplexer). The following +observations have been made: + +* An IP core (entity or procedure) must drive all record members with + value 'Z' which are only used as an input in the IP core. If this is + missed, then the respective record member will be driven by 'U' and + the effective value after resolution will be 'U' as well, see IEEE + Std. 1076-2008 para. 12.6.1. Thus simulation will fail. + + But these 'Z' drivers will flood the RTL / Netlist view of Altera + Quartus-II, Intel Quartus Prime and Lattice Diamond with always + tri-stated drivers and make this view unusable. + + Note: Simulation with ModelSim shows correct output even when the + 'Z' driver is missing, but a warning is reported that the behavior + is not VHDL Standard compliant. + +* Altera Quartus-II and Intel Quartus Prime report warnings about this + meaningless 'Z' drivers. Synthesis result is as expected if each + record member is only driven by one source in real hardware. + +* The synthesis result of the Lattice Synthesis Engine (3.7.0 / 3.8.0) + is not optimal. It seems that the synthesizer tries to implement the + internal (on-chip) tristate bus using AND-OR logic but failed to + optimize it away because there was only one real source. Test case + was a simple SRAM controller which used the record type + ``T_IO_TRISTATE`` to bring-out the data-bus so that the tri-state + driver could be instantiated on the top-level. + +Use separate records for the input and output data flow instead. + + +-------------------------------------------------------------------------------- + +.. _ISSUE:Aldec:ActiveHDL: + +Aldec Active-HDL +**************** * Aliases to functions and protected type methods -Altera -****** -Quartus-II -========== +.. _ISSUE:Altera:Quartus: +.. _ISSUE:Intel:Quartus: + +Altera Quartus-II / Intel Quartus Prime +*************************************** * Generic types of type strings filled with NUL + +.. _ISSUE:GHDL: + GHDL **** * Aliases to protected type methods -Xilinx -****** -ISE -=== +.. _ISSUE:Xilinx:ISE: + +Xilinx ISE +********** * Shared Variables in Simulation (VHDL-93) -Vivado -====== + +.. _ISSUE:Xilinx:Vivado: + +Xilinx Vivado +************* * Physical types in synthesis * VHDL-2008 mode in simulation diff --git a/docs/index.rst b/docs/index.rst index b2014035..46b3cf0d 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -36,9 +36,6 @@ Germany |br| .. image:: https://ci.appveyor.com/api/projects/status/r5dtv6amsppigpsp/branch/release?svg=true :target: https://ci.appveyor.com/project/Paebbels/poc/branch/release :alt: Build status by AppVeyor - .. image:: https://requires.io/github/VLSI-EDA/PoC/requirements.svg?branch=release - :target: https://requires.io/github/VLSI-EDA/PoC/requirements/?branch=release - :alt: Requirements Status .. image:: https://badges.gitter.im/VLSI-EDA/PoC.svg :target: https://gitter.im/VLSI-EDA/PoC :alt: Join @@ -51,9 +48,7 @@ Germany |br| :target: References/Licenses/License.html :alt: Apache License 2.0 - .. raw:: html - -
+ ----------------------------------------------------------------------------- The PoC-Library Documentation diff --git a/src/io/io.pkg.vhdl b/src/io/io.pkg.vhdl index 7bcbf99f..786abcb9 100644 --- a/src/io/io.pkg.vhdl +++ b/src/io/io.pkg.vhdl @@ -39,8 +39,9 @@ use PoC.physical.all; package io is - -- not yet supported by Xilinx ISE Simulator - the subsignal I (with reverse direction) is always 'U' - -- so use this record only in pure synthesis environments + -- Do not use this type for ``inout`` ports of synthesizable IP cores to drive + -- values in both directions, see also + -- :ref:`ISSUES:General:inout_records`. type T_IO_TRISTATE is record I : std_logic; -- input / from device to FPGA O : std_logic; -- output / from FPGA to device @@ -52,13 +53,18 @@ package io is N : std_logic; end record; + -- Do not use this type for ``inout`` ports of synthesizable IP cores to drive + -- values in both directions, see also + -- :ref:`ISSUES:General:inout_records`. type T_IO_TRISTATE_VECTOR is array(natural range <>) of T_IO_TRISTATE; + type T_IO_LVDS_VECTOR is array(natural range <>) of T_IO_LVDS; type T_IO_DATARATE is (IO_DATARATE_SDR, IO_DATARATE_DDR, IO_DATARATE_QDR); -- Drive a std_logic_vector from a Tri-State bus and in reverse. - -- Use this procedure only in simulation + -- Use this procedure only in simulation, see also + -- :ref:`ISSUES:General:inout_records`. procedure io_tristate_driver ( signal pad : inout std_logic_vector; signal tristate : inout T_IO_TRISTATE_VECTOR @@ -174,8 +180,13 @@ package body io is for k in pad'range loop pad(k) <= ite((tristate(k).t = '1'), 'Z', tristate(k).o); tristate(k).i <= pad(k); - tristate(k).t <= 'Z'; -- drive all record members - tristate(k).o <= 'Z'; -- drive all record members + -- As defined in IEEE Std. 1076-2008 para. 2.1.1.2: "a subprogram + -- contains a driver for each formal signal parameter of mode out or + -- inout". This driver will drive 'U' if the following 'Z' drivers are + -- missed. Driving 'U' would lead to an effective value of 'U' which is + -- not intended, see also :ref:`ISSUES:General:inout_records`. + tristate(k).t <= 'Z'; + tristate(k).o <= 'Z'; end loop; end procedure; From 11661aa4c0c3a2314f31755548e72fd7bf6258d8 Mon Sep 17 00:00:00 2001 From: Martin Zabel Date: Fri, 25 Nov 2016 18:11:24 +0100 Subject: [PATCH 85/97] Improved documentation of known issues about synthesis of bidirectional records. Reverted minor fixes from last commit. --- .appveyor.yml | 16 ++++++++++++++++ README.md | 1 + README.tpl | 1 + docs/IPCores/misc/misc_PulseTrain.rst | 4 ++-- docs/References/KnownIssues.rst | 4 ++-- docs/index.rst | 7 ++++++- 6 files changed, 28 insertions(+), 5 deletions(-) diff --git a/.appveyor.yml b/.appveyor.yml index 4f649c90..64986a16 100644 --- a/.appveyor.yml +++ b/.appveyor.yml @@ -18,3 +18,19 @@ install: - ps: .\poc.ps1 build: off + +build_script: + - ps: Write-Host "Testing query interface..." + - ps: .\poc.ps1 query INSTALL.PoC:InstallationDirectory + - ps: Write-Host "Testing information interface..." + - ps: .\poc.ps1 list-testbench PoC.* + - ps: .\poc.ps1 list-netlist PoC.* + - ps: Write-Host "Testing simulators..." + - ps: .\poc.ps1 --dryrun ghdl PoC.arith.prng --analyze --elaborate + - ps: Write-Host "Testing synthesizers..." +# - ps: .\poc.ps1 --dryrun quartus PoC.arith.prng --board=DE4 +# - ps: .\poc.ps1 --dryrun lse PoC.arith.prng --board=ECP5Versa +# - ps: .\poc.ps1 --dryrun xst PoC.arith.prng --board=KC705 +# - ps: .\poc.ps1 --dryrun vivado PoC.arith.prng --board=KC705 +# - ps: Write-Host "Testing core generators..." +# - ps: .\poc.ps1 --dryrun coregen PoC.xil.mig.Atlys_1x128 --board=Atlys diff --git a/README.md b/README.md index 97a4631e..f171c50f 100644 --- a/README.md +++ b/README.md @@ -5,6 +5,7 @@ [![Build Status by Travis-CI](https://travis-ci.org/VLSI-EDA/PoC.svg?branch=release)](https://travis-ci.org/VLSI-EDA/PoC/branches) [![Build status by AppVeyor](https://ci.appveyor.com/api/projects/status/r5dtv6amsppigpsp/branch/release?svg=true)](https://ci.appveyor.com/project/Paebbels/poc/branch/release) [![Documentation Status](https://readthedocs.org/projects/poc-library/badge/?version=latest)](http://poc-library.readthedocs.io/en/latest/?badge=latest) +[![Requirements Status](https://requires.io/github/VLSI-EDA/PoC/requirements.svg?branch=release)](https://requires.io/github/VLSI-EDA/PoC/requirements/?branch=release) [![Join the chat at https://gitter.im/VLSI-EDA/PoC](https://badges.gitter.im/VLSI-EDA/PoC.svg)](https://gitter.im/VLSI-EDA/PoC) ![Latest tag](https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat) [![Latest release](https://img.shields.io/github/release/VLSI-EDA/PoC.svg?style=flat)](https://github.com/VLSI-EDA/PoC/releases) diff --git a/README.tpl b/README.tpl index 56dcb74a..6423c0a0 100644 --- a/README.tpl +++ b/README.tpl @@ -5,6 +5,7 @@ [![Build Status by Travis-CI](https://travis-ci.org/VLSI-EDA/PoC.svg?branch={@BRANCH@})](https://travis-ci.org/VLSI-EDA/PoC/branches) [![Build status by AppVeyor](https://ci.appveyor.com/api/projects/status/r5dtv6amsppigpsp/branch/release?svg=true)](https://ci.appveyor.com/project/Paebbels/poc/branch/release) [![Documentation Status](https://readthedocs.org/projects/poc-library/badge/?version=latest)](http://poc-library.readthedocs.io/en/latest/?badge=latest) +[![Requirements Status](https://requires.io/github/VLSI-EDA/PoC/requirements.svg?branch=release)](https://requires.io/github/VLSI-EDA/PoC/requirements/?branch=release) [![Join the chat at https://gitter.im/VLSI-EDA/PoC](https://badges.gitter.im/VLSI-EDA/PoC.svg)](https://gitter.im/VLSI-EDA/PoC) ![Latest tag](https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat) [![Latest release](https://img.shields.io/github/release/VLSI-EDA/PoC.svg?style=flat)](https://github.com/VLSI-EDA/PoC/releases) diff --git a/docs/IPCores/misc/misc_PulseTrain.rst b/docs/IPCores/misc/misc_PulseTrain.rst index 461b75ed..e5186ad5 100644 --- a/docs/IPCores/misc/misc_PulseTrain.rst +++ b/docs/IPCores/misc/misc_PulseTrain.rst @@ -19,8 +19,8 @@ PoC.misc.PulseTrain * |gh-src| :pocsrc:`Sourcecode ` * |gh-tb| :poctb:`Testbench ` - This module generates pulse trains. This module was written as a answer for - a StackOverflow question: http://stackoverflow.com/questions/25783320 +This module generates pulse trains. This module was written as a answer for +a StackOverflow question: http://stackoverflow.com/questions/25783320 diff --git a/docs/References/KnownIssues.rst b/docs/References/KnownIssues.rst index dc6a005a..f56da099 100644 --- a/docs/References/KnownIssues.rst +++ b/docs/References/KnownIssues.rst @@ -47,8 +47,8 @@ Records are useful to group several signals of an IP core interface. But the corresponding port of this record type should not be of mode ``inout`` to pass data in both direction. This restriction holds even if a record member will be driven only by one source in the -real hardware and even if all possible drivers of this port are visible -to the current synthesis run (AND-OR based multiplexer). The following +real hardware and even if all the drivers (one for each record member) +are visible to the current synthesis run. The following observations have been made: * An IP core (entity or procedure) must drive all record members with diff --git a/docs/index.rst b/docs/index.rst index 46b3cf0d..b2014035 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -36,6 +36,9 @@ Germany |br| .. image:: https://ci.appveyor.com/api/projects/status/r5dtv6amsppigpsp/branch/release?svg=true :target: https://ci.appveyor.com/project/Paebbels/poc/branch/release :alt: Build status by AppVeyor + .. image:: https://requires.io/github/VLSI-EDA/PoC/requirements.svg?branch=release + :target: https://requires.io/github/VLSI-EDA/PoC/requirements/?branch=release + :alt: Requirements Status .. image:: https://badges.gitter.im/VLSI-EDA/PoC.svg :target: https://gitter.im/VLSI-EDA/PoC :alt: Join @@ -48,7 +51,9 @@ Germany |br| :target: References/Licenses/License.html :alt: Apache License 2.0 - ----------------------------------------------------------------------------- + .. raw:: html + +
The PoC-Library Documentation From 1290b81b7be8d11713bbef5439759387eedf3ff2 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 27 Nov 2016 23:02:52 +0100 Subject: [PATCH 86/97] Improved documentation. --- docs/IPCores/arith/arith_addw.rst | 7 +++++++ docs/IPCores/arith/arith_bcdcollect.rst | 7 +++++++ docs/IPCores/arith/arith_carrychain_inc.rst | 7 +++++++ docs/IPCores/arith/arith_convert_bin2bcd.rst | 7 +++++++ docs/IPCores/arith/arith_counter_bcd.rst | 7 +++++++ docs/IPCores/arith/arith_counter_free.rst | 7 +++++++ docs/IPCores/arith/arith_counter_gray.rst | 7 +++++++ docs/IPCores/arith/arith_counter_ring.rst | 7 +++++++ docs/IPCores/arith/arith_div.rst | 7 +++++++ docs/IPCores/arith/arith_firstone.rst | 7 +++++++ docs/IPCores/arith/arith_muls_wide.rst | 7 +++++++ docs/IPCores/arith/arith_prefix_and.rst | 7 +++++++ docs/IPCores/arith/arith_prefix_or.rst | 7 +++++++ docs/IPCores/arith/arith_prng.rst | 7 +++++++ docs/IPCores/arith/arith_same.rst | 7 +++++++ docs/IPCores/arith/arith_scaler.rst | 7 +++++++ docs/IPCores/arith/arith_shifter_barrel.rst | 7 +++++++ docs/IPCores/arith/arith_sqrt.rst | 7 +++++++ docs/IPCores/bus/bus_Arbiter.rst | 7 +++++++ docs/IPCores/bus/stream/stream_Buffer.rst | 7 +++++++ docs/IPCores/bus/stream/stream_DeMux.rst | 7 +++++++ docs/IPCores/bus/stream/stream_FrameGenerator.rst | 7 +++++++ docs/IPCores/bus/stream/stream_Mirror.rst | 7 +++++++ docs/IPCores/bus/stream/stream_Mux.rst | 7 +++++++ docs/IPCores/bus/stream/stream_Sink.rst | 7 +++++++ docs/IPCores/bus/stream/stream_Source.rst | 7 +++++++ docs/IPCores/bus/wb/wb_fifo_adapter.rst | 7 +++++++ docs/IPCores/bus/wb/wb_ocram.rst | 7 +++++++ docs/IPCores/bus/wb/wb_uart_wrapper.rst | 7 +++++++ docs/IPCores/cache/cache_cpu.rst | 7 +++++++ docs/IPCores/cache/cache_mem.rst | 7 +++++++ docs/IPCores/cache/cache_par.rst | 7 +++++++ docs/IPCores/cache/cache_par2.rst | 7 +++++++ docs/IPCores/cache/cache_replacement_policy.rst | 7 +++++++ docs/IPCores/cache/cache_tagunit_par.rst | 7 +++++++ docs/IPCores/cache/cache_tagunit_seq.rst | 7 +++++++ docs/IPCores/comm/comm_crc.rst | 7 +++++++ docs/IPCores/comm/comm_scramble.rst | 7 +++++++ docs/IPCores/fifo/fifo_cc_got.rst | 7 +++++++ docs/IPCores/fifo/fifo_cc_got_tempgot.rst | 7 +++++++ docs/IPCores/fifo/fifo_cc_got_tempput.rst | 7 +++++++ docs/IPCores/fifo/fifo_dc_got_sm.rst | 7 +++++++ docs/IPCores/fifo/fifo_glue.rst | 7 +++++++ docs/IPCores/fifo/fifo_ic_assembly.rst | 7 +++++++ docs/IPCores/fifo/fifo_ic_got.rst | 7 +++++++ docs/IPCores/fifo/fifo_shift.rst | 7 +++++++ docs/IPCores/io/ddrio/ddrio_in.rst | 7 +++++++ docs/IPCores/io/ddrio/ddrio_inout.rst | 7 +++++++ docs/IPCores/io/ddrio/ddrio_out.rst | 7 +++++++ docs/IPCores/io/iic/iic_BusController.rst | 7 +++++++ docs/IPCores/io/iic/iic_Controller.rst | 7 +++++++ docs/IPCores/io/iic/iic_Controller_SFF8431.rst | 7 +++++++ docs/IPCores/io/iic/iic_Switch_PCA9548A.rst | 7 +++++++ docs/IPCores/io/io_7SegmentMux_BCD.rst | 7 +++++++ docs/IPCores/io/io_7SegmentMux_HEX.rst | 7 +++++++ docs/IPCores/io/io_Debounce.rst | 7 +++++++ docs/IPCores/io/io_FanControl.rst | 7 +++++++ docs/IPCores/io/io_FrequencyCounter.rst | 7 +++++++ docs/IPCores/io/io_GlitchFilter.rst | 7 +++++++ docs/IPCores/io/io_KeyPadScanner.rst | 7 +++++++ docs/IPCores/io/io_PulseWidthModulation.rst | 7 +++++++ docs/IPCores/io/io_TimingCounter.rst | 7 +++++++ docs/IPCores/io/lcd/lcd_LCDBuffer.rst | 7 +++++++ docs/IPCores/io/lcd/lcd_LCDBusController.rst | 7 +++++++ docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst | 7 +++++++ docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst | 7 +++++++ docs/IPCores/io/lcd/lcd_dotmatrix.rst | 7 +++++++ docs/IPCores/io/mdio/mdio_Controller.rst | 7 +++++++ docs/IPCores/io/mdio/mdio_IIC_Adapter.rst | 7 +++++++ docs/IPCores/io/pio/pio_fifo_in.rst | 7 +++++++ docs/IPCores/io/pio/pio_fifo_out.rst | 7 +++++++ docs/IPCores/io/pio/pio_in.rst | 7 +++++++ docs/IPCores/io/pio/pio_out.rst | 7 +++++++ docs/IPCores/io/pmod/pmod_KYPD.rst | 7 +++++++ docs/IPCores/io/pmod/pmod_SSD.rst | 7 +++++++ docs/IPCores/io/pmod/pmod_USBUART.rst | 7 +++++++ docs/IPCores/io/uart/uart_bclk.rst | 7 +++++++ docs/IPCores/io/uart/uart_fifo.rst | 7 +++++++ docs/IPCores/io/uart/uart_ft245.rst | 7 +++++++ docs/IPCores/io/uart/uart_rx.rst | 7 +++++++ docs/IPCores/io/uart/uart_tx.rst | 7 +++++++ docs/IPCores/io/vga/vga_phy.rst | 7 +++++++ docs/IPCores/io/vga/vga_phy_ch7301c.rst | 7 +++++++ docs/IPCores/io/vga/vga_timing.rst | 7 +++++++ docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst | 7 +++++++ docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst | 7 +++++++ docs/IPCores/mem/lut/lut_Sine.rst | 7 +++++++ docs/IPCores/mem/ocram/ocram_esdp.rst | 7 +++++++ docs/IPCores/mem/ocram/ocram_sdp.rst | 7 +++++++ docs/IPCores/mem/ocram/ocram_sdp_wf.rst | 7 +++++++ docs/IPCores/mem/ocram/ocram_sp.rst | 7 +++++++ docs/IPCores/mem/ocram/ocram_tdp.rst | 7 +++++++ docs/IPCores/mem/ocram/ocram_tdp_sim.rst | 7 +++++++ docs/IPCores/mem/ocram/ocram_tdp_wf.rst | 7 +++++++ docs/IPCores/mem/ocrom/ocrom_dp.rst | 7 +++++++ docs/IPCores/mem/ocrom/ocrom_sp.rst | 7 +++++++ docs/IPCores/mem/sdram/sdram_ctrl_de0.rst | 7 +++++++ docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst | 7 +++++++ docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst | 7 +++++++ docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst | 7 +++++++ docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst | 7 +++++++ docs/IPCores/misc/filter/filter_and.rst | 7 +++++++ docs/IPCores/misc/filter/filter_mean.rst | 7 +++++++ docs/IPCores/misc/filter/filter_or.rst | 7 +++++++ docs/IPCores/misc/gearbox/gearbox_down_cc.rst | 7 +++++++ docs/IPCores/misc/gearbox/gearbox_down_dc.rst | 7 +++++++ docs/IPCores/misc/gearbox/gearbox_up_cc.rst | 7 +++++++ docs/IPCores/misc/gearbox/gearbox_up_dc.rst | 7 +++++++ docs/IPCores/misc/misc_BitwidthConverter.rst | 7 +++++++ docs/IPCores/misc/misc_ByteAligner.rst | 7 +++++++ docs/IPCores/misc/misc_Delay.rst | 7 +++++++ docs/IPCores/misc/misc_FrequencyMeasurement.rst | 7 +++++++ docs/IPCores/misc/misc_PulseTrain.rst | 7 +++++++ docs/IPCores/misc/misc_Sequencer.rst | 7 +++++++ docs/IPCores/misc/misc_StrobeGenerator.rst | 7 +++++++ docs/IPCores/misc/misc_StrobeLimiter.rst | 7 +++++++ docs/IPCores/misc/misc_bit_lz.rst | 7 +++++++ docs/IPCores/misc/stat/stat_Average.rst | 7 +++++++ docs/IPCores/misc/stat/stat_Histogram.rst | 7 +++++++ docs/IPCores/misc/stat/stat_Maximum.rst | 7 +++++++ docs/IPCores/misc/stat/stat_Minimum.rst | 7 +++++++ docs/IPCores/misc/sync/sync_Bits.rst | 7 +++++++ docs/IPCores/misc/sync/sync_Command.rst | 7 +++++++ docs/IPCores/misc/sync/sync_Pulse.rst | 7 +++++++ docs/IPCores/misc/sync/sync_Reset.rst | 7 +++++++ docs/IPCores/misc/sync/sync_Strobe.rst | 7 +++++++ docs/IPCores/misc/sync/sync_Vector.rst | 7 +++++++ docs/IPCores/net/arp/arp_BroadCast_Receiver.rst | 7 +++++++ docs/IPCores/net/arp/arp_BroadCast_Requester.rst | 7 +++++++ docs/IPCores/net/arp/arp_Cache.rst | 7 +++++++ docs/IPCores/net/arp/arp_IPPool.rst | 7 +++++++ docs/IPCores/net/arp/arp_Tester.rst | 7 +++++++ docs/IPCores/net/arp/arp_UniCast_Receiver.rst | 7 +++++++ docs/IPCores/net/arp/arp_UniCast_Responder.rst | 7 +++++++ docs/IPCores/net/arp/arp_Wrapper.rst | 7 +++++++ docs/IPCores/net/eth/eth_GEMAC_GMII.rst | 7 +++++++ docs/IPCores/net/eth/eth_GEMAC_RX.rst | 7 +++++++ docs/IPCores/net/eth/eth_GEMAC_TX.rst | 7 +++++++ docs/IPCores/net/eth/eth_PHYController.rst | 7 +++++++ .../IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst | 7 +++++++ docs/IPCores/net/eth/eth_Wrapper.rst | 7 +++++++ docs/IPCores/net/icmpv4/icmpv4_RX.rst | 7 +++++++ docs/IPCores/net/icmpv4/icmpv4_TX.rst | 7 +++++++ docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst | 7 +++++++ docs/IPCores/net/icmpv6/icmpv6_RX.rst | 7 +++++++ docs/IPCores/net/icmpv6/icmpv6_TX.rst | 7 +++++++ docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst | 7 +++++++ docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst | 7 +++++++ docs/IPCores/net/ipv4/ipv4_RX.rst | 7 +++++++ docs/IPCores/net/ipv4/ipv4_TX.rst | 7 +++++++ docs/IPCores/net/ipv4/ipv4_Wrapper.rst | 7 +++++++ docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst | 7 +++++++ docs/IPCores/net/ipv6/ipv6_RX.rst | 7 +++++++ docs/IPCores/net/ipv6/ipv6_TX.rst | 7 +++++++ docs/IPCores/net/ipv6/ipv6_Wrapper.rst | 7 +++++++ docs/IPCores/net/mac/mac_FrameLoopback.rst | 7 +++++++ docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst | 7 +++++++ docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst | 7 +++++++ docs/IPCores/net/mac/mac_RX_Type_Switch.rst | 7 +++++++ docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst | 7 +++++++ docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst | 7 +++++++ docs/IPCores/net/mac/mac_TX_Type_Prepender.rst | 7 +++++++ docs/IPCores/net/mac/mac_Wrapper.rst | 7 +++++++ docs/IPCores/net/ndp/ndp_DestinationCache.rst | 7 +++++++ docs/IPCores/net/ndp/ndp_FSMQuery.rst | 7 +++++++ docs/IPCores/net/ndp/ndp_NeighborCache.rst | 7 +++++++ docs/IPCores/net/ndp/ndp_Wrapper.rst | 7 +++++++ docs/IPCores/net/net_FrameChecksum.rst | 7 +++++++ docs/IPCores/net/net_FrameLoopback.rst | 7 +++++++ docs/IPCores/net/net_FramePerformanceCounter.rst | 7 +++++++ docs/IPCores/net/stack/stack_UDPv4.rst | 7 +++++++ docs/IPCores/net/udp/udp_FrameLoopback.rst | 7 +++++++ docs/IPCores/net/udp/udp_RX.rst | 7 +++++++ docs/IPCores/net/udp/udp_TX.rst | 7 +++++++ docs/IPCores/net/udp/udp_Wrapper.rst | 7 +++++++ docs/IPCores/sort/sort_ExpireList.rst | 7 +++++++ docs/IPCores/sort/sort_InsertSort.rst | 7 +++++++ docs/IPCores/sort/sort_LeastFrequentlyUsed.rst | 7 +++++++ docs/IPCores/sort/sort_lru_cache.rst | 7 +++++++ docs/IPCores/sort/sort_lru_list.rst | 7 +++++++ docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst | 7 +++++++ docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst | 7 +++++++ docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst | 7 +++++++ docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst | 7 +++++++ docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst | 7 +++++++ docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst | 7 +++++++ docs/IPCores/sort/sortnet/sortnet_Transform.rst | 7 +++++++ docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst | 7 +++++++ docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst | 7 +++++++ docs/IPCores/xil/xil_BSCAN.rst | 7 +++++++ docs/IPCores/xil/xil_ChipScopeICON.rst | 7 +++++++ docs/IPCores/xil/xil_DRP_BusMux.rst | 7 +++++++ docs/IPCores/xil/xil_DRP_BusSync.rst | 7 +++++++ docs/IPCores/xil/xil_ICAP.rst | 7 +++++++ docs/IPCores/xil/xil_Reconfigurator.rst | 7 +++++++ docs/IPCores/xil/xil_SystemMonitor.rst | 7 +++++++ docs/IPCores/xil/xil_SystemMonitor_Series7.rst | 7 +++++++ docs/IPCores/xil/xil_SystemMonitor_Virtex6.rst | 7 +++++++ docs/PyInfrastructure/index.rst | 8 +------- docs/UsingPoC/Requirements.rst | 1 + docs/_templates/autoapi/module.rst | 7 +++++++ docs/_templates/autoapi/script.rst | 7 +++++++ 202 files changed, 1402 insertions(+), 7 deletions(-) diff --git a/docs/IPCores/arith/arith_addw.rst b/docs/IPCores/arith/arith_addw.rst index b6884c8f..80f450fd 100644 --- a/docs/IPCores/arith/arith_addw.rst +++ b/docs/IPCores/arith/arith_addw.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arith_addw: PoC.arith.addw diff --git a/docs/IPCores/arith/arith_bcdcollect.rst b/docs/IPCores/arith/arith_bcdcollect.rst index 9fcf9e1b..a8aec2c6 100644 --- a/docs/IPCores/arith/arith_bcdcollect.rst +++ b/docs/IPCores/arith/arith_bcdcollect.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arith_bcdcollect: PoC.arith.bcdcollect diff --git a/docs/IPCores/arith/arith_carrychain_inc.rst b/docs/IPCores/arith/arith_carrychain_inc.rst index aeb6eedd..03f8e481 100644 --- a/docs/IPCores/arith/arith_carrychain_inc.rst +++ b/docs/IPCores/arith/arith_carrychain_inc.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arith_carrychain_inc: PoC.arith.carrychain_inc diff --git a/docs/IPCores/arith/arith_convert_bin2bcd.rst b/docs/IPCores/arith/arith_convert_bin2bcd.rst index 4267b204..ca4322e6 100644 --- a/docs/IPCores/arith/arith_convert_bin2bcd.rst +++ b/docs/IPCores/arith/arith_convert_bin2bcd.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arith_convert_bin2bcd: PoC.arith.convert_bin2bcd diff --git a/docs/IPCores/arith/arith_counter_bcd.rst b/docs/IPCores/arith/arith_counter_bcd.rst index 6e683c06..33ffbb93 100644 --- a/docs/IPCores/arith/arith_counter_bcd.rst +++ b/docs/IPCores/arith/arith_counter_bcd.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arith_counter_bcd: PoC.arith.counter_bcd diff --git a/docs/IPCores/arith/arith_counter_free.rst b/docs/IPCores/arith/arith_counter_free.rst index 741f2d91..b4b702e8 100644 --- a/docs/IPCores/arith/arith_counter_free.rst +++ b/docs/IPCores/arith/arith_counter_free.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arith_counter_free: PoC.arith.counter_free diff --git a/docs/IPCores/arith/arith_counter_gray.rst b/docs/IPCores/arith/arith_counter_gray.rst index d6ee1e68..5078f9ba 100644 --- a/docs/IPCores/arith/arith_counter_gray.rst +++ b/docs/IPCores/arith/arith_counter_gray.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arith_counter_gray: PoC.arith.counter_gray diff --git a/docs/IPCores/arith/arith_counter_ring.rst b/docs/IPCores/arith/arith_counter_ring.rst index c7541bcb..603fcf24 100644 --- a/docs/IPCores/arith/arith_counter_ring.rst +++ b/docs/IPCores/arith/arith_counter_ring.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arith_counter_ring: PoC.arith.counter_ring diff --git a/docs/IPCores/arith/arith_div.rst b/docs/IPCores/arith/arith_div.rst index 2a3ee2ad..71963fa9 100644 --- a/docs/IPCores/arith/arith_div.rst +++ b/docs/IPCores/arith/arith_div.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arith_div: PoC.arith.div diff --git a/docs/IPCores/arith/arith_firstone.rst b/docs/IPCores/arith/arith_firstone.rst index 10755ee9..c693f15e 100644 --- a/docs/IPCores/arith/arith_firstone.rst +++ b/docs/IPCores/arith/arith_firstone.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arith_firstone: PoC.arith.firstone diff --git a/docs/IPCores/arith/arith_muls_wide.rst b/docs/IPCores/arith/arith_muls_wide.rst index 68ed6a99..380105ea 100644 --- a/docs/IPCores/arith/arith_muls_wide.rst +++ b/docs/IPCores/arith/arith_muls_wide.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arith_muls_wide: PoC.arith.muls_wide diff --git a/docs/IPCores/arith/arith_prefix_and.rst b/docs/IPCores/arith/arith_prefix_and.rst index df992f4a..18747671 100644 --- a/docs/IPCores/arith/arith_prefix_and.rst +++ b/docs/IPCores/arith/arith_prefix_and.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arith_prefix_and: PoC.arith.prefix_and diff --git a/docs/IPCores/arith/arith_prefix_or.rst b/docs/IPCores/arith/arith_prefix_or.rst index 22ca9db2..e7d41994 100644 --- a/docs/IPCores/arith/arith_prefix_or.rst +++ b/docs/IPCores/arith/arith_prefix_or.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arith_prefix_or: PoC.arith.prefix_or diff --git a/docs/IPCores/arith/arith_prng.rst b/docs/IPCores/arith/arith_prng.rst index 935f8b80..1b04974c 100644 --- a/docs/IPCores/arith/arith_prng.rst +++ b/docs/IPCores/arith/arith_prng.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arith_prng: PoC.arith.prng diff --git a/docs/IPCores/arith/arith_same.rst b/docs/IPCores/arith/arith_same.rst index 605f25df..9ac34e36 100644 --- a/docs/IPCores/arith/arith_same.rst +++ b/docs/IPCores/arith/arith_same.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arith_same: PoC.arith.same diff --git a/docs/IPCores/arith/arith_scaler.rst b/docs/IPCores/arith/arith_scaler.rst index 6ca0174f..7ea0e576 100644 --- a/docs/IPCores/arith/arith_scaler.rst +++ b/docs/IPCores/arith/arith_scaler.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arith_scaler: PoC.arith.scaler diff --git a/docs/IPCores/arith/arith_shifter_barrel.rst b/docs/IPCores/arith/arith_shifter_barrel.rst index ee45718b..70ca9fe1 100644 --- a/docs/IPCores/arith/arith_shifter_barrel.rst +++ b/docs/IPCores/arith/arith_shifter_barrel.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arith_shifter_barrel: PoC.arith.shifter_barrel diff --git a/docs/IPCores/arith/arith_sqrt.rst b/docs/IPCores/arith/arith_sqrt.rst index f69b40d1..bce7f010 100644 --- a/docs/IPCores/arith/arith_sqrt.rst +++ b/docs/IPCores/arith/arith_sqrt.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arith_sqrt: PoC.arith.sqrt diff --git a/docs/IPCores/bus/bus_Arbiter.rst b/docs/IPCores/bus/bus_Arbiter.rst index becfeccd..ed049fbc 100644 --- a/docs/IPCores/bus/bus_Arbiter.rst +++ b/docs/IPCores/bus/bus_Arbiter.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:bus_Arbiter: PoC.bus.Arbiter diff --git a/docs/IPCores/bus/stream/stream_Buffer.rst b/docs/IPCores/bus/stream/stream_Buffer.rst index 1f304032..404b79f0 100644 --- a/docs/IPCores/bus/stream/stream_Buffer.rst +++ b/docs/IPCores/bus/stream/stream_Buffer.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:stream_Buffer: PoC.bus.stream.Buffer diff --git a/docs/IPCores/bus/stream/stream_DeMux.rst b/docs/IPCores/bus/stream/stream_DeMux.rst index 46a9f747..e9c88780 100644 --- a/docs/IPCores/bus/stream/stream_DeMux.rst +++ b/docs/IPCores/bus/stream/stream_DeMux.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:stream_DeMux: PoC.bus.stream.DeMux diff --git a/docs/IPCores/bus/stream/stream_FrameGenerator.rst b/docs/IPCores/bus/stream/stream_FrameGenerator.rst index 9e4c36f5..372aa835 100644 --- a/docs/IPCores/bus/stream/stream_FrameGenerator.rst +++ b/docs/IPCores/bus/stream/stream_FrameGenerator.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:stream_FrameGenerator: PoC.bus.stream.FrameGenerator diff --git a/docs/IPCores/bus/stream/stream_Mirror.rst b/docs/IPCores/bus/stream/stream_Mirror.rst index c4796273..d8263ec4 100644 --- a/docs/IPCores/bus/stream/stream_Mirror.rst +++ b/docs/IPCores/bus/stream/stream_Mirror.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:stream_Mirror: PoC.bus.stream.Mirror diff --git a/docs/IPCores/bus/stream/stream_Mux.rst b/docs/IPCores/bus/stream/stream_Mux.rst index 0c08de95..348d1e3f 100644 --- a/docs/IPCores/bus/stream/stream_Mux.rst +++ b/docs/IPCores/bus/stream/stream_Mux.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:stream_Mux: PoC.bus.stream.Mux diff --git a/docs/IPCores/bus/stream/stream_Sink.rst b/docs/IPCores/bus/stream/stream_Sink.rst index 1066b091..fd94e9f3 100644 --- a/docs/IPCores/bus/stream/stream_Sink.rst +++ b/docs/IPCores/bus/stream/stream_Sink.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:stream_Sink: PoC.bus.stream.Sink diff --git a/docs/IPCores/bus/stream/stream_Source.rst b/docs/IPCores/bus/stream/stream_Source.rst index 1e3a5d76..c25768fd 100644 --- a/docs/IPCores/bus/stream/stream_Source.rst +++ b/docs/IPCores/bus/stream/stream_Source.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:stream_Source: PoC.bus.stream.Source diff --git a/docs/IPCores/bus/wb/wb_fifo_adapter.rst b/docs/IPCores/bus/wb/wb_fifo_adapter.rst index 52ef58e2..f98dc881 100644 --- a/docs/IPCores/bus/wb/wb_fifo_adapter.rst +++ b/docs/IPCores/bus/wb/wb_fifo_adapter.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:wb_fifo_adapter: PoC.bus.wb.fifo_adapter diff --git a/docs/IPCores/bus/wb/wb_ocram.rst b/docs/IPCores/bus/wb/wb_ocram.rst index b6c3e2d8..56e8a887 100644 --- a/docs/IPCores/bus/wb/wb_ocram.rst +++ b/docs/IPCores/bus/wb/wb_ocram.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ocram_wb: PoC.bus.wb.ocram diff --git a/docs/IPCores/bus/wb/wb_uart_wrapper.rst b/docs/IPCores/bus/wb/wb_uart_wrapper.rst index 2036cff0..08bf064a 100644 --- a/docs/IPCores/bus/wb/wb_uart_wrapper.rst +++ b/docs/IPCores/bus/wb/wb_uart_wrapper.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:uart_wb: PoC.bus.wb.uart_wrapper diff --git a/docs/IPCores/cache/cache_cpu.rst b/docs/IPCores/cache/cache_cpu.rst index 55274fa1..15020678 100644 --- a/docs/IPCores/cache/cache_cpu.rst +++ b/docs/IPCores/cache/cache_cpu.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:cache_cpu: PoC.cache.cpu diff --git a/docs/IPCores/cache/cache_mem.rst b/docs/IPCores/cache/cache_mem.rst index a0da1e10..e7e931b8 100644 --- a/docs/IPCores/cache/cache_mem.rst +++ b/docs/IPCores/cache/cache_mem.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:cache_mem: PoC.cache.mem diff --git a/docs/IPCores/cache/cache_par.rst b/docs/IPCores/cache/cache_par.rst index 821b84f7..8bf8d0f7 100644 --- a/docs/IPCores/cache/cache_par.rst +++ b/docs/IPCores/cache/cache_par.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:cache_par: PoC.cache.par diff --git a/docs/IPCores/cache/cache_par2.rst b/docs/IPCores/cache/cache_par2.rst index 1c45ad63..f025e904 100644 --- a/docs/IPCores/cache/cache_par2.rst +++ b/docs/IPCores/cache/cache_par2.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:cache_par2: PoC.cache.par2 diff --git a/docs/IPCores/cache/cache_replacement_policy.rst b/docs/IPCores/cache/cache_replacement_policy.rst index da989e77..fc53ddb7 100644 --- a/docs/IPCores/cache/cache_replacement_policy.rst +++ b/docs/IPCores/cache/cache_replacement_policy.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:cache_replacement_policy: PoC.cache.replacement_policy diff --git a/docs/IPCores/cache/cache_tagunit_par.rst b/docs/IPCores/cache/cache_tagunit_par.rst index b0d9e6a8..d06d32c3 100644 --- a/docs/IPCores/cache/cache_tagunit_par.rst +++ b/docs/IPCores/cache/cache_tagunit_par.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:cache_tagunit_par: PoC.cache.tagunit_par diff --git a/docs/IPCores/cache/cache_tagunit_seq.rst b/docs/IPCores/cache/cache_tagunit_seq.rst index 3c6e0af9..b3439f23 100644 --- a/docs/IPCores/cache/cache_tagunit_seq.rst +++ b/docs/IPCores/cache/cache_tagunit_seq.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:cache_tagunit_seq: PoC.cache.tagunit_seq diff --git a/docs/IPCores/comm/comm_crc.rst b/docs/IPCores/comm/comm_crc.rst index 29607682..f8b22284 100644 --- a/docs/IPCores/comm/comm_crc.rst +++ b/docs/IPCores/comm/comm_crc.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:comm_crc: PoC.comm.crc diff --git a/docs/IPCores/comm/comm_scramble.rst b/docs/IPCores/comm/comm_scramble.rst index 031e60f7..35b45b67 100644 --- a/docs/IPCores/comm/comm_scramble.rst +++ b/docs/IPCores/comm/comm_scramble.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:comm_scramble: PoC.comm.scramble diff --git a/docs/IPCores/fifo/fifo_cc_got.rst b/docs/IPCores/fifo/fifo_cc_got.rst index 2e32c363..ac7cf083 100644 --- a/docs/IPCores/fifo/fifo_cc_got.rst +++ b/docs/IPCores/fifo/fifo_cc_got.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:fifo_cc_got: PoC.fifo.cc_got diff --git a/docs/IPCores/fifo/fifo_cc_got_tempgot.rst b/docs/IPCores/fifo/fifo_cc_got_tempgot.rst index 80420277..6e8a2f82 100644 --- a/docs/IPCores/fifo/fifo_cc_got_tempgot.rst +++ b/docs/IPCores/fifo/fifo_cc_got_tempgot.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:fifo_cc_got_tempgot: PoC.fifo.cc_got_tempgot diff --git a/docs/IPCores/fifo/fifo_cc_got_tempput.rst b/docs/IPCores/fifo/fifo_cc_got_tempput.rst index 7035089d..1cc78a19 100644 --- a/docs/IPCores/fifo/fifo_cc_got_tempput.rst +++ b/docs/IPCores/fifo/fifo_cc_got_tempput.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:fifo_cc_got_tempput: PoC.fifo.cc_got_tempput diff --git a/docs/IPCores/fifo/fifo_dc_got_sm.rst b/docs/IPCores/fifo/fifo_dc_got_sm.rst index 810f11c0..7a175fd8 100644 --- a/docs/IPCores/fifo/fifo_dc_got_sm.rst +++ b/docs/IPCores/fifo/fifo_dc_got_sm.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:fifo_dc_got_sm: PoC.fifo.dc_got_sm diff --git a/docs/IPCores/fifo/fifo_glue.rst b/docs/IPCores/fifo/fifo_glue.rst index 9734977c..ef2013ba 100644 --- a/docs/IPCores/fifo/fifo_glue.rst +++ b/docs/IPCores/fifo/fifo_glue.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:fifo_glue: PoC.fifo.glue diff --git a/docs/IPCores/fifo/fifo_ic_assembly.rst b/docs/IPCores/fifo/fifo_ic_assembly.rst index 66feb06a..a1daa7b2 100644 --- a/docs/IPCores/fifo/fifo_ic_assembly.rst +++ b/docs/IPCores/fifo/fifo_ic_assembly.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:fifo_ic_assembly: PoC.fifo.ic_assembly diff --git a/docs/IPCores/fifo/fifo_ic_got.rst b/docs/IPCores/fifo/fifo_ic_got.rst index 3a6e5dbc..6785e7d0 100644 --- a/docs/IPCores/fifo/fifo_ic_got.rst +++ b/docs/IPCores/fifo/fifo_ic_got.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:fifo_ic_got: PoC.fifo.ic_got diff --git a/docs/IPCores/fifo/fifo_shift.rst b/docs/IPCores/fifo/fifo_shift.rst index 25f3162b..83bfa04e 100644 --- a/docs/IPCores/fifo/fifo_shift.rst +++ b/docs/IPCores/fifo/fifo_shift.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:fifo_shift: PoC.fifo.shift diff --git a/docs/IPCores/io/ddrio/ddrio_in.rst b/docs/IPCores/io/ddrio/ddrio_in.rst index 20711814..927f3f47 100644 --- a/docs/IPCores/io/ddrio/ddrio_in.rst +++ b/docs/IPCores/io/ddrio/ddrio_in.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ddrio_in: PoC.io.ddrio.in diff --git a/docs/IPCores/io/ddrio/ddrio_inout.rst b/docs/IPCores/io/ddrio/ddrio_inout.rst index 56dfd31c..de0708df 100644 --- a/docs/IPCores/io/ddrio/ddrio_inout.rst +++ b/docs/IPCores/io/ddrio/ddrio_inout.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ddrio_inout: PoC.io.ddrio.inout diff --git a/docs/IPCores/io/ddrio/ddrio_out.rst b/docs/IPCores/io/ddrio/ddrio_out.rst index 569ad84b..d1acc9fa 100644 --- a/docs/IPCores/io/ddrio/ddrio_out.rst +++ b/docs/IPCores/io/ddrio/ddrio_out.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ddrio_out: PoC.io.ddrio.out diff --git a/docs/IPCores/io/iic/iic_BusController.rst b/docs/IPCores/io/iic/iic_BusController.rst index 170035e7..5f605701 100644 --- a/docs/IPCores/io/iic/iic_BusController.rst +++ b/docs/IPCores/io/iic/iic_BusController.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:iic_BusController: PoC.io.iic.BusController diff --git a/docs/IPCores/io/iic/iic_Controller.rst b/docs/IPCores/io/iic/iic_Controller.rst index cd76f285..bb48406c 100644 --- a/docs/IPCores/io/iic/iic_Controller.rst +++ b/docs/IPCores/io/iic/iic_Controller.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:iic_Controller: PoC.io.iic.Controller diff --git a/docs/IPCores/io/iic/iic_Controller_SFF8431.rst b/docs/IPCores/io/iic/iic_Controller_SFF8431.rst index 0504ccc8..c4c5c1b0 100644 --- a/docs/IPCores/io/iic/iic_Controller_SFF8431.rst +++ b/docs/IPCores/io/iic/iic_Controller_SFF8431.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:IICController_SFF8431: PoC.io.iic.Controller_SFF8431 diff --git a/docs/IPCores/io/iic/iic_Switch_PCA9548A.rst b/docs/IPCores/io/iic/iic_Switch_PCA9548A.rst index cc16c51c..d369b936 100644 --- a/docs/IPCores/io/iic/iic_Switch_PCA9548A.rst +++ b/docs/IPCores/io/iic/iic_Switch_PCA9548A.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:iic_Switch_PCA9548A: PoC.io.iic.Switch_PCA9548A diff --git a/docs/IPCores/io/io_7SegmentMux_BCD.rst b/docs/IPCores/io/io_7SegmentMux_BCD.rst index 282b5263..b0946660 100644 --- a/docs/IPCores/io/io_7SegmentMux_BCD.rst +++ b/docs/IPCores/io/io_7SegmentMux_BCD.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:io_7SegmentMux_BCD: PoC.io.7SegmentMux_BCD diff --git a/docs/IPCores/io/io_7SegmentMux_HEX.rst b/docs/IPCores/io/io_7SegmentMux_HEX.rst index f039534b..dd3c016b 100644 --- a/docs/IPCores/io/io_7SegmentMux_HEX.rst +++ b/docs/IPCores/io/io_7SegmentMux_HEX.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:io_7SegmentMux_HEX: PoC.io.7SegmentMux_HEX diff --git a/docs/IPCores/io/io_Debounce.rst b/docs/IPCores/io/io_Debounce.rst index e56df96b..178d724a 100644 --- a/docs/IPCores/io/io_Debounce.rst +++ b/docs/IPCores/io/io_Debounce.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:io_Debounce: PoC.io.Debounce diff --git a/docs/IPCores/io/io_FanControl.rst b/docs/IPCores/io/io_FanControl.rst index 6858fc80..f2c015d9 100644 --- a/docs/IPCores/io/io_FanControl.rst +++ b/docs/IPCores/io/io_FanControl.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:io_FanControl: PoC.io.FanControl diff --git a/docs/IPCores/io/io_FrequencyCounter.rst b/docs/IPCores/io/io_FrequencyCounter.rst index ef678db1..da769a8e 100644 --- a/docs/IPCores/io/io_FrequencyCounter.rst +++ b/docs/IPCores/io/io_FrequencyCounter.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:io_FrequencyCounter: PoC.io.FrequencyCounter diff --git a/docs/IPCores/io/io_GlitchFilter.rst b/docs/IPCores/io/io_GlitchFilter.rst index 21a8a8d3..b510c0e7 100644 --- a/docs/IPCores/io/io_GlitchFilter.rst +++ b/docs/IPCores/io/io_GlitchFilter.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:io_GlitchFilter: PoC.io.GlitchFilter diff --git a/docs/IPCores/io/io_KeyPadScanner.rst b/docs/IPCores/io/io_KeyPadScanner.rst index 9e894bcc..68d0219f 100644 --- a/docs/IPCores/io/io_KeyPadScanner.rst +++ b/docs/IPCores/io/io_KeyPadScanner.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:io_KeyPadScanner: PoC.io.KeyPadScanner diff --git a/docs/IPCores/io/io_PulseWidthModulation.rst b/docs/IPCores/io/io_PulseWidthModulation.rst index 43f23ee2..907fe614 100644 --- a/docs/IPCores/io/io_PulseWidthModulation.rst +++ b/docs/IPCores/io/io_PulseWidthModulation.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:io_PulseWidthModulation: PoC.io.PulseWidthModulation diff --git a/docs/IPCores/io/io_TimingCounter.rst b/docs/IPCores/io/io_TimingCounter.rst index eaaf8251..5e73423b 100644 --- a/docs/IPCores/io/io_TimingCounter.rst +++ b/docs/IPCores/io/io_TimingCounter.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:io_TimingCounter: PoC.io.TimingCounter diff --git a/docs/IPCores/io/lcd/lcd_LCDBuffer.rst b/docs/IPCores/io/lcd/lcd_LCDBuffer.rst index 4803a156..71f4ee13 100644 --- a/docs/IPCores/io/lcd/lcd_LCDBuffer.rst +++ b/docs/IPCores/io/lcd/lcd_LCDBuffer.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:lcd_LCDBuffer: PoC.io.lcd.LCDBuffer diff --git a/docs/IPCores/io/lcd/lcd_LCDBusController.rst b/docs/IPCores/io/lcd/lcd_LCDBusController.rst index 45d3a0ef..3df150ad 100644 --- a/docs/IPCores/io/lcd/lcd_LCDBusController.rst +++ b/docs/IPCores/io/lcd/lcd_LCDBusController.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:lcd_LCDBusController: PoC.io.lcd.LCDBusController diff --git a/docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst b/docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst index 9bc9f717..ddf85c92 100644 --- a/docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst +++ b/docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:lcd_LCDController_KS0066U: PoC.io.lcd.LCDController_KS0066U diff --git a/docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst b/docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst index 576e9c3d..ed9a0b7b 100644 --- a/docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst +++ b/docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:lcd_LCDSynchronizer: PoC.io.lcd.LCDSynchronizer diff --git a/docs/IPCores/io/lcd/lcd_dotmatrix.rst b/docs/IPCores/io/lcd/lcd_dotmatrix.rst index 300ca5ff..5604b7ad 100644 --- a/docs/IPCores/io/lcd/lcd_dotmatrix.rst +++ b/docs/IPCores/io/lcd/lcd_dotmatrix.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:lcd_dotmatrix: PoC.io.lcd.dotmatrix diff --git a/docs/IPCores/io/mdio/mdio_Controller.rst b/docs/IPCores/io/mdio/mdio_Controller.rst index c3b4c654..ad603bb2 100644 --- a/docs/IPCores/io/mdio/mdio_Controller.rst +++ b/docs/IPCores/io/mdio/mdio_Controller.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:mdio_Controller: PoC.io.mdio.Controller diff --git a/docs/IPCores/io/mdio/mdio_IIC_Adapter.rst b/docs/IPCores/io/mdio/mdio_IIC_Adapter.rst index fea3d8dd..20181eb3 100644 --- a/docs/IPCores/io/mdio/mdio_IIC_Adapter.rst +++ b/docs/IPCores/io/mdio/mdio_IIC_Adapter.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:mdio_IIC_Adapter: PoC.io.mdio.IIC_Adapter diff --git a/docs/IPCores/io/pio/pio_fifo_in.rst b/docs/IPCores/io/pio/pio_fifo_in.rst index 3c1564a0..f2e57d82 100644 --- a/docs/IPCores/io/pio/pio_fifo_in.rst +++ b/docs/IPCores/io/pio/pio_fifo_in.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:pio_fifo_in: PoC.io.pio.fifo_in diff --git a/docs/IPCores/io/pio/pio_fifo_out.rst b/docs/IPCores/io/pio/pio_fifo_out.rst index 7d7f7aa2..e50bbdb7 100644 --- a/docs/IPCores/io/pio/pio_fifo_out.rst +++ b/docs/IPCores/io/pio/pio_fifo_out.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:pio_fifo_out: PoC.io.pio.fifo_out diff --git a/docs/IPCores/io/pio/pio_in.rst b/docs/IPCores/io/pio/pio_in.rst index 89365672..e4869f25 100644 --- a/docs/IPCores/io/pio/pio_in.rst +++ b/docs/IPCores/io/pio/pio_in.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:pio_in: PoC.io.pio.in diff --git a/docs/IPCores/io/pio/pio_out.rst b/docs/IPCores/io/pio/pio_out.rst index b9a8c652..a7b895c7 100644 --- a/docs/IPCores/io/pio/pio_out.rst +++ b/docs/IPCores/io/pio/pio_out.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:pio_out: PoC.io.pio.out diff --git a/docs/IPCores/io/pmod/pmod_KYPD.rst b/docs/IPCores/io/pmod/pmod_KYPD.rst index 338a9e65..0f7d8f50 100644 --- a/docs/IPCores/io/pmod/pmod_KYPD.rst +++ b/docs/IPCores/io/pmod/pmod_KYPD.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:pmod_KYPD: PoC.io.pmod.KYPD diff --git a/docs/IPCores/io/pmod/pmod_SSD.rst b/docs/IPCores/io/pmod/pmod_SSD.rst index f59e2f3d..3e13a55b 100644 --- a/docs/IPCores/io/pmod/pmod_SSD.rst +++ b/docs/IPCores/io/pmod/pmod_SSD.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:pmod_SSD: PoC.io.pmod.SSD diff --git a/docs/IPCores/io/pmod/pmod_USBUART.rst b/docs/IPCores/io/pmod/pmod_USBUART.rst index db37da9d..a1d34d33 100644 --- a/docs/IPCores/io/pmod/pmod_USBUART.rst +++ b/docs/IPCores/io/pmod/pmod_USBUART.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:pmod_USBUART: PoC.io.pmod.USBUART diff --git a/docs/IPCores/io/uart/uart_bclk.rst b/docs/IPCores/io/uart/uart_bclk.rst index c4e848c3..32710006 100644 --- a/docs/IPCores/io/uart/uart_bclk.rst +++ b/docs/IPCores/io/uart/uart_bclk.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:uart_bclk: PoC.io.uart.bclk diff --git a/docs/IPCores/io/uart/uart_fifo.rst b/docs/IPCores/io/uart/uart_fifo.rst index 06d56bf3..9730b0c8 100644 --- a/docs/IPCores/io/uart/uart_fifo.rst +++ b/docs/IPCores/io/uart/uart_fifo.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:uart_fifo: PoC.io.uart.fifo diff --git a/docs/IPCores/io/uart/uart_ft245.rst b/docs/IPCores/io/uart/uart_ft245.rst index 7ec4cb90..3d2845c4 100644 --- a/docs/IPCores/io/uart/uart_ft245.rst +++ b/docs/IPCores/io/uart/uart_ft245.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:uart_ft245: PoC.io.uart.ft245 diff --git a/docs/IPCores/io/uart/uart_rx.rst b/docs/IPCores/io/uart/uart_rx.rst index 90fba9c0..094445e0 100644 --- a/docs/IPCores/io/uart/uart_rx.rst +++ b/docs/IPCores/io/uart/uart_rx.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:uart_rx: PoC.io.uart.rx diff --git a/docs/IPCores/io/uart/uart_tx.rst b/docs/IPCores/io/uart/uart_tx.rst index 5ec05da9..47911a65 100644 --- a/docs/IPCores/io/uart/uart_tx.rst +++ b/docs/IPCores/io/uart/uart_tx.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:uart_tx: PoC.io.uart.tx diff --git a/docs/IPCores/io/vga/vga_phy.rst b/docs/IPCores/io/vga/vga_phy.rst index 1e08bc4d..d928c1a8 100644 --- a/docs/IPCores/io/vga/vga_phy.rst +++ b/docs/IPCores/io/vga/vga_phy.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:vga_phy: PoC.io.vga.phy diff --git a/docs/IPCores/io/vga/vga_phy_ch7301c.rst b/docs/IPCores/io/vga/vga_phy_ch7301c.rst index fc82c28f..fed2655c 100644 --- a/docs/IPCores/io/vga/vga_phy_ch7301c.rst +++ b/docs/IPCores/io/vga/vga_phy_ch7301c.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:vga_phy_ch7301c: PoC.io.vga.phy_ch7301c diff --git a/docs/IPCores/io/vga/vga_timing.rst b/docs/IPCores/io/vga/vga_timing.rst index 4cff541f..c41c34f2 100644 --- a/docs/IPCores/io/vga/vga_timing.rst +++ b/docs/IPCores/io/vga/vga_timing.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:vga_timing: PoC.io.vga.timing diff --git a/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst b/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst index 62ba441c..a87e1f96 100644 --- a/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst +++ b/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ddr2_mem2mig_adapter_Spartan6: PoC.mem.ddr2.mem2mig_adapter_Spartan6 diff --git a/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst b/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst index f02332da..46b46c38 100644 --- a/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst +++ b/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ddr3_mem2mig_adapter_Series7: PoC.mem.ddr3.mem2mig_adapter_Series7 diff --git a/docs/IPCores/mem/lut/lut_Sine.rst b/docs/IPCores/mem/lut/lut_Sine.rst index 20d21936..236f3939 100644 --- a/docs/IPCores/mem/lut/lut_Sine.rst +++ b/docs/IPCores/mem/lut/lut_Sine.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:lut_Sine: PoC.mem.lut.Sine diff --git a/docs/IPCores/mem/ocram/ocram_esdp.rst b/docs/IPCores/mem/ocram/ocram_esdp.rst index e34c7bb5..d6276cc7 100644 --- a/docs/IPCores/mem/ocram/ocram_esdp.rst +++ b/docs/IPCores/mem/ocram/ocram_esdp.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ocram_esdp: PoC.mem.ocram.esdp diff --git a/docs/IPCores/mem/ocram/ocram_sdp.rst b/docs/IPCores/mem/ocram/ocram_sdp.rst index a55989eb..8467dead 100644 --- a/docs/IPCores/mem/ocram/ocram_sdp.rst +++ b/docs/IPCores/mem/ocram/ocram_sdp.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ocram_sdp: PoC.mem.ocram.sdp diff --git a/docs/IPCores/mem/ocram/ocram_sdp_wf.rst b/docs/IPCores/mem/ocram/ocram_sdp_wf.rst index 66561a39..7933e540 100644 --- a/docs/IPCores/mem/ocram/ocram_sdp_wf.rst +++ b/docs/IPCores/mem/ocram/ocram_sdp_wf.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ocram_sdp_wf: PoC.mem.ocram.sdp_wf diff --git a/docs/IPCores/mem/ocram/ocram_sp.rst b/docs/IPCores/mem/ocram/ocram_sp.rst index 8318520e..e749c5b3 100644 --- a/docs/IPCores/mem/ocram/ocram_sp.rst +++ b/docs/IPCores/mem/ocram/ocram_sp.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ocram_sp: PoC.mem.ocram.sp diff --git a/docs/IPCores/mem/ocram/ocram_tdp.rst b/docs/IPCores/mem/ocram/ocram_tdp.rst index 91bee648..b71e0353 100644 --- a/docs/IPCores/mem/ocram/ocram_tdp.rst +++ b/docs/IPCores/mem/ocram/ocram_tdp.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ocram_tdp: PoC.mem.ocram.tdp diff --git a/docs/IPCores/mem/ocram/ocram_tdp_sim.rst b/docs/IPCores/mem/ocram/ocram_tdp_sim.rst index 050c0154..db5dbdff 100644 --- a/docs/IPCores/mem/ocram/ocram_tdp_sim.rst +++ b/docs/IPCores/mem/ocram/ocram_tdp_sim.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ocram_tdp_sim: PoC.mem.ocram.tdp_sim diff --git a/docs/IPCores/mem/ocram/ocram_tdp_wf.rst b/docs/IPCores/mem/ocram/ocram_tdp_wf.rst index 59f51b2a..22c7d623 100644 --- a/docs/IPCores/mem/ocram/ocram_tdp_wf.rst +++ b/docs/IPCores/mem/ocram/ocram_tdp_wf.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ocram_tdp_wf: PoC.mem.ocram.tdp_wf diff --git a/docs/IPCores/mem/ocrom/ocrom_dp.rst b/docs/IPCores/mem/ocrom/ocrom_dp.rst index 53f67d78..cc69c160 100644 --- a/docs/IPCores/mem/ocrom/ocrom_dp.rst +++ b/docs/IPCores/mem/ocrom/ocrom_dp.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ocrom_dp: PoC.mem.ocrom.dp diff --git a/docs/IPCores/mem/ocrom/ocrom_sp.rst b/docs/IPCores/mem/ocrom/ocrom_sp.rst index ae2e4ed3..488bc59b 100644 --- a/docs/IPCores/mem/ocrom/ocrom_sp.rst +++ b/docs/IPCores/mem/ocrom/ocrom_sp.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ocrom_sp: PoC.mem.ocrom.sp diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst b/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst index 854dbf14..78b9c9c5 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:sdram_ctrl_de0: PoC.mem.sdram.ctrl_de0 diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst b/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst index 4641c2eb..f6cae9cf 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:sdram_ctrl_fsm: PoC.mem.sdram.ctrl_fsm diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst b/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst index 8029a2d4..667b32b3 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:sdram_ctrl_phy_de0: PoC.mem.sdram.ctrl_phy_de0 diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst b/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst index 111958c1..a15c736d 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:sdram_ctrl_phy_s3esk: PoC.mem.sdram.ctrl_phy_s3esk diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst b/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst index c4f927a2..e1403dc7 100644 --- a/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:sdram_ctrl_s3esk: PoC.mem.sdram.ctrl_s3esk diff --git a/docs/IPCores/misc/filter/filter_and.rst b/docs/IPCores/misc/filter/filter_and.rst index 3118b285..53745bcc 100644 --- a/docs/IPCores/misc/filter/filter_and.rst +++ b/docs/IPCores/misc/filter/filter_and.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:filter_and: PoC.misc.filter.and diff --git a/docs/IPCores/misc/filter/filter_mean.rst b/docs/IPCores/misc/filter/filter_mean.rst index b1d4b66a..e3b681b9 100644 --- a/docs/IPCores/misc/filter/filter_mean.rst +++ b/docs/IPCores/misc/filter/filter_mean.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:filter_mean: PoC.misc.filter.mean diff --git a/docs/IPCores/misc/filter/filter_or.rst b/docs/IPCores/misc/filter/filter_or.rst index 6d3151eb..0fb428eb 100644 --- a/docs/IPCores/misc/filter/filter_or.rst +++ b/docs/IPCores/misc/filter/filter_or.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:filter_or: PoC.misc.filter.or diff --git a/docs/IPCores/misc/gearbox/gearbox_down_cc.rst b/docs/IPCores/misc/gearbox/gearbox_down_cc.rst index 72eb096f..39a760db 100644 --- a/docs/IPCores/misc/gearbox/gearbox_down_cc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_down_cc.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:gearbox_down_cc: PoC.misc.gearbox.down_cc diff --git a/docs/IPCores/misc/gearbox/gearbox_down_dc.rst b/docs/IPCores/misc/gearbox/gearbox_down_dc.rst index 1470f504..4556ca02 100644 --- a/docs/IPCores/misc/gearbox/gearbox_down_dc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_down_dc.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:gearbox_down_dc: PoC.misc.gearbox.down_dc diff --git a/docs/IPCores/misc/gearbox/gearbox_up_cc.rst b/docs/IPCores/misc/gearbox/gearbox_up_cc.rst index c76107e0..81114563 100644 --- a/docs/IPCores/misc/gearbox/gearbox_up_cc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_up_cc.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:gearbox_up_cc: PoC.misc.gearbox.up_cc diff --git a/docs/IPCores/misc/gearbox/gearbox_up_dc.rst b/docs/IPCores/misc/gearbox/gearbox_up_dc.rst index 2df5fef6..495bdffb 100644 --- a/docs/IPCores/misc/gearbox/gearbox_up_dc.rst +++ b/docs/IPCores/misc/gearbox/gearbox_up_dc.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:gearbox_up_dc: PoC.misc.gearbox.up_dc diff --git a/docs/IPCores/misc/misc_BitwidthConverter.rst b/docs/IPCores/misc/misc_BitwidthConverter.rst index 77a1d6b9..4c4f05a2 100644 --- a/docs/IPCores/misc/misc_BitwidthConverter.rst +++ b/docs/IPCores/misc/misc_BitwidthConverter.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:misc_BitwidthConverter: PoC.misc.BitwidthConverter diff --git a/docs/IPCores/misc/misc_ByteAligner.rst b/docs/IPCores/misc/misc_ByteAligner.rst index 3352d216..d07ef3ce 100644 --- a/docs/IPCores/misc/misc_ByteAligner.rst +++ b/docs/IPCores/misc/misc_ByteAligner.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:misc_ByteAligner: PoC.misc.ByteAligner diff --git a/docs/IPCores/misc/misc_Delay.rst b/docs/IPCores/misc/misc_Delay.rst index f4fd8571..90a36c73 100644 --- a/docs/IPCores/misc/misc_Delay.rst +++ b/docs/IPCores/misc/misc_Delay.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:misc_Delay: PoC.misc.Delay diff --git a/docs/IPCores/misc/misc_FrequencyMeasurement.rst b/docs/IPCores/misc/misc_FrequencyMeasurement.rst index abf4290a..26d6c7d0 100644 --- a/docs/IPCores/misc/misc_FrequencyMeasurement.rst +++ b/docs/IPCores/misc/misc_FrequencyMeasurement.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:misc_FrequencyMeasurement: PoC.misc.FrequencyMeasurement diff --git a/docs/IPCores/misc/misc_PulseTrain.rst b/docs/IPCores/misc/misc_PulseTrain.rst index e5186ad5..62ac200d 100644 --- a/docs/IPCores/misc/misc_PulseTrain.rst +++ b/docs/IPCores/misc/misc_PulseTrain.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:misc_PulseTrain: PoC.misc.PulseTrain diff --git a/docs/IPCores/misc/misc_Sequencer.rst b/docs/IPCores/misc/misc_Sequencer.rst index 907e0535..5acfc3f3 100644 --- a/docs/IPCores/misc/misc_Sequencer.rst +++ b/docs/IPCores/misc/misc_Sequencer.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:misc_Sequencer: PoC.misc.Sequencer diff --git a/docs/IPCores/misc/misc_StrobeGenerator.rst b/docs/IPCores/misc/misc_StrobeGenerator.rst index c7f80240..d4191531 100644 --- a/docs/IPCores/misc/misc_StrobeGenerator.rst +++ b/docs/IPCores/misc/misc_StrobeGenerator.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:misc_StrobeGenerator: PoC.misc.StrobeGenerator diff --git a/docs/IPCores/misc/misc_StrobeLimiter.rst b/docs/IPCores/misc/misc_StrobeLimiter.rst index d5fe5d23..185bdf06 100644 --- a/docs/IPCores/misc/misc_StrobeLimiter.rst +++ b/docs/IPCores/misc/misc_StrobeLimiter.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:misc_StrobeLimiter: PoC.misc.StrobeLimiter diff --git a/docs/IPCores/misc/misc_bit_lz.rst b/docs/IPCores/misc/misc_bit_lz.rst index 61db582f..9a269319 100644 --- a/docs/IPCores/misc/misc_bit_lz.rst +++ b/docs/IPCores/misc/misc_bit_lz.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:misc_bit_lz: PoC.misc.bit_lz diff --git a/docs/IPCores/misc/stat/stat_Average.rst b/docs/IPCores/misc/stat/stat_Average.rst index 16367534..012eb182 100644 --- a/docs/IPCores/misc/stat/stat_Average.rst +++ b/docs/IPCores/misc/stat/stat_Average.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:stat_Average: PoC.misc.stat.Average diff --git a/docs/IPCores/misc/stat/stat_Histogram.rst b/docs/IPCores/misc/stat/stat_Histogram.rst index 55c90d0e..93c8b441 100644 --- a/docs/IPCores/misc/stat/stat_Histogram.rst +++ b/docs/IPCores/misc/stat/stat_Histogram.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:stat_Histogram: PoC.misc.stat.Histogram diff --git a/docs/IPCores/misc/stat/stat_Maximum.rst b/docs/IPCores/misc/stat/stat_Maximum.rst index 555e7f26..08b82f37 100644 --- a/docs/IPCores/misc/stat/stat_Maximum.rst +++ b/docs/IPCores/misc/stat/stat_Maximum.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:stat_Maximum: PoC.misc.stat.Maximum diff --git a/docs/IPCores/misc/stat/stat_Minimum.rst b/docs/IPCores/misc/stat/stat_Minimum.rst index b47d71a9..faf868b6 100644 --- a/docs/IPCores/misc/stat/stat_Minimum.rst +++ b/docs/IPCores/misc/stat/stat_Minimum.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:stat_Minimum: PoC.misc.stat.Minimum diff --git a/docs/IPCores/misc/sync/sync_Bits.rst b/docs/IPCores/misc/sync/sync_Bits.rst index 9247b6d4..27c14d0b 100644 --- a/docs/IPCores/misc/sync/sync_Bits.rst +++ b/docs/IPCores/misc/sync/sync_Bits.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:sync_Bits: PoC.misc.sync.Bits diff --git a/docs/IPCores/misc/sync/sync_Command.rst b/docs/IPCores/misc/sync/sync_Command.rst index 33d68f71..29e278f7 100644 --- a/docs/IPCores/misc/sync/sync_Command.rst +++ b/docs/IPCores/misc/sync/sync_Command.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:sync_Command: PoC.misc.sync.Command diff --git a/docs/IPCores/misc/sync/sync_Pulse.rst b/docs/IPCores/misc/sync/sync_Pulse.rst index 36015518..6586a2dc 100644 --- a/docs/IPCores/misc/sync/sync_Pulse.rst +++ b/docs/IPCores/misc/sync/sync_Pulse.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:sync_Pulse: PoC.misc.sync.Pulse diff --git a/docs/IPCores/misc/sync/sync_Reset.rst b/docs/IPCores/misc/sync/sync_Reset.rst index aa6f170a..94d35475 100644 --- a/docs/IPCores/misc/sync/sync_Reset.rst +++ b/docs/IPCores/misc/sync/sync_Reset.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:sync_Reset: PoC.misc.sync.Reset diff --git a/docs/IPCores/misc/sync/sync_Strobe.rst b/docs/IPCores/misc/sync/sync_Strobe.rst index 63751033..bf8600c6 100644 --- a/docs/IPCores/misc/sync/sync_Strobe.rst +++ b/docs/IPCores/misc/sync/sync_Strobe.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:sync_Strobe: PoC.misc.sync.Strobe diff --git a/docs/IPCores/misc/sync/sync_Vector.rst b/docs/IPCores/misc/sync/sync_Vector.rst index b963c1df..4516bd13 100644 --- a/docs/IPCores/misc/sync/sync_Vector.rst +++ b/docs/IPCores/misc/sync/sync_Vector.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:sync_Vector: PoC.misc.sync.Vector diff --git a/docs/IPCores/net/arp/arp_BroadCast_Receiver.rst b/docs/IPCores/net/arp/arp_BroadCast_Receiver.rst index f59c31fd..d5a641a6 100644 --- a/docs/IPCores/net/arp/arp_BroadCast_Receiver.rst +++ b/docs/IPCores/net/arp/arp_BroadCast_Receiver.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arp_BroadCast_Receiver: PoC.net.arp.BroadCast_Receiver diff --git a/docs/IPCores/net/arp/arp_BroadCast_Requester.rst b/docs/IPCores/net/arp/arp_BroadCast_Requester.rst index 99d68b0d..9087b91f 100644 --- a/docs/IPCores/net/arp/arp_BroadCast_Requester.rst +++ b/docs/IPCores/net/arp/arp_BroadCast_Requester.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arp_BroadCast_Requester: PoC.net.arp.BroadCast_Requester diff --git a/docs/IPCores/net/arp/arp_Cache.rst b/docs/IPCores/net/arp/arp_Cache.rst index 27dccbf0..a80b6829 100644 --- a/docs/IPCores/net/arp/arp_Cache.rst +++ b/docs/IPCores/net/arp/arp_Cache.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arp_Cache: PoC.net.arp.Cache diff --git a/docs/IPCores/net/arp/arp_IPPool.rst b/docs/IPCores/net/arp/arp_IPPool.rst index ad696224..a4d2db02 100644 --- a/docs/IPCores/net/arp/arp_IPPool.rst +++ b/docs/IPCores/net/arp/arp_IPPool.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arp_IPPool: PoC.net.arp.IPPool diff --git a/docs/IPCores/net/arp/arp_Tester.rst b/docs/IPCores/net/arp/arp_Tester.rst index c179f606..d7dd8f23 100644 --- a/docs/IPCores/net/arp/arp_Tester.rst +++ b/docs/IPCores/net/arp/arp_Tester.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arp_Tester: PoC.net.arp.Tester diff --git a/docs/IPCores/net/arp/arp_UniCast_Receiver.rst b/docs/IPCores/net/arp/arp_UniCast_Receiver.rst index 98180b97..defafdd9 100644 --- a/docs/IPCores/net/arp/arp_UniCast_Receiver.rst +++ b/docs/IPCores/net/arp/arp_UniCast_Receiver.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arp_UniCast_Receiver: PoC.net.arp.UniCast_Receiver diff --git a/docs/IPCores/net/arp/arp_UniCast_Responder.rst b/docs/IPCores/net/arp/arp_UniCast_Responder.rst index ec4da49f..28561bc3 100644 --- a/docs/IPCores/net/arp/arp_UniCast_Responder.rst +++ b/docs/IPCores/net/arp/arp_UniCast_Responder.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arp_UniCast_Responder: PoC.net.arp.UniCast_Responder diff --git a/docs/IPCores/net/arp/arp_Wrapper.rst b/docs/IPCores/net/arp/arp_Wrapper.rst index 58750f5a..505fbeff 100644 --- a/docs/IPCores/net/arp/arp_Wrapper.rst +++ b/docs/IPCores/net/arp/arp_Wrapper.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:arp_Wrapper: PoC.net.arp.Wrapper diff --git a/docs/IPCores/net/eth/eth_GEMAC_GMII.rst b/docs/IPCores/net/eth/eth_GEMAC_GMII.rst index 59edd608..d91d05a3 100644 --- a/docs/IPCores/net/eth/eth_GEMAC_GMII.rst +++ b/docs/IPCores/net/eth/eth_GEMAC_GMII.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:eth_GEMAC_GMII: PoC.net.eth.GEMAC_GMII diff --git a/docs/IPCores/net/eth/eth_GEMAC_RX.rst b/docs/IPCores/net/eth/eth_GEMAC_RX.rst index a3a48f69..16f20131 100644 --- a/docs/IPCores/net/eth/eth_GEMAC_RX.rst +++ b/docs/IPCores/net/eth/eth_GEMAC_RX.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:Eth_GEMAC_RX: PoC.net.eth.GEMAC_RX diff --git a/docs/IPCores/net/eth/eth_GEMAC_TX.rst b/docs/IPCores/net/eth/eth_GEMAC_TX.rst index 5a8e6e45..9f0096e6 100644 --- a/docs/IPCores/net/eth/eth_GEMAC_TX.rst +++ b/docs/IPCores/net/eth/eth_GEMAC_TX.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:Eth_GEMAC_TX: PoC.net.eth.GEMAC_TX diff --git a/docs/IPCores/net/eth/eth_PHYController.rst b/docs/IPCores/net/eth/eth_PHYController.rst index 45b6f121..f2bdddeb 100644 --- a/docs/IPCores/net/eth/eth_PHYController.rst +++ b/docs/IPCores/net/eth/eth_PHYController.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:Eth_PHYController: PoC.net.eth.PHYController diff --git a/docs/IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst b/docs/IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst index 9912b632..7d367011 100644 --- a/docs/IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst +++ b/docs/IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:Eth_PHYController_Marvell_88E1111: PoC.net.eth.PHYController_Marvell_88E1111 diff --git a/docs/IPCores/net/eth/eth_Wrapper.rst b/docs/IPCores/net/eth/eth_Wrapper.rst index aebdc49d..13295c4c 100644 --- a/docs/IPCores/net/eth/eth_Wrapper.rst +++ b/docs/IPCores/net/eth/eth_Wrapper.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:Eth_Wrapper: PoC.net.eth.Wrapper diff --git a/docs/IPCores/net/icmpv4/icmpv4_RX.rst b/docs/IPCores/net/icmpv4/icmpv4_RX.rst index 74acdffa..84c762ec 100644 --- a/docs/IPCores/net/icmpv4/icmpv4_RX.rst +++ b/docs/IPCores/net/icmpv4/icmpv4_RX.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:icmpv4_RX: PoC.net.icmpv4.RX diff --git a/docs/IPCores/net/icmpv4/icmpv4_TX.rst b/docs/IPCores/net/icmpv4/icmpv4_TX.rst index 8ff373e7..57b45871 100644 --- a/docs/IPCores/net/icmpv4/icmpv4_TX.rst +++ b/docs/IPCores/net/icmpv4/icmpv4_TX.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:icmpv4_TX: PoC.net.icmpv4.TX diff --git a/docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst b/docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst index 268f394a..229c9902 100644 --- a/docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst +++ b/docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:icmpv4_Wrapper: PoC.net.icmpv4.Wrapper diff --git a/docs/IPCores/net/icmpv6/icmpv6_RX.rst b/docs/IPCores/net/icmpv6/icmpv6_RX.rst index e08c5751..7d28138a 100644 --- a/docs/IPCores/net/icmpv6/icmpv6_RX.rst +++ b/docs/IPCores/net/icmpv6/icmpv6_RX.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:icmpv6_RX: PoC.net.icmpv6.RX diff --git a/docs/IPCores/net/icmpv6/icmpv6_TX.rst b/docs/IPCores/net/icmpv6/icmpv6_TX.rst index cf1b6bc6..8aab7d21 100644 --- a/docs/IPCores/net/icmpv6/icmpv6_TX.rst +++ b/docs/IPCores/net/icmpv6/icmpv6_TX.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:icmpv6_TX: PoC.net.icmpv6.TX diff --git a/docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst b/docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst index 0c424ce0..cf24a66e 100644 --- a/docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst +++ b/docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:icmpv6_Wrapper: PoC.net.icmpv6.Wrapper diff --git a/docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst b/docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst index 13779ba2..4fc10a52 100644 --- a/docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst +++ b/docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ipv4_FrameLoopback: PoC.net.ipv4.FrameLoopback diff --git a/docs/IPCores/net/ipv4/ipv4_RX.rst b/docs/IPCores/net/ipv4/ipv4_RX.rst index f665cd30..d1936146 100644 --- a/docs/IPCores/net/ipv4/ipv4_RX.rst +++ b/docs/IPCores/net/ipv4/ipv4_RX.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ipv4_RX: PoC.net.ipv4.RX diff --git a/docs/IPCores/net/ipv4/ipv4_TX.rst b/docs/IPCores/net/ipv4/ipv4_TX.rst index f0e4e333..c4ea3487 100644 --- a/docs/IPCores/net/ipv4/ipv4_TX.rst +++ b/docs/IPCores/net/ipv4/ipv4_TX.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ipv4_TX: PoC.net.ipv4.TX diff --git a/docs/IPCores/net/ipv4/ipv4_Wrapper.rst b/docs/IPCores/net/ipv4/ipv4_Wrapper.rst index 6f9cf25d..2be0304c 100644 --- a/docs/IPCores/net/ipv4/ipv4_Wrapper.rst +++ b/docs/IPCores/net/ipv4/ipv4_Wrapper.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ipv4_Wrapper: PoC.net.ipv4.Wrapper diff --git a/docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst b/docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst index 0f2e6a9a..a499f902 100644 --- a/docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst +++ b/docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ipv6_FrameLoopback: PoC.net.ipv6.FrameLoopback diff --git a/docs/IPCores/net/ipv6/ipv6_RX.rst b/docs/IPCores/net/ipv6/ipv6_RX.rst index 6a8a7bea..896a0dbd 100644 --- a/docs/IPCores/net/ipv6/ipv6_RX.rst +++ b/docs/IPCores/net/ipv6/ipv6_RX.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ipv6_RX: PoC.net.ipv6.RX diff --git a/docs/IPCores/net/ipv6/ipv6_TX.rst b/docs/IPCores/net/ipv6/ipv6_TX.rst index 39ab179b..85136704 100644 --- a/docs/IPCores/net/ipv6/ipv6_TX.rst +++ b/docs/IPCores/net/ipv6/ipv6_TX.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ipv6_TX: PoC.net.ipv6.TX diff --git a/docs/IPCores/net/ipv6/ipv6_Wrapper.rst b/docs/IPCores/net/ipv6/ipv6_Wrapper.rst index 7bce03cc..40f1823c 100644 --- a/docs/IPCores/net/ipv6/ipv6_Wrapper.rst +++ b/docs/IPCores/net/ipv6/ipv6_Wrapper.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ipv6_Wrapper: PoC.net.ipv6.Wrapper diff --git a/docs/IPCores/net/mac/mac_FrameLoopback.rst b/docs/IPCores/net/mac/mac_FrameLoopback.rst index 13950b61..fdcf100e 100644 --- a/docs/IPCores/net/mac/mac_FrameLoopback.rst +++ b/docs/IPCores/net/mac/mac_FrameLoopback.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:mac_FrameLoopback: PoC.net.mac.FrameLoopback diff --git a/docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst b/docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst index a9d4decf..49045289 100644 --- a/docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst +++ b/docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:mac_RX_DestMAC_Switch: PoC.net.mac.RX_DestMAC_Switch diff --git a/docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst b/docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst index 798b3c62..049e1496 100644 --- a/docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst +++ b/docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:mac_RX_SrcMAC_Filter: PoC.net.mac.RX_SrcMAC_Filter diff --git a/docs/IPCores/net/mac/mac_RX_Type_Switch.rst b/docs/IPCores/net/mac/mac_RX_Type_Switch.rst index 405916ff..2ce1c3d6 100644 --- a/docs/IPCores/net/mac/mac_RX_Type_Switch.rst +++ b/docs/IPCores/net/mac/mac_RX_Type_Switch.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:mac_RX_Type_Switch: PoC.net.mac.RX_Type_Switch diff --git a/docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst b/docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst index e1c35e1c..d2a4cdaf 100644 --- a/docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst +++ b/docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:mac_TX_DestMAC_Prepender: PoC.net.mac.TX_DestMAC_Prepender diff --git a/docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst b/docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst index 3d2bf089..c71d2f5d 100644 --- a/docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst +++ b/docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:mac_TX_SrcMAC_Prepender: PoC.net.mac.TX_SrcMAC_Prepender diff --git a/docs/IPCores/net/mac/mac_TX_Type_Prepender.rst b/docs/IPCores/net/mac/mac_TX_Type_Prepender.rst index cba4445c..8a71ace0 100644 --- a/docs/IPCores/net/mac/mac_TX_Type_Prepender.rst +++ b/docs/IPCores/net/mac/mac_TX_Type_Prepender.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:mac_TX_Type_Prepender: PoC.net.mac.TX_Type_Prepender diff --git a/docs/IPCores/net/mac/mac_Wrapper.rst b/docs/IPCores/net/mac/mac_Wrapper.rst index b930cff8..778354a2 100644 --- a/docs/IPCores/net/mac/mac_Wrapper.rst +++ b/docs/IPCores/net/mac/mac_Wrapper.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:mac_Wrapper: PoC.net.mac.Wrapper diff --git a/docs/IPCores/net/ndp/ndp_DestinationCache.rst b/docs/IPCores/net/ndp/ndp_DestinationCache.rst index ea92da57..c9235632 100644 --- a/docs/IPCores/net/ndp/ndp_DestinationCache.rst +++ b/docs/IPCores/net/ndp/ndp_DestinationCache.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ndp_DestinationCache: PoC.net.ndp.DestinationCache diff --git a/docs/IPCores/net/ndp/ndp_FSMQuery.rst b/docs/IPCores/net/ndp/ndp_FSMQuery.rst index 22220f80..e48e606b 100644 --- a/docs/IPCores/net/ndp/ndp_FSMQuery.rst +++ b/docs/IPCores/net/ndp/ndp_FSMQuery.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ndp_FSMQuery: PoC.net.ndp.FSMQuery diff --git a/docs/IPCores/net/ndp/ndp_NeighborCache.rst b/docs/IPCores/net/ndp/ndp_NeighborCache.rst index b1dd16ee..d813debe 100644 --- a/docs/IPCores/net/ndp/ndp_NeighborCache.rst +++ b/docs/IPCores/net/ndp/ndp_NeighborCache.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:ndp_NeighborCache: PoC.net.ndp.NeighborCache diff --git a/docs/IPCores/net/ndp/ndp_Wrapper.rst b/docs/IPCores/net/ndp/ndp_Wrapper.rst index 643a32c4..95102466 100644 --- a/docs/IPCores/net/ndp/ndp_Wrapper.rst +++ b/docs/IPCores/net/ndp/ndp_Wrapper.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:NDP_Wrapper: PoC.net.ndp.Wrapper diff --git a/docs/IPCores/net/net_FrameChecksum.rst b/docs/IPCores/net/net_FrameChecksum.rst index 9bd64e5b..0ca47cbe 100644 --- a/docs/IPCores/net/net_FrameChecksum.rst +++ b/docs/IPCores/net/net_FrameChecksum.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:net_FrameChecksum: PoC.net.FrameChecksum diff --git a/docs/IPCores/net/net_FrameLoopback.rst b/docs/IPCores/net/net_FrameLoopback.rst index 9ea66a2a..dffbfcd0 100644 --- a/docs/IPCores/net/net_FrameLoopback.rst +++ b/docs/IPCores/net/net_FrameLoopback.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:FrameLoopback: PoC.net.FrameLoopback diff --git a/docs/IPCores/net/net_FramePerformanceCounter.rst b/docs/IPCores/net/net_FramePerformanceCounter.rst index 81fc24e1..b98041fd 100644 --- a/docs/IPCores/net/net_FramePerformanceCounter.rst +++ b/docs/IPCores/net/net_FramePerformanceCounter.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:LocalLink_PerformanceCounter: PoC.net.FramePerformanceCounter diff --git a/docs/IPCores/net/stack/stack_UDPv4.rst b/docs/IPCores/net/stack/stack_UDPv4.rst index a9caf2ab..03cf1e52 100644 --- a/docs/IPCores/net/stack/stack_UDPv4.rst +++ b/docs/IPCores/net/stack/stack_UDPv4.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:stack_UDPv4: PoC.net.stack.UDPv4 diff --git a/docs/IPCores/net/udp/udp_FrameLoopback.rst b/docs/IPCores/net/udp/udp_FrameLoopback.rst index a2138d1e..bcad8e4a 100644 --- a/docs/IPCores/net/udp/udp_FrameLoopback.rst +++ b/docs/IPCores/net/udp/udp_FrameLoopback.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:udp_FrameLoopback: PoC.net.udp.FrameLoopback diff --git a/docs/IPCores/net/udp/udp_RX.rst b/docs/IPCores/net/udp/udp_RX.rst index 35c2a6d5..8875d645 100644 --- a/docs/IPCores/net/udp/udp_RX.rst +++ b/docs/IPCores/net/udp/udp_RX.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:udp_RX: PoC.net.udp.RX diff --git a/docs/IPCores/net/udp/udp_TX.rst b/docs/IPCores/net/udp/udp_TX.rst index c8be4697..351da0e8 100644 --- a/docs/IPCores/net/udp/udp_TX.rst +++ b/docs/IPCores/net/udp/udp_TX.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:udp_TX: PoC.net.udp.TX diff --git a/docs/IPCores/net/udp/udp_Wrapper.rst b/docs/IPCores/net/udp/udp_Wrapper.rst index 97d4cdb5..3c286454 100644 --- a/docs/IPCores/net/udp/udp_Wrapper.rst +++ b/docs/IPCores/net/udp/udp_Wrapper.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:udp_Wrapper: PoC.net.udp.Wrapper diff --git a/docs/IPCores/sort/sort_ExpireList.rst b/docs/IPCores/sort/sort_ExpireList.rst index 4b46c28d..f2fd3446 100644 --- a/docs/IPCores/sort/sort_ExpireList.rst +++ b/docs/IPCores/sort/sort_ExpireList.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:list_expire: PoC.sort.ExpireList diff --git a/docs/IPCores/sort/sort_InsertSort.rst b/docs/IPCores/sort/sort_InsertSort.rst index 4616c485..cf48afe9 100644 --- a/docs/IPCores/sort/sort_InsertSort.rst +++ b/docs/IPCores/sort/sort_InsertSort.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:list_lru_systolic: PoC.sort.InsertSort diff --git a/docs/IPCores/sort/sort_LeastFrequentlyUsed.rst b/docs/IPCores/sort/sort_LeastFrequentlyUsed.rst index 14227dff..a3b9b40c 100644 --- a/docs/IPCores/sort/sort_LeastFrequentlyUsed.rst +++ b/docs/IPCores/sort/sort_LeastFrequentlyUsed.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:sort_LeastFrequentlyUsed: PoC.sort.LeastFrequentlyUsed diff --git a/docs/IPCores/sort/sort_lru_cache.rst b/docs/IPCores/sort/sort_lru_cache.rst index b97b72c2..f2e88ece 100644 --- a/docs/IPCores/sort/sort_lru_cache.rst +++ b/docs/IPCores/sort/sort_lru_cache.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:sort_lru_cache: PoC.sort.lru_cache diff --git a/docs/IPCores/sort/sort_lru_list.rst b/docs/IPCores/sort/sort_lru_list.rst index f61b148f..761b35e8 100644 --- a/docs/IPCores/sort/sort_lru_list.rst +++ b/docs/IPCores/sort/sort_lru_list.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:sort_lru_list: PoC.sort.lru_list diff --git a/docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst b/docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst index 58274b6d..a07323e5 100644 --- a/docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst +++ b/docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:sortnet_BitonicSort: PoC.sort.sortnet.BitonicSort diff --git a/docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst b/docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst index eaeb3c3f..fdd2fa72 100644 --- a/docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst +++ b/docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:sortnet_MergeSort_Streamed: PoC.sort.sortnet.MergeSort_Streamed diff --git a/docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst b/docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst index 53ff3811..2771a913 100644 --- a/docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst +++ b/docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:sortnet_OddEvenMergeSort: PoC.sort.sortnet.OddEvenMergeSort diff --git a/docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst b/docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst index 3b27af41..f87dad1e 100644 --- a/docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst +++ b/docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:sortnet_OddEvenSort: PoC.sort.sortnet.OddEvenSort diff --git a/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst index a9330679..b9e1d7e1 100644 --- a/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst +++ b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:sortnet_Stream_Adapter: PoC.sort.sortnet.Stream_Adapter diff --git a/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst index 3043097c..def9d412 100644 --- a/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst +++ b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:sortnet_Stream_Adapter2: PoC.sort.sortnet.Stream_Adapter2 diff --git a/docs/IPCores/sort/sortnet/sortnet_Transform.rst b/docs/IPCores/sort/sortnet/sortnet_Transform.rst index cbb43a5f..a001656d 100644 --- a/docs/IPCores/sort/sortnet/sortnet_Transform.rst +++ b/docs/IPCores/sort/sortnet/sortnet_Transform.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:sortnet_Transform: PoC.sort.sortnet.Transform diff --git a/docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst b/docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst index 5d9d2544..7d93b55c 100644 --- a/docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst +++ b/docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:reconfig_icap_fsm: PoC.xil.reconfig.icap_fsm diff --git a/docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst b/docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst index 3bbfba70..94d71bf4 100644 --- a/docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst +++ b/docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:reconfig_icap_wrapper: PoC.xil.reconfig.icap_wrapper diff --git a/docs/IPCores/xil/xil_BSCAN.rst b/docs/IPCores/xil/xil_BSCAN.rst index 77c31e1d..21eef34f 100644 --- a/docs/IPCores/xil/xil_BSCAN.rst +++ b/docs/IPCores/xil/xil_BSCAN.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:xil_BSCAN: PoC.xil.BSCAN diff --git a/docs/IPCores/xil/xil_ChipScopeICON.rst b/docs/IPCores/xil/xil_ChipScopeICON.rst index 924e0561..ae957c26 100644 --- a/docs/IPCores/xil/xil_ChipScopeICON.rst +++ b/docs/IPCores/xil/xil_ChipScopeICON.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:xil_ChipScopeICON: PoC.xil.ChipScopeICON diff --git a/docs/IPCores/xil/xil_DRP_BusMux.rst b/docs/IPCores/xil/xil_DRP_BusMux.rst index 5f2182e7..6d668125 100644 --- a/docs/IPCores/xil/xil_DRP_BusMux.rst +++ b/docs/IPCores/xil/xil_DRP_BusMux.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:xil_DRP_BusMux: PoC.xil.DRP_BusMux diff --git a/docs/IPCores/xil/xil_DRP_BusSync.rst b/docs/IPCores/xil/xil_DRP_BusSync.rst index 431dfbe1..6d51d68b 100644 --- a/docs/IPCores/xil/xil_DRP_BusSync.rst +++ b/docs/IPCores/xil/xil_DRP_BusSync.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:xil_DRP_BusSync: PoC.xil.DRP_BusSync diff --git a/docs/IPCores/xil/xil_ICAP.rst b/docs/IPCores/xil/xil_ICAP.rst index 4a7bcc27..8d22cbc3 100644 --- a/docs/IPCores/xil/xil_ICAP.rst +++ b/docs/IPCores/xil/xil_ICAP.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:xil_ICAP: PoC.xil.ICAP diff --git a/docs/IPCores/xil/xil_Reconfigurator.rst b/docs/IPCores/xil/xil_Reconfigurator.rst index f1256b3f..2e041977 100644 --- a/docs/IPCores/xil/xil_Reconfigurator.rst +++ b/docs/IPCores/xil/xil_Reconfigurator.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:xil_Reconfigurator: PoC.xil.Reconfigurator diff --git a/docs/IPCores/xil/xil_SystemMonitor.rst b/docs/IPCores/xil/xil_SystemMonitor.rst index 232e2a8c..50f16b89 100644 --- a/docs/IPCores/xil/xil_SystemMonitor.rst +++ b/docs/IPCores/xil/xil_SystemMonitor.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:xil_SystemMonitor: PoC.xil.SystemMonitor diff --git a/docs/IPCores/xil/xil_SystemMonitor_Series7.rst b/docs/IPCores/xil/xil_SystemMonitor_Series7.rst index f67f6813..4ab4a031 100644 --- a/docs/IPCores/xil/xil_SystemMonitor_Series7.rst +++ b/docs/IPCores/xil/xil_SystemMonitor_Series7.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:xil_SystemMonitor_Series7: PoC.xil.SystemMonitor_Series7 diff --git a/docs/IPCores/xil/xil_SystemMonitor_Virtex6.rst b/docs/IPCores/xil/xil_SystemMonitor_Virtex6.rst index 41363b27..b1c47af1 100644 --- a/docs/IPCores/xil/xil_SystemMonitor_Virtex6.rst +++ b/docs/IPCores/xil/xil_SystemMonitor_Virtex6.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + .. _IP:xil_SystemMonitor_Virtex6: PoC.xil.SystemMonitor_Virtex6 diff --git a/docs/PyInfrastructure/index.rst b/docs/PyInfrastructure/index.rst index 3d4735ab..50700416 100644 --- a/docs/PyInfrastructure/index.rst +++ b/docs/PyInfrastructure/index.rst @@ -2,17 +2,11 @@ Python Infrastructure ##################### -Frontend Scripts -**************** - .. toctree:: PoC -Packages and Modules -******************** - .. toctree:: Base @@ -23,7 +17,7 @@ Packages and Modules ToolChains lib -.. foobar +.. # automodule:: PoC :members: :undoc-members: diff --git a/docs/UsingPoC/Requirements.rst b/docs/UsingPoC/Requirements.rst index ddfc41ec..e34021c4 100644 --- a/docs/UsingPoC/Requirements.rst +++ b/docs/UsingPoC/Requirements.rst @@ -1,5 +1,6 @@ .. # Load pre-defined aliases from docutils # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include .. include:: diff --git a/docs/_templates/autoapi/module.rst b/docs/_templates/autoapi/module.rst index b54b2cbc..c6d4a0f9 100644 --- a/docs/_templates/autoapi/module.rst +++ b/docs/_templates/autoapi/module.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + {{ node.name }} =={{ '=' * node.name|length }}== diff --git a/docs/_templates/autoapi/script.rst b/docs/_templates/autoapi/script.rst index 57c41c20..414161e5 100644 --- a/docs/_templates/autoapi/script.rst +++ b/docs/_templates/autoapi/script.rst @@ -1,3 +1,10 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + {{ node.name }}.py =={{ '=' * node.name|length }}== From 4f8ef06a452fbd35265804e2c33226aa782d2af0 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 5 Dec 2016 11:01:06 +0100 Subject: [PATCH 87/97] Reworked configuration mechanism. Added reworked VCD parser. Added more documentation in Python. Refactored Python code. --- docs/UsingPoC/VHDLConfiguration.rst | 8 +- py/Base/Compiler.py | 595 ----------- py/Base/Configuration.py | 257 ----- py/Base/Exceptions.py | 10 +- py/Base/Executable.py | 12 +- py/Base/Logging.py | 139 +-- py/Base/Project.py | 6 +- py/Base/Shared.py | 14 +- py/Base/Simulator.py | 394 ------- py/Base/ToolChain.py | 46 - py/Base/__init__.py | 38 +- py/Compiler/ISECompiler.py | 12 +- py/Compiler/LSECompiler.py | 14 +- py/Compiler/QuartusCompiler.py | 22 +- py/Compiler/VivadoCompiler.py | 12 +- py/Compiler/XCICompiler.py | 12 +- py/Compiler/XCOCompiler.py | 12 +- py/Compiler/XSTCompiler.py | 14 +- py/Compiler/__init__.py | 570 ++++++++++- py/DataBase/Config.py | 184 ++-- py/DataBase/Entity.py | 10 +- py/DataBase/Query.py | 119 --- py/DataBase/Solution.py | 8 +- py/DataBase/TestCase.py | 4 - py/DataBase/__init__.py | 103 +- py/Parser/FilesCodeDOM.py | 8 +- py/Parser/FilesParser.py | 6 +- py/Parser/RulesCodeDOM.py | 4 - py/Parser/RulesParser.py | 4 - py/Parser/__init__.py | 13 - py/PoC.py | 221 ++-- py/Processor/__init__.py | 13 - py/README.md | 49 +- py/Simulator/ActiveHDLSimulator.py | 34 +- py/Simulator/CocotbSimulator.py | 14 +- py/Simulator/GHDLSimulator.py | 11 +- py/Simulator/ISESimulator.py | 12 +- py/Simulator/QuestaSimulator.py | 34 +- py/Simulator/VivadoSimulator.py | 14 +- py/Simulator/__init__.py | 371 ++++++- py/ToolChains/Aldec/ActiveHDL.py | 161 ++- py/ToolChains/Aldec/__init__.py | 72 +- py/ToolChains/Altera/Altera.py | 75 -- py/ToolChains/Altera/ModelSim.py | 74 +- py/ToolChains/Altera/Quartus.py | 94 +- py/ToolChains/Altera/__init__.py | 72 +- py/ToolChains/GHDL.py | 86 +- py/ToolChains/GNU.py | 14 +- py/ToolChains/GTKWave.py | 66 +- py/ToolChains/Git.py | 78 +- py/ToolChains/Intel/ModelSim.py | 147 +++ py/ToolChains/Intel/Quartus.py | 126 +++ .../{Aldec/Aldec.py => Intel/__init__.py} | 40 +- py/ToolChains/Lattice/ActiveHDL.py | 43 +- py/ToolChains/Lattice/Diamond.py | 70 +- py/ToolChains/Lattice/Lattice.py | 82 -- py/ToolChains/Lattice/Synplify.py | 13 +- py/ToolChains/Lattice/__init__.py | 65 +- py/ToolChains/Mentor/Mentor.py | 71 -- py/ToolChains/Mentor/ModelSim.py | 240 +++++ py/ToolChains/Mentor/ModelSimPE.py | 121 --- py/ToolChains/Mentor/QuestaSim.py | 49 +- py/ToolChains/Mentor/__init__.py | 65 +- py/ToolChains/PoC.py | 59 +- py/ToolChains/Synopsys/Synopsys.py | 82 -- py/ToolChains/Synopsys/__init__.py | 68 +- py/ToolChains/Xilinx/HardwareServer.py | 68 -- py/ToolChains/Xilinx/ISE.py | 61 +- py/ToolChains/Xilinx/LabTools.py | 68 -- py/ToolChains/Xilinx/Vivado.py | 57 +- py/ToolChains/Xilinx/Xilinx.py | 108 -- py/ToolChains/Xilinx/__init__.py | 97 +- py/ToolChains/__init__.py | 969 ++++++++++++++++-- py/Wrapper/Lattice.Diamond.sh | 11 +- py/Wrapper/PoC.psm1 | 8 +- py/Wrapper/wrapper.sh | 58 +- py/__init__.py | 14 - py/config.boards.ini | 21 +- py/config.entity.ini | 7 + py/config.structure.ini | 3 + py/lib/CodeDOM.py | 6 +- py/lib/Decorators.py | 4 - py/lib/ExtendedConfigParser/__init__.py | 8 + py/lib/Functions.py | 104 +- py/lib/Parser.py | 4 - py/lib/SphinxExtensions/__init__.py | 4 - py/lib/__init__.py | 13 - py/lib/pyAttribute/ArgParseAttributes.py | 4 - py/lib/pyAttribute/__init__.py | 4 - src/common/config.vhdl | 12 +- src/mem/sdram/sdram_ctrl_s3esk.files | 6 +- src/sim/sim_VCDParser.vhdl | 115 +++ tb/common/my_config.files | 4 + tb/common/my_config_S3ESK500.vhdl | 51 + tb/sim/sim_VCDParser_tb.files | 12 + tb/sim/sim_VCDParser_tb.vcd | 57 ++ tb/sim/sim_VCDParser_tb.vhdl | 140 +++ 97 files changed, 4310 insertions(+), 3344 deletions(-) delete mode 100644 py/Base/Compiler.py delete mode 100644 py/Base/Configuration.py delete mode 100644 py/Base/Simulator.py delete mode 100644 py/Base/ToolChain.py delete mode 100644 py/DataBase/Query.py delete mode 100644 py/ToolChains/Altera/Altera.py create mode 100644 py/ToolChains/Intel/ModelSim.py create mode 100644 py/ToolChains/Intel/Quartus.py rename py/ToolChains/{Aldec/Aldec.py => Intel/__init__.py} (58%) delete mode 100644 py/ToolChains/Lattice/Lattice.py delete mode 100644 py/ToolChains/Mentor/Mentor.py create mode 100644 py/ToolChains/Mentor/ModelSim.py delete mode 100644 py/ToolChains/Mentor/ModelSimPE.py delete mode 100644 py/ToolChains/Synopsys/Synopsys.py delete mode 100644 py/ToolChains/Xilinx/HardwareServer.py delete mode 100644 py/ToolChains/Xilinx/LabTools.py delete mode 100644 py/ToolChains/Xilinx/Xilinx.py create mode 100644 src/sim/sim_VCDParser.vhdl create mode 100644 tb/common/my_config_S3ESK500.vhdl create mode 100644 tb/sim/sim_VCDParser_tb.files create mode 100644 tb/sim/sim_VCDParser_tb.vcd create mode 100644 tb/sim/sim_VCDParser_tb.vhdl diff --git a/docs/UsingPoC/VHDLConfiguration.rst b/docs/UsingPoC/VHDLConfiguration.rst index 5c133c4e..f4bc7270 100644 --- a/docs/UsingPoC/VHDLConfiguration.rst +++ b/docs/UsingPoC/VHDLConfiguration.rst @@ -3,7 +3,7 @@ Creating my_config/my_project.vhdl ################################## -The PoC-Library needs two VHDL files for it's configuration. These files are +The PoC-Library needs two VHDL files for its configuration. These files are used to determine the most suitable implementation depending on the provided platform information. These files are also used to select appropiate work arounds. @@ -17,10 +17,10 @@ Create my_config.vhdl The **my_config.vhdl** file can easily be created from the template file ``my_config.vhdl.template`` provided by PoC in ``PoCRoot\src\common``. (View source on `GitHub `_.) -Copy this file into the projects source directory and renamed into +Copy this file into the project's source directory and rename it to ``my_config.vhdl``. -This file should be included into version control systems and shared with other +This file should be included in version control systems and shared with other systems. ``my_config.vhdl`` defines three global constants, which need to be adjusted: @@ -31,7 +31,7 @@ adjusted: constant MY_VERBOSE : boolean := FALSE; -- activate report statements in VHDL subprograms The easiest way is to define a board name and set ``MY_DEVICE`` to ``None``. -So the device name is infered from the board information stored in ``PoCRoot\src\common\board.vhdl``. +So the device name is infered from the board information stored in ``PoCRoot\src\common\config.vhdl``. If the requested board is not known to PoC or it's custom made, then set ``MY_BOARD`` to ``Custom`` and ``MY_DEVICE`` to the full FPGA device string. diff --git a/py/Base/Compiler.py b/py/Base/Compiler.py deleted file mode 100644 index 347170b0..00000000 --- a/py/Base/Compiler.py +++ /dev/null @@ -1,595 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# -# ============================================================================== -# Authors: Patrick Lehmann -# Martin Zabel -# -# Python Class: Base class for all PoC***Compilers -# -# Description: -# ------------------------------------ -# TODO: -# - -# - -# -# License: -# ============================================================================== -# Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair of VLSI-Design, Diagnostics and Architecture -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# ============================================================================== -# -# load dependencies -from enum import Enum, unique -from pathlib import Path -from re import compile as re_compile, subn as re_subn, DOTALL as RE_DOTALL, MULTILINE as RE_MULTILINE, IGNORECASE as RE_IGNORECASE -from shutil import copy as shutil_copy - -from flags import Flags - -from lib.Functions import Init -from lib.Parser import ParserException -from Base.Exceptions import ExceptionBase, SkipableException -from Base.Project import VHDLVersion, Environment, FileTypes -from Base.Shared import Shared, to_time -from Parser.RulesParser import CopyRuleMixIn, ReplaceRuleMixIn, DeleteRuleMixIn, AppendLineRuleMixIn -from DataBase.Solution import RulesFile -from DataBase.TestCase import SynthesisSuite, Synthesis, CompileStatus - - -# required for autoapi.sphinx -from lib.SphinxExtensions import DocumentMemberAttribute - - -__api__ = [ - 'CompilerException', - 'SkipableCompilerException', - 'CopyTask', - 'DeleteTask', - 'ReplaceTask', - 'AppendLineTask', - 'CompileState', - 'CompileResult', - 'Compiler' -] -__all__ = __api__ - - -class CompilerException(ExceptionBase): - """Base class for all CompilerException classes. It is raised while running - compiler (synthesis) tasks in PoC. - """ - -class SkipableCompilerException(CompilerException, SkipableException): - """``SkipableCompilerException`` is a :py:exc:`CompilerException`, which - can be skipped. - """ - -class CopyTask(CopyRuleMixIn): - """This class represents a 'copy task' and inherits the partial class - :class:`CopyRuleMixIn `. - """ - -class DeleteTask(DeleteRuleMixIn): - """This class represents a 'delete task' and inherits the partial class - :class:`DeleteRuleMixIn `. - """ - -class ReplaceTask(ReplaceRuleMixIn): - """This class represents a 'replace task' and inherits the partial class - :class:`ReplaceRuleMixIn `. - """ - -class AppendLineTask(AppendLineRuleMixIn): - """This class represents a 'append line task' and inherits the partial class - :class:`AppendLineRuleMixIn `. - """ - - -@unique -class CompilerSteps(Flags): - """Compiler step enumeration.""" - Prepare = 1 << 0 - CleanUpBefore = 1 << 1 - CleanUpAfter = 1 << 2 - Synthesize = 1 << 5 - Merge = 1 << 6 - AnalyzeTiming = 1 << 7 - Place = 1 << 8 - Route = 1 << 9 - WriteBitfile = 1 << 10 - ShowReport = 1 << 15 - # Recompile = 1 << 25 - # Resimulate = 1 << 26 - # Review = 1 << 27 - -@unique -class CompileState(Enum): - """Compile state enumeration.""" - Prepare = 0 - PreCopy = 10 - PrePatch = 11 - - Compile = 50 - # Analyze = 61 - # Elaborate = 62 - # Optimize = 63 - # Translate = 64 - # Map = 65 - # Place = 66 - # Route = 67 - - PostCopy = 90 - PostPatch = 91 - PostDelete = 92 - CleanUp = 99 - -@unique -class CompileResult(Enum): - """Compilation result enumeration.""" - NotRun = 0 - Error = 1 - Failed = 2 - Success = 3 - - -class Compiler(Shared): - """Base class for all Compiler classes.""" - - ENVIRONMENT = Environment.Synthesis - VHDL_VERSION = VHDLVersion.VHDL93 - - class __Directories__(Shared.__Directories__): - Netlist = None - Source = None - Destination = None - - @DocumentMemberAttribute() - def __init__(self, host, dryRun, noCleanUp): - """Class initializer - - :type host: object - :param host: The hosting instance for this instance. - :type dryRun: bool - :param dryRun: Enable dry-run mode - :type noCleanUp: bool - :param noCleanUp: Don't clean up after a run. - """ - super().__init__(host, dryRun) - - self._noCleanUp = noCleanUp - - self._testSuite = SynthesisSuite() # TODO: This includes not the read ini files phases ... - self._state = CompileState.Prepare - self._preTasksTime = None - self._compileTime = None - self._postTasksTime = None - - @property - def NoCleanUp(self): return self._noCleanUp - - def _PrepareCompiler(self): - """Prepare for compilation. This method forwards to :py:meth:`Base.Compiler.Compiler._Prepare`, - which is inherited from :py:class:`Base.Shared.Shared`. - """ - - def TryRun(self, netlist, *args, **kwargs): - """Try to run a testbench. Skip skipable exceptions by printing the error and its cause.""" - - __COMPILE_STATE_TO_SYNTHESIS_STATUS__ = { - CompileState.Prepare: CompileStatus.InternalError, - CompileState.PreCopy: CompileStatus.SystemError, - CompileState.PrePatch: CompileStatus.SystemError, - CompileState.Compile: CompileStatus.CompileError, - CompileState.PostCopy: CompileStatus.SystemError, - CompileState.PostPatch: CompileStatus.SystemError, - CompileState.PostDelete: CompileStatus.SystemError - } - - synthesis = Synthesis(netlist) - self._testSuite.AddSynthesis(synthesis) - synthesis.StartTimer() - try: - self.Run(netlist, *args, **kwargs) - # synthesis.UpdateStatus(netlist.Result) - synthesis.Status = CompileStatus.CompileSuccess - except SkipableCompilerException as ex: - synthesis.Status = __COMPILE_STATE_TO_SYNTHESIS_STATUS__[self._state] - - self.LogQuiet(" {RED}ERROR:{NOCOLOR} {0}".format(ex.message, **Init.Foreground)) - cause = ex.__cause__ - if (cause is not None): - self.LogQuiet(" {YELLOW}{ExType}:{NOCOLOR} {ExMsg!s}".format(ExType=cause.__class__.__name__, ExMsg=cause, **Init.Foreground)) - cause = cause.__cause__ - if (cause is not None): - self.LogQuiet(" {YELLOW}{ExType}:{NOCOLOR} {ExMsg!s}".format(ExType=cause.__class__.__name__, ExMsg=cause, **Init.Foreground)) - self.LogQuiet(" {RED}[SKIPPED DUE TO ERRORS]{NOCOLOR}".format(**Init.Foreground)) - except CompilerException: - synthesis.Status = __COMPILE_STATE_TO_SYNTHESIS_STATUS__[self._state] - raise - except ExceptionBase: - synthesis.Status = CompileStatus.SystemError - raise - finally: - synthesis.StopTimer() - - def Run(self, netlist, board): - """Run a testbench.""" - - self.LogQuiet("{CYAN}IP core: {0!s}{NOCOLOR}".format(netlist.Parent, **Init.Foreground)) - # # TODO: refactor - # self.LogNormal("Checking for dependencies:") - # for dependency in netlist.Dependencies: - # print(" " + str(dependency)) - - # setup all needed paths to execute fuse - self._PrepareCompilerEnvironment(board.Device) - self._WriteSpecialSectionIntoConfig(board.Device) - - self._CreatePoCProject(netlist.ModuleName, board) - if netlist.FilesFile is not None: self._AddFileListFile(netlist.FilesFile) - if (netlist.RulesFile is not None): self._AddRulesFiles(netlist.RulesFile) - - def _PrepareCompilerEnvironment(self, device): - self.LogNormal("Preparing synthesis environment...") - self.Directories.Destination = self.Directories.Netlist / str(device) - - self._PrepareEnvironment() - - # create output directory for CoreGen if not existent - if (not self.Directories.Destination.exists()) : - self.LogVerbose("Creating output directory for generated files.") - self.LogDebug("Output directory: {0!s}.".format(self.Directories.Destination)) - try: - self.Directories.Destination.mkdir(parents=True) - except OSError as ex: - raise CompilerException("Error while creating '{0!s}'.".format(self.Directories.Destination)) from ex - - def _WriteSpecialSectionIntoConfig(self, device): - # add the key Device to section SPECIAL at runtime to change interpolation results - self.Host.PoCConfig['SPECIAL'] = {} - self.Host.PoCConfig['SPECIAL']['Device'] = device.ShortName - self.Host.PoCConfig['SPECIAL']['DeviceSeries'] = device.Series - self.Host.PoCConfig['SPECIAL']['OutputDir'] = self.Directories.Working.as_posix() - - def _AddRulesFiles(self, rulesFilePath): - self.LogVerbose("Reading rules from '{0!s}'".format(rulesFilePath)) - # add the *.rules file, parse and evaluate it - try: - rulesFile = self._pocProject.AddFile(RulesFile(rulesFilePath)) - rulesFile.Parse() - except ParserException as ex: - raise SkipableCompilerException("Error while parsing '{0!s}'.".format(rulesFilePath)) from ex - - self.LogDebug("Pre-process rules:") - for rule in rulesFile.PreProcessRules: - self.LogDebug(" {0!s}".format(rule)) - self.LogDebug("Post-process rules:") - for rule in rulesFile.PostProcessRules: - self.LogDebug(" {0!s}".format(rule)) - - def _RunPreCopy(self, netlist): - self.LogVerbose("Copy further input files into temporary directory...") - rulesFiles = [file for file in self.PoCProject.Files(fileType=FileTypes.RulesFile)] # FIXME: get rulefile from netlist object as a rulefile object instead of a path - preCopyTasks = [] - if (rulesFiles): - for rule in rulesFiles[0].PreProcessRules: - if isinstance(rule, CopyRuleMixIn): - sourcePath = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.SourcePath, {}) - destinationPath = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.DestinationPath, {}) - task = CopyTask(Path(sourcePath), Path(destinationPath)) - preCopyTasks.append(task) - else: - preCopyRules = self.Host.PoCConfig[netlist.ConfigSectionName]['PreCopyRules'] - self._ParseCopyRules(preCopyRules, preCopyTasks, "pre") - - if (len(preCopyTasks) != 0): - self._ExecuteCopyTasks(preCopyTasks, "pre") - else: - self.LogDebug("Nothing to copy") - - def _RunPostCopy(self, netlist): - self.LogVerbose("copy generated files into netlist directory...") - rulesFiles = [file for file in self.PoCProject.Files(fileType=FileTypes.RulesFile)] # FIXME: get rulefile from netlist object as a rulefile object instead of a path - postCopyTasks = [] - if (rulesFiles): - for rule in rulesFiles[0].PostProcessRules: - if isinstance(rule, CopyRuleMixIn): - sourcePath = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.SourcePath, {}) - destinationPath = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.DestinationPath, {}) - task = CopyTask(Path(sourcePath), Path(destinationPath)) - postCopyTasks.append(task) - else: - postCopyRules = self.Host.PoCConfig[netlist.ConfigSectionName]['PostCopyRules'] - self._ParseCopyRules(postCopyRules, postCopyTasks, "post") - - if (len(postCopyTasks) != 0): - self._ExecuteCopyTasks(postCopyTasks, "post") - else: - self.LogDebug("Nothing to copy") - - def _ParseCopyRules(self, rawList, copyTasks, text): - # read copy tasks - if (len(rawList) != 0): - self.LogDebug("Parsing {0}-copy tasks from config file:".format(text)) - rawList = rawList.split("\n") - - copyRegExpStr = r"^\s*(?P.*?)" # Source filename - copyRegExpStr += r"\s->\s" # Delimiter signs - copyRegExpStr += r"(?P.*?)$" # Destination filename - copyRegExp = re_compile(copyRegExpStr) - - for item in rawList: - preCopyRegExpMatch = copyRegExp.match(item) - if (preCopyRegExpMatch is None): - raise CompilerException("Error in copy rule '{0}'.".format(item)) - - task = CopyTask( - Path(preCopyRegExpMatch.group('SourceFilename')), - Path(preCopyRegExpMatch.group('DestFilename')) - ) - copyTasks.append(task) - self.LogDebug(" {0!s}".format(task)) - else: - self.LogDebug("No {0}-copy tasks specified in config file.".format(text)) - - def _ExecuteCopyTasks(self, tasks, text): - for task in tasks: - if (not self.DryRun and not task.SourcePath.exists()): - raise CompilerException("Cannot {0}-copy '{1!s}' to destination.".format(text, task.SourcePath)) from FileNotFoundError(str(task.SourcePath)) - - if not task.DestinationPath.parent.exists(): - if self.DryRun: - self.LogDryRun("mkdir '{0!s}'.".format(task.DestinationPath.parent)) - else: - try: - task.DestinationPath.parent.mkdir(parents=True) - except OSError as ex: - raise CompilerException("Error while creating '{0!s}'.".format(task.DestinationPath.parent)) from ex - - self.LogDebug("{0}-copying '{1!s}'.".format(text, task.SourcePath)) - if self.DryRun: - self.LogDryRun("Copy '{0!s}' to '{1!s}'.".format(task.SourcePath, task.DestinationPath)) - else: - try: - shutil_copy(str(task.SourcePath), str(task.DestinationPath)) - except OSError as ex: - raise CompilerException("Error while copying '{0!s}'.".format(task.SourcePath)) from ex - - def _RunPostDelete(self, netlist): - self.LogVerbose("copy generated files into netlist directory...") - rulesFiles = [file for file in self.PoCProject.Files(fileType=FileTypes.RulesFile)] # FIXME: get rulefile from netlist object as a rulefile object instead of a path - postDeleteTasks = [] - if (rulesFiles): - for rule in rulesFiles[0].PostProcessRules: - if isinstance(rule, DeleteRuleMixIn): - filePath = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.FilePath, {}) - task = DeleteTask(Path(filePath)) - postDeleteTasks.append(task) - else: - postDeleteRules = self.Host.PoCConfig[netlist.ConfigSectionName]['PostDeleteRules'] - self._ParseDeleteRules(postDeleteRules, postDeleteTasks, "post") - - if self.NoCleanUp: - self.LogWarning("Disabled cleanup. Skipping post-delete rules.") - elif (len(postDeleteTasks) != 0): - self._ExecuteDeleteTasks(postDeleteTasks, "post") - else: - self.LogDebug("Nothing to delete") - - def _ParseDeleteRules(self, rawList, deleteTasks, text): - # read delete tasks - if (len(rawList) != 0): - self.LogDebug("Parse {0}-delete tasks from config file:".format(text)) - rawList = rawList.split("\n") - - deleteRegExpStr = r"^\s*(?P.*?)$" # filename - deleteRegExp = re_compile(deleteRegExpStr) - - for item in rawList: - deleteRegExpMatch = deleteRegExp.match(item) - if (deleteRegExpMatch is None): - raise CompilerException("Error in delete rule '{0}'.".format(item)) - - task = DeleteTask(Path(deleteRegExpMatch.group('Filename'))) - deleteTasks.append(task) - self.LogDebug(" {0!s}".format(task)) - else: - self.LogDebug("No {0}-delete tasks specified in config file.".format(text)) - - def _ExecuteDeleteTasks(self, tasks, text): - for task in tasks: - if (not self.DryRun and not task.FilePath.exists()): - raise CompilerException("Cannot {0}-delete '{1!s}'.".format(text, task.FilePath)) from FileNotFoundError(str(task.FilePath)) - - self.LogDebug("{0}-deleting '{1!s}'.".format(text, task.FilePath)) - if self.DryRun: - self.LogDryRun("Delete '{0!s}'.".format(task.FilePath)) - else: - try: - task.FilePath.unlink() - except OSError as ex: - raise CompilerException("Error while deleting '{0!s}'.".format(task.FilePath)) from ex - - def _RunPreReplace(self, netlist): - self.LogVerbose("Patching files in temporary directory...") - rulesFiles = [file for file in self.PoCProject.Files(fileType=FileTypes.RulesFile)] # FIXME: get rulefile from netlist object as a rulefile object instead of a path - preReplaceTasks = [] - if (rulesFiles): - for rule in rulesFiles[0].PreProcessRules: - if isinstance(rule, ReplaceRuleMixIn): - filePath = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.FilePath, {}) - searchPattern = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.SearchPattern, {}) - replacePattern = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.ReplacePattern, {}) - task = ReplaceTask(Path(filePath), searchPattern, replacePattern, rule.RegExpOption_MultiLine, rule.RegExpOption_DotAll, rule.RegExpOption_CaseInsensitive) - preReplaceTasks.append(task) - elif isinstance(rule, AppendLineRuleMixIn): - filePath = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.FilePath, {}) - appendPattern = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.AppendPattern, {}) - task = AppendLineTask(Path(filePath), appendPattern) - preReplaceTasks.append(task) - elif isinstance(rule, CopyRuleMixIn): - pass - else: - raise CompilerException("Unknown pre-process rule '{0!s}'.".format(rule)) - else: - preReplaceRules = self.Host.PoCConfig[netlist.ConfigSectionName]['PreReplaceRules'] - self._ParseReplaceRules(preReplaceRules, preReplaceTasks, "pre") - - if (len(preReplaceTasks) != 0): - self._ExecuteReplaceTasks(preReplaceTasks, "pre") - else: - self.LogDebug("Nothing to patch.") - - def _RunPostReplace(self, netlist): - self.LogVerbose("Patching files in netlist directory...") - rulesFiles = [file for file in self.PoCProject.Files(fileType=FileTypes.RulesFile)] # FIXME: get rulefile from netlist object as a rulefile object instead of a path - postReplaceTasks = [] - if (rulesFiles): - for rule in rulesFiles[0].PostProcessRules: - if isinstance(rule, ReplaceRuleMixIn): - filePath = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.FilePath, {}) - searchPattern = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.SearchPattern, {}) - replacePattern = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.ReplacePattern, {}) - task = ReplaceTask(Path(filePath), searchPattern, replacePattern, rule.RegExpOption_MultiLine, rule.RegExpOption_DotAll, rule.RegExpOption_CaseInsensitive) - postReplaceTasks.append(task) - elif isinstance(rule, AppendLineRuleMixIn): - filePath = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.FilePath, {}) - appendPattern = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.AppendPattern, {}) - task = AppendLineTask(Path(filePath), appendPattern) - postReplaceTasks.append(task) - elif isinstance(rule, (CopyRuleMixIn, DeleteRuleMixIn)): - pass - else: - raise CompilerException("Unknown post-process rule '{0!s}'.".format(rule)) - else: - postReplaceRules = self.Host.PoCConfig[netlist.ConfigSectionName]['PostReplaceRules'] - self._ParseReplaceRules(postReplaceRules, postReplaceTasks, "post") - - if (len(postReplaceTasks) != 0): - self._ExecuteReplaceTasks(postReplaceTasks, "post") - else: - self.LogDebug("Nothing to patch.") - - def _ParseReplaceRules(self, rawList, replaceTasks, text): - # read replace tasks - if (len(rawList) != 0): - self.LogDebug("Parsing {0}-replacement tasks:".format(text)) - rawList = rawList.split("\n") - - # FIXME: Rework inline replace rule syntax. - replaceRegExpStr = r"^\s*(?P.*?)\s+:" # Filename - replaceRegExpStr += r"(?P[dim]{0,3}):\s+" # RegExp options - replaceRegExpStr += r"\"(?P.*?)\"\s+->\s+" # Search regexp - replaceRegExpStr += r"\"(?P.*?)\"$" # Replace regexp - replaceRegExp = re_compile(replaceRegExpStr) - - for item in rawList: - replaceRegExpMatch = replaceRegExp.match(item) - - if (replaceRegExpMatch is None): - raise CompilerException("Error in replace rule '{0}'.".format(item)) - - task = ReplaceTask( - Path(replaceRegExpMatch.group('Filename')), - replaceRegExpMatch.group('Search'), - replaceRegExpMatch.group('Replace'), - # replaceRegExpMatch.group('Options'), # FIXME: - # replaceRegExpMatch.group('Options'), # FIXME: - # replaceRegExpMatch.group('Options'), # FIXME: - False, False, False - ) - replaceTasks.append(task) - self.LogDebug(" {0!s}".format(task)) - else: - self.LogDebug("No {0}-replace tasks specified in config file.".format(text)) - - def _ExecuteReplaceTasks(self, tasks, text): - for task in tasks: - if (not self.DryRun and not task.FilePath.exists()): - raise CompilerException("Cannot {0}-replace in file '{1!s}'.".format(text, task.FilePath)) from FileNotFoundError(str(task.FilePath)) - self.LogDebug("{0}-replace in file '{1!s}': search for '{2}' replace by '{3}'.".format(text, task.FilePath, task.SearchPattern, task.ReplacePattern)) - - if self.DryRun: - self.LogDryRun("Patch '{0!s}'.".format(task.FilePath)) - else: - regExpFlags = 0 - if task.RegExpOption_CaseInsensitive: regExpFlags |= RE_IGNORECASE - if task.RegExpOption_MultiLine: regExpFlags |= RE_MULTILINE - if task.RegExpOption_DotAll: regExpFlags |= RE_DOTALL - - # compile regexp - regExp = re_compile(task.SearchPattern, regExpFlags) - # open file and read all lines - with task.FilePath.open('r') as fileHandle: - FileContent = fileHandle.read() - # replace - NewContent,replaceCount = re_subn(regExp, task.ReplacePattern, FileContent) - if (replaceCount == 0): - self.LogWarning(" Search pattern '{0}' not found in file '{1!s}'.".format(task.SearchPattern, task.FilePath)) - # open file to write the replaced data - with task.FilePath.open('w') as fileHandle: - fileHandle.write(NewContent) - - def PrintOverallCompileReport(self): - self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) - self.LogQuiet("{HEADLINE}{headline: ^80s}{NOCOLOR}".format(headline="Overall Compile Report", **Init.Foreground)) - self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) - # table header - self.LogQuiet("{Name: <24} | {Duration: >5} | {Status: ^11}".format(Name="Name", Duration="Time", Status="Status")) - self.LogQuiet("-" * 80) - self.PrintCompileReportLine(self._testSuite, 0, 24) - - self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) - self.LogQuiet("Time: {time: >5} Count: {count: <3} Success: {success: <3} Failed: {failed: <2} Errors: {error: <2}".format( - time=to_time(self._testSuite.OverallRunTime), - count=self._testSuite.Count, - success=self._testSuite.SuccessCount, - failed=self._testSuite.FailedCount, - error=self._testSuite.ErrorCount - )) - self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) - - __COMPILE_REPORT_COLOR_TABLE__ = { - CompileStatus.Unknown: "RED", - CompileStatus.InternalError: "DARK_RED", - CompileStatus.SystemError: "DARK_RED", - CompileStatus.CompileError: "RED", - CompileStatus.CompileSuccess: "GREEN" - } - - __COMPILE_REPORT_STATUS_TEXT_TABLE__ = { - CompileStatus.Unknown: "-- ?? --", - CompileStatus.InternalError: "INT. ERROR", - CompileStatus.SystemError: "SYS. ERROR", - CompileStatus.CompileError: "COMP. ERROR", - CompileStatus.CompileSuccess: "SUCCESS" - } - - def PrintCompileReportLine(self, testObject, indent, nameColumnWidth): - _indent = " " * indent - for group in testObject.Groups.values(): - pattern = "{indent}{{groupName: <{nameColumnWidth}}} | | ".format(indent=_indent, nameColumnWidth=nameColumnWidth) - self.LogQuiet(pattern.format(groupName=group.Name)) - self.PrintCompileReportLine(group, indent + 1, nameColumnWidth - 2) - for synthesis in testObject.Synthesises.values(): - pattern = "{indent}{{netlistName: <{nameColumnWidth}}} | {{duration: >5}} | {{{color}}}{{status: ^11}}{{NOCOLOR}}".format( - indent=_indent, nameColumnWidth=nameColumnWidth, color=self.__COMPILE_REPORT_COLOR_TABLE__[synthesis.Status]) - self.LogQuiet(pattern.format( - netlistName=synthesis.Name, - duration=to_time(synthesis.OverallRunTime), - status=self.__COMPILE_REPORT_STATUS_TEXT_TABLE__[synthesis.Status], **Init.Foreground - )) diff --git a/py/Base/Configuration.py b/py/Base/Configuration.py deleted file mode 100644 index 333fcbde..00000000 --- a/py/Base/Configuration.py +++ /dev/null @@ -1,257 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# -# ============================================================================== -# Authors: Patrick Lehmann -# Martin Zabel -# -# Python Class: TODO: -# -# Description: -# ------------------------------------ -# TODO: -# -# License: -# ============================================================================== -# Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair of VLSI-Design, Diagnostics and Architecture -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# ============================================================================== -# -# load dependencies -from collections import OrderedDict -from pathlib import Path - -from Base.Exceptions import ExceptionBase - - -__api__ = [ - 'ConfigurationException', - 'SkipConfigurationException', - 'Configuration' -] -__all__ = __api__ - - -class ConfigurationException(ExceptionBase): - """``ConfigurationException`` is raise while running configuration or database - tasks in PoC - """ - -class SkipConfigurationException(ExceptionBase): - """``SkipConfigurationException`` is a :py:exc:`ConfigurationException`, - which can be skipped. - """ - - - - -# class RegisterSubClassesMeta(type): -# def __new__(mcs, name, bases, members): -# #print("RegisterSubClassesMeta.new: {0} - ".format(name, members)) -# #print() -# inst = super().__new__(mcs, name, bases, members) -# if (len(bases) > 0): -# baseClass = bases[0] -# print(baseClass) -# if issubclass(baseClass, ISubClassRegistration): -# #print("interface match") -# baseClass.RegisterSubClass(inst) -# return inst -# -# class ISubClassRegistration(metaclass=RegisterSubClassesMeta): -# _subclasses = [] -# -# @classmethod -# def RegisterSubClass(cls, subcls): -# print("Register: {0}".format(str(subcls))) -# cls._subclasses.append(subcls) -# -# @property -# def SubClasses(self): -# return self._subclasses - -class Configuration: #(ISubClassRegistration): - """base class for all Configuration classes.""" - _vendor = "Unknown" - _toolName = "Unknown" - _section = "ERROR" - _template = {} - - def __init__(self, host): - self._host = host - - @property - def Host(self): - return self._host - - def IsSupportedPlatform(self): - if (self._host.Platform not in self._template): - return ("ALL" in self._template) - else: - return True - - def IsConfigured(self): - return (len(self._host.PoCConfig.options(self._section)) != 0) - - @classmethod - def GetSections(cls, platform): - if ("ALL" in cls._template): - for sectionName in cls._template['ALL']: - yield sectionName - if (platform in cls._template): - for sectionName in cls._template[platform]: - yield sectionName - - def CheckDependency(self): - return True - - def ConfigureForDarwin(self): - self.ConfigureForAll() - - def ConfigureForLinux(self): - self.ConfigureForAll() - - def ConfigureForWindows(self): - self.ConfigureForAll() - - def ConfigureForAll(self): - if self._toolName is None: - self._ConfigureVendorPath() - - def __str__(self): - if self._toolName is None: return self._vendor - return self._toolName - - def ClearSection(self): - self._host.PoCConfig[self._section] = OrderedDict() - - def _ConfigureVendorPath(self): - if (not self._AskInstalled("Are {0} products installed on your system?".format(self._vendor))): - self.ClearSection() - else: - self._ConfigureInstallationDirectory() - - def _AskInstalled(self, question): - isInstalled = input(" " + question + " [Y/n/p]: ") - isInstalled = isInstalled if isInstalled != "" else "Y" - if (isInstalled in ['p', 'P']): - raise SkipConfigurationException() - elif (isInstalled in ['n', 'N']): - return False - elif (isInstalled in ['y', 'Y']): - return True - else: - raise ConfigurationException("Unsupported choice '{0}'".format(isInstalled)) - - def _ConfigureInstallationDirectory(self): - """ - Asks for installation directory and updates section. - Checks if entered directory exists and returns Path object. - If no installation directory was configured before, then _GetDefaultInstallationDir is called. - """ - if self._host.PoCConfig.has_option(self._section, 'InstallationDirectory'): - defaultPath = Path(self._host.PoCConfig[self._section]['InstallationDirectory']) - else: - unresolved = self._GetDefaultInstallationDirectory() # may return an unresolved configuration string - self._host.PoCConfig[self._section]['InstallationDirectory'] = unresolved # create entry - defaultPath = Path(self._host.PoCConfig[self._section]['InstallationDirectory']) # resolve entry - - directory = input(" {0!s} installation directory [{1!s}]: ".format(self, defaultPath)) - if (directory != ""): - installPath = Path(directory) - else: - installPath = defaultPath - - if (not installPath.exists()): - raise ConfigurationException("{0!s} installation directory '{1!s}' does not exist.".format(self, installPath)) \ - from NotADirectoryError(str(installPath)) - - if directory != "": # update only if user entered something - self._host.PoCConfig[self._section]['InstallationDirectory'] = installPath.as_posix() - self._host.PoCConfig.Interpolation.clear_cache() - - return installPath - - def _GetDefaultInstallationDirectory(self): - """ - Returns unresolved default installation directory (str) from template. - Overwrite function in sub-class for automatic search of installation directory. - """ - return self._template[self._host.Platform][self._section]['InstallationDirectory'] - - def _TestDefaultInstallPath(self, defaults): - """Helper function for automatic search of installation directory.""" - if (self._host.Platform == "Linux"): - p = Path("/opt") / defaults["Linux"] - if (p.exists()): return p - p = Path("/opt") / defaults["Linux"].lower() - if (p.exists()): return p - elif (self._host.Platform == "Windows"): - for drive in "CDEFGH": - p = Path("{0}:/{1}".format(drive, defaults["Windows"])) - try: - if (p.exists()): return p - except OSError: - pass - return None - - def _ConfigureVersion(self): - """ - If no version was configured before, then _GetDefaultVersion is called. - Asks for version and updates section. Returns version as string. - """ - if self._host.PoCConfig.has_option(self._section, 'Version'): - defaultVersion = self._host.PoCConfig[self._section]['Version'] - else: - unresolved = self._GetDefaultVersion() # may return an unresolved configuration string - self._host.PoCConfig[self._section]['Version'] = unresolved # create entry - defaultVersion = self._host.PoCConfig[self._section]['Version'] # resolve entry - - version = input(" {0!s} version [{1!s}]: ".format(self, defaultVersion)) - if version != "": # update only if user entered something - self._host.PoCConfig[self._section]['Version'] = version - self._host.PoCConfig.Interpolation.clear_cache() - else: - version = defaultVersion - - return version - - def _GetDefaultVersion(self): - """ - Returns unresolved default version (str) from template. - Overwrite function in sub-class for automatic search of version. - """ - return self._template[self._host.Platform][self._section]['Version'] - - def _ConfigureBinaryDirectory(self): - """Updates section with value from :attr:`_template` and returns directory - as :class:`Path ` object. - """ - unresolved = self._template[self._host.Platform][self._section]['BinaryDirectory'] - self._host.PoCConfig[self._section]['BinaryDirectory'] = unresolved # create entry - defaultPath = Path(self._host.PoCConfig[self._section]['BinaryDirectory']) # resolve entry - - binPath = defaultPath # may be more complex in the future - - if (not binPath.exists()): - raise ConfigurationException("{0!s} binary directory '{1!s}' does not exist.".format(self, binPath)) \ - from NotADirectoryError(str(binPath)) - - return binPath - - def RunPostConfigurationTasks(self): - """Virtual method. Overwrite to execute post-configuration tasks.""" - pass diff --git a/py/Base/Exceptions.py b/py/Base/Exceptions.py index f3fc16e7..ffd3627b 100644 --- a/py/Base/Exceptions.py +++ b/py/Base/Exceptions.py @@ -5,17 +5,11 @@ # ============================================================================== # Authors: Patrick Lehmann # -# Python Class: TODO -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Module: This module contains exception base classes and common exceptions for PoC. # # License: # ============================================================================== -# Copyright 2007-2015 Technische Universitaet Dresden - Germany +# Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/py/Base/Executable.py b/py/Base/Executable.py index c7a4a289..d82af95a 100644 --- a/py/Base/Executable.py +++ b/py/Base/Executable.py @@ -5,13 +5,7 @@ # ============================================================================== # Authors: Patrick Lehmann # -# Python Class: TODO -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Module: Basic abstraction layer for executables. # # License: # ============================================================================== @@ -61,12 +55,14 @@ class ExecutableException(ExceptionBase): + """This exception is raised by all executable abstraction classes.""" def __init__(self, message=""): super().__init__(message) self.message = message class CommandLineArgument(type): + """Base class (and meta class) for all Arguments classes.""" _value = None # def __new__(mcls, name, bases, nmspc): @@ -75,6 +71,8 @@ class CommandLineArgument(type): class ExecutableArgument(CommandLineArgument): + """Represents the executable.""" + @property def Value(self): return self._value diff --git a/py/Base/Logging.py b/py/Base/Logging.py index 256b15b5..d267bf27 100644 --- a/py/Base/Logging.py +++ b/py/Base/Logging.py @@ -6,13 +6,7 @@ # Authors: Patrick Lehmann # Thomas B. Preusser # -# Python Class: TODO -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Class: Contains PoC's logging (console output) mechanism. # # License: # ============================================================================== @@ -49,6 +43,7 @@ @unique class Severity(Enum): + """Logging message severity levels.""" Fatal = 30 Error = 25 Quiet = 20 @@ -61,7 +56,7 @@ class Severity(Enum): All = 0 def __init__(self, *_): - """Patch the embedded MAP dictionary""" + """Patch the embedded MAP dictionary.""" for k,v in self.__class__.__VHDL_SEVERITY_LEVEL_MAP__.items(): if ((not isinstance(v, self.__class__)) and (v == self.value)): self.__class__.__VHDL_SEVERITY_LEVEL_MAP__[k] = self @@ -85,14 +80,17 @@ def __ge__(self, other): return self.value >= other.value @classmethod def ParseVHDLSeverityLevel(cls, severity, fallback=None): + """Translate a VHDL severity level into logging severity level.""" return cls.__VHDL_SEVERITY_LEVEL_MAP__.get(severity, fallback) class LogEntry: - def __init__(self, message, severity=Severity.Normal, indent=0): - self._severity = severity - self._message = message - self._indent = indent + """Represents a single line log message with a severity and indentation level.""" + def __init__(self, message, severity=Severity.Normal, indent=0, appendLinebreak=True): + self._severity = severity + self._message = message + self._indent = indent + self.AppendLinebreak = appendLinebreak _Log_MESSAGE_FORMAT__ = { Severity.Fatal: "FATAL: {message}", @@ -107,30 +105,44 @@ def __init__(self, message, severity=Severity.Normal, indent=0): } @property - def Severity(self): return self._severity + def Severity(self): + """Return the log message's severity level.""" + return self._severity + @property - def Indent(self): return self._indent + def Indent(self): + """Return the log message's indentation level.""" + return self._indent + @property - def Message(self): return (" " * self._indent) + self._message + def Message(self): + """Return the indented log message.""" + return (" " * self._indent) + self._message def IndentBy(self, indent): + """Increase a log message's indentation level.""" self._indent += indent def __str__(self): return self._Log_MESSAGE_FORMAT__[self._severity].format(message=self._message) + class Logger: - def __init__(self, host, logLevel, printToStdOut=True): - self._host = host + def __init__(self, logLevel, printToStdOut=True): + """Class nitializer.""" self._LogLevel = logLevel self._printToStdOut = printToStdOut self._entries = [] self._baseIndent = 0 @property - def LogLevel(self): return self._LogLevel + def LogLevel(self): + """Return the currently logged minimal severity level.""" + return self._LogLevel @LogLevel.setter - def LogLevel(self, value): self._LogLevel = value + def LogLevel(self, value): + """Set the logged minimal severity level.""" + self._LogLevel = value @property def BaseIndent(self): return self._baseIndent @@ -138,7 +150,7 @@ def BaseIndent(self): return self._baseIndent def BaseIndent(self, value): self._baseIndent = value _Log_MESSAGE_FORMAT__ = { - Severity.Fatal: "{DARKRED}{message}{NOCOLOR}", + Severity.Fatal: "{DARK_RED}{message}{NOCOLOR}", Severity.Error: "{RED}{message}{NOCOLOR}", Severity.Quiet: "{WHITE}{message}{NOCOLOR}", Severity.Warning: "{YELLOW}{message}{NOCOLOR}", @@ -153,7 +165,7 @@ def Write(self, entry): if (entry.Severity >= self._LogLevel): self._entries.append(entry) if self._printToStdOut: - print(self._Log_MESSAGE_FORMAT__[entry.Severity].format(message=entry.Message, **Init.Foreground)) + print(self._Log_MESSAGE_FORMAT__[entry.Severity].format(message=entry.Message, **Init.Foreground), end="\n" if entry.AppendLinebreak else "") return True else: return False @@ -161,96 +173,99 @@ def Write(self, entry): def TryWrite(self, entry): return (entry.Severity >= self._LogLevel) - def WriteFatal(self, message): - return self.Write(LogEntry(message, Severity.Fatal)) + def WriteFatal(self, message, indent=0, appendLinebreak=True): + return self.Write(LogEntry(message, Severity.Fatal, self._baseIndent + indent, appendLinebreak)) - def WriteError(self, message): - return self.Write(LogEntry(message, Severity.Error)) + def WriteError(self, message, indent=0, appendLinebreak=True): + return self.Write(LogEntry(message, Severity.Error, self._baseIndent + indent, appendLinebreak)) - def WriteWarning(self, message): - return self.Write(LogEntry(message, Severity.Warning)) + def WriteWarning(self, message, indent=0, appendLinebreak=True): + return self.Write(LogEntry(message, Severity.Warning, self._baseIndent + indent, appendLinebreak)) - def WriteInfo(self, message): - return self.Write(LogEntry(message, Severity.Info)) + def WriteInfo(self, message, indent=0, appendLinebreak=True): + return self.Write(LogEntry(message, Severity.Info, self._baseIndent + indent, appendLinebreak)) - def WriteQuiet(self, message): - return self.Write(LogEntry(message, Severity.Quiet)) + def WriteQuiet(self, message, indent=0, appendLinebreak=True): + return self.Write(LogEntry(message, Severity.Quiet, self._baseIndent + indent, appendLinebreak)) - def WriteNormal(self, message, indent=0): - return self.Write(LogEntry(message, Severity.Normal, self._baseIndent + indent)) + def WriteNormal(self, message, indent=0, appendLinebreak=True): + return self.Write(LogEntry(message, Severity.Normal, self._baseIndent + indent, appendLinebreak)) - def WriteVerbose(self, message, indent=1): - return self.Write(LogEntry(message, Severity.Verbose, self._baseIndent + indent)) + def WriteVerbose(self, message, indent=1, appendLinebreak=True): + return self.Write(LogEntry(message, Severity.Verbose, self._baseIndent + indent, appendLinebreak)) - def WriteDebug(self, message, indent=2): - return self.Write(LogEntry(message, Severity.Debug, self._baseIndent + indent)) + def WriteDebug(self, message, indent=2, appendLinebreak=True): + return self.Write(LogEntry(message, Severity.Debug, self._baseIndent + indent, appendLinebreak)) - def WriteDryRun(self, message, indent=2): - return self.Write(LogEntry(message, Severity.DryRun, self._baseIndent + indent)) + def WriteDryRun(self, message, indent=2, appendLinebreak=True): + return self.Write(LogEntry(message, Severity.DryRun, self._baseIndent + indent, appendLinebreak)) class ILogable: - """A mixin class to support local logging methods.""" + """A mixin class to provide local logging methods.""" def __init__(self, logger=None): + """MixIn initializer.""" self._logger = logger + # FIXME: Alter methods if a logger is present or set dummy methods + @property def Logger(self): """Return the local logger instance.""" return self._logger - def Log(self, entry): + def Log(self, entry, condition=True): """Write an entry to the local logger.""" - if self._logger is not None: + if ((self._logger is not None) and condition): return self._logger.Write(entry) return False - def _TryLog(self, *args, **kwargs): - if self._logger is not None: + def _TryLog(self, *args, condition=True, **kwargs): + if ((self._logger is not None) and condition): return self._logger.TryWrite(*args, **kwargs) return False - def LogFatal(self, *args, **kwargs): - if self._logger is not None: + def LogFatal(self, *args, condition=True, **kwargs): + if ((self._logger is not None) and condition): return self._logger.WriteFatal(*args, **kwargs) return False - def LogError(self, *args, **kwargs): - if self._logger is not None: + def LogError(self, *args, condition=True, **kwargs): + if ((self._logger is not None) and condition): return self._logger.WriteError(*args, **kwargs) return False - def LogWarning(self, *args, **kwargs): - if self._logger is not None: + def LogWarning(self, *args, condition=True, **kwargs): + if ((self._logger is not None) and condition): return self._logger.WriteWarning(*args, **kwargs) return False - def LogInfo(self, *args, **kwargs): - if self._logger is not None: + def LogInfo(self, *args, condition=True, **kwargs): + if ((self._logger is not None) and condition): return self._logger.WriteInfo(*args, **kwargs) return False - def LogQuiet(self, *args, **kwargs): - if self._logger is not None: + def LogQuiet(self, *args, condition=True, **kwargs): + if ((self._logger is not None) and condition): return self._logger.WriteQuiet(*args, **kwargs) return False - def LogNormal(self, *args, **kwargs): - if self._logger is not None: + def LogNormal(self, *args, condition=True, **kwargs): + if ((self._logger is not None) and condition): return self._logger.WriteNormal(*args, **kwargs) return False - def LogVerbose(self, *args, **kwargs): - if self._logger is not None: + def LogVerbose(self, *args, condition=True, **kwargs): + if ((self._logger is not None) and condition): return self._logger.WriteVerbose(*args, **kwargs) return False - def LogDebug(self, *args, **kwargs): - if self._logger is not None: + def LogDebug(self, *args, condition=True, **kwargs): + if ((self._logger is not None) and condition): return self._logger.WriteDebug(*args, **kwargs) return False - def LogDryRun(self, *args, **kwargs): - if self._logger is not None: + def LogDryRun(self, *args, condition=True, **kwargs): + if ((self._logger is not None) and condition): return self._logger.WriteDryRun(*args, **kwargs) return False diff --git a/py/Base/Project.py b/py/Base/Project.py index bdd6f701..71338ff3 100644 --- a/py/Base/Project.py +++ b/py/Base/Project.py @@ -8,10 +8,6 @@ # # Python Module: TODO # -# Description: -# ------------------------------------ -# TODO: -# # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany @@ -38,7 +34,7 @@ from lib.Functions import merge from Base.Exceptions import CommonException from Parser.FilesParser import VHDLSourceFileMixIn, VerilogSourceFileMixIn, CocotbSourceFileMixIn -from DataBase.Config import Board, Device +from DataBase.Config import Board, Device __api__ = [ diff --git a/py/Base/Shared.py b/py/Base/Shared.py index c82cbbec..88dc8a84 100644 --- a/py/Base/Shared.py +++ b/py/Base/Shared.py @@ -7,12 +7,6 @@ # # Python Class: Base class for *** # -# Description: -# ------------------------------------ -# TODO: -# - -# - -# # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany @@ -36,6 +30,7 @@ from datetime import datetime from os import chdir +from Base import IHost from lib.Functions import Init from lib.Parser import ParserException from Base.Exceptions import CommonException, SkipableCommonException @@ -88,11 +83,8 @@ class __Directories__: Working = None PoCRoot = None - def __init__(self, host, dryRun): - if isinstance(host, ILogable): - ILogable.__init__(self, host.Logger) - else: - ILogable.__init__(self, None) + def __init__(self, host : IHost, dryRun): + ILogable.__init__(self, host.Logger if isinstance(host, ILogable) else None) self._host = host self._dryRun = dryRun diff --git a/py/Base/Simulator.py b/py/Base/Simulator.py deleted file mode 100644 index df7a6cc6..00000000 --- a/py/Base/Simulator.py +++ /dev/null @@ -1,394 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# -# ============================================================================== -# Authors: Patrick Lehmann -# Martin Zabel -# -# Python Class: TODO -# -# Description: -# ------------------------------------ -# TODO: -# - -# - -# -# License: -# ============================================================================== -# Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair of VLSI-Design, Diagnostics and Architecture -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# ============================================================================== -# -# load dependencies -from datetime import datetime -from enum import Enum, unique - -from flags import Flags - -from lib.Decorators import MethodAlias -from lib.Functions import Init -from Base.Exceptions import ExceptionBase, SkipableException -from Base.Logging import LogEntry -from Base.Project import Environment, VHDLVersion -from Base.Shared import Shared, to_time -from DataBase.Entity import WildCard -from DataBase.TestCase import TestCase, SimulationStatus, TestSuite - - -# required for autoapi.sphinx -from lib.SphinxExtensions import DocumentMemberAttribute - - -__api__ = [ - 'SimulatorException', - 'SkipableSimulatorException', - 'PoCSimulationResultNotFoundException', - 'SimulationSteps', - 'SimulationState', - 'SimulationResult', - 'Simulator', - 'PoCSimulationResultFilter' -] -__all__ = __api__ - - -VHDL_TESTBENCH_LIBRARY_NAME = "test" - - -class SimulatorException(ExceptionBase): - """Base class for all SimulatorException classes. It is raised while running - simulation tasks in PoC. - """ - -class SkipableSimulatorException(SimulatorException, SkipableException): - """``SkipableSimulatorException`` is a :py:exc:`SimulatorException`, which - can be skipped. - """ - -class PoCSimulationResultNotFoundException(SkipableSimulatorException): - """This exception is raised if the expected PoC simulation result string was - not found in the simulator's output. - """ - - -@unique -class SimulationSteps(Flags): - """Simulation step enumeration.""" - Prepare = 1 << 0 - CleanUpBefore = 1 << 1 - CleanUpAfter = 1 << 2 - Analyze = 1 << 5 - Elaborate = 1 << 6 - # Compile = 1 << 7 - # Optimize = 1 << 8 - Simulate = 1 << 9 - ShowWaveform = 1 << 10 - ShowReport = 1 << 15 - Recompile = 1 << 25 - Resimulate = 1 << 26 - # Review = 1 << 27 - - def __and__(self, other): - if isinstance(other, bool): - return self if other else self.__class__.no_flags - else: - return super().__and__(other) - -@unique -class SimulationState(Enum): - """Simulation state enumeration.""" - Prepare = 0 - Analyze = 1 - Elaborate = 2 - Optimize = 3 - Simulate = 4 - View = 5 - -@unique -class SimulationResult(Enum): - """Simulation result enumeration.""" - NotRun = 0 - Error = 1 - Failed = 2 - NoAsserts = 3 - Passed = 4 - GUIRun = 5 - - -class Simulator(Shared): - """Base class for all Simulator classes.""" - - ENVIRONMENT = Environment.Simulation - VHDL_VERSION = VHDLVersion.VHDL2008 - - class __Directories__(Shared.__Directories__): - PreCompiled = None - - @DocumentMemberAttribute() - def __init__(self, host, dryRun, simulationSteps : SimulationSteps): - """Class initializer - - :type host: object - :param host: The hosting instance for this instance. - :type dryRun: bool - :param dryRun: Enable dry-run mode - :type simulationSteps: SimulationSteps - :param simulationSteps: A set of simulation step to precess. - """ - super().__init__(host, dryRun) - - self._vhdlVersion = None - self._vhdlGenerics = None - self._toolChain = None - - self._simulationSteps = simulationSteps - self._testSuite = TestSuite() # TODO: This includes not the read ini files phases ... - self._state = SimulationState.Prepare - self._analyzeTime = None - self._elaborationTime = None - self._simulationTime = None - - # class properties - # ============================================================================ - @property - def TestSuite(self): return self._testSuite - - def _PrepareSimulationEnvironment(self): - self.LogNormal("Preparing simulation environment...") - self._PrepareEnvironment() - - def _PrepareEnvironment_PurgeDirectory(self): - if (SimulationSteps.CleanUpBefore in self._simulationSteps): - super()._PrepareEnvironment_PurgeDirectory() - - @MethodAlias(Shared._Prepare) - def _PrepareSimulator(self): - pass - - def RunAll(self, fqnList, *args, **kwargs): - """Run a list of testbenches. Expand wildcards to all selected testbenches.""" - self._testSuite.StartTimer() - self.Logger.BaseIndent = int(len(fqnList) > 1) - try: - for fqn in fqnList: - entity = fqn.Entity - if (isinstance(entity, WildCard)): - self.Logger.BaseIndent = 1 - for testbench in entity.GetVHDLTestbenches(): - self.TryRun(testbench, *args, **kwargs) - else: - testbench = entity.VHDLTestbench - self.TryRun(testbench, *args, **kwargs) - except KeyboardInterrupt: - self.LogError("Received a keyboard interrupt.") - finally: - self._testSuite.StopTimer() - - if (SimulationSteps.ShowReport in self._simulationSteps): - self.PrintOverallSimulationReport() - - return self._testSuite.IsAllPassed - - def TryRun(self, testbench, *args, **kwargs): - """Try to run a testbench. Skip skipable exceptions by printing the error and its cause.""" - __SIMULATION_STATE_TO_TESTCASE_STATUS__ = { - SimulationState.Prepare: SimulationStatus.InternalError, - SimulationState.Analyze: SimulationStatus.AnalyzeError, - SimulationState.Elaborate: SimulationStatus.ElaborationError, - # SimulationState.Optimize: SimulationStatus.ElaborationError, - SimulationState.Simulate: SimulationStatus.SimulationError - } - - testCase = TestCase(testbench) - self._testSuite.AddTestCase(testCase) - testCase.StartTimer() - try: - self.Run(testbench, *args, **kwargs) - testCase.UpdateStatus(testbench.Result) - except SkipableSimulatorException as ex: - testCase.Status = __SIMULATION_STATE_TO_TESTCASE_STATUS__[self._state] - - self.LogQuiet(" {RED}ERROR:{NOCOLOR} {ExMsg}".format(ExMsg=ex.message, **Init.Foreground)) - cause = ex.__cause__ - if (cause is not None): - self.LogQuiet(" {YELLOW}{ExType}:{NOCOLOR} {ExMsg!s}".format(ExType=cause.__class__.__name__, ExMsg=cause, **Init.Foreground)) - cause = cause.__cause__ - if (cause is not None): - self.LogQuiet(" {YELLOW}{ExType}:{NOCOLOR} {ExMsg!s}".format(ExType=cause.__class__.__name__, ExMsg=cause, **Init.Foreground)) - self.LogQuiet(" {RED}[SKIPPED DUE TO ERRORS]{NOCOLOR}".format(**Init.Foreground)) - except SimulatorException: - testCase.Status = __SIMULATION_STATE_TO_TESTCASE_STATUS__[self._state] - raise - except ExceptionBase: - testCase.Status = SimulationStatus.SystemError - raise - finally: - testCase.StopTimer() - - def Run(self, testbench, board, vhdlVersion, vhdlGenerics=None): - """Write the Testbench message line, create a PoCProject and add the first *.files file to it.""" - self.LogQuiet("{CYAN}Testbench: {0!s}{NOCOLOR}".format(testbench.Parent, **Init.Foreground)) - - testbench.Result = SimulationResult.NotRun - - self._vhdlVersion = vhdlVersion - self._vhdlGenerics = vhdlGenerics - - # setup all needed paths to execute fuse - self._CreatePoCProject(testbench.ModuleName, board) - self._AddFileListFile(testbench.FilesFile) - - self._prepareTime = self._GetTimeDeltaSinceLastEvent() - - if self._simulationSteps.CleanUpBefore: - pass - - if self._simulationSteps.Prepare: - pass - - if self._simulationSteps.Analyze: - self.LogNormal("Running analysis for every vhdl file...") - self._state = SimulationState.Analyze - self._RunAnalysis(testbench) - self._analyzeTime = self._GetTimeDeltaSinceLastEvent() - - if self._simulationSteps.Elaborate: - self.LogNormal("Running elaboration...") - self._state = SimulationState.Elaborate - self._RunElaboration(testbench) - self._elaborationTime = self._GetTimeDeltaSinceLastEvent() - - # if self._simulationSteps.Optimize: - # pass - - if self._simulationSteps.Simulate: - self.LogNormal("Running simulation...") - self._state = SimulationState.Simulate - self._RunSimulation(testbench) - self._simulationTime = self._GetTimeDeltaSinceLastEvent() - - if self._simulationSteps.ShowWaveform: - self.LogNormal("Executing waveform viewer...") - self._state = SimulationState.View - self._RunView(testbench) - - self._endAt = datetime.now() - - def _RunAnalysis(self, testbench): - pass - - def _RunElaboration(self, testbench): - pass - - def _RunSimulation(self, testbench): - pass - - def _RunView(self, testbench): - pass - - def PrintOverallSimulationReport(self): - self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) - self.LogQuiet("{HEADLINE}{headline: ^80s}{NOCOLOR}".format(headline="Overall Simulation Report", **Init.Foreground)) - self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) - # table header - self.LogQuiet("{Name: <24} | {Duration: >5} | {Status: ^11}".format(Name="Name", Duration="Time", Status="Status")) - self.LogQuiet("-" * 80) - self.PrintSimulationReportLine(self._testSuite, 0, 24) - - self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) - self.LogQuiet("Time: {time: >5} Count: {count: <3} Passed: {passed: <3} No Asserts: {noassert: <2} Failed: {failed: <2} Errors: {error: <2}".format( - time=to_time(self._testSuite.OverallRunTime), - count=self._testSuite.Count, - passed=self._testSuite.PassedCount, - noassert=self._testSuite.NoAssertsCount, - failed=self._testSuite.FailedCount, - error=self._testSuite.ErrorCount - )) - self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) - - __SIMULATION_REPORT_COLOR_TABLE__ = { - SimulationStatus.Unknown: "RED", - SimulationStatus.InternalError: "DARK_RED", - SimulationStatus.SystemError: "DARK_RED", - SimulationStatus.AnalyzeError: "DARK_RED", - SimulationStatus.ElaborationError: "DARK_RED", - SimulationStatus.SimulationError: "RED", - SimulationStatus.SimulationFailed: "RED", - SimulationStatus.SimulationNoAsserts: "YELLOW", - SimulationStatus.SimulationSuccess: "GREEN", - SimulationStatus.SimulationGUIRun: "YELLOW" - } - - __SIMULATION_REPORT_STATUS_TEXT_TABLE__ = { - SimulationStatus.Unknown: "-- ?? --", - SimulationStatus.InternalError: "INT. ERROR", - SimulationStatus.SystemError: "SYS. ERROR", - SimulationStatus.AnalyzeError: "ANA. ERROR", - SimulationStatus.ElaborationError: "ELAB. ERROR", - SimulationStatus.SimulationError: "SIM. ERROR", - SimulationStatus.SimulationFailed: "FAILED", - SimulationStatus.SimulationNoAsserts: "NO ASSERTS", - SimulationStatus.SimulationSuccess: "PASSED", - SimulationStatus.SimulationGUIRun: "GUI RUN" - } - - def PrintSimulationReportLine(self, testObject, indent, nameColumnWidth): - _indent = " " * indent - for group in testObject.Groups.values(): - pattern = "{indent}{{groupName: <{nameColumnWidth}}} | | ".format(indent=_indent, nameColumnWidth=nameColumnWidth) - self.LogQuiet(pattern.format(groupName=group.Name)) - self.PrintSimulationReportLine(group, indent + 1, nameColumnWidth - 2) - for testCase in testObject.TestCases.values(): - pattern = "{indent}{{testcaseName: <{nameColumnWidth}}} | {{duration: >5}} | {{{color}}}{{status: ^11}}{{NOCOLOR}}".format( - indent=_indent, nameColumnWidth=nameColumnWidth, color=self.__SIMULATION_REPORT_COLOR_TABLE__[testCase.Status]) - self.LogQuiet(pattern.format(testcaseName=testCase.Name, duration=to_time(testCase.OverallRunTime), - status=self.__SIMULATION_REPORT_STATUS_TEXT_TABLE__[testCase.Status], **Init.Foreground)) - - -def PoCSimulationResultFilter(gen, simulationResult): - state = 0 - for line in gen: - if ((state == 0) and (line.Message == "========================================")): - state += 1 - elif ((state == 1) and (line.Message == "POC TESTBENCH REPORT")): - state += 1 - elif ((state == 2) and (line.Message == "========================================")): - state += 1 - elif ((state == 3) and (line.Message == "========================================")): - state += 1 - elif ((state == 4) and line.Message.startswith("SIMULATION RESULT = ")): - state += 1 - if line.Message.endswith("FAILED"): - color = Init.Foreground['RED'] - simulationResult <<= SimulationResult.Failed - elif line.Message.endswith("NO ASSERTS"): - color = Init.Foreground['YELLOW'] - simulationResult <<= SimulationResult.NoAsserts - elif line.Message.endswith("PASSED"): - color = Init.Foreground['GREEN'] - simulationResult <<= SimulationResult.Passed - else: - color = Init.Foreground['RED'] - simulationResult <<= SimulationResult.Error - - yield LogEntry("{COLOR}{line}{NOCOLOR}".format(COLOR=color,line=line.Message, **Init.Foreground), line.Severity, line.Indent) - continue - elif ((state == 5) and (line.Message == "========================================")): - state += 1 - - yield line - - if (state != 6): raise PoCSimulationResultNotFoundException("No PoC Testbench Report in simulator output found.") diff --git a/py/Base/ToolChain.py b/py/Base/ToolChain.py deleted file mode 100644 index 214de0aa..00000000 --- a/py/Base/ToolChain.py +++ /dev/null @@ -1,46 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# -# ============================================================================== -# Authors: Patrick Lehmann -# Martin Zabel -# -# Python Class: Base class for all PoC***Compilers -# -# Description: -# ------------------------------------ -# TODO: -# - -# - -# -# License: -# ============================================================================== -# Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair of VLSI-Design, Diagnostics and Architecture -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# ============================================================================== -# -# load dependencies -from Base.Exceptions import ExceptionBase - - -__api__ = [ - 'ToolChainException' -] -__all__ = __api__ - - -class ToolChainException(ExceptionBase): - pass diff --git a/py/Base/__init__.py b/py/Base/__init__.py index 793b2851..dde93f9a 100644 --- a/py/Base/__init__.py +++ b/py/Base/__init__.py @@ -3,18 +3,13 @@ # kate: tab-width 2; replace-tabs off; indent-width 2; # # ============================================================================== -# Authors: Patrick Lehmann -# -# Python Sub Module: Saves The PoC-Library configuration as python source code. -# -# Description: -# ------------------------------------ -# TODO: +# Authors: Patrick Lehmann # +# Python Package: Saves The PoC-Library configuration as python source code. # # License: # ============================================================================== -# Copyright 2007-2015 Technische Universitaet Dresden - Germany +# Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,3 +25,30 @@ # limitations under the License. # ============================================================================== # +# load dependencies +from lib.ExtendedConfigParser import ExtendedConfigParser +from Base.Logging import ILogable + + +__api__ = [ + 'IHost' +] +__all__ = __api__ + + +class IHost(ILogable): + """This is a type hint class (interface description) for a host instance. + + It's needed until PoC requires Python 3.6. + """ + + # instance fields + Platform = "string" + PoCConfig = ExtendedConfigParser() + + # methods + def SaveAndReloadPoCConfiguration(self): pass + + # Syntax not supported by Python 3.5 -> requires 3.6 + # Platform : str = None + # PoCConfig : ExtendedConfigParser = None diff --git a/py/Compiler/ISECompiler.py b/py/Compiler/ISECompiler.py index 10de1847..a72d53e4 100644 --- a/py/Compiler/ISECompiler.py +++ b/py/Compiler/ISECompiler.py @@ -5,13 +5,7 @@ # ============================================================================== # Authors: Patrick Lehmann # -# Python Class: This ISECompiler compiles any IPCores for the ISE tool chain -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Module: Xilinx ISE synthesizer (compiler). # # License: # ============================================================================== @@ -33,8 +27,8 @@ # # load dependencies from Base.Project import ToolChain, Tool -from Base.Compiler import Compiler as BaseCompiler -from DataBase.Entity import WildCard, FQN, EntityTypes +from DataBase.Entity import WildCard, FQN, EntityTypes +from Compiler import Compiler as BaseCompiler from Compiler.XCOCompiler import Compiler as XCOCompiler from Compiler.XSTCompiler import Compiler as XSTCompiler diff --git a/py/Compiler/LSECompiler.py b/py/Compiler/LSECompiler.py index e39c11e2..6823e955 100644 --- a/py/Compiler/LSECompiler.py +++ b/py/Compiler/LSECompiler.py @@ -6,13 +6,7 @@ # Authors: Patrick Lehmann # Martin Zabel # -# Python Class: This PoCXCOCompiler compiles xco IPCores to netlists -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Module: Lattice Diamond synthesizer (compiler). # # License: # ============================================================================== @@ -37,11 +31,11 @@ from pathlib import Path from Base.Exceptions import PlatformNotSupportedException -from Base.Compiler import Compiler as BaseCompiler, CompilerException, SkipableCompilerException, CompileState from Base.Project import ToolChain, Tool, VHDLVersion -from DataBase.Entity import WildCard -from ToolChains.Lattice.Lattice import LatticeException +from DataBase.Entity import WildCard +from ToolChains.Lattice import LatticeException from ToolChains.Lattice.Diamond import Diamond, SynthesisArgumentFile +from Compiler import CompilerException, SkipableCompilerException, CompileState, Compiler as BaseCompiler __api__ = [ diff --git a/py/Compiler/QuartusCompiler.py b/py/Compiler/QuartusCompiler.py index a9615704..3de267e8 100644 --- a/py/Compiler/QuartusCompiler.py +++ b/py/Compiler/QuartusCompiler.py @@ -6,13 +6,7 @@ # Authors: Patrick Lehmann # Martin Zabel # -# Python Class: This PoCXCOCompiler compiles xco IPCores to netlists -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Module: Altera Quartus synthesizer (compiler). # # License: # ============================================================================== @@ -37,9 +31,9 @@ from pathlib import Path from Base.Project import ToolChain, Tool -from Base.Compiler import Compiler as BaseCompiler, CompilerException, SkipableCompilerException, CompileState -from DataBase.Entity import WildCard +from DataBase.Entity import WildCard from ToolChains.Altera.Quartus import QuartusException, Quartus, QuartusSettings, QuartusProjectFile +from Compiler import CompilerException, SkipableCompilerException, CompileState, Compiler as BaseCompiler __api__ = [ @@ -64,9 +58,13 @@ def __init__(self, host, dryRun, noCleanUp): def _PrepareCompiler(self): super()._PrepareCompiler() - quartusSection = self.Host.PoCConfig['INSTALL.Altera.Quartus'] - binaryPath = Path(quartusSection['BinaryDirectory']) - version = quartusSection['Version'] + # XXX: check SectionName if Quartus is configured + # quartusSection = self.Host.PoCConfig['INSTALL.Altera.Quartus'] + # binaryPath = Path(quartusSection['BinaryDirectory']) + # version = quartusSection['Version'] + + binaryPath = Path(self.Host.PoCConfig['INSTALL.Quartus']['BinaryDirectory']) + version = self.Host.PoCConfig['INSTALL.Quartus']['Version'] self._toolChain = Quartus(self.Host.Platform, self.DryRun, binaryPath, version, logger=self.Logger) def RunAll(self, fqnList, *args, **kwargs): diff --git a/py/Compiler/VivadoCompiler.py b/py/Compiler/VivadoCompiler.py index 062da16d..c95bb209 100644 --- a/py/Compiler/VivadoCompiler.py +++ b/py/Compiler/VivadoCompiler.py @@ -5,13 +5,7 @@ # ============================================================================== # Authors: Patrick Lehmann # -# Python Class: This SynthCompiler compiles VHDL source files to design checkpoints -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Module: Xilinx Vivado synthesizer (compiler). # # License: # ============================================================================== @@ -36,9 +30,9 @@ from pathlib import Path from Base.Project import ToolChain, Tool, FileTypes -from Base.Compiler import Compiler as BaseCompiler, CompilerException, SkipableCompilerException, CompileState -from DataBase.Entity import WildCard +from DataBase.Entity import WildCard from ToolChains.Xilinx.Vivado import Vivado, VivadoException +from Compiler import CompilerException, SkipableCompilerException, CompileState, Compiler as BaseCompiler __api__ = [ diff --git a/py/Compiler/XCICompiler.py b/py/Compiler/XCICompiler.py index 7fb864fe..64428168 100644 --- a/py/Compiler/XCICompiler.py +++ b/py/Compiler/XCICompiler.py @@ -5,13 +5,7 @@ # ============================================================================== # Authors: Patrick Lehmann # -# Python Class: This XCICompiler compiles xci IPCores to netlists -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Module: Xilinx Vivado IP Catalog synthesizer (compiler) compiles xci IPCores to netlists. # # License: # ============================================================================== @@ -39,9 +33,9 @@ from textwrap import dedent from Base.Project import ToolChain, Tool -from Base.Compiler import Compiler as BaseCompiler, CompilerException, SkipableCompilerException, CompileState -from DataBase.Entity import WildCard +from DataBase.Entity import WildCard from ToolChains.Xilinx.Vivado import Vivado, VivadoException +from Compiler import CompilerException, SkipableCompilerException, CompileState, Compiler as BaseCompiler __api__ = [ diff --git a/py/Compiler/XCOCompiler.py b/py/Compiler/XCOCompiler.py index 4df12c15..2fbab6a1 100644 --- a/py/Compiler/XCOCompiler.py +++ b/py/Compiler/XCOCompiler.py @@ -6,13 +6,7 @@ # Authors: Patrick Lehmann # Martin Zabel # -# Python Class: This XCOCompiler compiles xco IPCores to netlists -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Module: Xilinx Core Generator (compiler) compiles xco IPCores to netlists. # # License: # ============================================================================== @@ -40,9 +34,9 @@ from textwrap import dedent from Base.Project import ToolChain, Tool -from Base.Compiler import Compiler as BaseCompiler, CompilerException, SkipableCompilerException, CompileState -from DataBase.Entity import WildCard +from DataBase.Entity import WildCard from ToolChains.Xilinx.ISE import ISE, ISEException +from Compiler import CompilerException, SkipableCompilerException, CompileState, Compiler as BaseCompiler __api__ = [ diff --git a/py/Compiler/XSTCompiler.py b/py/Compiler/XSTCompiler.py index 78b193b6..7b4fc2c5 100644 --- a/py/Compiler/XSTCompiler.py +++ b/py/Compiler/XSTCompiler.py @@ -6,13 +6,7 @@ # Authors: Patrick Lehmann # Martin Zabel # -# Python Class: This XSTCompiler compiles VHDL source files to netlists -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Module: Xilinx ISE synthesizer (compiler). # # License: # ============================================================================== @@ -37,10 +31,10 @@ from pathlib import Path from Base.Project import ToolChain, Tool -from Base.Compiler import Compiler as BaseCompiler, CompilerException, SkipableCompilerException, CompileState -from DataBase.Entity import WildCard -from ToolChains.Xilinx.Xilinx import XilinxProjectExportMixIn +from DataBase.Entity import WildCard +from ToolChains.Xilinx import XilinxProjectExportMixIn from ToolChains.Xilinx.ISE import ISE, ISEException +from Compiler import CompilerException, SkipableCompilerException, CompileState, Compiler as BaseCompiler __api__ = [ diff --git a/py/Compiler/__init__.py b/py/Compiler/__init__.py index 02303ff5..c458fc14 100644 --- a/py/Compiler/__init__.py +++ b/py/Compiler/__init__.py @@ -7,11 +7,6 @@ # # Python Sub Module: TODO: # -# Description: -# ------------------------------------ -# TODO: -# -# # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany @@ -30,3 +25,568 @@ # limitations under the License. # ============================================================================== # +from enum import unique, Enum +from pathlib import Path +from re import compile as re_compile, IGNORECASE, MULTILINE, DOTALL, subn +from shutil import copy as shutil_copy + +from flags import Flags + +from lib.Functions import Init +from lib.Parser import ParserException +from Base import IHost +from Base.Exceptions import ExceptionBase, SkipableException +from Base.Project import Environment, VHDLVersion, FileTypes +from Base.Shared import Shared, to_time +from Parser.RulesParser import CopyRuleMixIn, DeleteRuleMixIn, ReplaceRuleMixIn, AppendLineRuleMixIn +from DataBase.Solution import RulesFile +from DataBase.TestCase import SynthesisSuite, CompileStatus, Synthesis + +# required for autoapi.sphinx +from lib.SphinxExtensions import DocumentMemberAttribute + + +__api__ = [ + 'CompilerException', + 'SkipableCompilerException', + 'CopyTask', + 'DeleteTask', + 'ReplaceTask', + 'AppendLineTask', + 'CompileState', + 'CompileResult', + 'Compiler' +] +__all__ = __api__ + + +class CompilerException(ExceptionBase): + """Base class for all CompilerException classes. It is raised while running + compiler (synthesis) tasks in PoC. + """ + + +class SkipableCompilerException(CompilerException, SkipableException): + """``SkipableCompilerException`` is a :py:exc:`CompilerException`, which + can be skipped. + """ + + +class CopyTask(CopyRuleMixIn): + """This class represents a 'copy task' and inherits the partial class + :class:`CopyRuleMixIn `. + """ + + +class DeleteTask(DeleteRuleMixIn): + """This class represents a 'delete task' and inherits the partial class + :class:`DeleteRuleMixIn `. + """ + + +class ReplaceTask(ReplaceRuleMixIn): + """This class represents a 'replace task' and inherits the partial class + :class:`ReplaceRuleMixIn `. + """ + + +class AppendLineTask(AppendLineRuleMixIn): + """This class represents a 'append line task' and inherits the partial class + :class:`AppendLineRuleMixIn `. + """ + + +@unique +class CompileSteps(Flags): + """Compiler step enumeration.""" + Prepare = 1 << 0 + CleanUpBefore = 1 << 1 + CleanUpAfter = 1 << 2 + Synthesize = 1 << 5 + Merge = 1 << 6 + AnalyzeTiming = 1 << 7 + Place = 1 << 8 + Route = 1 << 9 + WriteBitfile = 1 << 10 + ShowReport = 1 << 15 + # Recompile = 1 << 25 + # Resimulate = 1 << 26 + # Review = 1 << 27 + +@unique +class CompileState(Enum): + """Compile state enumeration.""" + Prepare = 0 + PreCopy = 10 + PrePatch = 11 + + Compile = 50 + # Analyze = 61 + # Elaborate = 62 + # Optimize = 63 + # Translate = 64 + # Map = 65 + # Place = 66 + # Route = 67 + + PostCopy = 90 + PostPatch = 91 + PostDelete = 92 + CleanUp = 99 + +@unique +class CompileResult(Enum): + """Compilation result enumeration.""" + NotRun = 0 + Error = 1 + Failed = 2 + Success = 3 + + +class Compiler(Shared): + """Base class for all Compiler classes.""" + + ENVIRONMENT = Environment.Synthesis + VHDL_VERSION = VHDLVersion.VHDL93 + + class __Directories__(Shared.__Directories__): + Netlist = None + Source = None + Destination = None + + @DocumentMemberAttribute() + def __init__(self, host : IHost, dryRun, noCleanUp): + """Class initializer + + :type host: object + :param host: The hosting instance for this instance. + :type dryRun: bool + :param dryRun: Enable dry-run mode + :type noCleanUp: bool + :param noCleanUp: Don't clean up after a run. + """ + super().__init__(host, dryRun) + + self._noCleanUp = noCleanUp + + self._testSuite = SynthesisSuite() # TODO: This includes not the read ini files phases ... + self._state = CompileState.Prepare + self._preTasksTime = None + self._compileTime = None + self._postTasksTime = None + + @property + def NoCleanUp(self): return self._noCleanUp + + def _PrepareCompiler(self): + """Prepare for compilation. This method forwards to :py:meth:`Base.Compiler.Compiler._Prepare`, + which is inherited from :py:class:`Base.Shared.Shared`. + """ + + def TryRun(self, netlist, *args, **kwargs): + """Try to run a testbench. Skip skipable exceptions by printing the error and its cause.""" + + __COMPILE_STATE_TO_SYNTHESIS_STATUS__ = { + CompileState.Prepare: CompileStatus.InternalError, + CompileState.PreCopy: CompileStatus.SystemError, + CompileState.PrePatch: CompileStatus.SystemError, + CompileState.Compile: CompileStatus.CompileError, + CompileState.PostCopy: CompileStatus.SystemError, + CompileState.PostPatch: CompileStatus.SystemError, + CompileState.PostDelete: CompileStatus.SystemError + } + + synthesis = Synthesis(netlist) + self._testSuite.AddSynthesis(synthesis) + synthesis.StartTimer() + try: + self.Run(netlist, *args, **kwargs) + # synthesis.UpdateStatus(netlist.Result) + synthesis.Status = CompileStatus.CompileSuccess + except SkipableCompilerException as ex: + synthesis.Status = __COMPILE_STATE_TO_SYNTHESIS_STATUS__[self._state] + + self.LogQuiet(" {RED}ERROR:{NOCOLOR} {0}".format(ex.message, **Init.Foreground)) + cause = ex.__cause__ + if (cause is not None): + self.LogQuiet(" {YELLOW}{ExType}:{NOCOLOR} {ExMsg!s}".format(ExType=cause.__class__.__name__, ExMsg=cause, **Init.Foreground)) + cause = cause.__cause__ + if (cause is not None): + self.LogQuiet(" {YELLOW}{ExType}:{NOCOLOR} {ExMsg!s}".format(ExType=cause.__class__.__name__, ExMsg=cause, **Init.Foreground)) + self.LogQuiet(" {RED}[SKIPPED DUE TO ERRORS]{NOCOLOR}".format(**Init.Foreground)) + except CompilerException: + synthesis.Status = __COMPILE_STATE_TO_SYNTHESIS_STATUS__[self._state] + raise + except ExceptionBase: + synthesis.Status = CompileStatus.SystemError + raise + finally: + synthesis.StopTimer() + + def Run(self, netlist, board): + """Run a testbench.""" + + self.LogQuiet("{CYAN}IP core: {0!s}{NOCOLOR}".format(netlist.Parent, **Init.Foreground)) + # # TODO: refactor + # self.LogNormal("Checking for dependencies:") + # for dependency in netlist.Dependencies: + # print(" " + str(dependency)) + + # setup all needed paths to execute fuse + self._PrepareCompilerEnvironment(board.Device) + self._WriteSpecialSectionIntoConfig(board.Device) + + self._CreatePoCProject(netlist.ModuleName, board) + if netlist.FilesFile is not None: self._AddFileListFile(netlist.FilesFile) + if (netlist.RulesFile is not None): self._AddRulesFiles(netlist.RulesFile) + + def _PrepareCompilerEnvironment(self, device): + self.LogNormal("Preparing synthesis environment...") + self.Directories.Destination = self.Directories.Netlist / str(device) + + self._PrepareEnvironment() + + # create output directory for CoreGen if not existent + if (not self.Directories.Destination.exists()) : + self.LogVerbose("Creating output directory for generated files.") + self.LogDebug("Output directory: {0!s}.".format(self.Directories.Destination)) + try: + self.Directories.Destination.mkdir(parents=True) + except OSError as ex: + raise CompilerException("Error while creating '{0!s}'.".format(self.Directories.Destination)) from ex + + def _WriteSpecialSectionIntoConfig(self, device): + # add the key Device to section SPECIAL at runtime to change interpolation results + self.Host.PoCConfig['SPECIAL'] = {} + self.Host.PoCConfig['SPECIAL']['Device'] = device.ShortName + self.Host.PoCConfig['SPECIAL']['DeviceSeries'] = device.Series + self.Host.PoCConfig['SPECIAL']['OutputDir'] = self.Directories.Working.as_posix() + + def _AddRulesFiles(self, rulesFilePath): + self.LogVerbose("Reading rules from '{0!s}'".format(rulesFilePath)) + # add the *.rules file, parse and evaluate it + try: + rulesFile = self._pocProject.AddFile(RulesFile(rulesFilePath)) + rulesFile.Parse() + except ParserException as ex: + raise SkipableCompilerException("Error while parsing '{0!s}'.".format(rulesFilePath)) from ex + + self.LogDebug("Pre-process rules:") + for rule in rulesFile.PreProcessRules: + self.LogDebug(" {0!s}".format(rule)) + self.LogDebug("Post-process rules:") + for rule in rulesFile.PostProcessRules: + self.LogDebug(" {0!s}".format(rule)) + + def _RunPreCopy(self, netlist): + self.LogVerbose("Copy further input files into temporary directory...") + rulesFiles = [file for file in self.PoCProject.Files(fileType=FileTypes.RulesFile)] # FIXME: get rulefile from netlist object as a rulefile object instead of a path + preCopyTasks = [] + if (rulesFiles): + for rule in rulesFiles[0].PreProcessRules: + if isinstance(rule, CopyRuleMixIn): + sourcePath = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.SourcePath, {}) + destinationPath = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.DestinationPath, {}) + task = CopyTask(Path(sourcePath), Path(destinationPath)) + preCopyTasks.append(task) + else: + preCopyRules = self.Host.PoCConfig[netlist.ConfigSectionName]['PreCopyRules'] + self._ParseCopyRules(preCopyRules, preCopyTasks, "pre") + + if (len(preCopyTasks) != 0): + self._ExecuteCopyTasks(preCopyTasks, "pre") + else: + self.LogDebug("Nothing to copy") + + def _RunPostCopy(self, netlist): + self.LogVerbose("copy generated files into netlist directory...") + rulesFiles = [file for file in self.PoCProject.Files(fileType=FileTypes.RulesFile)] # FIXME: get rulefile from netlist object as a rulefile object instead of a path + postCopyTasks = [] + if (rulesFiles): + for rule in rulesFiles[0].PostProcessRules: + if isinstance(rule, CopyRuleMixIn): + sourcePath = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.SourcePath, {}) + destinationPath = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.DestinationPath, {}) + task = CopyTask(Path(sourcePath), Path(destinationPath)) + postCopyTasks.append(task) + else: + postCopyRules = self.Host.PoCConfig[netlist.ConfigSectionName]['PostCopyRules'] + self._ParseCopyRules(postCopyRules, postCopyTasks, "post") + + if (len(postCopyTasks) != 0): + self._ExecuteCopyTasks(postCopyTasks, "post") + else: + self.LogDebug("Nothing to copy") + + def _ParseCopyRules(self, rawList, copyTasks, text): + # read copy tasks + if (len(rawList) != 0): + self.LogDebug("Parsing {0}-copy tasks from config file:".format(text)) + rawList = rawList.split("\n") + + copyRegExpStr = r"^\s*(?P.*?)" # Source filename + copyRegExpStr += r"\s->\s" # Delimiter signs + copyRegExpStr += r"(?P.*?)$" # Destination filename + copyRegExp = re_compile(copyRegExpStr) + + for item in rawList: + preCopyRegExpMatch = copyRegExp.match(item) + if (preCopyRegExpMatch is None): + raise CompilerException("Error in copy rule '{0}'.".format(item)) + + task = CopyTask( + Path(preCopyRegExpMatch.group('SourceFilename')), + Path(preCopyRegExpMatch.group('DestFilename')) + ) + copyTasks.append(task) + self.LogDebug(" {0!s}".format(task)) + else: + self.LogDebug("No {0}-copy tasks specified in config file.".format(text)) + + def _ExecuteCopyTasks(self, tasks, text): + for task in tasks: + if (not self.DryRun and not task.SourcePath.exists()): + raise CompilerException("Cannot {0}-copy '{1!s}' to destination.".format(text, task.SourcePath)) from FileNotFoundError(str(task.SourcePath)) + + if not task.DestinationPath.parent.exists(): + if self.DryRun: + self.LogDryRun("mkdir '{0!s}'.".format(task.DestinationPath.parent)) + else: + try: + task.DestinationPath.parent.mkdir(parents=True) + except OSError as ex: + raise CompilerException("Error while creating '{0!s}'.".format(task.DestinationPath.parent)) from ex + + self.LogDebug("{0}-copying '{1!s}'.".format(text, task.SourcePath)) + if self.DryRun: + self.LogDryRun("Copy '{0!s}' to '{1!s}'.".format(task.SourcePath, task.DestinationPath)) + else: + try: + shutil_copy(str(task.SourcePath), str(task.DestinationPath)) + except OSError as ex: + raise CompilerException("Error while copying '{0!s}'.".format(task.SourcePath)) from ex + + def _RunPostDelete(self, netlist): + self.LogVerbose("copy generated files into netlist directory...") + rulesFiles = [file for file in self.PoCProject.Files(fileType=FileTypes.RulesFile)] # FIXME: get rulefile from netlist object as a rulefile object instead of a path + postDeleteTasks = [] + if (rulesFiles): + for rule in rulesFiles[0].PostProcessRules: + if isinstance(rule, DeleteRuleMixIn): + filePath = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.FilePath, {}) + task = DeleteTask(Path(filePath)) + postDeleteTasks.append(task) + else: + postDeleteRules = self.Host.PoCConfig[netlist.ConfigSectionName]['PostDeleteRules'] + self._ParseDeleteRules(postDeleteRules, postDeleteTasks, "post") + + if self.NoCleanUp: + self.LogWarning("Disabled cleanup. Skipping post-delete rules.") + elif (len(postDeleteTasks) != 0): + self._ExecuteDeleteTasks(postDeleteTasks, "post") + else: + self.LogDebug("Nothing to delete") + + def _ParseDeleteRules(self, rawList, deleteTasks, text): + # read delete tasks + if (len(rawList) != 0): + self.LogDebug("Parse {0}-delete tasks from config file:".format(text)) + rawList = rawList.split("\n") + + deleteRegExpStr = r"^\s*(?P.*?)$" # filename + deleteRegExp = re_compile(deleteRegExpStr) + + for item in rawList: + deleteRegExpMatch = deleteRegExp.match(item) + if (deleteRegExpMatch is None): + raise CompilerException("Error in delete rule '{0}'.".format(item)) + + task = DeleteTask(Path(deleteRegExpMatch.group('Filename'))) + deleteTasks.append(task) + self.LogDebug(" {0!s}".format(task)) + else: + self.LogDebug("No {0}-delete tasks specified in config file.".format(text)) + + def _ExecuteDeleteTasks(self, tasks, text): + for task in tasks: + if (not self.DryRun and not task.FilePath.exists()): + raise CompilerException("Cannot {0}-delete '{1!s}'.".format(text, task.FilePath)) from FileNotFoundError(str(task.FilePath)) + + self.LogDebug("{0}-deleting '{1!s}'.".format(text, task.FilePath)) + if self.DryRun: + self.LogDryRun("Delete '{0!s}'.".format(task.FilePath)) + else: + try: + task.FilePath.unlink() + except OSError as ex: + raise CompilerException("Error while deleting '{0!s}'.".format(task.FilePath)) from ex + + def _RunPreReplace(self, netlist): + self.LogVerbose("Patching files in temporary directory...") + rulesFiles = [file for file in self.PoCProject.Files(fileType=FileTypes.RulesFile)] # FIXME: get rulefile from netlist object as a rulefile object instead of a path + preReplaceTasks = [] + if (rulesFiles): + for rule in rulesFiles[0].PreProcessRules: + if isinstance(rule, ReplaceRuleMixIn): + filePath = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.FilePath, {}) + searchPattern = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.SearchPattern, {}) + replacePattern = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.ReplacePattern, {}) + task = ReplaceTask(Path(filePath), searchPattern, replacePattern, rule.RegExpOption_MultiLine, rule.RegExpOption_DotAll, rule.RegExpOption_CaseInsensitive) + preReplaceTasks.append(task) + elif isinstance(rule, AppendLineRuleMixIn): + filePath = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.FilePath, {}) + appendPattern = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.AppendPattern, {}) + task = AppendLineTask(Path(filePath), appendPattern) + preReplaceTasks.append(task) + elif isinstance(rule, CopyRuleMixIn): + pass + else: + raise CompilerException("Unknown pre-process rule '{0!s}'.".format(rule)) + else: + preReplaceRules = self.Host.PoCConfig[netlist.ConfigSectionName]['PreReplaceRules'] + self._ParseReplaceRules(preReplaceRules, preReplaceTasks, "pre") + + if (len(preReplaceTasks) != 0): + self._ExecuteReplaceTasks(preReplaceTasks, "pre") + else: + self.LogDebug("Nothing to patch.") + + def _RunPostReplace(self, netlist): + self.LogVerbose("Patching files in netlist directory...") + rulesFiles = [file for file in self.PoCProject.Files(fileType=FileTypes.RulesFile)] # FIXME: get rulefile from netlist object as a rulefile object instead of a path + postReplaceTasks = [] + if (rulesFiles): + for rule in rulesFiles[0].PostProcessRules: + if isinstance(rule, ReplaceRuleMixIn): + filePath = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.FilePath, {}) + searchPattern = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.SearchPattern, {}) + replacePattern = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.ReplacePattern, {}) + task = ReplaceTask(Path(filePath), searchPattern, replacePattern, rule.RegExpOption_MultiLine, rule.RegExpOption_DotAll, rule.RegExpOption_CaseInsensitive) + postReplaceTasks.append(task) + elif isinstance(rule, AppendLineRuleMixIn): + filePath = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.FilePath, {}) + appendPattern = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.AppendPattern, {}) + task = AppendLineTask(Path(filePath), appendPattern) + postReplaceTasks.append(task) + elif isinstance(rule, (CopyRuleMixIn, DeleteRuleMixIn)): + pass + else: + raise CompilerException("Unknown post-process rule '{0!s}'.".format(rule)) + else: + postReplaceRules = self.Host.PoCConfig[netlist.ConfigSectionName]['PostReplaceRules'] + self._ParseReplaceRules(postReplaceRules, postReplaceTasks, "post") + + if (len(postReplaceTasks) != 0): + self._ExecuteReplaceTasks(postReplaceTasks, "post") + else: + self.LogDebug("Nothing to patch.") + + def _ParseReplaceRules(self, rawList, replaceTasks, text): + # read replace tasks + if (len(rawList) != 0): + self.LogDebug("Parsing {0}-replacement tasks:".format(text)) + rawList = rawList.split("\n") + + # FIXME: Rework inline replace rule syntax. + replaceRegExpStr = r"^\s*(?P.*?)\s+:" # Filename + replaceRegExpStr += r"(?P[dim]{0,3}):\s+" # RegExp options + replaceRegExpStr += r"\"(?P.*?)\"\s+->\s+" # Search regexp + replaceRegExpStr += r"\"(?P.*?)\"$" # Replace regexp + replaceRegExp = re_compile(replaceRegExpStr) + + for item in rawList: + replaceRegExpMatch = replaceRegExp.match(item) + + if (replaceRegExpMatch is None): + raise CompilerException("Error in replace rule '{0}'.".format(item)) + + task = ReplaceTask( + Path(replaceRegExpMatch.group('Filename')), + replaceRegExpMatch.group('Search'), + replaceRegExpMatch.group('Replace'), + # replaceRegExpMatch.group('Options'), # FIXME: + # replaceRegExpMatch.group('Options'), # FIXME: + # replaceRegExpMatch.group('Options'), # FIXME: + False, False, False + ) + replaceTasks.append(task) + self.LogDebug(" {0!s}".format(task)) + else: + self.LogDebug("No {0}-replace tasks specified in config file.".format(text)) + + def _ExecuteReplaceTasks(self, tasks, text): + for task in tasks: + if (not self.DryRun and not task.FilePath.exists()): + raise CompilerException("Cannot {0}-replace in file '{1!s}'.".format(text, task.FilePath)) from FileNotFoundError(str(task.FilePath)) + self.LogDebug("{0}-replace in file '{1!s}': search for '{2}' replace by '{3}'.".format(text, task.FilePath, task.SearchPattern, task.ReplacePattern)) + + if self.DryRun: + self.LogDryRun("Patch '{0!s}'.".format(task.FilePath)) + else: + regExpFlags = 0 + if task.RegExpOption_CaseInsensitive: regExpFlags |= RE_IGNORECASE + if task.RegExpOption_MultiLine: regExpFlags |= RE_MULTILINE + if task.RegExpOption_DotAll: regExpFlags |= RE_DOTALL + + # compile regexp + regExp = re_compile(task.SearchPattern, regExpFlags) + # open file and read all lines + with task.FilePath.open('r') as fileHandle: + FileContent = fileHandle.read() + # replace + NewContent,replaceCount = re_subn(regExp, task.ReplacePattern, FileContent) + if (replaceCount == 0): + self.LogWarning(" Search pattern '{0}' not found in file '{1!s}'.".format(task.SearchPattern, task.FilePath)) + # open file to write the replaced data + with task.FilePath.open('w') as fileHandle: + fileHandle.write(NewContent) + + def PrintOverallCompileReport(self): + self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) + self.LogQuiet("{HEADLINE}{headline: ^80s}{NOCOLOR}".format(headline="Overall Compile Report", **Init.Foreground)) + self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) + # table header + self.LogQuiet("{Name: <24} | {Duration: >5} | {Status: ^11}".format(Name="Name", Duration="Time", Status="Status")) + self.LogQuiet("-" * 80) + self.PrintCompileReportLine(self._testSuite, 0, 24) + + self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) + self.LogQuiet("Time: {time: >5} Count: {count: <3} Success: {success: <3} Failed: {failed: <2} Errors: {error: <2}".format( + time=to_time(self._testSuite.OverallRunTime), + count=self._testSuite.Count, + success=self._testSuite.SuccessCount, + failed=self._testSuite.FailedCount, + error=self._testSuite.ErrorCount + )) + self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) + + __COMPILE_REPORT_COLOR_TABLE__ = { + CompileStatus.Unknown: "RED", + CompileStatus.InternalError: "DARK_RED", + CompileStatus.SystemError: "DARK_RED", + CompileStatus.CompileError: "RED", + CompileStatus.CompileSuccess: "GREEN" + } + + __COMPILE_REPORT_STATUS_TEXT_TABLE__ = { + CompileStatus.Unknown: "-- ?? --", + CompileStatus.InternalError: "INT. ERROR", + CompileStatus.SystemError: "SYS. ERROR", + CompileStatus.CompileError: "COMP. ERROR", + CompileStatus.CompileSuccess: "SUCCESS" + } + + def PrintCompileReportLine(self, testObject, indent, nameColumnWidth): + _indent = " " * indent + for group in testObject.Groups.values(): + pattern = "{indent}{{groupName: <{nameColumnWidth}}} | | ".format(indent=_indent, nameColumnWidth=nameColumnWidth) + self.LogQuiet(pattern.format(groupName=group.Name)) + self.PrintCompileReportLine(group, indent + 1, nameColumnWidth - 2) + for synthesis in testObject.Synthesises.values(): + pattern = "{indent}{{netlistName: <{nameColumnWidth}}} | {{duration: >5}} | {{{color}}}{{status: ^11}}{{NOCOLOR}}".format( + indent=_indent, nameColumnWidth=nameColumnWidth, color=self.__COMPILE_REPORT_COLOR_TABLE__[synthesis.Status]) + self.LogQuiet(pattern.format( + netlistName=synthesis.Name, + duration=to_time(synthesis.OverallRunTime), + status=self.__COMPILE_REPORT_STATUS_TEXT_TABLE__[synthesis.Status], **Init.Foreground + )) diff --git a/py/DataBase/Config.py b/py/DataBase/Config.py index 511326ce..0859866c 100644 --- a/py/DataBase/Config.py +++ b/py/DataBase/Config.py @@ -6,11 +6,7 @@ # Authors: Patrick Lehmann # Martin Zabel # -# Python Class: TODO -# -# Description: -# ------------------------------------ -# TODO: +# Python Class: TODO # # License: # ============================================================================== @@ -34,15 +30,15 @@ from enum import Enum, unique from re import compile as re_compile -from Base.Configuration import ConfigurationException +from ToolChains import ConfigurationException __api__ = [ 'BaseEnum', 'Vendors', - 'Families', 'GenericFamilies', 'XilinxFamilies', 'AlteraFamilies', 'LatticeFamilies', - 'Devices', - 'SubTypes', + 'Families', 'GenericFamilies', 'AlteraFamilies', 'LatticeFamilies', 'XilinxFamilies', + 'Devices', 'GenericDevices', 'AlteraDevices', 'LatticeDevices', 'XilinxDevices', + 'SubTypes', 'GenericSubTypes', 'AlteraSubTypes', 'LatticeSubTypes', 'XilinxSubTypes', 'Packages', 'Device', 'Board' @@ -75,19 +71,32 @@ def __repr__(self): class Families(BaseEnum): + """Base enum for all Family enums.""" + # @CachedReadOnlyProperty @property def Token(self): return self.value - class GenericFamilies(Families): + """Enumeration of all generic families.""" Unknown = None Generic = "g" +class AlteraFamilies(Families): + """Enumeration of all Altera families.""" + Max = "m" + Cyclone = "c" + Arria = "a" + Stratix = "s" + +class LatticeFamilies(Families): + """Enumeration of all Lattice families.""" + ECP = "lfe" + # TODO: MachXO, iCE, ... class XilinxFamilies(Families): - # Xilinx families + """Enumeration of all Xilinx families.""" Spartan = "s" Artix = "a" Kintex = "k" @@ -95,29 +104,21 @@ class XilinxFamilies(Families): Zynq = "z" -class AlteraFamilies(Families): - # Altera families - Max = "m" - Cyclone = "c" - Arria = "a" - Stratix = "s" - -class LatticeFamilies(Families): - # lattice families - ECP = "lfe" - # FIXME: MachXO, iCE, ... - - -@unique class Devices(BaseEnum): - Unknown = 0 - Generic = 1 + """Base enum for all Device enums.""" + +class GenericDevices(Devices): + """Enumeration of all generic devices.""" + Unknown = 0 + Generic = 1 +class AlteraDevices(Devices): + """Enumeration of all Altera devices.""" # Altera.Max devices Max2 = 100 Max4 = 101 Max5 = 102 - Max10 = 103 + Max10 = 103 # Altera.Cyclone devices Cyclone3 = 110 Cyclone4 = 111 @@ -129,19 +130,23 @@ class Devices(BaseEnum): Stratix2 = 130 Stratix4 = 131 Stratix5 = 132 - Stratix10 = 133 + Stratix10 = 133 +class LatticeDevices(Devices): + """Enumeration of all Lattice devices.""" # Lattice.iCE device - iCE40 = 200 + iCE40 = 200 # Lattice.MachXO MachXO = 210 - MachXO2 = 211 - MachXO3 = 212 + MachXO2 = 211 + MachXO3 = 212 # Lattice.ECP ECP2 = 220 ECP3 = 221 ECP5 = 222 +class XilinxDevices(Devices): + """Enumeration of all Xilinx devices.""" # Xilinx.Spartan devices Spartan3 = 310 Spartan6 = 311 @@ -149,15 +154,15 @@ class Devices(BaseEnum): # Xilinx.Artix devices Artix7 = 320 # Xilinx.Kintex devices - Kintex7 = 330 + Kintex7 = 330 KintexUltraScale = 331 KintexUltraScalePlus = 332 # Xilinx.Virtex devices - Virtex2 = 340 - Virtex4 = 341 - Virtex5 = 342 - Virtex6 = 343 - Virtex7 = 344 + Virtex2 = 340 + Virtex4 = 341 + Virtex5 = 342 + Virtex6 = 343 + Virtex7 = 344 VirtexUltraScale = 345 VirtexUltraScalePlus = 346 # Xilinx.Zynq devices @@ -165,45 +170,61 @@ class Devices(BaseEnum): class SubTypes(BaseEnum): - Unknown = None - Generic = 1 + """Base enum for all SubType enums.""" + + # @CachedReadOnlyProperty + @property + def Groups(self): + return self.value + +class GenericSubTypes(SubTypes): + """Enumeration of all generic device subtype.""" + Unknown = None + Generic = 1 NoSubType = ("", "") - # Altera device subtypes + +class AlteraSubTypes(SubTypes): + """Enumeration of all Altera device subtype.""" + NoSubType = ("", "") + LS = ("ls", "") - E = ("e", "") + E = ("e", "") GS = ("gs", "") GX = ("gx", "") GT = ("gt", "") GZ = ("gz", "") SX = ("sx", "") ST = ("st", "") - # lAttice device subtypes - U = ("u", "") + +class LatticeSubTypes(SubTypes): + """Enumeration of all Lattice device subtype.""" + NoSubType = ("", "") + + U = ("u", "") UM = ("um", "") - # Xilinx device subtypes - X = ("x", "") - T = ("", "t") + +class XilinxSubTypes(SubTypes): + """Enumeration of all Xilinx device subtype.""" + DA = ("d", "a") + E = ("", "e") + AN = ("", "an") + X = ("x", "") + T = ("", "t") XT = ("x", "t") HT = ("h", "t") LX = ("lx", "") - SXT = ("sx", "t") - LXT = ("lx", "t") - TXT = ("tx", "t") - FXT = ("fx", "t") - CXT = ("cx", "t") - HXT = ("hx", "t") - - - # @CachedReadOnlyProperty - @property - def Groups(self): - return self.value + SXT = ("sx", "t") + LXT = ("lx", "t") + TXT = ("tx", "t") + FXT = ("fx", "t") + CXT = ("cx", "t") + HXT = ("hx", "t") @unique class Packages(BaseEnum): - Unknown = 0 - Generic = 1 + Unknown = 0 + Generic = 1 TQG = 10 @@ -216,10 +237,11 @@ class Packages(BaseEnum): FBG = 30 FF = 31 FFG = 32 - FGG = 33 - FLG = 34 - FT = 35 - FTG = 36 + FG = 33 + FGG = 34 + FLG = 35 + FT = 36 + FTG = 37 RB = 40 RBG = 41 @@ -238,9 +260,9 @@ def __init__(self, deviceString): # Device members self.__vendor = Vendors.Unknown self.__family = GenericFamilies.Unknown - self.__device = Devices.Unknown + self.__device = GenericDevices.Unknown self.__generation = 0 - self.__subtype = SubTypes.Unknown + self.__subtype = GenericSubTypes.Unknown self.__number = 0 self.__speedGrade = 0 self.__package = Packages.Unknown @@ -265,7 +287,8 @@ def __init__(self, deviceString): def _DecodeGeneric(self): self.__vendor = Vendors.Generic self.__family = GenericFamilies.Generic - self.__subtype = SubTypes.Generic + self.__device = GenericDevices.Generic + self.__subtype = GenericSubTypes.Generic self.__package = Packages.Generic def _DecodeAltera(self, deviceString): @@ -292,10 +315,10 @@ def _DecodeAltera(self, deviceString): if (subtype != ""): d = {"g": "gx", "x": "sx", "t": "gt"} # re-name for Stratix 10 and Arria 10 if subtype in d: subtype = d[subtype] - try: self.__subtype = SubTypes[subtype.upper()] + try: self.__subtype = AlteraSubTypes[subtype.upper()] except KeyError as ex: raise ConfigurationException("Unknown subtype '{0}'.".format(subtype)) from ex else: - self.__subtype = SubTypes.NoSubType + self.__subtype = AlteraSubTypes.NoSubType else: raise ConfigurationException("RegExp mismatch.") @@ -316,29 +339,30 @@ def _DecodeLatticeLFE(self, deviceString): else: raise ConfigurationException("Unknown Lattice ECP generation.") def _DecodeLatticeECP3(self, deviceString): - self.__subtype = SubTypes.NoSubType + self.__device = LatticeDevices.ECP3 + self.__subtype = LatticeSubTypes.NoSubType self.__number = int(deviceString[5:8]) def _DecodeLatticeECP5(self, deviceString): - self.__device = Devices.ECP5 + self.__device = LatticeDevices.ECP5 familyToken = deviceString[4:6].lower() if (familyToken == "u-"): - self.__subtype = SubTypes.U + self.__subtype = LatticeSubTypes.U self.__number = int(deviceString[6:8]) self.__speedGrade = int(deviceString[10:11]) self.__package = Packages.CABGA - self.__pinCount = 381 # XXX: implement other packages and pin counts + self.__pinCount = 381 # TODO: implement other packages and pin counts elif (familyToken == "um"): - self.__subtype = SubTypes.UM + self.__subtype = LatticeSubTypes.UM self.__number = int(deviceString[7:9]) self.__speedGrade = int(deviceString[11:12]) self.__package = Packages.CABGA - self.__pinCount = 381 # XXX: implement other packages and pin counts + self.__pinCount = 381 # TODO: implement other packages and pin counts else: raise ConfigurationException("Unknown Lattice ECP5 subtype.") def _DecodeXilinx(self, deviceString): - self.__vendor = Vendors.Xilinx + self.__vendor = Vendors.Xilinx self.__generation = int(deviceString[2:3]) familyToken = deviceString[3:4].lower() @@ -351,7 +375,7 @@ def _DecodeXilinx(self, deviceString): deviceRegExpStr = r"(?P[a-z]{0,2})" # device subtype - part 1 deviceRegExpStr += r"(?P\d{1,4})" # device number - deviceRegExpStr += r"(?P[t]{0,1})" # device subtype - part 2 + deviceRegExpStr += r"(?P[aent]{0,2})" # device subtype - part 2 deviceRegExpStr += r"(?P[-1-5]{2})" # speed grade deviceRegExpStr += r"(?P[a-z]{1,3})" # package deviceRegExpStr += r"(?P\d{1,4})" # pin count @@ -363,9 +387,9 @@ def _DecodeXilinx(self, deviceString): package = deviceRegExpMatch.group('pack') if (subtype != ""): - try: self.__subtype = SubTypes[subtype.upper()] + try: self.__subtype = XilinxSubTypes[subtype.upper()] except KeyError as ex: raise ConfigurationException("Unknown subtype '{0}'.".format(subtype)) from ex - else: self.__subtype = SubTypes.NoSubType + else: self.__subtype = XilinxSubTypes.NoSubType self.__number = int(deviceRegExpMatch.group('no')) self.__speedGrade = int(deviceRegExpMatch.group('sg')) try: self.__package = Packages[package.upper()] diff --git a/py/DataBase/Entity.py b/py/DataBase/Entity.py index 000e3212..e2e49cd2 100644 --- a/py/DataBase/Entity.py +++ b/py/DataBase/Entity.py @@ -5,13 +5,7 @@ # ============================================================================== # Authors: Patrick Lehmann # -# Python Class: TODO -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Class: TODO # # License: # ============================================================================== @@ -39,7 +33,7 @@ from lib.Functions import Init from lib.Decorators import LazyLoadTrigger, ILazyLoadable -from Base.Configuration import ConfigurationException +from ToolChains import ConfigurationException __api__ = [ diff --git a/py/DataBase/Query.py b/py/DataBase/Query.py deleted file mode 100644 index 7ba8a340..00000000 --- a/py/DataBase/Query.py +++ /dev/null @@ -1,119 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# -# ============================================================================== -# Authors: Patrick Lehmann -# -# Python Class: TODO -# -# Description: -# ------------------------------------ -# TODO: -# -# License: -# ============================================================================== -# Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair of VLSI-Design, Diagnostics and Architecture -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# ============================================================================== -# -# -# load dependencies -from pathlib import Path - -from Base.Exceptions import NotConfiguredException, PlatformNotSupportedException -from Base.Configuration import ConfigurationException - - -__api__ = [ - 'Query' -] -__all__ = __api__ - - -class Query: - def __init__(self, host): - self.__host = host - - @property - def Host(self): return self.__host - @property - def Platform(self): return self.__host.Platform - @property - def PoCConfig(self): return self.__host.PoCConfig - - def QueryConfiguration(self, query): - if (query == "ModelSim:InstallationDirectory"): - result = self._GetModelSimInstallationDirectory() - elif (query == "ModelSim:BinaryDirectory"): - result = self._GetModelSimBinaryDirectory() - elif (query == "Xilinx.ISE:SettingsFile"): - result = self._GetXilinxISESettingsFile() - elif (query == "Xilinx.Vivado:SettingsFile"): - result = self._GetXilinxVivadoSettingsFile() - else: - parts = query.split(":") - if (len(parts) == 2): - sectionName = parts[0] - optionName = parts[1] - try: - result = self.PoCConfig[sectionName][optionName] - except KeyError as ex: - raise ConfigurationException("Requested setting '{0}:{1}' not found.".format(sectionName, optionName)) from ex - else: - raise ConfigurationException("Syntax error in query string '{0}'".format(query)) - - if isinstance(result, Path): result = str(result) - return result - - def _GetModelSimInstallationDirectory(self): - if (len(self.PoCConfig.options('INSTALL.Mentor.QuestaSim')) != 0): - return Path(self.PoCConfig['INSTALL.Mentor.QuestaSim']['InstallationDirectory']) - elif (len(self.PoCConfig.options('INSTALL.Altera.ModelSim')) != 0): - return Path(self.PoCConfig['INSTALL.Altera.ModelSim']['InstallationDirectory']) - else: - raise NotConfiguredException("ERROR: ModelSim is not configured on this system.") - - def _GetModelSimBinaryDirectory(self): - if (len(self.PoCConfig.options('INSTALL.Mentor.QuestaSim')) != 0): - return Path(self.PoCConfig['INSTALL.Mentor.QuestaSim']['BinaryDirectory']) - elif (len(self.PoCConfig.options('INSTALL.Altera.ModelSim')) != 0): - return Path(self.PoCConfig['INSTALL.Altera.ModelSim']['BinaryDirectory']) - else: - raise NotConfiguredException("ERROR: ModelSim is not configured on this system.") - - def _GetXilinxISESettingsFile(self): - if (len(self.PoCConfig.options('INSTALL.Xilinx.ISE')) != 0): - iseInstallationDirectoryPath = Path(self.PoCConfig['INSTALL.Xilinx.ISE']['InstallationDirectory']) - if (self.Platform == "Windows"): - return iseInstallationDirectoryPath / "settings64.bat" - elif (self.Platform == "Linux"): - return iseInstallationDirectoryPath / "settings64.sh" - else: - raise PlatformNotSupportedException(self.Platform) - else: - raise NotConfiguredException("ERROR: Xilinx ISE is not configured on this system.") - - def _GetXilinxVivadoSettingsFile(self): - if (len(self.PoCConfig.options('INSTALL.Xilinx.Vivado')) != 0): - iseInstallationDirectoryPath = Path(self.PoCConfig['INSTALL.Xilinx.Vivado']['InstallationDirectory']) - if (self.Platform == "Windows"): - return iseInstallationDirectoryPath / "settings64.bat" - elif (self.Platform == "Linux"): - return iseInstallationDirectoryPath / "settings64.sh" - else: - raise PlatformNotSupportedException(self.Platform) - else: - raise NotConfiguredException("ERROR: Xilinx ISE is not configured on this system.") diff --git a/py/DataBase/Solution.py b/py/DataBase/Solution.py index a713da1b..3990c79e 100644 --- a/py/DataBase/Solution.py +++ b/py/DataBase/Solution.py @@ -7,12 +7,6 @@ # # Python Class: TODO # -# Description: -# ------------------------------------ -# TODO: -# - -# - -# # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany @@ -37,12 +31,12 @@ from lib.Decorators import ILazyLoadable, LazyLoadTrigger from Base.Exceptions import CommonException -from Base.Configuration import ConfigurationException from Base.Project import Project as BaseProject, File, FileTypes, VHDLSourceFile, VerilogSourceFile, CocotbSourceFile #, ProjectFile from Parser.FilesParser import FilesParserMixIn from Parser.RulesParser import RulesParserMixIn from DataBase import __POC_SOLUTION_KEYWORD__ from DataBase.Entity import Visibility +from ToolChains import ConfigurationException __api__ = [ diff --git a/py/DataBase/TestCase.py b/py/DataBase/TestCase.py index a10c53bd..dc90fd85 100644 --- a/py/DataBase/TestCase.py +++ b/py/DataBase/TestCase.py @@ -7,10 +7,6 @@ # # Python Class: TODO # -# Description: -# ------------------------------------ -# TODO: -# # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany diff --git a/py/DataBase/__init__.py b/py/DataBase/__init__.py index b7f7c9a5..c9691698 100644 --- a/py/DataBase/__init__.py +++ b/py/DataBase/__init__.py @@ -7,11 +7,6 @@ # # Python Sub Module: Saves The PoC-Library configuration as python source code. # -# Description: -# ------------------------------------ -# TODO: -# -# # License: # ============================================================================== # Copyright 2007-2015 Technische Universitaet Dresden - Germany @@ -29,17 +24,97 @@ # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================== +# +# load dependencies +from pathlib import Path -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Repository Service Tool") +from Base.Exceptions import NotConfiguredException, PlatformNotSupportedException +from ToolChains import ConfigurationException -# load dependencies + +__api__ = [ + 'Query', + '__POC_SOLUTION_KEYWORD__', + '__POC_PROJECT_KEYWORD__' +] +__all__ = __api__ __POC_SOLUTION_KEYWORD__ = "Solution" -__POC_PROJECT_KEYWORD__ = "Project" +__POC_PROJECT_KEYWORD__ = "Project" + + +class Query: + def __init__(self, host): + self.__host = host + + @property + def Host(self): return self.__host + @property + def Platform(self): return self.__host.Platform + @property + def PoCConfig(self): return self.__host.PoCConfig + + def QueryConfiguration(self, query): + if (query == "ModelSim:InstallationDirectory"): + result = self._GetModelSimInstallationDirectory() + elif (query == "ModelSim:BinaryDirectory"): + result = self._GetModelSimBinaryDirectory() + elif (query == "Xilinx.ISE:SettingsFile"): + result = self._GetXilinxISESettingsFile() + elif (query == "Xilinx.Vivado:SettingsFile"): + result = self._GetXilinxVivadoSettingsFile() + else: + parts = query.split(":") + if (len(parts) == 2): + sectionName = parts[0] + optionName = parts[1] + try: + result = self.PoCConfig[sectionName][optionName] + except KeyError as ex: + raise ConfigurationException("Requested setting '{0}:{1}' not found.".format(sectionName, optionName)) from ex + else: + raise ConfigurationException("Syntax error in query string '{0}'".format(query)) + + if isinstance(result, Path): result = str(result) + return result + + def _GetModelSimInstallationDirectory(self): + if (len(self.PoCConfig.options('INSTALL.Mentor.QuestaSim')) != 0): + return Path(self.PoCConfig['INSTALL.Mentor.QuestaSim']['InstallationDirectory']) + elif (len(self.PoCConfig.options('INSTALL.Altera.ModelSim')) != 0): + return Path(self.PoCConfig['INSTALL.Altera.ModelSim']['InstallationDirectory']) + else: + raise NotConfiguredException("ERROR: ModelSim is not configured on this system.") + + def _GetModelSimBinaryDirectory(self): + if (len(self.PoCConfig.options('INSTALL.Mentor.QuestaSim')) != 0): + return Path(self.PoCConfig['INSTALL.Mentor.QuestaSim']['BinaryDirectory']) + elif (len(self.PoCConfig.options('INSTALL.Altera.ModelSim')) != 0): + return Path(self.PoCConfig['INSTALL.Altera.ModelSim']['BinaryDirectory']) + else: + raise NotConfiguredException("ERROR: ModelSim is not configured on this system.") + + def _GetXilinxISESettingsFile(self): + if (len(self.PoCConfig.options('INSTALL.Xilinx.ISE')) != 0): + iseInstallationDirectoryPath = Path(self.PoCConfig['INSTALL.Xilinx.ISE']['InstallationDirectory']) + if (self.Platform == "Windows"): + return iseInstallationDirectoryPath / "settings64.bat" + elif (self.Platform == "Linux"): + return iseInstallationDirectoryPath / "settings64.sh" + else: + raise PlatformNotSupportedException(self.Platform) + else: + raise NotConfiguredException("ERROR: Xilinx ISE is not configured on this system.") + + def _GetXilinxVivadoSettingsFile(self): + if (len(self.PoCConfig.options('INSTALL.Xilinx.Vivado')) != 0): + iseInstallationDirectoryPath = Path(self.PoCConfig['INSTALL.Xilinx.Vivado']['InstallationDirectory']) + if (self.Platform == "Windows"): + return iseInstallationDirectoryPath / "settings64.bat" + elif (self.Platform == "Linux"): + return iseInstallationDirectoryPath / "settings64.sh" + else: + raise PlatformNotSupportedException(self.Platform) + else: + raise NotConfiguredException("ERROR: Xilinx ISE is not configured on this system.") diff --git a/py/Parser/FilesCodeDOM.py b/py/Parser/FilesCodeDOM.py index 5a032387..5d4d41bc 100644 --- a/py/Parser/FilesCodeDOM.py +++ b/py/Parser/FilesCodeDOM.py @@ -8,10 +8,6 @@ # # Python Module: TODO # -# Description: -# ------------------------------------ -# TODO: -# # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany @@ -596,7 +592,7 @@ def GetParser(cls): token = yield if isinstance(token, CharacterToken): if (token.Value == ":"): - if (foundDelimiter == False): + if (foundDelimiter is False): foundDelimiter = True else: raise MismatchingParserResult("InterpolateLiteralParser: ") @@ -611,7 +607,7 @@ def GetParser(cls): else: raise MismatchingParserResult("InterpolateLiteralParser: ") - if (foundDelimiter == True): + if (foundDelimiter is True): sectionName = value[False] optionName = value[True] else: diff --git a/py/Parser/FilesParser.py b/py/Parser/FilesParser.py index 97d4f789..29161f6b 100644 --- a/py/Parser/FilesParser.py +++ b/py/Parser/FilesParser.py @@ -8,10 +8,6 @@ # # Python Module: TODO # -# Description: -# ------------------------------------ -# TODO: -# # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany @@ -170,7 +166,7 @@ def _Parse(self): print("{DARK_GRAY}{doc!s}{NOCOLOR}".format(doc=self._document, **Init.Foreground)) print("{DARK_GRAY}{line}{NOCOLOR}".format(line="*"*80, **Init.Foreground)) - # FIXME: is there a better way to passthrough/access host? + # QUESTION: Is there a better way to passthrough/access host? def _Resolve(self, host, statements=None): # mccabe:disable=MC0001 if (statements is None): statements = self._document.Statements diff --git a/py/Parser/RulesCodeDOM.py b/py/Parser/RulesCodeDOM.py index afdd14e8..f7ceb149 100644 --- a/py/Parser/RulesCodeDOM.py +++ b/py/Parser/RulesCodeDOM.py @@ -7,10 +7,6 @@ # # Python Module: TODO # -# Description: -# ------------------------------------ -# TODO: -# # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany diff --git a/py/Parser/RulesParser.py b/py/Parser/RulesParser.py index 557513ec..201d2555 100644 --- a/py/Parser/RulesParser.py +++ b/py/Parser/RulesParser.py @@ -7,10 +7,6 @@ # # Python Module: TODO # -# Description: -# ------------------------------------ -# TODO: -# # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany diff --git a/py/Parser/__init__.py b/py/Parser/__init__.py index 8a2a1fb4..2884a022 100644 --- a/py/Parser/__init__.py +++ b/py/Parser/__init__.py @@ -7,11 +7,6 @@ # # Python Sub Module: TODO: # -# Description: -# ------------------------------------ -# TODO: -# -# # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany @@ -30,12 +25,4 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Repository Service Tool") - # load dependencies diff --git a/py/PoC.py b/py/PoC.py index 39fe3b26..4ec7bd85 100644 --- a/py/PoC.py +++ b/py/PoC.py @@ -34,40 +34,38 @@ # ============================================================================== # # load dependencies -from argparse import RawDescriptionHelpFormatter -from collections import OrderedDict -from configparser import Error as ConfigParser_Error, DuplicateOptionError -from os import environ -from pathlib import Path -from platform import system as platform_system -from sys import argv as sys_argv -from textwrap import dedent - -from Base.Compiler import CompilerException -from Base.Configuration import ConfigurationException, SkipConfigurationException -from Base.Exceptions import ExceptionBase, CommonException, PlatformNotSupportedException, EnvironmentException, NotConfiguredException -from Base.Logging import ILogable, Logger, Severity -from Base.Project import VHDLVersion -from Base.Simulator import SimulatorException, Simulator as BaseSimulator, SimulationSteps -from Base.ToolChain import ToolChainException -from Compiler.LSECompiler import Compiler as LSECompiler -from Compiler.QuartusCompiler import Compiler as MapCompiler -from Compiler.ISECompiler import Compiler as ISECompiler -from Compiler.XCICompiler import Compiler as XCICompiler -from Compiler.XCOCompiler import Compiler as XCOCompiler -from Compiler.XSTCompiler import Compiler as XSTCompiler -from Compiler.VivadoCompiler import Compiler as VivadoCompiler +from argparse import RawDescriptionHelpFormatter +from configparser import Error as ConfigParser_Error, DuplicateOptionError +from os import environ +from pathlib import Path +from platform import system as platform_system +from sys import argv as sys_argv +from textwrap import dedent + +from Compiler import CompilerException, CompileSteps +from Base.Exceptions import ExceptionBase, CommonException, PlatformNotSupportedException, EnvironmentException, NotConfiguredException +from Base.Logging import ILogable, Logger, Severity +from Base.Project import VHDLVersion +from Simulator import SimulatorException, SimulationSteps, Simulator +from Compiler.LSECompiler import Compiler as LSECompiler +from Compiler.QuartusCompiler import Compiler as MapCompiler +from Compiler.ISECompiler import Compiler as ISECompiler +from Compiler.XCICompiler import Compiler as XCICompiler +from Compiler.XCOCompiler import Compiler as XCOCompiler +from Compiler.XSTCompiler import Compiler as XSTCompiler +from Compiler.VivadoCompiler import Compiler as VivadoCompiler +from DataBase import Query from DataBase.Config import Board from DataBase.Entity import NamespaceRoot, FQN, EntityTypes, WildCard, TestbenchKind, NetlistKind from DataBase.Solution import Repository -from DataBase.Query import Query +from Simulator import Simulator as BaseSimulator from Simulator.ActiveHDLSimulator import Simulator as ActiveHDLSimulator from Simulator.CocotbSimulator import Simulator as CocotbSimulator from Simulator.GHDLSimulator import Simulator as GHDLSimulator from Simulator.ISESimulator import Simulator as ISESimulator from Simulator.QuestaSimulator import Simulator as QuestaSimulator from Simulator.VivadoSimulator import Simulator as VivadoSimulator -from ToolChains import Configurations +from ToolChains import ToolChainException, Configurator, ConfigurationException from ToolChains.GHDL import Configuration as GHDLConfiguration from lib.pyAttribute.ArgParseAttributes import ArgParseMixin from lib.pyAttribute.ArgParseAttributes import CommandAttribute, CommandGroupAttribute, ArgumentAttribute, SwitchArgumentAttribute, DefaultAttribute @@ -132,7 +130,7 @@ def __call__(self, func): class CompileStepsAttribute(Attribute): def __call__(self, func): - # synthesize + self._AppendAttribute(func, SwitchArgumentAttribute("-s", "--synthesize", dest="Synthesize", help="Run only the prepare and synthesize step.")) # merge # place # route @@ -187,7 +185,7 @@ def __init__(self, debug, verbose, quiet, dryRun, sphinx=False): elif verbose: severity = Severity.Verbose else: severity = Severity.Normal - logger = Logger(self, severity, printToStdOut=True) + logger = Logger(severity, printToStdOut=True) ILogable.__init__(self, logger=logger) # Call the constructor of the ArgParseMixin @@ -231,6 +229,9 @@ def __init__(self, *args, **kwargs): self._configFiles.Structure = self.Directories.ConfigFiles / self.__CONFIGFILE_STRUCTURE self._configFiles.IPCores = self.Directories.ConfigFiles / self.__CONFIGFILE_IPCORES + self.__pocConfig = ExtendedConfigParser() + self.__pocConfig.optionxform = str + # class properties # ============================================================================ @property @@ -269,8 +270,6 @@ def __ReadPoCConfiguration(self): # create parser instance self.LogDebug("Reading PoC configuration from:") - self.__pocConfig = ExtendedConfigParser() - self.__pocConfig.optionxform = str try: # process first file (private) @@ -288,10 +287,10 @@ def __ReadPoCConfiguration(self): # check PoC installation directory if (self.Directories.Root != Path(self.PoCConfig['INSTALL.PoC']['InstallationDirectory'])): - raise NotConfiguredException("There is a mismatch between PoCRoot and PoC installation directory.") + raise NotConfiguredException("There is a mismatch between PoCRoot and PoC's installation directory.") # parsing values into class fields - configSection = self.PoCConfig['CONFIG.DirectoryNames'] + configSection = self.__pocConfig['CONFIG.DirectoryNames'] self.Directories.Source = self.Directories.Root / configSection['HDLSourceFiles'] self.Directories.Testbench = self.Directories.Root / configSection['TestbenchFiles'] self.Directories.NetList = self.Directories.Root / configSection['NetlistFiles'] @@ -312,10 +311,15 @@ def __WritePoCConfiguration(self): self.__pocConfig.remove_section("SOLUTION.DEFAULTS") # Writing configuration to disc - self.LogNormal("Writing configuration file to '{0!s}'".format(self._configFiles.Private)) + self.LogNormal("{GREEN}Writing configuration file to '{0!s}'.{NOCOLOR}".format(self._configFiles.Private, **Init.Foreground)) with self._configFiles.Private.open('w') as configFileHandle: self.PoCConfig.write(configFileHandle) + def SaveAndReloadPoCConfiguration(self): + self.__WritePoCConfiguration() + self.__pocConfig.clear() + self.__ReadPoCConfiguration() + def __PrepareForConfiguration(self): self.__ReadPoCConfiguration() @@ -391,97 +395,48 @@ def HandleHelp(self, args): # ---------------------------------------------------------------------------- @CommandGroupAttribute("Configuration commands") # mccabe:disable=MC0001 @CommandAttribute("configure", help="Configure vendor tools for PoC.") - @ArgumentAttribute(metavar="ToolChain", dest="ToolChain", type=str, nargs="?", help="Specify a tool chain to be configured.") + @ArgumentAttribute(metavar="ToolChain", dest="ToolChain", type=str, nargs="?", help="Specify a tool chain to be configured.") + @SwitchArgumentAttribute("--set-default-tools", dest="SetDefaultTools", help="Set default tool for a tool chain.") def HandleConfiguration(self, args): + """Handle 'configure' command.""" self.PrintHeadline() if (self.Platform not in ["Darwin", "Linux", "Windows"]): raise PlatformNotSupportedException(self.Platform) + # load existing configuration or create a new one try: self.__ReadPoCConfiguration() - self.__UpdateConfiguration() + configurator = Configurator(self) + configurator.UpdateConfiguration() except NotConfiguredException: - self._InitializeConfiguration() - - self.LogVerbose("starting manual configuration...") - print("Explanation of abbreviations:") - print(" {YELLOW}Y{NOCOLOR} - yes {YELLOW}P{NOCOLOR} - pass (jump to next question)".format(**Init.Foreground)) - print(" {YELLOW}N{NOCOLOR} - no {YELLOW}Ctrl + C{NOCOLOR} - abort (no changes are saved)".format(**Init.Foreground)) - print("Upper case or value in '[...]' means default value") - print("-"*80) - - # select tool chains for configuration - toolChain = args.ToolChain - if (toolChain is None): - configurators = [config(self) for config in Configurations] - elif (toolChain != ""): - sectionName = "INSTALL.{0}".format(toolChain) - configurators = [config(self) for config in Configurations if (config._section.lower().startswith(sectionName.lower()))] - - if (len(configurators) == 0): - self.LogError("{RED}No configuration named '{0}' found.{NOCOLOR}".format(toolChain, **Init.Foreground)) - return - - # configure each vendor or tool of a tool chain - print() - for configurator in configurators: - - # skip configuration with unsupported platforms - if (not configurator.IsSupportedPlatform()): continue - # skip configuration if dependency is not fulfilled - if (not configurator.CheckDependency()): - configurator.ClearSection() - continue - - self.LogNormal("{CYAN}Configuring {0!s}{NOCOLOR}".format(configurator, **Init.Foreground)) - nxt = False - while (nxt is False): - try: - if (self.Platform == "Darwin"): configurator.ConfigureForDarwin() - elif (self.Platform == "Linux"): configurator.ConfigureForLinux() - elif (self.Platform == "Windows"): configurator.ConfigureForWindows() - - nxt = True - except SkipConfigurationException: - break - except ExceptionBase as ex: - print(" {RED}FAULT:{NOCOLOR} {0}".format(ex.message, **Init.Foreground)) - except KeyboardInterrupt: - print("\n\n{RED}Abort configuration.\nNo files have been created or changed.{NOCOLOR}".format(**Init.Foreground)) - return - - # write and re-read configuration - self.__WritePoCConfiguration() - self.__ReadPoCConfiguration() - - # run post-configuration tasks - self.LogNormal("{CYAN}Running post configuration tasks{NOCOLOR}".format(**Init.Foreground)) - for configurator in configurators: - configurator.RunPostConfigurationTasks() - - def _InitializeConfiguration(self): - self.LogWarning("No private configuration found. Generating an empty PoC configuration...") - - for config in Configurations: - for sectionName in config.GetSections(self.Platform): - self.__pocConfig[sectionName] = OrderedDict() - - def __UpdateConfiguration(self): - pocSections = set([sectionName for sectionName in self.__pocConfig]) - configSections = set([sectionName for config in Configurations for sectionName in config.GetSections(self.Platform)]) + self.LogWarning("No private configuration found. Generating an empty PoC configuration...") + configurator = Configurator(self) + configurator.InitializeConfiguration() - addSections = configSections.difference(pocSections) - delSections = pocSections.difference(configSections) - - if addSections: - self.LogWarning("Adding new sections to configuration...") - for sectionName in addSections: - self.LogWarning(" Adding [{0}]".format(sectionName)) - self.__pocConfig[sectionName] = OrderedDict() - - if delSections: - for sectionName in delSections: - self.__pocConfig.remove_section(sectionName) + if (args.SetDefaultTools is True): + configurator.ConfigureDefaultTools() + else: + toolChain = args.ToolChain + if (toolChain is None): + configurator.ConfigureAll() + else: + configurator.ConfigureTool(toolChain) + + if (self.Logger.LogLevel is Severity.Debug): + self.LogDebug("Dumping PoCConfig...") + self.LogDebug("-" * 40) + for sectionName in self.__pocConfig.sections(): + if (not sectionName.startswith("INSTALL")): + continue + self.LogDebug("[{0}]".format(sectionName)) + configSection = self.__pocConfig[sectionName] + for optionName in configSection: + try: + optionValue = configSection[optionName] + except Exception: + optionValue = "-- ERROR --" + self.LogDebug("{0} = {1}".format(optionName, optionValue), indent=3) + self.LogDebug("-" * 40) # ---------------------------------------------------------------------------- # create the sub-parser for the "add-solution" command @@ -495,19 +450,23 @@ def HandleAddSolution(self, _): #args self.__PrepareForConfiguration() self.LogNormal("Register a new solutions in PoC") - solutionName = input(" Solution name: ") + self.LogNormal("Solution name: ", indent=1) + solutionName = input() if (solutionName == ""): raise ConfigurationException("Empty input. Aborting!") - solutionID = input(" Solution id: ") + self.LogNormal("Solution id: ", indent=1) + solutionID = input() if (solutionID == ""): raise ConfigurationException("Empty input. Aborting!") if (solutionID in self.__repo): raise ConfigurationException("Solution ID is already used.") - solutionRootPath = input(" Solution path: ") + self.LogNormal("Solution path: ", indent=1) + solutionRootPath = input() if (solutionRootPath == ""): raise ConfigurationException("Empty input. Aborting!") solutionRootPath = Path(solutionRootPath) if (not solutionRootPath.exists()): - createPath = input("Path does not exists. Should it be created? [Y/n]: ") + self.LogNormal("Path does not exists. Should it be created? [{CYAN}Y{NOCOLOR}/n]: ".format(**Init.Foreground), appendLinebreak=False) + createPath = input() createPath = createPath if createPath != "" else "Y" if (createPath in ['n', 'N']): raise ConfigurationException("Cannot continue to register the new project, because '{0!s}' does not exist.".format(solutionRootPath)) @@ -764,6 +723,21 @@ def _ExtractSimulationSteps(guiMode, analyze, elaborate, optimize, recompile, si simulationSteps |= SimulationSteps.ShowReport & showReport return simulationSteps + @staticmethod + def _ExtractCompileSteps(guiMode, synthesize, showReport, cleanUp): + compileSteps = CompileSteps.no_flags + if (not (synthesize)): + compileSteps |= CompileSteps.Prepare | SimulationSteps.CleanUpBefore + compileSteps |= CompileSteps.Synthesize + compileSteps |= CompileSteps.ShowReport & showReport + compileSteps |= CompileSteps.CleanUpAfter & cleanUp + else: + # simulationSteps |= SimulationSteps.CleanUpBefore & True #cleanup + compileSteps |= CompileSteps.Prepare & True #prepare + compileSteps |= CompileSteps.Synthesize & synthesize + compileSteps |= CompileSteps.ShowReport & showReport + return compileSteps + # ---------------------------------------------------------------------------- # create the sub-parser for the "list-testbench" command # ---------------------------------------------------------------------------- @@ -893,7 +867,7 @@ def HandleGHDLSimulation(self, args): config = GHDLConfiguration(self) if (not config.IsSupportedPlatform()): raise PlatformNotSupportedException() - if (not config.IsConfigured()): raise NotConfiguredException("GHDL is not configured on this system.") + if (not config.IsConfigured()): raise NotConfiguredException("GHDL is not configured on this system.") fqnList = self._ExtractFQNs(args.FQN) board = self._ExtractBoard(args.BoardName, args.DeviceName) @@ -951,8 +925,6 @@ def HandleQuestaSimulation(self, args): vhdlVersion = self._ExtractVHDLVersion(args.VHDLVersion) simulationSteps = self._ExtractSimulationSteps(args.GUIMode, args.Analyze, args.Elaborate, False, args.Recompile, args.Simulate, args.ShowWave, args.Resimulate, args.ShowReport, False) - print(simulationSteps) - simulator = QuestaSimulator(self, self.DryRun, simulationSteps) allPassed = simulator.RunAll(fqnList, board=board, vhdlVersion=vhdlVersion) @@ -1005,7 +977,7 @@ def HandleCocotbSimulation(self, args): # check if QuestaSim is configured if (len(self.PoCConfig.options("INSTALL.Mentor.QuestaSim")) == 0): if (len(self.PoCConfig.options("INSTALL.Altera.ModelSim")) == 0): - raise NotConfiguredException("Neither Mentor QuestaSim, Mentor ModelSimPE nor ModelSim Altera Edition are configured on this system.") + raise NotConfiguredException("Neither Mentor QuestaSim, Mentor ModelSim nor ModelSim Altera Edition are configured on this system.") fqnList = self._ExtractFQNs(args.FQN) board = self._ExtractBoard(args.BoardName, args.DeviceName) @@ -1229,8 +1201,7 @@ def HandleLSECompilation(self, args): # main program def main(): # mccabe:disable=MC0001 - """ - This is the entry point for PoC.py written as a function. + """This is the entry point for PoC.py written as a function. 1. It extracts common flags from the script's arguments list, before :py:class:`~argparse.ArgumentParser` is fully loaded. 2. It initializes colorama for colored outputs @@ -1288,7 +1259,7 @@ def main(): # mccabe:disable=MC0001 except EnvironmentException as ex: Exit.printEnvironmentException(ex) except NotConfiguredException as ex: Exit.printNotConfiguredException(ex) except PlatformNotSupportedException as ex: Exit.printPlatformNotSupportedException(ex) - except ExceptionBase as ex: Exit.printExceptionbase(ex) + except ExceptionBase as ex: Exit.printExceptionBase(ex) except NotImplementedError as ex: Exit.printNotImplementedError(ex) except Exception as ex: Exit.printException(ex) diff --git a/py/Processor/__init__.py b/py/Processor/__init__.py index 228b0ae3..2af16472 100644 --- a/py/Processor/__init__.py +++ b/py/Processor/__init__.py @@ -7,11 +7,6 @@ # # Python Sub Module: Saves The PoC-Library configuration as python source code. # -# Description: -# ------------------------------------ -# TODO: -# -# # License: # ============================================================================== # Copyright 2007-2015 Technische Universitaet Dresden - Germany @@ -30,12 +25,4 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Repository Service Tool") - # load dependencies diff --git a/py/README.md b/py/README.md index a11330c0..ba704f86 100644 --- a/py/README.md +++ b/py/README.md @@ -1,35 +1,14 @@ -# PoC Service Tool - -## Help command - -Print the help page(s) for a command. - -''' -.\poc.ps1 help -''' - -## Configuration commands - -## Simulation commands - -### Active-HDL - -### GHDL - -### QuestaSim - -### ISE Simulator - -### Vivado Simulator - -## Synthesis commands - -### Quartus - -### Lattice - -### Xilinx XST - -### Xilinx Core Generator - - +# The PoC-Library - Service Tool + +The complete Documentation is available on [PoC-Library.ReadTheDocs.io](http://poc-library.readthedocs.io/en/release/). +For a step by step introduction read our [Quick Start guide](http://poc-library.readthedocs.io/en/release/QuickStart.html). +A detailed usage guide is provided in the sections of [Using PoC](http://poc-library.readthedocs.io/en/release/UsingPoC/index.html). +Please also read [Tool Chain Specifics](http://poc-library.readthedocs.io/en/release/ToolChains/index.html) +for special tool chain features. + +The references chapter provides a complete [command line argument](http://poc-library.readthedocs.io/en/release/References/CmdRefs/PoC.html) +description for the service tool. In [IP Core Database](http://poc-library.readthedocs.io/en/release/References/Database.html) +we are describing how the IP Core database works so a user can integrate own cores into our repository and infrastructure. +PoC own file formats are documented [here](http://poc-library.readthedocs.io/en/release/References/FileFormats/index.html). +And finally, all Python packages, modules and classes are automatically documented by DocUtils/Sphinx in +[Python Infrastructure](http://poc-library.readthedocs.io/en/release/PyInfrastructure/index.html). diff --git a/py/Simulator/ActiveHDLSimulator.py b/py/Simulator/ActiveHDLSimulator.py index afd4906a..eafb1b9e 100644 --- a/py/Simulator/ActiveHDLSimulator.py +++ b/py/Simulator/ActiveHDLSimulator.py @@ -6,11 +6,7 @@ # Authors: Patrick Lehmann # Martin Zabel # -# Python Class: TODO -# -# Description: -# ------------------------------------ -# TODO: +# Python Module: Aldec Active-HDL simulator. # # License: # ============================================================================== @@ -31,12 +27,12 @@ # ============================================================================== # # load dependencies -from pathlib import Path +from pathlib import Path from Base.Exceptions import NotConfiguredException from Base.Project import FileTypes, ToolChain, Tool -from Base.Simulator import SimulatorException, Simulator as BaseSimulator, VHDL_TESTBENCH_LIBRARY_NAME, SkipableSimulatorException, SimulationSteps from ToolChains.Aldec.ActiveHDL import ActiveHDL, ActiveHDLException +from Simulator import VHDL_TESTBENCH_LIBRARY_NAME, SimulatorException, SkipableSimulatorException, SimulationSteps, Simulator as BaseSimulator __api__ = [ @@ -60,19 +56,19 @@ def __init__(self, host, dryRun, simulationSteps): self._PrepareSimulator() def _PrepareSimulator(self): - # create the Active-HDL executable factory + """Create the Active-HDL executable factory.""" self.LogVerbose("Preparing Active-HDL simulator.") - for sectionName in ['INSTALL.Aldec.ActiveHDL', 'INSTALL.Lattice.ActiveHDL']: - if (len(self.Host.PoCConfig.options(sectionName)) != 0): - break - else: - raise NotConfiguredException( - "Neither Aldec's Active-HDL nor Active-HDL Lattice Edition are configured on this system.") - - asimSection = self.Host.PoCConfig[sectionName] - binaryPath = Path(asimSection['BinaryDirectory']) - version = asimSection['Version'] - self._toolChain = ActiveHDL(self.Host.Platform, self.DryRun, binaryPath, version, logger=self.Logger) + # for sectionName in ['INSTALL.Aldec.ActiveHDL', 'INSTALL.Lattice.ActiveHDL']: + # if (len(self.Host.PoCConfig.options(sectionName)) != 0): + # break + # else: + # XXX: check SectionName if ActiveHDL is configured + # raise NotConfiguredException( + # "Neither Aldec's Active-HDL nor Active-HDL Lattice Edition are configured on this system.") + + binaryPath = Path(self.Host.PoCConfig['INSTALL.ActiveHDL']['BinaryDirectory']) + version = self.Host.PoCConfig['INSTALL.ActiveHDL']['Version'] + self._toolChain = ActiveHDL(self.Host.Platform, self.DryRun, binaryPath, version, logger=self.Logger) def _RunAnalysis(self, _): # create a ActiveHDLVHDLCompiler instance diff --git a/py/Simulator/CocotbSimulator.py b/py/Simulator/CocotbSimulator.py index a73526ea..193c7957 100644 --- a/py/Simulator/CocotbSimulator.py +++ b/py/Simulator/CocotbSimulator.py @@ -6,13 +6,7 @@ # Authors: Patrick Lehmann # Martin Zabel # -# Python Class: TODO -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Module: TODO # # License: # ============================================================================== @@ -37,10 +31,10 @@ from textwrap import dedent from Base.Project import FileTypes, ToolChain, Tool -from Base.Simulator import SimulatorException, Simulator as BaseSimulator, SimulationSteps -from DataBase.Config import Vendors -from DataBase.Entity import WildCard +from DataBase.Config import Vendors +from DataBase.Entity import WildCard from ToolChains.GNU import Make +from Simulator import SimulatorException, SimulationSteps, Simulator as BaseSimulator __api__ = [ diff --git a/py/Simulator/GHDLSimulator.py b/py/Simulator/GHDLSimulator.py index 4ffb9eab..5c98f7ee 100644 --- a/py/Simulator/GHDLSimulator.py +++ b/py/Simulator/GHDLSimulator.py @@ -6,13 +6,7 @@ # Authors: Patrick Lehmann # Martin Zabel # -# Python Class: TODO -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Module: GHDL simulator. # # License: # ============================================================================== @@ -38,7 +32,7 @@ from Base.Exceptions import NotConfiguredException from Base.Logging import Severity from Base.Project import FileTypes, VHDLVersion, ToolChain, Tool -from Base.Simulator import SimulatorException, Simulator as BaseSimulator, VHDL_TESTBENCH_LIBRARY_NAME, SkipableSimulatorException, SimulationSteps +from Simulator import VHDL_TESTBENCH_LIBRARY_NAME, SimulatorException, SkipableSimulatorException, SimulationSteps, Simulator as BaseSimulator from ToolChains.GHDL import GHDL, GHDLException, GHDLReanalyzeException from ToolChains.GTKWave import GTKWave @@ -157,6 +151,7 @@ def _RunElaboration(self, testbench): ghdl.Parameters[ghdl.SwitchVHDLLibrary] = VHDL_TESTBENCH_LIBRARY_NAME ghdl.Parameters[ghdl.ArgTopLevel] = testbench.ModuleName ghdl.Parameters[ghdl.FlagExplicit] = True + ghdl.Parameters[ghdl.SwitchLinkerOption] = ["-no-pie"] self._SetVHDLVersionAndIEEEFlavor(ghdl) self._SetExternalLibraryReferences(ghdl) diff --git a/py/Simulator/ISESimulator.py b/py/Simulator/ISESimulator.py index 43f7c3e2..9a0cc001 100644 --- a/py/Simulator/ISESimulator.py +++ b/py/Simulator/ISESimulator.py @@ -6,13 +6,7 @@ # Authors: Patrick Lehmann # Martin Zabel # -# Python Class: TODO -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Module: Xilinx ISE simulator. # # License: # ============================================================================== @@ -36,9 +30,9 @@ from pathlib import Path from Base.Project import ToolChain, Tool -from Base.Simulator import SimulatorException, Simulator as BaseSimulator, VHDL_TESTBENCH_LIBRARY_NAME, SkipableSimulatorException, SimulationSteps -from ToolChains.Xilinx.Xilinx import XilinxProjectExportMixIn +from ToolChains.Xilinx import XilinxProjectExportMixIn from ToolChains.Xilinx.ISE import ISE, ISESimulator, ISEException +from Simulator import VHDL_TESTBENCH_LIBRARY_NAME, SimulatorException, SkipableSimulatorException, SimulationSteps, Simulator as BaseSimulator __api__ = [ diff --git a/py/Simulator/QuestaSimulator.py b/py/Simulator/QuestaSimulator.py index 31ba51f8..f62716a1 100644 --- a/py/Simulator/QuestaSimulator.py +++ b/py/Simulator/QuestaSimulator.py @@ -6,11 +6,7 @@ # Authors: Patrick Lehmann # Martin Zabel # -# Python Class: TODO -# -# Description: -# ------------------------------------ -# TODO: +# Python Module: Mentor QuestaSim simulator. # # License: # ============================================================================== @@ -32,13 +28,13 @@ # # load dependencies from pathlib import Path -from textwrap import dedent +from textwrap import dedent from Base.Exceptions import NotConfiguredException from Base.Project import FileTypes, ToolChain, Tool -from Base.Simulator import SimulatorException, Simulator as BaseSimulator, VHDL_TESTBENCH_LIBRARY_NAME, SkipableSimulatorException, SimulationSteps from DataBase.Config import Vendors from ToolChains.Mentor.QuestaSim import QuestaSim, QuestaSimException +from Simulator import VHDL_TESTBENCH_LIBRARY_NAME, SimulatorException, SkipableSimulatorException, SimulationSteps, Simulator as BaseSimulator __api__ = [ @@ -70,16 +66,20 @@ def __init__(self, host, dryRun, simulationSteps): def _PrepareSimulator(self): # create the QuestaSim executable factory self.LogVerbose("Preparing Mentor simulator.") - for sectionName in ['INSTALL.Mentor.QuestaSim', 'INSTALL.Mentor.ModelSimPE', 'INSTALL.Altera.ModelSim']: - if (len(self.Host.PoCConfig.options(sectionName)) != 0): - break - else: - raise NotConfiguredException( - "Neither Mentor Graphics QuestaSim, ModelSim PE nor ModelSim Altera-Edition are configured on this system.") - - questaSection = self.Host.PoCConfig[sectionName] - binaryPath = Path(questaSection['BinaryDirectory']) - version = questaSection['Version'] + # for sectionName in ['INSTALL.Mentor.QuestaSim', 'INSTALL.Mentor.ModelSim', 'INSTALL.Altera.ModelSim']: + # if (len(self.Host.PoCConfig.options(sectionName)) != 0): + # break + # else: + # XXX: check SectionName if ModelSim is configured + # raise NotConfiguredException( + # "Neither Mentor Graphics QuestaSim, ModelSim PE nor ModelSim Altera-Edition are configured on this system.") + + # questaSection = self.Host.PoCConfig[sectionName] + # binaryPath = Path(questaSection['BinaryDirectory']) + # version = questaSection['Version'] + + binaryPath = Path(self.Host.PoCConfig['INSTALL.ModelSim']['BinaryDirectory']) + version = self.Host.PoCConfig['INSTALL.ModelSim']['Version'] self._toolChain = QuestaSim(self.Host.Platform, self.DryRun, binaryPath, version, logger=self.Logger) def Run(self, testbench, board, vhdlVersion, vhdlGenerics=None): diff --git a/py/Simulator/VivadoSimulator.py b/py/Simulator/VivadoSimulator.py index 4d466181..52cc939e 100644 --- a/py/Simulator/VivadoSimulator.py +++ b/py/Simulator/VivadoSimulator.py @@ -6,13 +6,7 @@ # Authors: Patrick Lehmann # Martin Zabel # -# Python Class: TODO -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Module: Xilinx Vivado simulator. # # License: # ============================================================================== @@ -35,11 +29,11 @@ # load dependencies from pathlib import Path -from Base.Project import ToolChain, Tool -from Base.Simulator import SimulatorException, Simulator as BaseSimulator, VHDL_TESTBENCH_LIBRARY_NAME, SkipableSimulatorException, SimulationSteps from Base.Logging import Severity -from ToolChains.Xilinx.Xilinx import XilinxProjectExportMixIn +from Base.Project import ToolChain, Tool +from ToolChains.Xilinx import XilinxProjectExportMixIn from ToolChains.Xilinx.Vivado import Vivado, VivadoException +from Simulator import VHDL_TESTBENCH_LIBRARY_NAME, SimulatorException, SkipableSimulatorException, SimulationSteps, Simulator as BaseSimulator __api__ = [ diff --git a/py/Simulator/__init__.py b/py/Simulator/__init__.py index 5c242809..52c4b6ad 100644 --- a/py/Simulator/__init__.py +++ b/py/Simulator/__init__.py @@ -7,11 +7,6 @@ # # Python Sub Module: TODO: # -# Description: -# ------------------------------------ -# TODO: -# -# # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany @@ -30,13 +25,363 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Repository Service Tool") - # load dependencies +from datetime import datetime +from enum import Enum, unique + +from flags import Flags + +from lib.Functions import Init +from lib.Decorators import MethodAlias +from Base import IHost +from Base.Exceptions import ExceptionBase, SkipableException +from Base.Logging import LogEntry +from Base.Project import Environment, VHDLVersion +from Base.Shared import Shared, to_time +from DataBase.Entity import WildCard +from DataBase.TestCase import TestCase, SimulationStatus, TestSuite + +# required for autoapi.sphinx +from lib.SphinxExtensions import DocumentMemberAttribute + + +__api__ = [ + 'SimulatorException', + 'SkipableSimulatorException', + 'PoCSimulationResultNotFoundException', + 'SimulationSteps', + 'SimulationState', + 'SimulationResult', + 'Simulator', + 'PoCSimulationResultFilter' +] +__all__ = __api__ + + +VHDL_TESTBENCH_LIBRARY_NAME = "test" + + +class SimulatorException(ExceptionBase): + """Base class for all SimulatorException classes. It is raised while running + simulation tasks in PoC. + """ + +class SkipableSimulatorException(SimulatorException, SkipableException): + """``SkipableSimulatorException`` is a :py:exc:`SimulatorException`, which + can be skipped. + """ + +class PoCSimulationResultNotFoundException(SkipableSimulatorException): + """This exception is raised if the expected PoC simulation result string was + not found in the simulator's output. + """ + + +@unique +class SimulationSteps(Flags): + """Simulation step enumeration.""" + Prepare = 1 << 0 + CleanUpBefore = 1 << 1 + CleanUpAfter = 1 << 2 + Analyze = 1 << 5 + Elaborate = 1 << 6 + # Compile = 1 << 7 + # Optimize = 1 << 8 + Simulate = 1 << 9 + ShowWaveform = 1 << 10 + ShowReport = 1 << 15 + Recompile = 1 << 25 + Resimulate = 1 << 26 + # Review = 1 << 27 + + def __and__(self, other): + if isinstance(other, bool): + return self if other else self.__class__.no_flags + else: + return super().__and__(other) + +@unique +class SimulationState(Enum): + """Simulation state enumeration.""" + Prepare = 0 + Analyze = 1 + Elaborate = 2 + Optimize = 3 + Simulate = 4 + View = 5 + +@unique +class SimulationResult(Enum): + """Simulation result enumeration.""" + NotRun = 0 + Error = 1 + Failed = 2 + NoAsserts = 3 + Passed = 4 + GUIRun = 5 + + +class Simulator(Shared): + """Base class for all Simulator classes.""" + + ENVIRONMENT = Environment.Simulation + VHDL_VERSION = VHDLVersion.VHDL2008 + + class __Directories__(Shared.__Directories__): + PreCompiled = None + + @DocumentMemberAttribute() + def __init__(self, host : IHost, dryRun, simulationSteps : SimulationSteps): + """Class initializer + + :type host: object + :param host: The hosting instance for this instance. + :type dryRun: bool + :param dryRun: Enable dry-run mode + :type simulationSteps: SimulationSteps + :param simulationSteps: A set of simulation step to precess. + """ + super().__init__(host, dryRun) + + self._vhdlVersion = None + self._vhdlGenerics = None + self._toolChain = None + + self._simulationSteps = simulationSteps + self._testSuite = TestSuite() # TODO: This includes not the read ini files phases ... + self._state = SimulationState.Prepare + self._analyzeTime = None + self._elaborationTime = None + self._simulationTime = None + + # class properties + # ============================================================================ + @property + def TestSuite(self): return self._testSuite + + def _PrepareSimulationEnvironment(self): + self.LogNormal("Preparing simulation environment...") + self._PrepareEnvironment() + + def _PrepareEnvironment_PurgeDirectory(self): + if (SimulationSteps.CleanUpBefore in self._simulationSteps): + super()._PrepareEnvironment_PurgeDirectory() + + @MethodAlias(Shared._Prepare) + def _PrepareSimulator(self): + pass + + def RunAll(self, fqnList, *args, **kwargs): + """Run a list of testbenches. Expand wildcards to all selected testbenches.""" + self._testSuite.StartTimer() + self.Logger.BaseIndent = int(len(fqnList) > 1) + try: + for fqn in fqnList: + entity = fqn.Entity + if (isinstance(entity, WildCard)): + self.Logger.BaseIndent = 1 + for testbench in entity.GetVHDLTestbenches(): + self.TryRun(testbench, *args, **kwargs) + else: + testbench = entity.VHDLTestbench + self.TryRun(testbench, *args, **kwargs) + except KeyboardInterrupt: + self.LogError("Received a keyboard interrupt.") + finally: + self._testSuite.StopTimer() + + if (SimulationSteps.ShowReport in self._simulationSteps): + self.PrintOverallSimulationReport() + + return self._testSuite.IsAllPassed + + def TryRun(self, testbench, *args, **kwargs): + """Try to run a testbench. Skip skipable exceptions by printing the error and its cause.""" + __SIMULATION_STATE_TO_TESTCASE_STATUS__ = { + SimulationState.Prepare: SimulationStatus.InternalError, + SimulationState.Analyze: SimulationStatus.AnalyzeError, + SimulationState.Elaborate: SimulationStatus.ElaborationError, + # SimulationState.Optimize: SimulationStatus.ElaborationError, + SimulationState.Simulate: SimulationStatus.SimulationError + } + + testCase = TestCase(testbench) + self._testSuite.AddTestCase(testCase) + testCase.StartTimer() + try: + self.Run(testbench, *args, **kwargs) + testCase.UpdateStatus(testbench.Result) + except SkipableSimulatorException as ex: + testCase.Status = __SIMULATION_STATE_TO_TESTCASE_STATUS__[self._state] + + self.LogQuiet(" {RED}ERROR:{NOCOLOR} {ExMsg}".format(ExMsg=ex.message, **Init.Foreground)) + cause = ex.__cause__ + if (cause is not None): + self.LogQuiet(" {YELLOW}{ExType}:{NOCOLOR} {ExMsg!s}".format(ExType=cause.__class__.__name__, ExMsg=cause, **Init.Foreground)) + cause = cause.__cause__ + if (cause is not None): + self.LogQuiet(" {YELLOW}{ExType}:{NOCOLOR} {ExMsg!s}".format(ExType=cause.__class__.__name__, ExMsg=cause, **Init.Foreground)) + self.LogQuiet(" {RED}[SKIPPED DUE TO ERRORS]{NOCOLOR}".format(**Init.Foreground)) + except SimulatorException: + testCase.Status = __SIMULATION_STATE_TO_TESTCASE_STATUS__[self._state] + raise + except ExceptionBase: + testCase.Status = SimulationStatus.SystemError + raise + finally: + testCase.StopTimer() + + def Run(self, testbench, board, vhdlVersion, vhdlGenerics=None): + """Write the Testbench message line, create a PoCProject and add the first *.files file to it.""" + self.LogQuiet("{CYAN}Testbench: {0!s}{NOCOLOR}".format(testbench.Parent, **Init.Foreground)) + + testbench.Result = SimulationResult.NotRun + + self._vhdlVersion = vhdlVersion + self._vhdlGenerics = vhdlGenerics + + # setup all needed paths to execute fuse + self._CreatePoCProject(testbench.ModuleName, board) + self._AddFileListFile(testbench.FilesFile) + + self._prepareTime = self._GetTimeDeltaSinceLastEvent() + + if self._simulationSteps.CleanUpBefore: + pass + + if self._simulationSteps.Prepare: + pass + + if self._simulationSteps.Analyze: + self.LogNormal("Running analysis for every vhdl file...") + self._state = SimulationState.Analyze + self._RunAnalysis(testbench) + self._analyzeTime = self._GetTimeDeltaSinceLastEvent() + + if self._simulationSteps.Elaborate: + self.LogNormal("Running elaboration...") + self._state = SimulationState.Elaborate + self._RunElaboration(testbench) + self._elaborationTime = self._GetTimeDeltaSinceLastEvent() + + # if self._simulationSteps.Optimize: + # pass + + if self._simulationSteps.Simulate: + self.LogNormal("Running simulation...") + self._state = SimulationState.Simulate + self._RunSimulation(testbench) + self._simulationTime = self._GetTimeDeltaSinceLastEvent() + + if self._simulationSteps.ShowWaveform: + self.LogNormal("Executing waveform viewer...") + self._state = SimulationState.View + self._RunView(testbench) + + self._endAt = datetime.now() + + def _RunAnalysis(self, testbench): + pass + + def _RunElaboration(self, testbench): + pass + + def _RunSimulation(self, testbench): + pass + + def _RunView(self, testbench): + pass + + def PrintOverallSimulationReport(self): + self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) + self.LogQuiet("{HEADLINE}{headline: ^80s}{NOCOLOR}".format(headline="Overall Simulation Report", **Init.Foreground)) + self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) + # table header + self.LogQuiet("{Name: <24} | {Duration: >5} | {Status: ^11}".format(Name="Name", Duration="Time", Status="Status")) + self.LogQuiet("-" * 80) + self.PrintSimulationReportLine(self._testSuite, 0, 24) + + self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) + self.LogQuiet("Time: {time: >5} Count: {count: <3} Passed: {passed: <3} No Asserts: {noassert: <2} Failed: {failed: <2} Errors: {error: <2}".format( + time=to_time(self._testSuite.OverallRunTime), + count=self._testSuite.Count, + passed=self._testSuite.PassedCount, + noassert=self._testSuite.NoAssertsCount, + failed=self._testSuite.FailedCount, + error=self._testSuite.ErrorCount + )) + self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) + + __SIMULATION_REPORT_COLOR_TABLE__ = { + SimulationStatus.Unknown: "RED", + SimulationStatus.InternalError: "DARK_RED", + SimulationStatus.SystemError: "DARK_RED", + SimulationStatus.AnalyzeError: "DARK_RED", + SimulationStatus.ElaborationError: "DARK_RED", + SimulationStatus.SimulationError: "RED", + SimulationStatus.SimulationFailed: "RED", + SimulationStatus.SimulationNoAsserts: "YELLOW", + SimulationStatus.SimulationSuccess: "GREEN", + SimulationStatus.SimulationGUIRun: "YELLOW" + } + + __SIMULATION_REPORT_STATUS_TEXT_TABLE__ = { + SimulationStatus.Unknown: "-- ?? --", + SimulationStatus.InternalError: "INT. ERROR", + SimulationStatus.SystemError: "SYS. ERROR", + SimulationStatus.AnalyzeError: "ANA. ERROR", + SimulationStatus.ElaborationError: "ELAB. ERROR", + SimulationStatus.SimulationError: "SIM. ERROR", + SimulationStatus.SimulationFailed: "FAILED", + SimulationStatus.SimulationNoAsserts: "NO ASSERTS", + SimulationStatus.SimulationSuccess: "PASSED", + SimulationStatus.SimulationGUIRun: "GUI RUN" + } + + def PrintSimulationReportLine(self, testObject, indent, nameColumnWidth): + _indent = " " * indent + for group in testObject.Groups.values(): + pattern = "{indent}{{groupName: <{nameColumnWidth}}} | | ".format(indent=_indent, nameColumnWidth=nameColumnWidth) + self.LogQuiet(pattern.format(groupName=group.Name)) + self.PrintSimulationReportLine(group, indent + 1, nameColumnWidth - 2) + for testCase in testObject.TestCases.values(): + pattern = "{indent}{{testcaseName: <{nameColumnWidth}}} | {{duration: >5}} | {{{color}}}{{status: ^11}}{{NOCOLOR}}".format( + indent=_indent, nameColumnWidth=nameColumnWidth, color=self.__SIMULATION_REPORT_COLOR_TABLE__[testCase.Status]) + self.LogQuiet(pattern.format(testcaseName=testCase.Name, duration=to_time(testCase.OverallRunTime), + status=self.__SIMULATION_REPORT_STATUS_TEXT_TABLE__[testCase.Status], **Init.Foreground)) + + +def PoCSimulationResultFilter(gen, simulationResult): + state = 0 + for line in gen: + if ((state == 0) and (line.Message == "========================================")): + state += 1 + elif ((state == 1) and (line.Message == "POC TESTBENCH REPORT")): + state += 1 + elif ((state == 2) and (line.Message == "========================================")): + state += 1 + elif ((state == 3) and (line.Message == "========================================")): + state += 1 + elif ((state == 4) and line.Message.startswith("SIMULATION RESULT = ")): + state += 1 + if line.Message.endswith("FAILED"): + color = Init.Foreground['RED'] + simulationResult <<= SimulationResult.Failed + elif line.Message.endswith("NO ASSERTS"): + color = Init.Foreground['YELLOW'] + simulationResult <<= SimulationResult.NoAsserts + elif line.Message.endswith("PASSED"): + color = Init.Foreground['GREEN'] + simulationResult <<= SimulationResult.Passed + else: + color = Init.Foreground['RED'] + simulationResult <<= SimulationResult.Error + + yield LogEntry("{COLOR}{line}{NOCOLOR}".format(COLOR=color,line=line.Message, **Init.Foreground), line.Severity, line.Indent) + continue + elif ((state == 5) and (line.Message == "========================================")): + state += 1 + + yield line + if (state != 6): raise PoCSimulationResultNotFoundException("No PoC Testbench Report in simulator output found.") diff --git a/py/ToolChains/Aldec/ActiveHDL.py b/py/ToolChains/Aldec/ActiveHDL.py index f49a3083..d46366ae 100644 --- a/py/ToolChains/Aldec/ActiveHDL.py +++ b/py/ToolChains/Aldec/ActiveHDL.py @@ -6,13 +6,7 @@ # Authors: Patrick Lehmann # Martin Zabel # -# Python Class: Aldec Active-HDL specific classes -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Class: Aldec Active-HDL specific classes # # License: # ============================================================================== @@ -32,23 +26,26 @@ # limitations under the License. # ============================================================================== # -# entry point +# load dependencies +from collections import OrderedDict +from enum import unique from subprocess import check_output -from ToolChains import ToolMixIn -from lib.Functions import CallByRefParam +from lib.Functions import CallByRefParam, Init from Base.Exceptions import PlatformNotSupportedException from Base.Logging import LogEntry, Severity -from Base.Simulator import SimulationResult, PoCSimulationResultFilter from Base.Executable import Executable from Base.Executable import ExecutableArgument, PathArgument, StringArgument from Base.Executable import LongFlagArgument, ShortValuedFlagArgument, ShortTupleArgument, CommandLineArgumentList -from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException -from ToolChains.Aldec.Aldec import AldecException +from ToolChains import ToolMixIn, ConfigurationException, ToolConfiguration, EditionDescription, Edition, ToolSelector +from ToolChains.Aldec import AldecException +from Simulator import SimulationResult, PoCSimulationResultFilter __api__ = [ 'ActiveHDLException', + 'AldecActiveHDLEditions', + 'ActiveHDLEditions', 'Configuration', 'ActiveHDL', 'VHDLCompiler', @@ -63,74 +60,168 @@ class ActiveHDLException(AldecException): - pass + """An ActiveHDLException is raised if Active-HDL catches a system exception.""" + + +@unique +class AldecActiveHDLEditions(Edition): + """Enumeration of all Active-HDL editions provided by Aldec itself.""" + StandardEdition = EditionDescription(Name="Active-HDL", Section="foo") + StudentEdition = EditionDescription(Name="Active-HDL (Student Edition)", Section="bar") -class Configuration(BaseConfiguration): - _vendor = "Aldec" - _toolName = "Aldec Active-HDL" - _section = "INSTALL.Aldec.ActiveHDL" +@unique +class ActiveHDLEditions(Edition): + """Enumeration of all Active-HDL editions provided by Aldec inclusive editions + shipped by other vendors. + """ + StandardEdition = EditionDescription(Name="Aldec Active-HDL", Section="INSTALL.Aldec.ActiveHDL") + LatticeEdition = EditionDescription(Name="Active-HDL Lattice Edition", Section="INSTALL.Lattice.ActiveHDL") + # StudentEdition = "Active-HDL (Student Edition)" + + +class Configuration(ToolConfiguration): + _vendor = "Aldec" #: The name of the tools vendor. + _toolName = "Aldec Active-HDL" #: The name of the tool. + _section = "INSTALL.Aldec.ActiveHDL" #: The name of the configuration section. Pattern: ``INSTALL.Vendor.ToolName``. + _multiVersionSupport = True #: Aldec Active-HDL supports multiple versions installed on the same system. _template = { "Windows": { _section: { "Version": "10.3", - "InstallationDirectory": "${INSTALL.Aldec:InstallationDirectory}/Active-HDL", - "BinaryDirectory": "${InstallationDirectory}/BIN" - } - }, - "Linux": { - _section: { - # "Version": "10.4c", - # "InstallationDirectory": "${INSTALL.Aldec:InstallationDirectory}/${Version}", - # "BinaryDirectory": "${InstallationDirectory}/bin" + "SectionName": ("%{PathWithRoot}#${Version}", None), + "Edition": ("${${SectionName}:Edition}", "Active-HDL"), + "InstallationDirectory": ("${${SectionName}:InstallationDirectory}", "${INSTALL.Aldec:InstallationDirectory}/Active-HDL"), + "BinaryDirectory": ("${${SectionName}:BinaryDirectory}", "${InstallationDirectory}/BIN") } } - } + } #: The template for the configuration sections represented as nested dictionaries. def CheckDependency(self): - # return True if Aldec is configured + """Check if general Aldec support is configured in PoC.""" return (len(self._host.PoCConfig['INSTALL.Aldec']) != 0) def ConfigureForAll(self): + """Configuration routine for Aldec Active-HDL on all supported platforms. + + #. Ask if Active-HDL is installed. + + * Pass |rarr| skip this configuration. Don't change existing settings. + * Yes |rarr| collect installation information for Active-HDL. + * No |rarr| clear the Active-HDL configuration section. + + #. Ask for Active-HDL's version. + #. Ask for Active-HDL's edition (normal, student). + #. Ask for Active-HDL's installation directory. + """ try: if (not self._AskInstalled("Is Aldec Active-HDL installed on your system?")): self.ClearSection() else: + # Configure Active-HDL version version = self._ConfigureVersion() + if self._multiVersionSupport: + self.PrepareVersionedSections() + sectionName = self._host.PoCConfig[self._section]['SectionName'] + self._host.PoCConfig[sectionName]['Version'] = version + + # Configure Active-HDL edition + changed,edition = self._ConfigureEdition() + if changed: + if (edition is AldecActiveHDLEditions.StudentEdition): + if self._multiVersionSupport: + sectionName = self._host.PoCConfig[self._section]['SectionName'] + else: + sectionName = self._section + self._host.PoCConfig[sectionName]['InstallationDirectory'] = self._host.PoCConfig.get(sectionName, 'InstallationDirectory', raw=True) + "-Student-Edition" + self._host.PoCConfig.Interpolation.clear_cache() + # Configure installation directory self._ConfigureInstallationDirectory() + # Configure binary directory binPath = self._ConfigureBinaryDirectory() + # Check version for correctness self.__CheckActiveHDLVersion(binPath, version) + self._host.LogNormal("{DARK_GREEN}Aldec Active-HDL is now configured.{NOCOLOR}".format(**Init.Foreground), indent=1) except ConfigurationException: self.ClearSection() + # FIXME: also remove all versioned sections; implement it in ClearSection? raise + def _ConfigureEdition(self): + """Configure Active-HDL for Aldec.""" + sectionName = self._section + if self._multiVersionSupport: + sectionName = self._host.PoCConfig[sectionName]['SectionName'] + + configSection = self._host.PoCConfig[sectionName] + defaultEdition = AldecActiveHDLEditions.Parse(configSection['Edition']) + edition = super()._ConfigureEdition(AldecActiveHDLEditions, defaultEdition) + + if (edition is not defaultEdition): + configSection['Edition'] = edition.Name + self._host.PoCConfig.Interpolation.clear_cache() + return (True, edition) + else: + return (False, edition) + def __CheckActiveHDLVersion(self, binPath, version): + """Compare the given Active-HDL version with the tool's version string.""" + # TODO: use vsim abstraction? if (self._host.Platform == "Windows"): vsimPath = binPath / "vsim.exe" else: vsimPath = binPath / "vsim" if not vsimPath.exists(): - raise ConfigurationException("Executable '{0!s}' not found.".format(vsimPath)) from FileNotFoundError( - str(vsimPath)) + raise ConfigurationException("Executable '{0!s}' not found.".format(vsimPath)) \ + from FileNotFoundError(str(vsimPath)) output = check_output([str(vsimPath), "-version"], universal_newlines=True) if str(version) not in output: raise ConfigurationException("Active-HDL version mismatch. Expected version {0}.".format(version)) +class Selector(ToolSelector): + _toolName = "Active-HDL" + + def Select(self): + editions = self._GetConfiguredEditions(ActiveHDLEditions) + + if (len(editions) == 0): + self._host.LogWarning("No Active-HDL installation found.", indent=1) + self._host.PoCConfig['INSTALL.ActiveHDL'] = OrderedDict() + elif (len(editions) == 1): + self._host.LogNormal("Default Active-HDL installation:", indent=1) + self._host.LogNormal("Set to {0}".format(editions[0].Name), indent=2) + self._host.PoCConfig['INSTALL.ActiveHDL']['SectionName'] = editions[0].Section + else: + self._host.LogNormal("Select Active-HDL installation:", indent=1) + + defaultEdition = ActiveHDLEditions.LatticeEdition + if defaultEdition not in editions: + defaultEdition = editions[0] + + selectedEdition = self._AskSelection(editions, defaultEdition) + self._host.PoCConfig['INSTALL.ActiveHDL']['SectionName'] = selectedEdition.Section + + class ActiveHDL(ToolMixIn): + """Factory for executable abstractions in Active-HDL.""" def GetVHDLLibraryTool(self): + """Return an instance of Active-HDL's VHDL library management tool 'vlib'.""" return ActiveHDLVHDLLibraryTool(self) def GetVHDLCompiler(self): + """Return an instance of Active-HDL's VHDL compiler 'vcom'.""" return VHDLCompiler(self) def GetSimulator(self): + """Return an instance of Active-HDL's VHDL simulator 'vsim'.""" return StandaloneSimulator(self) class VHDLCompiler(Executable, ToolMixIn): + """Abstraction layer of Active-HDL's VHDL compiler 'vcom'.""" def __init__(self, toolchain : ToolMixIn): ToolMixIn.__init__( self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, @@ -230,6 +321,7 @@ def Compile(self): class StandaloneSimulator(Executable, ToolMixIn): + """Abstraction layer of Active-HDL's VHDL standalone simulator 'vsimsa'.""" def __init__(self, toolchain : ToolMixIn): ToolMixIn.__init__( self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, @@ -305,6 +397,7 @@ def Simulate(self): class Simulator(Executable, ToolMixIn): + """Abstraction layer of Active-HDL's VHDL simulator 'vsim'.""" def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): ToolMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger=logger) if (self._platform == "Windows"): executablePath = binaryDirectoryPath / "vsimsa.exe" @@ -371,6 +464,7 @@ def Simulate(self): class ActiveHDLVHDLLibraryTool(Executable, ToolMixIn): + """Abstraction layer of Active-HDL's VHDL library management tool 'vlib'.""" def __init__(self, toolchain : ToolMixIn): ToolMixIn.__init__( self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, @@ -463,6 +557,7 @@ def CreateLibrary(self): def VHDLCompilerFilter(gen): # mccabe:disable=MC0001 + """A line based output stream filter for Active-HDL's VHDL compiler.""" for line in gen: if line.startswith("Aldec, Inc. VHDL Compiler"): yield LogEntry(line, Severity.Debug) @@ -497,6 +592,7 @@ def VHDLCompilerFilter(gen): # mccabe:disable=MC0001 def SimulatorFilter(gen): + """A line based output stream filter for Active-HDL's VHDL simulator.""" PoCOutputFound = False for line in gen: if line.startswith("asim"): @@ -525,6 +621,9 @@ def SimulatorFilter(gen): yield LogEntry(line, Severity.Normal) def VHDLLibraryToolFilter(gen): + """A line based output stream filter for Active-HDL's VHDL library management + tool. + """ for line in gen: if line.startswith("ALIB: Library "): yield LogEntry(line, Severity.Verbose) diff --git a/py/ToolChains/Aldec/__init__.py b/py/ToolChains/Aldec/__init__.py index 896b9579..74cd1b97 100644 --- a/py/ToolChains/Aldec/__init__.py +++ b/py/ToolChains/Aldec/__init__.py @@ -1,16 +1,12 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; # # ============================================================================== -# Authors: Patrick Lehmann -# -# Python Sub Module: TODO: -# -# Description: -# ------------------------------------ -# TODO: +# Authors: Patrick Lehmann +# Martin Zabel # +# Python Class: TODO # # License: # ============================================================================== @@ -21,7 +17,7 @@ # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # -# http://www.apache.org/licenses/LICENSE-2.0 +# http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, @@ -30,13 +26,57 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Repository Service Tool") +# load dependencies +from lib.Functions import Init +from ToolChains import ToolChainException, VendorConfiguration + + +__api__ = [ + 'AldecException', + 'Configuration' +] +__all__ = __api__ + + +class AldecException(ToolChainException): + """Base class for all Aldec tool's exceptions.""" + + +class Configuration(VendorConfiguration): + """Configuration routines for Aldec as a vendor. + This configuration provides a common installation directory setup for all + Aldec tools installed on a system. + """ + _vendor = "Aldec" #: The name of the tools vendor. + _section = "INSTALL.Aldec" #: The name of the configuration section. Pattern: ``INSTALL.Vendor.ToolName``. + _template = { + "ALL": { + "INSTALL.ActiveHDL": { + "SectionName": "", + "Version": "${${SectionName}:Version}", + "Edition": "${${SectionName}:Edition}", + "InstallationDirectory": "${${SectionName}:InstallationDirectory}", + "BinaryDirectory": "${${SectionName}:BinaryDirectory}" + } + }, + "Windows": { + _section: { + "InstallationDirectory": "C:/Aldec" + } + }, + "Linux": { + _section: { + "InstallationDirectory": "/opt/Aldec" + } + } + } #: The template for the configuration sections represented as nested dictionaries. + def ConfigureForAll(self): + super().ConfigureForAll() + self._host.LogNormal("{DARK_GREEN}Aldec is now configured.{NOCOLOR}".format(**Init.Foreground), indent=1) + def _GetDefaultInstallationDirectory(self): + path = self._TestDefaultInstallPath({"Windows": "Aldec", "Linux": "Aldec"}) + if path is None: return super()._GetDefaultInstallationDirectory() + return path.as_posix() diff --git a/py/ToolChains/Altera/Altera.py b/py/ToolChains/Altera/Altera.py deleted file mode 100644 index 6f773f67..00000000 --- a/py/ToolChains/Altera/Altera.py +++ /dev/null @@ -1,75 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# -# ============================================================================== -# Authors: Patrick Lehmann -# Martin Zabel -# -# Python Class: TODO -# -# Description: -# ------------------------------------ -# TODO: -# - -# - -# -# License: -# ============================================================================== -# Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair of VLSI-Design, Diagnostics and Architecture -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# ============================================================================== -# -# load dependencies -from Base.Configuration import Configuration as BaseConfiguration -from Base.ToolChain import ToolChainException - - -__api__ = [ - 'AlteraException', - 'Configuration' -] -__all__ = __api__ - - -class AlteraException(ToolChainException): - pass - - -class Configuration(BaseConfiguration): - _vendor = "Altera" - _toolName = None # automatically configure only vendor path - _section = "INSTALL.Altera" - _template = { - "Windows": { - _section: { - "InstallationDirectory": "C:/Altera" - } - }, - "Linux": { - _section: { - "InstallationDirectory": "/opt/Altera" - } - } - } - - def _GetDefaultInstallationDirectory(self): - # altera = environ.get("QUARTUS_ROOTDIR") # on Windows: D:\Altera\13.1\quartus - # if (altera is not None): - # return str(Path(altera).parent.parent) - - path = self._TestDefaultInstallPath({"Windows": "Altera", "Linux": "Altera"}) - if path is None: return super()._GetDefaultInstallationDirectory() - return path.as_posix() diff --git a/py/ToolChains/Altera/ModelSim.py b/py/ToolChains/Altera/ModelSim.py index 283bd02c..14d20d5a 100644 --- a/py/ToolChains/Altera/ModelSim.py +++ b/py/ToolChains/Altera/ModelSim.py @@ -9,12 +9,6 @@ # # Python Class: Altera ModelSim specific classes # -# Description: -# ------------------------------------ -# TODO: -# - -# - -# # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany @@ -34,48 +28,60 @@ # ============================================================================== # # load dependencies -from re import compile as RegExpCompile +from enum import unique +from re import compile as re_compile from subprocess import check_output -from Base.Configuration import ConfigurationException -from ToolChains.Mentor.ModelSimPE import Configuration as ModelSimPE_Configuration -from ToolChains.Altera.Altera import AlteraException +from lib.Functions import Init +from ToolChains import ConfigurationException, EditionDescription, Edition +from ToolChains.Altera import AlteraException +from ToolChains.Mentor.ModelSim import Configuration as Mentor_ModelSim_Configuration, ModelSimException as Mentor_ModelSimException __api__ = [ 'ModelSimException', + 'AlteraModelSimEditions', 'Configuration' ] __all__ = __api__ -class ModelSimException(AlteraException): +class ModelSimException(AlteraException, Mentor_ModelSimException): pass -class Configuration(ModelSimPE_Configuration): - _vendor = "Altera" - _toolName = "ModelSim Altera Edition" - _section = "INSTALL.Altera.ModelSim" +@unique +class AlteraModelSimEditions(Edition): + """Enumeration of all ModelSim editions provided by Altera.""" + ModelSimAlteraEdition = EditionDescription(Name="ModelSim Altera Edition", Section=None) + ModelSimAlteraStarterEdition = EditionDescription(Name="ModelSim Altera Starter Edition", Section=None) + + +class Configuration(Mentor_ModelSim_Configuration): + _vendor = "Altera" #: The name of the tools vendor. + _toolName = "Altera ModelSim" #: The name of the tool. + _section = "INSTALL.Altera.ModelSim" #: The name of the configuration section. Pattern: ``INSTALL.Vendor.ToolName``. _template = { "Windows": { _section: { "Version": "10.4b", - "InstallationDirectory": "${INSTALL.Altera:InstallationDirectory}/${INSTALL.Altera.Quartus:Version}/modelsim_ase", + "Edition": "ModelSim Altera Edition", + "InstallationDirectory": "${INSTALL.Altera:InstallationDirectory}/${INSTALL.Altera.Quartus:Version}/modelsim_ae", "BinaryDirectory": "${InstallationDirectory}/win32aloem" } }, "Linux": { _section: { "Version": "10.4b", - "InstallationDirectory": "${INSTALL.Altera:InstallationDirectory}/${INSTALL.Altera.Quartus:Version}/modelsim_ase", + "Edition": "ModelSim Altera Edition", + "InstallationDirectory": "${INSTALL.Altera:InstallationDirectory}/${INSTALL.Altera.Quartus:Version}/modelsim_ae", "BinaryDirectory": "${InstallationDirectory}/linuxaloem" } } - } + } #: The template for the configuration sections represented as nested dictionaries. def CheckDependency(self): - # return True if Altera is configured + """Check if general Altera support is configured in PoC.""" return (len(self._host.PoCConfig['INSTALL.Altera']) != 0) def ConfigureForAll(self): @@ -83,13 +89,37 @@ def ConfigureForAll(self): if (not self._AskInstalled("Is ModelSim Altera Edition installed on your system?")): self.ClearSection() else: + # Configure ModelSim version + + changed,edition = self._ConfigureEdition() + if changed: + configSection = self._host.PoCConfig[self._section] + if (edition is AlteraModelSimEditions.ModelSimAlteraEdition): + configSection['InstallationDirectory'] = self._host.PoCConfig.get(self._section, 'InstallationDirectory', raw=True).replace("_ase", "_ae") + elif (edition is AlteraModelSimEditions.ModelSimAlteraStarterEdition): + configSection['InstallationDirectory'] = self._host.PoCConfig.get(self._section, 'InstallationDirectory', raw=True).replace("_ae", "_ase") + self._ConfigureInstallationDirectory() binPath = self._ConfigureBinaryDirectory() self.__GetModelSimVersion(binPath) + self._host.LogNormal("{DARK_GREEN}Altera ModelSim is now configured.{NOCOLOR}".format(**Init.Foreground), indent=1) except ConfigurationException: self.ClearSection() raise + def _ConfigureEdition(self): + """Configure ModelSim for Altera.""" + configSection = self._host.PoCConfig[self._section] + defaultEdition = AlteraModelSimEditions.Parse(configSection['Edition']) + edition = super()._ConfigureEdition(AlteraModelSimEditions, defaultEdition) + + if (edition is not defaultEdition): + configSection['Edition'] = edition.Name + self._host.PoCConfig.Interpolation.clear_cache() + return (True, edition) + else: + return (False, edition) + def __GetModelSimVersion(self, binPath): if (self._host.Platform == "Windows"): vsimPath = binPath / "vsim.exe" @@ -97,8 +127,8 @@ def __GetModelSimVersion(self, binPath): vsimPath = binPath / "vsim" if not vsimPath.exists(): - raise ConfigurationException("Executable '{0!s}' not found.".format(vsimPath)) from FileNotFoundError( - str(vsimPath)) + raise ConfigurationException("Executable '{0!s}' not found.".format(vsimPath)) \ + from FileNotFoundError(str(vsimPath)) # get version and backend try: @@ -108,7 +138,7 @@ def __GetModelSimVersion(self, binPath): version = None versionRegExpStr = r"^.* vsim (.+?) " - versionRegExp = RegExpCompile(versionRegExpStr) + versionRegExp = re_compile(versionRegExpStr) for line in output.split('\n'): if version is None: match = versionRegExp.match(line) diff --git a/py/ToolChains/Altera/Quartus.py b/py/ToolChains/Altera/Quartus.py index 2468e548..6142c5e1 100644 --- a/py/ToolChains/Altera/Quartus.py +++ b/py/ToolChains/Altera/Quartus.py @@ -6,13 +6,7 @@ # Authors: Patrick Lehmann # Martin Zabel # -# Python Class: Altera Quartus specific classes -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Class: Altera Quartus specific classes # # License: # ============================================================================== @@ -34,22 +28,23 @@ # # load dependencies from collections import OrderedDict +from enum import unique from subprocess import check_output, STDOUT -from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException +from lib.Functions import Init from Base.Exceptions import PlatformNotSupportedException -from Base.Logging import Severity, LogEntry +from Base.Logging import Severity, LogEntry from Base.Executable import Executable, CommandLineArgumentList from Base.Executable import ExecutableArgument, ShortValuedFlagArgument, LongValuedFlagArgument, StringArgument, ShortFlagArgument -from Base.Project import Project as BaseProject, ProjectFile, FileTypes, SettingsFile -from ToolChains import ToolMixIn -from ToolChains.Altera.Altera import AlteraException +from Base.Project import Project as BaseProject, ProjectFile, FileTypes, SettingsFile +from ToolChains import ToolMixIn, ConfigurationException, ToolConfiguration, EditionDescription, Edition, ToolSelector +from ToolChains.Altera import AlteraException __api__ = [ 'QuartusException', + 'QuartusEditions', 'Configuration', - 'ToolMixIn', 'Quartus', 'Map', 'TclShell', @@ -66,29 +61,39 @@ class QuartusException(AlteraException): pass -class Configuration(BaseConfiguration): - _vendor = "Altera" - _toolName = "Altera Quartus" - _section = "INSTALL.Altera.Quartus" +@unique +class QuartusEditions(Edition): + """Enumeration of all Quartus editions provided by Altera itself.""" + AlteraQuartus = EditionDescription(Name="Altera Quartus", Section="INSTALL.Altera.Quartus") + IntelQuartus = EditionDescription(Name="Intel Quartus", Section="INSTALL.Intel.Quartus") + + +class Configuration(ToolConfiguration): + _vendor = "Altera" #: The name of the tools vendor. + _toolName = "Altera Quartus" #: The name of the tool. + _section = "INSTALL.Altera.Quartus" #: The name of the configuration section. Pattern: ``INSTALL.Vendor.ToolName``. + _multiVersionSupport = True #: Altera Quartus supports multiple versions installed on the same system. _template = { "Windows": { _section: { - "Version": "15.1", - "InstallationDirectory": "${INSTALL.Altera:InstallationDirectory}/${Version}/quartus", - "BinaryDirectory": "${InstallationDirectory}/bin64" + "Version": "16.0", + "SectionName": ("%{PathWithRoot}#${Version}", None), + "InstallationDirectory": ("${${SectionName}:InstallationDirectory}", "${INSTALL.Altera:InstallationDirectory}/${Version}/quartus"), + "BinaryDirectory": ("${${SectionName}:BinaryDirectory}", "${InstallationDirectory}/bin64") } }, "Linux": { _section: { - "Version": "15.1", - "InstallationDirectory": "${INSTALL.Altera:InstallationDirectory}/${Version}/quartus", - "BinaryDirectory": "${InstallationDirectory}/bin" + "Version": "16.0", + "SectionName": ("%{PathWithRoot}#${Version}", None), + "InstallationDirectory": ("${${SectionName}:InstallationDirectory}", "${INSTALL.Altera:InstallationDirectory}/${Version}/quartus"), + "BinaryDirectory": ("${${SectionName}:BinaryDirectory}", "${InstallationDirectory}/bin") } } - } + } #: The template for the configuration sections represented as nested dictionaries. def CheckDependency(self): - # return True if Altera is configured + """Check if general Altera support is configured in PoC.""" return (len(self._host.PoCConfig['INSTALL.Altera']) != 0) def ConfigureForAll(self): @@ -96,10 +101,20 @@ def ConfigureForAll(self): if (not self._AskInstalled("Is Altera Quartus-II or Quartus Prime installed on your system?")): self.ClearSection() else: + # Configure Quartus version version = self._ConfigureVersion() + if self._multiVersionSupport: + self.PrepareVersionedSections() + sectionName = self._host.PoCConfig[self._section]['SectionName'] + self._host.PoCConfig[sectionName]['Version'] = version + self._ConfigureInstallationDirectory() binPath = self._ConfigureBinaryDirectory() + + self.LogNormal("Checking Altera Quartus version... (this may take a few seconds)", indent=1) self.__CheckQuartusVersion(binPath, version) + + self.LogNormal("{DARK_GREEN}Altera Quartus is now configured.{NOCOLOR}".format(**Init.Foreground), indent=1) except ConfigurationException: self.ClearSection() raise @@ -111,14 +126,38 @@ def __CheckQuartusVersion(self, binPath, version): quartusPath = binPath / "quartus_sh" if not quartusPath.exists(): - raise ConfigurationException("Executable '{0!s}' not found.".format(quartusPath)) from FileNotFoundError( - str(quartusPath)) + raise ConfigurationException("Executable '{0!s}' not found.".format(quartusPath)) \ + from FileNotFoundError(str(quartusPath)) output = check_output([str(quartusPath), "-v"], universal_newlines=True, stderr=STDOUT) if "Version {0}".format(version) not in output: raise ConfigurationException("Quartus version mismatch. Expected version {0}.".format(version)) +class Selector(ToolSelector): + _toolName = "Quartus" + + def Select(self): + editions = self._GetConfiguredEditions(QuartusEditions) + + if (len(editions) == 0): + self._host.LogWarning("No Quartus installation found.", indent=1) + self._host.PoCConfig['INSTALL.Quartus'] = OrderedDict() + elif (len(editions) == 1): + self._host.LogNormal("Default Quartus installation:", indent=1) + self._host.LogNormal("Set to {0}".format(editions[0].Name), indent=2) + self._host.PoCConfig['INSTALL.Quartus']['SectionName'] = editions[0].Section + else: + self._host.LogNormal("Select Quartus installation:", indent=1) + + defaultEdition = QuartusEditions.IntelQuartus + if defaultEdition not in editions: + defaultEdition = editions[0] + + selectedEdition = self._AskSelection(editions, defaultEdition) + self._host.PoCConfig['INSTALL.Quartus']['SectionName'] = selectedEdition.Section + + class Quartus(ToolMixIn): def GetMap(self): return Map(self) @@ -399,4 +438,3 @@ def Write(self): class QuartusProjectFile(ProjectFile): def __init__(self, file): super().__init__(file) - diff --git a/py/ToolChains/Altera/__init__.py b/py/ToolChains/Altera/__init__.py index 896b9579..084740b9 100644 --- a/py/ToolChains/Altera/__init__.py +++ b/py/ToolChains/Altera/__init__.py @@ -1,16 +1,12 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; # # ============================================================================== -# Authors: Patrick Lehmann -# -# Python Sub Module: TODO: -# -# Description: -# ------------------------------------ -# TODO: +# Authors: Patrick Lehmann +# Martin Zabel # +# Python Class: TODO # # License: # ============================================================================== @@ -21,7 +17,7 @@ # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # -# http://www.apache.org/licenses/LICENSE-2.0 +# http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, @@ -30,13 +26,59 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here +# load dependencies +from ToolChains import ToolChainException, VendorConfiguration + + +__api__ = [ + 'AlteraException', + 'Configuration' +] +__all__ = __api__ + + +class AlteraException(ToolChainException): pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Repository Service Tool") +class Configuration(VendorConfiguration): + """Configuration routines for Altera as a vendor. + + This configuration provides a common installation directory setup for all + Altera tools installed on a system. + """ + _vendor = "Altera" #: The name of the tools vendor. + _section = "INSTALL.Altera" #: The name of the configuration section. Pattern: ``INSTALL.Vendor.ToolName``. + _template = { + "ALL": { + "INSTALL.Quartus": { + "SectionName": "", + "Version": "${${SectionName}:Version}", + "Edition": "${${SectionName}:Edition}", + "InstallationDirectory": "${${SectionName}:InstallationDirectory}", + "BinaryDirectory": "${${SectionName}:BinaryDirectory}" + } + }, + "Windows": { + _section: { + "InstallationDirectory": "C:/Altera" + } + }, + "Linux": { + _section: { + "InstallationDirectory": "/opt/Altera" + } + } + } #: The template for the configuration sections represented as nested dictionaries. + + def _GetDefaultInstallationDirectory(self): + """Return default installation directory (str).""" + + # altera = environ.get("QUARTUS_ROOTDIR") # on Windows: D:\Altera\13.1\quartus + # if (altera is not None): + # return str(Path(altera).parent.parent) + defaultInstallPath = self._TestDefaultInstallPath({"Windows": "Altera", "Linux": ["Altera", ""]}) + if defaultInstallPath is None: + return super()._GetDefaultInstallationDirectory() + return defaultInstallPath.as_posix() diff --git a/py/ToolChains/GHDL.py b/py/ToolChains/GHDL.py index e55a1cba..400b0a95 100644 --- a/py/ToolChains/GHDL.py +++ b/py/ToolChains/GHDL.py @@ -9,12 +9,6 @@ # # Python Class: GHDL specific classes # -# Description: -# ------------------------------------ -# TODO: -# - -# - -# # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany @@ -38,16 +32,14 @@ from re import compile as re_compile from subprocess import check_output, CalledProcessError -from lib.Functions import CallByRefParam -from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException +from lib.Functions import CallByRefParam, Init from Base.Exceptions import PlatformNotSupportedException +from Base.Logging import LogEntry, Severity from Base.Executable import Executable, LongValuedFlagArgument from Base.Executable import ExecutableArgument, PathArgument, StringArgument, ValuedFlagListArgument from Base.Executable import ShortFlagArgument, LongFlagArgument, CommandLineArgumentList -from Base.Logging import LogEntry, Severity -from Base.Simulator import PoCSimulationResultFilter, SimulationResult -from Base.ToolChain import ToolChainException -from ToolChains import ToolMixIn +from ToolChains import ToolMixIn, ToolChainException, ConfigurationException, ToolConfiguration +from Simulator import SimulationResult, PoCSimulationResultFilter __api__ = [ @@ -73,48 +65,59 @@ class GHDLReanalyzeException(GHDLException): pass -class Configuration(BaseConfiguration): - _vendor = None - _toolName = "GHDL" - _section = "INSTALL.GHDL" +class Configuration(ToolConfiguration): + _vendor = "tgingold" #: The name of the tools vendor. + _toolName = "GHDL" #: The name of the tool. + _section = "INSTALL.GHDL" #: The name of the configuration section. Pattern: ``INSTALL.Vendor.ToolName``. + _multiVersionSupport = True #: Git supports multiple versions installed on the same system. _template = { "Windows": { _section: { - "Version": "0.34dev", - "InstallationDirectory": "C:/Tools/GHDL/0.34dev", - "BinaryDirectory": "${InstallationDirectory}/bin", - "ScriptDirectory": "${InstallationDirectory}/lib/vendors", - "Backend": "mcode" + "Version": "0.34-dev", + "Backend": "mcode", + "Runtime": "gnatgpl32", + "SectionName": ("%{PathWithRoot}#${Version}-${Runtime}-${Backend}", None), + "InstallationDirectory": ("${${SectionName}:InstallationDirectory}", "C:/Tools/GHDL/${Version}-${Runtime}-${Backend}"), + "BinaryDirectory": ("${${SectionName}:BinaryDirectory}", "${InstallationDirectory}/bin"), + "ScriptDirectory": ("${${SectionName}:ScriptDirectory}", "${InstallationDirectory}/lib/vendors") } }, "Linux": { _section: { - "Version": "0.34dev", - "InstallationDirectory": "/usr/local", - "BinaryDirectory": "${InstallationDirectory}/bin", - "ScriptDirectory": "${InstallationDirectory}/lib/ghdl/vendors", - "Backend": "llvm" + "Version": "0.34-dev", + "Backend": "llvm", + "SectionName": ("%{PathWithRoot}#${Version}-${Backend}", None), + "InstallationDirectory": ("${${SectionName}:InstallationDirectory}", "/usr/local"), + "BinaryDirectory": ("${${SectionName}:BinaryDirectory}", "${InstallationDirectory}/bin"), + "ScriptDirectory": ("${${SectionName}:ScriptDirectory}", "${InstallationDirectory}/lib/ghdl/vendors") } }, "Darwin": { _section: { - "Version": "0.34dev", - "InstallationDirectory": "/usr/local", - "BinaryDirectory": "${InstallationDirectory}/bin", - "ScriptDirectory": "${InstallationDirectory}/lib/ghdl/vendors", - "Backend": "llvm" + "Version": "0.34-dev", + "Backend": "llvm", + "SectionName": ("%{PathWithRoot}#${Version}-${Backend}", None), + "InstallationDirectory": ("${${SectionName}:InstallationDirectory}", "/usr/local"), + "BinaryDirectory": ("${${SectionName}:BinaryDirectory}", "${InstallationDirectory}/bin"), + "ScriptDirectory": ("${${SectionName}:ScriptDirectory}", "${InstallationDirectory}/lib/ghdl/vendors") } } - } + } #: The template for the configuration sections represented as nested dictionaries. def ConfigureForAll(self): try: if (not self._AskInstalled("Is GHDL installed on your system?")): self.ClearSection() else: + # Configure GHDL version + if self._multiVersionSupport: + self.PrepareVersionedSections() + self._ConfigureInstallationDirectory() binPath = self._ConfigureBinaryDirectory() + self.__WriteGHDLSection(binPath) + self._host.LogNormal("{DARK_GREEN}GHDL is now configured.{NOCOLOR}".format(**Init.Foreground), indent=1) except ConfigurationException: self.ClearSection() raise @@ -136,8 +139,8 @@ def _ConfigureBinaryDirectory(self): def _ConfigureScriptDirectory(self): """Updates section with value from _template and returns directory as Path object.""" - unresolved = self._template[self._host.Platform][self._section]['ScriptDirectory'] - self._host.PoCConfig[self._section]['ScriptDirectory'] = unresolved # create entry + # unresolved = self._template[self._host.Platform][self._section]['ScriptDirectory'] + # self._host.PoCConfig[self._section]['ScriptDirectory'] = unresolved # create entry scriptPath = Path(self._host.PoCConfig[self._section]['ScriptDirectory']) # resolve entry if (not scriptPath.exists()): @@ -264,6 +267,18 @@ class FlagSynBinding(metaclass=LongFlagArgument): class FlagPSL(metaclass=ShortFlagArgument): _name = "fpsl" + class SwitchCompilerOption(metaclass=ValuedFlagListArgument): + _pattern = "-{0},{1}" + _name = "Wc" + + class SwitchAssemblerOption(metaclass=ValuedFlagListArgument): + _pattern = "-{0},{1}" + _name = "Wa" + + class SwitchLinkerOption(metaclass=ValuedFlagListArgument): + _pattern = "-{0},{1}" + _name = "Wl" + class SwitchIEEEFlavor(metaclass=LongValuedFlagArgument): _name = "ieee" @@ -296,6 +311,9 @@ class ArgTopLevel(metaclass=StringArgument): FlagMultiByteComments, FlagSynBinding, FlagPSL, + SwitchCompilerOption, + SwitchAssemblerOption, + SwitchLinkerOption, SwitchIEEEFlavor, SwitchVHDLVersion, SwitchVHDLLibrary, diff --git a/py/ToolChains/GNU.py b/py/ToolChains/GNU.py index 44526e3b..3a0648b9 100644 --- a/py/ToolChains/GNU.py +++ b/py/ToolChains/GNU.py @@ -6,13 +6,7 @@ # Authors: Patrick Lehmann # Martin Zabel # -# Python Class: GNU tools specific classes -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Class: GNU tools specific classes # # License: # ============================================================================== @@ -35,12 +29,12 @@ # load dependencies import re +from lib.Functions import Init, CallByRefParam from Base.Exceptions import PlatformNotSupportedException from Base.Executable import Executable, ExecutableArgument, CommandLineArgumentList, ValuedFlagArgument from Base.Logging import LogEntry, Severity -from Base.Simulator import SimulationResult -from Base.ToolChain import ToolChainException -from lib.Functions import Init, CallByRefParam +from Simulator import SimulationResult +from ToolChains import ToolChainException __api__ = [ diff --git a/py/ToolChains/GTKWave.py b/py/ToolChains/GTKWave.py index 31f873b1..fe10a054 100644 --- a/py/ToolChains/GTKWave.py +++ b/py/ToolChains/GTKWave.py @@ -7,13 +7,7 @@ # Martin Zabel # Thomas B. Preusser # -# Python Class: GTKWave specific classes -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Class: GTKWave specific classes # # License: # ============================================================================== @@ -34,15 +28,15 @@ # ============================================================================== # # load dependencies -from pathlib import Path -from re import compile as RegExpCompile -from subprocess import check_output, CalledProcessError +from pathlib import Path +from re import compile as re_compile +from subprocess import check_output, CalledProcessError -from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException -from Base.Exceptions import PlatformNotSupportedException -from Base.Executable import Executable, ExecutableArgument, LongValuedFlagArgument, CommandLineArgumentList -from Base.Logging import LogEntry, Severity -from Base.ToolChain import ToolChainException +from lib.Functions import Init +from Base.Exceptions import PlatformNotSupportedException +from Base.Logging import LogEntry, Severity +from Base.Executable import Executable, ExecutableArgument, LongValuedFlagArgument, CommandLineArgumentList +from ToolChains import ToolChainException, ConfigurationException, ToolConfiguration __api__ = [ @@ -59,33 +53,37 @@ class GTKWaveException(ToolChainException): pass -class Configuration(BaseConfiguration): - _vendor = None - _toolName = "GTKWave" - _section = "INSTALL.GTKWave" +class Configuration(ToolConfiguration): + _vendor = "TonyBybell" #: The name of the tools vendor. + _toolName = "GTKWave" #: The name of the tool. + _section = "INSTALL.GTKWave" #: The name of the configuration section. Pattern: ``INSTALL.Vendor.ToolName``. + _multiVersionSupport = True #: GTKWave supports multiple versions installed on the same system. _template = { "Windows": { _section: { - "Version": "3.3.71", - "InstallationDirectory": "C:/Program Files (x86)/GTKWave", - "BinaryDirectory": "${InstallationDirectory}/bin" + "Version": "3.3.78", + "SectionName": ("%{PathWithRoot}#${Version}", None), + "InstallationDirectory": ("${${SectionName}:InstallationDirectory}", "C:/Program Files (x86)/GTKWave"), + "BinaryDirectory": ("${${SectionName}:BinaryDirectory}", "${InstallationDirectory}/bin") } }, "Linux": { _section: { - "Version": "3.3.71", - "InstallationDirectory": "/usr/bin", - "BinaryDirectory": "${InstallationDirectory}" + "Version": "3.3.78", + "SectionName": ("%{PathWithRoot}#${Version}", None), + "InstallationDirectory": ("${${SectionName}:InstallationDirectory}", "/usr/bin"), + "BinaryDirectory": ("${${SectionName}:BinaryDirectory}", "${InstallationDirectory}") } }, "Darwin": { _section: { - "Version": "3.3.71", - "InstallationDirectory": "/usr/bin", - "BinaryDirectory": "${InstallationDirectory}" + "Version": "3.3.78", + "SectionName": ("%{PathWithRoot}#${Version}", None), + "InstallationDirectory": ("${${SectionName}:InstallationDirectory}", "/usr/bin"), + "BinaryDirectory": ("${${SectionName}:BinaryDirectory}", "${InstallationDirectory}") } } - } + } #: The template for the configuration sections represented as nested dictionaries. def CheckDependency(self): # return True if Xilinx is configured @@ -96,9 +94,17 @@ def ConfigureForAll(self): if (not self._AskInstalled("Is GTKWave installed on your system?")): self.ClearSection() else: + # Configure GTKWave version + version = "3.3.78" + if self._multiVersionSupport: + self.PrepareVersionedSections() + sectionName = self._host.PoCConfig[self._section]['SectionName'] + self._host.PoCConfig[sectionName]['Version'] = version + self._ConfigureInstallationDirectory() binPath = self._ConfigureBinaryDirectory() self.__WriteGtkWaveSection(binPath) + self._host.LogNormal("{DARK_GREEN}GTKWave is now configured.{NOCOLOR}".format(**Init.Foreground), indent=1) except ConfigurationException: self.ClearSection() raise @@ -127,7 +133,7 @@ def __WriteGtkWaveSection(self, binPath): output = check_output([str(gtkwPath), "--version"], universal_newlines=True) version = None versionRegExpStr = r"^GTKWave Analyzer v(.+?) " - versionRegExp = RegExpCompile(versionRegExpStr) + versionRegExp = re_compile(versionRegExpStr) for line in output.split('\n'): if version is None: match = versionRegExp.match(line) diff --git a/py/ToolChains/Git.py b/py/ToolChains/Git.py index cabf66e0..1a0b02a2 100644 --- a/py/ToolChains/Git.py +++ b/py/ToolChains/Git.py @@ -7,13 +7,7 @@ # Martin Zabel # Thomas B. Preusser # -# Python Class: Git specific classes -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Class: Git specific classes # # License: # ============================================================================== @@ -40,12 +34,11 @@ from os import environ from shutil import copy as shutil_copy +from lib.Functions import Init from Base.Exceptions import PlatformNotSupportedException, CommonException -from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException, SkipConfigurationException from Base.Executable import Executable, ExecutableArgument, CommandLineArgumentList from Base.Executable import CommandArgument, LongFlagArgument, ValuedFlagArgument, StringArgument, LongValuedFlagArgument, LongTupleArgument -from Base.ToolChain import ToolChainException -from ToolChains import ToolMixIn +from ToolChains import ToolMixIn, ToolChainException, ConfigurationException, SkipConfigurationException, ChangeState, ToolConfiguration __api__ = [ @@ -65,10 +58,10 @@ class GitException(ToolChainException): pass -class Configuration(BaseConfiguration): - _vendor = "Git SCM" - _toolName = "Git" - _section = "INSTALL.Git" +class Configuration(ToolConfiguration): + _vendor = "Git SCM" #: The name of the tools vendor. + _toolName = "Git" #: The name of the tool. + _section = "INSTALL.Git" #: The name of the configuration section. Pattern: ``INSTALL.Vendor.ToolName``. _template = { "Windows": { _section: { @@ -84,7 +77,7 @@ class Configuration(BaseConfiguration): "BinaryDirectory": "${InstallationDirectory}" } } - } + } #: The template for the configuration sections represented as nested dictionaries. def __init__(self, host): super().__init__(host) @@ -96,7 +89,10 @@ def ConfigureForAll(self): if (not self._AskInstalled("Is Git installed on your system?")): self.ClearSection() else: + # Configure Git version self._host.PoCConfig[self._section]['Version'] = self._template[self._host.Platform][self._section]['Version'] + + self._ConfigureInstallationDirectory() binPath = self._ConfigureBinaryDirectory() self.__WriteGitSection(binPath) @@ -105,7 +101,8 @@ def ConfigureForAll(self): raise if (len(self._host.PoCConfig['INSTALL.Git']) == 0): - self._host.LogNormal(" Skipping Git setup. Not Git installation found.") + self._host.LogNormal("Skipping further Git setup. No Git installation found.", indent=1) + self._host.LogNormal("{DARK_GREEN}Git is now configured.{NOCOLOR}".format(**Init.Foreground), indent=1) return try: @@ -115,18 +112,30 @@ def ConfigureForAll(self): self._host.LogWarning(str(ex)) if (not self.__IsUnderGitControl()): - self._host.LogNormal("Skipping Git setup. This directory is not under Git control.") + self._host.LogNormal("Skipping Git setup. This directory is not under Git control.", indent=1) + self._host.LogNormal("{DARK_GREEN}Git is now configured.{NOCOLOR}".format(**Init.Foreground), indent=1) return - if (not self._AskDoInstall("Install Git mechanisms for PoC developers?")): - self.__UninstallGitFilters() - self.__UninstallGitHooks() - return + try: + if (not self._AskYes_NoPass("Install Git mechanisms for PoC developers?")): + self._changed = ChangeState.Changed + self._host.PoCConfig[self._section]['HasInstalledGitFilters'] = "True" + self._host.PoCConfig[self._section]['HasInstalledGitHooks'] = "True" + self._host.LogNormal("{DARK_GREEN}Git is now configured.{NOCOLOR}".format(**Init.Foreground), indent=1) + return + except SkipConfigurationException: + self._host.LogNormal("{DARK_GREEN}Git is now configured.{NOCOLOR}".format(**Init.Foreground), indent=1) + raise if (self._AskInstalled("Install Git filters?")): - self.__InstallGitFilters() + self._changed = ChangeState.Changed + self._host.PoCConfig[self._section]['HasInstalledGitFilters'] = "True" + if (self._AskInstalled("Install Git hooks?")): - self.__InstallGitHooks() + self._changed = ChangeState.Changed + self._host.PoCConfig[self._section]['HasInstalledGitHooks'] = "True" + + self._host.LogNormal("{DARK_GREEN}Git is now configured.{NOCOLOR}".format(**Init.Foreground), indent=1) def _GetDefaultInstallationDirectory(self): if (self._host.Platform == "Windows"): @@ -147,17 +156,18 @@ def _GetDefaultInstallationDirectory(self): return super()._GetDefaultInstallationDirectory() - def _AskDoInstall(self, question): - isInstalled = input(" " + question + " [y/N/p]: ") - isInstalled = isInstalled if isInstalled != "" else "N" - if (isInstalled in ['p', 'P']): - raise SkipConfigurationException() - elif (isInstalled in ['n', 'N']): - return False - elif (isInstalled in ['y', 'Y']): - return True - else: - raise ConfigurationException("Unsupported choice '{0}'".format(isInstalled)) + def RunPostConfigurationTasks(self): + if self._changed is ChangeState.Changed: + pocSection = self._host.PoCConfig[self._section] + if pocSection['HasInstalledGitFilters']: + self.__InstallGitFilters() + else: + self.__UninstallGitFilters() + + if pocSection['HasInstalledGitHooks']: + self.__InstallGitHooks() + else: + self.__UninstallGitHooks() def __WriteGitSection(self, binPath): if (self._host.Platform == "Windows"): diff --git a/py/ToolChains/Intel/ModelSim.py b/py/ToolChains/Intel/ModelSim.py new file mode 100644 index 00000000..a880201d --- /dev/null +++ b/py/ToolChains/Intel/ModelSim.py @@ -0,0 +1,147 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# Martin Zabel +# Thomas B. Preusser +# +# Python Class: Intel ModelSim specific classes +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair of VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +# +# load dependencies +from enum import unique +from re import compile as re_compile +from subprocess import check_output + +from lib.Functions import Init +from ToolChains import ConfigurationException, EditionDescription, Edition +from ToolChains.Mentor.ModelSim import ModelSimException as Mentor_ModelSimException, Configuration as Mentor_ModelSim_Configuration +from ToolChains.Intel import IntelException + + +__api__ = [ + 'ModelSimException', + 'IntelModelSimEditions', + 'Configuration' +] +__all__ = __api__ + + +class ModelSimException(IntelException, Mentor_ModelSimException): + pass + + +@unique +class IntelModelSimEditions(Edition): + ModelSimIntelEdition = EditionDescription(Name="ModelSim Intel Edition", Section=None) + ModelSimIntelStarterEdition = EditionDescription(Name="ModelSim Intel Starter Edition", Section=None) + + +class Configuration(Mentor_ModelSim_Configuration): + _vendor = "Intel" #: The name of the tools vendor. + _toolName = "Intel ModelSim" #: The name of the tool. + _section = "INSTALL.Intel.ModelSim" #: The name of the configuration section. Pattern: ``INSTALL.Vendor.ToolName``. + _template = { + "Windows": { + _section: { + "Version": "10.5b", + "Edition": "ModelSim Intel Edition", + "InstallationDirectory": "${INSTALL.Intel:InstallationDirectory}/${INSTALL.Intel.Quartus:Version}/modelsim_ae", # _ase + "BinaryDirectory": "${InstallationDirectory}/win32aloem" + } + }, + "Linux": { + _section: { + "Version": "10.5b", + "Edition": "ModelSim Intel Edition", + "InstallationDirectory": "${INSTALL.Intel:InstallationDirectory}/${INSTALL.Intel.Quartus:Version}/modelsim_ae", + "BinaryDirectory": "${InstallationDirectory}/linuxaloem" + } + } + } #: The template for the configuration sections represented as nested dictionaries. + + def CheckDependency(self): + """Check if general Intel support is configured in PoC.""" + return (len(self._host.PoCConfig['INSTALL.Intel']) != 0) + + def ConfigureForAll(self): + try: + if (not self._AskInstalled("Is ModelSim Intel Edition installed on your system?")): + self.ClearSection() + else: + # Configure ModelSim version + edition = self._ConfigureEdition() + + + configSection = self._host.PoCConfig[self._section] + if (edition is IntelModelSimEditions.ModelSimIntelEdition): + configSection['InstallationDirectory'] = self._host.PoCConfig.get(self._section, 'InstallationDirectory', raw=True).replace("_ase", "_ae") + elif (edition is IntelModelSimEditions.ModelSimIntelStarterEdition): + configSection['InstallationDirectory'] = self._host.PoCConfig.get(self._section, 'InstallationDirectory', raw=True).replace("_ase", "_ase") + + self._ConfigureInstallationDirectory() + binPath = self._ConfigureBinaryDirectory() + self.__GetModelSimVersion(binPath) + self._host.LogNormal("{DARK_GREEN}Intel ModelSim is now configured.{NOCOLOR}".format(**Init.Foreground), indent=1) + except ConfigurationException: + self.ClearSection() + raise + + def _ConfigureEdition(self): + """Configure ModelSim for Intel.""" + configSection = self._host.PoCConfig[self._section] + defaultEdition = IntelModelSimEditions.Parse(configSection['Edition']) + edition = super()._ConfigureEdition(IntelModelSimEditions, defaultEdition) + + if (edition is not defaultEdition): + configSection['Edition'] = edition.Name + self._host.PoCConfig.Interpolation.clear_cache() + return (True, edition) + else: + return (False, edition) + + def __GetModelSimVersion(self, binPath): + if (self._host.Platform == "Windows"): + vsimPath = binPath / "vsim.exe" + else: + vsimPath = binPath / "vsim" + + if not vsimPath.exists(): + raise ConfigurationException("Executable '{0!s}' not found.".format(vsimPath)) \ + from FileNotFoundError(str(vsimPath)) + + # get version and backend + try: + output = check_output([str(vsimPath), "-version"], universal_newlines=True) + except OSError as ex: + raise ConfigurationException("Error while accessing '{0!s}'.".format(vsimPath)) from ex + + version = None + versionRegExpStr = r"^.* vsim (.+?) " + versionRegExp = re_compile(versionRegExpStr) + for line in output.split('\n'): + if version is None: + match = versionRegExp.match(line) + if match is not None: + version = match.group(1) + + self._host.PoCConfig[self._section]['Version'] = version diff --git a/py/ToolChains/Intel/Quartus.py b/py/ToolChains/Intel/Quartus.py new file mode 100644 index 00000000..3e9f1558 --- /dev/null +++ b/py/ToolChains/Intel/Quartus.py @@ -0,0 +1,126 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# Martin Zabel +# +# Python Class: Intel Quartus specific classes +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair of VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +# +# load dependencies +from subprocess import check_output, STDOUT + +from ToolChains import ConfigurationException +from ToolChains.Altera.Quartus import QuartusException as Altera_QuartusException, Configuration as Altera_Quartus_Configuration, Quartus as Altera_Quartus, Map as Altera_Quartus_Map +from ToolChains.Intel import IntelException +from lib.Functions import Init + + +__api__ = [ + 'QuartusException', + 'Configuration', + 'Quartus', + 'Map' +] +__all__ = __api__ + + +class QuartusException(IntelException, Altera_QuartusException): + pass + + +class Configuration(Altera_Quartus_Configuration): + _vendor = "Intel" #: The name of the tools vendor. + _toolName = "Intel Quartus" #: The name of the tool. + _section = "INSTALL.Intel.Quartus" #: The name of the configuration section. Pattern: ``INSTALL.Vendor.ToolName``. + _multiVersionSupport = True #: Intel Quartus supports multiple versions installed on the same system. + _template = { + "Windows": { + _section: { + "Version": "16.1", + "SectionName": ("%{PathWithRoot}#${Version}", None), + "InstallationDirectory": ("${${SectionName}:InstallationDirectory}", "${INSTALL.Intel:InstallationDirectory}/${Version}/quartus"), + "BinaryDirectory": ("${${SectionName}:BinaryDirectory}", "${InstallationDirectory}/bin64") + } + }, + "Linux": { + _section: { + "Version": "16.1", + "SectionName": ("%{PathWithRoot}#${Version}", None), + "InstallationDirectory": ("${${SectionName}:InstallationDirectory}", "${INSTALL.Intel:InstallationDirectory}/${Version}/quartus"), + "BinaryDirectory": ("${${SectionName}:BinaryDirectory}", "${InstallationDirectory}/bin") + } + } + } #: The template for the configuration sections represented as nested dictionaries. + + def CheckDependency(self): + """Check if general Intel support is configured in PoC.""" + return (len(self._host.PoCConfig['INSTALL.Intel']) != 0) + + def ConfigureForAll(self): + try: + if (not self._AskInstalled("Is Intel Quartus Prime installed on your system?")): + self.ClearSection() + else: + # Configure Quartus version + version = self._ConfigureVersion() + if self._multiVersionSupport: + self.PrepareVersionedSections() + sectionName = self._host.PoCConfig[self._section]['SectionName'] + self._host.PoCConfig[sectionName]['Version'] = version + + self._ConfigureInstallationDirectory() + binPath = self._ConfigureBinaryDirectory() + + self.LogNormal("Checking Altera Quartus version... (this may take a few seconds)", indent=1) + self.__CheckQuartusVersion(binPath, version) + + self._host.LogNormal("{DARK_GREEN}Intel Quartus Prime is now configured.{NOCOLOR}".format(**Init.Foreground), indent=1) + except ConfigurationException: + self.ClearSection() + raise + + def __CheckQuartusVersion(self, binPath, version): + if (self._host.Platform == "Windows"): + quartusPath = binPath / "quartus_sh.exe" + else: + quartusPath = binPath / "quartus_sh" + + if not quartusPath.exists(): + raise ConfigurationException("Executable '{0!s}' not found.".format(quartusPath)) from FileNotFoundError( + str(quartusPath)) + + output = check_output([str(quartusPath), "-v"], universal_newlines=True, stderr=STDOUT) + if "Version {0}".format(version) not in output: + raise ConfigurationException("Quartus version mismatch. Expected version {0}.".format(version)) + + +class Quartus(Altera_Quartus): + def GetMap(self): + return Map(self) + + # def GetTclShell(self): + # return TclShell(self) + + +class Map(Altera_Quartus_Map): + pass diff --git a/py/ToolChains/Aldec/Aldec.py b/py/ToolChains/Intel/__init__.py similarity index 58% rename from py/ToolChains/Aldec/Aldec.py rename to py/ToolChains/Intel/__init__.py index 22147bf0..b27df3a0 100644 --- a/py/ToolChains/Aldec/Aldec.py +++ b/py/ToolChains/Intel/__init__.py @@ -4,15 +4,8 @@ # # ============================================================================== # Authors: Patrick Lehmann -# Martin Zabel # -# Python Class: TODO -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Class: TODO # # License: # ============================================================================== @@ -33,39 +26,46 @@ # ============================================================================== # # load dependencies -from Base.Configuration import Configuration as BaseConfiguration -from Base.ToolChain import ToolChainException +from ToolChains import ToolChainException, VendorConfiguration __api__ = [ - 'AldecException', + 'IntelException', 'Configuration' ] __all__ = __api__ -class AldecException(ToolChainException): +class IntelException(ToolChainException): pass -class Configuration(BaseConfiguration): - _vendor = "Aldec" - _toolName = None # automatically configure only vendor path - _section = "INSTALL.Aldec" +class Configuration(VendorConfiguration): + """Configuration routines for Intel as a vendor. + + This configuration provides a common installation directory setup for all + Intel tools installed on a system. + """ + _vendor = "Intel" #: The name of the tools vendor. + _section = "INSTALL.Intel" #: The name of the configuration section. Pattern: ``INSTALL.Vendor.ToolName``. _template = { "Windows": { _section: { - "InstallationDirectory": "C:/Aldec" + "InstallationDirectory": "C:/IntelFPGA" } }, "Linux": { _section: { - "InstallationDirectory": "/opt/Aldec" + "InstallationDirectory": "/opt/Intel" } } - } + } #: The template for the configuration sections represented as nested dictionaries. def _GetDefaultInstallationDirectory(self): - path = self._TestDefaultInstallPath({"Windows": "Aldec", "Linux": "Aldec"}) + # Intel = environ.get("QUARTUS_ROOTDIR") # on Windows: D:\IntelFPGA\16.1\quartus + # if (Intel is not None): + # return str(Path(Intel).parent.parent) + + path = self._TestDefaultInstallPath({"Windows": "IntelFPGA", "Linux": "Intel"}) if path is None: return super()._GetDefaultInstallationDirectory() return path.as_posix() diff --git a/py/ToolChains/Lattice/ActiveHDL.py b/py/ToolChains/Lattice/ActiveHDL.py index b1383dcc..6de2bd2e 100644 --- a/py/ToolChains/Lattice/ActiveHDL.py +++ b/py/ToolChains/Lattice/ActiveHDL.py @@ -6,13 +6,7 @@ # Authors: Patrick Lehmann # Martin Zabel # -# Python Class: Lattice Active-HDL specific classes -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Class: Lattice Active-HDL specific classes # # License: # ============================================================================== @@ -33,39 +27,34 @@ # ============================================================================== # # load dependencies -from subprocess import check_output +from subprocess import check_output -from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException -from ToolChains.Lattice.Lattice import LatticeException +from lib.Functions import Init +from ToolChains import ConfigurationException +from ToolChains.Lattice import LatticeException +from ToolChains.Aldec.ActiveHDL import Configuration as ActiveHDL_Configuration, ActiveHDLException as Aldec_ActiveHDL_ActiveHDLException -class ActiveHDLException(LatticeException): +class ActiveHDLException(LatticeException, Aldec_ActiveHDL_ActiveHDLException): pass -class Configuration(BaseConfiguration): - _vendor = "Lattice" - _toolName = "Active-HDL Lattice Edition" - _section = "INSTALL.Lattice.ActiveHDL" +class Configuration(ActiveHDL_Configuration): + _vendor = "Lattice" #: The name of the tools vendor. + _toolName = "Active-HDL Lattice Edition" #: The name of the tool. + _section = "INSTALL.Lattice.ActiveHDL" #: The name of the configuration section. Pattern: ``INSTALL.Vendor.ToolName``. _template = { "Windows": { _section: { - "Version": "10.2", + "Version": "10.3", "InstallationDirectory": "${INSTALL.Lattice.Diamond:InstallationDirectory}/active-hdl", "BinaryDirectory": "${InstallationDirectory}/BIN" } - }, - "Linux": { - _section: { - # "Version": "15.0", - # "InstallationDirectory": "${INSTALL.Lattice:InstallationDirectory}/${Version}/activeHDL", - # "BinaryDirectory": "${InstallationDirectory}/fix_me" - } } - } + } #: The template for the configuration sections represented as nested dictionaries. def CheckDependency(self): - # return True if Lattice is configured + """Check if Lattice Diamond support is configured in PoC.""" return (len(self._host.PoCConfig['INSTALL.Lattice.Diamond']) != 0) def ConfigureForAll(self): @@ -73,10 +62,14 @@ def ConfigureForAll(self): if (not self._AskInstalled("Is Aldec Active-HDL installed on your system?")): self.ClearSection() else: + # Configure Active-HDL version version = self._ConfigureVersion() + + self._ConfigureInstallationDirectory() binPath = self._ConfigureBinaryDirectory() self.__CheckActiveHDLVersion(binPath, version) + self._host.LogNormal("{DARK_GREEN}Lattice Active-HDL is now configured.{NOCOLOR}".format(**Init.Foreground), indent=1) except ConfigurationException: self.ClearSection() raise diff --git a/py/ToolChains/Lattice/Diamond.py b/py/ToolChains/Lattice/Diamond.py index 55c023e3..7c263808 100644 --- a/py/ToolChains/Lattice/Diamond.py +++ b/py/ToolChains/Lattice/Diamond.py @@ -6,13 +6,7 @@ # Authors: Patrick Lehmann # Martin Zabel # -# Python Class: Lattice Diamond specific classes -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Class: Lattice Diamond specific classes # # License: # ============================================================================== @@ -35,16 +29,16 @@ # load dependencies import time -from pathlib import Path -from subprocess import check_output, CalledProcessError, STDOUT +from pathlib import Path +from subprocess import check_output, CalledProcessError, STDOUT -from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException -from Base.Exceptions import PlatformNotSupportedException -from Base.Executable import Executable, CommandLineArgumentList, ExecutableArgument, ShortTupleArgument -from Base.Logging import Severity, LogEntry -from Base.Project import File, FileTypes, VHDLVersion -from ToolChains import ToolMixIn -from ToolChains.Lattice.Lattice import LatticeException +from lib.Functions import Init +from Base.Exceptions import PlatformNotSupportedException +from Base.Logging import Severity, LogEntry +from Base.Executable import Executable, CommandLineArgumentList, ExecutableArgument, ShortTupleArgument +from Base.Project import File, FileTypes, VHDLVersion +from ToolChains import ToolMixIn, ConfigurationException, ToolConfiguration +from ToolChains.Lattice import LatticeException __api__ = [ @@ -63,31 +57,34 @@ class DiamondException(LatticeException): pass -class Configuration(BaseConfiguration): - _vendor = "Lattice" - _toolName = "Lattice Diamond" - _section = "INSTALL.Lattice.Diamond" +class Configuration(ToolConfiguration): + _vendor = "Lattice" #: The name of the tools vendor. + _toolName = "Lattice Diamond" #: The name of the tool. + _section = "INSTALL.Lattice.Diamond" #: The name of the configuration section. Pattern: ``INSTALL.Vendor.ToolName``. + _multiVersionSupport = True #: Lattice Diamond supports multiple versions installed on the same system. _template = { "Windows": { _section: { - "Version": "3.7", - "InstallationDirectory": "${INSTALL.Lattice:InstallationDirectory}/Diamond/${Version}_x64", - "BinaryDirectory": "${InstallationDirectory}/bin/nt64", - "BinaryDirectory2": "${InstallationDirectory}/ispfpga/bin/nt64" + "Version": "3.8", + "SectionName": ("%{PathWithRoot}#${Version}", None), + "InstallationDirectory": ("${${SectionName}:InstallationDirectory}", "${INSTALL.Lattice:InstallationDirectory}/Diamond/${Version}_x64"), + "BinaryDirectory": ("${${SectionName}:BinaryDirectory}", "${InstallationDirectory}/bin/nt64"), + "BinaryDirectory2": ("${${SectionName}:BinaryDirectory2}", "${InstallationDirectory}/ispfpga/bin/nt64") } }, "Linux": { _section: { - "Version": "3.7", - "InstallationDirectory": "${INSTALL.Lattice:InstallationDirectory}/diamond/${Version}_x64", - "BinaryDirectory": "${InstallationDirectory}/bin/lin64", - "BinaryDirectory2": "${InstallationDirectory}/ispfpga/bin/lin64" + "Version": "3.8", + "SectionName": ("%{PathWithRoot}#${Version}", None), + "InstallationDirectory": ("${${SectionName}:InstallationDirectory}", "${INSTALL.Lattice:InstallationDirectory}/diamond/${Version}_x64"), + "BinaryDirectory": ("${${SectionName}:BinaryDirectory}", "${InstallationDirectory}/bin/lin64"), + "BinaryDirectory2": ("${${SectionName}:BinaryDirectory2}", "${InstallationDirectory}/ispfpga/bin/lin64") } } - } + } #: The template for the configuration sections represented as nested dictionaries. def CheckDependency(self): - # return True if Lattice is configured + """Check if general Lattice support is configured in PoC.""" return (len(self._host.PoCConfig['INSTALL.Lattice']) != 0) def ConfigureForAll(self): @@ -95,10 +92,17 @@ def ConfigureForAll(self): if (not self._AskInstalled("Is Lattice Diamond installed on your system?")): self.ClearSection() else: + # Configure Diamond version version = self._ConfigureVersion() + if self._multiVersionSupport: + self.PrepareVersionedSections() + sectionName = self._host.PoCConfig[self._section]['SectionName'] + self._host.PoCConfig[sectionName]['Version'] = version + self._ConfigureInstallationDirectory() binPath = self._ConfigureBinaryDirectory() self.__CheckDiamondVersion(binPath, version) + self._host.LogNormal("{DARK_GREEN}Lattice Diamond is now configured.{NOCOLOR}".format(**Init.Foreground), indent=1) except ConfigurationException: self.ClearSection() raise @@ -127,8 +131,8 @@ def __CheckDiamondVersion(self, binPath, version): def _ConfigureBinaryDirectory(self): """Updates section with value from _template and returns directory as Path object.""" binPath = super()._ConfigureBinaryDirectory() - unresolved = self._template[self._host.Platform][self._section]['BinaryDirectory2'] - self._host.PoCConfig[self._section]['BinaryDirectory2'] = unresolved # create entry + # unresolved = self._template[self._host.Platform][self._section]['BinaryDirectory2'] + # self._host.PoCConfig[self._section]['BinaryDirectory2'] = unresolved # create entry defaultPath = Path(self._host.PoCConfig[self._section]['BinaryDirectory2']) # resolve entry binPath2 = defaultPath # may be more complex in the future @@ -182,7 +186,7 @@ class SwitchProjectFile(metaclass=ShortTupleArgument): def GetLogFileReader(self, logFile): while True: if logFile.exists(): break - time.sleep(5) # XXX: implement a 'tail -f' functionality + time.sleep(5) # FIXME: implement a 'tail -f' functionality with logFile.open('r') as logFileHandle: for line in logFileHandle: diff --git a/py/ToolChains/Lattice/Lattice.py b/py/ToolChains/Lattice/Lattice.py deleted file mode 100644 index 27a41401..00000000 --- a/py/ToolChains/Lattice/Lattice.py +++ /dev/null @@ -1,82 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# -# ============================================================================== -# Authors: Patrick Lehmann -# Martin Zabel -# -# Python Class: Lattice Diamond specific classes -# -# Description: -# ------------------------------------ -# TODO: -# - -# - -# -# License: -# ============================================================================== -# Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair of VLSI-Design, Diagnostics and Architecture -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# ============================================================================== -# -# load dependencies -from Base.Configuration import Configuration as BaseConfiguration -from Base.Project import ConstraintFile, FileTypes -from Base.ToolChain import ToolChainException - - -__api__ = [ - 'LatticeException', - 'Configuration', - 'LatticeDesignConstraintFile' -] -__all__ = __api__ - - -class LatticeException(ToolChainException): - pass - - -class Configuration(BaseConfiguration): - _vendor = "Lattice" - _toolName = None # automatically configure only vendor path - _section = "INSTALL.Lattice" - _template = { - "Windows": { - _section: { - "InstallationDirectory": "C:/Lattice" - } - }, - "Linux": { - _section: { - "InstallationDirectory": "/usr/local" - } - } - } - - def _GetDefaultInstallationDirectory(self): - path = self._TestDefaultInstallPath({"Windows": "Lattice", "Linux": "lattice"}) - if path is None: return super()._GetDefaultInstallationDirectory() - return path.as_posix() - - -class LatticeDesignConstraintFile(ConstraintFile): - _FileType = FileTypes.LdcConstraintFile - - def __str__(self): - return "LDC file: '{0!s}".format(self._file) - - diff --git a/py/ToolChains/Lattice/Synplify.py b/py/ToolChains/Lattice/Synplify.py index 5410d382..7d8b2ee9 100644 --- a/py/ToolChains/Lattice/Synplify.py +++ b/py/ToolChains/Lattice/Synplify.py @@ -5,13 +5,7 @@ # ============================================================================== # Authors: Patrick Lehmann # -# Python Class: Lattice Synopsys specific classes -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Class: Lattice Synopsys specific classes # # License: # ============================================================================== @@ -32,8 +26,7 @@ # ============================================================================== # # load dependencies -from Base.Configuration import Configuration as BaseConfiguration -from Base.ToolChain import ToolChainException +from ToolChains import ToolChainException, ToolConfiguration __api__ = [ @@ -47,6 +40,6 @@ class SynplifyException(ToolChainException): pass -class Configuration(BaseConfiguration): +class Configuration(ToolConfiguration): def __init__(self, host): super().__init__(host) diff --git a/py/ToolChains/Lattice/__init__.py b/py/ToolChains/Lattice/__init__.py index 896b9579..039d0884 100644 --- a/py/ToolChains/Lattice/__init__.py +++ b/py/ToolChains/Lattice/__init__.py @@ -1,16 +1,12 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; # # ============================================================================== -# Authors: Patrick Lehmann -# -# Python Sub Module: TODO: -# -# Description: -# ------------------------------------ -# TODO: +# Authors: Patrick Lehmann +# Martin Zabel # +# Python Class: Lattice Diamond specific classes # # License: # ============================================================================== @@ -21,7 +17,7 @@ # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # -# http://www.apache.org/licenses/LICENSE-2.0 +# http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, @@ -30,13 +26,52 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here +# load dependencies +from Base.Project import ConstraintFile, FileTypes +from ToolChains import ToolChainException, VendorConfiguration + + +__api__ = [ + 'LatticeException', + 'Configuration', + 'LatticeDesignConstraintFile' +] +__all__ = __api__ + + +class LatticeException(ToolChainException): pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Repository Service Tool") +class Configuration(VendorConfiguration): + """Configuration routines for Lattice as a vendor. + + This configuration provides a common installation directory setup for all + Lattice tools installed on a system. + """ + _vendor = "Lattice" #: The name of the tools vendor. + _section = "INSTALL.Lattice" #: The name of the configuration section. Pattern: ``INSTALL.Vendor.ToolName``. + _template = { + "Windows": { + _section: { + "InstallationDirectory": "C:/Lattice" + } + }, + "Linux": { + _section: { + "InstallationDirectory": "/usr/local" + } + } + } #: The template for the configuration sections represented as nested dictionaries. + + def _GetDefaultInstallationDirectory(self): + path = self._TestDefaultInstallPath({"Windows": "Lattice", "Linux": "lattice"}) + if path is None: return super()._GetDefaultInstallationDirectory() + return path.as_posix() + + +class LatticeDesignConstraintFile(ConstraintFile): + _FileType = FileTypes.LdcConstraintFile + def __str__(self): + return "LDC file: '{0!s}".format(self._file) diff --git a/py/ToolChains/Mentor/Mentor.py b/py/ToolChains/Mentor/Mentor.py deleted file mode 100644 index 9f74a37f..00000000 --- a/py/ToolChains/Mentor/Mentor.py +++ /dev/null @@ -1,71 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# -# ============================================================================== -# Authors: Patrick Lehmann -# Martin Zabel -# -# Python Class: Mentor specific classes -# -# Description: -# ------------------------------------ -# TODO: -# - -# - -# -# License: -# ============================================================================== -# Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair of VLSI-Design, Diagnostics and Architecture -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# ============================================================================== -# -# load dependencies -from Base.Configuration import Configuration as BaseConfiguration -from Base.ToolChain import ToolChainException - - -__api__ = [ - 'MentorException', - 'Configuration' -] -__all__ = __api__ - - -class MentorException(ToolChainException): - pass - - -class Configuration(BaseConfiguration): - _vendor = "Mentor" - _toolName = None # automatically configure only vendor path - _section = "INSTALL.Mentor" - _template = { - "Windows": { - _section: { - "InstallationDirectory": "C:/Mentor" - } - }, - "Linux": { - _section: { - "InstallationDirectory": "/opt/QuestaSim" - } - } - } - - def _GetDefaultInstallationDirectory(self): - path = self._TestDefaultInstallPath({"Windows": "Mentor", "Linux": "Mentor"}) - if path is None: return super()._GetDefaultInstallationDirectory() - return path.as_posix() diff --git a/py/ToolChains/Mentor/ModelSim.py b/py/ToolChains/Mentor/ModelSim.py new file mode 100644 index 00000000..4966cffd --- /dev/null +++ b/py/ToolChains/Mentor/ModelSim.py @@ -0,0 +1,240 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# Martin Zabel +# Thomas B. Preusser +# +# Python Class: Mentor Graphics ModelSim specific classes +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair of VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +# +# load dependencies +from collections import OrderedDict +from enum import unique +from re import compile as re_compile +from subprocess import check_output + +from lib.Functions import Init +from ToolChains import ConfigurationException, EditionDescription, Edition, ToolSelector +from ToolChains.Mentor import MentorException +from ToolChains.Mentor.QuestaSim import Configuration as QuestaSim_Configuration + + +__api__ = [ + 'ModelSimException', + 'MentorModelSimEditions', + 'ModelSimEditions', + 'Configuration' +] +__all__ = __api__ + + +class ModelSimException(MentorException): + pass + + +@unique +class MentorModelSimEditions(Edition): + """Enumeration of all ModelSim editions provided by Mentor Graphics itself.""" + ModelSimPE = EditionDescription(Name="ModelSim PE", Section=None) + ModelSimPEEducation = EditionDescription(Name="ModelSim PE (Student Edition)", Section=None) + ModelSimSE32 = EditionDescription(Name="ModelSim SE 32-bit", Section=None) + ModelSimSE64 = EditionDescription(Name="ModelSim SE 64-bit", Section=None) + + +@unique +class ModelSimEditions(Edition): + """Enumeration of all ModelSim editions provided by Mentor Graphics inclusive + editions shipped by other vendors. + """ + ModelSimPE = EditionDescription(Name="ModelSim PE", Section="INSTALL.Mentor.ModelSim") + ModelSimPEEducation = EditionDescription(Name="ModelSim PE (Student Edition)", Section="INSTALL.Mentor.ModelSim") + ModelSimSE32 = EditionDescription(Name="ModelSim SE 32-bit", Section="INSTALL.Mentor.ModelSim") + ModelSimSE64 = EditionDescription(Name="ModelSim SE 64-bit", Section="INSTALL.Mentor.ModelSim") + ModelSimAlteraEdition = EditionDescription(Name="ModelSim Altera Edition", Section="INSTALL.Altera.ModelSim") + # ModelSimAlteraStarterEdition = EditionDescription(Name="ModelSim Altera Starter Edition", Section=None) + ModelSimIntelEdition = EditionDescription(Name="ModelSim Intel Edition", Section="INSTALL.Intel.ModelSim") + # ModelSimIntelStarterEdition = EditionDescription(Name="ModelSim Intel Starter Edition", Section=None) + QuestaSim = EditionDescription(Name="QuestaSim", Section="INSTALL.Mentor.QuestaSim") + + +class Configuration(QuestaSim_Configuration): + _vendor = "Mentor" #: The name of the tools vendor. + _toolName = "Mentor ModelSim" #: The name of the tool. + _section = "INSTALL.Mentor.ModelSim" #: The name of the configuration section. Pattern: ``INSTALL.Vendor.ToolName``. + _multiVersionSupport = True #: Mentor ModelSim supports multiple versions installed on the same system. + _template = { + "Windows": { + _section: { + "Version": "10.5c", + "SectionName": ("%{PathWithRoot}#${Version}", None), + "Edition": "ModelSim PE", + "ToolInstallationName": "ModelSim PE", + "InstallationDirectory": ("${${SectionName}:InstallationDirectory}", "${INSTALL.Mentor:InstallationDirectory}/${ToolInstallationName}/${Version}"), + "BinaryDirectory": ("${${SectionName}:BinaryDirectory}", "${InstallationDirectory}/win") # 32pe / 32pe_edu + } + }, + "Linux": { + _section: { + "Version": "10.5c", + "SectionName": ("%{PathWithRoot}#${Version}", None), + "Edition": "ModelSim PE", + "ToolInstallationName": "ModelSim PE", + "InstallationDirectory": ("${${SectionName}:InstallationDirectory}", "${INSTALL.Mentor:InstallationDirectory}/${ToolInstallationName}/${Version}"), + "BinaryDirectory": ("${${SectionName}:BinaryDirectory}", "${InstallationDirectory}/linux_x86_64") + } + } + } #: The template for the configuration sections represented as nested dictionaries. + + def CheckDependency(self): + """Check if general Mentor Graphics support is configured in PoC.""" + return (len(self._host.PoCConfig['INSTALL.Mentor']) != 0) + + def ConfigureForAll(self): + """Configuration routine for Mentor Graphics ModelSim on all supported + platforms. + + #. Ask if ModelSim is installed. + + * Pass |rarr| skip this configuration. Don't change existing settings. + * Yes |rarr| collect installation information for ModelSim. + * No |rarr| clear the ModelSim configuration section. + + #. Ask for ModelSim's version. + #. Ask for ModelSim's edition (PE, PE student, SE 32-bit, SE 64-bit). + #. Ask for ModelSim's installation directory. + """ + try: + if (not self._AskInstalled("Is Mentor ModelSim installed on your system?")): + self.ClearSection() + else: + # Configure ModelSim version + version = self._ConfigureVersion() + if self._multiVersionSupport: + self.PrepareVersionedSections() + sectionName = self._host.PoCConfig[self._section]['SectionName'] + self._host.PoCConfig[sectionName]['Version'] = version + + _,edition = self._ConfigureEdition() + if self._multiVersionSupport: + sectionName = self._host.PoCConfig[self._section]['SectionName'] + else: + sectionName = self._section + + configSection = self._host.PoCConfig[sectionName] + binaryDirectory = self._host.PoCConfig.get(sectionName, 'BinaryDirectory', raw=True) + if (edition is MentorModelSimEditions.ModelSimPE): + toolInstallaionName = "ModelSim PE" + binaryDirectory = binaryDirectory.replace("win", "win32pe") + elif (edition is MentorModelSimEditions.ModelSimPEEducation): + toolInstallaionName = "ModelSim PE Student Edition" + binaryDirectory = binaryDirectory.replace("win", "win32peedu") + elif (edition is MentorModelSimEditions.ModelSimSE32): + toolInstallaionName = "ModelSim SE" + binaryDirectory = binaryDirectory.replace("win", "win32") + elif (edition is MentorModelSimEditions.ModelSimSE64): + toolInstallaionName = "ModelSim SE" + binaryDirectory = binaryDirectory.replace("win", "win64") + + configSection['ToolInstallationName'] = toolInstallaionName + configSection['BinaryDirectory'] = binaryDirectory + + self._ConfigureInstallationDirectory() + binPath = self._ConfigureBinaryDirectory() + self.__CheckQuestaSimVersion(binPath, version) + self._host.LogNormal("{DARK_GREEN}Mentor Graphics ModelSim is now configured.{NOCOLOR}".format(**Init.Foreground), indent=1) + except ConfigurationException: + self.ClearSection() + raise + + def __GetModelSimVersion(self, binPath): + if (self._host.Platform == "Windows"): + vsimPath = binPath / "vsim.exe" + else: + vsimPath = binPath / "vsim" + + if not vsimPath.exists(): + raise ConfigurationException("Executable '{0!s}' not found.".format(vsimPath)) from FileNotFoundError( + str(vsimPath)) + + # get version and backend + try: + output = check_output([str(vsimPath), "-version"], universal_newlines=True) + except OSError as ex: + raise ConfigurationException("Error while accessing '{0!s}'.".format(vsimPath)) from ex + + version = None + versionRegExpStr = r"^.* vsim (.+?) " + versionRegExp = re_compile(versionRegExpStr) + for line in output.split('\n'): + if version is None: + match = versionRegExp.match(line) + if match is not None: + version = match.group(1) + + print(self._section, version) + + self._host.PoCConfig[self._section]['Version'] = version + + def _ConfigureEdition(self, editions=None, defaultEdition=None): + """Configure ModelSim for Mentor Graphics.""" + if (editions is None): + sectionName = self._section + if self._multiVersionSupport: + sectionName = self._host.PoCConfig[sectionName]['SectionName'] + + configSection = self._host.PoCConfig[sectionName] + defaultEdition = MentorModelSimEditions.Parse(configSection['Edition']) + edition = super()._ConfigureEdition(MentorModelSimEditions, defaultEdition) + + if (edition is not defaultEdition): + configSection['Edition'] = edition.Name + self._host.PoCConfig.Interpolation.clear_cache() + return (True, edition) + else: + return (False, edition) + else: + return super()._ConfigureEdition(editions, defaultEdition) + + +class Selector(ToolSelector): + _toolName = "ModelSim" + + def Select(self): + editions = self._GetConfiguredEditions(ModelSimEditions) + + if (len(editions) == 0): + self._host.LogWarning("No ModelSim installation found.", indent=1) + self._host.PoCConfig['INSTALL.ModelSim'] = OrderedDict() + elif (len(editions) == 1): + self._host.LogNormal("Default ModelSim installation:", indent=1) + self._host.LogNormal("Set to {0}".format(editions[0].Name), indent=2) + self._host.PoCConfig['INSTALL.ModelSim']['SectionName'] = editions[0].Section + else: + self._host.LogNormal("Select ModelSim installation:", indent=1) + + defaultEdition = ModelSimEditions.ModelSimSE64 + if defaultEdition not in editions: + defaultEdition = editions[0] + + selectedEdition = self._AskSelection(editions, defaultEdition) + self._host.PoCConfig['INSTALL.ModelSim']['SectionName'] = selectedEdition.Section diff --git a/py/ToolChains/Mentor/ModelSimPE.py b/py/ToolChains/Mentor/ModelSimPE.py deleted file mode 100644 index 15ea1eab..00000000 --- a/py/ToolChains/Mentor/ModelSimPE.py +++ /dev/null @@ -1,121 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# -# ============================================================================== -# Authors: Patrick Lehmann -# Martin Zabel -# Thomas B. Preusser -# -# Python Class: Mentor Graphics ModelSim specific classes -# -# Description: -# ------------------------------------ -# TODO: -# - -# - -# -# License: -# ============================================================================== -# Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair of VLSI-Design, Diagnostics and Architecture -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# ============================================================================== -# -# load dependencies -from re import compile as RegExpCompile -from subprocess import check_output - -from Base.Configuration import ConfigurationException -from ToolChains.Mentor.Mentor import MentorException -from ToolChains.Mentor.QuestaSim import Configuration as QuestaSim_Configuration - - -__api__ = [ - 'ModelSimException', - 'Configuration' -] -__all__ = __api__ - - -class ModelSimException(MentorException): - pass - - -class Configuration(QuestaSim_Configuration): - _vendor = "Mentor" - _toolName = "ModelSim PE" - _section = "INSTALL.Mentor.ModelSimPE" - _template = { - "Windows": { - _section: { - "Version": "10.4a", - "InstallationDirectory": "${INSTALL.Mentor:InstallationDirectory}/ModelSim PE/${Version}", - "BinaryDirectory": "${InstallationDirectory}/win32pe_edu" - } - }, - "Linux": { - _section: { - "Version": "10.4a", - "InstallationDirectory": "${INSTALL.Mentor:InstallationDirectory}/ModelSim PE/${Version}", - "BinaryDirectory": "${InstallationDirectory}/linux32pe" - } - } - } - - def CheckDependency(self): - # return True if Mentor is configured - return (len(self._host.PoCConfig['INSTALL.Mentor']) != 0) - - def ConfigureForAll(self): - try: - if (not self._AskInstalled("Is Mentor ModelSim PE installed on your system?")): - self.ClearSection() - else: - version = self._ConfigureVersion() - self._ConfigureInstallationDirectory() - binPath = self._ConfigureBinaryDirectory() - self.__CheckQuestaSimVersion(binPath, version) - except ConfigurationException: - self.ClearSection() - raise - - def __GetModelSimVersion(self, binPath): - if (self._host.Platform == "Windows"): - vsimPath = binPath / "vsim.exe" - else: - vsimPath = binPath / "vsim" - - if not vsimPath.exists(): - raise ConfigurationException("Executable '{0!s}' not found.".format(vsimPath)) from FileNotFoundError( - str(vsimPath)) - - # get version and backend - try: - output = check_output([str(vsimPath), "-version"], universal_newlines=True) - except OSError as ex: - raise ConfigurationException("Error while accessing '{0!s}'.".format(vsimPath)) from ex - - version = None - versionRegExpStr = r"^.* vsim (.+?) " - versionRegExp = RegExpCompile(versionRegExpStr) - for line in output.split('\n'): - if version is None: - match = versionRegExp.match(line) - if match is not None: - version = match.group(1) - - print(self._section, version) - - self._host.PoCConfig[self._section]['Version'] = version diff --git a/py/ToolChains/Mentor/QuestaSim.py b/py/ToolChains/Mentor/QuestaSim.py index 834c1d8f..bbc7b9da 100644 --- a/py/ToolChains/Mentor/QuestaSim.py +++ b/py/ToolChains/Mentor/QuestaSim.py @@ -6,13 +6,7 @@ # Authors: Patrick Lehmann # Martin Zabel # -# Python Class: Mentor QuestaSim specific classes -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Class: Mentor QuestaSim specific classes # # License: # ============================================================================== @@ -39,12 +33,11 @@ from lib.Functions import CallByRefParam, Init from Base.Exceptions import PlatformNotSupportedException from Base.Logging import LogEntry, Severity -from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException -from Base.Simulator import SimulationResult, PoCSimulationResultFilter, PoCSimulationResultNotFoundException from Base.Executable import Executable from Base.Executable import ExecutableArgument, ShortFlagArgument, ShortTupleArgument, PathArgument, StringArgument, CommandLineArgumentList -from ToolChains import ToolMixIn -from ToolChains.Mentor.Mentor import MentorException +from ToolChains import ToolMixIn, ConfigurationException, ToolConfiguration +from ToolChains.Mentor import MentorException +from Simulator import PoCSimulationResultNotFoundException, SimulationResult, PoCSimulationResultFilter __api__ = [ @@ -65,29 +58,32 @@ class QuestaSimException(MentorException): pass -class Configuration(BaseConfiguration): - _vendor = "Mentor" - _toolName = "Mentor QuestaSim" - _section = "INSTALL.Mentor.QuestaSim" +class Configuration(ToolConfiguration): + _vendor = "Mentor" #: The name of the tools vendor. + _toolName = "Mentor QuestaSim" #: The name of the tool. + _section = "INSTALL.Mentor.QuestaSim" #: The name of the configuration section. Pattern: ``INSTALL.Vendor.ToolName``. + _multiVersionSupport = True #: Mentor QuestaSim supports multiple versions installed on the same system. _template = { "Windows": { _section: { - "Version": "10.4d", - "InstallationDirectory": "${INSTALL.Mentor:InstallationDirectory}/QuestaSim/${Version}", - "BinaryDirectory": "${InstallationDirectory}/win64" + "Version": "10.5c", + "SectionName": ("%{PathWithRoot}#${Version}", None), + "InstallationDirectory": ("${${SectionName}:InstallationDirectory}", "${INSTALL.Mentor:InstallationDirectory}/QuestaSim/${Version}"), + "BinaryDirectory": ("${${SectionName}:BinaryDirectory}", "${InstallationDirectory}/win64") } }, "Linux": { _section: { - "Version": "10.4d", - "InstallationDirectory": "${INSTALL.Mentor:InstallationDirectory}/${Version}/questasim", - "BinaryDirectory": "${InstallationDirectory}/bin" + "Version": "10.5c", + "SectionName": ("%{PathWithRoot}#${Version}", None), + "InstallationDirectory": ("${${SectionName}:InstallationDirectory}", "${INSTALL.Mentor:InstallationDirectory}/${Version}/questasim"), + "BinaryDirectory": ("${${SectionName}:BinaryDirectory}", "${InstallationDirectory}/bin") } } - } + } #: The template for the configuration sections represented as nested dictionaries. def CheckDependency(self): - # return True if Xilinx is configured + """Check if general Mentor support is configured in PoC.""" return (len(self._host.PoCConfig['INSTALL.Mentor']) != 0) def ConfigureForAll(self): @@ -95,10 +91,17 @@ def ConfigureForAll(self): if (not self._AskInstalled("Is Mentor QuestaSim installed on your system?")): self.ClearSection() else: + # Configure QuestaSim version version = self._ConfigureVersion() + if self._multiVersionSupport: + self.PrepareVersionedSections() + sectionName = self._host.PoCConfig[self._section]['SectionName'] + self._host.PoCConfig[sectionName]['Version'] = version + self._ConfigureInstallationDirectory() binPath = self._ConfigureBinaryDirectory() self.__CheckQuestaSimVersion(binPath, version) + self._host.LogNormal("{DARK_GREEN}Mentor Graphics QuestaSim is now configured.{NOCOLOR}".format(**Init.Foreground), indent=1) except ConfigurationException: self.ClearSection() raise diff --git a/py/ToolChains/Mentor/__init__.py b/py/ToolChains/Mentor/__init__.py index c4506a37..e07abd90 100644 --- a/py/ToolChains/Mentor/__init__.py +++ b/py/ToolChains/Mentor/__init__.py @@ -1,16 +1,12 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; # # ============================================================================== -# Authors: Patrick Lehmann -# -# Python Sub Module: TODO: -# -# Description: -# ------------------------------------ -# TODO: +# Authors: Patrick Lehmann +# Martin Zabel # +# Python Class: Mentor specific classes # # License: # ============================================================================== @@ -21,7 +17,7 @@ # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # -# http://www.apache.org/licenses/LICENSE-2.0 +# http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, @@ -30,13 +26,52 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here +# load dependencies +from ToolChains import ToolChainException, VendorConfiguration + + +__api__ = [ + 'MentorException', + 'Configuration' +] +__all__ = __api__ + + +class MentorException(ToolChainException): pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Repository Service Tool") +class Configuration(VendorConfiguration): + """Configuration routines for Mentor Graphics as a vendor. + + This configuration provides a common installation directory setup for all + Mentor Graphics tools installed on a system. + """ + _vendor = "Mentor" #: The name of the tools vendor. + _section = "INSTALL.Mentor" #: The name of the configuration section. Pattern: ``INSTALL.Vendor.ToolName``. + _template = { + "ALL": { + "INSTALL.ModelSim": { + "SectionName": "", + "Version": "${${SectionName}:Version}", + "Edition": "${${SectionName}:Edition}", + "InstallationDirectory": "${${SectionName}:InstallationDirectory}", + "BinaryDirectory": "${${SectionName}:BinaryDirectory}" + } + }, + "Windows": { + _section: { + "InstallationDirectory": "C:/Mentor" + } + }, + "Linux": { + _section: { + "InstallationDirectory": "/opt/mentor" + } + } + } #: The template for the configuration sections represented as nested dictionaries. + def _GetDefaultInstallationDirectory(self): + path = self._TestDefaultInstallPath({"Windows": "Mentor", "Linux": "Mentor"}) + if path is None: return super()._GetDefaultInstallationDirectory() + return path.as_posix() diff --git a/py/ToolChains/PoC.py b/py/ToolChains/PoC.py index b5056710..649eb0d8 100644 --- a/py/ToolChains/PoC.py +++ b/py/ToolChains/PoC.py @@ -7,13 +7,7 @@ # Martin Zabel # Thomas B. Preusser # -# Python Class: PoC specific classes -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Class: PoC specific classes # # License: # ============================================================================== @@ -36,9 +30,10 @@ # load dependencies from os import environ from pathlib import Path -from subprocess import check_output, check_call, CalledProcessError +from subprocess import CalledProcessError -from Base.Configuration import Configuration as BaseConfiguration +from Base.Exceptions import EnvironmentException +from ToolChains import ToolConfiguration from ToolChains.Git import Git @@ -48,33 +43,53 @@ __all__ = __api__ - -class Configuration(BaseConfiguration): - _vendor = "VLSI-EDA" - _toolName = "PoC" +class Configuration(ToolConfiguration): + _vendor = "VLSI-EDA" #: The name of the tools vendor. + _toolName = "PoC" #: The name of the tool. + _section = "INSTALL.PoC" #: The name of the configuration section. Pattern: ``INSTALL.Vendor.ToolName``. _template = { "ALL": { - "INSTALL.PoC": { + _section: { "Version": "1.1.0", - "InstallationDirectory": None + "InstallationDirectory": "", + "RepositoryKind": "Public", + "IsGitRepository": "True", + "GitRemoteBranch": "master", + "MultiVersionSupport": "True", + "HasInstalledGitHooks": "False", + "HasInstalledGitFilters": "False" }, - "SOLUTION.Solutions": {} + "SOLUTION.Solutions": {} } - } + } #: The template for the configuration sections represented as nested dictionaries. def ConfigureForAll(self): + pocInstallationDirectory = Path(environ.get('PoCRootDirectory')) + if (not pocInstallationDirectory.exists()): + raise EnvironmentException("Path '{0!s}' in environment variable 'PoCRootDirectory' does not exist.") + elif (not pocInstallationDirectory.is_dir()): + raise EnvironmentException("Path '{0!s}' in environment variable 'PoCRootDirectory' is not a directory.") \ + from NotADirectoryError(str(pocInstallationDirectory)) + + self._host.LogNormal(" Installation directory: {0!s} (found in environment variable)".format(pocInstallationDirectory)) + self._host.PoCConfig['INSTALL.PoC']['InstallationDirectory'] = pocInstallationDirectory.as_posix() + + def RunPostConfigurationTasks(self): success = False if (len(self._host.PoCConfig['INSTALL.Git']) != 0): try: binaryDirectoryPath = Path(self._host.PoCConfig['INSTALL.Git']['BinaryDirectory']) git = Git(self._host.Platform, self._host.DryRun, binaryDirectoryPath, "", logger=self._host.Logger) - gitRevList = git.GetGitRevList() + + gitRevList = git.GetGitRevList() gitRevList.RevListParameters[gitRevList.SwitchTags] = True gitRevList.RevListParameters[gitRevList.SwitchMaxCount] = 1 latestTagHash = gitRevList.Execute().strip() - gitDescribe = git.GetGitDescribe() + + gitDescribe = git.GetGitDescribe() gitDescribe.DescribeParameters[gitDescribe.SwitchTags] = latestTagHash latestTagName = gitDescribe.Execute().strip() + self._host.LogNormal(" PoC version: {0} (found in git)".format(latestTagName)) self._host.PoCConfig['INSTALL.PoC']['Version'] = latestTagName success = True @@ -82,15 +97,11 @@ def ConfigureForAll(self): pass if not success: - print("WARNING: Can't get version information from latest git tag.") + self._host.LogWarning("Can't get version information from latest Git tag.") pocVersion = self._template['ALL']['INSTALL.PoC']['Version'] self._host.LogNormal(" PoC version: {0} (found in default configuration)".format(pocVersion)) self._host.PoCConfig['INSTALL.PoC']['Version'] = pocVersion - pocInstallationDirectory = Path(environ.get('PoCRootDirectory')) - self._host.LogNormal(" Installation directory: {0!s} (found in environment variable)".format(pocInstallationDirectory)) - self._host.PoCConfig['INSTALL.PoC']['InstallationDirectory'] = pocInstallationDirectory.as_posix() - # LOCAL = git rev-parse @ # PS G:\git\PoC> git rev-parse "@" # 9c05494ef52c276dabec69dbf734a22f65939305 diff --git a/py/ToolChains/Synopsys/Synopsys.py b/py/ToolChains/Synopsys/Synopsys.py deleted file mode 100644 index 9a7c50d4..00000000 --- a/py/ToolChains/Synopsys/Synopsys.py +++ /dev/null @@ -1,82 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# -# ============================================================================== -# Authors: Patrick Lehmann -# -# Python Class: Mentor QuestaSim specific classes -# -# Description: -# ------------------------------------ -# TODO: -# - -# - -# -# License: -# ============================================================================== -# Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair of VLSI-Design, Diagnostics and Architecture -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# ============================================================================== -# -# load dependencies -from Base.Configuration import Configuration as BaseConfiguration -from Base.Project import ConstraintFile, FileTypes -from Base.ToolChain import ToolChainException - - -__api__ = [ - 'SynopsysException', - 'Configuration', - 'SynopsysDesignConstraintFile' -] -__all__ = __api__ - - -class SynopsysException(ToolChainException): - pass - - -class Configuration(BaseConfiguration): - _vendor = "Synopsys" - _toolName = None # automatically configure only vendor path - _section = "INSTALL.Synopsys" - _template = { - "Windows": { - _section: { - "InstallationDirectory": "C:/Synopsys" - } - }, - "Linux": { - _section: { - "InstallationDirectory": "/opt/Synopsys" - } - } - } - - def _GetDefaultInstallationDirectory(self): - # synopsys = environ.get("QUARTUS_ROOTDIR") # on Windows: D:\Synopsys\13.1\quartus - # if (synopsys is not None): - # return Path(synopsys).parent.parent - - return self._TestDefaultInstallPath({"Windows": "Synopsys", "Linux": "Synopsys"}).as_posix() - - -class SynopsysDesignConstraintFile(ConstraintFile): - _FileType = FileTypes.SdcConstraintFile - - def __str__(self): - return "SDC file: '{0!s}".format(self._file) - diff --git a/py/ToolChains/Synopsys/__init__.py b/py/ToolChains/Synopsys/__init__.py index 7183c8d9..56959d60 100644 --- a/py/ToolChains/Synopsys/__init__.py +++ b/py/ToolChains/Synopsys/__init__.py @@ -1,16 +1,11 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; # # ============================================================================== -# Authors: Patrick Lehmann -# -# Python Sub Module: TODO: -# -# Description: -# ------------------------------------ -# TODO: +# Authors: Patrick Lehmann # +# Python Class: Mentor QuestaSim specific classes # # License: # ============================================================================== @@ -21,7 +16,7 @@ # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # -# http://www.apache.org/licenses/LICENSE-2.0 +# http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, @@ -30,11 +25,54 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here +# load dependencies +from Base.Project import ConstraintFile, FileTypes +from ToolChains import ToolChainException, VendorConfiguration + + +__api__ = [ + 'SynopsysException', + 'Configuration', + 'SynopsysDesignConstraintFile' +] +__all__ = __api__ + + +class SynopsysException(ToolChainException): pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Repository Service Tool") + +class Configuration(VendorConfiguration): + """Configuration routines for Synopsys as a vendor. + + This configuration provides a common installation directory setup for all + Synopsys tools installed on a system. + """ + _vendor = "Synopsys" #: The name of the tools vendor. + _section = "INSTALL.Synopsys" #: The name of the configuration section. Pattern: ``INSTALL.Vendor.ToolName``. + _template = { + "Windows": { + _section: { + "InstallationDirectory": "C:/Synopsys" + } + }, + "Linux": { + _section: { + "InstallationDirectory": "/opt/Synopsys" + } + } + } #: The template for the configuration sections represented as nested dictionaries. + + def _GetDefaultInstallationDirectory(self): + # synopsys = environ.get("QUARTUS_ROOTDIR") # on Windows: D:\Synopsys\13.1\quartus + # if (synopsys is not None): + # return Path(synopsys).parent.parent + + return self._TestDefaultInstallPath({"Windows": "Synopsys", "Linux": "Synopsys"}).as_posix() + + +class SynopsysDesignConstraintFile(ConstraintFile): + _FileType = FileTypes.SdcConstraintFile + + def __str__(self): + return "SDC file: '{0!s}".format(self._file) diff --git a/py/ToolChains/Xilinx/HardwareServer.py b/py/ToolChains/Xilinx/HardwareServer.py deleted file mode 100644 index 90f74151..00000000 --- a/py/ToolChains/Xilinx/HardwareServer.py +++ /dev/null @@ -1,68 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# -# ============================================================================== -# Authors: Patrick Lehmann -# -# Python Class: Xilinx Hardware Server specific classes -# -# Description: -# ------------------------------------ -# TODO: -# - -# - -# -# License: -# ============================================================================== -# Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair of VLSI-Design, Diagnostics and Architecture -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# ============================================================================== -# -# entry point -if __name__ != "__main__" : - # place library initialization code here - pass -else : - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module ToolChains.Xilinx.HardwareServer") - -from Base.Configuration import Configuration as BaseConfiguration - - -class Configuration(BaseConfiguration): - _vendor = "Xilinx" - _toolName = "Xilinx HardwareServer" - _section = "INSTALL.Xilinx.HardwareServer" - _template = { - "Windows": { - _section: { - "Version": "2015.4", - "InstallationDirectory": "${INSTALL.Xilinx:InstallationDirectory}/Vivado/${Version}", - "BinaryDirectory": "${InstallationDirectory}/bin" - } - }, - "Linux": { - _section: { - "Version": "2015.4", - "InstallationDirectory": "${INSTALL.Xilinx:InstallationDirectory}/Vivado/${Version}", - "BinaryDirectory": "${InstallationDirectory}/bin" - } - } - } - - def CheckDependency(self): - # return True if Xilinx is configured - return (len(self._host.PoCConfig['INSTALL.Xilinx']) != 0) diff --git a/py/ToolChains/Xilinx/ISE.py b/py/ToolChains/Xilinx/ISE.py index f3e2b95f..c465a88a 100644 --- a/py/ToolChains/Xilinx/ISE.py +++ b/py/ToolChains/Xilinx/ISE.py @@ -6,13 +6,7 @@ # Authors: Patrick Lehmann # Martin Zabel # -# Python Class: Xilinx ISE specific classes -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Class: Xilinx ISE specific classes # # License: # ============================================================================== @@ -33,18 +27,17 @@ # ============================================================================== # # load dependencies -from subprocess import check_output +from subprocess import check_output -from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException -from Base.Exceptions import PlatformNotSupportedException -from Base.Executable import Executable -from Base.Executable import ExecutableArgument, ShortFlagArgument, ShortTupleArgument, StringArgument, CommandLineArgumentList -from Base.Logging import LogEntry, Severity -from Base.Project import Project as BaseProject, ProjectFile, ConstraintFile, FileTypes -from Base.Simulator import SimulationResult, PoCSimulationResultFilter -from ToolChains import ToolMixIn -from ToolChains.Xilinx.Xilinx import XilinxException -from lib.Functions import CallByRefParam +from lib.Functions import CallByRefParam, Init +from Base.Exceptions import PlatformNotSupportedException +from Base.Executable import Executable +from Base.Executable import ExecutableArgument, ShortFlagArgument, ShortTupleArgument, StringArgument, CommandLineArgumentList +from Base.Logging import LogEntry, Severity +from Base.Project import Project as BaseProject, ProjectFile, ConstraintFile, FileTypes +from ToolChains import ToolMixIn, ConfigurationException, ToolConfiguration +from ToolChains.Xilinx import XilinxException +from Simulator import SimulationResult, PoCSimulationResultFilter __api__ = [ @@ -71,29 +64,32 @@ class ISEException(XilinxException): pass -class Configuration(BaseConfiguration): - _vendor = "Xilinx" - _toolName = "Xilinx ISE" - _section = "INSTALL.Xilinx.ISE" +class Configuration(ToolConfiguration): + _vendor = "Xilinx" #: The name of the tools vendor. + _toolName = "Xilinx ISE" #: The name of the tool. + _section = "INSTALL.Xilinx.ISE" #: The name of the configuration section. Pattern: ``INSTALL.Vendor.ToolName``. + _multiVersionSupport = True #: Xilinx ISE supports multiple versions installed on the same system. _template = { "Windows": { _section: { "Version": "14.7", - "InstallationDirectory": "${INSTALL.Xilinx:InstallationDirectory}/${Version}/ISE_DS", - "BinaryDirectory": "${InstallationDirectory}/ISE/bin/nt64" + "SectionName": ("%{PathWithRoot}#${Version}", None), + "InstallationDirectory": ("${${SectionName}:InstallationDirectory}", "${INSTALL.Xilinx:InstallationDirectory}/${Version}/ISE_DS"), + "BinaryDirectory": ("${${SectionName}:BinaryDirectory}", "${InstallationDirectory}/ISE/bin/nt64") } }, "Linux": { _section: { "Version": "14.7", - "InstallationDirectory": "${INSTALL.Xilinx:InstallationDirectory}/${Version}/ISE_DS", - "BinaryDirectory": "${InstallationDirectory}/ISE/bin/lin64" + "SectionName": ("%{PathWithRoot}#${Version}", None), + "InstallationDirectory": ("${${SectionName}:InstallationDirectory}", "${INSTALL.Xilinx:InstallationDirectory}/${Version}/ISE_DS"), + "BinaryDirectory": ("${${SectionName}:BinaryDirectory}", "${InstallationDirectory}/ISE/bin/lin64") } } - } + } #: The template for the configuration sections represented as nested dictionaries. def CheckDependency(self): - # return True if Xilinx is configured + """Check if general Xilinx support is configured in PoC.""" return (len(self._host.PoCConfig['INSTALL.Xilinx']) != 0) def ConfigureForAll(self): @@ -101,10 +97,17 @@ def ConfigureForAll(self): if (not self._AskInstalled("Is Xilinx ISE installed on your system?")): self.ClearSection() else: - self._host.PoCConfig[self._section]['Version'] = self._template[self._host.Platform][self._section]['Version'] + # Configure ISE version + version = self._ConfigureVersion() + if self._multiVersionSupport: + self.PrepareVersionedSections() + sectionName = self._host.PoCConfig[self._section]['SectionName'] + self._host.PoCConfig[sectionName]['Version'] = version + self._ConfigureInstallationDirectory() binPath = self._ConfigureBinaryDirectory() self.__CheckISEVersion(binPath) + self._host.LogNormal("{DARK_GREEN}Xilinx ISE is now configured.{NOCOLOR}".format(**Init.Foreground), indent=1) except ConfigurationException: self.ClearSection() raise diff --git a/py/ToolChains/Xilinx/LabTools.py b/py/ToolChains/Xilinx/LabTools.py deleted file mode 100644 index 96f77320..00000000 --- a/py/ToolChains/Xilinx/LabTools.py +++ /dev/null @@ -1,68 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# -# ============================================================================== -# Authors: Patrick Lehmann -# -# Python Class: Xilinx LabTools specific classes -# -# Description: -# ------------------------------------ -# TODO: -# - -# - -# -# License: -# ============================================================================== -# Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair of VLSI-Design, Diagnostics and Architecture -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# ============================================================================== -# -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module ToolChains.Xilinx.LabTools") - -from Base.Configuration import Configuration as BaseConfiguration - - -class Configuration(BaseConfiguration): - _vendor = "Xilinx" - _toolName = "Xilinx LabTools" - _section = "INSTALL.Xilinx.LabTools" - _template = { - "Windows": { - _section: { - "Version": "14.7", - "InstallationDirectory": "${INSTALL.Xilinx:InstallationDirectory}/${Version}/LabTools", - "BinaryDirectory": "${InstallationDirectory}/LabTools/bin/nt64" - } - }, - "Linux": { - _section: { - "Version": "14.7", - "InstallationDirectory": "${INSTALL.Xilinx:InstallationDirectory}/${Version}/LabTools", - "BinaryDirectory": "${InstallationDirectory}/LabTools/bin/lin64" - } - } - } - - def CheckDependency(self): - # return True if Xilinx is configured - return (len(self._host.PoCConfig['INSTALL.Xilinx']) != 0) diff --git a/py/ToolChains/Xilinx/Vivado.py b/py/ToolChains/Xilinx/Vivado.py index 66e9c386..c995e1b9 100644 --- a/py/ToolChains/Xilinx/Vivado.py +++ b/py/ToolChains/Xilinx/Vivado.py @@ -6,13 +6,7 @@ # Authors: Patrick Lehmann # Martin Zabel # -# Python Class: Xilinx Vivado specific classes -# -# Description: -# ------------------------------------ -# TODO: -# - -# - +# Python Class: Xilinx Vivado specific classes # # License: # ============================================================================== @@ -33,18 +27,17 @@ # ============================================================================== # # load dependencies -from subprocess import check_output +from subprocess import check_output -from ToolChains import ToolMixIn -from lib.Functions import CallByRefParam +from lib.Functions import CallByRefParam, Init from Base.Exceptions import PlatformNotSupportedException -from Base.Logging import LogEntry, Severity -from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException -from Base.Project import Project as BaseProject, ProjectFile, ConstraintFile, FileTypes -from Base.Simulator import SimulationResult, PoCSimulationResultFilter +from Base.Logging import LogEntry, Severity +from Base.Project import Project as BaseProject, ProjectFile, ConstraintFile, FileTypes from Base.Executable import Executable from Base.Executable import ExecutableArgument, ShortFlagArgument, ShortValuedFlagArgument, ShortTupleArgument, StringArgument, CommandLineArgumentList -from ToolChains.Xilinx.Xilinx import XilinxException +from ToolChains import ToolMixIn, ConfigurationException, ToolConfiguration +from ToolChains.Xilinx import XilinxException +from Simulator import SimulationResult, PoCSimulationResultFilter __api__ = [ @@ -69,29 +62,32 @@ class VivadoException(XilinxException): pass -class Configuration(BaseConfiguration): - _vendor = "Xilinx" - _toolName = "Xilinx Vivado" - _section = "INSTALL.Xilinx.Vivado" +class Configuration(ToolConfiguration): + _vendor = "Xilinx" #: The name of the tools vendor. + _toolName = "Xilinx Vivado" #: The name of the tool. + _section = "INSTALL.Xilinx.Vivado" #: The name of the configuration section. Pattern: ``INSTALL.Vendor.ToolName``. + _multiVersionSupport = True #: Xilinx Vivado supports multiple versions installed on the same system. _template = { "Windows": { _section: { - "Version": "2016.2", - "InstallationDirectory": "${INSTALL.Xilinx:InstallationDirectory}/Vivado/${Version}", - "BinaryDirectory": "${InstallationDirectory}/bin" + "Version": "2016.3", + "SectionName": ("%{PathWithRoot}#${Version}", None), + "InstallationDirectory": ("${${SectionName}:InstallationDirectory}", "${INSTALL.Xilinx:InstallationDirectory}/Vivado/${Version}"), + "BinaryDirectory": ("${${SectionName}:BinaryDirectory}", "${InstallationDirectory}/bin") } }, "Linux": { _section: { - "Version": "2016.2", - "InstallationDirectory": "${INSTALL.Xilinx:InstallationDirectory}/Vivado/${Version}", - "BinaryDirectory": "${InstallationDirectory}/bin" + "Version": "2016.3", + "SectionName": ("%{PathWithRoot}#${Version}", None), + "InstallationDirectory": ("${${SectionName}:InstallationDirectory}", "${INSTALL.Xilinx:InstallationDirectory}/Vivado/${Version}"), + "BinaryDirectory": ("${${SectionName}:BinaryDirectory}", "${InstallationDirectory}/bin") } } - } + } #: The template for the configuration sections represented as nested dictionaries. def CheckDependency(self): - # return True if Xilinx is configured + """Check if general Xilinx support is configured in PoC.""" return (len(self._host.PoCConfig['INSTALL.Xilinx']) != 0) def ConfigureForAll(self): @@ -99,10 +95,17 @@ def ConfigureForAll(self): if (not self._AskInstalled("Is Xilinx Vivado installed on your system?")): self.ClearSection() else: + # Configure Vivado version version = self._ConfigureVersion() + if self._multiVersionSupport: + self.PrepareVersionedSections() + sectionName = self._host.PoCConfig[self._section]['SectionName'] + self._host.PoCConfig[sectionName]['Version'] = version + self._ConfigureInstallationDirectory() binPath = self._ConfigureBinaryDirectory() self.__CheckVivadoVersion(binPath, version) + self._host.LogNormal("{DARK_GREEN}Xilinx Vivado is now configured.{NOCOLOR}".format(**Init.Foreground), indent=1) except ConfigurationException: self.ClearSection() raise diff --git a/py/ToolChains/Xilinx/Xilinx.py b/py/ToolChains/Xilinx/Xilinx.py deleted file mode 100644 index 69893847..00000000 --- a/py/ToolChains/Xilinx/Xilinx.py +++ /dev/null @@ -1,108 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# -# ============================================================================== -# Authors: Patrick Lehmann -# Martin Zabel -# -# Python Class: TODO -# -# Description: -# ------------------------------------ -# TODO: -# - -# - -# -# License: -# ============================================================================== -# Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair of VLSI-Design, Diagnostics and Architecture -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# ============================================================================== -# -# load dependencies -from os import environ -from pathlib import Path - -from Base.Configuration import Configuration as BaseConfiguration -from Base.Project import FileTypes, VHDLVersion -from Base.ToolChain import ToolChainException - - -__api__ = [ - 'XilinxException', - 'Configuration', - 'XilinxProjectExportMixIn' -] -__all__ = __api__ - - -class XilinxException(ToolChainException): - pass - - -class Configuration(BaseConfiguration): - _vendor = "Xilinx" - _toolName = None # automatically configure only vendor path - _section = "INSTALL.Xilinx" - _template = { - "Windows": { - _section: { - "InstallationDirectory": "C:/Xilinx" - } - }, - "Linux": { - _section: { - "InstallationDirectory": "/opt/Xilinx" - } - } - } - - def _GetDefaultInstallationDirectory(self): - xilinx = environ.get("XILINX") - if (xilinx is not None): - return Path(xilinx).parent.parent.parent.as_posix() - - xilinx = environ.get("XILINX_VIVADO") - if (xilinx is not None): - return Path(xilinx).parent.parent.as_posix() - - path = self._TestDefaultInstallPath({"Windows": "Xilinx", "Linux": "Xilinx"}) - if path is None: return super()._GetDefaultInstallationDirectory() - return path.as_posix() - - -class XilinxProjectExportMixIn: - def __init__(self): - pass - - def _GenerateXilinxProjectFileContent(self, tool, vhdlVersion=VHDLVersion.VHDL93): - projectFileContent = "" - for file in self.PoCProject.Files(fileType=FileTypes.VHDLSourceFile | FileTypes.VerilogSourceFile): #self.PoCProject only available via late binding - if (not file.Path.exists()): raise XilinxException("Cannot add '{0!s}' to {1} project file.".format(file.Path, tool)) from FileNotFoundError(str(file.Path)) - if file.FileType is FileTypes.VHDLSourceFile: - # create one VHDL line for each VHDL file - if (vhdlVersion is VHDLVersion.VHDL2008): projectFileContent += "vhdl2008 {0} \"{1!s}\"\n".format(file.LibraryName, file.Path) - else: projectFileContent += "vhdl {0} \"{1!s}\"\n".format(file.LibraryName, file.Path) - else: # verilog - projectFileContent += "verilog work \"{0!s}\"\n".format(file.Path) - - return projectFileContent - - def _WriteXilinxProjectFile(self, projectFilePath, tool, vhdlVersion=VHDLVersion.VHDL93): - projectFileContent = self._GenerateXilinxProjectFileContent(tool, vhdlVersion) - self.LogDebug("Writing {0} project file to '{1!s}'".format(tool, projectFilePath)) #self.LogDebug only available via late binding - with projectFilePath.open('w') as prjFileHandle: - prjFileHandle.write(projectFileContent) diff --git a/py/ToolChains/Xilinx/__init__.py b/py/ToolChains/Xilinx/__init__.py index 7183c8d9..1322e72f 100644 --- a/py/ToolChains/Xilinx/__init__.py +++ b/py/ToolChains/Xilinx/__init__.py @@ -1,16 +1,12 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; # # ============================================================================== -# Authors: Patrick Lehmann -# -# Python Sub Module: TODO: -# -# Description: -# ------------------------------------ -# TODO: +# Authors: Patrick Lehmann +# Martin Zabel # +# Python Class: TODO # # License: # ============================================================================== @@ -21,7 +17,7 @@ # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # -# http://www.apache.org/licenses/LICENSE-2.0 +# http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, @@ -30,11 +26,82 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here +# load dependencies +from os import environ +from pathlib import Path + +from Base.Project import FileTypes, VHDLVersion +from ToolChains import ToolChainException, VendorConfiguration + + +__api__ = [ + 'XilinxException', + 'Configuration', + 'XilinxProjectExportMixIn' +] +__all__ = __api__ + + +class XilinxException(ToolChainException): pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Repository Service Tool") + +class Configuration(VendorConfiguration): + """Configuration routines for Xilinx as a vendor. + + This configuration provides a common installation directory setup for all + Xilinx tools installed on a system. + """ + _vendor = "Xilinx" #: The name of the tools vendor. + _section = "INSTALL.Xilinx" #: The name of the configuration section. Pattern: ``INSTALL.Vendor.ToolName``. + _template = { + "Windows": { + _section: { + "InstallationDirectory": "C:/Xilinx" + } + }, + "Linux": { + _section: { + "InstallationDirectory": "/opt/Xilinx" + } + } + } #: The template for the configuration sections represented as nested dictionaries. + + def _GetDefaultInstallationDirectory(self): + xilinx = environ.get("XILINX") + if (xilinx is not None): + return Path(xilinx).parent.parent.parent.as_posix() + + xilinx = environ.get("XILINX_VIVADO") + if (xilinx is not None): + return Path(xilinx).parent.parent.as_posix() + + path = self._TestDefaultInstallPath({"Windows": "Xilinx", "Linux": "Xilinx"}) + if path is None: return super()._GetDefaultInstallationDirectory() + return path.as_posix() + + +class XilinxProjectExportMixIn: + def __init__(self): + pass + + def _GenerateXilinxProjectFileContent(self, tool, vhdlVersion=VHDLVersion.VHDL93): + projectFileContent = "" + for file in self.PoCProject.Files(fileType=FileTypes.VHDLSourceFile | FileTypes.VerilogSourceFile): # self.PoCProject only available via late binding + if (not file.Path.exists()): raise XilinxException("Cannot add '{0!s}' to {1} project file.".format(file.Path, tool)) from FileNotFoundError(str(file.Path)) + if file.FileType is FileTypes.VHDLSourceFile: + # create one VHDL line for each VHDL file + if (vhdlVersion is VHDLVersion.VHDL2008): + projectFileContent += "vhdl2008 {0} \"{1!s}\"\n".format(file.LibraryName, file.Path) + else: + projectFileContent += "vhdl {0} \"{1!s}\"\n".format(file.LibraryName, file.Path) + else: # verilog + projectFileContent += "verilog work \"{0!s}\"\n".format(file.Path) + + return projectFileContent + + def _WriteXilinxProjectFile(self, projectFilePath, tool, vhdlVersion=VHDLVersion.VHDL93): + projectFileContent = self._GenerateXilinxProjectFileContent(tool, vhdlVersion) + self.LogDebug("Writing {0} project file to '{1!s}'".format(tool, projectFilePath)) # self.LogDebug only available via late binding + with projectFilePath.open('w') as prjFileHandle: + prjFileHandle.write(projectFileContent) diff --git a/py/ToolChains/__init__.py b/py/ToolChains/__init__.py index c3f6d23b..fb913655 100644 --- a/py/ToolChains/__init__.py +++ b/py/ToolChains/__init__.py @@ -3,15 +3,10 @@ # kate: tab-width 2; replace-tabs off; indent-width 2; # # ============================================================================== -# Authors: Patrick Lehmann -# Martin Zabel -# -# Python Sub Module: TODO: -# -# Description: -# ------------------------------------ -# TODO: +# Authors: Patrick Lehmann +# Martin Zabel # +# Python package: Contains PoC's configuration mechanism. # # License: # ============================================================================== @@ -31,6 +26,70 @@ # limitations under the License. # ============================================================================== # +# load dependencies +from collections import OrderedDict, namedtuple +from enum import unique, Enum +from pathlib import Path + +from lib.Functions import Init, CallByRefBoolParam +from Base import ILogable, IHost +from Base.Exceptions import ExceptionBase +from Base.Logging import Severity + + +__api__ = [ + 'ToolChainException', + 'ConfigurationException', + 'SkipConfigurationException', + 'ToolMixIn', + 'Configurations', + 'Configurator', + 'ConfigurationState', + 'ChangeState', + 'AskMixIn', + 'Configuration', + 'VendorConfiguration', + 'ToolConfiguration', + 'EditionDescription', + 'Edition', + 'ToolSelector' +] +__all__ = __api__ + + +class ToolChainException(ExceptionBase): + """Base class for all tool specific exceptions""" + +class ConfigurationException(ExceptionBase): + """``ConfigurationException`` is raise while running configuration or database + tasks in PoC + """ + +class SkipConfigurationException(ExceptionBase): + """``SkipConfigurationException`` is a :py:exc:`ConfigurationException`, + which can be skipped. + """ + + +@unique +class ConfigurationState(Enum): + """Describes the configuration state of a tool or vendor.""" + Unconfigured = 0 + Configured = 1 + + def __bool__(self): + return self is self.Configured + +@unique +class ChangeState(Enum): + """Describes if a configuration was changed.""" + Unchanged = 0 + Changed = 1 + + def __bool__(self): + return self is self.Changed + + class ToolMixIn: def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): self._platform = platform @@ -40,53 +99,847 @@ def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): self._logger = logger -from .PoC import Configuration as PoC_Configuration -from .Git import Configuration as Git_Configuration -from .Aldec.Aldec import Configuration as Aldec_Configuration -from .Aldec.ActiveHDL import Configuration as ActiveHDL_Configuration -from .Altera.Altera import Configuration as Altera_Configuration -from .Altera.Quartus import Configuration as Quartus_Configuration -from .Altera.ModelSim import Configuration as AlteraModelSim_Configuration -from .GHDL import Configuration as GHDL_Configuration -from .GTKWave import Configuration as GTKW_Configuration -from .Lattice.Lattice import Configuration as Lattice_Configuration -from .Lattice.Diamond import Configuration as Diamond_Configuration -from .Lattice.ActiveHDL import Configuration as LatticeActiveHDL_Configuration -# from .Lattice.Symplify import Configuration as LatticeSymplify_Configuration -from .Mentor.Mentor import Configuration as Mentor_Configuration -from .Mentor.QuestaSim import Configuration as Questa_Configuration -from .Mentor.ModelSimPE import Configuration as ModelSimPE_Configuration -# from .Mentor.PrecisionRTL import Configuration as PrecisionRTL_Configuration -# from .Synopsys.Synopsys import Configuration as Synopsys_Configuration -# from .Synopsys.Symplify import Configuration as Symplify_Configuration -from .Xilinx.Xilinx import Configuration as Xilinx_Configuration -from .Xilinx.ISE import Configuration as ISE_Configuration -from .Xilinx.Vivado import Configuration as Vivado_Configuration - - -Configurations = [ - Git_Configuration, - PoC_Configuration, - # Aldec products - Aldec_Configuration, - ActiveHDL_Configuration, - # Altera products - Altera_Configuration, - Quartus_Configuration, - AlteraModelSim_Configuration, - # Lattice products - Lattice_Configuration, - Diamond_Configuration, - LatticeActiveHDL_Configuration, - # Mentor products - Mentor_Configuration, - Questa_Configuration, - ModelSimPE_Configuration, - # Xilinx products - Xilinx_Configuration, - ISE_Configuration, - Vivado_Configuration, - # other products - GHDL_Configuration, - GTKW_Configuration -] +class AskMixIn: + def _Ask(self, question, default, beforeDefault="", afterDefault="", indent=1): + question += " [{beforeDefault!s}{CYAN}{default!s}{NOCOLOR}{afterDefault!s}]: " + self.LogNormal(question.format(beforeDefault=beforeDefault, default=default, afterDefault=afterDefault, **Init.Foreground), indent=indent, appendLinebreak=False) + print(Init.Foreground["GREEN"], end="") + answer = input() + print(Init.Foreground["NOCOLOR"], end="") + + if (answer == ""): + answer = default + question = "\x1B[1A" + question + "{GREEN}{default!s}{NOCOLOR}" # cursor 1 up + self.LogNormal(question.format(beforeDefault=beforeDefault, default=default, afterDefault=afterDefault, **Init.Foreground), indent=indent) + return answer + + def _Ask_YesNoPass(self, question, indent=1): + """Ask a YES/no/pass question.""" + while True: + isInstalled = self._Ask(question, default="Y", afterDefault="/n/p", indent=indent) + if (isInstalled in ['p', 'P']): + raise SkipConfigurationException() + elif (isInstalled in ['n', 'N']): + return False + elif (isInstalled in ['y', 'Y']): + return True + else: + self.LogNormal("Unsupported choice '{0}'".format(isInstalled), indent=indent) + + def _AskYes_NoPass(self, question, indent=1): + """Ask a yes/NO/pass question.""" + while True: + isInstalled = self._Ask(question, default="N", beforeDefault="y/", afterDefault="/p", indent=indent) + if (isInstalled in ['p', 'P']): + raise SkipConfigurationException() + elif (isInstalled in ['n', 'N']): + return False + elif (isInstalled in ['y', 'Y']): + return True + else: + self.LogNormal("Unsupported choice '{0}'".format(isInstalled), indent=indent) + + def _PrintAvailableEditions(self, editions, selectedEdition): + """Print all available editions and return the selected index.""" + if (not isinstance(editions, (list, tuple))): + # if issubclass(editions, Edition): + editions = list(editions) + + selectedIndex = 0 + for i, item in enumerate(editions): + if (item is selectedEdition): + self.LogNormal("{DARK_CYAN}{0}: {1!s}{NOCOLOR}".format(i, item.Name, **Init.Foreground), indent=2) + selectedIndex = i + else: + self.LogNormal("{0}: {1!s}".format(i, item.Name), indent=2) + + return selectedIndex + + +class Configuration(ILogable, AskMixIn): #(ISubClassRegistration): + """Base class for all Configuration classes.""" + + _vendor = "Unknown" #: The name of the tools vendor. + _section = "INSTALL.Name" #: The name of the configuration section. Pattern: ``INSTALL.Tool``. + _multiVersionSupport = False #: True if a tool supports multiple versions installed on the same system. + _template = { + "ALL": { _section: {} }, + "Darwin": { _section: {} }, + "Linux": { _section: {} }, + "Windows": { _section: {} } + } #: The template for the configuration sections represented as nested dictionaries. + + def __init__(self, host : IHost): + """Class initializer.""" + self._host = host + self._state = self.IsConfigured() + self._changed = ChangeState.Unchanged + + ILogable.__init__(self, host.Logger if isinstance(host, ILogable) else None) + + @property + def Host(self): + """Return the hosting object.""" + return self._host + + @property + def State(self): + """Return the configuration state.""" + return self._state + + def IsSupportedPlatform(self): + """Return true if the given platform is supported by this configuration routine.""" + return ('ALL' in self._template) or (self._host.Platform in self._template) + + def IsConfigured(self): + """Return true if the configurations section is configured""" + if self._host.PoCConfig.has_section(self._section): + optionCount = len(self._host.PoCConfig.options(self._section)) + if (optionCount > 0): + return ConfigurationState.Configured + + return ConfigurationState.Unconfigured + + def CheckDependency(self): + """Check if all vendor or tool dependencies are fulfilled to configure this tool.""" + return True + + @classmethod + def GetSections(cls, platform): + """Return all section names for this configuration.""" + if ("ALL" in cls._template): + for sectionName in cls._template['ALL']: + yield sectionName + if (platform in cls._template): + for sectionName in cls._template[platform]: + yield sectionName + + def PrepareSections(self, warningWasWritten, writeWarnings=True): + pocConfig = self._host.PoCConfig + for platform in ["ALL", self._host.Platform]: + if (platform in self._template): + for sectionName, section in self._template[platform].items(): + if (not pocConfig.has_section(sectionName)): + self.LogWarning("WARNING: Adding new sections to configuration...", condition=(writeWarnings and not warningWasWritten)) + warningWasWritten |= True + + self.LogVerbose("Adding [{0}]".format(sectionName), condition=writeWarnings) + pocConfig[sectionName] = OrderedDict() + + def ClearSection(self, writeWarnings=False): + """Clear the configuration section associated to this Configuration class.""" + self.LogWarning("WARNING: Clearing section '{0}'...".format(self._section), condition=writeWarnings, indent=1) + self._host.PoCConfig[self._section] = OrderedDict() + if self._multiVersionSupport: + warningWasWritten = False + sectionNames = [sectionName for sectionName in self._host.PoCConfig if ((len(sectionName) > len(self._section)) and sectionName.startswith(self._section))] + for sectionName in sectionNames: + self.LogWarning("WARNING: Removing versioned sections...", condition=(writeWarnings and not warningWasWritten), indent=1) + self.LogWarning(sectionName, condition=writeWarnings, indent=2) + self._host.PoCConfig.remove_section(sectionName) + + def PrepareOptions(self, writeWarnings=True): + pocConfig = self._host.PoCConfig + for platform in ["ALL", self._host.Platform]: + if (platform in self._template): + for sectionName, section in self._template[platform].items(): + warningWasWritten = False + pocSection = pocConfig[sectionName] + + for optionName, optionValue in section.items(): + if (not pocConfig.has_option(sectionName, optionName)): + self.LogWarning("Adding new options to section '{0}'...".format(sectionName), condition=(writeWarnings and not warningWasWritten), indent=2) + warningWasWritten |= True + + if (self._multiVersionSupport and isinstance(optionValue, tuple)): + value = optionValue[0] + if (value is not None): + self.LogWarning("Adding {0} = {1}".format(optionName, value), condition=writeWarnings, indent=3) + pocSection[optionName] = value + else: + self.LogWarning("Adding {0} = {1}".format(optionName, optionValue), condition=writeWarnings, indent=3) + pocSection[optionName] = optionValue + + def ConfigureForDarwin(self): + """Start the configuration procedure for Darwin. + + This method is a wrapper for :py:meth:`ConfigureForAll`. Overwrite this + method to implement a Darwin specific configuration routine. + """ + self.ConfigureForAll() + + def ConfigureForLinux(self): + """Start the configuration procedure for Linux. + + This method is a wrapper for :py:meth:`ConfigureForAll`. Overwrite this + method to implement a Linux specific configuration routine. + """ + self.ConfigureForAll() + + def ConfigureForWindows(self): + """Start the configuration procedure for Windows. + + This method is a wrapper for :py:meth:`ConfigureForAll`. Overwrite this + method to implement a Windows specific configuration routine. + """ + self.ConfigureForAll() + + def ConfigureForAll(self): + """Start a generic (platform independent) configuration procedure. + + Overwrite this method to implement a generic configuration routine for a + (tool) Configuration class. + """ + raise NotImplementedError("Either ``ConfigureForAll()`` or one of the platform specific ``ConfigureFor***()`` methods must be overwritten.") + + def __str__(self): + """Return the vendor name.""" + return self._vendor + + def _AskInstalled(self, question): + """Ask a Yes/No/Pass question.""" + return self._Ask_YesNoPass(question) + + def _ConfigureInstallationDirectory(self): + """ + Asks for installation directory and updates section. + Checks if entered directory exists and returns Path object. + If no installation directory was configured before, then _GetDefaultInstallationDir is called. + """ + # if self._host.PoCConfig.has_option(self._section, 'InstallationDirectory'): + defaultPath = Path(self._host.PoCConfig[self._section]['InstallationDirectory']) + # else: + # unresolved = self._GetDefaultInstallationDirectory() # may return an unresolved configuration string + # self._host.PoCConfig[self._section]['InstallationDirectory'] = unresolved # create entry + # defaultPath = Path(self._host.PoCConfig[self._section]['InstallationDirectory']) # resolve entry + + question = "{0!s} installation directory".format(self) + installPath = self._Ask(question, default=defaultPath) + if isinstance(installPath, str): + installPath = Path(installPath) + + if (not installPath.exists()): + raise ConfigurationException("{0!s} installation directory '{1!s}' does not exist.".format(self, installPath)) \ + from NotADirectoryError(str(installPath)) + + if installPath != defaultPath: # update only if user entered something + if self._multiVersionSupport: + sectionName = self._host.PoCConfig[self._section]['SectionName'] + else: + sectionName = self._section + + self._host.PoCConfig[sectionName]['InstallationDirectory'] = installPath.as_posix() + self._host.PoCConfig.Interpolation.clear_cache() + + return installPath + + def _GetDefaultInstallationDirectory(self): + """Return unresolved default installation directory (str) from template. + + Overwrite function in sub-class for automatic search of installation directory. + """ + return self._GetDefaultOptionValue('InstallationDirectory') + + def _GetDefaultOptionValue(self, optionName): + for platform in ["ALL", self._host.Platform]: + if (platform in self._template): + platformDict = self._template[platform] + if (self._section in platformDict): + sectionDict = platformDict[self._section] + if (optionName in sectionDict): + optionValue = sectionDict[optionName] + if self._multiVersionSupport: + return optionValue[1] + else: + return optionValue + + def _TestDefaultInstallPath(self, defaults): + """Helper function for automatic search of installation directory.""" + if (self._host.Platform == "Windows"): + for drive in "CDEFGH": + defaultPathNames = defaults["Windows"] + if (not isinstance(defaultPathNames, (list, tuple))): + defaultPathNames = (defaultPathNames) + for pathName in defaultPathNames: + defaultInstallPath = Path("{0}:/{1}".format(drive, pathName)) + try: + if (defaultInstallPath.exists()): + return defaultInstallPath + except OSError: + pass + else: + defaultPathNames = defaults[self._host.Platform] + if (not isinstance(defaultPathNames, (list, tuple))): + defaultPathNames = (defaultPathNames) + + for pathName in defaultPathNames: + defaultInstallPath = Path("/opt") / pathName + print("testing: {0!s}".format(defaultInstallPath)) + try: + if (defaultInstallPath.exists()): + return defaultInstallPath + except OSError: + pass + + defaultInstallPath = Path("/opt") / pathName.lower() + print("testing: {0!s}".format(defaultInstallPath)) + try: + if (defaultInstallPath.exists()): + return defaultInstallPath + except OSError: + pass + + return None + + def RunPostConfigurationTasks(self): + """Virtual method. Overwrite to execute post-configuration tasks.""" + pass + + +class VendorConfiguration(Configuration): + """Base class for all vendor Configuration classes.""" + _section = "INSTALL.Vendor.Tool" #: The name of the configuration section. Pattern: ``INSTALL.Vendor``. + _template = { + "Darwin": { + _section: { + "InstallationDirectory": "/opt/Vendor", + } + }, + "Linux": { + _section: { + "InstallationDirectory": "/opt/Vendor", + } + }, + "Windows": { + _section: { + "InstallationDirectory": "C:/Vendor", + } + } + } #: The template for the configuration section represented as nested dictionaries. + + # Method aliases + IsConfigured = Configuration.IsConfigured + """Return true if the vendor represented by this Configuration class is + configured in PoC. + + Inherited method :py:meth:`~Configuration.IsConfigured` from class + :py:class:`Configuration`. + """ + + def ConfigureForAll(self): + """Start a generic (platform independent) vendor configuration procedure. + + This method configures a vendor path. Overwrite this method to implement a + vendor specific configuration routine for a vendor Configuration class. + """ + try: + if (not self._AskInstalled("Are {0} products installed on your system?".format(self._vendor))): + self.ClearSection() + else: + self._ConfigureInstallationDirectory() + except SkipConfigurationException: + if (self._state is not ConfigurationState.Configured): + self.ClearSection() + raise + + +class ToolConfiguration(Configuration): + """Base class for all tool Configuration classes.""" + + _section = "INSTALL.Vendor.Tool" #: The name of the configuration section. Pattern: ``INSTALL.Vendor.ToolName``. + _toolName = "Tool" #: The name of the tool. + _template = { + "ALL": { + _section: { + "Version": "1.0", + } + }, + "Darwin": { + _section: { + "InstallationDirectory": "${INSTALL.Vendor:InstallationDirectory}/${Version}/Tool", + "BinaryDirectory": "${InstallationDirectory}/bin" + } + }, + "Linux": { + _section: { + "InstallationDirectory": "${INSTALL.Vendor:InstallationDirectory}/${Version}/Tool", + "BinaryDirectory": "${InstallationDirectory}/bin" + } + }, + "Windows": { + _section: { + "InstallationDirectory": "${INSTALL.Vendor:InstallationDirectory}/${Version}/Tool/", + "BinaryDirectory": "${InstallationDirectory}/bin" + } + } + } #: The template for the configuration section represented as nested dictionaries. + + # Method aliases + IsConfigured = Configuration.IsConfigured + """Return true if the tool represented by this Configuration class is + configured in PoC. + + Inherited method :py:meth:`~Configuration.IsConfigured` from class + :py:class:`Configuration`. + """ + + def _ConfigureVersion(self): + """ + If no version was configured before, then _GetDefaultVersion is called. + Asks for version and updates section. Returns version as string. + """ + # if self._host.PoCConfig.has_option(self._section, 'Version'): + defaultVersion = self._host.PoCConfig[self._section]['Version'] + # else: + # unresolved = self._GetDefaultVersion() # may return an unresolved configuration string + # self._host.PoCConfig[self._section]['Version'] = unresolved # create entry + # defaultVersion = self._host.PoCConfig[self._section]['Version'] # resolve entry + + question = "{0!s} version".format(defaultVersion) + version = self._Ask(question, default=defaultVersion, indent=1) + + if (version != defaultVersion): # update only if user entered something + self._host.PoCConfig[self._section]['Version'] = version + self._host.PoCConfig.Interpolation.clear_cache() + + return version + + def _GetDefaultVersion(self): + """Returns unresolved default version (str) from template. + + Overwrite this method in a sub-class for automatic search of version. + """ + return self._template[self._host.Platform][self._section]['Version'] + + def _ConfigureEdition(self, editions, defaultEdition): + self._host.LogNormal(" Which {0} edition is installed on the system?".format(self._toolName)) + defaultIndex = self._PrintAvailableEditions(editions, defaultEdition) + + question = "Installed edition [{CYAN}{0}{NOCOLOR}]: " + while True: + self._host.LogNormal(question.format(defaultIndex, **Init.Foreground), indent=1, appendLinebreak=False) + print(Init.Foreground["GREEN"], end="") + selectedIndex = input() + print(Init.Foreground["NOCOLOR"], end="") + + if (selectedIndex != ""): + # FIXME: Can I use editions.Parse()? + selectedIndex = int(selectedIndex) + for i, item in enumerate(editions.__members__.values()): + if (i == selectedIndex): + edition = item + break + else: + self._host.LogError("Invalid choice.") + continue # the outer while loop + + else: + edition = defaultEdition + # reprint the colored lines on console + print("\x1B[{n}A".format(n=len(editions) + 2)) # cursor n+2 up + self._PrintAvailableEditions(editions, edition) + question += "{GREEN}{0}" + self._host.LogNormal(question.format(defaultIndex, **Init.Foreground), indent=1) + break + + return edition + + def _GetDefaultEdition(self): + """Returns unresolved default edition (str) from template. + + Overwrite this method in a sub-class for automatic search of editions. + """ + return self._template[self._host.Platform][self._section]['Edition'] + + def _ConfigureBinaryDirectory(self): + """Updates section with value from :attr:`_template` and returns directory + as :class:`Path ` object. + """ + # unresolved = self._template[self._host.Platform][self._section]['BinaryDirectory'] + # self._host.PoCConfig[self._section]['BinaryDirectory'] = unresolved # create entry + defaultPath = Path(self._host.PoCConfig[self._section]['BinaryDirectory']) # resolve entry + + binPath = defaultPath # may be more complex in the future + + if (not binPath.exists()): + raise ConfigurationException("{0!s} binary directory '{1!s}' does not exist.".format(self, binPath)) \ + from NotADirectoryError(str(binPath)) + + return binPath + + def PrepareVersionedSections(self, writeWarnings=False): + warningWasWritten = False + pocConfig = self._host.PoCConfig + for platform in ["ALL", self._host.Platform]: + if ((platform not in self._template) or (self._section not in self._template[platform])): + continue + + sectionName = self._host.PoCConfig[self._section]['SectionName'] + if (not pocConfig.has_section(sectionName)): + self.LogWarning("WARNING: Adding new sections to configuration...", condition=(writeWarnings and not warningWasWritten), indent=2) + warningWasWritten |= True + + self.LogWarning("Adding [{0}]".format(sectionName), condition=writeWarnings, indent=2) + pocConfig[sectionName] = OrderedDict() + + section = self._template[platform][self._section] + pocSection = pocConfig[sectionName] + for optionName, optionValue in section.items(): + if (not pocConfig.has_option(sectionName, optionName)): + self.LogWarning("Adding new options to section '{0}'...".format(sectionName), condition=(writeWarnings and not warningWasWritten), indent=2) + warningWasWritten |= True + + if (self._multiVersionSupport and isinstance(optionValue, tuple)): + value = optionValue[1] + if (value is not None): + self.LogWarning("Adding {0} = {1}".format(optionName, value), condition=writeWarnings, indent=3) + pocSection[optionName] = value + else: + self.LogWarning("Adding {0} = {1}".format(optionName, optionValue), condition=writeWarnings, indent=3) + pocSection[optionName] = optionValue + + def __str__(self): + """Return the tool name.""" + return self._toolName + + +EditionDescription = namedtuple('EditionDescription', ['Name', 'Section']) + + +class Edition(Enum): + def __new__(cls, *args, **kwargs): + value = len(cls.__members__) + 1 + obj = object.__new__(cls) + obj._value_ = value + return obj + + def __init__(self, name, section): + self.Name = name + self.Section = section + + @classmethod + def Parse(cls, value): + """Resolve edition name to enum member""" + for item in cls.__members__.values(): + if (item.Name == value): + return item + else: + raise ValueError("Unknown enum value '{0}'.".format(value)) + + def __repr__(self): + return self.Name + + +class ToolSelector(ILogable, AskMixIn): + """Base class for all Configuration classes.""" + + def __init__(self, host: IHost): + """Class initializer.""" + self._host = host + + ILogable.__init__(self, host.Logger if isinstance(host, ILogable) else None) + + def _GetConfiguredEditions(self, editions): + """Return all configured editions.""" + _editions = [] + for edition in editions: + if (len(self._host.PoCConfig[edition.Section]) > 0): + _editions.append(edition) + + return _editions + + def _AskSelection(self, editions, defaultEdition): + defaultIndex = self._PrintAvailableEditions(editions, defaultEdition) + + question = "Selected installation [{CYAN}{0}{NOCOLOR}]: " + while True: + self._host.LogNormal(question.format(defaultIndex, **Init.Foreground), indent=1, appendLinebreak=False) + print(Init.Foreground["GREEN"], end="") + selectedIndex = input() + print(Init.Foreground["NOCOLOR"], end="") + + if (selectedIndex != ""): + # FIXME: Can I use editions.Parse()? + selectedIndex = int(selectedIndex) + for i, item in enumerate(editions): + if (i == selectedIndex): + edition = item + break + else: + + # try: + # selectedIndex = int(selectedIndex) + # edition = editions.Parse(selectedIndex) + # break + # except: + self._host.LogError("Invalid choice.") + continue # the outer while loop + + else: + edition = defaultEdition + # reprint the colored lines on console + print("\x1B[{n}A".format(n=len(editions) + 2)) # cursor n+2 up + self._PrintAvailableEditions(editions, edition) + question += "{GREEN}{0}" + self._host.LogNormal(question.format(defaultIndex, **Init.Foreground), indent=1) + break + + return edition + + +class Configurator(ILogable, AskMixIn): + """A instance of this class controls the interactive configuration process.""" + def __init__(self, host : IHost): + """Class initializier.""" + ILogable.__init__(self, host.Logger if isinstance(host, ILogable) else None) + + self._host = host + self._saveConfiguration = True + + from .PoC import Configuration as PoC_Configuration + from .Git import Configuration as Git_Configuration + from .Aldec import Configuration as Aldec_Configuration + from .Aldec.ActiveHDL import Configuration as ActiveHDL_Configuration, ActiveHDLEditions + from .Altera import Configuration as Altera_Configuration + from .Altera.Quartus import Configuration as AlteraQuartus_Configuration + from .Altera.ModelSim import Configuration as AlteraModelSim_Configuration + from .Intel import Configuration as Intel_Configuration + from .Intel.Quartus import Configuration as IntelQuartus_Configuration + from .Intel.ModelSim import Configuration as IntelModelSim_Configuration + from .GHDL import Configuration as GHDL_Configuration + from .GTKWave import Configuration as GTKW_Configuration + from .Lattice import Configuration as Lattice_Configuration + from .Lattice.Diamond import Configuration as Diamond_Configuration + from .Lattice.ActiveHDL import Configuration as LatticeActiveHDL_Configuration + # from .Lattice.Symplify import Configuration as LatticeSymplify_Configuration + from .Mentor import Configuration as Mentor_Configuration + from .Mentor.QuestaSim import Configuration as Questa_Configuration + from .Mentor.ModelSim import Configuration as ModelSim_Configuration + # from .Mentor.PrecisionRTL import Configuration as PrecisionRTL_Configuration + # from .Synopsys import Configuration as Synopsys_Configuration + # from .Synopsys.Symplify import Configuration as Symplify_Configuration + from .Xilinx import Configuration as Xilinx_Configuration + from .Xilinx.ISE import Configuration as ISE_Configuration + from .Xilinx.Vivado import Configuration as Vivado_Configuration + #: List of all available (and thus enabled) Configuration classes. + Configurations = [ + PoC_Configuration, + Git_Configuration, + # Aldec products + Aldec_Configuration, + ActiveHDL_Configuration, + # Altera products + Altera_Configuration, + AlteraQuartus_Configuration, + AlteraModelSim_Configuration, + # Intel products + Intel_Configuration, + IntelQuartus_Configuration, + IntelModelSim_Configuration, + # Lattice products + Lattice_Configuration, + Diamond_Configuration, + LatticeActiveHDL_Configuration, + # Mentor products + Mentor_Configuration, + ModelSim_Configuration, + Questa_Configuration, + # Xilinx products + Xilinx_Configuration, + ISE_Configuration, + Vivado_Configuration, + # other products + GHDL_Configuration, + GTKW_Configuration + ] + + from .Aldec.ActiveHDL import Selector as ActiveHDL_Selector + from .Altera.Quartus import Selector as Quartus_Selector + from .Mentor.ModelSim import Selector as ModelSim_Selector + #: List of all available (and thus enabled) Selector classes. + Selectors = [ + ActiveHDL_Selector, + ModelSim_Selector, + Quartus_Selector + ] + + self._configurators = [configuration(self._host) for configuration in Configurations] + self._selectors = [selector(self._host) for selector in Selectors] + + def ConfigureAll(self): + """Select all tool chains for configuration""" + self._WriteConfigurationHeader() + self._ConfigureTools(self._configurators) + + # Write and re-read configuration + if self._saveConfiguration: + self._host.SaveAndReloadPoCConfiguration() + + def ConfigureTool(self, toolChain): + """Select tool chains for configuration.""" + sectionName = ("INSTALL.{0}".format(toolChain)).lower() + configurators = [config for config in self._configurators if (config._section.lower().startswith(sectionName))] + + if (len(configurators) == 0): + self.LogError("{RED}No configuration named '{0}' found.{NOCOLOR}".format(toolChain, **Init.Foreground)) + return + + self._WriteConfigurationHeader() + self._ConfigureTools(configurators) + + # Write and re-read configuration + if self._saveConfiguration: + self._host.SaveAndReloadPoCConfiguration() + + def InitializeConfiguration(self): + """Initialize PoC's configuration with empty sections. + + The list of sections is gathered from all enabled configurators' + :py:data:`_template` fields. + """ + warningWasWritten = CallByRefBoolParam(False) + for configurator in self._configurators: + configurator.PrepareSections(warningWasWritten, writeWarnings=False) + + def UpdateConfiguration(self): + """Update an existing configuration e.g. after a PoC update.""" + warningWasWritten = CallByRefBoolParam(False) + for configurator in self._configurators: + configurator.PrepareSections(warningWasWritten) + + configured = configurator.IsConfigured() + if configured: + configurator.PrepareOptions() + + # pocSections = set([sectionName for sectionName in self._host.PoCConfig]) + # configSections = set([sectionName for config in Configurations for sectionName in config.GetSections(self._host.Platform)]) # FIXME: what about the ALL platform? + # delSections = pocSections.difference(configSections) + + # if delSections: + # for sectionName in delSections: + # self._host.PoCConfig.remove_section(sectionName) + + def _ConfigureTools(self, configurators): + """Run the configuration routines for a list of configurators""" + self.LogNormal("{CYAN}Configuring installed tools\n---------------------------{NOCOLOR}".format(**Init.Foreground)) + + # Configure each vendor or tool of a tool chain + for configurator in configurators: + # Skip configuration with unsupported platforms + if (not configurator.IsSupportedPlatform()): + configurator.ClearSection() + continue + + # Skip configuration if dependency is not fulfilled + if (not configurator.CheckDependency()): + configurator.ClearSection() + continue + + # Start configuration + self.LogNormal("{DARK_CYAN}Configuring {0!s}{NOCOLOR}".format(configurator, **Init.Foreground)) + + # Start configuration loop for the current configurator + try: + self._ConfigurationLoop(configurator) + except KeyboardInterrupt: + self._saveConfiguration = False + self.LogNormal("\n\n{RED}Abort configuration.\nNo files have been created or changed.{NOCOLOR}".format(**Init.Foreground)) + return + + # TODO: move to host instance + # Print the currently collected configuration if in debug mode + if (self.Logger.LogLevel is Severity.Debug): + self.LogDebug("-" * 40, indent=1) + for sectionName in self._host.PoCConfig.sections(): + if (not sectionName.startswith("INSTALL")): + continue + self.LogDebug("[{0}]".format(sectionName), indent=1) + configSection = self._host.PoCConfig[sectionName] + for optionName in configSection: + optionRaw = self._host.PoCConfig.get(sectionName, optionName, raw=True) + try: + optionValue = configSection[optionName] + except Exception: + optionValue = "-- ERROR --" + + self.LogDebug("{0: <23} {1: <90} {2}".format(optionName + " =", optionRaw, optionValue), indent=2) + self.LogDebug("-" * 40, indent=1) + + # TODO: MultiVersion installations? + + self.LogNormal("") + if self._AskConfigureDefaultTools(): + self._ConfigureDefaultTools() + else: + self.LogWarning("You can rerun this configuration step with '.\poc.ps1 configure --set-default-tools'.", indent=1) + + # Write and re-read configuration + self._host.SaveAndReloadPoCConfiguration() + + # Run post-configuration tasks + self.LogNormal("{DARK_CYAN}Running post configuration tasks{NOCOLOR}".format(**Init.Foreground)) + for configurator in configurators: + configurator.RunPostConfigurationTasks() + + def _ConfigurationLoop(self, configurator): + """Retry to configure a vendor or tool until it succeeds or the user presses + :kbd:`P` to pass a configuration step. + + A :py:exec:`KeyboardInterrupt` should be handled in a calling method. + """ + while True: + # Copy all options for a configurator's sections from _template into PoCConfig + configurator.PrepareOptions(writeWarnings=False) + + try: + if (self._host.Platform == "Darwin"): configurator.ConfigureForDarwin() + elif (self._host.Platform == "Linux"): configurator.ConfigureForLinux() + elif (self._host.Platform == "Windows"): configurator.ConfigureForWindows() + + break + except SkipConfigurationException: + break + except ExceptionBase as ex: + print(" {RED}FAULT: {0}{NOCOLOR}".format(ex.message, **Init.Foreground))# Print the currently collected configuration if in debug mode + + def ConfigureDefaultTools(self): + self._WriteConfigurationHeader() + self._ConfigureDefaultTools() + + # Write and re-read configuration + if self._saveConfiguration: + self._host.SaveAndReloadPoCConfiguration() + + def _ConfigureDefaultTools(self): + self.LogNormal("{CYAN}Choosing default tools\n----------------------{NOCOLOR}".format(**Init.Foreground)) + for selector in self._selectors: + self._host.LogNormal("{DARK_CYAN}Selecting {0} installation{NOCOLOR}".format(selector._toolName, **Init.Foreground)) + try: + selector.Select() + except KeyboardInterrupt: + self._saveConfiguration = False + self.LogNormal("\n\n{RED}Abort configuration.\nNo files have been created or changed.{NOCOLOR}".format(**Init.Foreground)) + return + + def _WriteConfigurationHeader(self): + """Write a header containing general information about the configuration + and list allowed input values for yes/no/pass questions. + """ + # self.LogVerbose("starting manual configuration...") + self.LogNormal("Explanation of abbreviations:") + self.LogNormal(" {YELLOW}Y{NOCOLOR} - yes {YELLOW}P{NOCOLOR} - pass (jump to next question)".format(**Init.Foreground)) + self.LogNormal(" {YELLOW}N{NOCOLOR} - no {YELLOW}Ctrl + C{NOCOLOR} - abort (no changes are saved)".format(**Init.Foreground)) + self.LogNormal("Upper case or value in '[...]' means default value") + self.LogNormal("-" * 80) + self.LogNormal("") + + def _AskConfigureDefaultTools(self): + """Ask if default tools should be configured now.""" + while True: + configureDefaultTools = self._Ask("Configure default tools?", default="Y", afterDefault="/n", indent=0) + if (configureDefaultTools in ['n', 'N']): + return False + elif (configureDefaultTools in ['y', 'Y']): + return True + else: + self.LogNormal("Unsupported choice '{0}'".format(configureDefaultTools)) diff --git a/py/Wrapper/Lattice.Diamond.sh b/py/Wrapper/Lattice.Diamond.sh index 0c1bc2ce..a7d6c766 100644 --- a/py/Wrapper/Lattice.Diamond.sh +++ b/py/Wrapper/Lattice.Diamond.sh @@ -3,14 +3,9 @@ # kate: tab-width 2; replace-tabs off; indent-width 2; # # ============================================================================== -# Authors: Patrick Lehmann +# Authors: Patrick Lehmann # -# BashModule: -# -# Description: -# ------------------------------------ -# TODO: -# - +# BashModule: Create an environment for Lattice Diamond # # License: # ============================================================================== @@ -53,7 +48,7 @@ OpenEnvironment() { echo 1>&2 -e "${RED}Run 'PoC.py configure' to configure your Lattice Diamond installation.${NOCOLOR}" return 1 fi - # QUESTION: move into PoC.py query like ISESettingsFile ? + # QUESTION: Move into PoC.py query like ISESettingsFile ? Diamond_SettingsFile=$Diamond_BinDir/diamond_env if [ ! -f "$Diamond_SettingsFile" ]; then echo 1>&2 -e "${RED}Lattice Diamond settings file not found.${NOCOLOR}" diff --git a/py/Wrapper/PoC.psm1 b/py/Wrapper/PoC.psm1 index 6336b5a3..6579af3a 100644 --- a/py/Wrapper/PoC.psm1 +++ b/py/Wrapper/PoC.psm1 @@ -154,12 +154,12 @@ $PoC_Environments = @{ "PSModule" = "Mentor.PrecisionRTL.psm1"; "PreHookFile" = "Mentor.PrecisionRTL.pre.ps1"; "PostHookFile" = "Mentor.PrecisionRTL.post.ps1"}; - "ModelSimPE" = @{ + "ModelSim" = @{ "Load" = $false; "Commands" = @("vsim", "msim"); - "PSModule" = "Mentor.ModelSimPE.psm1"; - "PreHookFile" = "Mentor.ModelSimPE.pre.ps1"; - "PostHookFile" = "Mentor.ModelSimPE.post.ps1"}; + "PSModule" = "Mentor.ModelSim.psm1"; + "PreHookFile" = "Mentor.ModelSim.pre.ps1"; + "PostHookFile" = "Mentor.ModelSim.post.ps1"}; "QuestaSim" = @{ "Load" = $false; "Commands" = @("vsim", "qsim"); diff --git a/py/Wrapper/wrapper.sh b/py/Wrapper/wrapper.sh index 1eaaab05..384b8a84 100644 --- a/py/Wrapper/wrapper.sh +++ b/py/Wrapper/wrapper.sh @@ -3,9 +3,9 @@ # kate: tab-width 2; replace-tabs off; indent-width 2; # # ============================================================================== -# Authors: Patrick Lehmann -# Thomas B. Preusser -# Martin Zabel +# Authors: Patrick Lehmann +# Thomas B. Preusser +# Martin Zabel # # Bash Script: Wrapper Script to execute a given Python script # @@ -42,9 +42,9 @@ PoC_WrapperDirectory="$PoC_PythonScriptDir/Wrapper" PoC_HookDirectory="$PoC_WrapperDirectory/Hooks" # define color escape codes -RED='\e[0;31m' # Red -YELLOW='\e[1;33m' # Yellow -NOCOLOR='\e[0m' # No Color +ANSI_RED='\e[0;31m' # Red +ANSI_YELLOW='\e[1;33m' # Yellow +ANSI_NOCOLOR='\e[0m' # No Color # set default values PyWrapper_Debug=0 @@ -126,7 +126,7 @@ declare -A Env_Lattice_ActiveHDL=( declare -A Env_Mentor=( ["PreHookFile"]="Mentor.pre.sh" ["PostHookFile"]="Mentor.post.sh" - ["Tools"]="PrecisionRTL ModelSimPE QuestaSim" + ["Tools"]="PrecisionRTL QuestaSim" ) declare -A Env_Mentor_PrecisionRTL=( ["Load"]=0 @@ -135,12 +135,12 @@ declare -A Env_Mentor_PrecisionRTL=( ["PreHookFile"]="Mentor.PrecisionRTL.pre.sh" ["PostHookFile"]="Mentor.PrecisionRTL.post.sh" ) -declare -A Env_Mentor_ModelSimPE=( +declare -A Env_Mentor_ModelSim=( ["Load"]=0 ["Commands"]="vsim" - ["BashModule"]="Mentor.ModelSimPE.sh" - ["PreHookFile"]="Mentor.ModelSimPE.pre.sh" - ["PostHookFile"]="Mentor.ModelSimPE.post.sh" + ["BashModule"]="Mentor.ModelSim.sh" + ["PreHookFile"]="Mentor.ModelSim.pre.sh" + ["PostHookFile"]="Mentor.ModelSim.post.sh" ) declare -A Env_Mentor_QuestaSim=( ["Load"]=0 @@ -233,19 +233,19 @@ export PoCRootDirectory=$PoC_RootDir export PoCWorkingDirectory=$PoC_WorkingDir if [ $PyWrapper_Debug -eq 1 ]; then - echo -e "${YELLOW}This is the PoC Library script wrapper operating in debug mode.${NOCOLOR}" + echo -e "${ANSI_YELLOW}This is the PoC Library script wrapper operating in debug mode.${ANSI_NOCOLOR}" echo - echo -e "${YELLOW}Directories:${NOCOLOR}" - echo -e "${YELLOW} PoC root: $PoC_RootDir${NOCOLOR}" - echo -e "${YELLOW} working: $PoC_WorkingDir${NOCOLOR}" - echo -e "${YELLOW}Script:${NOCOLOR}" - echo -e "${YELLOW} Filename: $PyWrapper_Script${NOCOLOR}" - echo -e "${YELLOW} Solution: $PyWrapper_Solution${NOCOLOR}" - echo -e "${YELLOW} Parameters: $PyWrapper_Parameters${NOCOLOR}" - echo -e "${YELLOW}Load Environment: ${NOCOLOR}" - echo -e "${YELLOW} Lattice Diamond: ${Env_Lattice_Diamond["Load"]}${NOCOLOR}" - echo -e "${YELLOW} Xilinx ISE: ${Env_Xilinx_ISE["Load"]}${NOCOLOR}" - echo -e "${YELLOW} Xilinx VIVADO: ${Env_Xilinx_Vivado["Load"]}${NOCOLOR}" + echo -e "${ANSI_YELLOW}Directories:${ANSI_NOCOLOR}" + echo -e "${ANSI_YELLOW} PoC root: $PoC_RootDir${ANSI_NOCOLOR}" + echo -e "${ANSI_YELLOW} working: $PoC_WorkingDir${ANSI_NOCOLOR}" + echo -e "${ANSI_YELLOW}Script:${ANSI_NOCOLOR}" + echo -e "${ANSI_YELLOW} Filename: $PyWrapper_Script${ANSI_NOCOLOR}" + echo -e "${ANSI_YELLOW} Solution: $PyWrapper_Solution${ANSI_NOCOLOR}" + echo -e "${ANSI_YELLOW} Parameters: $PyWrapper_Parameters${ANSI_NOCOLOR}" + echo -e "${ANSI_YELLOW}Load Environment: ${ANSI_NOCOLOR}" + echo -e "${ANSI_YELLOW} Lattice Diamond: ${Env_Lattice_Diamond["Load"]}${ANSI_NOCOLOR}" + echo -e "${ANSI_YELLOW} Xilinx ISE: ${Env_Xilinx_ISE["Load"]}${ANSI_NOCOLOR}" + echo -e "${ANSI_YELLOW} Xilinx VIVADO: ${Env_Xilinx_Vivado["Load"]}${ANSI_NOCOLOR}" echo fi @@ -254,7 +254,7 @@ Python_VersionTest='import sys; sys.exit(not (0x03050000 < sys.hexversion < 0x04 python -c "$Python_VersionTest" 2>/dev/null if [ $? -eq 0 ]; then Python_Interpreter=$(which python 2>/dev/null) - test $PyWrapper_Debug -eq 1 && echo -e "${YELLOW}PythonInterpreter: use standard interpreter: '$Python_Interpreter'${NOCOLOR}" + test $PyWrapper_Debug -eq 1 && echo -e "${ANSI_YELLOW}PythonInterpreter: use standard interpreter: '$Python_Interpreter'${ANSI_NOCOLOR}" else # standard python interpreter is not suitable, try to find a suitable version manually for pyVersion in 3.9 3.8 3.7 3.6 3.5; do @@ -266,12 +266,12 @@ else if [ $? -eq 0 ]; then break; fi fi done - test $PyWrapper_Debug -eq 1 && echo -e "${YELLOW}PythonInterpreter: use this interpreter: '$Python_Interpreter'${NOCOLOR}" + test $PyWrapper_Debug -eq 1 && echo -e "${ANSI_YELLOW}PythonInterpreter: use this interpreter: '$Python_Interpreter'${ANSI_NOCOLOR}" fi # if no interpreter was found => exit if [ -z "$Python_Interpreter" ]; then - echo 1>&2 -e "${RED}No suitable Python interpreter found.${NOCOLOR}" - echo 1>&2 -e "${RED}The script requires Python >= $PyWrapper_MinVersion${NOCOLOR}" + echo 1>&2 -e "${ANSI_RED}No suitable Python interpreter found.${ANSI_NOCOLOR}" + echo 1>&2 -e "${ANSI_RED}The script requires Python >= $PyWrapper_MinVersion${ANSI_NOCOLOR}" PoC_ExitCode=1 fi @@ -315,8 +315,8 @@ if [ $PoC_ExitCode -eq 0 ]; then fi if [ $PyWrapper_Debug -eq 1 ]; then - echo -e "${YELLOW}Launching: '$Python_Interpreter $Python_Script $Python_ScriptParameters'${NOCOLOR}" - echo -e "${YELLOW}------------------------------------------------------------${NOCOLOR}" + echo -e "${ANSI_YELLOW}Launching: '$Python_Interpreter $Python_Script $Python_ScriptParameters'${ANSI_NOCOLOR}" + echo -e "${ANSI_YELLOW}------------------------------------------------------------${ANSI_NOCOLOR}" fi # launching python script diff --git a/py/__init__.py b/py/__init__.py index 228b0ae3..932cf54e 100644 --- a/py/__init__.py +++ b/py/__init__.py @@ -7,11 +7,6 @@ # # Python Sub Module: Saves The PoC-Library configuration as python source code. # -# Description: -# ------------------------------------ -# TODO: -# -# # License: # ============================================================================== # Copyright 2007-2015 Technische Universitaet Dresden - Germany @@ -30,12 +25,3 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Repository Service Tool") - -# load dependencies diff --git a/py/config.boards.ini b/py/config.boards.ini index 218b1f08..f745779e 100644 --- a/py/config.boards.ini +++ b/py/config.boards.ini @@ -3,9 +3,9 @@ # kate: tab-width 2replace-tabs offindent-width 2; # # ============================================================================== -# Authors: Patrick Lehmann +# Authors: Patrick Lehmann # -# Supported boards: This file stores all supported boards and it's settings. +# Supported Boards: This file stores all supported boards and it's settings. # # Description: # ------------------------------------ @@ -50,7 +50,9 @@ S3SK = BOARD.S3SK200 S3SK200 = BOARD.S3SK200 S3SK500 = BOARD.S3SK500 S3SK1000 = BOARD.S3SK1000 -S3SK1600 = BOARD.S3SK1600 +S3ESK = BOARD.S3ESK500 +S3ESK500 = BOARD.S3ESK500 +S3ESK1600 = BOARD.S3ESK1600 ML505 = BOARD.ML505 ML506 = BOARD.ML505 ML507 = BOARD.ML507 @@ -82,16 +84,19 @@ FPGA = EP5SGXEA7N2F45C2 FPGA = LFE5UM-45F-6BG381C [BOARD.S3SK200] -FPGA = XC3S200FT256 +FPGA = XC3S200-4FT256 [BOARD.S3SK500] -FPGA = XC3S500FT256 +FPGA = XC3S500-4FT256 [BOARD.S3SK1000] -FPGA = XC3S1000FT256 +FPGA = XC3S1000-4FT256 -[BOARD.S3SK1600] -FPGA = XC3S1600FT256 +[BOARD.S3ESK500] +FPGA = XC3S500E-4FG320 + +[BOARD.S3ESK1600] +FPGA = XC3S1600E-4FG320 [BOARD.ML505] FPGA = XC5VLX50T-1FF1136 diff --git a/py/config.entity.ini b/py/config.entity.ini index bd492aec..eb362825 100644 --- a/py/config.entity.ini +++ b/py/config.entity.ini @@ -541,6 +541,8 @@ HDLParameters = A_BITS=12; D_BITS=16 # PoC.mem.sdram # ------------------------------------------------------------------------------ [IP.mem.sdram.ctrl_s3esk] +nl = XSTNetlist +[XST.mem.sdram.ctrl_s3esk.nl] [IP.mem.sdram.ctrl_de0] @@ -873,7 +875,12 @@ PostReplaceRules = ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.vhdl :: tb = VHDLTestbench [TB.sim.ClockGenerator.tb] +[IP.sim.VCDParser] +tb = VHDLTestbench +[TB.sim.VCDParser.tb] + [IP.sim.Waveform] +Visibility = Private tb = VHDLTestbench [TB.sim.Waveform.tb] diff --git a/py/config.structure.ini b/py/config.structure.ini index 37bb8175..4ef1f0a0 100644 --- a/py/config.structure.ini +++ b/py/config.structure.ini @@ -354,6 +354,9 @@ Wrapper = Entity [PoC.sim] +ClockGenerator = Entity +VCDParser = Entity +Waveform = Entity [PoC.sort] sortnet = Namespace diff --git a/py/lib/CodeDOM.py b/py/lib/CodeDOM.py index 2104d166..05e9d9c7 100644 --- a/py/lib/CodeDOM.py +++ b/py/lib/CodeDOM.py @@ -8,10 +8,6 @@ # # Python Module: TODO # -# Description: -# ------------------------------------ -# TODO: -# # License: # ============================================================================== # Copyright 2007-2016 Patrick Lehmann - Dresden, Germany @@ -152,7 +148,7 @@ def Parse(cls, string, printChar): if printChar: print("{BLUE}{token!s}{NOCOLOR}".format(token=token, **Init.Foreground)) parser.send(token) - # XXX: print("send empty token") + # FIXME: print("send empty token") parser.send(None) except MatchingParserResult as ex: return ex.value diff --git a/py/lib/Decorators.py b/py/lib/Decorators.py index 2e0ad17c..805f7f90 100644 --- a/py/lib/Decorators.py +++ b/py/lib/Decorators.py @@ -8,10 +8,6 @@ # # Python functions: Auxillary functions to exit a program and report an error message. # -# Description: -# ------------------------------------ -# TODO: -# # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany diff --git a/py/lib/ExtendedConfigParser/__init__.py b/py/lib/ExtendedConfigParser/__init__.py index 53dcf847..499b0f75 100644 --- a/py/lib/ExtendedConfigParser/__init__.py +++ b/py/lib/ExtendedConfigParser/__init__.py @@ -57,6 +57,9 @@ def __getitem__(self, key): raise KeyError(self._name + ":" + key) return self._parser.get(self._name, key) + def __setitem__(self, key, value): + super().__setitem__(key, value) + self.parser.Interpolation.clear_cache() # WORKAROUND: Required for ReadTheDocs, which doesn't support Python 3.5 yet. if (version_info < (3,5,0)): @@ -331,6 +334,11 @@ def __init__(self, defaults=None, dict_type=_default_dict, allow_no_value=False, elif (interpolation is _UNSET): self._interpolation = ExtendedInterpolation() else: self._interpolation = interpolation + def clear(self): + super().clear() + if isinstance(self._interpolation, ExtendedInterpolation): + self._interpolation.clear_cache() + @property def Interpolation(self): return self._interpolation diff --git a/py/lib/Functions.py b/py/lib/Functions.py index a3850696..1d1f2394 100644 --- a/py/lib/Functions.py +++ b/py/lib/Functions.py @@ -6,11 +6,7 @@ # Authors: Patrick Lehmann # Thomas B. Preusser # -# Python functions: Auxillary functions to exit a program and report an error message. -# -# Description: -# ------------------------------------ -# TODO: +# Python functions: Auxillary functions to exit a program and report an error message. # # License: # ============================================================================== @@ -31,9 +27,9 @@ # ============================================================================== # # load dependencies -from functools import reduce -from operator import or_ -from sys import version_info +from functools import reduce +from operator import or_ +from sys import version_info __api__ = [ @@ -53,7 +49,17 @@ def merge_with(f, *dicts): """Merge 2 or more dictionaries. Apply function f to each element during merge.""" return {k : reduce(lambda x: f(*x) if (len(x) > 1) else x[0])([ d[k] for d in dicts if k in d ]) for k in reduce(or_, map(lambda x: x.keys(), dicts), set()) } + class CallByRefParam: + """Implements a "call by reference" parameter. + + .. seealso:: + + :py:class:`CallByRefBoolParam` + A special "call by reference" implementation for boolean reference types. + :py:class:`CallByRefIntParam` + A special "call by reference" implementation for integer reference types. + """ def __init__(self, value=None): self.value = value @@ -63,19 +69,63 @@ def __ilshift__(self, other): def __eq__(self, other): return self.value == other def __ne__(self, other): return self.value != other - def __lt__(self, other): return self.value < other + def __repr__(self): return repr(self.value) + def __str__(self): return str(self.value) + + +class CallByRefBoolParam(CallByRefParam): + """A special "call by reference" implementation for boolean reference types.""" + # unary operators + def __neg__(self): return not self.value + + # binary operators - logical + def __and__(self, other): return self.value and other + def __or__(self, other): return self.value or other + + # binary inplace operators + def __iand__(self, other): + self.value = self.value and other + return self + def __ior__(self, other): + self.value = self.value or other + return self + + # type conversion operators + def __bool__(self): return self.value + def __int__(self): return int(self.value) + +class CallByRefIntParam(CallByRefParam): + """A special "call by reference" implementation for integer reference types.""" + + # unary operators + def __neg__(self): return not self.value + + # binary operators - arithmetic + def __add__(self, other): return self.value + other + def __sub__(self, other): return self.value - other + def __truediv__(self, other): return self.value / other + def __mul__(self, other): return self.value * other + def __mod__(self, other): return self.value % other + def __pow__(self, other): return self.value ** other + + # binary operators - comparison + def __eq__(self, other): return self.value == other + def __ne__(self, other): return self.value != other + def __lt__(self, other): return self.value < other def __le__(self, other): return self.value <= other - def __gt__(self, other): return self.value > other + def __gt__(self, other): return self.value > other def __ge__(self, other): return self.value >= other - def __neg__(self): return not self.value + + # type conversion operators + def __bool__(self): return bool(self.value) + def __int__(self): return self.value class Init: @classmethod def init(cls): - from colorama import init - init() - from colorama import Back as Background + from colorama import init, Back as Background + init()#strip=False) print(Background.BLACK, end="") from colorama import Fore as Foreground @@ -114,26 +164,6 @@ def versionCheck(cls, version): print(" Minimal required Python version is {version}".format(version=".".join(version))) cls.exit(1) - @classmethod - def printThisIsNoExecutableFile(cls, message): - Init.init() - print("=" * 80) - print("{: ^80s}".format(message)) - print("=" * 80) - print() - print("{RED}ERROR:{NOCOLOR} This is not a executable file!".format(**Init.Foreground)) - cls.exit(1) - - @classmethod - def printThisIsNoLibraryFile(cls, message): - Init.init() - print("=" * 80) - print("{: ^80s}".format(message)) - print("=" * 80) - print() - print("{RED}ERROR:{NOCOLOR} This is not a library file!".format(**Init.Foreground)) - cls.exit(1) - @classmethod def printException(cls, ex): from traceback import print_tb, walk_tb @@ -145,9 +175,9 @@ def printException(cls, ex): filename = frame.f_code.co_filename funcName = frame.f_code.co_name print("{YELLOW} Caused by:{NOCOLOR} {function} in file '{filename}' at line {line}".format(function=funcName, filename=filename, line=sourceLine, **Init.Foreground)) - print("-" * 80) + print(("{RED}" + ("-" * 80) + "{NOCOLOR}").format(**Init.Foreground)) print_tb(ex.__traceback__) - print("-" * 80) + print(("{RED}" + ("-" * 80) + "{NOCOLOR}").format(**Init.Foreground)) Exit.exit(1) @classmethod @@ -161,7 +191,7 @@ def printNotImplementedError(cls, ex): Exit.exit(1) @classmethod - def printExceptionbase(cls, ex): + def printExceptionBase(cls, ex): Init.init() print("{RED}ERROR:{NOCOLOR} {message}".format(message=ex.message, **Init.Foreground)) Exit.exit(1) diff --git a/py/lib/Parser.py b/py/lib/Parser.py index c3522b45..2eba8bf5 100644 --- a/py/lib/Parser.py +++ b/py/lib/Parser.py @@ -7,10 +7,6 @@ # # Python Module: TODO # -# Description: -# ------------------------------------ -# TODO: -# # License: # ============================================================================== # Copyright 2007-2016 Patrick Lehmann - Dresden, Germany diff --git a/py/lib/SphinxExtensions/__init__.py b/py/lib/SphinxExtensions/__init__.py index 9c065ea9..9a128347 100644 --- a/py/lib/SphinxExtensions/__init__.py +++ b/py/lib/SphinxExtensions/__init__.py @@ -7,10 +7,6 @@ # # Python Module: # -# Description: -# ------------------------------------ -# - TODO -# # License: # ============================================================================== # Copyright 2007-2016 Patrick Lehmann - Dresden, Germany diff --git a/py/lib/__init__.py b/py/lib/__init__.py index 228b0ae3..2af16472 100644 --- a/py/lib/__init__.py +++ b/py/lib/__init__.py @@ -7,11 +7,6 @@ # # Python Sub Module: Saves The PoC-Library configuration as python source code. # -# Description: -# ------------------------------------ -# TODO: -# -# # License: # ============================================================================== # Copyright 2007-2015 Technische Universitaet Dresden - Germany @@ -30,12 +25,4 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Repository Service Tool") - # load dependencies diff --git a/py/lib/pyAttribute/ArgParseAttributes.py b/py/lib/pyAttribute/ArgParseAttributes.py index 715319af..5a7d1bf4 100644 --- a/py/lib/pyAttribute/ArgParseAttributes.py +++ b/py/lib/pyAttribute/ArgParseAttributes.py @@ -15,10 +15,6 @@ # # Python module: pyAttributes for ArgParse # -# Description: -# ------------------------------------ -# TODO -# # License: # ============================================================================ # Copyright 2007-2016 Patrick Lehmann - Dresden, Germany diff --git a/py/lib/pyAttribute/__init__.py b/py/lib/pyAttribute/__init__.py index 0d8019a7..f6e77d2f 100644 --- a/py/lib/pyAttribute/__init__.py +++ b/py/lib/pyAttribute/__init__.py @@ -15,10 +15,6 @@ # # Python package: pyAttribute Implementation # -# Description: -# ------------------------------------ -# TODO -# # License: # ============================================================================ # Copyright 2007-2016 Patrick Lehmann - Dresden, Germany diff --git a/src/common/config.vhdl b/src/common/config.vhdl index 6952d5c1..854ec5a4 100644 --- a/src/common/config.vhdl +++ b/src/common/config.vhdl @@ -211,25 +211,25 @@ package body config_private is -- ========================================================================= ( BoardName => conf("S3SK200"), - FPGADevice => conf("XC3S200FT256"), -- XC2S200FT256 + FPGADevice => conf("XC3S200-4FT256"), -- XC3S200-4FT256 UART => C_BOARD_UART_EMPTY, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ),( - BoardName => conf("S3ESK500"), - FPGADevice => conf("XC3S500EFT256"), -- XC2S500FT256 + BoardName => conf("S3SK1000"), + FPGADevice => conf("XC3S1000-4FT256"), -- XC2S1000-4FT256 UART => C_BOARD_UART_EMPTY, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ),( - BoardName => conf("S3SK1000"), - FPGADevice => conf("XC3S1000FT256"), -- XC2S1000FT256 + BoardName => conf("S3ESK500"), + FPGADevice => conf("XC3S500E-4FG320"), -- XC3S500E-4FG320 UART => C_BOARD_UART_EMPTY, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ),( BoardName => conf("S3ESK1600"), - FPGADevice => conf("XC3S1600EFT256"), -- XC2S1600FT256 + FPGADevice => conf("XC3S1600E-4FG320"), -- XC3S1600E-4FG320 UART => C_BOARD_UART_EMPTY, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 diff --git a/src/mem/sdram/sdram_ctrl_s3esk.files b/src/mem/sdram/sdram_ctrl_s3esk.files index 6fca803f..a83489a2 100644 --- a/src/mem/sdram/sdram_ctrl_s3esk.files +++ b/src/mem/sdram/sdram_ctrl_s3esk.files @@ -10,9 +10,9 @@ include "src/common/common.files" # load common packages # PoC.mem.sdram if (DeviceVendor = "Xilinx") then include "lib/Xilinx.files" # Xilinx primitives - vhdl poc "src/mem/ocram/sdram_ctrl_phy_s3esk.vhdl" # Physical layer abstraction for the Terrasic DE0 board - vhdl poc "src/mem/ocram/sdram_ctrl_fsm.vhdl" # SDR/DDR SDRAM controller FSM - vhdl poc "src/mem/ocram/sdram_ctrl_s3esk.vhdl" # Top-Level + vhdl poc "src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl" # Physical layer abstraction for the Spartan-3E Starter Kit board + vhdl poc "src/mem/sdram/sdram_ctrl_fsm.vhdl" # SDR/DDR SDRAM controller FSM + vhdl poc "src/mem/sdram/sdram_ctrl_s3esk.vhdl" # Top-Level else report "This SDRAM controller supports only the 'Spartan-3E Starter Kit' board." end if diff --git a/src/sim/sim_VCDParser.vhdl b/src/sim/sim_VCDParser.vhdl new file mode 100644 index 00000000..a9381b4c --- /dev/null +++ b/src/sim/sim_VCDParser.vhdl @@ -0,0 +1,115 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Patrick Lehmann +-- +-- Package: A parser for VCD files. +-- +-- Description: +-- ------------------------------------- +-- This function package parses *.VCD files and drives simulation stimulies. +-- +-- * "VCD_ReadHeader" reads the file header. +-- * "VCD_ReadLine" reads a line from *.vcd file. +-- * "VCD_Read_StdLogic" parses a vcd one bit value to std_logic. +-- * "VCD_Read_StdLogicVector" parses a vcd N bit value to std_logic_vector with N bits. +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany +-- Chair of VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= +-- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_TEXTIO.all; +use IEEE.NUMERIC_STD.all; +use STD.TEXTIO.all; + +library PoC; +use PoC.utils.all; +use PoC.strings.all; + + +package sim_VCDParser is + subtype T_VCDLINE is string(1 to 80); + + procedure VCD_ReadHeader(file VCDFile : TEXT; VCDLine : inout T_VCDLINE); + procedure VCD_ReadLine(file VCDFile : TEXT; VCDLine : out string); + + procedure VCD_Read_StdLogic(VCDLine : string; signal sl : out std_logic; WaveName : string); + procedure VCD_Read_StdLogicVector(VCDLine : string; signal slv : out std_logic_vector; WaveName : string; def : std_logic := '0'); + +end package; + + +package body sim_VCDParser is + procedure VCD_ReadHeader(file VCDFile : TEXT; VCDLine : inout T_VCDLINE) is + begin + while not endfile(VCDFile) loop + VCD_ReadLine(VCDFile, VCDLine); + exit when (VCDLine(1) = '#'); + end loop; + end procedure; + + procedure VCD_ReadLine(file VCDFile : TEXT; VCDLine : out string) is + variable vcdFileLine : LINE; + variable char : character; + variable isString : boolean; + begin + readline(VCDFile, vcdFileLine); + + -- clear VCDLine + VCDLine := (VCDLine'range => C_POC_NUL); + + -- TODO: use imin of ranges, not 'range + for i in VCDLine'range loop + read(vcdFileLine, char, isString); + exit when not isString; + VCDLine(I) := char; + end loop; + end procedure; + + procedure VCD_Read_StdLogic(VCDLine : string; signal sl : out std_logic; WaveName : string) is + constant length : natural := str_length(VCDLine); + begin + if (str_equal(VCDLine(2 to length), WaveName)) then + sl <= to_sl(VCDLine(1)); + end if; + end procedure; + + procedure VCD_Read_StdLogicVector(VCDLine : string; signal slv : out std_logic_vector; WaveName : string; def : std_logic := '0') is + constant length : natural := str_length(VCDLine); + variable Result : std_logic_vector(slv'range); + variable k : natural; + begin + Result := (others => def); + k := 0; + + for i in 2 to length loop + if not is_sl(VCDLine(i)) then + k := i; + exit; + else + Result := Result(Result'high - 1 downto Result'low) & to_sl(VCDLine(i)); + end if; + end loop; + + if (str_equal(VCDLine(k + 1 to length), WaveName)) then + slv <= Result; + end if; + end procedure; +end package body; diff --git a/tb/common/my_config.files b/tb/common/my_config.files index 5b06bd5f..e8921c9a 100644 --- a/tb/common/my_config.files +++ b/tb/common/my_config.files @@ -57,6 +57,10 @@ elseif (BoardName = "ECP5Versa") then elseif (BoardName = "S3SK1000") then vhdl poc "tb/common/my_config_S3SK1000.vhdl" +# Spartan-3E boards +elseif (BoardName = "S3ESK500") then + vhdl poc "tb/common/my_config_S3ESK500.vhdl" + # Spartan-6 boards elseif (BoardName = "Atlys") then vhdl poc "tb/common/my_config_Atlys.vhdl" diff --git a/tb/common/my_config_S3ESK500.vhdl b/tb/common/my_config_S3ESK500.vhdl new file mode 100644 index 00000000..d497bbaa --- /dev/null +++ b/tb/common/my_config_S3ESK500.vhdl @@ -0,0 +1,51 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Package: Project specific configuration. +-- +-- Authors: Thomas B. Preusser +-- Martin Zabel +-- Patrick Lehmann +-- +-- Package: Project specific configuration. +-- +-- Description: +-- ------------ +-- This file was created from the template file: +-- +-- /src/common/my_config.template.vhdl +-- +-- and customized for: +-- +-- Spartan-3E Starter Kit with a XC3S500E FPGA +-- +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany, +-- Chair of VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + + +package my_config is + -- Change these lines to setup configuration. + constant MY_BOARD : string := "S3ESK500"; -- Spartan-3E Starter Kit + constant MY_DEVICE : string := "None"; + + -- For internal use only + constant MY_VERBOSE : boolean := true; +end package; diff --git a/tb/sim/sim_VCDParser_tb.files b/tb/sim/sim_VCDParser_tb.files new file mode 100644 index 00000000..566a42d0 --- /dev/null +++ b/tb/sim/sim_VCDParser_tb.files @@ -0,0 +1,12 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# ============================================================================== +# Note: all files are relative to PoC root directory +# +# Common PoC packages for configuration, synthesis and simulation +include "src/common/common.files" # Load common packages +vhdl PoC "src/sim/sim_VCDParser.vhdl" # VCD parser + +# Testbench file(s) +vhdl test "tb/sim/sim_VCDParser_tb.vhdl" # Testbench diff --git a/tb/sim/sim_VCDParser_tb.vcd b/tb/sim/sim_VCDParser_tb.vcd new file mode 100644 index 00000000..8373e02d --- /dev/null +++ b/tb/sim/sim_VCDParser_tb.vcd @@ -0,0 +1,57 @@ +$date + Apr 20, 2012 19:07:21 +$end +$version + ChipScope Pro Analyzer 13.4 O.87xd (Build 13400.12.7.126) +$end +$timescale + 1ns +$end + +$scope module sim_vcd_example_tb $end +$var wire 1 n0 ack $end +$var wire 1 n1 sof $end +$var wire 1 n2 eof $end +$var wire 8 n3 data $end +$var wire 1 n4 valid $end +$upscope $end +$enddefinitions $end + +#0 +0n0 +0n1 +0n2 +b0 n3 +0n4 +#2 +1n0 +#4 +1n1 +b1 n3 +1n4 +#5 +0n1 +b10 n3 +#6 +b11 n3 +#7 +b100 n3 +#8 +b101 n3 +#9 +0n0 +#12 +1n0 +b110 n3 +#13 +b111 n3 +#14 +1n2 +b1000 n3 +#15 +0n2 +b0 n3 +0n4 +#16 +0n0 +#17 \ No newline at end of file diff --git a/tb/sim/sim_VCDParser_tb.vhdl b/tb/sim/sim_VCDParser_tb.vhdl new file mode 100644 index 00000000..c15a71d0 --- /dev/null +++ b/tb/sim/sim_VCDParser_tb.vhdl @@ -0,0 +1,140 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Patrick Lehmann +-- +-- Testbench: A parser for VCD files. +-- +-- Description: +-- ------------------------------------- +-- +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany +-- Chair of VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= +-- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_TEXTIO.all; +use IEEE.NUMERIC_STD.all; +use STD.TEXTIO.all; + +library PoC; +use PoC.my_project.all; +use PoC.strings.all; +use PoC.physical.all; +-- simulation only packages +use PoC.sim_types.all; +use PoC.simulation.all; +use PoC.waveform.all; +use PoC.sim_VCDParser.all; + + +entity sim_VCDParser_tb is +end entity; + + +architecture tb of sim_VCDParser_tb is + constant CLOCK_FREQ : FREQ := 100 MHz; + + constant simTestID : T_SIM_TEST_ID := simCreateTest("Testing the VCD parser."); + + signal Clock : std_logic := '1'; + signal Reset : std_logic := '0'; + + signal valid : std_logic; + signal sof : std_logic; + signal eof : std_logic; + signal data : std_logic_vector(7 downto 0); + signal ack : std_logic; + +begin + -- initialize global simulation status + simInitialize; + -- generate global testbench clock and reset + simGenerateClock(simTestID, Clock, CLOCK_FREQ); + + VCDProcess: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "VCD reader process"); + + file VCDFile : TEXT; + variable VCDLine : T_VCDLINE; + + variable VCDTime : integer; + variable VCDTime_nx : integer; + + begin + Reset <= '0'; + simWaitUntilRisingEdge(Clock, 2); + + Reset <= '1'; + simWaitUntilRisingEdge(Clock, 1); + + Reset <= '0'; + simWaitUntilRisingEdge(Clock, 2); + + -- open *.vcd file and read header + file_open(VCDFile, MY_PROJECT_DIR & "tb/sim/sim_VCDParser_tb.vcd", READ_MODE); + VCD_ReadHeader(VCDFile, VCDLine); + + -- read initial stimuli values + -- ============================================================== + VCDTime := to_natural_dec(VCDLine(2 to str_length(VCDLine))); + if (VCDTime = -1) then + assert (FALSE) report "no positive after #-symbol!" & VCDLine severity FAILURE; + elsif (VCDTime /= 0) then + assert (FALSE) report "no initial stimuli" severity FAILURE; + end if; + + -- read waveform stimuli + -- ============================================================== + loop0 : while (not endfile(VCDFile)) loop + loop1 : while (not endfile(VCDFile)) loop + VCD_ReadLine(VCDFile, VCDLine); + + exit loop0 when endfile(VCDFile); + exit loop1 when (VCDLine(1) = '#'); + + if (VCDLine(1) = 'b') then + -- add binary vectors here + VCD_Read_StdLogicVector(VCDLine, data, "n3", '0'); + else + -- add single bit signals here + VCD_Read_StdLogic(VCDLine, valid, "n4"); + VCD_Read_StdLogic(VCDLine, sof, "n1"); + VCD_Read_StdLogic(VCDLine, eof, "n2"); + VCD_Read_StdLogic(VCDLine, ack, "n0"); + end if; + end loop; + + VCDTime_nx := to_natural_dec(VCDLine(2 to str_length(VCDLine))); + simWaitUntilRisingEdge(Clock, (VCDTime_nx - VCDTime)); + VCDTime := VCDTime_nx; + end loop; -- WHILE TRUE + + -- ============================================================== + -- close *.vcd-file + file_close(VCDFile); + + assert FALSE report "End of VCD file." severity WARNING; + + -- This process is finished + simDeactivateProcess(simProcessID); + wait; -- forever + end process; +end architecture; From 5251c41296eba0fa93505a18588acf468d6833fa Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 5 Dec 2016 11:09:32 +0100 Subject: [PATCH 88/97] Added one test in full debug mode. --- tools/Travis-CI/poc.run.sh | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tools/Travis-CI/poc.run.sh b/tools/Travis-CI/poc.run.sh index ab726359..f53e75a6 100755 --- a/tools/Travis-CI/poc.run.sh +++ b/tools/Travis-CI/poc.run.sh @@ -28,6 +28,15 @@ if grcat $TRAVIS_DIR/poc.run.grcrules/dev/null; then exec 1>&${COPROC[1]}- fi + +echo -e "Testing PoC infrastructure (1/1)..." +$POCROOT/poc.sh list-testbenches "PoC.*" + + +echo -e "Running one testbenche in debug mode..." +$POCROOT/poc.sh -d ghdl "PoC.arith.prng" + + echo -e "Running all testbenches..." mode=-q if [ "x$1" = 'x-d' -o "x$1" = 'x-v' ]; then From 6ddfc0a0aa90f54394b26440527601006a2792dd Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 5 Dec 2016 11:16:11 +0100 Subject: [PATCH 89/97] Debugging GCC on Travis-CI. --- tools/Travis-CI/ghdl.setup.sh | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tools/Travis-CI/ghdl.setup.sh b/tools/Travis-CI/ghdl.setup.sh index 8ca2c815..2c3eb6c6 100755 --- a/tools/Travis-CI/ghdl.setup.sh +++ b/tools/Travis-CI/ghdl.setup.sh @@ -69,6 +69,10 @@ fi # remove downloaded files rm $GHDL_TARBALL +# gcc debugging +echo -e "${CYAN}Testing GCC version and configuration...${NOCOLOR}" +gcc -v + # test ghdl version echo -e "${CYAN}Testing GHDL version...${NOCOLOR}" ./bin/ghdl -v From 13d0631674cb8fd4ed84d57777a082220140a593 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 5 Dec 2016 11:29:35 +0100 Subject: [PATCH 90/97] Disabled '-no-pie' flag for old GCC 4.8.4 on Travis. --- py/Simulator/GHDLSimulator.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/py/Simulator/GHDLSimulator.py b/py/Simulator/GHDLSimulator.py index 5c98f7ee..d342304f 100644 --- a/py/Simulator/GHDLSimulator.py +++ b/py/Simulator/GHDLSimulator.py @@ -151,7 +151,7 @@ def _RunElaboration(self, testbench): ghdl.Parameters[ghdl.SwitchVHDLLibrary] = VHDL_TESTBENCH_LIBRARY_NAME ghdl.Parameters[ghdl.ArgTopLevel] = testbench.ModuleName ghdl.Parameters[ghdl.FlagExplicit] = True - ghdl.Parameters[ghdl.SwitchLinkerOption] = ["-no-pie"] + # ghdl.Parameters[ghdl.SwitchLinkerOption] = ["-no-pie"] self._SetVHDLVersionAndIEEEFlavor(ghdl) self._SetExternalLibraryReferences(ghdl) From c272c648228834665a83592d5069836dbcf92679 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 5 Dec 2016 12:10:43 +0100 Subject: [PATCH 91/97] Fixed warnings and smells reported by Landscape.io. --- py/Compiler/__init__.py | 3 ++- py/PoC.py | 4 ++-- py/Simulator/ActiveHDLSimulator.py | 1 - py/Simulator/QuestaSimulator.py | 1 - py/ToolChains/__init__.py | 37 +++++++++++++++--------------- 5 files changed, 23 insertions(+), 23 deletions(-) diff --git a/py/Compiler/__init__.py b/py/Compiler/__init__.py index c458fc14..4b3bcf09 100644 --- a/py/Compiler/__init__.py +++ b/py/Compiler/__init__.py @@ -27,7 +27,7 @@ # from enum import unique, Enum from pathlib import Path -from re import compile as re_compile, IGNORECASE, MULTILINE, DOTALL, subn +from re import compile as re_compile, subn as re_subn, IGNORECASE as RE_IGNORECASE, MULTILINE as RE_MULTILINE, DOTALL as RE_DOTALL from shutil import copy as shutil_copy from flags import Flags @@ -109,6 +109,7 @@ class CompileSteps(Flags): Route = 1 << 9 WriteBitfile = 1 << 10 ShowReport = 1 << 15 + ShowGUI = 1 << 20 # Recompile = 1 << 25 # Resimulate = 1 << 26 # Review = 1 << 27 diff --git a/py/PoC.py b/py/PoC.py index 4ec7bd85..f900467a 100644 --- a/py/PoC.py +++ b/py/PoC.py @@ -46,7 +46,6 @@ from Base.Exceptions import ExceptionBase, CommonException, PlatformNotSupportedException, EnvironmentException, NotConfiguredException from Base.Logging import ILogable, Logger, Severity from Base.Project import VHDLVersion -from Simulator import SimulatorException, SimulationSteps, Simulator from Compiler.LSECompiler import Compiler as LSECompiler from Compiler.QuartusCompiler import Compiler as MapCompiler from Compiler.ISECompiler import Compiler as ISECompiler @@ -58,7 +57,7 @@ from DataBase.Config import Board from DataBase.Entity import NamespaceRoot, FQN, EntityTypes, WildCard, TestbenchKind, NetlistKind from DataBase.Solution import Repository -from Simulator import Simulator as BaseSimulator +from Simulator import Simulator as BaseSimulator, SimulatorException, SimulationSteps from Simulator.ActiveHDLSimulator import Simulator as ActiveHDLSimulator from Simulator.CocotbSimulator import Simulator as CocotbSimulator from Simulator.GHDLSimulator import Simulator as GHDLSimulator @@ -736,6 +735,7 @@ def _ExtractCompileSteps(guiMode, synthesize, showReport, cleanUp): compileSteps |= CompileSteps.Prepare & True #prepare compileSteps |= CompileSteps.Synthesize & synthesize compileSteps |= CompileSteps.ShowReport & showReport + compileSteps |= CompileSteps.ShowGUI & guiMode return compileSteps # ---------------------------------------------------------------------------- diff --git a/py/Simulator/ActiveHDLSimulator.py b/py/Simulator/ActiveHDLSimulator.py index eafb1b9e..ca197558 100644 --- a/py/Simulator/ActiveHDLSimulator.py +++ b/py/Simulator/ActiveHDLSimulator.py @@ -29,7 +29,6 @@ # load dependencies from pathlib import Path -from Base.Exceptions import NotConfiguredException from Base.Project import FileTypes, ToolChain, Tool from ToolChains.Aldec.ActiveHDL import ActiveHDL, ActiveHDLException from Simulator import VHDL_TESTBENCH_LIBRARY_NAME, SimulatorException, SkipableSimulatorException, SimulationSteps, Simulator as BaseSimulator diff --git a/py/Simulator/QuestaSimulator.py b/py/Simulator/QuestaSimulator.py index f62716a1..793d195c 100644 --- a/py/Simulator/QuestaSimulator.py +++ b/py/Simulator/QuestaSimulator.py @@ -30,7 +30,6 @@ from pathlib import Path from textwrap import dedent -from Base.Exceptions import NotConfiguredException from Base.Project import FileTypes, ToolChain, Tool from DataBase.Config import Vendors from ToolChains.Mentor.QuestaSim import QuestaSim, QuestaSimException diff --git a/py/ToolChains/__init__.py b/py/ToolChains/__init__.py index fb913655..31634e1b 100644 --- a/py/ToolChains/__init__.py +++ b/py/ToolChains/__init__.py @@ -41,18 +41,17 @@ 'ToolChainException', 'ConfigurationException', 'SkipConfigurationException', - 'ToolMixIn', - 'Configurations', - 'Configurator', 'ConfigurationState', 'ChangeState', + 'ToolMixIn', 'AskMixIn', 'Configuration', 'VendorConfiguration', 'ToolConfiguration', 'EditionDescription', 'Edition', - 'ToolSelector' + 'ToolSelector', + 'Configurator' ] __all__ = __api__ @@ -142,7 +141,6 @@ def _AskYes_NoPass(self, question, indent=1): def _PrintAvailableEditions(self, editions, selectedEdition): """Print all available editions and return the selected index.""" if (not isinstance(editions, (list, tuple))): - # if issubclass(editions, Edition): editions = list(editions) selectedIndex = 0 @@ -187,6 +185,11 @@ def State(self): """Return the configuration state.""" return self._state + @property + def SectionName(self): + """Return the configuration's section name.""" + return self._section + def IsSupportedPlatform(self): """Return true if the given platform is supported by this configuration routine.""" return ('ALL' in self._template) or (self._host.Platform in self._template) @@ -607,7 +610,7 @@ def __str__(self): class Edition(Enum): - def __new__(cls, *args, **kwargs): + def __new__(cls, *_, **__): value = len(cls.__members__) + 1 obj = object.__new__(cls) obj._value_ = value @@ -623,15 +626,15 @@ def Parse(cls, value): for item in cls.__members__.values(): if (item.Name == value): return item - else: - raise ValueError("Unknown enum value '{0}'.".format(value)) + raise ValueError("Unknown enum value '{0}'.".format(value)) def __repr__(self): return self.Name class ToolSelector(ILogable, AskMixIn): - """Base class for all Configuration classes.""" + """Base class for all Selector classes.""" + _toolName = "" def __init__(self, host: IHost): """Class initializer.""" @@ -639,6 +642,10 @@ def __init__(self, host: IHost): ILogable.__init__(self, host.Logger if isinstance(host, ILogable) else None) + @property + def ToolName(self): + return self._toolName + def _GetConfiguredEditions(self, editions): """Return all configured editions.""" _editions = [] @@ -666,12 +673,6 @@ def _AskSelection(self, editions, defaultEdition): edition = item break else: - - # try: - # selectedIndex = int(selectedIndex) - # edition = editions.Parse(selectedIndex) - # break - # except: self._host.LogError("Invalid choice.") continue # the outer while loop @@ -699,7 +700,7 @@ def __init__(self, host : IHost): from .PoC import Configuration as PoC_Configuration from .Git import Configuration as Git_Configuration from .Aldec import Configuration as Aldec_Configuration - from .Aldec.ActiveHDL import Configuration as ActiveHDL_Configuration, ActiveHDLEditions + from .Aldec.ActiveHDL import Configuration as ActiveHDL_Configuration from .Altera import Configuration as Altera_Configuration from .Altera.Quartus import Configuration as AlteraQuartus_Configuration from .Altera.ModelSim import Configuration as AlteraModelSim_Configuration @@ -778,7 +779,7 @@ def ConfigureAll(self): def ConfigureTool(self, toolChain): """Select tool chains for configuration.""" sectionName = ("INSTALL.{0}".format(toolChain)).lower() - configurators = [config for config in self._configurators if (config._section.lower().startswith(sectionName))] + configurators = [config for config in self._configurators if (config.SectionName.lower().startswith(sectionName))] if (len(configurators) == 0): self.LogError("{RED}No configuration named '{0}' found.{NOCOLOR}".format(toolChain, **Init.Foreground)) @@ -913,7 +914,7 @@ def ConfigureDefaultTools(self): def _ConfigureDefaultTools(self): self.LogNormal("{CYAN}Choosing default tools\n----------------------{NOCOLOR}".format(**Init.Foreground)) for selector in self._selectors: - self._host.LogNormal("{DARK_CYAN}Selecting {0} installation{NOCOLOR}".format(selector._toolName, **Init.Foreground)) + self._host.LogNormal("{DARK_CYAN}Selecting {0} installation{NOCOLOR}".format(selector.ToolName, **Init.Foreground)) try: selector.Select() except KeyboardInterrupt: From 3fda0f92d6e48fc6aae629b9a3427176a465927f Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 5 Dec 2016 19:32:11 +0100 Subject: [PATCH 92/97] Write configuration backup file before every "configure" run. --- py/.idea/misc.xml | 12 +- py/.idea/py.iml | 2 +- py/.idea/workspace.xml | 951 +++++++++++++++++++------------ py/Compiler/XCICompiler.py | 4 +- py/Compiler/XCOCompiler.py | 4 +- py/PoC.py | 57 +- py/Simulator/CocotbSimulator.py | 4 +- py/Simulator/GHDLSimulator.py | 1 - py/ToolChains/Altera/ModelSim.py | 2 +- 9 files changed, 650 insertions(+), 387 deletions(-) diff --git a/py/.idea/misc.xml b/py/.idea/misc.xml index 58450a2b..95a2e3ab 100644 --- a/py/.idea/misc.xml +++ b/py/.idea/misc.xml @@ -1,14 +1,4 @@ - - - - - - - - - - - + \ No newline at end of file diff --git a/py/.idea/py.iml b/py/.idea/py.iml index eaaad0b1..abd3de5f 100644 --- a/py/.idea/py.iml +++ b/py/.idea/py.iml @@ -6,7 +6,7 @@ - + diff --git a/py/.idea/workspace.xml b/py/.idea/workspace.xml index aeb0ff9d..0abab28d 100644 --- a/py/.idea/workspace.xml +++ b/py/.idea/workspace.xml @@ -2,7 +2,10 @@ - + + + + @@ -22,124 +25,84 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + - - - + + + + + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - - - - - - - - - - - - - - + + - - + + - - + + - - + + - - + + - - + + @@ -154,19 +117,22 @@ + + + if self._logger is not None: + , *args, **kwargs + + + if ((self._logger is not None) and condition): + , *args, condition=True, **kwargs + + @@ -239,16 +212,7 @@ - - - - - - - - - - + @@ -271,6 +235,60 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -281,6 +299,14 @@ + + + + @@ -295,6 +321,10 @@ + + @@ -310,7 +340,7 @@ - @@ -324,14 +354,14 @@