diff --git a/src/cpu.rs b/src/cpu.rs
index 4733edf..1a441b6 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -50,9 +50,9 @@ pub struct CpuCache<'a> {
 impl CpuCache<'_> {
     /// Create a new cache and parse the cpu databases into memory
     pub fn new() -> Self {
-        let intel_cpus = get_intel_cpus();
+        let mut intel_cpus = get_intel_cpus();
         debug!("Intel CPU list deserialized");
-        let mut intel_index: Vec<IndexEntry> = Vec::with_capacity(2048);
+        let mut intel_index: Vec<IndexEntry> = Vec::with_capacity(512);
         for (i, cpu) in intel_cpus.iter().enumerate() {
             match generate_index_entry(&cpu.name, i) {
                 Ok(idx) => {
@@ -64,7 +64,7 @@ impl CpuCache<'_> {
             }
         }
         debug!("Index generated for Intel CPUs");
-        let amd_cpus = get_amd_cpus();
+        let mut amd_cpus = get_amd_cpus();
         debug!("Amd CPU list deserialized");
         let mut amd_index: Vec<IndexEntry> = Vec::with_capacity(2048);
         for (i, cpu) in amd_cpus.iter().enumerate() {
@@ -77,6 +77,12 @@ impl CpuCache<'_> {
                 }
             }
         }
+        // because of the way memory allocations for vectors are done, over time, a lot of empty elements can get pre-allocated.
+        // remove those now
+        intel_cpus.shrink_to_fit();
+        amd_cpus.shrink_to_fit();
+        intel_index.shrink_to_fit();
+        amd_index.shrink_to_fit();
 
         Self {
             intel_cpus,
diff --git a/src/cpu/amd/mod.rs b/src/cpu/amd/mod.rs
index 76840a8..95209ac 100644
--- a/src/cpu/amd/mod.rs
+++ b/src/cpu/amd/mod.rs
@@ -38,7 +38,7 @@ fn process_json<'a>(json: AmdJson) -> Vec<Cpu<String>> {
         };
         let mut output_cpu = Cpu {
             name,
-            attributes: HashMap::with_capacity(75),
+            attributes: HashMap::new(),
         };
         for key in raw_data.keys() {
             // stripping out keys that are either garbage, or already handled (model)
diff --git a/src/cpu/intel/parser.rs b/src/cpu/intel/parser.rs
index 1cf1d01..a6bce2e 100644
--- a/src/cpu/intel/parser.rs
+++ b/src/cpu/intel/parser.rs
@@ -6,11 +6,11 @@ use std::error::Error;
 pub fn parse_csv(csv: &'_ str) -> Result<Vec<Cpu<&str>>, Box<dyn Error + '_>> {
     let lexer_output = lex_csv(csv)?;
     // the returned value
-    let mut output: Vec<Cpu<&str>> = Vec::with_capacity(lexer_output.cpus.len());
+    let mut output: Vec<Cpu<&str>> = Vec::new();
     for (i, cpu_name) in lexer_output.cpus.iter().enumerate() {
         let mut cpu: Cpu<&str> = Cpu {
             name: cpu_name,
-            attributes: HashMap::with_capacity(256),
+            attributes: HashMap::new(),
         };
         for record in lexer_output.records.clone() {
             // println!("{:#?}", record[0].to_string());
diff --git a/src/pcie/mod.rs b/src/pcie/mod.rs
index 7b28900..c1dab57 100644
--- a/src/pcie/mod.rs
+++ b/src/pcie/mod.rs
@@ -48,10 +48,12 @@ impl PcieCache {
     /// create a new pcie cache and parse the database into memory
     pub fn new() -> Self {
         let mut vendors: HashMap<u16, Vendor, BuildNoHashHasher<u16>> =
-            HashMap::with_capacity_and_hasher(2048, BuildNoHashHasher::default());
+            HashMap::with_capacity_and_hasher(512, BuildNoHashHasher::default());
         for vendor in parse_pcie_db().unwrap() {
             vendors.insert(vendor.id, vendor);
         }
+        // cut down on those unnecessary allocations again (1gb vps life)
+        vendors.shrink_to_fit();
         Self { vendors }
     }
 
diff --git a/src/usb/mod.rs b/src/usb/mod.rs
index df5eaed..d1f0ed0 100644
--- a/src/usb/mod.rs
+++ b/src/usb/mod.rs
@@ -39,6 +39,7 @@ impl UsbCache {
         for vendor in parse_usb_db() {
             vendors.insert(vendor.id, vendor);
         }
+        vendors.shrink_to_fit();
         Self { vendors }
     }